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soc: intel_adsp: rename CONFIG_SOC_INTEL_ACE* to CONFIG_SOC_ACE*

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Just following guidelines here.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
2026-01-16 11:24:39 -08:00
committed by Anas Nashif
parent 1dae40fa2e
commit 61e9f9ea04
19 changed files with 62 additions and 71 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
boards/intel/adsp/Kconfig.intel_adsp
View File

@@ -4,14 +4,14 @@
config BOARD_INTEL_ADSP
select SOC_CAVSV25 if BOARD_INTEL_ADSP_CAVS25
select SOC_CAVSV25 if BOARD_INTEL_ADSP_CAVS25_TGPH
select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM
select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM_SIM
select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL
select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM
select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL
select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL_SIM
select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVLS
select SOC_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM
select SOC_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM_SIM
select SOC_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL
select SOC_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM
select SOC_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL
select SOC_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM
select SOC_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL
select SOC_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM
select SOC_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL
select SOC_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL_SIM
select SOC_ACE40 if BOARD_INTEL_ADSP_ACE40_NVLS

2
drivers/dai/intel/alh/Kconfig.alh
View File

@@ -18,7 +18,7 @@ if DAI_INTEL_ALH
config DAI_ALH_HAS_OWNERSHIP
bool "Intel ALH driver has ownership only on ACE 1.5"
default y
depends on SOC_INTEL_ACE15_MTPM
depends on SOC_ACE15_MTPM
help
Select this to enable programming HW ownership

20
drivers/dai/intel/dmic/dmic.c
View File

@@ -162,8 +162,7 @@ static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic)
static inline uint32_t dai_dmic_base(const struct dai_intel_dmic *dmic)
{
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
defined(CONFIG_SOC_INTEL_ACE40)
#if defined(CONFIG_SOC_ACE20_LNL) || defined(CONFIG_SOC_ACE30) || defined(CONFIG_SOC_ACE40)
return dmic->hdamldmic_base;
#else
return dmic->shim_base;
@@ -176,8 +175,7 @@ static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_in
uint32_t val = CONFIG_DAI_DMIC_HW_IOCLK / period - 1;
uint32_t base = dai_dmic_base(dmic);
/* DMIC Change sync period */
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
defined(CONFIG_SOC_INTEL_ACE40)
#if defined(CONFIG_SOC_ACE20_LNL) || defined(CONFIG_SOC_ACE30) || defined(CONFIG_SOC_ACE40)
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val),
base + DMICSYNC_OFFSET);
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU,
@@ -264,8 +262,7 @@ static void dai_dmic_stop_fifo_packers(struct dai_intel_dmic *dmic,
static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
{
/* Disable DMIC clock gating */
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
defined(CONFIG_SOC_INTEL_ACE40)
#if defined(CONFIG_SOC_ACE20_LNL) || defined(CONFIG_SOC_ACE30) || defined(CONFIG_SOC_ACE40)
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD),
dmic->vshim_base + DMICLVSCTL_OFFSET);
#else
@@ -277,8 +274,7 @@ static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic)
{
/* Enable DMIC clock gating */
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
defined(CONFIG_SOC_INTEL_ACE40)
#if defined(CONFIG_SOC_ACE20_LNL) || defined(CONFIG_SOC_ACE30) || defined(CONFIG_SOC_ACE40)
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD),
dmic->vshim_base + DMICLVSCTL_OFFSET);
#else /* All other CAVS and ACE platforms */
@@ -292,8 +288,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi
const struct dai_config *cfg,
uint32_t index)
{
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
defined(CONFIG_SOC_INTEL_ACE40)
#if defined(CONFIG_SOC_ACE20_LNL) || defined(CONFIG_SOC_ACE30) || defined(CONFIG_SOC_ACE40)
uint16_t pcmsycm = cfg->link_config;
uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index;
@@ -302,7 +297,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi
ARG_UNUSED(dmic);
ARG_UNUSED(cfg);
ARG_UNUSED(index);
#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40 */
#endif /* CONFIG_SOC_ACE20_LNL || CONFIG_SOC_ACE30 || CONFIG_SOC_ACE40 */
}
static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
@@ -312,8 +307,7 @@ static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
sys_write32((sys_read32(base + DMICLCTL_OFFSET) | DMICLCTL_SPA),
base + DMICLCTL_OFFSET);
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
defined(CONFIG_SOC_INTEL_ACE40)
#if defined(CONFIG_SOC_ACE20_LNL) || defined(CONFIG_SOC_ACE30) || defined(CONFIG_SOC_ACE40)
while (!(sys_read32(base + DMICLCTL_OFFSET) & DMICLCTL_CPA)) {
k_busy_wait(100);
}

3
drivers/dai/intel/dmic/dmic.h
View File

@@ -173,8 +173,7 @@ struct dai_intel_dmic {
/* hardware parameters */
uint32_t reg_base;
uint32_t shim_base;
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
defined(CONFIG_SOC_INTEL_ACE40)
#if defined(CONFIG_SOC_ACE20_LNL) || defined(CONFIG_SOC_ACE30) || defined(CONFIG_SOC_ACE40)
uint32_t hdamldmic_base;
uint32_t vshim_base;
#endif

5
drivers/dai/intel/dmic/dmic_nhlt.c
View File

@@ -282,8 +282,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic, const int c
static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic, uint32_t source)
{
uint32_t val;
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
defined(CONFIG_SOC_INTEL_ACE40) /* ACE 2.0,3.0,4.0 */
#if defined(CONFIG_SOC_ACE20_LNL) || defined(CONFIG_SOC_ACE30) || defined(CONFIG_SOC_ACE40)
val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET);
val &= ~DMICLVSCTL_MLCS;
val |= FIELD_PREP(DMICLVSCTL_MLCS, source);
@@ -309,7 +308,7 @@ static int dai_dmic_set_clock(const struct dai_intel_dmic *dmic, const uint8_t c
return -ENOTSUP;
}
#if defined(CONFIG_SOC_INTEL_ACE15_MTPM)
#if defined(CONFIG_SOC_ACE15_MTPM)
if (clock_source && !(sys_read32(dmic->shim_base + DMICLCAP_OFFSET) & DMICLCAP_MLCS)) {
return -ENOTSUP;
}

2
drivers/dai/intel/ssp/dai-params-intel-ipc4.h
View File

@@ -270,7 +270,7 @@ struct dai_intel_ipc4_ssp_mclk_config_2 {
} __packed;
struct dai_intel_ipc4_ssp_driver_config {
#if defined(CONFIG_SOC_INTEL_ACE30) || defined(CONFIG_SOC_INTEL_ACE40)
#if defined(CONFIG_SOC_ACE30) || defined(CONFIG_SOC_ACE40)
struct dai_intel_ipc4_ssp_config_ver_3_0 i2s_config;
#else
struct dai_intel_ipc4_ssp_config i2s_config;

4
drivers/dai/intel/ssp/ssp.c
View File

@@ -859,7 +859,7 @@ static void dai_ssp_pm_runtime_dis_ssp_power(struct dai_intel_ssp *dp, uint32_t
static void dai_ssp_program_channel_map(struct dai_intel_ssp *dp,
const struct dai_config *cfg, uint32_t ssp_index, const void *spec_config)
{
#if defined(CONFIG_SOC_INTEL_ACE20_LNL)
#if defined(CONFIG_SOC_ACE20_LNL)
ARG_UNUSED(spec_config);
uint16_t pcmsycm = cfg->link_config;
/* Set upper slot number from configuration */
@@ -918,7 +918,7 @@ static void dai_ssp_program_channel_map(struct dai_intel_ssp *dp,
ARG_UNUSED(cfg);
ARG_UNUSED(ssp_index);
ARG_UNUSED(spec_config);
#endif /* CONFIG_SOC_INTEL_ACE20_LNL */
#endif /* CONFIG_SOC_ACE20_LNL */
}
/* empty SSP transmit FIFO */

14
drivers/dai/intel/ssp/ssp.h
View File

@@ -16,13 +16,13 @@
/* SSP IP version defined by CONFIG_SOC*/
#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_CAVS)
#define SSP_IP_VER SSP_IP_VER_1_0
#elif defined(CONFIG_SOC_INTEL_ACE15_MTPM)
#elif defined(CONFIG_SOC_ACE15_MTPM)
#define SSP_IP_VER SSP_IP_VER_1_5
#elif defined(CONFIG_SOC_INTEL_ACE20_LNL)
#elif defined(CONFIG_SOC_ACE20_LNL)
#define SSP_IP_VER SSP_IP_VER_2_0
#elif defined(CONFIG_SOC_INTEL_ACE30)
#elif defined(CONFIG_SOC_ACE30)
#define SSP_IP_VER SSP_IP_VER_3_0
#elif defined(CONFIG_SOC_INTEL_ACE40)
#elif defined(CONFIG_SOC_ACE40)
#define SSP_IP_VER SSP_IP_VER_4_0
#else
#error "Unknown SSP IP"
@@ -68,11 +68,11 @@
#define DAI_INTEL_SSP_CLOCK_AUDIO_CARDINAL 0x1
#define DAI_INTEL_SSP_CLOCK_PLL_FIXED 0x2
#if defined(CONFIG_SOC_INTEL_ACE15_MTPM) || defined(CONFIG_SOC_SERIES_INTEL_ADSP_CAVS)
#if defined(CONFIG_SOC_ACE15_MTPM) || defined(CONFIG_SOC_SERIES_INTEL_ADSP_CAVS)
#include "ssp_regs_v1.h"
#elif defined(CONFIG_SOC_INTEL_ACE20_LNL)
#elif defined(CONFIG_SOC_ACE20_LNL)
#include "ssp_regs_v2.h"
#elif defined(CONFIG_SOC_INTEL_ACE30) || defined(CONFIG_SOC_INTEL_ACE40)
#elif defined(CONFIG_SOC_ACE30) || defined(CONFIG_SOC_ACE40)
#include "ssp_regs_v3.h"
#else
#error "Missing ssp definitions"

2
drivers/dma/dma_intel_adsp_hda.c
View File

@@ -235,7 +235,7 @@ int intel_adsp_hda_dma_status(const struct device *dev, uint32_t channel,
stat->pending_length = used;
stat->free = unused;
#if CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40
#if CONFIG_SOC_ACE20_LNL || CONFIG_SOC_ACE30 || CONFIG_SOC_ACE40
/* Linear Link Position via HDA-DMA is only supported on ACE2 or newer */
if (cfg->direction == MEMORY_TO_PERIPHERAL || cfg->direction == PERIPHERAL_TO_MEMORY) {
uint32_t tmp;

2
drivers/power_domain/power_domain_intel_adsp.c
View File

@@ -32,7 +32,7 @@ static int pd_intel_adsp_set_power_enable(struct pg_bits *bits, bool power_enabl
return -EIO;
}
} else {
#if CONFIG_SOC_INTEL_ACE15_MTPM
#if CONFIG_SOC_ACE15_MTPM
extern uint32_t adsp_pending_buffer;
if (bits->SPA_bit == INTEL_ADSP_HST_DOMAIN_BIT) {

6
soc/intel/intel_adsp/ace/CMakeLists.txt
View File

@@ -15,7 +15,7 @@ zephyr_library_sources(
)
if(CONFIG_GDBSTUB)
if(CONFIG_SOC_INTEL_ACE40)
if(CONFIG_SOC_ACE40)
zephyr_library_sources(gdbstub_ace40.c)
else()
zephyr_library_sources(gdbstub.c)
@@ -32,8 +32,8 @@ zephyr_library_sources_ifdef(
)
if(CONFIG_XTENSA_MMU)
zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30 mmu_ace30.c)
zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE40 mmu_ace40.c)
zephyr_library_sources_ifdef(CONFIG_SOC_ACE30 mmu_ace30.c)
zephyr_library_sources_ifdef(CONFIG_SOC_ACE40 mmu_ace40.c)
endif()
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

2
soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm
View File

@@ -1,7 +1,7 @@
# Copyright (c) 2022-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_INTEL_ACE15_MTPM
if SOC_ACE15_MTPM
config MP_MAX_NUM_CPUS
default 3

2
soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl
View File

@@ -1,7 +1,7 @@
# Copyright (c) 2022-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_INTEL_ACE20_LNL
if SOC_ACE20_LNL
config MP_MAX_NUM_CPUS
default 5

2
soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30
View File

@@ -2,7 +2,7 @@
# SPDX-License-Identifier: Apache-2.0
if SOC_INTEL_ACE30
if SOC_ACE30
config MP_MAX_NUM_CPUS
default 5 if BOARD_INTEL_ADSP_ACE30_PTL || BOARD_INTEL_ADSP_ACE30_PTL_SIM

2
soc/intel/intel_adsp/ace/Kconfig.defconfig.ace40
View File

@@ -2,7 +2,7 @@
# SPDX-License-Identifier: Apache-2.0
if SOC_INTEL_ACE40
if SOC_ACE40
config MP_MAX_NUM_CPUS
default 4 if BOARD_INTEL_ADSP_ACE40_NVL

24
soc/intel/intel_adsp/ace/Kconfig.soc
View File

@@ -11,7 +11,7 @@ config SOC_SERIES_INTEL_ADSP_ACE
config SOC_SERIES_INTEL_ADSP_ACE15
bool
config SOC_INTEL_ACE15_MTPM
config SOC_ACE15_MTPM
bool
select SOC_SERIES_INTEL_ADSP_ACE
select SOC_SERIES_INTEL_ADSP_ACE15
@@ -21,7 +21,7 @@ config SOC_INTEL_ACE15_MTPM
config SOC_SERIES_INTEL_ADSP_ACE20
bool
config SOC_INTEL_ACE20_LNL
config SOC_ACE20_LNL
bool
select SOC_SERIES_INTEL_ADSP_ACE
select SOC_SERIES_INTEL_ADSP_ACE20
@@ -31,7 +31,7 @@ config SOC_INTEL_ACE20_LNL
config SOC_SERIES_INTEL_ADSP_ACE30
bool
config SOC_INTEL_ACE30
config SOC_ACE30
bool
select SOC_SERIES_INTEL_ADSP_ACE
select SOC_SERIES_INTEL_ADSP_ACE30
@@ -41,7 +41,7 @@ config SOC_INTEL_ACE30
config SOC_SERIES_INTEL_ADSP_ACE40
bool
config SOC_INTEL_ACE40
config SOC_ACE40
bool
select SOC_SERIES_INTEL_ADSP_ACE
select SOC_SERIES_INTEL_ADSP_ACE40
@@ -52,13 +52,13 @@ config SOC_SERIES
default "intel_adsp_ace" if SOC_SERIES_INTEL_ADSP_ACE
config SOC_TOOLCHAIN_NAME
default "intel_ace15_mtpm" if SOC_INTEL_ACE15_MTPM
default "intel_ace15_mtpm" if SOC_INTEL_ACE20_LNL
default "intel_ace30_ptl" if SOC_INTEL_ACE30
default "intel_ace40" if SOC_INTEL_ACE40
default "intel_ace15_mtpm" if SOC_ACE15_MTPM
default "intel_ace15_mtpm" if SOC_ACE20_LNL
default "intel_ace30_ptl" if SOC_ACE30
default "intel_ace40" if SOC_ACE40
config SOC
default "ace15_mtpm" if SOC_INTEL_ACE15_MTPM
default "ace20_lnl" if SOC_INTEL_ACE20_LNL
default "ace30" if SOC_INTEL_ACE30
default "ace40" if SOC_INTEL_ACE40
default "ace15_mtpm" if SOC_ACE15_MTPM
default "ace20_lnl" if SOC_ACE20_LNL
default "ace30" if SOC_ACE30
default "ace40" if SOC_ACE40

8
soc/intel/intel_adsp/ace/include/dmic_regs.h
View File

@@ -347,13 +347,13 @@
/* Digital Mic Shim Registers */
#ifdef CONFIG_SOC_INTEL_ACE20_LNL
#ifdef CONFIG_SOC_ACE20_LNL
#include <ace20_lnl/dmic_regs_ace2x.h>
#elif CONFIG_SOC_INTEL_ACE15_MTPM
#elif CONFIG_SOC_ACE15_MTPM
#include <ace15_mtpm/dmic_regs_ace1x.h>
#elif CONFIG_SOC_INTEL_ACE30
#elif CONFIG_SOC_ACE30
#include <ace30/dmic_regs_ace3x.h>
#elif CONFIG_SOC_INTEL_ACE40
#elif CONFIG_SOC_ACE40
#include <ace40/dmic_regs_ace4x.h>
#else
#error "Unknown SoC"

8
soc/intel/intel_adsp/ace/power.c
View File

@@ -24,12 +24,12 @@
#define LPSRAM_MAGIC_VALUE 0x13579BDF
#define LPSCTL_BATTR_MASK GENMASK(16, 12)
#if CONFIG_SOC_INTEL_ACE15_MTPM
#if CONFIG_SOC_ACE15_MTPM
/* Used to force any pending transaction by HW issuing an upstream read before
* power down host domain.
*/
uint8_t adsp_pending_buffer[CONFIG_DCACHE_LINE_SIZE] __aligned(CONFIG_DCACHE_LINE_SIZE);
#endif /* CONFIG_SOC_INTEL_ACE15_MTPM */
#endif /* CONFIG_SOC_ACE15_MTPM */
__imr void power_init(void)
{
@@ -41,13 +41,13 @@ __imr void power_init(void)
DSPCS.bootctl[0].bctl |= DSPBR_BCTL_WAITIPCG | DSPBR_BCTL_WAITIPPG;
#endif /* CONFIG_ADSP_IDLE_CLOCK_GATING */
#if CONFIG_SOC_INTEL_ACE15_MTPM
#if CONFIG_SOC_ACE15_MTPM
*((__sparse_force uint32_t *)sys_cache_cached_ptr_get(&adsp_pending_buffer)) =
INTEL_ADSP_ACE15_MAGIC_KEY;
sys_cache_data_flush_range((__sparse_force void *)
sys_cache_cached_ptr_get(&adsp_pending_buffer),
sizeof(adsp_pending_buffer));
#endif /* CONFIG_SOC_INTEL_ACE15_MTPM */
#endif /* CONFIG_SOC_ACE15_MTPM */
}
#ifdef CONFIG_PM

3
soc/intel/intel_adsp/common/gdbstub_backend_sram.c
View File

@@ -21,8 +21,7 @@
#define RING_SIZE 512
#if CONFIG_SOC_CAVSV25
#define SOF_GDB_WINDOW_OFFSET 1024
#elif CONFIG_SOC_INTEL_ACE15_MTPM || CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 || \
CONFIG_SOC_INTEL_ACE40
#elif CONFIG_SOC_ACE15_MTPM || CONFIG_SOC_ACE20_LNL || CONFIG_SOC_ACE30 || CONFIG_SOC_ACE40
/*
* MTL has 2 usable slots in debug window, which is more than 1 slot on TGL, but
* still slot 0 is always used for logging, slot 1 is assigned to shell