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drivers: clock_control: sf32lb_hxt48: add initial driver

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Add driver for HXT48.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas
2025-09-05 14:45:53 +02:00
committed by Benjamin Cabé
parent 25160c1328
commit 6558029f99
4 changed files with 106 additions and 0 deletions
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1
drivers/clock_control/CMakeLists.txt
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@@ -63,6 +63,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_AUXPLL clock_cont
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BOUFFALOLAB_BL60X clock_control_bl60x.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BOUFFALOLAB_BL61X clock_control_bl61x.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BOUFFALOLAB_BL70X clock_control_bl70x.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SF32LB_HXT48 clock_control_sf32lb_hxt48.c)
if(CONFIG_CLOCK_CONTROL_RENESAS_RZA2M_CPG)
zephyr_library_sources(clock_control_renesas_rza2m_cpg.c)

2
drivers/clock_control/Kconfig
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@@ -116,4 +116,6 @@ source "drivers/clock_control/Kconfig.it51xxx"
source "drivers/clock_control/Kconfig.mchp"
source "drivers/clock_control/Kconfig.sf32lb_hxt48"
endif # CLOCK_CONTROL

9
drivers/clock_control/Kconfig.sf32lb_hxt48 Normal file
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@@ -0,0 +1,9 @@
# Copyright (c) 2025 Core Devices LLC
# SPDX-License-Identifier: Apache-2.0
config CLOCK_CONTROL_SF32LB_HXT48
bool "SF32LB HXT48 clock control driver"
default y
depends on DT_HAS_SIFLI_SF32LB_HXT48_ENABLED
help
Enable driver for SiFli SF32LB HXT48.

94
drivers/clock_control/clock_control_sf32lb_hxt48.c Normal file
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@@ -0,0 +1,94 @@
/*
* Copyright (c) 2025 Core Devices LLC
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sifli_sf32lb_hxt48
#include <stdint.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <register.h>
#define HPSYS_AON_ACR offsetof(HPSYS_AON_TypeDef, ACR)
struct clock_control_sf32lb_hxt48_config {
uintptr_t aon;
uint32_t freq_hz;
};
static int clock_control_sf32lb_hxt48_on(const struct device *dev, clock_control_subsys_t sys)
{
const struct clock_control_sf32lb_hxt48_config *config = dev->config;
uint32_t val;
ARG_UNUSED(sys);
val = sys_read32(config->aon + HPSYS_AON_ACR);
val |= HPSYS_AON_ACR_HXT48_REQ;
sys_write32(val, config->aon + HPSYS_AON_ACR);
while (sys_test_bit(config->aon + HPSYS_AON_ACR, HPSYS_AON_ACR_HXT48_RDY_Pos) == 0U) {
}
return 0;
}
static int clock_control_sf32lb_hxt48_off(const struct device *dev, clock_control_subsys_t sys)
{
const struct clock_control_sf32lb_hxt48_config *config = dev->config;
uint32_t val;
ARG_UNUSED(sys);
val = sys_read32(config->aon + HPSYS_AON_ACR);
val &= ~HPSYS_AON_ACR_HXT48_REQ;
sys_write32(val, config->aon + HPSYS_AON_ACR);
return 0;
}
static enum clock_control_status clock_control_sf32lb_hxt48_get_status(const struct device *dev,
clock_control_subsys_t sys)
{
const struct clock_control_sf32lb_hxt48_config *config = dev->config;
ARG_UNUSED(sys);
if (sys_test_bit(config->aon + HPSYS_AON_ACR, HPSYS_AON_ACR_HXT48_RDY_Pos) != 0U) {
return CLOCK_CONTROL_STATUS_ON;
}
return CLOCK_CONTROL_STATUS_OFF;
}
static int clock_control_sf32lb_hxt48_get_rate(const struct device *dev, clock_control_subsys_t sys,
uint32_t *rate)
{
const struct clock_control_sf32lb_hxt48_config *config = dev->config;
ARG_UNUSED(sys);
*rate = config->freq_hz;
return 0;
}
static DEVICE_API(clock_control, clock_control_sf32lb_hxt48_api) = {
.on = clock_control_sf32lb_hxt48_on,
.off = clock_control_sf32lb_hxt48_off,
.get_status = clock_control_sf32lb_hxt48_get_status,
.get_rate = clock_control_sf32lb_hxt48_get_rate,
};
static const struct clock_control_sf32lb_hxt48_config config = {
.aon = DT_REG_ADDR(DT_INST_PHANDLE(0, sifli_aon)),
.freq_hz = DT_INST_PROP(0, clock_frequency),
};
DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, &config, PRE_KERNEL_1,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_sf32lb_hxt48_api);