soc: gd_gd32: move pinctrl_soc.h content back to soc folder
Because we can now group all architectures within the same family, so there's no need to place files outside of soc/family folder. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas
committed by
Carles Cufi
Carles Cufi
parent
2bd84a1bc5
commit
71600d7e95
@@ -1,194 +0,0 @@
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/*
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* Copyright (c) 2021 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* Gigadevice SoC specific helpers for pinctrl driver
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
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#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/types.h>
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#ifdef CONFIG_PINCTRL_GD32_AF
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#include <dt-bindings/pinctrl/gd32-af.h>
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#else
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#include <dt-bindings/pinctrl/gd32-afio.h>
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#endif /* CONFIG_PINCTRL_GD32_AF */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @cond INTERNAL_HIDDEN */
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/** @brief Type for GD32 pin.
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*
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* Bits (AF model):
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* - 0-12: GD32_PINMUX_AF bit field.
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* - 13-25: Reserved.
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* - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
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*
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* Bits (AFIO model):
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* - 0-19: GD32_PINMUX_AFIO bit field.
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* - 20-25: Reserved.
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* - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
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*/
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typedef uint32_t pinctrl_soc_pin_t;
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/**
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* @brief Utility macro to initialize each pin.
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*
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* @param node_id Node identifier.
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* @param prop Property name.
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* @param idx Property entry index.
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*/
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
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(DT_PROP_BY_IDX(node_id, prop, idx) | \
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((GD32_PUPD_PULLUP * DT_PROP(node_id, bias_pull_up)) \
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<< GD32_PUPD_POS) | \
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((GD32_PUPD_PULLDOWN * DT_PROP(node_id, bias_pull_down)) \
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<< GD32_PUPD_POS) | \
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((GD32_OTYPE_OD * DT_PROP(node_id, drive_open_drain)) \
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<< GD32_OTYPE_POS) | \
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(DT_ENUM_IDX(node_id, slew_rate) << GD32_OSPEED_POS)),
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/**
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* @brief Utility macro to initialize state pins contained in a given property.
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*
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* @param node_id Node identifier.
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* @param prop Property name describing state pins.
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*/
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
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DT_FOREACH_PROP_ELEM, pinmux, \
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Z_PINCTRL_STATE_PIN_INIT)}
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/** @endcond */
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/**
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* @name GD32 PUPD (values match the ones in the HAL for AF model).
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* @{
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*/
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/** No pull-up/down */
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#define GD32_PUPD_NONE 0U
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/** Pull-up */
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#define GD32_PUPD_PULLUP 1U
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/** Pull-down */
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#define GD32_PUPD_PULLDOWN 2U
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/** @} */
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/**
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* @name GD32 OTYPE (values match the ones in the HAL for AF model).
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* @{
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*/
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/** Push-pull */
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#define GD32_OTYPE_PP 0U
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/** Open-drain */
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#define GD32_OTYPE_OD 1U
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/** @} */
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/**
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* @name GD32 OSPEED (values match the ones in the HAL for AF model, mode minus
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* one for AFIO model).
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* @{
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*/
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#ifdef CONFIG_PINCTRL_GD32_AF
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/** Maximum 2MHz */
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#define GD32_OSPEED_2MHZ 0U
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#if defined(CONFIG_SOC_SERIES_GD32F3X0) || \
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defined(CONFIG_SOC_SERIES_GD32A50X) || \
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defined(CONFIG_SOC_SERIES_GD32L23X)
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/** Maximum 10MHz */
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#define GD32_OSPEED_10MHZ 1U
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/** Maximum 50MHz */
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#define GD32_OSPEED_50MHZ 3U
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#else
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/** Maximum 25MHz */
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#define GD32_OSPEED_25MHZ 1U
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/** Maximum 50MHz */
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#define GD32_OSPEED_50MHZ 2U
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/** Maximum speed */
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#define GD32_OSPEED_MAX 3U
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#endif
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#else /* CONFIG_PINCTRL_GD32_AF */
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/** Maximum 10MHz */
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#define GD32_OSPEED_10MHZ 0U
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/** Maximum 2MHz */
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#define GD32_OSPEED_2MHZ 1U
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/** Maximum 50MHz */
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#define GD32_OSPEED_50MHZ 2U
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/** Maximum speed */
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#define GD32_OSPEED_MAX 3U
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#endif /* CONFIG_PINCTRL_GD32_AF */
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/** @} */
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/**
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* @name GD32 pin configuration bit field mask and positions.
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* @anchor GD32_PINCFG
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*
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* Fields:
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*
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* - 31..29: Pull-up/down
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* - 28: Output type
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* - 27..26: Output speed
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*
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* @{
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*/
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/** PUPD field mask. */
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#define GD32_PUPD_MSK 0x3U
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/** PUPD field position. */
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#define GD32_PUPD_POS 29U
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/** OTYPE field mask. */
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#define GD32_OTYPE_MSK 0x1U
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/** OTYPE field position. */
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#define GD32_OTYPE_POS 28U
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/** OSPEED field mask. */
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#define GD32_OSPEED_MSK 0x3U
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/** OSPEED field position. */
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#define GD32_OSPEED_POS 26U
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/** @} */
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/**
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* Obtain PUPD field from pinctrl_soc_pin_t configuration.
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*
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* @param pincfg pinctrl_soc_pin_t bit field value.
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*/
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#define GD32_PUPD_GET(pincfg) \
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(((pincfg) >> GD32_PUPD_POS) & GD32_PUPD_MSK)
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/**
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* Obtain OTYPE field from pinctrl_soc_pin_t configuration.
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*
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* @param pincfg pinctrl_soc_pin_t bit field value.
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*/
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#define GD32_OTYPE_GET(pincfg) \
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(((pincfg) >> GD32_OTYPE_POS) & GD32_OTYPE_MSK)
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/**
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* Obtain OSPEED field from pinctrl_soc_pin_t configuration.
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*
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* @param pincfg pinctrl_soc_pin_t bit field value.
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*/
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#define GD32_OSPEED_GET(pincfg) \
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(((pincfg) >> GD32_OSPEED_POS) & GD32_OSPEED_MSK)
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_ */
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@@ -9,9 +9,186 @@
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* Gigadevice SoC specific helpers for pinctrl driver
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*/
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#ifndef ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_
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#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
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#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
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#include <zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/types.h>
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#endif /* ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_ */
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#ifdef CONFIG_PINCTRL_GD32_AF
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#include <dt-bindings/pinctrl/gd32-af.h>
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#else
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#include <dt-bindings/pinctrl/gd32-afio.h>
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#endif /* CONFIG_PINCTRL_GD32_AF */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @cond INTERNAL_HIDDEN */
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/** @brief Type for GD32 pin.
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*
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* Bits (AF model):
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* - 0-12: GD32_PINMUX_AF bit field.
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* - 13-25: Reserved.
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* - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
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*
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* Bits (AFIO model):
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* - 0-19: GD32_PINMUX_AFIO bit field.
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* - 20-25: Reserved.
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* - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
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*/
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typedef uint32_t pinctrl_soc_pin_t;
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/**
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* @brief Utility macro to initialize each pin.
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*
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* @param node_id Node identifier.
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* @param prop Property name.
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* @param idx Property entry index.
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*/
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
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(DT_PROP_BY_IDX(node_id, prop, idx) | \
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((GD32_PUPD_PULLUP * DT_PROP(node_id, bias_pull_up)) \
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<< GD32_PUPD_POS) | \
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((GD32_PUPD_PULLDOWN * DT_PROP(node_id, bias_pull_down)) \
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<< GD32_PUPD_POS) | \
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((GD32_OTYPE_OD * DT_PROP(node_id, drive_open_drain)) \
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<< GD32_OTYPE_POS) | \
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(DT_ENUM_IDX(node_id, slew_rate) << GD32_OSPEED_POS)),
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/**
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* @brief Utility macro to initialize state pins contained in a given property.
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*
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* @param node_id Node identifier.
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* @param prop Property name describing state pins.
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*/
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
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DT_FOREACH_PROP_ELEM, pinmux, \
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Z_PINCTRL_STATE_PIN_INIT)}
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/** @endcond */
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/**
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* @name GD32 PUPD (values match the ones in the HAL for AF model).
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* @{
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*/
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/** No pull-up/down */
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#define GD32_PUPD_NONE 0U
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/** Pull-up */
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#define GD32_PUPD_PULLUP 1U
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/** Pull-down */
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#define GD32_PUPD_PULLDOWN 2U
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/** @} */
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/**
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* @name GD32 OTYPE (values match the ones in the HAL for AF model).
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* @{
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*/
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/** Push-pull */
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#define GD32_OTYPE_PP 0U
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/** Open-drain */
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#define GD32_OTYPE_OD 1U
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/** @} */
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/**
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* @name GD32 OSPEED (values match the ones in the HAL for AF model, mode minus
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* one for AFIO model).
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* @{
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*/
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#ifdef CONFIG_PINCTRL_GD32_AF
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/** Maximum 2MHz */
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#define GD32_OSPEED_2MHZ 0U
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#if defined(CONFIG_SOC_SERIES_GD32F3X0) || \
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defined(CONFIG_SOC_SERIES_GD32A50X) || \
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defined(CONFIG_SOC_SERIES_GD32L23X)
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/** Maximum 10MHz */
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#define GD32_OSPEED_10MHZ 1U
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/** Maximum 50MHz */
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#define GD32_OSPEED_50MHZ 3U
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#else
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/** Maximum 25MHz */
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#define GD32_OSPEED_25MHZ 1U
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/** Maximum 50MHz */
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#define GD32_OSPEED_50MHZ 2U
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/** Maximum speed */
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#define GD32_OSPEED_MAX 3U
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#endif
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#else /* CONFIG_PINCTRL_GD32_AF */
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/** Maximum 10MHz */
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#define GD32_OSPEED_10MHZ 0U
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/** Maximum 2MHz */
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#define GD32_OSPEED_2MHZ 1U
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/** Maximum 50MHz */
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#define GD32_OSPEED_50MHZ 2U
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/** Maximum speed */
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#define GD32_OSPEED_MAX 3U
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#endif /* CONFIG_PINCTRL_GD32_AF */
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/** @} */
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/**
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* @name GD32 pin configuration bit field mask and positions.
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* @anchor GD32_PINCFG
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*
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* Fields:
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*
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* - 31..29: Pull-up/down
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* - 28: Output type
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* - 27..26: Output speed
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*
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* @{
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*/
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/** PUPD field mask. */
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#define GD32_PUPD_MSK 0x3U
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/** PUPD field position. */
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#define GD32_PUPD_POS 29U
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/** OTYPE field mask. */
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#define GD32_OTYPE_MSK 0x1U
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/** OTYPE field position. */
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#define GD32_OTYPE_POS 28U
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/** OSPEED field mask. */
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#define GD32_OSPEED_MSK 0x3U
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/** OSPEED field position. */
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#define GD32_OSPEED_POS 26U
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/** @} */
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/**
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* Obtain PUPD field from pinctrl_soc_pin_t configuration.
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*
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* @param pincfg pinctrl_soc_pin_t bit field value.
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*/
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#define GD32_PUPD_GET(pincfg) \
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(((pincfg) >> GD32_PUPD_POS) & GD32_PUPD_MSK)
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/**
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* Obtain OTYPE field from pinctrl_soc_pin_t configuration.
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*
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* @param pincfg pinctrl_soc_pin_t bit field value.
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*/
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#define GD32_OTYPE_GET(pincfg) \
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(((pincfg) >> GD32_OTYPE_POS) & GD32_OTYPE_MSK)
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/**
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* Obtain OSPEED field from pinctrl_soc_pin_t configuration.
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*
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* @param pincfg pinctrl_soc_pin_t bit field value.
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*/
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#define GD32_OSPEED_GET(pincfg) \
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(((pincfg) >> GD32_OSPEED_POS) & GD32_OSPEED_MSK)
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_ */
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@@ -1,17 +0,0 @@
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/*
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* Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* Gigadevice SoC specific helpers for pinctrl driver
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*/
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#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_
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#include <zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h>
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#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_ */
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