soc: gd_gd32: port gd32vf103 series to HWMv2

Port the only RISC-V SoC from GigaDevice to HWMv2.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>

soc/gd_gd32/gd32vf103/CMakeLists.txt

@@ -4,6 +4,8 @@
 zephyr_sources(entry.S)
 zephyr_sources(soc.c)
 
+zephyr_include_directories(.)
+
 zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/gd_gd32/gd32vf103/Kconfig

@@ -4,17 +4,17 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_GD32VF103
-	bool "GigaDevice GD32VF103 series SoC implementation"
 	select RISCV
 	select RISCV_PRIVILEGED
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_HAS_CLIC
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
-	select BUILD_OUTPUT_HEX
-	select XIP
 	select GD32_HAS_AFIO_PINMUX
 	select GD32_HAS_IRC_40K
-	select HAS_GD32_HAL
-	select RISCV_HAS_CLIC
-	select SOC_FAMILY_GD32
-	help
-	  Enable support for GigaDevice GD32VF1 series SoC
+	select XIP

soc/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103

@@ -3,9 +3,6 @@
 
 if SOC_GD32VF103
 
-config SOC
-	default "gd32vf103"
-
 config KERNEL_ENTRY
 	default "__nuclei_start"
 
@@ -30,15 +27,6 @@ config NUM_IRQS
 config 2ND_LEVEL_INTERRUPTS
 	default y
 
-config PINCTRL
-	default y
-
-config RESET
-	default y
-
-config CLOCK_CONTROL
-	default y
-
 config ARCH_IRQ_VECTOR_TABLE_ALIGN
 	default 512 if NUCLEI_ECLIC
 

soc/gd_gd32/gd32vf103/Kconfig.defconfig.series

@@ -3,9 +3,6 @@
 
 if SOC_SERIES_GD32VF103
 
-source "soc/soc_legacy/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103*"
-
-config SOC_SERIES
-	default "gd32vf103"
+rsource "Kconfig.defconfig.gd32*"
 
 endif # SOC_SERIES_GD32VF103

soc/gd_gd32/gd32vf103/Kconfig.soc

@@ -0,0 +1,20 @@
+# GD32VF103 SOC configuration options
+
+# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32VF103
+	bool
+	select SOC_FAMILY_GD_GD32
+	help
+	  Enable support for GigaDevice GD32VF103 MCU series
+
+config SOC_SERIES
+	default "gd32vf103" if SOC_SERIES_GD32VF103
+
+config SOC_GD32VF103
+	bool
+	select SOC_SERIES_GD32VF103
+
+config SOC
+	default "gd32vf103" if SOC_GD32VF103

soc/gd_gd32/soc.yml

@@ -25,3 +25,6 @@ family:
   - name: gd32l23x
     socs:
     - name: gd32l233
+  - name: gd32vf103
+    socs:
+    - name: gd32vf103

soc/soc_legacy/riscv/gd_gd32/CMakeLists.txt

@@ -1,4 +0,0 @@
-# Copyright (c) 2024 Nordic Semiconductor
-# SPDX-License-Identifier: Apache-2.0
-
-add_subdirectory(${SOC_SERIES})

soc/soc_legacy/riscv/gd_gd32/Kconfig

@@ -1,15 +0,0 @@
-# Copyright (c) 2024 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_FAMILY_GD32
-	bool
-
-if SOC_FAMILY_GD32
-
-config SOC_FAMILY
-	string
-	default "gd_gd32"
-
-source "soc/soc_legacy/riscv/gd_gd32/*/Kconfig.soc"
-
-endif # SOC_FAMILY_GIGADEVICE_GD32

soc/soc_legacy/riscv/gd_gd32/Kconfig.defconfig

@@ -1,4 +0,0 @@
-# Copyright (c) 2024 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/riscv/gd_gd32/*/Kconfig.defconfig.series"

soc/soc_legacy/riscv/gd_gd32/Kconfig.soc

@@ -1,4 +0,0 @@
-# Copyright (c) 2024 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/riscv/gd_gd32/*/Kconfig.series"

soc/soc_legacy/riscv/gd_gd32/gd32vf103/Kconfig.soc

@@ -1,19 +0,0 @@
-# GD32VF103 SOC configuration options
-
-# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "GigaDevice GD32VF103 SOC implementation"
-	depends on SOC_SERIES_GD32VF103
-
-config SOC_GD32VF103
-	bool "GD32VF103"
-	select RISCV_ISA_RV32I
-	select RISCV_ISA_EXT_M
-	select RISCV_ISA_EXT_A
-	select RISCV_ISA_EXT_C
-	select RISCV_ISA_EXT_ZICSR
-	select RISCV_ISA_EXT_ZIFENCEI
-
-endchoice