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soc: sifli: sf32lb52x: Add pinctrl definition

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- Add helper macros related to sifli,analog
- Standardize driver level descriptions to `DS` instead of `DS0`

Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
This commit is contained in:
Haoran Jiang
2025-12-01 16:19:38 +08:00
committed by Benjamin Cabé
parent f71beede1a
commit 7ebf5091c2
1 changed files with 23 additions and 13 deletions
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36
soc/sifli/sf32/sf32lb52x/pinctrl_soc.h
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@@ -1,5 +1,6 @@
/*
* Copyright (c) 2025 Core Devices LLC
* Copyright (c) 2025 SiFli Technologies(Nanjing) Co., Ltd
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,6 +10,7 @@
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/pinctrl/sf32lb-common-pinctrl.h>
#include <zephyr/sys/util.h>
#ifdef __cplusplus
@@ -26,28 +28,36 @@ extern "C" {
* - 6: Input enable (0=disable, 1=enable)
* - 7: Input select (0=normal, 1=schmitt trigger)
* - 8: Slew rate (0=slow, 1=fast)
* - 9-10: Drive strength (0=2mA, 1=4mA, 2=8mA, 3=12mA)
* - 11: Reserved
* - 11-31: Location, port, pad, PINR register field and offset.
* - 9-10: Drive strength {DS0, DS1} (0-3), DS0 is high bit, default=2 (4mA)
* - 11-13: Drive strength enum index (0-4 for 2/4/8/12/20 mA)
* - 14-31: Location, port, pad, PINR register field and offset.
*/
typedef uint32_t pinctrl_soc_pin_t;
#define SF32LB_PE_MSK BIT(4U)
#define SF32LB_PS_MSK BIT(5U)
#define SF32LB_IE_MSK BIT(6U)
#define SF32LB_IS_MSK BIT(7U)
#define SF32LB_SR_MSK BIT(8U)
#define SF32LB_DS0_MSK GENMASK(10U, 9U)
#define SF32LB_PE_MSK BIT(4U)
#define SF32LB_PS_MSK BIT(5U)
#define SF32LB_IE_MSK BIT(6U)
#define SF32LB_DS_MSK GENMASK(10U, 9U)
/* Drive strength enum index position and mask (stored in bits 11-13) */
#define SF32LB_DS_IDX_POS 11U
#define SF32LB_DS_IDX_MSK GENMASK(13U, 11U)
/*
* Pin configuration mask for bits that should be modified.
* SR (slew-rate) and IS (input-schmitt) are preserved from hardware defaults.
* DS bits (9-10) are set by driver after mA-to-register conversion.
*/
#define SF32LB_PINMUX_CFG_MSK \
(SF32LB_FSEL_MSK | SF32LB_PE_MSK | SF32LB_PS_MSK | SF32LB_IE_MSK | SF32LB_DS_MSK)
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
(DT_PROP_BY_IDX(node_id, prop, idx) | \
FIELD_PREP(SF32LB_PE_MSK, \
DT_PROP(node_id, bias_pull_up) | DT_PROP(node_id, bias_pull_down)) | \
(DT_PROP(node_id, bias_pull_up) | DT_PROP(node_id, bias_pull_down))) | \
FIELD_PREP(SF32LB_PS_MSK, DT_PROP(node_id, bias_pull_up)) | \
FIELD_PREP(SF32LB_IE_MSK, DT_PROP(node_id, input_enable)) | \
FIELD_PREP(SF32LB_IS_MSK, DT_PROP(node_id, input_schmitt_enable)) | \
FIELD_PREP(SF32LB_SR_MSK, DT_PROP(node_id, slew_rate)) | \
FIELD_PREP(SF32LB_DS0_MSK, DT_ENUM_IDX(node_id, drive_strength))),
FIELD_PREP(SF32LB_DS_IDX_MSK, DT_ENUM_IDX(node_id, drive_strength))),
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \