soc: telink: tlsr951x: use RISC-V custom CSR common code
TLSR951x also supports Andes extended CSR. Reworks the following CSR handling to use the RISC-V custom CSR common code: 1. Use common macros for HWDSP CSR context save/restore. 2. Use common macros for PFT CSR context save/restore. 3. Use common low-level CSR initialization via __reset hook. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng
committed by
Chris Friedt
Chris Friedt
parent
679ce42f15
commit
7ee9fd978c
@@ -8,6 +8,3 @@ CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_SERIAL=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# HW DSP options
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CONFIG_TELINK_B91_HWDSP=n
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@@ -23,7 +23,7 @@
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cpu0: cpu@0 {
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reg = <0>;
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clock-frequency = <24000000>;
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compatible = "telink,b91", "riscv";
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compatible = "telink,b91", "andestech,andescore-v5", "riscv";
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riscv,isa = "rv32imac_zicsr_zifencei";
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hlic: interrupt-controller {
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@@ -13,7 +13,7 @@ zephyr_include_directories(.)
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zephyr_ld_options(-fuse-ld=bfd)
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# Set compile options
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zephyr_compile_options_ifdef(CONFIG_TELINK_B91_HWDSP -mext-dsp)
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zephyr_compile_options_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP -mext-dsp)
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zephyr_compile_options_ifndef(CONFIG_RISCV_GP -mno-relax)
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zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld)
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@@ -15,19 +15,23 @@ config SOC_SERIES_TLSR951X
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select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
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select HAS_TELINK_DRIVERS
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select CPU_HAS_FPU
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select INCLUDE_RESET_VECTOR
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select CPU_HAS_DCACHE
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select CPU_HAS_ICACHE
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select CPU_HAS_ANDES_HWDSP
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select CPU_HAS_ANDES_PFT
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select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_HWDSP
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select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_PFT
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imply XIP
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select SOC_EARLY_INIT_HOOK
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if SOC_SERIES_TLSR951X
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config TELINK_B91_HWDSP
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bool "Support Hardware DSP"
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select RISCV_SOC_CONTEXT_SAVE
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bool
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select DEPRECATED
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config TELINK_B91_PFT_ARCH
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bool "Support performance throttling"
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default y
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select RISCV_SOC_CONTEXT_SAVE
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bool
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select DEPRECATED
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endif # SOC_SERIES_TLSR951X
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@@ -30,4 +30,8 @@ config 2ND_LVL_INTR_00_OFFSET
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config HAS_FLASH_LOAD_OFFSET
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default y if BOOTLOADER_MCUBOOT
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choice CACHE_TYPE
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default EXTERNAL_CACHE
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endchoice
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endif # SOC_SERIES_TLSR951X
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@@ -7,43 +7,16 @@
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#ifndef SOC_RISCV_TELINK_B91_SOC_CONTEXT_H
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#define SOC_RISCV_TELINK_B91_SOC_CONTEXT_H
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#include <csr_context.h>
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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/* Telink B91 specific registers. */
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#if defined(CONFIG_TELINK_B91_PFT_ARCH) && defined(__riscv_dsp)
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#define SOC_ESF_MEMBERS \
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uint32_t mxstatus; \
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uint32_t ucode \
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#define SOC_ESF_MEMBERS \
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CUSTOM_CSR_ESF_MEMBERS
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#define SOC_ESF_INIT \
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0xdeadbaad, \
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0xdeadbaad
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#define SOC_ESF_THREAD_INIT(soc_context) \
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(soc_context)->mxstatus = 0; \
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(soc_context)->ucode = 0
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#elif defined(CONFIG_TELINK_B91_PFT_ARCH)
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#define SOC_ESF_MEMBERS \
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uint32_t mxstatus
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#define SOC_ESF_INIT \
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0xdeadbaad
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#define SOC_ESF_THREAD_INIT(soc_context) \
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(soc_context)->mxstatus = 0
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#elif defined(__riscv_dsp)
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#define SOC_ESF_MEMBERS \
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uint32_t ucode
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#define SOC_ESF_INIT \
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0xdeadbaad
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#define SOC_ESF_THREAD_INIT(soc_context) \
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(soc_context)->ucode = 0
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#endif
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#define SOC_ESF_INIT \
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CUSTOM_CSR_ESF_INIT
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#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
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@@ -6,51 +6,24 @@
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#include <zephyr/offsets.h>
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#include <zephyr/toolchain.h>
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#include <csr_irq.inc>
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#include <soc.h>
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#define NDS_MXSTATUS 0x7C4
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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/* Exports */
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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GTEXT(__soc_save_context)
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GTEXT(__soc_restore_context)
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#endif
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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SECTION_FUNC(exception.other, __soc_save_context)
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#ifdef CONFIG_TELINK_B91_PFT_ARCH
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csrr t0, NDS_MXSTATUS
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#endif
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#ifdef __riscv_dsp
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csrr t1, ucode
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#endif
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__custom_csr_save_context a0, t0
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#ifdef CONFIG_TELINK_B91_PFT_ARCH
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sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
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#endif
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#ifdef __riscv_dsp
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sw t1, __soc_esf_t_ucode_OFFSET(a0)
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#endif
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ret
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SECTION_FUNC(exception.other, __soc_restore_context)
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#ifdef CONFIG_TELINK_B91_PFT_ARCH
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lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
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#endif
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#ifdef __riscv_dsp
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lw t1, __soc_esf_t_ucode_OFFSET(a0)
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#endif
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__custom_csr_restore_context a0, t0
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#ifdef CONFIG_TELINK_B91_PFT_ARCH
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csrw NDS_MXSTATUS, t0
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#endif
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#ifdef __riscv_dsp
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csrw ucode, t1
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#endif
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ret
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#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
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@@ -7,23 +7,13 @@
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#ifndef SOC_RISCV_TELINK_B91_SOC_OFFSETS_H
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#define SOC_RISCV_TELINK_B91_SOC_OFFSETS_H
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#include <csr_offsets.h>
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#ifdef CONFIG_RISCV_SOC_OFFSETS
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/* Telink B91 specific registers. */
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#if defined(CONFIG_TELINK_B91_PFT_ARCH) && defined(__riscv_dsp)
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_OFFSET_SYM(soc_esf_t, mxstatus); \
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GEN_OFFSET_SYM(soc_esf_t, ucode)
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#elif defined(CONFIG_TELINK_B91_PFT_ARCH)
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_OFFSET_SYM(soc_esf_t, mxstatus)
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#elif defined(__riscv_dsp)
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_OFFSET_SYM(soc_esf_t, ucode)
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#endif
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_CUSTOM_CSR_OFFSET_SYMS()
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#endif /* CONFIG_RISCV_SOC_OFFSETS */
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@@ -4,9 +4,6 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define NDS_MCACHE_CTL 0x7CA
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#define NDS_MMISC_CTL 0x7D0
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#include <zephyr/toolchain.h>
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.option push
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@@ -31,17 +28,6 @@ entry:
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start:
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/* Enable I/D-Cache */
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csrr t0, NDS_MCACHE_CTL
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ori t0, t0, 1 #/I-Cache
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ori t0, t0, 2 #/D-Cache
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csrw NDS_MCACHE_CTL, t0
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fence.i
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/* Enable misaligned access and non-blocking load */
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li t0, (1 << 8) | (1 << 6)
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csrs NDS_MMISC_CTL, t0
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_ZERO_AES:
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lui t0, 0
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la t2, _AES_DATA_VMA_START
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