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drivers: clock_control: Add clock sources to common enabled_clock check

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Add clock sources PLL2CLK, PLL3CLK and EXT_HSE.
Needed to check that these clocks are enabled in MCO code.

Signed-off-by: Joakim Andersson <joerchan@gmail.com>
This commit is contained in:
Joakim Andersson
2024-09-03 16:09:04 +02:00
committed by Carles Cufí
parent 3c3487ae07
commit 807ccf5b03
2 changed files with 30 additions and 0 deletions
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21
drivers/clock_control/clock_stm32_ll_common.c
View File

@@ -133,6 +133,13 @@ int enabled_clock(uint32_t src_clk)
}
break;
#endif /* STM32_SRC_HSE */
#if defined(STM32_SRC_EXT_HSE)
case STM32_SRC_EXT_HSE:
/* EXT_HSE is the raw OSC_IN signal, so it is always
* available, regardless of the clocks configuration.
*/
break;
#endif /* STM32_SRC_HSE */
#if defined(STM32_SRC_HSI)
case STM32_SRC_HSI:
if (!IS_ENABLED(STM32_HSI_ENABLED)) {
@@ -210,6 +217,20 @@ int enabled_clock(uint32_t src_clk)
}
break;
#endif /* STM32_SRC_PLLI2S_R */
#if defined(STM32_SRC_PLL2CLK)
case STM32_SRC_PLL2CLK:
if (!IS_ENABLED(STM32_PLL2_ENABLED)) {
r = -ENOTSUP;
}
break;
#endif
#if defined(STM32_SRC_PLL3CLK)
case STM32_SRC_PLL3CLK:
if (!IS_ENABLED(STM32_PLL3_ENABLED)) {
r = -ENOTSUP;
}
break;
#endif
default:
return -ENOTSUP;
}

9
drivers/clock_control/clock_stm32f1.c
View File

@@ -23,6 +23,15 @@
#if defined(STM32_PLL_ENABLED)
uint32_t get_pllout_frequency(void)
{
/* Stub implementation for compatibility with clock_stm32_ll_common.
* The PLL domain clock is only used for MCO configuration, but the
* MCO driver never queries the PLL output clock frequency.
*/
return 0;
}
/*
* Select PLL source for STM32F1 Connectivity line devices (STM32F105xx and
* STM32F107xx).