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driver: Reuse andes_cache driver for compatible MCUs

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Fixed a wrong function declare of 'nds_l2_cache_init'.
Replace `SOC_FAMILY_ANDES_V5` with `DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED`
condition to enable it to be used by compatible MCUs

Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
This commit is contained in:
Jacky Lee
2025-10-02 11:30:11 +08:00
committed by Benjamin Cabé
parent 9cde077512
commit 83afba85d1
2 changed files with 3 additions and 3 deletions
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4
drivers/cache/Kconfig.andes vendored
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@@ -5,10 +5,10 @@
config CACHE_ANDES
bool "ANDES external cache driver"
default y
depends on SOC_FAMILY_ANDES_V5
depends on DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED
select CACHE_HAS_DRIVER
help
This option enables the CACHE driver for ANDES V5 series SOC.
This option enables the CACHE driver for SoC based on Andes V5 core.
if CACHE_ANDES

2
drivers/cache/cache_andes.c vendored
View File

@@ -74,7 +74,7 @@ static ALWAYS_INLINE void nds_l2_cache_disable(void) { }
static ALWAYS_INLINE int nds_l2_cache_range(void *addr, size_t size, int op) { return 0; }
static ALWAYS_INLINE int nds_l2_cache_all(int op) { return 0; }
static ALWAYS_INLINE int nds_l2_cache_is_inclusive(void) { return 0; }
static ALWAYS_INLINE int nds_l2_cache_init(void) { return 0; }
static ALWAYS_INLINE int nds_l2_cache_init(uint8_t line_size) { return 0; }
#endif /* DT_NODE_HAS_COMPAT_STATUS(DT_INST(0, andestech_l2c), andestech_l2c, okay) */
static ALWAYS_INLINE int nds_cctl_range_operations(void *addr, size_t size, int line_size, int cmd)