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soc: wch: Add CH32V307 Support

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Fixes PLL Issues with PR#95814.
Based on the work of Thomas Boje <info@andocs.biz>

Signed-off-by: James Bennion-Pedley <james@bojit.org>
This commit is contained in:
James Bennion-Pedley
2025-09-26 10:20:04 +01:00
committed by Chris Friedt
parent 344241718a
commit 99b0c25d01
10 changed files with 297 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/clock_control/clock_control_wch_rcc.c
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@@ -35,7 +35,14 @@
#define WCH_RCC_SRC_IS_HSI 1
#endif
#if defined(CONFIG_SOC_CH32V307)
/* TODO: Entry 13 is 6.5x (fractional multiple currently unsupported without
* changes to RCC config datatype)
*/
static const uint8_t pllmul_lut[] = {18, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0, 15, 16};
#else
static const uint8_t pllmul_lut[] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18};
#endif
struct clock_control_wch_rcc_config {
RCC_TypeDef *regs;

1
dts/bindings/vendor-prefixes.txt
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@@ -601,6 +601,7 @@ sandisk Sandisk Corporation
satoz Satoz International Co., Ltd
sbs Smart Battery System
sc Space Cubics Inc.
scdz Shenzhen Qiushi IoT Technology Co., Ltd.
schindler Schindler
sciosense Sciosense B.V.
seagate Seagate Technology PLC

226
dts/riscv/wch/ch32v307/ch32v307.dtsi Normal file
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@@ -0,0 +1,226 @@
/*
* Copyright (c) 2025 Thomas Boje
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <freq.h>
#include <mem.h>
#include <wch/qingke-v4f.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h>
/ {
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "wch,ch32v00x-hse-clock";
clock-frequency = <DT_FREQ_M(8)>;
status = "disabled";
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "wch,ch32v00x-hsi-clock";
clock-frequency = <DT_FREQ_M(8)>;
status = "disabled";
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(32)>;
status = "disabled";
};
pll: pll {
#clock-cells = <0>;
compatible = "wch,ch32v20x_30x-pll-clock";
mul = <18>;
status = "disabled";
};
};
soc {
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(32)>;
};
flash: flash-controller@40022000 {
compatible = "wch,ch32v20x_30x-flash-controller";
reg = <0x40022000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "soc-nv-flash";
reg = <0x08000000 DT_SIZE_K(480)>;
};
};
pwr: pwr@40007000 {
compatible = "wch,pwr";
reg = <0x40007000 16>;
};
pinctrl: pin-controller@40010000 {
compatible = "wch,20x_30x-afio";
reg = <0x40010000 16>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&rcc CH32V20X_V30X_CLOCK_AFIO>;
gpioa: gpio@40010800 {
compatible = "wch,gpio";
reg = <0x40010800 0x20>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>;
};
gpiob: gpio@40010C00 {
compatible = "wch,gpio";
reg = <0x40010C00 0x20>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>;
};
gpioc: gpio@40011000 {
compatible = "wch,gpio";
reg = <0x40011000 0x20>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>;
};
gpiod: gpio@40011400 {
compatible = "wch,gpio";
reg = <0x40011400 0x20>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>;
};
gpioe: gpio@40011800 {
compatible = "wch,gpio";
reg = <0x40011800 0x20>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPE>;
};
};
usart1: uart@40013800 {
compatible = "wch,usart";
reg = <0x40013800 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>;
interrupt-parent = <&pfic>;
interrupts = <53>;
status = "disabled";
};
usart2: uart@40004400 {
compatible = "wch,usart";
reg = <0x40004400 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>;
interrupt-parent = <&pfic>;
interrupts = <54>;
status = "disabled";
};
usart3: uart@40004800 {
compatible = "wch,usart";
reg = <0x40004800 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>;
interrupt-parent = <&pfic>;
interrupts = <55>;
status = "disabled";
};
usart4: uart@40004c00 {
compatible = "wch,usart";
reg = <0x40004C00 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>;
interrupt-parent = <&pfic>;
interrupts = <68>;
status = "disabled";
};
usart5: uart@40005000 {
compatible = "wch,usart";
reg = <0x40005000 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART5>;
interrupt-parent = <&pfic>;
interrupts = <69>;
status = "disabled";
};
usart6: uart@40001800 {
compatible = "wch,usart";
reg = <0x40001800 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART6>;
interrupt-parent = <&pfic>;
interrupts = <87>;
status = "disabled";
};
usart7: uart@40001c00 {
compatible = "wch,usart";
reg = <0x40001c00 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART7>;
interrupt-parent = <&pfic>;
interrupts = <88>;
status = "disabled";
};
usart8: uart@40002000 {
compatible = "wch,usart";
reg = <0x40002000 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART8>;
interrupt-parent = <&pfic>;
interrupts = <89>;
status = "disabled";
};
rcc: rcc@40021000 {
compatible = "wch,rcc";
reg = <0x40021000 16>;
#clock-cells = <1>;
status = "okay";
};
dma1: dma@40020000 {
compatible = "wch,wch-dma";
reg = <0x40020000 0x90>;
clocks = <&rcc CH32V20X_V30X_CLOCK_DMA1>;
#dma-cells = <1>;
interrupt-parent = <&pfic>;
interrupts = <27>, <28>, <29>, <30>, <31>, <32>, <33>;
dma-channels = <7>;
};
dma2: dma@40020400 {
compatible = "wch,wch-dma";
reg = <0x40020400 0x90>;
clocks = <&rcc CH32V20X_V30X_CLOCK_DMA2>;
#dma-cells = <1>;
interrupt-parent = <&pfic>;
interrupts = <72>, <73>, <74>, <75>, <76>, <98>, <99>, <100>,
<101>, <102>, <103>;
dma-channels = <11>;
};
};
};
&cpu0 {
clock-frequency = <DT_FREQ_M(144)>;
};

15
dts/riscv/wch/ch32v307/ch32v307rc.dtsi Normal file
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@@ -0,0 +1,15 @@
/*
* Copyright (c) 2025 Thomas Boje
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <wch/ch32v307/ch32v307.dtsi>
&gpiod {
gpio-reserved-ranges = <3 13>;
};
&gpioe {
gpio-reserved-ranges = <0 16>;
};

7
dts/riscv/wch/ch32v307/ch32v307vc.dtsi Normal file
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@@ -0,0 +1,7 @@
/*
* Copyright (c) 2025 Thomas Boje
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <wch/ch32v307/ch32v307.dtsi>

15
dts/riscv/wch/ch32v307/ch32v307wc.dtsi Normal file
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@@ -0,0 +1,15 @@
/*
* Copyright (c) 2025 Thomas Boje
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <wch/ch32v307/ch32v307.dtsi>
&gpiod {
gpio-reserved-ranges = <3 5>, <10 6>;
};
&gpioe {
gpio-reserved-ranges = <1 15>;
};

3
modules/hal_wch/hal_ch32fun.h
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@@ -39,6 +39,9 @@
#define CH32V30x 1
#if defined(CONFIG_SOC_CH32V303)
#define CH32V30x_D8 1
#elif defined(CONFIG_SOC_CH32V307)
#define CH32V30x_D8C 1
#endif
#include <ch32fun.h>
#endif /* defined(CONFIG_SOC_SERIES_QINGKE_V4F) */

12
soc/wch/ch32v/qingke_v4f/Kconfig.defconfig.ch32v307 Normal file
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@@ -0,0 +1,12 @@
# Copyright (c) 2025 Thomas Boje
# SPDX-License-Identifier: Apache-2.0
if SOC_CH32V307
config VECTOR_TABLE_SIZE
default 103
config NUM_IRQS
default 128
endif # SOC_CH32V307

9
soc/wch/ch32v/qingke_v4f/Kconfig.soc.ch32v307 Normal file
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@@ -0,0 +1,9 @@
# Copyright (c) 2025 Thomas Boje
# SPDX-License-Identifier: Apache-2.0
config SOC_CH32V307
bool
select SOC_SERIES_QINGKE_V4F
config SOC
default "ch32v307" if SOC_CH32V307

2
soc/wch/ch32v/soc.yml
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@@ -1,4 +1,5 @@
# Copyright (c) 2024 Michael Hope
# Copyright (c) 2025 Thomas Boje
# SPDX-License-Identifier: Apache-2.0
family:
@@ -19,3 +20,4 @@ family:
- name: qingke-v4f
socs:
- name: ch32v303
- name: ch32v307