drivers: reset: microchip: update RSTC G1 driver for PIC32CM JH

Update the reset driver to add support for the
PIC32CM JH family

Signed-off-by: Farsin Nasar V A <farsin.nasarva@microchip.com>
This commit is contained in:
Farsin Nasar V A
2026-01-08 12:44:02 +05:30
committed by Henrik Brix Andersen
parent a28ee312b0
commit 9d156cc98b
2 changed files with 14 additions and 11 deletions

View File

@@ -1,22 +1,14 @@
/*
* Copyright (c) 2025 Microchip Technology Inc.
* Copyright (c) 2025-2026 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file reset_mchp_rstc_g1.c
* @brief Zephyr reset driver for Microchip G1 peripherals
*
* This file implements the driver for the Microchip RSTC g1 reset controller,
* providing APIs to assert, deassert, toggle, and query the status of reset lines.
*
*/
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/drivers/reset/mchp_rstc_g1.h>
#define DT_DRV_COMPAT microchip_rstc_g1_reset
@@ -46,6 +38,8 @@ static int reset_mchp_status(const struct device *dev, uint32_t id, uint8_t *sta
if (id >= MCHP_RST_LINE_MAX) {
ret = -EINVAL;
} else if ((BIT(id) & RSTC_UNSUPPORTED_RCAUSE) != 0U) {
ret = -ENOTSUP;
} else {
rcause = (((const struct reset_mchp_config *)((dev)->config))->regs)->RSTC_RCAUSE;
*status = (rcause & BIT(id)) ? 1 : 0;

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2025 Microchip Technology Inc.
* Copyright (c) 2025-2026 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -32,4 +32,13 @@ enum rstc_g1_rcause {
RSTC_G1_RCAUSE_BACKUP = 7 /* Backup Reset */
};
#ifdef CONFIG_SOC_FAMILY_MICROCHIP_PIC32CM_JH
/* Reserved reset-cause bits on PIC32CM JH */
#define RSTC_RESERVED_BIT_3 BIT(3)
#define RSTC_RESERVED_BIT_7 BIT(7)
#define RSTC_UNSUPPORTED_RCAUSE ((RSTC_RESERVED_BIT_3) | (RSTC_RESERVED_BIT_7))
#else
#define RSTC_UNSUPPORTED_RCAUSE 0U
#endif /* CONFIG_SOC_FAMILY_MICROCHIP_PIC32CM_JH */
#endif /* INCLUDE_ZEPHYR_DRIVERS_RESET_MCHP_RSTC_G1_H_ */