soc: ti: k3: Add support for AM62L
The TI AM62L is a low-power ARM Cortex-A53 based SoC with display for IOT, HMI and general purpose applications. More information here: https://www.ti.com/product/AM62L Add initial SoC and DTS support here. Signed-off-by: Andrew Davis <afd@ti.com>
This commit is contained in:
Andrew Davis
committed by
Fabio Baltieri
Fabio Baltieri
parent
13eeffbc4b
commit
a159d0ee03
173
dts/arm64/ti/am62l3_a53.dtsi
Normal file
173
dts/arm64/ti/am62l3_a53.dtsi
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@@ -0,0 +1,173 @@
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/*
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* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <arm64/armv8-a.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <ti/am62l-main.dtsi>
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#include <ti/am62l-wakeup.dtsi>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <1>;
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};
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};
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firmware {
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psci: psci {
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compatible = "arm,psci-1.1";
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method = "smc";
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};
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scmi {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0x82004000>;
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shmem = <&scmi_shmem>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_pds: protocol@11 {
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compatible = "arm,scmi-power";
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reg = <0x11>;
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#power-domain-cells = <1>;
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};
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scmi_clk: protocol@14 {
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compatible = "arm,scmi-clock";
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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};
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oc_sram: sram@70800000 {
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compatible = "mmio-sram";
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reg = <0x70800000 DT_SIZE_K(64)>;
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ranges = <0x0 0x70800000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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scmi_shmem: sram@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x100>;
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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gic: interrupt-controller@1800000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x01800000 0x10000>, /* GICD */
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<0x01840000 0xc0000>; /* GICR */
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interrupt-controller;
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#interrupt-cells = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x01820000 0x10000>;
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status = "okay";
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};
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};
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};
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&wkup_timer0 {
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&wkup_timer1 {
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interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&wkup_i2c0 {
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&main_uart0 {
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&main_uart1 {
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&main_uart2 {
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&main_uart3 {
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&main_uart4 {
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&main_uart5 {
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&main_uart6 {
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&main_i2c0 {
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&main_i2c1 {
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&main_i2c2 {
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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&main_i2c3 {
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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283
dts/vendor/ti/am62l-main.dtsi
vendored
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283
dts/vendor/ti/am62l-main.dtsi
vendored
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@@ -0,0 +1,283 @@
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/*
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* Device Tree Source for AM62L SoC Family Main Domain peripherals
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*
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* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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main_uart0: serial@2800000 {
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compatible = "ns16550";
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reg = <0x02800000 0x100>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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main_uart1: serial@2810000 {
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compatible = "ns16550";
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reg = <0x02810000 0x100>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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main_uart2: serial@2820000 {
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compatible = "ns16550";
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reg = <0x02820000 0x100>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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main_uart3: serial@2830000 {
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compatible = "ns16550";
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reg = <0x02830000 0x100>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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main_uart4: serial@2840000 {
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compatible = "ns16550";
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reg = <0x02840000 0x100>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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main_uart5: serial@2850000 {
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compatible = "ns16550";
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reg = <0x02850000 0x100>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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main_uart6: serial@2860000 {
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compatible = "ns16550";
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reg = <0x02860000 0x100>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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main_i2c0: i2c@20000000 {
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compatible = "ti,omap-i2c";
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reg = <0x20000000 0x100>;
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clock-frequency = <100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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main_i2c1: i2c@20010000 {
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compatible = "ti,omap-i2c";
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reg = <0x20010000 0x100>;
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clock-frequency = <100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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main_i2c2: i2c@20020000 {
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compatible = "ti,omap-i2c";
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reg = <0x20020000 0x100>;
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clock-frequency = <100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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main_i2c3: i2c@20030000 {
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compatible = "ti,omap-i2c";
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reg = <0x20030000 0x100>;
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clock-frequency = <100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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main_gpio0: main-gpio0 {
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#gpio-cells = <2>;
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gpio-map = <0 0 &main_gpio0_0 0 0>, <1 0 &main_gpio0_0 1 0>,
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<2 0 &main_gpio0_0 2 0>, <3 0 &main_gpio0_0 3 0>,
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<4 0 &main_gpio0_0 4 0>, <5 0 &main_gpio0_0 5 0>,
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<6 0 &main_gpio0_0 6 0>, <7 0 &main_gpio0_0 7 0>,
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<8 0 &main_gpio0_0 8 0>, <9 0 &main_gpio0_0 9 0>,
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<10 0 &main_gpio0_0 10 0>, <11 0 &main_gpio0_0 11 0>,
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<12 0 &main_gpio0_0 12 0>, <13 0 &main_gpio0_0 13 0>,
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<14 0 &main_gpio0_0 14 0>, <15 0 &main_gpio0_0 15 0>,
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<16 0 &main_gpio0_0 16 0>, <17 0 &main_gpio0_0 17 0>,
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<18 0 &main_gpio0_0 18 0>, <19 0 &main_gpio0_0 19 0>,
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<20 0 &main_gpio0_0 20 0>, <21 0 &main_gpio0_0 21 0>,
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<22 0 &main_gpio0_0 22 0>, <23 0 &main_gpio0_0 23 0>,
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<24 0 &main_gpio0_0 24 0>, <25 0 &main_gpio0_0 25 0>,
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<26 0 &main_gpio0_0 26 0>, <27 0 &main_gpio0_0 27 0>,
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<28 0 &main_gpio0_0 28 0>, <29 0 &main_gpio0_0 29 0>,
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<30 0 &main_gpio0_0 30 0>, <31 0 &main_gpio0_0 31 0>,
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<32 0 &main_gpio0_1 0 0>, <33 0 &main_gpio0_1 1 0>,
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<34 0 &main_gpio0_1 2 0>, <35 0 &main_gpio0_1 3 0>,
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<36 0 &main_gpio0_1 4 0>, <37 0 &main_gpio0_1 5 0>,
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<38 0 &main_gpio0_1 6 0>, <39 0 &main_gpio0_1 7 0>,
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<40 0 &main_gpio0_1 8 0>, <41 0 &main_gpio0_1 9 0>,
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<42 0 &main_gpio0_1 10 0>, <43 0 &main_gpio0_1 11 0>,
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<44 0 &main_gpio0_1 12 0>, <45 0 &main_gpio0_1 13 0>,
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<46 0 &main_gpio0_1 14 0>, <47 0 &main_gpio0_1 15 0>,
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<48 0 &main_gpio0_1 16 0>, <49 0 &main_gpio0_1 17 0>,
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<50 0 &main_gpio0_1 18 0>, <51 0 &main_gpio0_1 19 0>,
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<52 0 &main_gpio0_1 20 0>, <53 0 &main_gpio0_1 21 0>,
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<54 0 &main_gpio0_1 22 0>, <55 0 &main_gpio0_1 23 0>,
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<56 0 &main_gpio0_1 24 0>, <57 0 &main_gpio0_1 25 0>,
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<58 0 &main_gpio0_1 26 0>, <59 0 &main_gpio0_1 27 0>,
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<60 0 &main_gpio0_1 28 0>, <61 0 &main_gpio0_1 29 0>,
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<62 0 &main_gpio0_1 30 0>, <63 0 &main_gpio0_1 31 0>,
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<64 0 &main_gpio0_2 0 0>, <65 0 &main_gpio0_2 1 0>,
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<66 0 &main_gpio0_2 2 0>, <67 0 &main_gpio0_2 3 0>,
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<68 0 &main_gpio0_2 4 0>, <69 0 &main_gpio0_2 5 0>,
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<70 0 &main_gpio0_2 6 0>, <71 0 &main_gpio0_2 7 0>,
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<72 0 &main_gpio0_2 8 0>, <73 0 &main_gpio0_2 9 0>,
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<74 0 &main_gpio0_2 10 0>, <75 0 &main_gpio0_2 11 0>,
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<76 0 &main_gpio0_2 12 0>, <77 0 &main_gpio0_2 13 0>,
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<78 0 &main_gpio0_2 14 0>, <79 0 &main_gpio0_2 15 0>,
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<80 0 &main_gpio0_2 16 0>, <81 0 &main_gpio0_2 17 0>,
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<82 0 &main_gpio0_2 18 0>, <83 0 &main_gpio0_2 17 0>,
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<84 0 &main_gpio0_2 20 0>, <85 0 &main_gpio0_2 21 0>,
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<86 0 &main_gpio0_2 22 0>, <87 0 &main_gpio0_2 23 0>,
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<88 0 &main_gpio0_2 24 0>, <89 0 &main_gpio0_2 25 0>,
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<90 0 &main_gpio0_2 26 0>, <91 0 &main_gpio0_2 27 0>,
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<92 0 &main_gpio0_2 28 0>, <93 0 &main_gpio0_2 29 0>,
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<94 0 &main_gpio0_2 30 0>, <95 0 &main_gpio0_2 31 0>,
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<96 0 &main_gpio0_3 0 0>, <97 0 &main_gpio0_3 1 0>,
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<98 0 &main_gpio0_3 2 0>, <99 0 &main_gpio0_3 3 0>,
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<100 0 &main_gpio0_3 4 0>, <101 0 &main_gpio0_3 5 0>,
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<102 0 &main_gpio0_3 6 0>, <103 0 &main_gpio0_3 7 0>,
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<104 0 &main_gpio0_3 8 0>, <105 0 &main_gpio0_3 9 0>,
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<106 0 &main_gpio0_3 10 0>, <107 0 &main_gpio0_3 11 0>,
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<108 0 &main_gpio0_3 12 0>, <109 0 &main_gpio0_3 13 0>,
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<110 0 &main_gpio0_3 14 0>, <111 0 &main_gpio0_3 15 0>,
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<112 0 &main_gpio0_3 16 0>, <113 0 &main_gpio0_3 17 0>,
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<114 0 &main_gpio0_3 18 0>, <115 0 &main_gpio0_3 17 0>,
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<116 0 &main_gpio0_3 20 0>, <117 0 &main_gpio0_3 21 0>,
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<118 0 &main_gpio0_3 22 0>, <119 0 &main_gpio0_3 23 0>,
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<120 0 &main_gpio0_3 24 0>, <121 0 &main_gpio0_3 25 0>,
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<122 0 &main_gpio0_3 26 0>, <123 0 &main_gpio0_3 27 0>,
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<124 0 &main_gpio0_3 28 0>, <125 0 &main_gpio0_3 29 0>;
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gpio-map-mask = <0xffff 0x0>;
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gpio-map-pass-thru = <0x0 0x1>;
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};
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main_gpio0_0: gpio@600010 {
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compatible = "ti,davinci-gpio";
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reg = <0x00600010 0x28>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "disabled";
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};
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main_gpio0_1: gpio@600038 {
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compatible = "ti,davinci-gpio";
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reg = <0x00600038 0x28>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "disabled";
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};
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main_gpio0_2: gpio@600060 {
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compatible = "ti,davinci-gpio";
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reg = <0x00600060 0x28>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "disabled";
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};
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main_gpio0_3: gpio@600088 {
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compatible = "ti,davinci-gpio";
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reg = <0x00600088 0x28>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <30>;
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status = "disabled";
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};
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main_rti0: watchdog@e000000 {
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compatible = "ti,j7-rti-wdt";
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reg = <0x0e000000 0x100>;
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clock-frequency = <DT_FREQ_M(25)>;
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status = "disabled";
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};
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main_rti1: watchdog@e010000 {
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compatible = "ti,j7-rti-wdt";
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reg = <0x0e010000 0x100>;
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clock-frequency = <DT_FREQ_M(25)>;
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status = "disabled";
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};
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main_spi0: spi@20100000 {
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compatible = "ti,omap-mcspi";
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reg = <0x20100000 0x400>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&scmi_pds 72>;
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clock-frequency = <DT_FREQ_M(50)>;
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clocks = <&scmi_clk 299>;
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ti,spi-num-cs = <4>;
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status = "disabled";
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};
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|
||||
main_spi1: spi@20110000 {
|
||||
compatible = "ti,omap-mcspi";
|
||||
reg = <0x20110000 0x400>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&scmi_pds 73>;
|
||||
clock-frequency = <DT_FREQ_M(50)>;
|
||||
clocks = <&scmi_clk 302>;
|
||||
ti,spi-num-cs = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_spi2: spi@20120000 {
|
||||
compatible = "ti,omap-mcspi";
|
||||
reg = <0x20120000 0x400>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&scmi_pds 74>;
|
||||
clock-frequency = <DT_FREQ_M(50)>;
|
||||
clocks = <&scmi_clk 305>;
|
||||
ti,spi-num-cs = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_spi3: spi@20130000 {
|
||||
compatible = "ti,omap-mcspi";
|
||||
reg = <0x20130000 0x400>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&scmi_pds 75>;
|
||||
clock-frequency = <DT_FREQ_M(50)>;
|
||||
clocks = <&scmi_clk 308>;
|
||||
ti,spi-num-cs = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
56
dts/vendor/ti/am62l-wakeup.dtsi
vendored
Normal file
56
dts/vendor/ti/am62l-wakeup.dtsi
vendored
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Device Tree Source for AM62L SoC Family Wakeup Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/ {
|
||||
wkup_pinctrl: pinctrl@4084000 {
|
||||
compatible = "ti,k3-pinctrl";
|
||||
reg = <0x04084000 0x24c>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_gpio0: gpio@4201010 {
|
||||
compatible = "ti,davinci-gpio";
|
||||
reg = <0x04201010 0x28>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <7>;
|
||||
power-domains = <&scmi_pds 36>;
|
||||
clocks = <&scmi_clk 146>;
|
||||
clock-names = "gpio";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_timer0: timer@2b100000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x2b100000 DT_SIZE_K(1)>;
|
||||
clocks = <&scmi_clk 93>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&scmi_pds 19>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_timer1: timer@2b110000 {
|
||||
compatible = "ti,am654-timer";
|
||||
reg = <0x2b110000 DT_SIZE_K(1)>;
|
||||
clocks = <&scmi_clk 98>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&scmi_pds 20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@2b200000 {
|
||||
compatible = "ti,omap-i2c";
|
||||
reg = <0x2b200000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&scmi_pds 57>;
|
||||
clocks = <&scmi_clk 262>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@@ -4,7 +4,7 @@
|
||||
zephyr_include_directories(.)
|
||||
zephyr_sources(common/ctrl_partitions.c)
|
||||
|
||||
if(CONFIG_SOC_AM6234_A53 OR CONFIG_SOC_AM6232_A53 OR CONFIG_SOC_AM6254_A53)
|
||||
if(CONFIG_SOC_AM6234_A53 OR CONFIG_SOC_AM6232_A53 OR CONFIG_SOC_AM6254_A53 OR CONFIG_SOC_AM62L3_A53)
|
||||
zephyr_sources_ifdef(CONFIG_ARM_MMU a53/mmu_regions.c)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
|
||||
|
||||
@@ -39,6 +39,7 @@ config SOC_PART_NUMBER
|
||||
default "AM6234" if SOC_AM6234_A53
|
||||
default "AM6234" if SOC_AM6234_M4
|
||||
default "AM6254" if SOC_AM6254_M4 || SOC_AM6254_A53
|
||||
default "AM62L3" if SOC_AM62L3_A53
|
||||
default "AM6442" if SOC_AM6442_M4
|
||||
default "AM6442" if SOC_AM6442_R5F0_0
|
||||
default "AM6442" if SOC_AM6442_R5F0_1
|
||||
|
||||
@@ -47,6 +47,10 @@ config SOC_AM6232_M4
|
||||
bool
|
||||
select SOC_SERIES_AM6X_M4
|
||||
|
||||
config SOC_AM62L3_A53
|
||||
bool
|
||||
select SOC_SERIES_AM6X_A53
|
||||
|
||||
config SOC_AM6442_M4
|
||||
bool
|
||||
select SOC_SERIES_AM6X_M4
|
||||
@@ -95,6 +99,7 @@ config SOC
|
||||
default "am6232" if SOC_AM6232_M4 || SOC_AM6232_A53
|
||||
default "am6234" if SOC_AM6234_M4 || SOC_AM6234_A53
|
||||
default "am6254" if SOC_AM6254_M4 || SOC_AM6254_A53
|
||||
default "am62l3" if SOC_AM62L3_A53
|
||||
default "am6442" if SOC_AM6442_M4
|
||||
default "am6442" if SOC_AM6442_R5F0_0
|
||||
default "am6442" if SOC_AM6442_R5F0_1
|
||||
|
||||
@@ -15,6 +15,9 @@ family:
|
||||
cpuclusters:
|
||||
- name: m4
|
||||
- name: a53
|
||||
- name: am62l3
|
||||
cpuclusters:
|
||||
- name: a53
|
||||
- name: am6442
|
||||
cpuclusters:
|
||||
- name: m4
|
||||
|
||||
Reference in New Issue
Block a user