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drivers: clock_control: PIC32CM_JH: Add clock control driver

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Add clock control driver.
Implement bootup clock initialization, on, off and get_rate API.

Signed-off-by: Sunil Abraham <sunil.abraham@microchip.com>
This commit is contained in:
Sunil Abraham
2025-09-26 12:10:32 +05:30
committed by Anas Nashif
parent 236589252e
commit a280bb5b9d
6 changed files with 2088 additions and 1 deletions
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1
drivers/clock_control/CMakeLists.txt
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@@ -83,6 +83,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IT51XXX clock_control_it51xxx.
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X clock_control_lpc11u6x.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MAX32 clock_control_max32.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_PIC32CM_JH clock_control_mchp_pic32cm_jh.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_SAM_D5X_E5X clock_control_mchp_sam_d5x_e5x.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_XEC clock_control_mchp_xec.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_CCM clock_control_mcux_ccm.c)

10
drivers/clock_control/Kconfig.mchp
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@@ -7,13 +7,21 @@ config CLOCK_CONTROL_MCHP_COMMON
Common options for Microchip clock control drivers.
config CLOCK_CONTROL_MCHP_SAM_D5X_E5X
bool "Microchip SAM D5X/E5X clock controller Support"
bool
depends on DT_HAS_MICROCHIP_SAM_D5X_E5X_CLOCK_ENABLED
default y
select CLOCK_CONTROL_MCHP_COMMON
help
Enable clock controller driver for Microchip SAM D5X/E5X SoC family.
config CLOCK_CONTROL_MCHP_PIC32CM_JH
bool
default y
depends on DT_HAS_MICROCHIP_PIC32CM_JH_CLOCK_ENABLED
select CLOCK_CONTROL_MCHP_COMMON
help
Enable clock controller driver for Microchip PIC32CM_JH family.
if CLOCK_CONTROL_MCHP_COMMON
config CLOCK_CONTROL_MCHP_CONFIG_BOOTUP

1874
drivers/clock_control/clock_control_mchp_pic32cm_jh.c Normal file
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File diff suppressed because it is too large Load Diff

4
include/zephyr/drivers/clock_control/mchp_clock_control.h
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@@ -22,4 +22,8 @@
#include <zephyr/drivers/clock_control/mchp_clock_sam_d5x_e5x.h>
#endif /* CLOCK_CONTROL_MCHP_SAM_D5X_E5X */
#if CONFIG_CLOCK_CONTROL_MCHP_PIC32CM_JH
#include <zephyr/drivers/clock_control/mchp_clock_pic32cm_jh.h>
#endif /* CONFIG_CLOCK_CONTROL_MCHP_PIC32CM_JH */
#endif /* INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_CONTROL_H_ */

199
include/zephyr/drivers/clock_control/mchp_clock_pic32cm_jh.h Normal file
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@@ -0,0 +1,199 @@
/*
* Copyright (c) 2025 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file mchp_clock_pic32cm_jh.h
* @brief Clock control header file for Microchip pic32cm_jh family.
*
* This file provides clock driver interface definitions and structures
* for pic32cm_jh family
*/
#ifndef INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_PIC32CM_JH_H_
#define INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_PIC32CM_JH_H_
#include <zephyr/dt-bindings/clock/mchp_pic32cm_jh_clock.h>
struct clock_mchp_subsys_xosc_config {
/** @brief configure oscillator to ON, when a peripheral is requesting it as a source */
bool on_demand_en;
/** @brief configure oscillator to ON in standby sleep mode, unless on_demand_en is set */
bool run_in_standby_en;
};
/** @brief Control the oscillator frequency range by adjusting the division ratio */
enum clock_mchp_osc48m_divider_freq {
CLOCK_MCHP_DIVIDER_48_MHZ,
CLOCK_MCHP_DIVIDER_24_MHZ,
CLOCK_MCHP_DIVIDER_16_MHZ,
CLOCK_MCHP_DIVIDER_12_MHZ,
CLOCK_MCHP_DIVIDER_9_6_MHZ,
CLOCK_MCHP_DIVIDER_8_MHZ,
CLOCK_MCHP_DIVIDER_6_86_MHZ,
CLOCK_MCHP_DIVIDER_6_MHZ,
CLOCK_MCHP_DIVIDER_5_33_MHZ,
CLOCK_MCHP_DIVIDER_4_8_MHZ,
CLOCK_MCHP_DIVIDER_4_36_MHZ,
CLOCK_MCHP_DIVIDER_4_MHZ,
CLOCK_MCHP_DIVIDER_3_69_MHZ,
CLOCK_MCHP_DIVIDER_3_43_MHZ,
CLOCK_MCHP_DIVIDER_3_2_MHZ,
CLOCK_MCHP_DIVIDER_3_MHZ
};
struct clock_mchp_subsys_osc48m_config {
/** @brief configure oscillator to ON, when a peripheral is requesting it as a source */
bool on_demand_en;
/** @brief configure oscillator to ON in standby sleep mode, unless on_demand_en is set */
bool run_in_standby_en;
/** @brief Control the oscillator frequency range by adjusting the division ratio */
enum clock_mchp_osc48m_divider_freq post_divider_freq;
};
/** @brief FDPLL source clocks */
enum clock_mchp_fdpll_src_clock {
CLOCK_MCHP_FDPLL_SRC_GCLK0,
CLOCK_MCHP_FDPLL_SRC_GCLK1,
CLOCK_MCHP_FDPLL_SRC_GCLK2,
CLOCK_MCHP_FDPLL_SRC_GCLK3,
CLOCK_MCHP_FDPLL_SRC_GCLK4,
CLOCK_MCHP_FDPLL_SRC_GCLK5,
CLOCK_MCHP_FDPLL_SRC_GCLK6,
CLOCK_MCHP_FDPLL_SRC_GCLK7,
CLOCK_MCHP_FDPLL_SRC_GCLK8,
CLOCK_MCHP_FDPLL_SRC_XOSC32K,
CLOCK_MCHP_FDPLL_SRC_XOSC,
CLOCK_MCHP_FDPLL_SRC_MAX = CLOCK_MCHP_FDPLL_SRC_XOSC
};
struct clock_mchp_subsys_fdpll_config {
/** @brief configure oscillator to ON, when a peripheral is requesting it as a source */
bool on_demand_en;
/** @brief configure oscillator to ON in standby sleep mode, unless on_demand_en is set */
bool run_in_standby_en;
/** @brief Set the fractional part of the frequency multiplier. (0 - 31) */
uint32_t divider_ratio_frac;
/** @brief Set the integer part of the frequency multiplier. (0 - 4095) */
uint32_t divider_ratio_int;
/** @brief Set the XOSC clock division factor (0 - 2047) */
uint32_t xosc_clock_divider;
/** @brief Reference source clock selection */
enum clock_mchp_fdpll_src_clock src;
};
/** @brief RTC source clocks */
enum clock_mchp_rtc_src_clock {
CLOCK_MCHP_RTC_SRC_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K,
CLOCK_MCHP_RTC_SRC_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K,
CLOCK_MCHP_RTC_SRC_OSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K,
CLOCK_MCHP_RTC_SRC_OSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K,
CLOCK_MCHP_RTC_SRC_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K,
CLOCK_MCHP_RTC_SRC_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K
};
struct clock_mchp_subsys_rtc_config {
/** @brief RTC source clock selection */
enum clock_mchp_rtc_src_clock src;
};
struct clock_mchp_subsys_xosc32k_config {
/** @brief configure oscillator to ON, when a peripheral is requesting it as a source */
bool on_demand_en;
/** @brief configure oscillator to ON in standby sleep mode, unless on_demand_en is set */
bool run_in_standby_en;
};
struct clock_mchp_subsys_osc32k_config {
/** @brief configure oscillator to ON, when a peripheral is requesting it as a source */
bool on_demand_en;
/** @brief configure oscillator to ON in standby sleep mode, unless on_demand_en is set */
bool run_in_standby_en;
};
/** @brief Gclk Generator source clocks */
enum clock_mchp_gclk_src_clock {
CLOCK_MCHP_GCLK_SRC_XOSC,
CLOCK_MCHP_GCLK_SRC_GCLKPIN,
CLOCK_MCHP_GCLK_SRC_GCLKGEN1,
CLOCK_MCHP_GCLK_SRC_OSCULP32K,
CLOCK_MCHP_GCLK_SRC_OSC32K,
CLOCK_MCHP_GCLK_SRC_XOSC32K,
CLOCK_MCHP_GCLK_SRC_OSC48M,
CLOCK_MCHP_GCLK_SRC_FDPLL,
CLOCK_MCHP_GCLK_SRC_MAX = CLOCK_MCHP_GCLK_SRC_FDPLL
};
struct clock_mchp_subsys_gclkgen_config {
/** @brief Represent a division value for the corresponding Generator. The actual division
* factor is dependent on the state of div_select (gclk1 0 - 65535, others 0 - 255)
*/
uint16_t div_factor;
/** @brief configure oscillator to ON in standby sleep mode, unless on_demand_en is set */
bool run_in_standby_en;
/** @brief Generator source clock selection */
enum clock_mchp_gclk_src_clock src;
};
/** @brief GCLK generator numbers */
enum clock_mchp_gclkgen {
CLOCK_MCHP_GCLKGEN_GEN0,
CLOCK_MCHP_GCLKGEN_GEN1,
CLOCK_MCHP_GCLKGEN_GEN2,
CLOCK_MCHP_GCLKGEN_GEN3,
CLOCK_MCHP_GCLKGEN_GEN4,
CLOCK_MCHP_GCLKGEN_GEN5,
CLOCK_MCHP_GCLKGEN_GEN6,
CLOCK_MCHP_GCLKGEN_GEN7,
CLOCK_MCHP_GCLKGEN_GEN8
};
struct clock_mchp_subsys_gclkperiph_config {
/** @brief gclk generator source of a peripheral clock */
enum clock_mchp_gclkgen src;
};
/** @brief division ratio of mclk prescaler for CPU */
enum clock_mchp_mclk_cpu_div {
CLOCK_MCHP_MCLK_CPU_DIV_1 = 1,
CLOCK_MCHP_MCLK_CPU_DIV_2 = 2,
CLOCK_MCHP_MCLK_CPU_DIV_4 = 4,
CLOCK_MCHP_MCLK_CPU_DIV_8 = 8,
CLOCK_MCHP_MCLK_CPU_DIV_16 = 16,
CLOCK_MCHP_MCLK_CPU_DIV_32 = 32,
CLOCK_MCHP_MCLK_CPU_DIV_64 = 64,
CLOCK_MCHP_MCLK_CPU_DIV_128 = 128
};
/** @brief MCLK configuration structure
*
* Used for CLOCK_MCHP_SUBSYS_TYPE_MCLKCPU
*/
struct clock_mchp_subsys_mclkcpu_config {
/** @brief division ratio of mclk prescaler for CPU */
enum clock_mchp_mclk_cpu_div division_factor;
};
/** @brief clock rate datatype
*
* Used for setting a clock rate
*/
typedef uint32_t *clock_mchp_rate_t;
#endif /* INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_PIC32CM_JH_H_ */

1
soc/microchip/pic32c/pic32cm_jh/Kconfig
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@@ -9,3 +9,4 @@ config SOC_FAMILY_MICROCHIP_PIC32CM_JH
select CPU_CORTEX_M_HAS_VTOR
select CPU_HAS_ARM_MPU
select SOC_RESET_HOOK
select CLOCK_CONTROL