drivers: dma: siwx91x: replace pm_state with pm_device (udma and gpdma)
Removed unnecessary power management state lock calls since the DMA is on a power domain that already handles state locking. It will now managed directly pm_device which will active power_domain and then block pm_state. Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
This commit is contained in:
committed by
Benjamin Cabé
parent
d5c45b10e5
commit
aa315948dc
@@ -14,7 +14,7 @@
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/pm/policy.h>
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#include <zephyr/pm/device_runtime.h>
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#include <zephyr/types.h>
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#include "rsi_rom_udma.h"
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#include "rsi_rom_udma_wrapper.h"
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@@ -63,16 +63,6 @@ struct dma_siwx91x_data {
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*/
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};
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static void siwx91x_dma_pm_policy_state_lock_get(void)
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{
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pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
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}
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static void siwx91x_dma_pm_policy_state_lock_put(void)
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{
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pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
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}
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static enum dma_xfer_dir siwx91x_transfer_direction(uint32_t dir)
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{
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if (dir == MEMORY_TO_MEMORY) {
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@@ -495,15 +485,14 @@ static int siwx91x_dma_start(const struct device *dev, uint32_t channel)
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return -EINVAL;
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}
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/* Get the power management policy state lock */
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if (!data->zephyr_channel_info[channel].channel_active) {
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siwx91x_dma_pm_policy_state_lock_get();
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pm_device_runtime_get(dev);
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data->zephyr_channel_info[channel].channel_active = true;
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}
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if (RSI_UDMA_ChannelEnable(udma_handle, channel) != 0) {
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if (data->zephyr_channel_info[channel].channel_active) {
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siwx91x_dma_pm_policy_state_lock_put();
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pm_device_runtime_put(dev);
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data->zephyr_channel_info[channel].channel_active = false;
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}
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return -EINVAL;
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@@ -534,7 +523,7 @@ static int siwx91x_dma_stop(const struct device *dev, uint32_t channel)
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}
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if (data->zephyr_channel_info[channel].channel_active) {
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siwx91x_dma_pm_policy_state_lock_put();
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pm_device_runtime_put(dev);
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data->zephyr_channel_info[channel].channel_active = false;
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}
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@@ -680,16 +669,16 @@ static void siwx91x_dma_isr(const struct device *dev)
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}
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if (data->chan_info[channel].Cnt == data->chan_info[channel].Size) {
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if (data->zephyr_channel_info[channel].channel_active) {
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pm_device_runtime_put_async(dev, K_NO_WAIT);
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data->zephyr_channel_info[channel].channel_active = false;
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}
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if (data->zephyr_channel_info[channel].dma_callback) {
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/* Transfer complete, call user callback */
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data->zephyr_channel_info[channel].dma_callback(
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dev, data->zephyr_channel_info[channel].cb_data, channel, 0);
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}
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sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->UDMA_DONE_STATUS_REG);
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if (data->zephyr_channel_info[channel].channel_active) {
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siwx91x_dma_pm_policy_state_lock_put();
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data->zephyr_channel_info[channel].channel_active = false;
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}
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} else {
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/* Call UDMA ROM IRQ handler. */
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ROMAPI_UDMA_WRAPPER_API->uDMAx_IRQHandler(&udma_resources, udma_resources.desc,
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@@ -12,7 +12,7 @@
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/pm/policy.h>
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#include <zephyr/pm/device_runtime.h>
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#include "rsi_gpdma.h"
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#include "rsi_rom_gpdma.h"
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@@ -43,6 +43,7 @@ struct siwx91x_gpdma_channel_info {
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void *cb_data;
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RSI_GPDMA_DESC_T *desc;
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enum gpdma_xfer_dir xfer_direction;
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bool channel_active;
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};
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struct siwx91x_gpdma_config {
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@@ -62,16 +63,6 @@ struct siwx19x_gpdma_data {
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uint8_t reload_compatible;
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};
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static void siwx91x_gpdma_pm_policy_state_lock_get(void)
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{
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pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
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}
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static void siwx91x_gpdma_pm_policy_state_lock_put(void)
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{
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pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
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}
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static bool siwx91x_gpdma_is_priority_valid(uint32_t channel_priority)
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{
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return (channel_priority >= GPDMA_MIN_PRIORITY && channel_priority <= GPDMA_MAX_PRIORITY);
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@@ -408,19 +399,22 @@ static int siwx91x_gpdma_reload(const struct device *dev, uint32_t channel, uint
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static int siwx91x_gpdma_start(const struct device *dev, uint32_t channel)
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{
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const struct siwx91x_gpdma_config *cfg = dev->config;
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struct siwx19x_gpdma_data *data = dev->data;
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if (channel >= data->dma_ctx.dma_channels) {
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return -EINVAL;
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}
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if (!sys_test_bit((mem_addr_t)&cfg->reg->GLOBAL.DMA_CHNL_ENABLE_REG, channel)) {
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siwx91x_gpdma_pm_policy_state_lock_get();
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if (data->chan_info[channel].channel_active) {
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pm_device_runtime_get(dev);
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data->chan_info[channel].channel_active = true;
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}
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if (RSI_GPDMA_DMAChannelTrigger(&data->hal_ctx, channel)) {
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siwx91x_gpdma_pm_policy_state_lock_put();
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if (data->chan_info[channel].channel_active) {
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pm_device_runtime_put(dev);
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data->chan_info[channel].channel_active = false;
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}
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return -EINVAL;
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}
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@@ -429,7 +423,6 @@ static int siwx91x_gpdma_start(const struct device *dev, uint32_t channel)
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static int siwx91x_gpdma_stop(const struct device *dev, uint32_t channel)
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{
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const struct siwx91x_gpdma_config *cfg = dev->config;
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struct siwx19x_gpdma_data *data = dev->data;
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k_spinlock_key_t key;
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@@ -437,10 +430,6 @@ static int siwx91x_gpdma_stop(const struct device *dev, uint32_t channel)
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return -EINVAL;
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}
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if (sys_test_bit((mem_addr_t)&cfg->reg->GLOBAL.DMA_CHNL_ENABLE_REG, channel)) {
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siwx91x_gpdma_pm_policy_state_lock_put();
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}
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if (RSI_GPDMA_AbortChannel(&data->hal_ctx, channel)) {
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return -EINVAL;
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}
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@@ -449,6 +438,11 @@ static int siwx91x_gpdma_stop(const struct device *dev, uint32_t channel)
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siwx91x_gpdma_free_desc(data->desc_pool, data->chan_info[channel].desc);
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k_spin_unlock(&data->desc_pool_lock, key);
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if (data->chan_info[channel].channel_active) {
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pm_device_runtime_put(dev);
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data->chan_info[channel].channel_active = false;
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}
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return 0;
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}
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@@ -552,7 +546,10 @@ static void siwx91x_gpdma_isr(const struct device *dev)
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if (channel_int_status & abort_mask) {
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RSI_GPDMA_AbortChannel(&data->hal_ctx, channel);
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cfg->reg->GLOBAL.INTERRUPT_STAT_REG = abort_mask;
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siwx91x_gpdma_pm_policy_state_lock_put();
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if (data->chan_info[channel].channel_active) {
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pm_device_runtime_put_async(dev, K_NO_WAIT);
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data->chan_info[channel].channel_active = false;
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}
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}
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if (channel_int_status & desc_fetch_mask) {
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@@ -569,11 +566,16 @@ static void siwx91x_gpdma_isr(const struct device *dev)
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k_spin_unlock(&data->desc_pool_lock, key);
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data->chan_info[channel].desc = NULL;
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cfg->reg->GLOBAL.INTERRUPT_STAT_REG = done_mask;
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if (data->chan_info[channel].channel_active) {
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pm_device_runtime_put_async(dev, K_NO_WAIT);
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data->chan_info[channel].channel_active = false;
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}
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if (data->chan_info[channel].cb) {
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data->chan_info[channel].cb(dev, data->chan_info[channel].cb_data, channel,
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0);
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}
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siwx91x_gpdma_pm_policy_state_lock_put();
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}
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}
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