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nordic: update and align to nrfx 4.0.1

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New nrfx release contains major rework of nrfx drivers
instantiation making it easier to integrate with dts nodes.
Now, nrfx driver instances can no longer be `const`
because they contain driver runtime state.
Additionally, all nrfx drivers return `errno` error codes
instead of deprecated `nrfx_err_t`.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
This commit is contained in:
Nikodem Kastelik
2025-10-31 16:21:51 +01:00
committed by Carles Cufí
parent 8ae38804ac
commit ad1e5ac253
143 changed files with 1802 additions and 5246 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
boards/native/nrf_bsim/CMakeLists.txt
View File

@@ -25,12 +25,21 @@ zephyr_library_sources(
argparse.c
nsi_if.c
native_remap.c
gpiote_nrfx_bsim.c
soc/nrfx_coredep.c
common/bstests_entry.c
common/cmsis/cmsis.c
common/trace_hook.c
)
# Include GPIOTE nrfx from real SOC code
zephyr_library_sources(${ZEPHYR_BASE}/soc/nordic/common/gpiote_nrfx.c)
# Include gppi_init from real SOC code if enabled
if(CONFIG_NRFX_GPPI AND NOT CONFIG_NRFX_GPPI_V1)
zephyr_library_sources(${ZEPHYR_BASE}/soc/nordic/common/gppi_init.c)
endif()
# Include sync_rtc from real SOC code if enabled
zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC
${ZEPHYR_BASE}/soc/nordic/nrf53/sync_rtc.c

2
boards/native/nrf_bsim/common/cmsis/cmsis.h
View File

@@ -15,7 +15,7 @@
#include <stdint.h>
#include "cmsis_instr.h"
#if defined(CONFIG_SOC_COMPATIBLE_NRF52833)
#include "nrf52833.h"
#include "mdk/nrf52833.h"
#endif
#ifdef __cplusplus

39
boards/native/nrf_bsim/gpiote_nrfx_bsim.c Normal file
View File

@@ -0,0 +1,39 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <nrfx_gpiote.h>
#include "gpiote_nrfx.h"
#define GPIOTE_NRFX_INST_IDX(idx) DT_CAT3(NRFX_GPIOTE, idx, _INST_IDX)
#define GPIOTE_INST_IDX(node_id) GPIOTE_NRFX_INST_IDX(DT_PROP(node_id, instance))
#define GPIOTE_INST_AND_COMMA(node_id) \
[GPIOTE_INST_IDX(node_id)] = &GPIOTE_NRFX_INST_BY_NODE(node_id),
/* Conversion of hardcoded DT addresses into the correct ones for simulation
* is done here rather than within `gpio` driver implementation because `gpio` driver
* operates on GPIO ports instances, which might or might not be associated
* with a GPIOTE instance. Additionally, single GPIOTE instance might be associated
* with multiple GPIO ports instances. This makes iterating over all enabled GPIOTE instances
* problematic in the `gpio` driver initialization function context.
*/
static int gpiote_bsim_init(void)
{
nrfx_gpiote_t *gpiote_instances[] = {
DT_FOREACH_STATUS_OKAY(nordic_nrf_gpiote, GPIOTE_INST_AND_COMMA)
};
/* For simulated devices we need to convert the hardcoded DT address from the real
* peripheral into the correct one for simulation
*/
for (int inst = 0; inst < ARRAY_SIZE(gpiote_instances); inst++) {
gpiote_instances[inst]->p_reg =
nhw_convert_periph_base_addr(gpiote_instances[inst]->p_reg);
}
return 0;
}
SYS_INIT(gpiote_bsim_init, PRE_KERNEL_1, 0);

2
boards/native/nrf_bsim/soc/soc_secure.h
View File

@@ -12,7 +12,7 @@
#include <stdint.h>
#include <nrf.h>
#include <nrfx.h>
#include <hal/nrf_ficr.h>
static inline void soc_secure_read_deviceid(uint32_t deviceid[2])

6
drivers/adc/adc_nrfx_adc.c
View File

@@ -265,12 +265,12 @@ static int init_adc(const struct device *dev)
{
const nrfx_adc_config_t config = NRFX_ADC_DEFAULT_CONFIG;
nrfx_err_t result = nrfx_adc_init(&config, event_handler);
int result = nrfx_adc_init(&config, event_handler);
if (result != NRFX_SUCCESS) {
if (result != 0) {
LOG_ERR("Failed to initialize device: %s",
dev->name);
return -EBUSY;
return result;
}
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),

283
drivers/adc/adc_nrfx_saadc.c
View File

@@ -6,9 +6,7 @@
#include "adc_context.h"
#include <nrfx_saadc.h>
#include <zephyr/dt-bindings/adc/nrf-saadc-v3.h>
#include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
#include <zephyr/dt-bindings/adc/nrf-saadc-haltium.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
@@ -22,91 +20,22 @@ LOG_MODULE_REGISTER(adc_nrfx_saadc, CONFIG_ADC_LOG_LEVEL);
#define DT_DRV_COMPAT nordic_nrf_saadc
#if (NRF_SAADC_HAS_AIN_AS_PIN)
#if defined(CONFIG_NRF_PLATFORM_HALTIUM)
static const uint32_t saadc_psels[NRF_SAADC_AIN13 + 1] = {
[NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1),
[NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(1U, 1),
[NRF_SAADC_AIN2] = NRF_PIN_PORT_TO_PIN_NUMBER(2U, 1),
[NRF_SAADC_AIN3] = NRF_PIN_PORT_TO_PIN_NUMBER(3U, 1),
[NRF_SAADC_AIN4] = NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1),
[NRF_SAADC_AIN5] = NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
[NRF_SAADC_AIN6] = NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
[NRF_SAADC_AIN7] = NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1),
[NRF_SAADC_AIN8] = NRF_PIN_PORT_TO_PIN_NUMBER(0U, 9),
[NRF_SAADC_AIN9] = NRF_PIN_PORT_TO_PIN_NUMBER(1U, 9),
[NRF_SAADC_AIN10] = NRF_PIN_PORT_TO_PIN_NUMBER(2U, 9),
[NRF_SAADC_AIN11] = NRF_PIN_PORT_TO_PIN_NUMBER(3U, 9),
[NRF_SAADC_AIN12] = NRF_PIN_PORT_TO_PIN_NUMBER(4U, 9),
[NRF_SAADC_AIN13] = NRF_PIN_PORT_TO_PIN_NUMBER(5U, 9),
};
#elif defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15)
static const uint32_t saadc_psels[NRF_SAADC_DVDD + 1] = {
[NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1),
[NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
[NRF_SAADC_AIN2] = NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
[NRF_SAADC_AIN3] = NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1),
[NRF_SAADC_AIN4] = NRF_PIN_PORT_TO_PIN_NUMBER(11U, 1),
[NRF_SAADC_AIN5] = NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1),
[NRF_SAADC_AIN6] = NRF_PIN_PORT_TO_PIN_NUMBER(13U, 1),
[NRF_SAADC_AIN7] = NRF_PIN_PORT_TO_PIN_NUMBER(14U, 1),
[NRF_SAADC_VDD] = NRF_SAADC_INPUT_VDD,
[NRF_SAADC_AVDD] = NRF_SAADC_INPUT_AVDD,
[NRF_SAADC_DVDD] = NRF_SAADC_INPUT_DVDD,
};
#elif defined(NRF54LM20A_ENGA_XXAA)
static const uint32_t saadc_psels[NRF_SAADC_DVDD + 1] = {
[NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1),
[NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(31U, 1),
[NRF_SAADC_AIN2] = NRF_PIN_PORT_TO_PIN_NUMBER(30U, 1),
[NRF_SAADC_AIN3] = NRF_PIN_PORT_TO_PIN_NUMBER(29U, 1),
[NRF_SAADC_AIN4] = NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
[NRF_SAADC_AIN5] = NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
[NRF_SAADC_AIN6] = NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1),
[NRF_SAADC_AIN7] = NRF_PIN_PORT_TO_PIN_NUMBER(3U, 1),
[NRF_SAADC_VDD] = NRF_SAADC_INPUT_VDD,
[NRF_SAADC_AVDD] = NRF_SAADC_INPUT_AVDD,
[NRF_SAADC_DVDD] = NRF_SAADC_INPUT_DVDD,
};
#elif defined(NRF54LV10A_ENGA_XXAA)
static const uint32_t saadc_psels[NRF_SAADC_AIN7 + 1] = {
[NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1),
[NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(1U, 1),
[NRF_SAADC_AIN2] = NRF_PIN_PORT_TO_PIN_NUMBER(2U, 1),
[NRF_SAADC_AIN3] = NRF_PIN_PORT_TO_PIN_NUMBER(3U, 1),
[NRF_SAADC_AIN4] = NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1),
[NRF_SAADC_AIN5] = NRF_PIN_PORT_TO_PIN_NUMBER(10U, 1),
[NRF_SAADC_AIN6] = NRF_PIN_PORT_TO_PIN_NUMBER(11U, 1),
[NRF_SAADC_AIN7] = NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1),
};
#elif defined(NRF54LS05B_ENGA_XXAA)
static const uint32_t saadc_psels[NRF_SAADC_AIN3 + 1] = {
[NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1),
[NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
[NRF_SAADC_AIN2] = NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
[NRF_SAADC_AIN3] = NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1),
};
BUILD_ASSERT((NRF_SAADC_AIN0 == NRFX_ANALOG_EXTERNAL_AIN0) &&
(NRF_SAADC_AIN1 == NRFX_ANALOG_EXTERNAL_AIN1) &&
(NRF_SAADC_AIN2 == NRFX_ANALOG_EXTERNAL_AIN2) &&
(NRF_SAADC_AIN3 == NRFX_ANALOG_EXTERNAL_AIN3) &&
(NRF_SAADC_AIN4 == NRFX_ANALOG_EXTERNAL_AIN4) &&
(NRF_SAADC_AIN5 == NRFX_ANALOG_EXTERNAL_AIN5) &&
(NRF_SAADC_AIN6 == NRFX_ANALOG_EXTERNAL_AIN6) &&
(NRF_SAADC_AIN7 == NRFX_ANALOG_EXTERNAL_AIN7) &&
#if NRF_SAADC_HAS_INPUT_VDDHDIV5
(NRF_SAADC_VDDHDIV5 == NRFX_ANALOG_INTERNAL_VDDHDIV5) &&
#endif
#else
BUILD_ASSERT((NRF_SAADC_AIN0 == NRF_SAADC_INPUT_AIN0) &&
(NRF_SAADC_AIN1 == NRF_SAADC_INPUT_AIN1) &&
(NRF_SAADC_AIN2 == NRF_SAADC_INPUT_AIN2) &&
(NRF_SAADC_AIN3 == NRF_SAADC_INPUT_AIN3) &&
(NRF_SAADC_AIN4 == NRF_SAADC_INPUT_AIN4) &&
(NRF_SAADC_AIN5 == NRF_SAADC_INPUT_AIN5) &&
(NRF_SAADC_AIN6 == NRF_SAADC_INPUT_AIN6) &&
(NRF_SAADC_AIN7 == NRF_SAADC_INPUT_AIN7) &&
#if defined(SAADC_CH_PSELP_PSELP_VDDHDIV5)
(NRF_SAADC_VDDHDIV5 == NRF_SAADC_INPUT_VDDHDIV5) &&
#endif
#if defined(SAADC_CH_PSELP_PSELP_VDD)
(NRF_SAADC_VDD == NRF_SAADC_INPUT_VDD) &&
#if NRF_SAADC_HAS_INPUT_VDD
(NRF_SAADC_VDD == NRFX_ANALOG_INTERNAL_VDD) &&
#endif
1,
"Definitions from nrf-adc.h do not match those from nrf_saadc.h");
#endif
"Definitions from nrf-saadc.h do not match those from nrfx_analog_common.h");
struct driver_data {
struct adc_context ctx;
@@ -188,96 +117,46 @@ static int acq_time_set(nrf_saadc_channel_config_t *ch_cfg, uint16_t acquisition
return 0;
}
static int input_assign(nrf_saadc_input_t *pin_p,
nrf_saadc_input_t *pin_n,
const struct adc_channel_cfg *channel_cfg)
{
#if (NRF_SAADC_HAS_AIN_AS_PIN)
if (channel_cfg->input_positive > ARRAY_SIZE(saadc_psels) ||
channel_cfg->input_positive < NRF_SAADC_AIN0) {
LOG_ERR("Invalid analog positive input number: %d", channel_cfg->input_positive);
return -EINVAL;
}
*pin_p = saadc_psels[channel_cfg->input_positive];
#if NRF_GPIO_HAS_RETENTION_SETCLEAR
nrf_gpio_pin_retain_disable(saadc_psels[channel_cfg->input_positive]);
#endif
if (channel_cfg->differential) {
if (channel_cfg->input_negative > ARRAY_SIZE(saadc_psels) ||
(IS_ENABLED(CONFIG_NRF_PLATFORM_HALTIUM) &&
(channel_cfg->input_positive > NRF_SAADC_AIN7) !=
(channel_cfg->input_negative > NRF_SAADC_AIN7))) {
LOG_ERR("Invalid analog negative input number: %d",
channel_cfg->input_negative);
return -EINVAL;
}
*pin_n = channel_cfg->input_negative == NRF_SAADC_GND ?
NRF_SAADC_INPUT_DISABLED :
saadc_psels[channel_cfg->input_negative];
#if NRF_GPIO_HAS_RETENTION_SETCLEAR
if (channel_cfg->input_negative != NRF_SAADC_GND) {
nrf_gpio_pin_retain_disable(saadc_psels[channel_cfg->input_negative]);
}
#endif
} else {
*pin_n = NRF_SAADC_INPUT_DISABLED;
}
#else
*pin_p = channel_cfg->input_positive;
*pin_n = (channel_cfg->differential && (channel_cfg->input_negative != NRF_SAADC_GND))
? channel_cfg->input_negative
: NRF_SAADC_INPUT_DISABLED;
#endif
LOG_DBG("ADC positive input: %d", *pin_p);
LOG_DBG("ADC negative input: %d", *pin_n);
return 0;
}
static int gain_set(nrf_saadc_channel_config_t *ch_cfg, enum adc_gain gain)
{
#if NRF_SAADC_HAS_CH_GAIN
switch (gain) {
#if defined(SAADC_CH_CONFIG_GAIN_Gain1_6)
#if NRF_SAADC_HAS_GAIN_1_6
case ADC_GAIN_1_6:
ch_cfg->gain = NRF_SAADC_GAIN1_6;
break;
#endif
#if defined(SAADC_CH_CONFIG_GAIN_Gain1_5)
#if NRF_SAADC_HAS_GAIN_1_5
case ADC_GAIN_1_5:
ch_cfg->gain = NRF_SAADC_GAIN1_5;
break;
#endif
#if defined(SAADC_CH_CONFIG_GAIN_Gain1_4) || defined(SAADC_CH_CONFIG_GAIN_Gain2_8)
#if NRF_SAADC_HAS_GAIN_1_4
case ADC_GAIN_1_4:
ch_cfg->gain = NRF_SAADC_GAIN1_4;
break;
#endif
#if defined(SAADC_CH_CONFIG_GAIN_Gain2_7)
#if NRF_SAADC_HAS_GAIN_2_7
case ADC_GAIN_2_7:
ch_cfg->gain = NRF_SAADC_GAIN2_7;
break;
#endif
#if defined(SAADC_CH_CONFIG_GAIN_Gain1_3) || defined(SAADC_CH_CONFIG_GAIN_Gain2_6)
#if NRF_SAADC_HAS_GAIN_1_3
case ADC_GAIN_1_3:
ch_cfg->gain = NRF_SAADC_GAIN1_3;
break;
#endif
#if defined(SAADC_CH_CONFIG_GAIN_Gain2_5)
#if NRF_SAADC_HAS_GAIN_2_5
case ADC_GAIN_2_5:
ch_cfg->gain = NRF_SAADC_GAIN2_5;
break;
#endif
#if defined(SAADC_CH_CONFIG_GAIN_Gain1_2) || defined(SAADC_CH_CONFIG_GAIN_Gain2_4)
#if NRF_SAADC_HAS_GAIN_1_2
case ADC_GAIN_1_2:
ch_cfg->gain = NRF_SAADC_GAIN1_2;
break;
#endif
#if defined(SAADC_CH_CONFIG_GAIN_Gain2_3)
#if NRF_SAADC_HAS_GAIN_2_3
case ADC_GAIN_2_3:
ch_cfg->gain = NRF_SAADC_GAIN2_3;
break;
@@ -288,7 +167,7 @@ static int gain_set(nrf_saadc_channel_config_t *ch_cfg, enum adc_gain gain)
case ADC_GAIN_2:
ch_cfg->gain = NRF_SAADC_GAIN2;
break;
#if defined(SAADC_CH_CONFIG_GAIN_Gain4)
#if NRF_SAADC_HAS_GAIN_4
case ADC_GAIN_4:
ch_cfg->gain = NRF_SAADC_GAIN4;
break;
@@ -296,7 +175,7 @@ static int gain_set(nrf_saadc_channel_config_t *ch_cfg, enum adc_gain gain)
default:
#else
if (gain != ADC_GAIN_1) {
#endif /* defined(NRF_SAADC_HAS_CH_GAIN) */
#endif /* NRF_SAADC_HAS_CH_GAIN */
LOG_ERR("Selected ADC gain is not valid");
return -EINVAL;
}
@@ -307,17 +186,17 @@ static int gain_set(nrf_saadc_channel_config_t *ch_cfg, enum adc_gain gain)
static int reference_set(nrf_saadc_channel_config_t *ch_cfg, enum adc_reference reference)
{
switch (reference) {
#if defined(SAADC_CH_CONFIG_REFSEL_Internal)
#if NRF_SAADC_HAS_REFERENCE_INTERNAL
case ADC_REF_INTERNAL:
ch_cfg->reference = NRF_SAADC_REFERENCE_INTERNAL;
break;
#endif
#if defined(SAADC_CH_CONFIG_REFSEL_VDD1_4)
#if NRF_SAADC_HAS_REFERENCE_VDD4
case ADC_REF_VDD_1_4:
ch_cfg->reference = NRF_SAADC_REFERENCE_VDD4;
break;
#endif
#if defined(SAADC_CH_CONFIG_REFSEL_External)
#if NRF_SAADC_HAS_REFERENCE_EXTERNAL
case ADC_REF_EXTERNAL0:
ch_cfg->reference = NRF_SAADC_REFERENCE_EXTERNAL;
break;
@@ -347,6 +226,11 @@ static int adc_nrfx_channel_setup(const struct device *dev,
#endif
},
.channel_index = channel_cfg->channel_id,
.pin_p = channel_cfg->input_positive,
.pin_n = (channel_cfg->differential &&
(channel_cfg->input_negative != NRF_SAADC_GND))
? channel_cfg->input_negative
: NRF_SAADC_AIN_DISABLED,
};
if (channel_cfg->channel_id >= SAADC_CH_NUM) {
@@ -356,11 +240,6 @@ static int adc_nrfx_channel_setup(const struct device *dev,
ch_cfg = &cfg.channel_config;
err = input_assign(&cfg.pin_p, &cfg.pin_n, channel_cfg);
if (err != 0) {
return err;
}
err = gain_set(ch_cfg, channel_cfg->gain);
if (err != 0) {
return err;
@@ -394,11 +273,11 @@ static int adc_nrfx_channel_setup(const struct device *dev,
m_data.divide_single_ended_value &= ~BIT(channel_cfg->channel_id);
}
nrfx_err_t ret = nrfx_saadc_channel_config(&cfg);
err = nrfx_saadc_channel_config(&cfg);
if (ret != NRFX_SUCCESS) {
LOG_ERR("Cannot configure channel %d: 0x%08x", channel_cfg->channel_id, ret);
return -EINVAL;
if (err != 0) {
LOG_ERR("Cannot configure channel %d: %d", channel_cfg->channel_id, err);
return err;
}
return 0;
@@ -409,10 +288,10 @@ static void adc_context_start_sampling(struct adc_context *ctx)
if (ctx->sequence.calibrate) {
nrfx_saadc_offset_calibrate(event_handler);
} else {
nrfx_err_t ret = nrfx_saadc_mode_trigger();
int ret = nrfx_saadc_mode_trigger();
if (ret != NRFX_SUCCESS) {
LOG_ERR("Cannot start sampling: 0x%08x", ret);
if (ret != 0) {
LOG_ERR("Cannot start sampling: %d", ret);
adc_context_complete(ctx, -EIO);
}
}
@@ -437,10 +316,9 @@ static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repe
return;
}
nrfx_err_t nrfx_err =
nrfx_saadc_buffer_set(samples_buffer, m_data.active_channel_cnt);
if (nrfx_err != NRFX_SUCCESS) {
LOG_ERR("Failed to set buffer: 0x%08x", nrfx_err);
error = nrfx_saadc_buffer_set(samples_buffer, m_data.active_channel_cnt);
if (error != 0) {
LOG_ERR("Failed to set buffer: %d", error);
adc_context_complete(ctx, -EIO);
}
}
@@ -451,10 +329,10 @@ static inline void adc_context_enable_timer(struct adc_context *ctx)
if (!m_data.internal_timer_enabled) {
k_timer_start(&m_data.timer, K_NO_WAIT, K_USEC(ctx->options.interval_us));
} else {
nrfx_err_t ret = nrfx_saadc_mode_trigger();
int ret = nrfx_saadc_mode_trigger();
if (ret != NRFX_SUCCESS) {
LOG_ERR("Cannot start sampling: 0x%08x", ret);
if (ret != 0) {
LOG_ERR("Cannot start sampling: %d", ret);
adc_context_complete(&m_data.ctx, -EIO);
}
}
@@ -624,7 +502,6 @@ static inline uint16_t interval_to_cc(uint16_t interval_us)
static int start_read(const struct device *dev,
const struct adc_sequence *sequence)
{
nrfx_err_t nrfx_err;
int error;
uint32_t selected_channels = sequence->channels;
nrf_saadc_resolution_t resolution;
@@ -682,21 +559,21 @@ static int start_read(const struct device *dev,
m_data.internal_timer_enabled = true;
nrfx_err = nrfx_saadc_advanced_mode_set(selected_channels, resolution, &adv_config,
event_handler);
error = nrfx_saadc_advanced_mode_set(selected_channels, resolution, &adv_config,
event_handler);
} else {
m_data.internal_timer_enabled = false;
nrfx_err = nrfx_saadc_simple_mode_set(selected_channels, resolution, oversampling,
event_handler);
error = nrfx_saadc_simple_mode_set(selected_channels, resolution, oversampling,
event_handler);
}
if (nrfx_err != NRFX_SUCCESS) {
return -EINVAL;
if (error != 0) {
return error;
}
error = check_buffer_size(sequence, active_channel_cnt);
if (error) {
if (error != 0) {
return error;
}
@@ -717,14 +594,13 @@ static int start_read(const struct device *dev,
/* Buffer is filled in chunks, each chunk composed of number of samples equal to number
* of active channels. Buffer pointer is advanced and reloaded after each chunk.
*/
nrfx_err = nrfx_saadc_buffer_set(
samples_buffer,
(m_data.internal_timer_enabled
? (1 + sequence->options->extra_samplings)
: active_channel_cnt));
if (nrfx_err != NRFX_SUCCESS) {
LOG_ERR("Failed to set buffer: 0x%08x", nrfx_err);
return -EINVAL;
error = nrfx_saadc_buffer_set(samples_buffer,
(m_data.internal_timer_enabled
? (1 + sequence->options->extra_samplings)
: active_channel_cnt));
if (error != 0) {
LOG_ERR("Failed to set buffer: %d", error);
return error;
}
adc_context_start_read(&m_data.ctx, sequence);
@@ -772,7 +648,7 @@ static int adc_nrfx_read_async(const struct device *dev,
static void event_handler(const nrfx_saadc_evt_t *event)
{
nrfx_err_t err;
int err;
if (event->type == NRFX_SAADC_EVT_DONE) {
dmm_buffer_in_release(
@@ -791,8 +667,8 @@ static void event_handler(const nrfx_saadc_evt_t *event)
adc_context_on_sampling_done(&m_data.ctx, DEVICE_DT_INST_GET(0));
} else if (event->type == NRFX_SAADC_EVT_CALIBRATEDONE) {
err = nrfx_saadc_mode_trigger();
if (err != NRFX_SUCCESS) {
LOG_ERR("Cannot start sampling: 0x%08x", err);
if (err != 0) {
LOG_ERR("Cannot start sampling: %d", err);
adc_context_complete(&m_data.ctx, -EIO);
}
} else if (event->type == NRFX_SAADC_EVT_FINISHED) {
@@ -809,13 +685,13 @@ static int saadc_pm_handler(const struct device *dev, enum pm_device_action acti
static int init_saadc(const struct device *dev)
{
nrfx_err_t err;
int err;
k_timer_init(&m_data.timer, external_timer_expired_handler, NULL);
/* The priority value passed here is ignored (see nrfx_glue.h). */
err = nrfx_saadc_init(0);
if (err != NRFX_SUCCESS) {
if (err != 0) {
LOG_ERR("Failed to initialize device: %s", dev->name);
return -EIO;
}
@@ -833,38 +709,9 @@ static DEVICE_API(adc, adc_nrfx_driver_api) = {
#ifdef CONFIG_ADC_ASYNC
.read_async = adc_nrfx_read_async,
#endif
#if defined(NRF54LV10A_ENGA_XXAA)
.ref_internal = 1300,
#elif defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
.ref_internal = 900,
#elif defined(CONFIG_NRF_PLATFORM_HALTIUM)
.ref_internal = 1024,
#else
.ref_internal = 600,
#endif
.ref_internal = NRFX_SAADC_REF_INTERNAL_VALUE,
};
#if defined(CONFIG_NRF_PLATFORM_HALTIUM)
/* AIN8-AIN14 inputs are on 3v3 GPIO port and they cannot be mixed with other
* analog inputs (from 1v8 ports) in differential mode.
*/
#define CH_IS_3V3(val) (val >= NRF_SAADC_AIN8)
#define MIXED_3V3_1V8_INPUTS(node) \
(DT_NODE_HAS_PROP(node, zephyr_input_negative) && \
(CH_IS_3V3(DT_PROP_OR(node, zephyr_input_negative, 0)) != \
CH_IS_3V3(DT_PROP_OR(node, zephyr_input_positive, 0))))
#else
#define MIXED_3V3_1V8_INPUTS(node) false
#endif
#define VALIDATE_CHANNEL_CONFIG(node) \
BUILD_ASSERT(MIXED_3V3_1V8_INPUTS(node) == false, \
"1v8 inputs cannot be mixed with 3v3 inputs");
/* Validate configuration of all channels. */
DT_FOREACH_CHILD(DT_DRV_INST(0), VALIDATE_CHANNEL_CONFIG)
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(DT_DRV_INST(0));
PM_DEVICE_DT_INST_DEFINE(0, saadc_pm_handler);

4
drivers/audio/Kconfig.dmic_pdm_nrfx
View File

@@ -5,9 +5,7 @@ config AUDIO_DMIC_NRFX_PDM
bool "nRF PDM nrfx driver"
default y
depends on DT_HAS_NORDIC_NRF_PDM_ENABLED
select NRFX_PDM0 if HAS_HW_NRF_PDM0
select NRFX_PDM20 if HAS_HW_NRF_PDM20
select NRFX_PDM21 if HAS_HW_NRF_PDM21
select NRFX_PDM
select PINCTRL
help
Enable support for nrfx PDM driver for nRF MCU series.

393
drivers/audio/dmic_nrfx_pdm.c
View File

@@ -4,6 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_pdm
#include <zephyr/audio/dmic.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <zephyr/drivers/pinctrl.h>
@@ -21,7 +23,6 @@ LOG_MODULE_REGISTER(dmic_nrfx_pdm, CONFIG_AUDIO_DMIC_LOG_LEVEL);
#if CONFIG_SOC_SERIES_NRF54HX
#define DMIC_NRFX_CLOCK_FREQ MHZ(16)
#define DMIC_NRFX_CLOCK_FACTOR 8192
#define DMIC_NRFX_AUDIO_CLOCK_FREQ DT_PROP_OR(NODE_AUDIOPLL, frequency, 0)
#elif DT_NODE_HAS_STATUS_OKAY(NODE_AUDIO_AUXPLL)
#define AUXPLL_FREQUENCY_SETTING DT_PROP(NODE_AUDIO_AUXPLL, nordic_frequency)
@@ -35,13 +36,12 @@ BUILD_ASSERT((AUXPLL_FREQUENCY_SETTING == NRF_AUXPLL_FREQ_DIV_AUDIO_48K) ||
#else
#define DMIC_NRFX_CLOCK_FREQ MHZ(32)
#define DMIC_NRFX_CLOCK_FACTOR 4096
#define DMIC_NRFX_AUDIO_CLOCK_FREQ DT_PROP_OR(DT_NODELABEL(aclk), clock_frequency, \
DT_PROP_OR(DT_NODELABEL(clock), hfclkaudio_frequency, 0))
#endif
struct dmic_nrfx_pdm_drv_data {
const nrfx_pdm_t *pdm;
nrfx_pdm_t pdm;
#if CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL || DT_NODE_HAS_STATUS_OKAY(NODE_AUDIO_AUXPLL)
const struct device *audiopll_dev;
#elif CONFIG_CLOCK_CONTROL_NRF
@@ -79,7 +79,7 @@ static void free_buffer(struct dmic_nrfx_pdm_drv_data *drv_data, void *buffer)
static void stop_pdm(struct dmic_nrfx_pdm_drv_data *drv_data)
{
drv_data->stopping = true;
nrfx_pdm_stop(drv_data->pdm);
nrfx_pdm_stop(&drv_data->pdm);
}
static int request_clock(struct dmic_nrfx_pdm_drv_data *drv_data)
@@ -120,7 +120,7 @@ static void event_handler(const struct device *dev, const nrfx_pdm_evt_t *evt)
if (evt->buffer_requested) {
void *buffer;
nrfx_err_t err;
int err;
ret = k_mem_slab_alloc(drv_data->mem_slab, &mem_slab_buffer, K_NO_WAIT);
if (ret < 0) {
@@ -142,9 +142,9 @@ static void event_handler(const struct device *dev, const nrfx_pdm_evt_t *evt)
stop_pdm(drv_data);
return;
}
err = nrfx_pdm_buffer_set(drv_data->pdm, buffer, drv_data->block_size / 2);
if (err != NRFX_SUCCESS) {
LOG_ERR("Failed to set buffer: 0x%08x", err);
err = nrfx_pdm_buffer_set(&drv_data->pdm, buffer, drv_data->block_size / 2);
if (err != 0) {
LOG_ERR("Failed to set buffer: %d", err);
stop = true;
}
}
@@ -206,220 +206,6 @@ static void event_handler(const struct device *dev, const nrfx_pdm_evt_t *evt)
}
}
static bool is_in_freq_range(uint32_t freq, const struct dmic_cfg *pdm_cfg)
{
return freq >= pdm_cfg->io.min_pdm_clk_freq && freq <= pdm_cfg->io.max_pdm_clk_freq;
}
static bool is_better(uint32_t freq,
uint8_t ratio,
uint32_t req_rate,
uint32_t *best_diff,
uint32_t *best_rate,
uint32_t *best_freq)
{
uint32_t act_rate = freq / ratio;
uint32_t diff = act_rate >= req_rate ? (act_rate - req_rate)
: (req_rate - act_rate);
LOG_DBG("Freq %u, ratio %u, act_rate %u", freq, ratio, act_rate);
if (diff < *best_diff) {
*best_diff = diff;
*best_rate = act_rate;
*best_freq = freq;
return true;
}
return false;
}
static bool check_pdm_frequencies(const struct dmic_nrfx_pdm_drv_cfg *drv_cfg,
nrfx_pdm_config_t *config,
const struct dmic_cfg *pdm_cfg,
uint8_t ratio,
uint32_t *best_diff,
uint32_t *best_rate,
uint32_t *best_freq)
{
uint32_t req_rate = pdm_cfg->streams[0].pcm_rate;
bool better_found = false;
const uint32_t src_freq =
(NRF_PDM_HAS_SELECTABLE_CLOCK && drv_cfg->clk_src == ACLK)
? DMIC_NRFX_AUDIO_CLOCK_FREQ
: DMIC_NRFX_CLOCK_FREQ;
#if NRF_PDM_HAS_PRESCALER
uint32_t req_freq = req_rate * ratio;
uint32_t prescaler = src_freq / req_freq;
uint32_t act_freq = src_freq / prescaler;
if (is_in_freq_range(act_freq, pdm_cfg) &&
is_better(act_freq, ratio, req_rate, best_diff, best_rate, best_freq)) {
config->prescaler = prescaler;
better_found = true;
}
/* Stop if an exact rate match is found. */
if (*best_diff == 0) {
return true;
}
/* Prescaler value is rounded down by default,
* thus value rounded up should be checked as well.
*/
prescaler += 1;
act_freq = src_freq / prescaler;
if (is_in_freq_range(act_freq, pdm_cfg) &&
is_better(act_freq, ratio, req_rate, best_diff, best_rate, best_freq)) {
config->prescaler = prescaler;
better_found = true;
}
#else
if (IS_ENABLED(CONFIG_SOC_SERIES_NRF53X) || IS_ENABLED(CONFIG_SOC_SERIES_NRF54HX)) {
uint32_t req_freq = req_rate * ratio;
/* As specified in the nRF5340 PS:
*
* PDMCLKCTRL = 4096 * floor(f_pdm * 1048576 /
* (f_source + f_pdm / 2))
* f_actual = f_source / floor(1048576 * 4096 / PDMCLKCTRL)
*/
uint32_t clk_factor = (uint32_t)((req_freq * 1048576ULL) /
(src_freq + req_freq / 2));
uint32_t act_freq = src_freq / (1048576 / clk_factor);
if (is_in_freq_range(act_freq, pdm_cfg) &&
is_better(act_freq, ratio, req_rate, best_diff, best_rate, best_freq)) {
config->clock_freq = clk_factor * DMIC_NRFX_CLOCK_FACTOR;
better_found = true;
}
} else { /* -> !IS_ENABLED(CONFIG_SOC_SERIES_NRF53X)) */
static const struct {
uint32_t freq_val;
nrf_pdm_freq_t freq_enum;
} freqs[] = {
{ 1000000, NRF_PDM_FREQ_1000K },
{ 1032000, NRF_PDM_FREQ_1032K },
{ 1067000, NRF_PDM_FREQ_1067K },
#if defined(PDM_PDMCLKCTRL_FREQ_1231K)
{ 1231000, NRF_PDM_FREQ_1231K },
#endif
#if defined(PDM_PDMCLKCTRL_FREQ_1280K)
{ 1280000, NRF_PDM_FREQ_1280K },
#endif
#if defined(PDM_PDMCLKCTRL_FREQ_1333K)
{ 1333000, NRF_PDM_FREQ_1333K }
#endif
};
for (int i = 0; i < ARRAY_SIZE(freqs); ++i) {
uint32_t freq_val = freqs[i].freq_val;
if (freq_val < pdm_cfg->io.min_pdm_clk_freq) {
continue;
}
if (freq_val > pdm_cfg->io.max_pdm_clk_freq) {
break;
}
if (is_better(freq_val, ratio, req_rate,
best_diff, best_rate, best_freq)) {
config->clock_freq = freqs[i].freq_enum;
/* Stop if an exact rate match is found. */
if (*best_diff == 0) {
return true;
}
better_found = true;
}
/* Since frequencies are in ascending order, stop
* checking next ones for the current ratio after
* resulting PCM rate goes above the one requested.
*/
if ((freq_val / ratio) > req_rate) {
break;
}
}
}
#endif /* NRF_PDM_HAS_PRESCALER */
return better_found;
}
/* Finds clock settings that give the PCM output rate closest to that requested,
* taking into account the hardware limitations.
*/
static bool find_suitable_clock(const struct dmic_nrfx_pdm_drv_cfg *drv_cfg,
nrfx_pdm_config_t *config,
const struct dmic_cfg *pdm_cfg)
{
uint32_t best_diff = UINT32_MAX;
uint32_t best_rate;
uint32_t best_freq;
#if NRF_PDM_HAS_RATIO_CONFIG
static const struct {
uint8_t ratio_val;
nrf_pdm_ratio_t ratio_enum;
} ratios[] = {
#if defined(PDM_RATIO_RATIO_Ratio32)
{ 32, NRF_PDM_RATIO_32X },
#endif
#if defined(PDM_RATIO_RATIO_Ratio48)
{ 48, NRF_PDM_RATIO_48X },
#endif
#if defined(PDM_RATIO_RATIO_Ratio50)
{ 50, NRF_PDM_RATIO_50X },
#endif
{ 64, NRF_PDM_RATIO_64X },
{ 80, NRF_PDM_RATIO_80X },
#if defined(PDM_RATIO_RATIO_Ratio96)
{ 96, NRF_PDM_RATIO_96X },
#endif
#if defined(PDM_RATIO_RATIO_Ratio100)
{ 100, NRF_PDM_RATIO_100X },
#endif
#if defined(PDM_RATIO_RATIO_Ratio128)
{ 128, NRF_PDM_RATIO_128X }
#endif
};
for (int r = 0; best_diff != 0 && r < ARRAY_SIZE(ratios); ++r) {
uint8_t ratio = ratios[r].ratio_val;
if (check_pdm_frequencies(drv_cfg, config, pdm_cfg, ratio,
&best_diff, &best_rate, &best_freq)) {
config->ratio = ratios[r].ratio_enum;
/* Look no further if a configuration giving the exact
* PCM rate is found.
*/
if (best_diff == 0) {
break;
}
}
}
#else
uint8_t ratio = 64;
(void)check_pdm_frequencies(drv_cfg, config, pdm_cfg, ratio,
&best_diff, &best_rate, &best_freq);
#endif
if (best_diff == UINT32_MAX) {
return false;
}
LOG_INF("PDM clock frequency: %u, actual PCM rate: %u",
best_freq, best_rate);
return true;
}
static int dmic_nrfx_pdm_configure(const struct device *dev,
struct dmic_cfg *config)
{
@@ -429,7 +215,7 @@ static int dmic_nrfx_pdm_configure(const struct device *dev,
struct pcm_stream_cfg *stream = &config->streams[0];
uint32_t def_map, alt_map;
nrfx_pdm_config_t nrfx_cfg;
nrfx_err_t err;
int err;
if (drv_data->active) {
LOG_ERR("Cannot configure device while it is active");
@@ -475,7 +261,7 @@ static int dmic_nrfx_pdm_configure(const struct device *dev,
/* If either rate or width is 0, the stream is to be disabled. */
if (stream->pcm_rate == 0 || stream->pcm_width == 0) {
if (drv_data->configured) {
nrfx_pdm_uninit(drv_data->pdm);
nrfx_pdm_uninit(&drv_data->pdm);
drv_data->configured = false;
}
@@ -503,19 +289,28 @@ static int dmic_nrfx_pdm_configure(const struct device *dev,
? NRF_PDM_MCLKSRC_ACLK
: NRF_PDM_MCLKSRC_PCLK32M;
#endif
if (!find_suitable_clock(drv_cfg, &nrfx_cfg, config)) {
nrfx_pdm_output_t output_config = {
.base_clock_freq = (NRF_PDM_HAS_SELECTABLE_CLOCK && drv_cfg->clk_src == ACLK)
? DMIC_NRFX_AUDIO_CLOCK_FREQ
: DMIC_NRFX_CLOCK_FREQ,
.sampling_rate = config->streams[0].pcm_rate,
.output_freq_min = config->io.min_pdm_clk_freq,
.output_freq_max = config->io.max_pdm_clk_freq
};
if (nrfx_pdm_prescalers_calc(&output_config, &nrfx_cfg.prescalers) != 0) {
LOG_ERR("Cannot find suitable PDM clock configuration.");
return -EINVAL;
}
if (drv_data->configured) {
nrfx_pdm_uninit(drv_data->pdm);
nrfx_pdm_uninit(&drv_data->pdm);
drv_data->configured = false;
}
err = nrfx_pdm_init(drv_data->pdm, &nrfx_cfg, drv_cfg->event_handler);
if (err != NRFX_SUCCESS) {
LOG_ERR("Failed to initialize PDM: 0x%08x", err);
err = nrfx_pdm_init(&drv_data->pdm, &nrfx_cfg, drv_cfg->event_handler);
if (err != 0) {
LOG_ERR("Failed to initialize PDM: %d", err);
return -EIO;
}
@@ -536,15 +331,15 @@ static int dmic_nrfx_pdm_configure(const struct device *dev,
static int start_transfer(struct dmic_nrfx_pdm_drv_data *drv_data)
{
nrfx_err_t err;
int err;
int ret;
err = nrfx_pdm_start(drv_data->pdm);
if (err == NRFX_SUCCESS) {
err = nrfx_pdm_start(&drv_data->pdm);
if (err == 0) {
return 0;
}
LOG_ERR("Failed to start PDM: 0x%08x", err);
LOG_ERR("Failed to start PDM: %d", err);
ret = -EIO;
ret = release_clock(drv_data);
@@ -621,7 +416,7 @@ static int dmic_nrfx_pdm_trigger(const struct device *dev,
case DMIC_TRIGGER_STOP:
if (drv_data->active) {
drv_data->stopping = true;
nrfx_pdm_stop(drv_data->pdm);
nrfx_pdm_stop(&drv_data->pdm);
}
break;
@@ -704,80 +499,60 @@ static const struct _dmic_ops dmic_ops = {
.read = dmic_nrfx_pdm_read,
};
#define PDM(idx) DT_NODELABEL(pdm##idx)
#define PDM_CLK_SRC(idx) DT_STRING_TOKEN(PDM(idx), clock_source)
#define PDM_CLK_SRC(inst) DT_STRING_TOKEN(DT_DRV_INST(inst), clock_source)
#define PDM_NRFX_DEVICE(idx) \
static void *rx_msgs##idx[DT_PROP(PDM(idx), queue_size)]; \
static void *mem_slab_msgs##idx[DT_PROP(PDM(idx), queue_size)]; \
static struct dmic_nrfx_pdm_drv_data dmic_nrfx_pdm_data##idx; \
static const nrfx_pdm_t dmic_nrfx_pdm##idx = NRFX_PDM_INSTANCE(idx); \
static int pdm_nrfx_init##idx(const struct device *dev) \
{ \
IRQ_CONNECT(DT_IRQN(PDM(idx)), DT_IRQ(PDM(idx), priority), \
nrfx_isr, nrfx_pdm_##idx##_irq_handler, 0); \
const struct dmic_nrfx_pdm_drv_cfg *drv_cfg = dev->config; \
int err = pinctrl_apply_state(drv_cfg->pcfg, \
PINCTRL_STATE_DEFAULT); \
if (err < 0) { \
return err; \
} \
dmic_nrfx_pdm_data##idx.pdm = &dmic_nrfx_pdm##idx; \
k_msgq_init(&dmic_nrfx_pdm_data##idx.rx_queue, \
(char *)rx_msgs##idx, sizeof(void *), \
ARRAY_SIZE(rx_msgs##idx)); \
k_msgq_init(&dmic_nrfx_pdm_data##idx.mem_slab_queue, \
(char *)mem_slab_msgs##idx, sizeof(void *), \
ARRAY_SIZE(mem_slab_msgs##idx)); \
init_clock_manager(dev); \
return 0; \
} \
static void event_handler##idx(const nrfx_pdm_evt_t *evt) \
{ \
event_handler(DEVICE_DT_GET(PDM(idx)), evt); \
} \
PINCTRL_DT_DEFINE(PDM(idx)); \
static const struct dmic_nrfx_pdm_drv_cfg dmic_nrfx_pdm_cfg##idx = { \
.event_handler = event_handler##idx, \
.nrfx_def_cfg = NRFX_PDM_DEFAULT_CONFIG(0, 0), \
.nrfx_def_cfg.skip_gpio_cfg = true, \
.nrfx_def_cfg.skip_psel_cfg = true, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(PDM(idx)), \
.clk_src = PDM_CLK_SRC(idx), \
.mem_reg = DMM_DEV_TO_REG(PDM(idx)), \
}; \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(PDM(idx)); \
BUILD_ASSERT(PDM_CLK_SRC(idx) != ACLK || \
NRF_PDM_HAS_SELECTABLE_CLOCK, \
"Clock source ACLK is not available."); \
BUILD_ASSERT(PDM_CLK_SRC(idx) != ACLK || \
DT_NODE_HAS_PROP(DT_NODELABEL(clock), \
hfclkaudio_frequency) || \
DT_NODE_HAS_PROP(DT_NODELABEL(aclk), \
clock_frequency) || \
DT_NODE_HAS_PROP(NODE_AUDIOPLL, \
frequency) || \
DT_NODE_HAS_PROP(NODE_AUDIO_AUXPLL, \
nordic_frequency), \
"Clock source ACLK requires one following defined frequency "\
"properties: " \
"hfclkaudio-frequency in the nordic,nrf-clock node, " \
"clock-frequency in the aclk node, " \
"frequency in the audiopll node, " \
"nordic-frequency in the audio_auxpll node"); \
DEVICE_DT_DEFINE(PDM(idx), pdm_nrfx_init##idx, NULL, \
&dmic_nrfx_pdm_data##idx, &dmic_nrfx_pdm_cfg##idx, \
POST_KERNEL, CONFIG_AUDIO_DMIC_INIT_PRIORITY, \
&dmic_ops);
#define PDM_NRFX_DEVICE(inst) \
static void *rx_msgs##inst[DT_INST_PROP(inst, queue_size)]; \
static void *mem_slab_msgs##inst[DT_INST_PROP(inst, queue_size)]; \
static struct dmic_nrfx_pdm_drv_data dmic_nrfx_pdm_data##inst = { \
.pdm = NRFX_PDM_INSTANCE(DT_INST_REG_ADDR(inst)), \
}; \
static int pdm_nrfx_init##inst(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), nrfx_pdm_irq_handler, \
&dmic_nrfx_pdm_data##inst.pdm, 0); \
const struct dmic_nrfx_pdm_drv_cfg *drv_cfg = dev->config; \
int err = pinctrl_apply_state(drv_cfg->pcfg, PINCTRL_STATE_DEFAULT); \
if (err < 0) { \
return err; \
} \
k_msgq_init(&dmic_nrfx_pdm_data##inst.rx_queue, (char *)rx_msgs##inst, \
sizeof(void *), ARRAY_SIZE(rx_msgs##inst)); \
k_msgq_init(&dmic_nrfx_pdm_data##inst.mem_slab_queue, (char *)mem_slab_msgs##inst, \
sizeof(void *), ARRAY_SIZE(mem_slab_msgs##inst)); \
init_clock_manager(dev); \
return 0; \
} \
static void event_handler##inst(const nrfx_pdm_evt_t *evt) \
{ \
event_handler(DEVICE_DT_INST_GET(inst), evt); \
} \
PINCTRL_DT_INST_DEFINE(inst); \
static const struct dmic_nrfx_pdm_drv_cfg dmic_nrfx_pdm_cfg##inst = { \
.event_handler = event_handler##inst, \
.nrfx_def_cfg = NRFX_PDM_DEFAULT_CONFIG(0, 0), \
.nrfx_def_cfg.skip_gpio_cfg = true, \
.nrfx_def_cfg.skip_psel_cfg = true, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.clk_src = PDM_CLK_SRC(inst), \
.mem_reg = DMM_DEV_TO_REG(DT_DRV_INST(inst)), \
}; \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(DT_DRV_INST(inst)); \
BUILD_ASSERT(PDM_CLK_SRC(inst) != ACLK || NRF_PDM_HAS_SELECTABLE_CLOCK, \
"Clock source ACLK is not available."); \
BUILD_ASSERT(PDM_CLK_SRC(inst) != ACLK || \
DT_NODE_HAS_PROP(DT_NODELABEL(clock), hfclkaudio_frequency) || \
DT_NODE_HAS_PROP(DT_NODELABEL(aclk), clock_frequency) || \
DT_NODE_HAS_PROP(NODE_AUDIOPLL, frequency) || \
DT_NODE_HAS_PROP(NODE_AUDIO_AUXPLL, nordic_frequency), \
"Clock source ACLK requires one following defined frequency " \
"properties: " \
"hfclkaudio-frequency in the nordic,nrf-clock node, " \
"clock-frequency in the aclk node, " \
"frequency in the audiopll node, " \
"nordic-frequency in the audio_auxpll node"); \
DEVICE_DT_INST_DEFINE(inst, pdm_nrfx_init##inst, NULL, &dmic_nrfx_pdm_data##inst, \
&dmic_nrfx_pdm_cfg##inst, POST_KERNEL, \
CONFIG_AUDIO_DMIC_INIT_PRIORITY, &dmic_ops);
#ifdef CONFIG_HAS_HW_NRF_PDM0
PDM_NRFX_DEVICE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_PDM20
PDM_NRFX_DEVICE(20);
#endif
#ifdef CONFIG_HAS_HW_NRF_PDM21
PDM_NRFX_DEVICE(21);
#endif
DT_INST_FOREACH_STATUS_OKAY(PDM_NRFX_DEVICE)

9
drivers/clock_control/clock_control_nrf.c
View File

@@ -14,7 +14,6 @@
#include <zephyr/logging/log.h>
#include <zephyr/shell/shell.h>
#include <zephyr/irq.h>
#include <nrf_erratas.h>
LOG_MODULE_REGISTER(clock_control, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
@@ -317,7 +316,7 @@ static void hfclk_start(void)
hf_start_tstamp = k_uptime_get();
}
nrfx_clock_hfclk_start();
nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
}
static void hfclk_stop(void)
@@ -326,7 +325,7 @@ static void hfclk_stop(void)
hf_stop_tstamp = k_uptime_get();
}
nrfx_clock_hfclk_stop();
nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
}
#if NRF_CLOCK_HAS_HFCLK24M
@@ -797,7 +796,6 @@ static void hfclkaudio_init(void)
static int clk_init(const struct device *dev)
{
nrfx_err_t nrfx_err;
int err;
static const struct onoff_transitions transitions = {
.start = onoff_start,
@@ -811,8 +809,7 @@ static int clk_init(const struct device *dev)
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
nrfx_isr, nrfx_power_clock_irq_handler, 0);
nrfx_err = nrfx_clock_init(clock_event_handler);
if (nrfx_err != NRFX_SUCCESS) {
if (nrfx_clock_init(clock_event_handler) != 0) {
return -EIO;
}

53
drivers/comparator/comparator_nrf_common.h
View File

@@ -1,53 +0,0 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_COMPARATOR_NRF_COMMON_H_
#define ZEPHYR_DRIVERS_COMPARATOR_NRF_COMMON_H_
#include <nrfx.h>
#if (NRF_COMP_HAS_AIN_AS_PIN || NRF_LPCOMP_HAS_AIN_AS_PIN)
static const uint32_t shim_nrf_comp_ain_map[] = {
#if defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280)
NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(1U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(2U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(3U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1),
#elif defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15)
NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(11U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(13U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(14U, 1),
#elif defined(NRF54LM20A_ENGA_XXAA)
NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(31U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(30U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(29U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(3U, 1),
#elif defined(NRF54LV10A_ENGA_XXAA)
NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(1U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(2U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(3U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(10U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(11U, 1),
NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1),
#endif
};
#endif
#endif /* ZEPHYR_DRIVERS_COMPARATOR_NRF_COMMON_H_ */

281
drivers/comparator/comparator_nrf_comp.c
View File

@@ -10,7 +10,6 @@
#include <zephyr/drivers/comparator/nrf_comp.h>
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include "comparator_nrf_common.h"
#define DT_DRV_COMPAT nordic_nrf_comp
@@ -45,20 +44,6 @@
#define SHIM_NRF_COMP_DT_INST_PSEL(inst) DT_INST_PROP(inst, psel)
#if defined(COMP_HYST_HYST_Hyst40mV)
#define NRF_COMP_HYST_ENABLED NRF_COMP_HYST_40MV
#elif defined(COMP_HYST_HYST_Hyst50mV)
#define NRF_COMP_HYST_ENABLED NRF_COMP_HYST_50MV
#endif
#define NRF_COMP_HYST_DISABLED NRF_COMP_HYST_NO_HYST
#if defined(NRF_COMP_HYST_ENABLED)
#define NRF_COMP_HAS_HYST 1
#else
#define NRF_COMP_HAS_HYST 0
#endif
struct shim_nrf_comp_data {
uint32_t event_mask;
bool started;
@@ -72,84 +57,41 @@ BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_TH_DOWN(0) < 64);
BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_TH_UP(0) < 64);
#endif
#if (NRF_COMP_HAS_AIN_AS_PIN)
BUILD_ASSERT(NRF_COMP_AIN0 == 0);
BUILD_ASSERT(NRF_COMP_AIN7 == 7);
#else
BUILD_ASSERT((NRF_COMP_AIN0 == NRF_COMP_INPUT_0) &&
(NRF_COMP_AIN1 == NRF_COMP_INPUT_1) &&
(NRF_COMP_AIN2 == NRF_COMP_INPUT_2) &&
(NRF_COMP_AIN3 == NRF_COMP_INPUT_3) &&
#if defined(COMP_PSEL_PSEL_AnalogInput4)
(NRF_COMP_AIN4 == NRF_COMP_INPUT_4) &&
BUILD_ASSERT((NRF_COMP_AIN0 == NRFX_ANALOG_EXTERNAL_AIN0) &&
(NRF_COMP_AIN1 == NRFX_ANALOG_EXTERNAL_AIN1) &&
(NRF_COMP_AIN2 == NRFX_ANALOG_EXTERNAL_AIN2) &&
(NRF_COMP_AIN3 == NRFX_ANALOG_EXTERNAL_AIN3) &&
(NRF_COMP_AIN4 == NRFX_ANALOG_EXTERNAL_AIN4) &&
(NRF_COMP_AIN5 == NRFX_ANALOG_EXTERNAL_AIN5) &&
(NRF_COMP_AIN6 == NRFX_ANALOG_EXTERNAL_AIN6) &&
(NRF_COMP_AIN7 == NRFX_ANALOG_EXTERNAL_AIN7) &&
#if NRF_COMP_HAS_VDDH_DIV5
(NRF_COMP_AIN_VDDH_DIV5 == NRFX_ANALOG_INTERNAL_VDDHDIV5) &&
#endif
#if defined(COMP_PSEL_PSEL_AnalogInput5)
(NRF_COMP_AIN5 == NRF_COMP_INPUT_5) &&
#endif
#if defined(COMP_PSEL_PSEL_AnalogInput6)
(NRF_COMP_AIN6 == NRF_COMP_INPUT_6) &&
#endif
#if defined(COMP_PSEL_PSEL_AnalogInput7)
(NRF_COMP_AIN7 == NRF_COMP_INPUT_7) &&
#endif
(NRF_COMP_AIN0 == NRF_COMP_EXT_REF_0) &&
(NRF_COMP_AIN1 == NRF_COMP_EXT_REF_1) &&
(NRF_COMP_AIN2 == NRF_COMP_EXT_REF_2) &&
(NRF_COMP_AIN3 == NRF_COMP_EXT_REF_3) &&
#if defined(COMP_EXTREFSEL_EXTREFSEL_AnalogReference4)
(NRF_COMP_AIN4 == NRF_COMP_EXT_REF_4) &&
#endif
#if defined(COMP_EXTREFSEL_EXTREFSEL_AnalogReference5)
(NRF_COMP_AIN5 == NRF_COMP_EXT_REF_5) &&
#endif
#if defined(COMP_EXTREFSEL_EXTREFSEL_AnalogReference6)
(NRF_COMP_AIN6 == NRF_COMP_EXT_REF_6) &&
#endif
#if defined(COMP_EXTREFSEL_EXTREFSEL_AnalogReference7)
(NRF_COMP_AIN7 == NRF_COMP_EXT_REF_7) &&
#endif
#if defined(COMP_PSEL_PSEL_VddDiv2)
(NRF_COMP_VDD_DIV2 == NRF_COMP_VDD_DIV2) &&
#endif
#if defined(COMP_PSEL_PSEL_VddhDiv5)
(NRF_COMP_VDDH_DIV5 == NRF_COMP_VDDH_DIV5) &&
#if NRF_COMP_HAS_VDD_DIV2
(NRF_COMP_AIN_VDD_DIV2 == NRFX_ANALOG_INTERNAL_VDDDIV2) &&
#endif
1,
"Definitions from nrf-comp.h do not match those from HAL");
#endif
"Definitions from nrf-comp.h do not match those from nrfx_analog_common.h");
#ifndef COMP_MODE_SP_Normal
#if !NRF_COMP_HAS_SP_MODE_NORMAL
BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_SP_MODE(0) != COMP_NRF_COMP_SP_MODE_NORMAL);
#endif
#if NRF_COMP_HAS_ISOURCE
#ifndef COMP_ISOURCE_ISOURCE_Ien2uA5
BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_ISOURCE(0) != COMP_NRF_COMP_ISOURCE_2UA5);
#endif
#ifndef COMP_ISOURCE_ISOURCE_Ien5uA
BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_ISOURCE(0) != COMP_NRF_COMP_ISOURCE_5UA);
#endif
#ifndef COMP_ISOURCE_ISOURCE_Ien10uA
BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_ISOURCE(0) != COMP_NRF_COMP_ISOURCE_10UA);
#endif
#endif
#if SHIM_NRF_COMP_DT_INST_MAIN_MODE_IS_SE(0)
#ifndef COMP_REFSEL_REFSEL_Int1V8
#if !NRF_COMP_HAS_REF_INT_1V8
BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_REFSEL(0) != COMP_NRF_COMP_REFSEL_INT_1V8);
#endif
#ifndef COMP_REFSEL_REFSEL_Int2V4
#if !NRF_COMP_HAS_REF_INT_2V4
BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_REFSEL(0) != COMP_NRF_COMP_REFSEL_INT_2V4);
#endif
#ifndef COMP_REFSEL_REFSEL_AVDDAO1V8
#if !NRF_COMP_HAS_REF_AVDDAO1V8
BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_REFSEL(0) != COMP_NRF_COMP_REFSEL_AVDDAO1V8);
#endif
#ifndef COMP_REFSEL_REFSEL_VDD
#if !NRF_COMP_HAS_REF_VDD
BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_REFSEL(0) != COMP_NRF_COMP_REFSEL_VDD);
#endif
#endif
@@ -241,87 +183,6 @@ static int shim_nrf_comp_pm_callback(const struct device *dev, enum pm_device_ac
return 0;
}
#if (NRF_COMP_HAS_AIN_AS_PIN)
static int shim_nrf_comp_psel_to_nrf(uint8_t shim,
nrf_comp_input_t *nrf)
{
if (shim >= ARRAY_SIZE(shim_nrf_comp_ain_map)) {
return -EINVAL;
}
*nrf = shim_nrf_comp_ain_map[shim];
#if NRF_GPIO_HAS_RETENTION_SETCLEAR
nrf_gpio_pin_retain_disable(shim_nrf_comp_ain_map[shim]);
#endif
return 0;
}
#else
static int shim_nrf_comp_psel_to_nrf(uint8_t shim,
nrf_comp_input_t *nrf)
{
switch (shim) {
case NRF_COMP_AIN0:
*nrf = NRF_COMP_INPUT_0;
break;
case NRF_COMP_AIN1:
*nrf = NRF_COMP_INPUT_1;
break;
case NRF_COMP_AIN2:
*nrf = NRF_COMP_INPUT_2;
break;
case NRF_COMP_AIN3:
*nrf = NRF_COMP_INPUT_3;
break;
#if defined(COMP_PSEL_PSEL_AnalogInput4)
case NRF_COMP_AIN4:
*nrf = NRF_COMP_INPUT_4;
break;
#endif
#if defined(COMP_PSEL_PSEL_AnalogInput5)
case NRF_COMP_AIN5:
*nrf = NRF_COMP_INPUT_5;
break;
#endif
#if defined(COMP_PSEL_PSEL_AnalogInput6)
case NRF_COMP_AIN6:
*nrf = NRF_COMP_INPUT_6;
break;
#endif
#if defined(COMP_PSEL_PSEL_AnalogInput7)
case NRF_COMP_AIN7:
*nrf = NRF_COMP_INPUT_7;
break;
#endif
#if defined(COMP_PSEL_PSEL_VddDiv2)
case NRF_COMP_AIN_VDD_DIV2:
*nrf = NRF_COMP_VDD_DIV2;
break;
#endif
#if defined(COMP_PSEL_PSEL_VddhDiv5)
case NRF_COMP_AIN_VDDH_DIV5:
*nrf = NRF_COMP_VDDH_DIV5;
break;
#endif
default:
return -EINVAL;
}
return 0;
}
#endif
static int shim_nrf_comp_sp_mode_to_nrf(enum comp_nrf_comp_sp_mode shim,
nrf_comp_sp_mode_t *nrf)
{
@@ -330,7 +191,7 @@ static int shim_nrf_comp_sp_mode_to_nrf(enum comp_nrf_comp_sp_mode shim,
*nrf = NRF_COMP_SP_MODE_LOW;
break;
#if defined(COMP_MODE_SP_Normal)
#if NRF_COMP_HAS_SP_MODE_NORMAL
case COMP_NRF_COMP_SP_MODE_NORMAL:
*nrf = NRF_COMP_SP_MODE_NORMAL;
break;
@@ -349,95 +210,21 @@ static int shim_nrf_comp_sp_mode_to_nrf(enum comp_nrf_comp_sp_mode shim,
#if NRF_COMP_HAS_ISOURCE
static int shim_nrf_comp_isource_to_nrf(enum comp_nrf_comp_isource shim,
nrf_isource_t *nrf)
nrf_comp_isource_t *nrf)
{
switch (shim) {
case COMP_NRF_COMP_ISOURCE_DISABLED:
*nrf = NRF_COMP_ISOURCE_OFF;
break;
#if defined(COMP_ISOURCE_ISOURCE_Ien2uA5)
case COMP_NRF_COMP_ISOURCE_2UA5:
*nrf = NRF_COMP_ISOURCE_IEN_2UA5;
break;
#endif
#if defined(COMP_ISOURCE_ISOURCE_Ien5uA)
case COMP_NRF_COMP_ISOURCE_5UA:
*nrf = NRF_COMP_ISOURCE_IEN_5UA;
break;
#endif
#if defined(COMP_ISOURCE_ISOURCE_Ien10uA)
case COMP_NRF_COMP_ISOURCE_10UA:
*nrf = NRF_COMP_ISOURCE_IEN_10UA;
break;
#endif
default:
return -EINVAL;
}
return 0;
}
#endif
#if (NRF_COMP_HAS_AIN_AS_PIN)
static int shim_nrf_comp_extrefsel_to_nrf(uint8_t shim,
nrf_comp_ext_ref_t *nrf)
{
if (shim >= ARRAY_SIZE(shim_nrf_comp_ain_map)) {
return -EINVAL;
}
*nrf = shim_nrf_comp_ain_map[shim];
return 0;
}
#else
static int shim_nrf_comp_extrefsel_to_nrf(uint8_t shim,
nrf_comp_ext_ref_t *nrf)
{
switch (shim) {
case NRF_COMP_AIN0:
*nrf = NRF_COMP_EXT_REF_0;
break;
case NRF_COMP_AIN1:
*nrf = NRF_COMP_EXT_REF_1;
break;
case NRF_COMP_AIN2:
*nrf = NRF_COMP_EXT_REF_2;
break;
case NRF_COMP_AIN3:
*nrf = NRF_COMP_EXT_REF_3;
break;
#if defined(COMP_EXTREFSEL_EXTREFSEL_AnalogReference4)
case NRF_COMP_AIN4:
*nrf = NRF_COMP_EXT_REF_4;
break;
#endif
#if defined(COMP_EXTREFSEL_EXTREFSEL_AnalogReference5)
case NRF_COMP_AIN5:
*nrf = NRF_COMP_EXT_REF_5;
break;
#endif
#if defined(COMP_EXTREFSEL_EXTREFSEL_AnalogReference6)
case NRF_COMP_AIN6:
*nrf = NRF_COMP_EXT_REF_6;
break;
#endif
#if defined(COMP_EXTREFSEL_EXTREFSEL_AnalogReference7)
case NRF_COMP_AIN7:
*nrf = NRF_COMP_EXT_REF_7;
break;
#endif
default:
return -EINVAL;
}
@@ -454,25 +241,25 @@ static int shim_nrf_comp_refsel_to_nrf(enum comp_nrf_comp_refsel shim,
*nrf = NRF_COMP_REF_INT_1V2;
break;
#if defined(COMP_REFSEL_REFSEL_Int1V8)
#if NRF_COMP_HAS_REF_INT_1V8
case COMP_NRF_COMP_REFSEL_INT_1V8:
*nrf = NRF_COMP_REF_INT_1V8;
break;
#endif
#if defined(COMP_REFSEL_REFSEL_Int2V4)
#if NRF_COMP_HAS_REF_INT_2V4
case COMP_NRF_COMP_REFSEL_INT_2V4:
*nrf = NRF_COMP_REF_INT_2V4;
break;
#endif
#if defined(COMP_REFSEL_REFSEL_AVDDAO1V8)
#if NRF_COMP_HAS_REF_AVDDAO1V8
case COMP_NRF_COMP_REFSEL_AVDDAO1V8:
*nrf = NRF_COMP_REF_AVDDAO1V8;
break;
#endif
#if defined(COMP_REFSEL_REFSEL_VDD)
#if NRF_COMP_HAS_REF_VDD
case COMP_NRF_COMP_REFSEL_VDD:
*nrf = NRF_COMP_REF_VDD;
break;
@@ -496,9 +283,8 @@ static int shim_nrf_comp_se_config_to_nrf(const struct comp_nrf_comp_se_config *
return -EINVAL;
}
if (shim_nrf_comp_extrefsel_to_nrf(shim->extrefsel, &nrf->ext_ref)) {
return -EINVAL;
}
nrf->ext_ref = (nrfx_analog_input_t)shim->extrefsel;
nrf->input = (nrfx_analog_input_t)shim->psel;
nrf->main_mode = NRF_COMP_MAIN_MODE_SE;
@@ -525,10 +311,6 @@ static int shim_nrf_comp_se_config_to_nrf(const struct comp_nrf_comp_se_config *
}
#endif
if (shim_nrf_comp_psel_to_nrf(shim->psel, &nrf->input)) {
return -EINVAL;
}
nrf->interrupt_priority = 0;
return 0;
}
@@ -538,9 +320,8 @@ static int shim_nrf_comp_diff_config_to_nrf(const struct comp_nrf_comp_diff_conf
{
nrf->reference = NRF_COMP_REF_AREF;
if (shim_nrf_comp_extrefsel_to_nrf(shim->extrefsel, &nrf->ext_ref)) {
return -EINVAL;
}
nrf->ext_ref = (nrfx_analog_input_t)shim->extrefsel;
nrf->input = (nrfx_analog_input_t)shim->psel;
nrf->main_mode = NRF_COMP_MAIN_MODE_DIFF;
nrf->threshold.th_down = 0;
@@ -572,10 +353,6 @@ static int shim_nrf_comp_diff_config_to_nrf(const struct comp_nrf_comp_diff_conf
}
#endif
if (shim_nrf_comp_psel_to_nrf(shim->psel, &nrf->input)) {
return -EINVAL;
}
nrf->interrupt_priority = 0;
return 0;
}
@@ -723,7 +500,7 @@ static int shim_nrf_comp_init(const struct device *dev)
(void)shim_nrf_comp_diff_config_to_nrf(&shim_nrf_comp_config0, &nrf);
#endif
if (nrfx_comp_init(&nrf, shim_nrf_comp_event_handler) != NRFX_SUCCESS) {
if (nrfx_comp_init(&nrf, shim_nrf_comp_event_handler) != 0) {
return -ENODEV;
}

130
drivers/comparator/comparator_nrf_lpcomp.c
View File

@@ -10,7 +10,6 @@
#include <zephyr/drivers/comparator/nrf_lpcomp.h>
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include "comparator_nrf_common.h"
#include <string.h>
@@ -38,22 +37,15 @@ struct shim_nrf_lpcomp_data {
void *user_data;
};
#if (NRF_LPCOMP_HAS_AIN_AS_PIN)
BUILD_ASSERT(NRF_COMP_AIN0 == 0);
BUILD_ASSERT(NRF_COMP_AIN7 == 7);
#else
BUILD_ASSERT((NRF_COMP_AIN0 == NRF_LPCOMP_INPUT_0) &&
(NRF_COMP_AIN1 == NRF_LPCOMP_INPUT_1) &&
(NRF_COMP_AIN2 == NRF_LPCOMP_INPUT_2) &&
(NRF_COMP_AIN3 == NRF_LPCOMP_INPUT_3) &&
(NRF_COMP_AIN4 == NRF_LPCOMP_INPUT_4) &&
(NRF_COMP_AIN5 == NRF_LPCOMP_INPUT_5) &&
(NRF_COMP_AIN6 == NRF_LPCOMP_INPUT_6) &&
(NRF_COMP_AIN7 == NRF_LPCOMP_INPUT_7) &&
(NRF_COMP_AIN0 == NRF_LPCOMP_EXT_REF_REF0) &&
(NRF_COMP_AIN1 == NRF_LPCOMP_EXT_REF_REF1),
"Definitions from nrf-comp.h do not match those from HAL");
#endif
BUILD_ASSERT((NRF_COMP_AIN0 == NRFX_ANALOG_EXTERNAL_AIN0) &&
(NRF_COMP_AIN1 == NRFX_ANALOG_EXTERNAL_AIN1) &&
(NRF_COMP_AIN2 == NRFX_ANALOG_EXTERNAL_AIN2) &&
(NRF_COMP_AIN3 == NRFX_ANALOG_EXTERNAL_AIN3) &&
(NRF_COMP_AIN4 == NRFX_ANALOG_EXTERNAL_AIN4) &&
(NRF_COMP_AIN5 == NRFX_ANALOG_EXTERNAL_AIN5) &&
(NRF_COMP_AIN6 == NRFX_ANALOG_EXTERNAL_AIN6) &&
(NRF_COMP_AIN7 == NRFX_ANALOG_EXTERNAL_AIN7),
"Definitions from nrf-comp.h do not match those from nrfx_analog_common.h");
#if (LPCOMP_REFSEL_RESOLUTION == 8)
BUILD_ASSERT((SHIM_NRF_LPCOMP_DT_INST_REFSEL(0) < COMP_NRF_LPCOMP_REFSEL_VDD_1_16) ||
@@ -134,99 +126,6 @@ static int shim_nrf_lpcomp_pm_callback(const struct device *dev, enum pm_device_
return 0;
}
#if (NRF_LPCOMP_HAS_AIN_AS_PIN)
static int shim_nrf_lpcomp_psel_to_nrf(uint8_t shim,
nrf_lpcomp_input_t *nrf)
{
if (shim >= ARRAY_SIZE(shim_nrf_comp_ain_map)) {
return -EINVAL;
}
*nrf = shim_nrf_comp_ain_map[shim];
#if NRF_GPIO_HAS_RETENTION_SETCLEAR
nrf_gpio_pin_retain_disable(shim_nrf_comp_ain_map[shim]);
#endif
return 0;
}
#else
static int shim_nrf_lpcomp_psel_to_nrf(uint8_t shim,
nrf_lpcomp_input_t *nrf)
{
switch (shim) {
case NRF_COMP_AIN0:
*nrf = NRF_LPCOMP_INPUT_0;
break;
case NRF_COMP_AIN1:
*nrf = NRF_LPCOMP_INPUT_1;
break;
case NRF_COMP_AIN2:
*nrf = NRF_LPCOMP_INPUT_2;
break;
case NRF_COMP_AIN3:
*nrf = NRF_LPCOMP_INPUT_3;
break;
case NRF_COMP_AIN4:
*nrf = NRF_LPCOMP_INPUT_4;
break;
case NRF_COMP_AIN5:
*nrf = NRF_LPCOMP_INPUT_5;
break;
case NRF_COMP_AIN6:
*nrf = NRF_LPCOMP_INPUT_6;
break;
case NRF_COMP_AIN7:
*nrf = NRF_LPCOMP_INPUT_7;
break;
default:
return -EINVAL;
}
return 0;
}
#endif
#if (NRF_LPCOMP_HAS_AIN_AS_PIN)
static int shim_nrf_lpcomp_extrefsel_to_nrf(uint8_t shim,
nrf_lpcomp_ext_ref_t *nrf)
{
if (shim >= ARRAY_SIZE(shim_nrf_comp_ain_map)) {
return -EINVAL;
}
*nrf = shim_nrf_comp_ain_map[shim];
return 0;
}
#else
static int shim_nrf_lpcomp_extrefsel_to_nrf(uint8_t shim,
nrf_lpcomp_ext_ref_t *nrf)
{
switch (shim) {
case NRF_COMP_AIN0:
*nrf = NRF_LPCOMP_EXT_REF_REF0;
break;
case NRF_COMP_AIN1:
*nrf = NRF_LPCOMP_EXT_REF_REF1;
break;
default:
return -EINVAL;
}
return 0;
}
#endif
static int shim_nrf_lpcomp_refsel_to_nrf(enum comp_nrf_lpcomp_refsel shim,
nrf_lpcomp_ref_t *nrf)
{
@@ -311,9 +210,8 @@ static int shim_nrf_lpcomp_config_to_nrf(const struct comp_nrf_lpcomp_config *sh
return -EINVAL;
}
if (shim_nrf_lpcomp_extrefsel_to_nrf(shim->extrefsel, &nrf->ext_ref)) {
return -EINVAL;
}
nrf->ext_ref = (nrfx_analog_input_t)shim->extrefsel;
nrf->input = (nrfx_analog_input_t)shim->psel;
#if NRF_LPCOMP_HAS_HYST
if (shim->enable_hyst) {
@@ -327,10 +225,6 @@ static int shim_nrf_lpcomp_config_to_nrf(const struct comp_nrf_lpcomp_config *sh
}
#endif
if (shim_nrf_lpcomp_psel_to_nrf(shim->psel, &nrf->input)) {
return -EINVAL;
}
return 0;
}
@@ -463,7 +357,7 @@ static int shim_nrf_lpcomp_init(const struct device *dev)
&shim_nrf_lpcomp_data0.config);
if (nrfx_lpcomp_init(&shim_nrf_lpcomp_data0.config,
shim_nrf_lpcomp_event_handler) != NRFX_SUCCESS) {
shim_nrf_lpcomp_event_handler) != 0) {
return -ENODEV;
}

3
drivers/counter/Kconfig.nrfx
View File

@@ -22,8 +22,7 @@ config COUNTER_RTC_WITH_PPI_WRAP
$(dt_nodelabel_bool_prop,rtc1,ppi-wrap) || \
$(dt_nodelabel_bool_prop,rtc2,ppi-wrap)
depends on COUNTER_NRF_RTC
select NRFX_PPI if HAS_HW_NRF_PPI
select NRFX_DPPI if HAS_HW_NRF_DPPIC
select NRFX_GPPI
# Internal flag which detects if fixed top feature is enabled for any instance
config COUNTER_RTC_CUSTOM_TOP_SUPPORT

60
drivers/counter/counter_nrfx_rtc.c
View File

@@ -11,11 +11,7 @@
#endif
#include <haly/nrfy_rtc.h>
#include <zephyr/sys/atomic.h>
#ifdef DPPI_PRESENT
#include <nrfx_dppi.h>
#else
#include <nrfx_ppi.h>
#endif
#include <helpers/nrfx_gppi.h>
#define LOG_MODULE_NAME counter_rtc
#include <zephyr/logging/log.h>
@@ -58,7 +54,7 @@ struct counter_nrfx_data {
/* Store channel interrupt pending and CC adjusted flags. */
atomic_t ipend_adj;
#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
uint8_t ppi_ch;
nrfx_gppi_handle_t ppi_handle;
#endif
};
@@ -379,41 +375,21 @@ static int ppi_setup(const struct device *dev, uint8_t chan)
struct counter_nrfx_data *data = dev->data;
NRF_RTC_Type *rtc = nrfx_config->rtc;
nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
nrfx_err_t result;
uint32_t eep = nrf_rtc_event_address_get(rtc, evt);
uint32_t tep = nrfy_rtc_task_address_get(rtc, NRF_RTC_TASK_CLEAR);
int err;
if (!nrfx_config->use_ppi) {
return 0;
}
nrfy_rtc_event_enable(rtc, NRF_RTC_CHANNEL_INT_MASK(chan));
#ifdef DPPI_PRESENT
nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0);
result = nrfx_dppi_channel_alloc(&dppi, &data->ppi_ch);
if (result != NRFX_SUCCESS) {
ERR("Failed to allocate PPI channel.");
return -ENODEV;
err = nrfx_gppi_conn_alloc(eep, tep, &data->ppi_handle);
if (err < 0) {
return err;
}
nrfy_rtc_subscribe_set(rtc, NRF_RTC_TASK_CLEAR, data->ppi_ch);
nrfy_rtc_publish_set(rtc, evt, data->ppi_ch);
(void)nrfx_dppi_channel_enable(&dppi, data->ppi_ch);
#else /* DPPI_PRESENT */
uint32_t evt_addr;
uint32_t task_addr;
evt_addr = nrfy_rtc_event_address_get(rtc, evt);
task_addr = nrfy_rtc_task_address_get(rtc, NRF_RTC_TASK_CLEAR);
result = nrfx_ppi_channel_alloc(&data->ppi_ch);
if (result != NRFX_SUCCESS) {
ERR("Failed to allocate PPI channel.");
return -ENODEV;
}
(void)nrfx_ppi_channel_assign(data->ppi_ch, evt_addr, task_addr);
(void)nrfx_ppi_channel_enable(data->ppi_ch);
nrfx_gppi_conn_enable(data->ppi_handle);
#endif
#endif /* CONFIG_COUNTER_RTC_WITH_PPI_WRAP */
return 0;
}
@@ -422,25 +398,17 @@ static void ppi_free(const struct device *dev, uint8_t chan)
#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
const struct counter_nrfx_config *nrfx_config = dev->config;
struct counter_nrfx_data *data = dev->data;
uint8_t ppi_ch = data->ppi_ch;
NRF_RTC_Type *rtc = nrfx_config->rtc;
nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
uint32_t eep = nrf_rtc_event_address_get(rtc, evt);
uint32_t tep = nrfy_rtc_task_address_get(rtc, NRF_RTC_TASK_CLEAR);
if (!nrfx_config->use_ppi) {
return;
}
nrfy_rtc_event_disable(rtc, NRF_RTC_CHANNEL_INT_MASK(chan));
#ifdef DPPI_PRESENT
nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0);
(void)nrfx_dppi_channel_disable(&dppi, ppi_ch);
nrfy_rtc_subscribe_clear(rtc, NRF_RTC_TASK_CLEAR);
nrfy_rtc_publish_clear(rtc, evt);
(void)nrfx_dppi_channel_free(&dppi, ppi_ch);
#else /* DPPI_PRESENT */
(void)nrfx_ppi_channel_disable(ppi_ch);
(void)nrfx_ppi_channel_free(ppi_ch);
#endif
nrfx_gppi_conn_disable(data->ppi_handle);
nrfx_gppi_conn_free(eep, tep, data->ppi_handle);
#endif
}

2
drivers/display/Kconfig.nrf_led_matrix
View File

@@ -6,7 +6,7 @@ config DISPLAY_NRF_LED_MATRIX
default y
depends on DT_HAS_NORDIC_NRF_LED_MATRIX_ENABLED
select NRFX_GPIOTE
select NRFX_PPI if HAS_HW_NRF_PPI
select NRFX_GPPI
help
Enable driver for a LED matrix with rows and columns driven by
GPIOs. The driver allows setting one of 256 levels of brightness

52
drivers/display/display_nrf_led_matrix.c
View File

@@ -13,10 +13,8 @@
#include <hal/nrf_pwm.h>
#endif
#include <nrfx_gpiote.h>
#ifdef PPI_PRESENT
#include <nrfx_ppi.h>
#endif
#include <nrf_peripherals.h>
#include <gpiote_nrfx.h>
#include <helpers/nrfx_gppi.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(nrf_led_matrix, CONFIG_DISPLAY_LOG_LEVEL);
@@ -91,7 +89,7 @@ struct display_drv_config {
#if USE_PWM
NRF_PWM_Type *pwm;
#else
nrfx_gpiote_t gpiote;
nrfx_gpiote_t *gpiote;
#endif
uint8_t rows[ROW_COUNT];
uint8_t cols[COL_COUNT];
@@ -327,7 +325,7 @@ static void prepare_pixel_pulse(const struct device *dev,
/* First timer channel is used for timing the period of pulses. */
nrf_timer_cc_set(dev_config->timer, 1 + channel_idx, pulse);
dev_config->gpiote.p_reg->CONFIG[dev_data->gpiote_ch[channel_idx]] = gpiote_cfg;
dev_config->gpiote->p_reg->CONFIG[dev_data->gpiote_ch[channel_idx]] = gpiote_cfg;
#endif /* USE_PWM */
}
@@ -357,7 +355,7 @@ static void timer_irq_handler(void *arg)
}
#else
for (int i = 0; i < GROUP_SIZE; ++i) {
dev_config->gpiote.p_reg->CONFIG[dev_data->gpiote_ch[i]] = 0;
dev_config->gpiote->p_reg->CONFIG[dev_data->gpiote_ch[i]] = 0;
}
#endif
@@ -437,38 +435,37 @@ static int instance_init(const struct device *dev)
nrf_pwm_loop_set(dev_config->pwm, 0);
nrf_pwm_shorts_set(dev_config->pwm, NRF_PWM_SHORT_SEQEND0_STOP_MASK);
#else
nrfx_err_t err;
nrf_ppi_channel_t ppi_ch;
nrfx_gppi_handle_t ppi_handle;
int rv;
for (int i = 0; i < GROUP_SIZE; ++i) {
uint8_t *gpiote_ch = &dev_data->gpiote_ch[i];
err = nrfx_ppi_channel_alloc(&ppi_ch);
if (err != NRFX_SUCCESS) {
LOG_ERR("Failed to allocate PPI channel.");
/* Do not bother with freeing resources allocated
* so far. The application needs to be reconfigured
* anyway.
*/
return -ENOMEM;
}
err = nrfx_gpiote_channel_alloc(&dev_config->gpiote, gpiote_ch);
if (err != NRFX_SUCCESS) {
rv = nrfx_gpiote_channel_alloc(dev_config->gpiote, gpiote_ch);
if (rv != 0) {
LOG_ERR("Failed to allocate GPIOTE channel.");
/* Do not bother with freeing resources allocated
* so far. The application needs to be reconfigured
* anyway.
*/
return -ENOMEM;
return rv;
}
nrf_ppi_channel_endpoint_setup(NRF_PPI, ppi_ch,
rv = nrfx_gppi_conn_alloc(
nrf_timer_event_address_get(dev_config->timer,
nrf_timer_compare_event_get(1 + i)),
nrf_gpiote_event_address_get(dev_config->gpiote.p_reg,
nrf_gpiote_out_task_get(*gpiote_ch)));
nrf_ppi_channel_enable(NRF_PPI, ppi_ch);
nrf_gpiote_event_address_get(dev_config->gpiote->p_reg,
nrf_gpiote_out_task_get(*gpiote_ch)),
&ppi_handle);
if (rv < 0) {
LOG_ERR("Failed to allocate PPI channel.");
/* Do not bother with freeing resources allocated
* so far. The application needs to be reconfigured
* anyway.
*/
return rv;
}
nrfx_gppi_conn_enable(ppi_handle);
}
#endif /* USE_PWM */
@@ -542,8 +539,7 @@ static const struct display_drv_config instance_config = {
#if USE_PWM
.pwm = (NRF_PWM_Type *)DT_REG_ADDR(PWM_NODE),
#else
.gpiote = NRFX_GPIOTE_INSTANCE(
NRF_DT_GPIOTE_INST_BY_IDX(MATRIX_NODE, col_gpios, 0)),
.gpiote = &GPIOTE_NRFX_INST_BY_NODE(NRF_DT_GPIOTE_NODE(MATRIX_NODE, col_gpios)),
#endif
.rows = { DT_FOREACH_PROP_ELEM(MATRIX_NODE, row_gpios, GET_PIN_INFO) },
.cols = { DT_FOREACH_PROP_ELEM(MATRIX_NODE, col_gpios, GET_PIN_INFO) },

14
drivers/entropy/entropy_nrf_cracen.c
View File

@@ -23,12 +23,10 @@ static int nrf_cracen_get_entropy_isr(const struct device *dev, uint8_t *buf, ui
irq_unlock(key);
if (likely(ret == NRFX_SUCCESS)) {
if (likely(ret == 0)) {
return len;
} else if (ret == NRFX_ERROR_INVALID_PARAM) {
return -EINVAL;
} else {
return -EAGAIN;
return ret;
}
}
@@ -47,13 +45,7 @@ static int nrf_cracen_cracen_init(const struct device *dev)
{
(void)dev;
int ret = nrfx_cracen_ctr_drbg_init();
if (ret == NRFX_SUCCESS) {
return 0;
} else {
return -EIO;
}
return nrfx_cracen_ctr_drbg_init();
}
static DEVICE_API(entropy, nrf_cracen_api_funcs) = {

125
drivers/flash/nrf_qspi_nor.c
View File

@@ -22,7 +22,6 @@ LOG_MODULE_REGISTER(qspi_nor, CONFIG_FLASH_LOG_LEVEL);
#include "spi_nor.h"
#include "jesd216.h"
#include "flash_priv.h"
#include <nrf_erratas.h>
#include <nrfx_qspi.h>
#include <hal/nrf_clock.h>
#include <hal/nrf_gpio.h>
@@ -111,7 +110,7 @@ BUILD_ASSERT(INST_0_SCK_FREQUENCY >= (NRF_QSPI_BASE_CLOCK_FREQ / 16),
#define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_1
#define INST_0_SCK_CFG NRF_QSPI_FREQ_DIV1
/* If anomaly 159 is to be prevented, only /1 divider can be used. */
#elif NRF53_ERRATA_159_ENABLE_WORKAROUND
#elif NRF_ERRATA_STATIC_CHECK(53, 159)
#define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_1
#define INST_0_SCK_CFG (DIV_ROUND_UP(NRF_QSPI_BASE_CLOCK_FREQ, \
INST_0_SCK_FREQUENCY) - 1)
@@ -238,32 +237,6 @@ static int exit_dpd(const struct device *const dev);
#define QSPI_IS_SECTOR_ALIGNED(_ofs) (((_ofs) & (QSPI_SECTOR_SIZE - 1U)) == 0)
#define QSPI_IS_BLOCK_ALIGNED(_ofs) (((_ofs) & (QSPI_BLOCK_SIZE - 1U)) == 0)
/**
* @brief Converts NRFX return codes to the zephyr ones
*/
static inline int qspi_get_zephyr_ret_code(nrfx_err_t res)
{
switch (res) {
case NRFX_SUCCESS:
return 0;
case NRFX_ERROR_INVALID_PARAM:
case NRFX_ERROR_INVALID_ADDR:
return -EINVAL;
case NRFX_ERROR_INVALID_STATE:
return -ECANCELED;
#if NRF53_ERRATA_159_ENABLE_WORKAROUND
case NRFX_ERROR_FORBIDDEN:
LOG_ERR("nRF5340 anomaly 159 conditions detected");
LOG_ERR("Set the CPU clock to 64 MHz before starting QSPI operation");
return -ECANCELED;
#endif
case NRFX_ERROR_BUSY:
case NRFX_ERROR_TIMEOUT:
default:
return -EBUSY;
}
}
static inline void qspi_lock(const struct device *dev)
{
#ifdef CONFIG_MULTITHREADING
@@ -375,12 +348,11 @@ static void qspi_release(const struct device *dev)
}
}
static inline void qspi_wait_for_completion(const struct device *dev,
nrfx_err_t res)
static inline void qspi_wait_for_completion(const struct device *dev, int res)
{
struct qspi_nor_data *dev_data = dev->data;
if (res == NRFX_SUCCESS) {
if (res == 0) {
#ifdef CONFIG_MULTITHREADING
k_sem_take(&dev_data->sync, K_FOREVER);
#else /* CONFIG_MULTITHREADING */
@@ -476,9 +448,7 @@ static int qspi_send_cmd(const struct device *dev, const struct qspi_cmd *cmd,
.wren = wren,
};
int res = nrfx_qspi_cinstr_xfer(&cinstr_cfg, tx_buf, rx_buf);
return qspi_get_zephyr_ret_code(res);
return nrfx_qspi_cinstr_xfer(&cinstr_cfg, tx_buf, rx_buf);
}
/* RDSR. Negative value is error. */
@@ -606,7 +576,7 @@ static int qspi_erase(const struct device *dev, uint32_t addr, uint32_t size)
return rc;
}
while (size > 0) {
nrfx_err_t res = !NRFX_SUCCESS;
int res = -1;
uint32_t adj = 0;
if (size == params->size) {
@@ -626,11 +596,11 @@ static int qspi_erase(const struct device *dev, uint32_t addr, uint32_t size)
} else {
/* minimal erase size is at least a sector size */
LOG_ERR("unsupported at 0x%lx size %zu", (long)addr, size);
res = NRFX_ERROR_INVALID_PARAM;
res = -EINVAL;
}
qspi_wait_for_completion(dev, res);
if (res == NRFX_SUCCESS) {
if (res == 0) {
addr += adj;
size -= adj;
@@ -645,7 +615,7 @@ static int qspi_erase(const struct device *dev, uint32_t addr, uint32_t size)
}
} else {
LOG_ERR("erase error at 0x%lx size %zu", (long)addr, size);
rc = qspi_get_zephyr_ret_code(res);
rc = res;
break;
}
}
@@ -780,24 +750,24 @@ static int qspi_sfdp_read(const struct device *dev, off_t offset,
.io2_level = true,
.io3_level = true,
};
nrfx_err_t res;
int res;
qspi_acquire(dev);
res = nrfx_qspi_lfm_start(&cinstr_cfg);
if (res != NRFX_SUCCESS) {
if (res != 0) {
LOG_DBG("lfm_start: %x", res);
goto out;
}
res = nrfx_qspi_lfm_xfer(addr_buf, NULL, sizeof(addr_buf), false);
if (res != NRFX_SUCCESS) {
if (res != 0) {
LOG_DBG("lfm_xfer addr: %x", res);
goto out;
}
res = nrfx_qspi_lfm_xfer(NULL, data, len, true);
if (res != NRFX_SUCCESS) {
if (res != 0) {
LOG_DBG("lfm_xfer read: %x", res);
goto out;
}
@@ -805,14 +775,14 @@ static int qspi_sfdp_read(const struct device *dev, off_t offset,
out:
qspi_release(dev);
return qspi_get_zephyr_ret_code(res);
return res;
}
#endif /* CONFIG_FLASH_JESD216_API */
static inline nrfx_err_t read_non_aligned(const struct device *dev,
off_t addr,
void *dest, size_t size)
static inline int read_non_aligned(const struct device *dev,
off_t addr,
void *dest, size_t size)
{
uint8_t __aligned(WORD_SIZE) buf[WORD_SIZE * 2];
uint8_t *dptr = dest;
@@ -839,14 +809,14 @@ static inline nrfx_err_t read_non_aligned(const struct device *dev,
flash_suffix = size - flash_prefix - flash_middle;
}
nrfx_err_t res = NRFX_SUCCESS;
int res = 0;
/* read from aligned flash to aligned memory */
if (flash_middle != 0) {
res = nrfx_qspi_read(dptr + dest_prefix, flash_middle,
addr + flash_prefix);
qspi_wait_for_completion(dev, res);
if (res != NRFX_SUCCESS) {
if (res != 0) {
return res;
}
@@ -861,7 +831,7 @@ static inline nrfx_err_t read_non_aligned(const struct device *dev,
res = nrfx_qspi_read(buf, WORD_SIZE, addr -
(WORD_SIZE - flash_prefix));
qspi_wait_for_completion(dev, res);
if (res != NRFX_SUCCESS) {
if (res != 0) {
return res;
}
memcpy(dptr, buf + WORD_SIZE - flash_prefix, flash_prefix);
@@ -872,7 +842,7 @@ static inline nrfx_err_t read_non_aligned(const struct device *dev,
res = nrfx_qspi_read(buf, WORD_SIZE * 2,
addr + flash_prefix + flash_middle);
qspi_wait_for_completion(dev, res);
if (res != NRFX_SUCCESS) {
if (res != 0) {
return res;
}
memcpy(dptr + flash_prefix + flash_middle, buf, flash_suffix);
@@ -885,7 +855,7 @@ static int qspi_nor_read(const struct device *dev, off_t addr, void *dest,
size_t size)
{
const struct qspi_nor_config *params = dev->config;
nrfx_err_t res;
int res;
if (!dest) {
return -EINVAL;
@@ -911,15 +881,15 @@ static int qspi_nor_read(const struct device *dev, off_t addr, void *dest,
qspi_release(dev);
return qspi_get_zephyr_ret_code(res);
return res;
}
/* addr aligned, sptr not null, slen less than 4 */
static inline nrfx_err_t write_sub_word(const struct device *dev, off_t addr,
const void *sptr, size_t slen)
static inline int write_sub_word(const struct device *dev, off_t addr,
const void *sptr, size_t slen)
{
uint8_t __aligned(4) buf[4];
nrfx_err_t res;
int res;
/* read out the whole word so that unchanged data can be
* written back
@@ -927,7 +897,7 @@ static inline nrfx_err_t write_sub_word(const struct device *dev, off_t addr,
res = nrfx_qspi_read(buf, sizeof(buf), addr);
qspi_wait_for_completion(dev, res);
if (res == NRFX_SUCCESS) {
if (res == 0) {
memcpy(buf, sptr, slen);
res = nrfx_qspi_write(buf, sizeof(buf), addr);
qspi_wait_for_completion(dev, res);
@@ -944,30 +914,30 @@ BUILD_ASSERT((CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE % 4) == 0,
*
* If not enabled return the error the peripheral would have produced.
*/
static nrfx_err_t write_through_buffer(const struct device *dev, off_t addr,
static int write_through_buffer(const struct device *dev, off_t addr,
const void *sptr, size_t slen)
{
nrfx_err_t res = NRFX_SUCCESS;
int res = 0;
if (CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE > 0) {
uint8_t __aligned(4) buf[CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE];
const uint8_t *sp = sptr;
while ((slen > 0) && (res == NRFX_SUCCESS)) {
while ((slen > 0) && (res == 0)) {
size_t len = MIN(slen, sizeof(buf));
memcpy(buf, sp, len);
res = nrfx_qspi_write(buf, len, addr);
qspi_wait_for_completion(dev, res);
if (res == NRFX_SUCCESS) {
if (res == 0) {
slen -= len;
sp += len;
addr += len;
}
}
} else {
res = NRFX_ERROR_INVALID_ADDR;
res = -EACCES;
}
return res;
}
@@ -1006,19 +976,15 @@ static int qspi_nor_write(const struct device *dev, off_t addr,
rc = qspi_nor_write_protection_set(dev, false);
if (rc == 0) {
nrfx_err_t res;
if (size < 4U) {
res = write_sub_word(dev, addr, src, size);
rc = write_sub_word(dev, addr, src, size);
} else if (!nrfx_is_in_ram(src) ||
!nrfx_is_word_aligned(src)) {
res = write_through_buffer(dev, addr, src, size);
rc = write_through_buffer(dev, addr, src, size);
} else {
res = nrfx_qspi_write(src, size, addr);
qspi_wait_for_completion(dev, res);
rc = nrfx_qspi_write(src, size, addr);
qspi_wait_for_completion(dev, rc);
}
rc = qspi_get_zephyr_ret_code(res);
}
rc2 = qspi_nor_write_protection_set(dev, true);
@@ -1080,11 +1046,9 @@ static int qspi_init(const struct device *dev)
{
const struct qspi_nor_config *dev_config = dev->config;
uint8_t id[SPI_NOR_MAX_ID_LEN];
nrfx_err_t res;
int rc;
res = nrfx_qspi_init(&dev_config->nrfx_cfg, qspi_handler, dev->data);
rc = qspi_get_zephyr_ret_code(res);
rc = nrfx_qspi_init(&dev_config->nrfx_cfg, qspi_handler, dev->data);
if (rc < 0) {
return rc;
}
@@ -1269,15 +1233,14 @@ static int exit_dpd(const struct device *const dev)
.op_code = SPI_NOR_CMD_RDPD,
};
uint32_t t_exit_dpd = DT_INST_PROP_OR(0, t_exit_dpd, 0);
nrfx_err_t res;
int rc;
nrf_qspi_pins_get(NRF_QSPI, &pins);
nrf_qspi_pins_set(NRF_QSPI, &disconnected_pins);
res = nrfx_qspi_activate(true);
rc = nrfx_qspi_activate(true);
nrf_qspi_pins_set(NRF_QSPI, &pins);
if (res != NRFX_SUCCESS) {
if (rc != 0) {
return -EIO;
}
@@ -1301,11 +1264,10 @@ static int exit_dpd(const struct device *const dev)
static int qspi_suspend(const struct device *dev)
{
const struct qspi_nor_config *dev_config = dev->config;
nrfx_err_t res;
int rc;
res = nrfx_qspi_mem_busy_check();
if (res != NRFX_SUCCESS) {
rc = nrfx_qspi_mem_busy_check();
if (rc != 0) {
return -EBUSY;
}
@@ -1322,7 +1284,6 @@ static int qspi_suspend(const struct device *dev)
static int qspi_resume(const struct device *dev)
{
const struct qspi_nor_config *dev_config = dev->config;
nrfx_err_t res;
int rc;
rc = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
@@ -1330,9 +1291,9 @@ static int qspi_resume(const struct device *dev)
return rc;
}
res = nrfx_qspi_init(&dev_config->nrfx_cfg, qspi_handler, dev->data);
if (res != NRFX_SUCCESS) {
return -EIO;
rc = nrfx_qspi_init(&dev_config->nrfx_cfg, qspi_handler, dev->data);
if (rc < 0) {
return rc;
}
return exit_dpd(dev);

5
drivers/flash/soc_flash_nrf.c
View File

@@ -15,7 +15,6 @@
#include <zephyr/drivers/flash.h>
#include <string.h>
#include <nrfx_nvmc.h>
#include <nrf_erratas.h>
#include "soc_flash_nrf.h"
@@ -116,7 +115,7 @@ static inline bool is_uicr_addr_valid(off_t addr, size_t len)
#endif /* CONFIG_SOC_FLASH_NRF_UICR */
}
#if CONFIG_SOC_FLASH_NRF_UICR && IS_ENABLED(NRF91_ERRATA_7_ENABLE_WORKAROUND)
#if CONFIG_SOC_FLASH_NRF_UICR && NRF_ERRATA_STATIC_CHECK(91, 7)
static inline void nrf91_errata_7_enter(void)
{
__disable_irq();
@@ -159,7 +158,7 @@ static int flash_nrf_read(const struct device *dev, off_t addr,
return 0;
}
#if CONFIG_SOC_FLASH_NRF_UICR && IS_ENABLED(NRF91_ERRATA_7_ENABLE_WORKAROUND)
#if CONFIG_SOC_FLASH_NRF_UICR && NRF_ERRATA_STATIC_CHECK(91, 7)
if (within_uicr) {
nrf_buffer_read_91_uicr(data, (uint32_t)addr, len);
return 0;

8
drivers/flash/soc_flash_nrf_mramc.c
View File

@@ -186,11 +186,11 @@ static int mramc_sys_init(const struct device *dev)
ARG_UNUSED(dev);
nrfx_mramc_config_t config = NRFX_MRAMC_DEFAULT_CONFIG();
nrfx_err_t err = nrfx_mramc_init(&config, NULL);
int ret = nrfx_mramc_init(&config, NULL);
if (err != NRFX_SUCCESS) {
LOG_ERR("Failed to initialize MRAMC: %d", err);
return -EIO;
if (ret != 0) {
LOG_ERR("Failed to initialize MRAMC: %d", ret);
return ret;
}
LOG_DBG("MRAMC initialized successfully");
return 0;

134
drivers/gpio/gpio_nrfx.c
View File

@@ -7,8 +7,10 @@
#define DT_DRV_COMPAT nordic_nrf_gpio
#include <nrfx_gpiote.h>
#include <gpiote_nrfx.h>
#include <string.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_nrf.h>
#include <zephyr/dt-bindings/gpio/nordic-nrf-gpio.h>
#include <zephyr/irq.h>
#include <zephyr/pm/device.h>
@@ -45,9 +47,9 @@ struct gpio_nrfx_cfg {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
NRF_GPIO_Type *port;
nrfx_gpiote_t *gpiote;
uint32_t edge_sense;
uint8_t port_num;
nrfx_gpiote_t gpiote;
#if defined(GPIOTE_FEATURE_FLAG)
uint32_t flags;
#endif
@@ -63,9 +65,16 @@ static inline const struct gpio_nrfx_cfg *get_port_cfg(const struct device *port
return port->config;
}
void *gpio_nrf_gpiote_by_port_get(const struct device *port)
{
const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
return cfg->gpiote;
}
static bool has_gpiote(const struct gpio_nrfx_cfg *cfg)
{
return cfg->gpiote.p_reg != NULL;
return cfg->gpiote != NULL;
}
#if NRF_GPIO_HAS_RETENTION_SETCLEAR
@@ -111,7 +120,7 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin,
gpio_flags_t flags)
{
int ret = 0;
nrfx_err_t err = NRFX_SUCCESS;
int err = 0;
uint8_t ch;
bool free_ch = false;
const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
@@ -173,13 +182,13 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin,
* to be freed when the pin is reconfigured or disconnected.
*/
if (IS_ENABLED(CONFIG_GPIO_NRFX_INTERRUPT)) {
err = nrfx_gpiote_channel_get(&cfg->gpiote, abs_pin, &ch);
free_ch = (err == NRFX_SUCCESS);
err = nrfx_gpiote_channel_get(cfg->gpiote, abs_pin, &ch);
free_ch = (err == 0);
}
if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
/* Ignore the error code. The pin may not have been used. */
(void)nrfx_gpiote_pin_uninit(&cfg->gpiote, abs_pin);
(void)nrfx_gpiote_pin_uninit(cfg->gpiote, abs_pin);
} else {
/* Remove previously configured trigger when pin is reconfigured. */
if (IS_ENABLED(CONFIG_GPIO_NRFX_INTERRUPT)) {
@@ -190,11 +199,9 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin,
.p_trigger_config = &trigger_config,
};
err = nrfx_gpiote_input_configure(&cfg->gpiote,
err = nrfx_gpiote_input_configure(cfg->gpiote,
abs_pin, &input_pin_config);
if (err != NRFX_SUCCESS) {
ret = -EINVAL;
if (err < 0) {
goto end;
}
}
@@ -208,7 +215,7 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin,
.pull = pull,
};
err = nrfx_gpiote_output_configure(&cfg->gpiote,
err = nrfx_gpiote_output_configure(cfg->gpiote,
abs_pin, &output_config, NULL);
port_retain_set(cfg, BIT(pin));
@@ -217,12 +224,11 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin,
.p_pull_config = &pull,
};
err = nrfx_gpiote_input_configure(&cfg->gpiote,
err = nrfx_gpiote_input_configure(cfg->gpiote,
abs_pin, &input_pin_config);
}
if (err != NRFX_SUCCESS) {
ret = -EINVAL;
if (err < 0) {
goto end;
}
}
@@ -234,8 +240,8 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin,
goto end;
}
#endif
err = nrfx_gpiote_channel_free(&cfg->gpiote, ch);
__ASSERT_NO_MSG(err == NRFX_SUCCESS);
err = nrfx_gpiote_channel_free(cfg->gpiote, ch);
__ASSERT_NO_MSG(err == 0);
}
end:
@@ -391,7 +397,7 @@ static nrfx_gpiote_trigger_t get_trigger(enum gpio_int_mode mode,
NRFX_GPIOTE_TRIGGER_LOTOHI;
}
static nrfx_err_t chan_alloc(const struct gpio_nrfx_cfg *cfg, gpio_pin_t pin, uint8_t *ch)
static int chan_alloc(const struct gpio_nrfx_cfg *cfg, gpio_pin_t pin, uint8_t *ch)
{
#ifdef GPIOTE_FEATURE_FLAG
if (cfg->flags & GPIOTE_FLAG_FIXED_CHAN) {
@@ -401,25 +407,25 @@ static nrfx_err_t chan_alloc(const struct gpio_nrfx_cfg *cfg, gpio_pin_t pin, ui
* - P1: channel => pin - 4, e.g. P1.4 => channel 0, P1.5 => channel 1
* - P2: channel => pin % 8, e.g. P2.0 => channel 0, P2.8 => channel 0
*/
nrfx_err_t err = NRFX_SUCCESS;
int err = 0;
if (cfg->port_num == 1) {
if (pin < 4) {
err = NRFX_ERROR_INVALID_PARAM;
err = -EINVAL;
} else {
*ch = pin - 4;
}
} else if (cfg->port_num == 2) {
*ch = pin & 0x7;
} else {
err = NRFX_ERROR_INVALID_PARAM;
err = -EINVAL;
}
return err;
}
#endif
return nrfx_gpiote_channel_alloc(&cfg->gpiote, ch);
return nrfx_gpiote_channel_alloc(cfg->gpiote, ch);
}
static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
@@ -429,7 +435,7 @@ static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
{
const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
nrfx_err_t err;
int err;
uint8_t ch;
if (!has_gpiote(cfg)) {
@@ -437,7 +443,7 @@ static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
}
if (mode == GPIO_INT_MODE_DISABLED) {
nrfx_gpiote_trigger_disable(&cfg->gpiote, abs_pin);
nrfx_gpiote_trigger_disable(cfg->gpiote, abs_pin);
return 0;
}
@@ -455,11 +461,11 @@ static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
if (!(BIT(pin) & cfg->edge_sense) &&
(mode == GPIO_INT_MODE_EDGE) &&
(nrf_gpio_pin_dir_get(abs_pin) == NRF_GPIO_PIN_DIR_INPUT)) {
err = nrfx_gpiote_channel_get(&cfg->gpiote, abs_pin, &ch);
if (err == NRFX_ERROR_INVALID_PARAM) {
err = nrfx_gpiote_channel_get(cfg->gpiote, abs_pin, &ch);
if (err == -EINVAL) {
err = chan_alloc(cfg, pin, &ch);
if (err != NRFX_SUCCESS) {
return -ENOMEM;
if (err < 0) {
return err;
}
}
@@ -473,19 +479,19 @@ static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
/* If edge mode with channel was previously used and we are changing to sense or
* level triggered, we must free the channel.
*/
err = nrfx_gpiote_channel_get(&cfg->gpiote, abs_pin, &ch);
if (err == NRFX_SUCCESS) {
err = nrfx_gpiote_channel_free(&cfg->gpiote, ch);
__ASSERT_NO_MSG(err == NRFX_SUCCESS);
err = nrfx_gpiote_channel_get(cfg->gpiote, abs_pin, &ch);
if (err == 0) {
err = nrfx_gpiote_channel_free(cfg->gpiote, ch);
__ASSERT_NO_MSG(err == 0);
}
}
err = nrfx_gpiote_input_configure(&cfg->gpiote, abs_pin, &input_pin_config);
if (err != NRFX_SUCCESS) {
return -EINVAL;
err = nrfx_gpiote_input_configure(cfg->gpiote, abs_pin, &input_pin_config);
if (err < 0) {
return err;
}
nrfx_gpiote_trigger_enable(&cfg->gpiote, abs_pin, true);
nrfx_gpiote_trigger_enable(cfg->gpiote, abs_pin, true);
return 0;
}
@@ -574,9 +580,26 @@ static void nrfx_gpio_handler(nrfx_gpiote_pin_t abs_pin,
}
#endif /* CONFIG_GPIO_NRFX_INTERRUPT */
#define GPIOTE_IRQ_HANDLER_CONNECT(node_id) \
IRQ_CONNECT(DT_IRQN(node_id), DT_IRQ(node_id, priority), nrfx_isr, \
NRFX_CONCAT(nrfx_gpiote_, DT_PROP(node_id, instance), _irq_handler), 0);
#ifdef CONFIG_GPIO_NRFX_INTERRUPT
/* Wrap nrfx IRQ handler to make native builds happy, as providing nrfx IRQ handler
* directly in IRQ_CONNECT causes complaints about mismatched types.
* Casting brings similar effect, however clashes with IRQ_CONNECT macro implementation
* for non-native builds.
*/
void gpio_nrfx_gpiote_irq_handler(void const *param)
{
nrfx_gpiote_t *gpiote = (nrfx_gpiote_t *)param;
nrfx_gpiote_irq_handler(gpiote);
}
#endif
#define GPIOTE_IRQ_HANDLER_CONNECT(node_id) \
IRQ_CONNECT(DT_IRQN(node_id), \
DT_IRQ(node_id, priority), \
gpio_nrfx_gpiote_irq_handler, \
&GPIOTE_NRFX_INST_BY_NODE(node_id), \
0);
static int gpio_nrfx_pm_hook(const struct device *port, enum pm_device_action action)
{
@@ -588,23 +611,23 @@ static int gpio_nrfx_pm_hook(const struct device *port, enum pm_device_action ac
static int gpio_nrfx_init(const struct device *port)
{
const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
nrfx_err_t err;
int err;
if (!has_gpiote(cfg)) {
goto pm_init;
}
if (nrfx_gpiote_init_check(&cfg->gpiote)) {
if (nrfx_gpiote_init_check(cfg->gpiote)) {
goto pm_init;
}
err = nrfx_gpiote_init(&cfg->gpiote, 0 /*not used*/);
if (err != NRFX_SUCCESS) {
err = nrfx_gpiote_init(cfg->gpiote, 0 /*not used*/);
if (err != 0) {
return -EIO;
}
#ifdef CONFIG_GPIO_NRFX_INTERRUPT
nrfx_gpiote_global_callback_set(&cfg->gpiote, nrfx_gpio_handler, NULL);
nrfx_gpiote_global_callback_set(cfg->gpiote, nrfx_gpio_handler, NULL);
DT_FOREACH_STATUS_OKAY(nordic_nrf_gpiote, GPIOTE_IRQ_HANDLER_CONNECT);
#endif /* CONFIG_GPIO_NRFX_INTERRUPT */
@@ -631,35 +654,36 @@ static DEVICE_API(gpio, gpio_nrfx_drv_api_funcs) = {
#endif
};
#define GPIOTE_INST(id) DT_PROP(GPIOTE_PHANDLE(id), instance)
#define GPIOTE_INSTANCE(id) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(id, gpiote_instance), \
(NRFX_GPIOTE_INSTANCE(GPIOTE_INST(id))), \
({ .p_reg = NULL }))
/* Device instantiation is done with node labels because 'port_num' is
* the peripheral number by SoC numbering. We therefore cannot use
* DT_INST APIs here without wider changes.
*/
#define HAS_GPIOTE(id) DT_INST_NODE_HAS_PROP(id, gpiote_instance)
#define GPIOTE_CHECK(id) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(id, gpiote_instance), \
(BUILD_ASSERT(DT_NODE_HAS_STATUS_OKAY(GPIOTE_PHANDLE(id)), \
COND_CODE_1(HAS_GPIOTE(id), \
(BUILD_ASSERT(DT_NODE_HAS_STATUS_OKAY(GPIOTE_PHANDLE(id)), \
"Please enable GPIOTE instance for used GPIO port!")), \
())
#define GPIOTE_REF(id) \
COND_CODE_1(HAS_GPIOTE(id), \
(&GPIOTE_NRFX_INST_BY_NODE(GPIOTE_PHANDLE(id))), \
(NULL))
#define GPIO_NRF_DEVICE(id) \
GPIOTE_CHECK(id); \
static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \
static const struct gpio_nrfx_cfg gpio_nrfx_p##id##_cfg = { \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(id), \
}, \
.port = _CONCAT(NRF_P, DT_INST_PROP(id, port)), \
.port_num = DT_INST_PROP(id, port), \
.gpiote = GPIOTE_REF(id), \
.edge_sense = DT_INST_PROP_OR(id, sense_edge_mask, 0), \
.gpiote = GPIOTE_INSTANCE(id), \
.port_num = DT_INST_PROP(id, port), \
IF_ENABLED(GPIOTE_FEATURE_FLAG, \
(.flags = \
(DT_PROP_OR(GPIOTE_PHANDLE(id), no_port_event, 0) ? \
@@ -669,8 +693,6 @@ static DEVICE_API(gpio, gpio_nrfx_drv_api_funcs) = {
) \
}; \
\
static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \
\
PM_DEVICE_DT_INST_DEFINE(id, gpio_nrfx_pm_hook); \
\
DEVICE_DT_INST_DEFINE(id, gpio_nrfx_init, \

38
drivers/i2c/Kconfig.nrfx
View File

@@ -23,25 +23,7 @@ config I2C_NRFX_TWI
config I2C_NRFX_TWIM
def_bool y
depends on DT_HAS_NORDIC_NRF_TWIM_ENABLED
select NRFX_TWIM0 if HAS_HW_NRF_TWIM0
select NRFX_TWIM1 if HAS_HW_NRF_TWIM1
select NRFX_TWIM2 if HAS_HW_NRF_TWIM2
select NRFX_TWIM3 if HAS_HW_NRF_TWIM3
select NRFX_TWIM20 if HAS_HW_NRF_TWIM20
select NRFX_TWIM21 if HAS_HW_NRF_TWIM21
select NRFX_TWIM22 if HAS_HW_NRF_TWIM22
select NRFX_TWIM23 if HAS_HW_NRF_TWIM23
select NRFX_TWIM24 if HAS_HW_NRF_TWIM24
select NRFX_TWIM30 if HAS_HW_NRF_TWIM30
select NRFX_TWIM120 if HAS_HW_NRF_TWIM120
select NRFX_TWIM130 if HAS_HW_NRF_TWIM130
select NRFX_TWIM131 if HAS_HW_NRF_TWIM131
select NRFX_TWIM132 if HAS_HW_NRF_TWIM132
select NRFX_TWIM133 if HAS_HW_NRF_TWIM133
select NRFX_TWIM134 if HAS_HW_NRF_TWIM134
select NRFX_TWIM135 if HAS_HW_NRF_TWIM135
select NRFX_TWIM136 if HAS_HW_NRF_TWIM136
select NRFX_TWIM137 if HAS_HW_NRF_TWIM137
select NRFX_TWIM
config I2C_NRFX_TRANSFER_TIMEOUT
int "Transfer timeout [ms]"
@@ -56,23 +38,7 @@ config I2C_NRFX_TWIS
depends on DT_HAS_NORDIC_NRF_TWIS_ENABLED
depends on I2C_TARGET
depends on I2C_TARGET_BUFFER_MODE
select NRFX_TWIS0 if HAS_HW_NRF_TWIS0
select NRFX_TWIS1 if HAS_HW_NRF_TWIS1
select NRFX_TWIS2 if HAS_HW_NRF_TWIS2
select NRFX_TWIS3 if HAS_HW_NRF_TWIS3
select NRFX_TWIS20 if HAS_HW_NRF_TWIS20
select NRFX_TWIS21 if HAS_HW_NRF_TWIS21
select NRFX_TWIS22 if HAS_HW_NRF_TWIS22
select NRFX_TWIS23 if HAS_HW_NRF_TWIS23
select NRFX_TWIS24 if HAS_HW_NRF_TWIS24
select NRFX_TWIS30 if HAS_HW_NRF_TWIS30
select NRFX_TWIS130 if HAS_HW_NRF_TWIS130
select NRFX_TWIS131 if HAS_HW_NRF_TWIS131
select NRFX_TWIS133 if HAS_HW_NRF_TWIS133
select NRFX_TWIS134 if HAS_HW_NRF_TWIS134
select NRFX_TWIS135 if HAS_HW_NRF_TWIS135
select NRFX_TWIS136 if HAS_HW_NRF_TWIS136
select NRFX_TWIS137 if HAS_HW_NRF_TWIS137
select NRFX_TWIS
if I2C_NRFX_TWIS

87
drivers/i2c/i2c_nrfx_twi.c
View File

@@ -27,7 +27,7 @@ struct i2c_nrfx_twi_data {
uint32_t dev_config;
struct k_sem transfer_sync;
struct k_sem completion_sync;
volatile nrfx_err_t res;
volatile int res;
};
/* Enforce dev_config matches the same offset as the common structure,
@@ -109,16 +109,16 @@ static void event_handler(nrfx_twi_evt_t const *p_event, void *p_context)
switch (p_event->type) {
case NRFX_TWI_EVT_DONE:
dev_data->res = NRFX_SUCCESS;
dev_data->res = 0;
break;
case NRFX_TWI_EVT_ADDRESS_NACK:
dev_data->res = NRFX_ERROR_DRV_TWI_ERR_ANACK;
dev_data->res = -EIO;
break;
case NRFX_TWI_EVT_DATA_NACK:
dev_data->res = NRFX_ERROR_DRV_TWI_ERR_DNACK;
dev_data->res = -EAGAIN;
break;
default:
dev_data->res = NRFX_ERROR_INTERNAL;
dev_data->res = -ECANCELED;
break;
}
@@ -131,49 +131,40 @@ static DEVICE_API(i2c, i2c_nrfx_twi_driver_api) = {
.recover_bus = i2c_nrfx_twi_recover_bus,
};
#define I2C_NRFX_TWI_DEVICE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(I2C(idx)); \
BUILD_ASSERT(I2C_FREQUENCY(idx) != \
I2C_NRFX_TWI_INVALID_FREQUENCY, \
"Wrong I2C " #idx " frequency setting in dts"); \
static int twi_##idx##_init(const struct device *dev) \
{ \
IRQ_CONNECT(DT_IRQN(I2C(idx)), DT_IRQ(I2C(idx), priority), \
nrfx_isr, nrfx_twi_##idx##_irq_handler, 0); \
const struct i2c_nrfx_twi_config *config = dev->config; \
int err = pinctrl_apply_state(config->pcfg, \
PINCTRL_STATE_DEFAULT); \
if (err < 0) { \
return err; \
} \
return i2c_nrfx_twi_init(dev); \
} \
static struct i2c_nrfx_twi_data twi_##idx##_data = { \
.transfer_sync = Z_SEM_INITIALIZER( \
twi_##idx##_data.transfer_sync, 1, 1), \
.completion_sync = Z_SEM_INITIALIZER( \
twi_##idx##_data.completion_sync, 0, 1) \
}; \
PINCTRL_DT_DEFINE(I2C(idx)); \
static const struct i2c_nrfx_twi_config twi_##idx##z_config = { \
.twi = NRFX_TWI_INSTANCE(idx), \
.config = { \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.frequency = I2C_FREQUENCY(idx), \
}, \
.event_handler = event_handler, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(I2C(idx)), \
}; \
PM_DEVICE_DT_DEFINE(I2C(idx), twi_nrfx_pm_action); \
I2C_DEVICE_DT_DEFINE(I2C(idx), \
twi_##idx##_init, \
PM_DEVICE_DT_GET(I2C(idx)), \
&twi_##idx##_data, \
&twi_##idx##z_config, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_nrfx_twi_driver_api)
#define I2C_NRFX_TWI_DEVICE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(I2C(idx)); \
BUILD_ASSERT(I2C_FREQUENCY(I2C(idx)) != I2C_NRFX_TWI_INVALID_FREQUENCY, \
"Wrong I2C " #idx " frequency setting in dts"); \
static int twi_##idx##_init(const struct device *dev) \
{ \
IRQ_CONNECT(DT_IRQN(I2C(idx)), DT_IRQ(I2C(idx), priority), nrfx_isr, \
nrfx_twi_##idx##_irq_handler, 0); \
const struct i2c_nrfx_twi_config *config = dev->config; \
int err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); \
if (err < 0) { \
return err; \
} \
return i2c_nrfx_twi_init(dev); \
} \
static struct i2c_nrfx_twi_data twi_##idx##_data = { \
.transfer_sync = Z_SEM_INITIALIZER(twi_##idx##_data.transfer_sync, 1, 1), \
.completion_sync = Z_SEM_INITIALIZER(twi_##idx##_data.completion_sync, 0, 1)}; \
PINCTRL_DT_DEFINE(I2C(idx)); \
static const struct i2c_nrfx_twi_config twi_##idx##z_config = { \
.twi = NRFX_TWI_INSTANCE(idx), \
.config = \
{ \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.frequency = I2C_FREQUENCY(I2C(idx)), \
}, \
.event_handler = event_handler, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(I2C(idx)), \
}; \
PM_DEVICE_DT_DEFINE(I2C(idx), twi_nrfx_pm_action); \
I2C_DEVICE_DT_DEFINE(I2C(idx), twi_##idx##_init, PM_DEVICE_DT_GET(I2C(idx)), \
&twi_##idx##_data, &twi_##idx##z_config, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, &i2c_nrfx_twi_driver_api)
#ifdef CONFIG_HAS_HW_NRF_TWI0
I2C_NRFX_TWI_DEVICE(0);

25
drivers/i2c/i2c_nrfx_twi_common.c
View File

@@ -16,12 +16,12 @@ LOG_MODULE_DECLARE(i2c_nrfx_twi);
int i2c_nrfx_twi_init(const struct device *dev)
{
const struct i2c_nrfx_twi_config *config = dev->config;
nrfx_err_t result = nrfx_twi_init(&config->twi, &config->config,
config->event_handler, (void *)dev);
if (result != NRFX_SUCCESS) {
int result = nrfx_twi_init(&config->twi, &config->config,
config->event_handler, (void *)dev);
if (result != 0) {
LOG_ERR("Failed to initialize device: %s",
dev->name);
return -EBUSY;
return result;
}
return 0;
@@ -58,13 +58,11 @@ int i2c_nrfx_twi_recover_bus(const struct device *dev)
const struct i2c_nrfx_twi_config *config = dev->config;
uint32_t scl_pin;
uint32_t sda_pin;
nrfx_err_t err;
scl_pin = nrf_twi_scl_pin_get(config->twi.p_twi);
sda_pin = nrf_twi_sda_pin_get(config->twi.p_twi);
err = nrfx_twi_bus_recover(scl_pin, sda_pin);
return (err == NRFX_SUCCESS ? 0 : -EBUSY);
return nrfx_twi_bus_recover(scl_pin, sda_pin);
}
int i2c_nrfx_twi_msg_transfer(const struct device *dev, uint8_t flags,
@@ -74,7 +72,6 @@ int i2c_nrfx_twi_msg_transfer(const struct device *dev, uint8_t flags,
const struct i2c_nrfx_twi_config *config = dev->config;
int ret = 0;
uint32_t xfer_flags = 0;
nrfx_err_t res;
nrfx_twi_xfer_desc_t cur_xfer = {
.p_primary_buf = buf,
.primary_length = buf_len,
@@ -110,17 +107,7 @@ int i2c_nrfx_twi_msg_transfer(const struct device *dev, uint8_t flags,
}
if (!ret) {
res = nrfx_twi_xfer(&config->twi, &cur_xfer, xfer_flags);
switch (res) {
case NRFX_SUCCESS:
break;
case NRFX_ERROR_BUSY:
ret = -EBUSY;
break;
default:
ret = -EIO;
break;
}
ret = nrfx_twi_xfer(&config->twi, &cur_xfer, xfer_flags);
}
return ret;

197
drivers/i2c/i2c_nrfx_twim.c
View File

@@ -29,9 +29,10 @@ LOG_MODULE_REGISTER(i2c_nrfx_twim, CONFIG_I2C_LOG_LEVEL);
#endif
struct i2c_nrfx_twim_data {
nrfx_twim_t twim;
struct k_sem transfer_sync;
struct k_sem completion_sync;
volatile nrfx_err_t res;
volatile int res;
};
int i2c_nrfx_twim_exclusive_access_acquire(const struct device *dev, k_timeout_t timeout)
@@ -81,7 +82,7 @@ static int i2c_nrfx_twim_transfer(const struct device *dev,
break;
}
bool dma_accessible = nrf_dma_accessible_check(&dev_config->twim, msgs[i].buf);
bool dma_accessible = nrf_dma_accessible_check(&dev_data->twim, msgs[i].buf);
/* This fragment needs to be merged with the next one if:
* - it is not the last fragment
@@ -162,7 +163,7 @@ static int i2c_nrfx_twim_transfer(const struct device *dev,
break;
}
if (dev_data->res != NRFX_SUCCESS) {
if (dev_data->res < 0) {
ret = -EIO;
break;
}
@@ -191,23 +192,23 @@ static int i2c_nrfx_twim_transfer(const struct device *dev,
return ret;
}
static void event_handler(nrfx_twim_evt_t const *p_event, void *p_context)
static void event_handler(nrfx_twim_event_t const *p_event, void *p_context)
{
const struct device *dev = p_context;
struct i2c_nrfx_twim_data *dev_data = dev->data;
switch (p_event->type) {
case NRFX_TWIM_EVT_DONE:
dev_data->res = NRFX_SUCCESS;
dev_data->res = 0;
break;
case NRFX_TWIM_EVT_ADDRESS_NACK:
dev_data->res = NRFX_ERROR_DRV_TWI_ERR_ANACK;
dev_data->res = -EFAULT;
break;
case NRFX_TWIM_EVT_DATA_NACK:
dev_data->res = NRFX_ERROR_DRV_TWI_ERR_DNACK;
dev_data->res = -EAGAIN;
break;
default:
dev_data->res = NRFX_ERROR_INTERNAL;
dev_data->res = -EIO;
break;
}
@@ -240,142 +241,66 @@ static DEVICE_API(i2c, i2c_nrfx_twim_driver_api) = {
.recover_bus = i2c_nrfx_twim_recover_bus,
};
#define CONCAT_BUF_SIZE(idx) \
COND_CODE_1(DT_NODE_HAS_PROP(I2C(idx), zephyr_concat_buf_size), \
(DT_PROP(I2C(idx), zephyr_concat_buf_size)), (0))
#define FLASH_BUF_MAX_SIZE(idx) \
COND_CODE_1(DT_NODE_HAS_PROP(I2C(idx), zephyr_flash_buf_max_size), \
(DT_PROP(I2C(idx), zephyr_flash_buf_max_size)), (0))
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twim)
#define DT_DRV_COMPAT nordic_nrf_twim
#endif
#define USES_MSG_BUF(idx) \
COND_CODE_0(CONCAT_BUF_SIZE(idx), \
(COND_CODE_0(FLASH_BUF_MAX_SIZE(idx), (0), (1))), \
#define CONCAT_BUF_SIZE(idx) \
COND_CODE_1(DT_NODE_HAS_PROP(DT_DRV_INST(idx), zephyr_concat_buf_size), \
(DT_INST_PROP(idx, zephyr_concat_buf_size)), (0))
#define FLASH_BUF_MAX_SIZE(idx) \
COND_CODE_1(DT_NODE_HAS_PROP(DT_DRV_INST(idx), zephyr_flash_buf_max_size), \
(DT_INST_PROP(idx, zephyr_flash_buf_max_size)), (0))
#define USES_MSG_BUF(idx) \
COND_CODE_0(CONCAT_BUF_SIZE(idx), \
(COND_CODE_0(FLASH_BUF_MAX_SIZE(idx), (0), (1))), \
(1))
#define MSG_BUF_SIZE(idx) MAX(CONCAT_BUF_SIZE(idx), FLASH_BUF_MAX_SIZE(idx))
#define I2C_NRFX_TWIM_DEVICE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(I2C(idx)); \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(I2C(idx)); \
BUILD_ASSERT(I2C_FREQUENCY(idx) != \
I2C_NRFX_TWIM_INVALID_FREQUENCY, \
"Wrong I2C " #idx " frequency setting in dts"); \
static void irq_connect##idx(void) \
{ \
IRQ_CONNECT(DT_IRQN(I2C(idx)), DT_IRQ(I2C(idx), priority), \
nrfx_isr, nrfx_twim_##idx##_irq_handler, 0); \
} \
#define I2C_NRFX_TWIM_DEVICE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(DT_DRV_INST(idx)); \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(DT_DRV_INST(idx)); \
BUILD_ASSERT(I2C_FREQUENCY(DT_DRV_INST(idx)) != I2C_NRFX_TWIM_INVALID_FREQUENCY, \
"Wrong I2C " #idx " frequency setting in dts"); \
static struct i2c_nrfx_twim_data twim_##idx##_data; \
static struct i2c_nrfx_twim_common_config twim_##idx##z_config; \
static void pre_init##idx(void) \
{ \
twim_##idx##z_config.twim = &twim_##idx##_data.twim; \
twim_##idx##_data.twim.p_twim = (NRF_TWIM_Type *)DT_INST_REG_ADDR(idx); \
IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), nrfx_twim_irq_handler, \
&twim_##idx##_data.twim, 0); \
} \
IF_ENABLED(USES_MSG_BUF(idx), \
(static uint8_t twim_##idx##_msg_buf[MSG_BUF_SIZE(idx)] \
I2C_MEMORY_SECTION(idx);)) \
static struct i2c_nrfx_twim_data twim_##idx##_data; \
PINCTRL_DT_DEFINE(I2C(idx)); \
static const \
struct i2c_nrfx_twim_common_config twim_##idx##z_config = { \
.twim = NRFX_TWIM_INSTANCE(idx), \
.twim_config = { \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.frequency = I2C_FREQUENCY(idx), \
}, \
.event_handler = event_handler, \
.msg_buf_size = MSG_BUF_SIZE(idx), \
.irq_connect = irq_connect##idx, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(I2C(idx)), \
I2C_MEMORY_SECTION(idx);)) \
PINCTRL_DT_INST_DEFINE(idx); \
static struct i2c_nrfx_twim_common_config twim_##idx##z_config = { \
.twim_config = \
{ \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.frequency = I2C_FREQUENCY(DT_DRV_INST(idx)), \
}, \
.event_handler = event_handler, \
.msg_buf_size = MSG_BUF_SIZE(idx), \
.pre_init = pre_init##idx, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
IF_ENABLED(USES_MSG_BUF(idx), \
(.msg_buf = twim_##idx##_msg_buf,)) \
.max_transfer_size = BIT_MASK( \
DT_PROP(I2C(idx), easydma_maxcnt_bits)), \
}; \
PM_DEVICE_DT_DEFINE(I2C(idx), twim_nrfx_pm_action, \
I2C_PM_ISR_SAFE(idx)); \
I2C_DEVICE_DT_DEINIT_DEFINE(I2C(idx), \
i2c_nrfx_twim_init, \
i2c_nrfx_twim_deinit, \
PM_DEVICE_DT_GET(I2C(idx)), \
&twim_##idx##_data, \
&twim_##idx##z_config, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_nrfx_twim_driver_api)
(.msg_buf = twim_##idx##_msg_buf,)) .max_transfer_size = \
BIT_MASK(DT_INST_PROP(idx, easydma_maxcnt_bits)), \
}; \
PM_DEVICE_DT_INST_DEFINE(idx, twim_nrfx_pm_action, I2C_PM_ISR_SAFE(idx)); \
I2C_DEVICE_DT_INST_DEINIT_DEFINE(idx, i2c_nrfx_twim_init, i2c_nrfx_twim_deinit, \
PM_DEVICE_DT_INST_GET(idx), &twim_##idx##_data, \
&twim_##idx##z_config, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, &i2c_nrfx_twim_driver_api)
#define I2C_MEMORY_SECTION(idx) \
COND_CODE_1(I2C_HAS_PROP(idx, memory_regions), \
#define I2C_MEMORY_SECTION(idx) \
COND_CODE_1(DT_NODE_HAS_PROP(DT_DRV_INST(idx), memory_regions), \
(__attribute__((__section__(LINKER_DT_NODE_REGION_NAME( \
DT_PHANDLE(I2C(idx), memory_regions)))))), \
DT_PHANDLE(DT_DRV_INST(idx), memory_regions)))))), \
())
#ifdef CONFIG_HAS_HW_NRF_TWIM0
I2C_NRFX_TWIM_DEVICE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM1
I2C_NRFX_TWIM_DEVICE(1);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM2
I2C_NRFX_TWIM_DEVICE(2);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM3
I2C_NRFX_TWIM_DEVICE(3);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM20
I2C_NRFX_TWIM_DEVICE(20);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM21
I2C_NRFX_TWIM_DEVICE(21);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM22
I2C_NRFX_TWIM_DEVICE(22);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM23
I2C_NRFX_TWIM_DEVICE(23);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM24
I2C_NRFX_TWIM_DEVICE(24);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM30
I2C_NRFX_TWIM_DEVICE(30);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM120
I2C_NRFX_TWIM_DEVICE(120);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM130
I2C_NRFX_TWIM_DEVICE(130);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM131
I2C_NRFX_TWIM_DEVICE(131);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM132
I2C_NRFX_TWIM_DEVICE(132);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM133
I2C_NRFX_TWIM_DEVICE(133);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM134
I2C_NRFX_TWIM_DEVICE(134);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM135
I2C_NRFX_TWIM_DEVICE(135);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM136
I2C_NRFX_TWIM_DEVICE(136);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM137
I2C_NRFX_TWIM_DEVICE(137);
#endif
DT_INST_FOREACH_STATUS_OKAY(I2C_NRFX_TWIM_DEVICE)

44
drivers/i2c/i2c_nrfx_twim_common.c
View File

@@ -20,15 +20,15 @@ int i2c_nrfx_twim_recover_bus(const struct device *dev)
enum pm_device_state state;
uint32_t scl_pin;
uint32_t sda_pin;
nrfx_err_t err;
int err;
scl_pin = nrf_twim_scl_pin_get(config->twim.p_twim);
sda_pin = nrf_twim_sda_pin_get(config->twim.p_twim);
scl_pin = nrf_twim_scl_pin_get(config->twim->p_twim);
sda_pin = nrf_twim_sda_pin_get(config->twim->p_twim);
/* disable peripheral if active (required to release SCL/SDA lines) */
(void)pm_device_state_get(dev, &state);
if (state == PM_DEVICE_STATE_ACTIVE) {
nrfx_twim_disable(&config->twim);
nrfx_twim_disable(config->twim);
}
err = nrfx_twim_bus_recover(scl_pin, sda_pin);
@@ -36,10 +36,10 @@ int i2c_nrfx_twim_recover_bus(const struct device *dev)
/* restore peripheral if it was active before */
if (state == PM_DEVICE_STATE_ACTIVE) {
(void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
nrfx_twim_enable(&config->twim);
nrfx_twim_enable(config->twim);
}
return (err == NRFX_SUCCESS ? 0 : -EBUSY);
return err;
}
int i2c_nrfx_twim_configure(const struct device *dev, uint32_t i2c_config)
@@ -52,14 +52,14 @@ int i2c_nrfx_twim_configure(const struct device *dev, uint32_t i2c_config)
switch (I2C_SPEED_GET(i2c_config)) {
case I2C_SPEED_STANDARD:
nrf_twim_frequency_set(config->twim.p_twim, NRF_TWIM_FREQ_100K);
nrf_twim_frequency_set(config->twim->p_twim, NRF_TWIM_FREQ_100K);
break;
case I2C_SPEED_FAST:
nrf_twim_frequency_set(config->twim.p_twim, NRF_TWIM_FREQ_400K);
nrf_twim_frequency_set(config->twim->p_twim, NRF_TWIM_FREQ_400K);
break;
#if NRF_TWIM_HAS_1000_KHZ_FREQ
case I2C_SPEED_FAST_PLUS:
nrf_twim_frequency_set(config->twim.p_twim, NRF_TWIM_FREQ_1000K);
nrf_twim_frequency_set(config->twim->p_twim, NRF_TWIM_FREQ_1000K);
break;
#endif
default:
@@ -80,8 +80,6 @@ int i2c_nrfx_twim_msg_transfer(const struct device *dev, uint8_t flags, uint8_t
.p_primary_buf = buf,
.primary_length = buf_len,
};
nrfx_err_t res;
int ret = 0;
if (buf_len > config->max_transfer_size) {
LOG_ERR("Trying to transfer more than the maximum size "
@@ -90,16 +88,8 @@ int i2c_nrfx_twim_msg_transfer(const struct device *dev, uint8_t flags, uint8_t
return -ENOSPC;
}
res = nrfx_twim_xfer(&config->twim, &cur_xfer,
(flags & I2C_MSG_STOP) ? 0 : NRFX_TWIM_FLAG_TX_NO_STOP);
if (res != NRFX_SUCCESS) {
if (res == NRFX_ERROR_BUSY) {
ret = -EBUSY;
} else {
ret = -EIO;
}
}
return ret;
return nrfx_twim_xfer(config->twim, &cur_xfer,
(flags & I2C_MSG_STOP) ? 0 : NRFX_TWIM_FLAG_TX_NO_STOP);
}
void twim_nrfx_pm_resume(const struct device *dev)
@@ -107,14 +97,14 @@ void twim_nrfx_pm_resume(const struct device *dev)
const struct i2c_nrfx_twim_common_config *config = dev->config;
(void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
nrfx_twim_enable(&config->twim);
nrfx_twim_enable(config->twim);
}
void twim_nrfx_pm_suspend(const struct device *dev)
{
const struct i2c_nrfx_twim_common_config *config = dev->config;
nrfx_twim_disable(&config->twim);
nrfx_twim_disable(config->twim);
(void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
}
@@ -138,12 +128,12 @@ int i2c_nrfx_twim_common_init(const struct device *dev)
{
const struct i2c_nrfx_twim_common_config *config = dev->config;
config->irq_connect();
config->pre_init();
(void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
if (nrfx_twim_init(&config->twim, &config->twim_config, config->event_handler,
(void *)dev) != NRFX_SUCCESS) {
if (nrfx_twim_init(config->twim, &config->twim_config, config->event_handler, (void *)dev) <
0) {
LOG_ERR("Failed to initialize device: %s", dev->name);
return -EIO;
}
@@ -176,7 +166,7 @@ int i2c_nrfx_twim_common_deinit(const struct device *dev)
#endif
/* Uninit device hardware */
nrfx_twim_uninit(&config->twim);
nrfx_twim_uninit(config->twim);
return 0;
}
#endif

17
drivers/i2c/i2c_nrfx_twim_common.h
View File

@@ -28,8 +28,8 @@ extern "C" {
#define I2C(idx) DT_NODELABEL(i2c##idx)
#define I2C_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(I2C(idx), prop)
#define I2C_FREQUENCY(idx) I2C_NRFX_TWIM_FREQUENCY(DT_PROP_OR(I2C(idx), clock_frequency, \
I2C_BITRATE_STANDARD))
#define I2C_FREQUENCY(node) \
I2C_NRFX_TWIM_FREQUENCY(DT_PROP_OR(node, clock_frequency, I2C_BITRATE_STANDARD))
/* Macro determines PM actions interrupt safety level.
*
@@ -38,13 +38,14 @@ extern "C" {
* no longer ISR safe. This macro let's us check if we will be requesting/releasing
* power domains and determines PM device ISR safety value.
*/
#define I2C_PM_ISR_SAFE(idx) \
#define I2C_PM_ISR_SAFE(idx) \
COND_CODE_1( \
UTIL_AND( \
IS_ENABLED(CONFIG_PM_DEVICE_POWER_DOMAIN), \
UTIL_AND( \
DT_NODE_HAS_PROP(I2C(idx), power_domains), \
DT_NODE_HAS_STATUS_OKAY(DT_PHANDLE(I2C(idx), power_domains)) \
DT_NODE_HAS_PROP(DT_DRV_INST(idx), power_domains), \
DT_NODE_HAS_STATUS_OKAY(DT_PHANDLE(DT_DRV_INST(idx), \
power_domains)) \
) \
), \
(0), \
@@ -52,14 +53,14 @@ extern "C" {
)
struct i2c_nrfx_twim_common_config {
nrfx_twim_t twim;
nrfx_twim_config_t twim_config;
nrfx_twim_evt_handler_t event_handler;
nrfx_twim_event_handler_t event_handler;
uint16_t msg_buf_size;
void (*irq_connect)(void);
void (*pre_init)(void);
const struct pinctrl_dev_config *pcfg;
uint8_t *msg_buf;
uint16_t max_transfer_size;
nrfx_twim_t *twim;
};
int i2c_nrfx_twim_common_init(const struct device *dev);

139
drivers/i2c/i2c_nrfx_twim_rtio.c
View File

@@ -21,12 +21,15 @@
LOG_MODULE_REGISTER(i2c_nrfx_twim, CONFIG_I2C_LOG_LEVEL);
#define DT_DRV_COMPAT nordic_nrf_twim
struct i2c_nrfx_twim_rtio_config {
struct i2c_nrfx_twim_common_config common;
struct i2c_rtio *ctx;
};
struct i2c_nrfx_twim_rtio_data {
nrfx_twim_t twim;
uint8_t *user_rx_buf;
uint16_t user_rx_buf_size;
};
@@ -182,7 +185,7 @@ static void i2c_nrfx_twim_rtio_submit(const struct device *dev, struct rtio_iode
}
}
static void event_handler(nrfx_twim_evt_t const *p_event, void *p_context)
static void event_handler(nrfx_twim_event_t const *p_event, void *p_context)
{
const struct device *dev = p_context;
const struct i2c_nrfx_twim_rtio_config *config = dev->config;
@@ -219,21 +222,20 @@ static int i2c_nrfx_twim_rtio_deinit(const struct device *dev)
#endif
#define CONCAT_BUF_SIZE(idx) \
COND_CODE_1(DT_NODE_HAS_PROP(I2C(idx), zephyr_concat_buf_size), \
(DT_PROP(I2C(idx), zephyr_concat_buf_size)), (0))
COND_CODE_1(DT_NODE_HAS_PROP(DT_DRV_INST(idx), zephyr_concat_buf_size), \
(DT_INST_PROP(idx, zephyr_concat_buf_size)), (0))
#define FLASH_BUF_MAX_SIZE(idx) \
COND_CODE_1(DT_NODE_HAS_PROP(I2C(idx), zephyr_flash_buf_max_size), \
(DT_PROP(I2C(idx), zephyr_flash_buf_max_size)), (0))
COND_CODE_1(DT_NODE_HAS_PROP(DT_DRV_INST(idx), zephyr_flash_buf_max_size), \
(DT_INST_PROP(idx, zephyr_flash_buf_max_size)), (0))
#define USES_MSG_BUF(idx) \
COND_CODE_0(CONCAT_BUF_SIZE(idx), (COND_CODE_0(FLASH_BUF_MAX_SIZE(idx), (0), (1))), (1))
#define MSG_BUF_SIZE(idx) MAX(CONCAT_BUF_SIZE(idx), FLASH_BUF_MAX_SIZE(idx))
#define MSG_BUF_HAS_MEMORY_REGIONS(idx) \
DT_NODE_HAS_PROP(I2C(idx), memory_regions)
#define MSG_BUF_HAS_MEMORY_REGIONS(idx) DT_NODE_HAS_PROP(DT_DRV_INST(idx), memory_regions)
#define MSG_BUF_LINKER_REGION_NAME(idx) \
LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(I2C(idx), memory_regions))
#define MSG_BUF_LINKER_REGION_NAME(idx) \
LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(DT_DRV_INST(idx), memory_regions))
#define MSG_BUF_ATTR_SECTION(idx) \
__attribute__((__section__(MSG_BUF_LINKER_REGION_NAME(idx))))
@@ -251,122 +253,53 @@ static int i2c_nrfx_twim_rtio_deinit(const struct device *dev)
#define MSG_BUF_DEFINE(idx) \
static uint8_t MSG_BUF_SYM(idx)[MSG_BUF_SIZE(idx)] MSG_BUF_ATTR(idx)
#define MAX_TRANSFER_SIZE(idx) \
BIT_MASK(DT_PROP(I2C(idx), easydma_maxcnt_bits))
#define MAX_TRANSFER_SIZE(idx) BIT_MASK(DT_INST_PROP(idx, easydma_maxcnt_bits))
#define I2C_NRFX_TWIM_RTIO_DEVICE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(I2C(idx)); \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(I2C(idx)); \
BUILD_ASSERT(I2C_FREQUENCY(idx) != I2C_NRFX_TWIM_INVALID_FREQUENCY, \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(DT_DRV_INST(idx)); \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(DT_DRV_INST(idx)); \
BUILD_ASSERT(I2C_FREQUENCY(DT_DRV_INST(idx)) != I2C_NRFX_TWIM_INVALID_FREQUENCY, \
"Wrong I2C " #idx " frequency setting in dts"); \
static void irq_connect##idx(void) \
static struct i2c_nrfx_twim_rtio_data twim_##idx##z_data = { \
.twim = \
{ \
.p_twim = (NRF_TWIM_Type *)DT_INST_REG_ADDR(idx), \
}, \
}; \
static void pre_init##idx(void) \
{ \
IRQ_CONNECT(DT_IRQN(I2C(idx)), DT_IRQ(I2C(idx), priority), nrfx_isr, \
nrfx_twim_##idx##_irq_handler, 0); \
twim_##idx##z_data.twim.p_twim = (NRF_TWIM_Type *)DT_INST_REG_ADDR(idx); \
IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), nrfx_twim_irq_handler, \
&twim_##idx##z_data.twim, 0); \
} \
IF_ENABLED(USES_MSG_BUF(idx), (MSG_BUF_DEFINE(idx);)) \
I2C_RTIO_DEFINE(_i2c##idx##_twim_rtio, \
DT_INST_PROP_OR(n, sq_size, CONFIG_I2C_RTIO_SQ_SIZE), \
DT_INST_PROP_OR(n, cq_size, CONFIG_I2C_RTIO_CQ_SIZE)); \
PINCTRL_DT_DEFINE(I2C(idx)); \
static struct i2c_nrfx_twim_rtio_data twim_##idx##z_data; \
PINCTRL_DT_INST_DEFINE(idx); \
static const struct i2c_nrfx_twim_rtio_config twim_##idx##z_config = { \
.common = \
{ \
.twim = NRFX_TWIM_INSTANCE(idx), \
.twim_config = \
{ \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.frequency = I2C_FREQUENCY(idx), \
.frequency = I2C_FREQUENCY(DT_DRV_INST(idx)), \
}, \
.event_handler = event_handler, \
.msg_buf_size = MSG_BUF_SIZE(idx), \
.irq_connect = irq_connect##idx, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(I2C(idx)), \
.pre_init = pre_init##idx, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
IF_ENABLED(USES_MSG_BUF(idx), (.msg_buf = MSG_BUF_SYM(idx),)) \
.max_transfer_size = MAX_TRANSFER_SIZE(idx), \
.twim = &twim_##idx##z_data.twim, \
}, \
.ctx = &_i2c##idx##_twim_rtio, \
}; \
PM_DEVICE_DT_DEFINE(I2C(idx), twim_nrfx_pm_action, I2C_PM_ISR_SAFE(idx)); \
I2C_DEVICE_DT_DEINIT_DEFINE(I2C(idx), i2c_nrfx_twim_rtio_init, i2c_nrfx_twim_rtio_deinit, \
PM_DEVICE_DT_GET(I2C(idx)), &twim_##idx##z_data, \
&twim_##idx##z_config, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_nrfx_twim_driver_api);
PM_DEVICE_DT_INST_DEFINE(idx, twim_nrfx_pm_action, I2C_PM_ISR_SAFE(idx)); \
I2C_DEVICE_DT_INST_DEINIT_DEFINE(idx, i2c_nrfx_twim_rtio_init, i2c_nrfx_twim_rtio_deinit, \
PM_DEVICE_DT_INST_GET(idx), &twim_##idx##z_data, \
&twim_##idx##z_config, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, &i2c_nrfx_twim_driver_api);
#ifdef CONFIG_HAS_HW_NRF_TWIM0
I2C_NRFX_TWIM_RTIO_DEVICE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM1
I2C_NRFX_TWIM_RTIO_DEVICE(1);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM2
I2C_NRFX_TWIM_RTIO_DEVICE(2);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM3
I2C_NRFX_TWIM_RTIO_DEVICE(3);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM20
I2C_NRFX_TWIM_RTIO_DEVICE(20);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM21
I2C_NRFX_TWIM_RTIO_DEVICE(21);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM22
I2C_NRFX_TWIM_RTIO_DEVICE(22);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM23
I2C_NRFX_TWIM_RTIO_DEVICE(23);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM24
I2C_NRFX_TWIM_RTIO_DEVICE(24);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM30
I2C_NRFX_TWIM_RTIO_DEVICE(30);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM120
I2C_NRFX_TWIM_RTIO_DEVICE(120);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM130
I2C_NRFX_TWIM_RTIO_DEVICE(130);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM131
I2C_NRFX_TWIM_RTIO_DEVICE(131);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM132
I2C_NRFX_TWIM_RTIO_DEVICE(132);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM133
I2C_NRFX_TWIM_RTIO_DEVICE(133);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM134
I2C_NRFX_TWIM_RTIO_DEVICE(134);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM135
I2C_NRFX_TWIM_RTIO_DEVICE(135);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM136
I2C_NRFX_TWIM_RTIO_DEVICE(136);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM137
I2C_NRFX_TWIM_RTIO_DEVICE(137);
#endif
DT_INST_FOREACH_STATUS_OKAY(I2C_NRFX_TWIM_RTIO_DEVICE)

219
drivers/i2c/i2c_nrfx_twis.c
View File

@@ -16,26 +16,10 @@
#define DT_DRV_COMPAT nordic_nrf_twis
#define SHIM_NRF_TWIS_NODE(id) \
DT_NODELABEL(_CONCAT(i2c, id))
#define SHIM_NRF_TWIS_HAS_MEMORY_REGIONS(id) DT_NODE_HAS_PROP(DT_DRV_INST(id), memory_regions)
#define SHIM_NRF_TWIS_DEVICE_GET(id) \
DEVICE_DT_GET(SHIM_NRF_TWIS_NODE(id))
#define SHIM_NRF_TWIS_IRQ_HANDLER(id) \
_CONCAT_3(nrfx_twis_, id, _irq_handler)
#define SHIM_NRF_TWIS_IRQN(id) \
DT_IRQN(SHIM_NRF_TWIS_NODE(id))
#define SHIM_NRF_TWIS_IRQ_PRIO(id) \
DT_IRQ(SHIM_NRF_TWIS_NODE(id), priority)
#define SHIM_NRF_TWIS_HAS_MEMORY_REGIONS(id) \
DT_NODE_HAS_PROP(SHIM_NRF_TWIS_NODE(id), memory_regions)
#define SHIM_NRF_TWIS_LINKER_REGION_NAME(id) \
LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(SHIM_NRF_TWIS_NODE(id), memory_regions))
#define SHIM_NRF_TWIS_LINKER_REGION_NAME(id) \
LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(DT_DRV_INST(id), memory_regions))
#define SHIM_NRF_TWIS_BUF_ATTR_SECTION(id) \
__attribute__((__section__(SHIM_NRF_TWIS_LINKER_REGION_NAME(id))))
@@ -53,14 +37,14 @@
LOG_MODULE_REGISTER(i2c_nrfx_twis, CONFIG_I2C_LOG_LEVEL);
struct shim_nrf_twis_config {
nrfx_twis_t twis;
void (*irq_connect)(void);
void (*event_handler)(nrfx_twis_evt_t const *event);
void (*pre_init)(void);
void (*event_handler)(nrfx_twis_event_t const *event);
const struct pinctrl_dev_config *pcfg;
uint8_t *buf;
};
struct shim_nrf_twis_data {
nrfx_twis_t twis;
struct i2c_target_config *target_config;
bool enabled;
};
@@ -105,7 +89,7 @@ static void shim_nrf_twis_enable(const struct device *dev)
}
(void)pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
nrfx_twis_enable(&dev_config->twis);
nrfx_twis_enable(&dev_data->twis);
dev_data->enabled = true;
}
@@ -119,7 +103,7 @@ static void shim_nrf_twis_disable(const struct device *dev)
}
dev_data->enabled = false;
nrfx_twis_disable(&dev_config->twis);
nrfx_twis_disable(&dev_data->twis);
(void)pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_SLEEP);
}
@@ -129,10 +113,10 @@ static void shim_nrf_twis_handle_read_req(const struct device *dev)
const struct shim_nrf_twis_config *dev_config = dev->config;
struct i2c_target_config *target_config = dev_data->target_config;
const struct i2c_target_callbacks *callbacks = target_config->callbacks;
const nrfx_twis_t *twis = &dev_config->twis;
nrfx_twis_t *twis = &dev_data->twis;
uint8_t *buf;
uint32_t buf_size;
nrfx_err_t err;
int err;
if (callbacks->buf_read_requested(target_config, &buf, &buf_size)) {
LOG_ERR("no buffer provided");
@@ -147,7 +131,7 @@ static void shim_nrf_twis_handle_read_req(const struct device *dev)
memcpy(dev_config->buf, buf, buf_size);
err = nrfx_twis_tx_prepare(twis, dev_config->buf, buf_size);
if (err != NRFX_SUCCESS) {
if (err < 0) {
LOG_ERR("tx prepare failed");
return;
}
@@ -155,12 +139,13 @@ static void shim_nrf_twis_handle_read_req(const struct device *dev)
static void shim_nrf_twis_handle_write_req(const struct device *dev)
{
struct shim_nrf_twis_data *dev_data = dev->data;
const struct shim_nrf_twis_config *dev_config = dev->config;
const nrfx_twis_t *twis = &dev_config->twis;
nrfx_err_t err;
nrfx_twis_t *twis = &dev_data->twis;
int err;
err = nrfx_twis_rx_prepare(twis, dev_config->buf, SHIM_NRF_TWIS_BUF_SIZE);
if (err != NRFX_SUCCESS) {
if (err < 0) {
LOG_ERR("rx prepare failed");
return;
}
@@ -172,13 +157,12 @@ static void shim_nrf_twis_handle_write_done(const struct device *dev)
const struct shim_nrf_twis_config *dev_config = dev->config;
struct i2c_target_config *target_config = dev_data->target_config;
const struct i2c_target_callbacks *callbacks = target_config->callbacks;
const nrfx_twis_t *twis = &dev_config->twis;
nrfx_twis_t *twis = &dev_data->twis;
callbacks->buf_write_received(target_config, dev_config->buf, nrfx_twis_rx_amount(twis));
}
static void shim_nrf_twis_event_handler(const struct device *dev,
nrfx_twis_evt_t const *event)
static void shim_nrf_twis_event_handler(const struct device *dev, nrfx_twis_event_t const *event)
{
switch (event->type) {
case NRFX_TWIS_EVT_READ_REQ:
@@ -223,9 +207,8 @@ static int shim_nrf_twis_target_register(const struct device *dev,
struct i2c_target_config *target_config)
{
struct shim_nrf_twis_data *dev_data = dev->data;
const struct shim_nrf_twis_config *dev_config = dev->config;
const nrfx_twis_t *twis = &dev_config->twis;
nrfx_err_t err;
nrfx_twis_t *twis = &dev_data->twis;
int err;
const nrfx_twis_config_t config = {
.addr = {
target_config->address,
@@ -242,7 +225,7 @@ static int shim_nrf_twis_target_register(const struct device *dev,
shim_nrf_twis_disable(dev);
err = nrfx_twis_reconfigure(twis, &config);
if (err != NRFX_SUCCESS) {
if (err < 0) {
return -ENODEV;
}
@@ -276,26 +259,26 @@ const struct i2c_driver_api shim_nrf_twis_api = {
static int shim_nrf_twis_init(const struct device *dev)
{
struct shim_nrf_twis_data *dev_data = dev->data;
const struct shim_nrf_twis_config *dev_config = dev->config;
nrfx_err_t err;
int err;
const nrfx_twis_config_t config = {
.skip_gpio_cfg = true,
.skip_psel_cfg = true,
};
err = nrfx_twis_init(&dev_config->twis, &config, dev_config->event_handler);
if (err != NRFX_SUCCESS) {
dev_config->pre_init();
err = nrfx_twis_init(&dev_data->twis, &config, dev_config->event_handler);
if (err < 0) {
return -ENODEV;
}
dev_config->irq_connect();
return pm_device_driver_init(dev, shim_nrf_twis_pm_action_cb);
}
#ifdef CONFIG_DEVICE_DEINIT_SUPPORT
static int shim_nrf_twis_deinit(const struct device *dev)
{
const struct shim_nrf_twis_config *dev_config = dev->config;
struct shim_nrf_twis_data *dev_data = dev->data;
if (dev_data->target_config != NULL) {
@@ -318,7 +301,7 @@ static int shim_nrf_twis_deinit(const struct device *dev)
#endif
/* Uninit device hardware */
nrfx_twis_uninit(&dev_config->twis);
nrfx_twis_uninit(&dev_data->twis);
return 0;
}
#endif
@@ -326,120 +309,38 @@ static int shim_nrf_twis_deinit(const struct device *dev)
#define SHIM_NRF_TWIS_NAME(id, name) \
_CONCAT_4(shim_nrf_twis_, name, _, id)
#define SHIM_NRF_TWIS_DEVICE_DEFINE(id) \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(SHIM_NRF_TWIS_NODE(id)); \
static void SHIM_NRF_TWIS_NAME(id, irq_connect)(void) \
{ \
IRQ_CONNECT( \
SHIM_NRF_TWIS_IRQN(id), \
SHIM_NRF_TWIS_IRQ_PRIO(id), \
nrfx_isr, \
SHIM_NRF_TWIS_IRQ_HANDLER(id), \
0 \
); \
} \
\
static void SHIM_NRF_TWIS_NAME(id, event_handler)(nrfx_twis_evt_t const *event) \
{ \
shim_nrf_twis_event_handler(SHIM_NRF_TWIS_DEVICE_GET(id), event); \
} \
\
static struct shim_nrf_twis_data SHIM_NRF_TWIS_NAME(id, data); \
\
PINCTRL_DT_DEFINE(SHIM_NRF_TWIS_NODE(id)); \
\
static uint8_t SHIM_NRF_TWIS_NAME(id, buf) \
[SHIM_NRF_TWIS_BUF_SIZE] SHIM_NRF_TWIS_BUF_ATTR(id); \
\
static const struct shim_nrf_twis_config SHIM_NRF_TWIS_NAME(id, config) = { \
.twis = NRFX_TWIS_INSTANCE(id), \
.irq_connect = SHIM_NRF_TWIS_NAME(id, irq_connect), \
.event_handler = SHIM_NRF_TWIS_NAME(id, event_handler), \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(SHIM_NRF_TWIS_NODE(id)), \
.buf = SHIM_NRF_TWIS_NAME(id, buf), \
}; \
\
PM_DEVICE_DT_DEFINE( \
SHIM_NRF_TWIS_NODE(id), \
shim_nrf_twis_pm_action_cb, \
); \
\
DEVICE_DT_DEINIT_DEFINE( \
SHIM_NRF_TWIS_NODE(id), \
shim_nrf_twis_init, \
shim_nrf_twis_deinit, \
PM_DEVICE_DT_GET(SHIM_NRF_TWIS_NODE(id)), \
&SHIM_NRF_TWIS_NAME(id, data), \
&SHIM_NRF_TWIS_NAME(id, config), \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&shim_nrf_twis_api \
);
#define SHIM_NRF_TWIS_DEVICE_DEFINE(id) \
static struct shim_nrf_twis_data SHIM_NRF_TWIS_NAME(id, data); \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(DT_DRV_INST(id)); \
static void SHIM_NRF_TWIS_NAME(id, pre_init)(void) \
{ \
SHIM_NRF_TWIS_NAME(id, data).twis.p_reg = (NRF_TWIS_Type *)DT_INST_REG_ADDR(id); \
IRQ_CONNECT(DT_INST_IRQN(id), DT_INST_IRQ(id, priority), nrfx_twis_irq_handler, \
&SHIM_NRF_TWIS_NAME(id, data).twis, 0); \
} \
\
static void SHIM_NRF_TWIS_NAME(id, event_handler)(nrfx_twis_event_t const *event) \
{ \
shim_nrf_twis_event_handler(DEVICE_DT_INST_GET(id), event); \
} \
\
PINCTRL_DT_INST_DEFINE(id); \
\
static uint8_t SHIM_NRF_TWIS_NAME(id, \
buf)[SHIM_NRF_TWIS_BUF_SIZE] SHIM_NRF_TWIS_BUF_ATTR(id); \
\
static const struct shim_nrf_twis_config SHIM_NRF_TWIS_NAME(id, config) = { \
.pre_init = SHIM_NRF_TWIS_NAME(id, pre_init), \
.event_handler = SHIM_NRF_TWIS_NAME(id, event_handler), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(id), \
.buf = SHIM_NRF_TWIS_NAME(id, buf), \
}; \
\
PM_DEVICE_DT_INST_DEFINE(id, shim_nrf_twis_pm_action_cb,); \
\
DEVICE_DT_INST_DEINIT_DEFINE(id, shim_nrf_twis_init, shim_nrf_twis_deinit, \
PM_DEVICE_DT_INST_GET(id), &SHIM_NRF_TWIS_NAME(id, data), \
&SHIM_NRF_TWIS_NAME(id, config), POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, &shim_nrf_twis_api);
#ifdef CONFIG_HAS_HW_NRF_TWIS0
SHIM_NRF_TWIS_DEVICE_DEFINE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS1
SHIM_NRF_TWIS_DEVICE_DEFINE(1);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS2
SHIM_NRF_TWIS_DEVICE_DEFINE(2);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS3
SHIM_NRF_TWIS_DEVICE_DEFINE(3);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS20
SHIM_NRF_TWIS_DEVICE_DEFINE(20);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS21
SHIM_NRF_TWIS_DEVICE_DEFINE(21);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS22
SHIM_NRF_TWIS_DEVICE_DEFINE(22);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS23
SHIM_NRF_TWIS_DEVICE_DEFINE(23);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS24
SHIM_NRF_TWIS_DEVICE_DEFINE(24);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS30
SHIM_NRF_TWIS_DEVICE_DEFINE(30);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS130
SHIM_NRF_TWIS_DEVICE_DEFINE(130);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS131
SHIM_NRF_TWIS_DEVICE_DEFINE(131);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS133
SHIM_NRF_TWIS_DEVICE_DEFINE(133);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS134
SHIM_NRF_TWIS_DEVICE_DEFINE(134);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS135
SHIM_NRF_TWIS_DEVICE_DEFINE(135);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS136
SHIM_NRF_TWIS_DEVICE_DEFINE(136);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIS137
SHIM_NRF_TWIS_DEVICE_DEFINE(137);
#endif
DT_INST_FOREACH_STATUS_OKAY(SHIM_NRF_TWIS_DEVICE_DEFINE)

3
drivers/i2s/Kconfig.nrfx
View File

@@ -5,8 +5,7 @@ menuconfig I2S_NRFX
bool "nRF I2S nrfx driver"
default y
depends on DT_HAS_NORDIC_NRF_I2S_ENABLED
select NRFX_I2S0 if HAS_HW_NRF_I2S0
select NRFX_I2S20 if HAS_HW_NRF_I2S20
select NRFX_I2S
select PINCTRL
help
Enable support for nrfx I2S driver for nRF MCU series.

328
drivers/i2s/i2s_nrfx.c
View File

@@ -4,6 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_i2s
#include <stdlib.h>
#include <zephyr/drivers/i2s.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
@@ -33,21 +35,20 @@ struct i2s_nrfx_drv_data {
struct k_msgq tx_queue;
struct stream_cfg rx;
struct k_msgq rx_queue;
const nrfx_i2s_t *p_i2s;
nrfx_i2s_t i2s;
const uint32_t *last_tx_buffer;
enum i2s_state state;
enum i2s_dir active_dir;
bool stop; /* stop after the current (TX or RX) block */
bool discard_rx; /* discard further RX blocks */
volatile bool next_tx_buffer_needed;
bool tx_configured : 1;
bool rx_configured : 1;
bool request_clock : 1;
bool tx_configured: 1;
bool rx_configured: 1;
bool request_clock: 1;
};
struct i2s_nrfx_drv_cfg {
nrfx_i2s_data_handler_t data_handler;
nrfx_i2s_t i2s;
nrfx_i2s_config_t nrfx_def_cfg;
const struct pinctrl_dev_config *pcfg;
enum clock_source {
@@ -64,148 +65,26 @@ static void find_suitable_clock(const struct i2s_nrfx_drv_cfg *drv_cfg,
nrfx_i2s_config_t *config,
const struct i2s_config *i2s_cfg)
{
static const struct {
uint16_t ratio_val;
nrf_i2s_ratio_t ratio_enum;
} ratios[] = {
{ 32, NRF_I2S_RATIO_32X },
{ 48, NRF_I2S_RATIO_48X },
{ 64, NRF_I2S_RATIO_64X },
{ 96, NRF_I2S_RATIO_96X },
{ 128, NRF_I2S_RATIO_128X },
{ 192, NRF_I2S_RATIO_192X },
{ 256, NRF_I2S_RATIO_256X },
{ 384, NRF_I2S_RATIO_384X },
{ 512, NRF_I2S_RATIO_512X }
const nrfx_i2s_clk_params_t clk_params = {
.base_clock_freq =
(NRF_I2S_HAS_CLKCONFIG && drv_cfg->clk_src == ACLK)
/* The I2S_NRFX_DEVICE() macro contains build assertions that
* make sure that the ACLK clock source is only used when it is
* available and only with the "hfclkaudio-frequency" property
* defined, but the default value of 0 here needs to be used to
* prevent compilation errors when the property is not defined
* (this expression will be eventually optimized away then).
*/
? DT_PROP_OR(DT_NODELABEL(clock), hfclkaudio_frequency, 0)
: 32*1000*1000UL,
.transfer_rate = i2s_cfg->frame_clk_freq,
.swidth = config->sample_width,
.allow_bypass = IS_ENABLED(CONFIG_I2S_NRFX_ALLOW_MCK_BYPASS),
};
const uint32_t src_freq =
(NRF_I2S_HAS_CLKCONFIG && drv_cfg->clk_src == ACLK)
/* The I2S_NRFX_DEVICE() macro contains build assertions that
* make sure that the ACLK clock source is only used when it is
* available and only with the "hfclkaudio-frequency" property
* defined, but the default value of 0 here needs to be used to
* prevent compilation errors when the property is not defined
* (this expression will be eventually optimized away then).
*/
? DT_PROP_OR(DT_NODELABEL(clock), hfclkaudio_frequency, 0)
: 32*1000*1000UL;
uint32_t bits_per_frame = 2 * i2s_cfg->word_size;
uint32_t best_diff = UINT32_MAX;
uint8_t r, best_r = 0;
nrf_i2s_mck_t best_mck_cfg = 0;
uint32_t best_mck = 0;
#if defined(CONFIG_I2S_NRFX_ALLOW_MCK_BYPASS) && NRF_I2S_HAS_CLKCONFIG
/* Check for bypass before calculating f_MCK */
for (r = 0; r < ARRAY_SIZE(ratios); ++r) {
if (i2s_cfg->frame_clk_freq * ratios[r].ratio_val == src_freq) {
LOG_INF("MCK bypass calculated");
best_r = r;
best_mck = src_freq;
best_diff = 0;
/* Set CONFIG.MCKFREQ register to non-zero reset value to
* ensure peripheral functionality
*/
best_mck_cfg = NRF_I2S_MCK_32MDIV8;
config->enable_bypass = true;
break;
}
if (nrfx_i2s_prescalers_calc(&clk_params, &config->prescalers) != 0) {
LOG_ERR("Failed to find suitable I2S clock configuration.");
}
#endif
for (r = 0; (best_diff != 0) && (r < ARRAY_SIZE(ratios)); ++r) {
/* Only multiples of the frame width can be used as ratios. */
if ((ratios[r].ratio_val % bits_per_frame) != 0) {
continue;
}
if (IS_ENABLED(CONFIG_SOC_SERIES_NRF53X) || IS_ENABLED(CONFIG_SOC_SERIES_NRF54LX)) {
uint32_t requested_mck =
i2s_cfg->frame_clk_freq * ratios[r].ratio_val;
/* As specified in the nRF5340 PS:
*
* MCKFREQ = 4096 * floor(f_MCK * 1048576 /
* (f_source + f_MCK / 2))
* f_actual = f_source /
* floor(1048576 * 4096 / MCKFREQ)
*/
enum { MCKCONST = 1048576 };
uint32_t mck_factor =
(uint32_t)(((uint64_t)requested_mck * MCKCONST) /
(src_freq + requested_mck / 2));
/* skip cases when mck_factor is too big for dividing */
if (mck_factor > MCKCONST) {
continue;
}
uint32_t actual_mck = src_freq / (MCKCONST / mck_factor);
uint32_t lrck_freq = actual_mck / ratios[r].ratio_val;
uint32_t diff = lrck_freq >= i2s_cfg->frame_clk_freq
? (lrck_freq - i2s_cfg->frame_clk_freq)
: (i2s_cfg->frame_clk_freq - lrck_freq);
if (diff < best_diff) {
best_mck_cfg = mck_factor * 4096;
best_mck = actual_mck;
best_r = r;
best_diff = diff;
}
} else {
static const struct {
uint8_t divider_val;
nrf_i2s_mck_t divider_enum;
} dividers[] = {
{ 8, NRF_I2S_MCK_32MDIV8 },
{ 10, NRF_I2S_MCK_32MDIV10 },
{ 11, NRF_I2S_MCK_32MDIV11 },
{ 15, NRF_I2S_MCK_32MDIV15 },
{ 16, NRF_I2S_MCK_32MDIV16 },
{ 21, NRF_I2S_MCK_32MDIV21 },
{ 23, NRF_I2S_MCK_32MDIV23 },
{ 30, NRF_I2S_MCK_32MDIV30 },
{ 31, NRF_I2S_MCK_32MDIV31 },
{ 32, NRF_I2S_MCK_32MDIV32 },
{ 42, NRF_I2S_MCK_32MDIV42 },
{ 63, NRF_I2S_MCK_32MDIV63 },
{ 125, NRF_I2S_MCK_32MDIV125 }
};
for (uint8_t d = 0; (best_diff != 0) && (d < ARRAY_SIZE(dividers)); ++d) {
uint32_t mck_freq =
src_freq / dividers[d].divider_val;
uint32_t lrck_freq =
mck_freq / ratios[r].ratio_val;
uint32_t diff =
lrck_freq >= i2s_cfg->frame_clk_freq
? (lrck_freq - i2s_cfg->frame_clk_freq)
: (i2s_cfg->frame_clk_freq - lrck_freq);
if (diff < best_diff) {
best_mck_cfg = dividers[d].divider_enum;
best_mck = mck_freq;
best_r = r;
best_diff = diff;
}
/* Since dividers are in ascending order, stop
* checking next ones for the current ratio
* after resulting LRCK frequency falls below
* the one requested.
*/
if (lrck_freq < i2s_cfg->frame_clk_freq) {
break;
}
}
}
}
config->mck_setup = best_mck_cfg;
config->ratio = ratios[best_r].ratio_enum;
LOG_INF("I2S MCK frequency: %u, actual PCM rate: %u",
best_mck, best_mck / ratios[best_r].ratio_val);
}
static bool get_next_tx_buffer(struct i2s_nrfx_drv_data *drv_data,
@@ -256,7 +135,7 @@ static bool supply_next_buffers(struct i2s_nrfx_drv_data *drv_data,
if (drv_data->active_dir != I2S_DIR_TX) { /* -> RX active */
if (!get_next_rx_buffer(drv_data, next)) {
drv_data->state = I2S_STATE_ERROR;
nrfx_i2s_stop(drv_data->p_i2s);
nrfx_i2s_stop(&drv_data->i2s);
return false;
}
/* Set buffer size if there is no TX buffer (which effectively
@@ -271,7 +150,7 @@ static bool supply_next_buffers(struct i2s_nrfx_drv_data *drv_data,
drv_data->last_tx_buffer = next->p_tx_buffer;
LOG_DBG("Next buffers: %p/%p", next->p_tx_buffer, next->p_rx_buffer);
nrfx_i2s_next_buffers_set(drv_data->p_i2s, next);
nrfx_i2s_next_buffers_set(&drv_data->i2s, next);
return true;
}
@@ -303,7 +182,7 @@ static void data_handler(const struct device *dev,
}
drv_data->last_tx_buffer = NULL;
}
nrfx_i2s_uninit(drv_data->p_i2s);
nrfx_i2s_uninit(&drv_data->i2s);
if (drv_data->request_clock) {
(void)onoff_release(drv_data->clk_mgr);
}
@@ -320,7 +199,7 @@ static void data_handler(const struct device *dev,
LOG_ERR("Next buffers not supplied on time");
drv_data->state = I2S_STATE_ERROR;
}
nrfx_i2s_stop(drv_data->p_i2s);
nrfx_i2s_stop(&drv_data->i2s);
return;
}
@@ -370,7 +249,7 @@ static void data_handler(const struct device *dev,
}
if (stop_transfer) {
nrfx_i2s_stop(drv_data->p_i2s);
nrfx_i2s_stop(&drv_data->i2s);
} else if (status & NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED) {
nrfx_i2s_buffers_t next = { 0 };
@@ -541,8 +420,7 @@ static int i2s_nrfx_configure(const struct device *dev, enum i2s_dir dir,
* the MCK output is used), find a suitable clock configuration for it.
*/
if (nrfx_cfg.mode == NRF_I2S_MODE_MASTER ||
(nrf_i2s_mck_pin_get(drv_cfg->i2s.p_reg) & I2S_PSEL_MCK_CONNECT_Msk)
== I2S_PSEL_MCK_CONNECT_Connected << I2S_PSEL_MCK_CONNECT_Pos) {
nrf_i2s_mck_pin_connected_check(drv_data->i2s.p_reg)) {
find_suitable_clock(drv_cfg, &nrfx_cfg, i2s_cfg);
/* Unless the PCLK32M source is used with the HFINT oscillator
* (which is always available without any additional actions),
@@ -551,7 +429,7 @@ static int i2s_nrfx_configure(const struct device *dev, enum i2s_dir dir,
*/
drv_data->request_clock = (drv_cfg->clk_src != PCLK32M);
} else {
nrfx_cfg.mck_setup = NRF_I2S_MCK_DISABLED;
nrfx_cfg.prescalers.mck_setup = NRF_I2S_MCK_DISABLED;
drv_data->request_clock = false;
}
@@ -700,7 +578,7 @@ static int start_transfer(struct i2s_nrfx_drv_data *drv_data)
/* Failed to allocate next RX buffer */
ret = -ENOMEM;
} else {
nrfx_err_t err;
int err;
/* It is necessary to set buffer size here only for I2S_DIR_RX,
* because only then the get_next_tx_buffer() call in the if
@@ -713,16 +591,16 @@ static int start_transfer(struct i2s_nrfx_drv_data *drv_data)
drv_data->last_tx_buffer = initial_buffers.p_tx_buffer;
err = nrfx_i2s_start(drv_data->p_i2s, &initial_buffers, 0);
if (err == NRFX_SUCCESS) {
err = nrfx_i2s_start(&drv_data->i2s, &initial_buffers, 0);
if (err == 0) {
return 0;
}
LOG_ERR("Failed to start I2S transfer: 0x%08x", err);
LOG_ERR("Failed to start I2S transfer: %d", err);
ret = -EIO;
}
nrfx_i2s_uninit(drv_data->p_i2s);
nrfx_i2s_uninit(&drv_data->i2s);
if (drv_data->request_clock) {
(void)onoff_release(drv_data->clk_mgr);
}
@@ -751,7 +629,7 @@ static void clock_started_callback(struct onoff_manager *mgr,
* the actual transfer in such case.
*/
if (drv_data->state == I2S_STATE_READY) {
nrfx_i2s_uninit(drv_data->p_i2s);
nrfx_i2s_uninit(&drv_data->i2s);
(void)onoff_release(drv_data->clk_mgr);
} else {
(void)start_transfer(drv_data);
@@ -762,25 +640,25 @@ static int trigger_start(const struct device *dev)
{
struct i2s_nrfx_drv_data *drv_data = dev->data;
const struct i2s_nrfx_drv_cfg *drv_cfg = dev->config;
nrfx_err_t err;
int err;
int ret;
const nrfx_i2s_config_t *nrfx_cfg = (drv_data->active_dir == I2S_DIR_TX)
? &drv_data->tx.nrfx_cfg
: &drv_data->rx.nrfx_cfg;
err = nrfx_i2s_init(drv_data->p_i2s, nrfx_cfg, drv_cfg->data_handler);
if (err != NRFX_SUCCESS) {
LOG_ERR("Failed to initialize I2S: 0x%08x", err);
err = nrfx_i2s_init(&drv_data->i2s, nrfx_cfg, drv_cfg->data_handler);
if (err != 0) {
LOG_ERR("Failed to initialize I2S: %d", err);
return -EIO;
}
drv_data->state = I2S_STATE_RUNNING;
#if NRF_I2S_HAS_CLKCONFIG
nrf_i2s_clk_configure(drv_cfg->i2s.p_reg,
nrf_i2s_clk_configure(drv_data->i2s.p_reg,
drv_cfg->clk_src == ACLK ? NRF_I2S_CLKSRC_ACLK
: NRF_I2S_CLKSRC_PCLK32M,
nrfx_cfg->enable_bypass);
nrfx_cfg->prescalers.enable_bypass);
#endif
/* If it is required to use certain HF clock, request it to be running
@@ -791,7 +669,7 @@ static int trigger_start(const struct device *dev)
clock_started_callback);
ret = onoff_request(drv_data->clk_mgr, &drv_data->clk_cli);
if (ret < 0) {
nrfx_i2s_uninit(drv_data->p_i2s);
nrfx_i2s_uninit(&drv_data->i2s);
drv_data->state = I2S_STATE_READY;
LOG_ERR("Failed to request clock: %d", ret);
@@ -898,7 +776,7 @@ static int i2s_nrfx_trigger(const struct device *dev,
case I2S_TRIGGER_DROP:
if (drv_data->state != I2S_STATE_READY) {
drv_data->discard_rx = true;
nrfx_i2s_stop(drv_data->p_i2s);
nrfx_i2s_stop(&drv_data->i2s);
}
purge_queue(dev, dir);
drv_data->state = I2S_STATE_READY;
@@ -943,72 +821,56 @@ static DEVICE_API(i2s, i2s_nrf_drv_api) = {
.trigger = i2s_nrfx_trigger,
};
#define I2S(idx) DT_NODELABEL(i2s##idx)
#define I2S_CLK_SRC(idx) DT_STRING_TOKEN(I2S(idx), clock_source)
#define I2S_CLK_SRC(inst) DT_STRING_TOKEN(DT_DRV_INST(inst), clock_source)
#define I2S_NRFX_DEVICE(idx) \
static struct i2s_buf tx_msgs##idx[CONFIG_I2S_NRFX_TX_BLOCK_COUNT]; \
static struct i2s_buf rx_msgs##idx[CONFIG_I2S_NRFX_RX_BLOCK_COUNT]; \
static void data_handler##idx(nrfx_i2s_buffers_t const *p_released, \
uint32_t status) \
{ \
data_handler(DEVICE_DT_GET(I2S(idx)), p_released, status); \
} \
PINCTRL_DT_DEFINE(I2S(idx)); \
static const struct i2s_nrfx_drv_cfg i2s_nrfx_cfg##idx = { \
.data_handler = data_handler##idx, \
.i2s = NRFX_I2S_INSTANCE(idx), \
.nrfx_def_cfg = NRFX_I2S_DEFAULT_CONFIG( \
NRF_I2S_PIN_NOT_CONNECTED, \
NRF_I2S_PIN_NOT_CONNECTED, \
NRF_I2S_PIN_NOT_CONNECTED, \
NRF_I2S_PIN_NOT_CONNECTED, \
NRF_I2S_PIN_NOT_CONNECTED), \
.nrfx_def_cfg.skip_gpio_cfg = true, \
.nrfx_def_cfg.skip_psel_cfg = true, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(I2S(idx)), \
.clk_src = I2S_CLK_SRC(idx), \
}; \
static struct i2s_nrfx_drv_data i2s_nrfx_data##idx = { \
.state = I2S_STATE_READY, \
.p_i2s = &i2s_nrfx_cfg##idx.i2s \
}; \
static int i2s_nrfx_init##idx(const struct device *dev) \
{ \
IRQ_CONNECT(DT_IRQN(I2S(idx)), DT_IRQ(I2S(idx), priority), \
nrfx_isr, nrfx_i2s_##idx##_irq_handler, 0); \
const struct i2s_nrfx_drv_cfg *drv_cfg = dev->config; \
int err = pinctrl_apply_state(drv_cfg->pcfg, \
PINCTRL_STATE_DEFAULT); \
if (err < 0) { \
return err; \
} \
k_msgq_init(&i2s_nrfx_data##idx.tx_queue, \
(char *)tx_msgs##idx, sizeof(struct i2s_buf), \
ARRAY_SIZE(tx_msgs##idx)); \
k_msgq_init(&i2s_nrfx_data##idx.rx_queue, \
(char *)rx_msgs##idx, sizeof(struct i2s_buf), \
ARRAY_SIZE(rx_msgs##idx)); \
init_clock_manager(dev); \
return 0; \
} \
BUILD_ASSERT(I2S_CLK_SRC(idx) != ACLK || \
(NRF_I2S_HAS_CLKCONFIG && NRF_CLOCK_HAS_HFCLKAUDIO), \
"Clock source ACLK is not available."); \
BUILD_ASSERT(I2S_CLK_SRC(idx) != ACLK || \
DT_NODE_HAS_PROP(DT_NODELABEL(clock), \
hfclkaudio_frequency), \
"Clock source ACLK requires the hfclkaudio-frequency " \
"property to be defined in the nordic,nrf-clock node."); \
DEVICE_DT_DEFINE(I2S(idx), i2s_nrfx_init##idx, NULL, \
&i2s_nrfx_data##idx, &i2s_nrfx_cfg##idx, \
POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, \
&i2s_nrf_drv_api);
#define I2S_NRFX_DEVICE(inst) \
static struct i2s_buf tx_msgs##inst[CONFIG_I2S_NRFX_TX_BLOCK_COUNT]; \
static struct i2s_buf rx_msgs##inst[CONFIG_I2S_NRFX_RX_BLOCK_COUNT]; \
static void data_handler##inst(nrfx_i2s_buffers_t const *p_released, uint32_t status) \
{ \
data_handler(DEVICE_DT_GET(DT_DRV_INST(inst)), p_released, status); \
} \
PINCTRL_DT_DEFINE(DT_DRV_INST(inst)); \
static const struct i2s_nrfx_drv_cfg i2s_nrfx_cfg##inst = { \
.data_handler = data_handler##inst, \
.nrfx_def_cfg = NRFX_I2S_DEFAULT_CONFIG( \
NRF_I2S_PIN_NOT_CONNECTED, NRF_I2S_PIN_NOT_CONNECTED, \
NRF_I2S_PIN_NOT_CONNECTED, NRF_I2S_PIN_NOT_CONNECTED, \
NRF_I2S_PIN_NOT_CONNECTED), \
.nrfx_def_cfg.skip_gpio_cfg = true, \
.nrfx_def_cfg.skip_psel_cfg = true, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_DRV_INST(inst)), \
.clk_src = I2S_CLK_SRC(inst), \
}; \
static struct i2s_nrfx_drv_data i2s_nrfx_data##inst = { \
.state = I2S_STATE_READY, \
.i2s = NRFX_I2S_INSTANCE(DT_INST_REG_ADDR(inst)), \
}; \
static int i2s_nrfx_init##inst(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), nrfx_i2s_irq_handler, \
&i2s_nrfx_data##inst.i2s, 0); \
const struct i2s_nrfx_drv_cfg *drv_cfg = dev->config; \
int err = pinctrl_apply_state(drv_cfg->pcfg, PINCTRL_STATE_DEFAULT); \
if (err < 0) { \
return err; \
} \
k_msgq_init(&i2s_nrfx_data##inst.tx_queue, (char *)tx_msgs##inst, \
sizeof(struct i2s_buf), ARRAY_SIZE(tx_msgs##inst)); \
k_msgq_init(&i2s_nrfx_data##inst.rx_queue, (char *)rx_msgs##inst, \
sizeof(struct i2s_buf), ARRAY_SIZE(rx_msgs##inst)); \
init_clock_manager(dev); \
return 0; \
} \
BUILD_ASSERT(I2S_CLK_SRC(inst) != ACLK || \
(NRF_I2S_HAS_CLKCONFIG && NRF_CLOCK_HAS_HFCLKAUDIO), \
"Clock source ACLK is not available."); \
BUILD_ASSERT(I2S_CLK_SRC(inst) != ACLK || \
DT_NODE_HAS_PROP(DT_NODELABEL(clock), hfclkaudio_frequency), \
"Clock source ACLK requires the hfclkaudio-frequency " \
"property to be defined in the nordic,nrf-clock node."); \
DEVICE_DT_INST_DEFINE(inst, i2s_nrfx_init##inst, NULL, &i2s_nrfx_data##inst, \
&i2s_nrfx_cfg##inst, POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, \
&i2s_nrf_drv_api);
#ifdef CONFIG_HAS_HW_NRF_I2S0
I2S_NRFX_DEVICE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_I2S20
I2S_NRFX_DEVICE(20);
#endif
DT_INST_FOREACH_STATUS_OKAY(I2S_NRFX_DEVICE)

2
drivers/mspi/mspi_dw_vendor_specific.h
View File

@@ -12,7 +12,7 @@
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_exmif)
#include <nrf.h>
#include <nrfx.h>
static inline void vendor_specific_init(const struct device *dev)
{

13
drivers/pwm/Kconfig.nrfx
View File

@@ -5,18 +5,7 @@ config PWM_NRFX
bool "nRF PWM nrfx driver"
default y
depends on DT_HAS_NORDIC_NRF_PWM_ENABLED
select NRFX_PWM0 if HAS_HW_NRF_PWM0
select NRFX_PWM1 if HAS_HW_NRF_PWM1
select NRFX_PWM2 if HAS_HW_NRF_PWM2
select NRFX_PWM3 if HAS_HW_NRF_PWM3
select NRFX_PWM20 if HAS_HW_NRF_PWM20
select NRFX_PWM21 if HAS_HW_NRF_PWM21
select NRFX_PWM22 if HAS_HW_NRF_PWM22
select NRFX_PWM120 if HAS_HW_NRF_PWM120
select NRFX_PWM130 if HAS_HW_NRF_PWM130
select NRFX_PWM131 if HAS_HW_NRF_PWM131
select NRFX_PWM132 if HAS_HW_NRF_PWM132
select NRFX_PWM133 if HAS_HW_NRF_PWM133
select NRFX_PWM
select PINCTRL
help
Enable support for nrfx Hardware PWM driver for nRF52 MCU series.

69
drivers/pwm/pwm_nrf_sw.c
View File

@@ -14,6 +14,7 @@
#include <hal/nrf_gpio.h>
#include <hal/nrf_rtc.h>
#include <hal/nrf_timer.h>
#include <gpiote_nrfx.h>
#include <zephyr/logging/log.h>
@@ -62,7 +63,7 @@ struct pwm_config {
NRF_RTC_Type *rtc;
NRF_TIMER_Type *timer;
};
nrfx_gpiote_t gpiote[PWM_0_MAP_SIZE];
nrfx_gpiote_t *gpiote[PWM_0_MAP_SIZE];
uint8_t psel_ch[PWM_0_MAP_SIZE];
uint8_t initially_inverted;
uint8_t map_size;
@@ -72,8 +73,9 @@ struct pwm_config {
struct pwm_data {
uint32_t period_cycles;
uint32_t pulse_cycles[PWM_0_MAP_SIZE];
uint8_t ppi_ch[PWM_0_MAP_SIZE][PPI_PER_CH];
nrfx_gppi_handle_t ppi_h[PWM_0_MAP_SIZE][PPI_PER_CH];
uint8_t gpiote_ch[PWM_0_MAP_SIZE];
uint32_t ppi_ch_mask[PWM_0_MAP_SIZE];
};
static inline NRF_RTC_Type *pwm_config_rtc(const struct pwm_config *config)
@@ -126,11 +128,11 @@ static int pwm_nrf_sw_set_cycles(const struct device *dev, uint32_t channel,
NRF_RTC_Type *rtc = pwm_config_rtc(config);
NRF_GPIOTE_Type *gpiote;
struct pwm_data *data = dev->data;
uint32_t ppi_mask;
uint8_t active_level;
uint8_t psel_ch;
uint8_t gpiote_ch;
const uint8_t *ppi_chs;
const nrfx_gppi_handle_t *ppi_chs;
uint32_t src_d = nrfx_gppi_domain_id_get(USE_RTC ? (uint32_t)rtc : (uint32_t)timer);
int ret;
if (channel >= config->map_size) {
@@ -163,18 +165,16 @@ static int pwm_nrf_sw_set_cycles(const struct device *dev, uint32_t channel,
}
}
gpiote = config->gpiote[channel].p_reg;
gpiote = config->gpiote[channel]->p_reg;
psel_ch = config->psel_ch[channel];
gpiote_ch = data->gpiote_ch[channel];
ppi_chs = data->ppi_ch[channel];
ppi_chs = data->ppi_h[channel];
LOG_DBG("channel %u, period %u, pulse %u",
channel, period_cycles, pulse_cycles);
/* clear PPI used */
ppi_mask = BIT(ppi_chs[0]) | BIT(ppi_chs[1]) |
(PPI_PER_CH > 2 ? BIT(ppi_chs[2]) : 0);
nrfx_gppi_channels_disable(ppi_mask);
/* disable PPI used */
nrfx_gppi_channels_disable(src_d, data->ppi_ch_mask[channel]);
active_level = (flags & PWM_POLARITY_INVERTED) ? 0 : 1;
@@ -278,12 +278,10 @@ static int pwm_nrf_sw_set_cycles(const struct device *dev, uint32_t channel,
nrf_rtc_compare_event_get(0));
#if PPI_FORK_AVAILABLE
nrfx_gppi_fork_endpoint_setup(ppi_chs[1],
clear_task_address);
nrfx_gppi_ep_attach(clear_task_address, ppi_chs[1]);
#else
nrfx_gppi_channel_endpoints_setup(ppi_chs[2],
period_end_event_address,
clear_task_address);
nrfx_gppi_ep_attach(period_end_event_address, ppi_chs[2]);
nrfx_gppi_ep_attach(clear_task_address, ppi_chs[2]);
#endif
} else {
pulse_end_event_address =
@@ -294,13 +292,13 @@ static int pwm_nrf_sw_set_cycles(const struct device *dev, uint32_t channel,
nrf_timer_compare_event_get(0));
}
nrfx_gppi_channel_endpoints_setup(ppi_chs[0],
pulse_end_event_address,
pulse_end_task_address);
nrfx_gppi_channel_endpoints_setup(ppi_chs[1],
period_end_event_address,
period_end_task_address);
nrfx_gppi_channels_enable(ppi_mask);
nrfx_gppi_ep_attach(pulse_end_event_address, ppi_chs[0]);
nrfx_gppi_ep_attach(pulse_end_task_address, ppi_chs[0]);
nrfx_gppi_ep_attach(period_end_event_address, ppi_chs[1]);
nrfx_gppi_ep_attach(period_end_task_address, ppi_chs[1]);
nrfx_gppi_channels_enable(src_d, data->ppi_ch_mask[channel]);
/* start timer, hence PWM */
if (USE_RTC) {
@@ -351,28 +349,37 @@ static int pwm_nrf_sw_init(const struct device *dev)
NRF_RTC_Type *rtc = pwm_config_rtc(config);
for (uint32_t i = 0; i < config->map_size; i++) {
nrfx_err_t err;
uint32_t src_d = nrfx_gppi_domain_id_get(USE_RTC ? (uint32_t)rtc : (uint32_t)timer);
uint32_t dst_d = nrfx_gppi_domain_id_get((uint32_t)config->gpiote[i]->p_reg);
int rv;
/* Allocate resources. */
for (uint32_t j = 0; j < PPI_PER_CH; j++) {
err = nrfx_gppi_channel_alloc(&data->ppi_ch[i][j]);
if (err != NRFX_SUCCESS) {
int ch;
rv = nrfx_gppi_domain_conn_alloc(src_d, dst_d, &data->ppi_h[i][j]);
if (rv < 0) {
/* Do not free allocated resource. It is a fatal condition,
* system requires reconfiguration.
*/
LOG_ERR("Failed to allocate PPI channel");
return -ENOMEM;
return rv;
}
/* Enable connection but at the end disable channel on the source domain. */
nrfx_gppi_conn_enable(data->ppi_h[i][j]);
ch = nrfx_gppi_domain_channel_get(data->ppi_h[i][j], src_d);
__ASSERT_NO_MSG(ch >= 0);
data->ppi_ch_mask[i] |= BIT(ch);
}
nrfx_gppi_channels_disable(src_d, data->ppi_ch_mask[i]);
err = nrfx_gpiote_channel_alloc(&config->gpiote[i],
&data->gpiote_ch[i]);
if (err != NRFX_SUCCESS) {
rv = nrfx_gpiote_channel_alloc(config->gpiote[i], &data->gpiote_ch[i]);
if (rv < 0) {
/* Do not free allocated resource. It is a fatal condition,
* system requires reconfiguration.
*/
LOG_ERR("Failed to allocate GPIOTE channel");
return -ENOMEM;
return rv;
}
/* Set initial state of the output pins. */
@@ -410,7 +417,7 @@ static int pwm_nrf_sw_init(const struct device *dev)
? BIT(_idx) : 0) |
#define GPIOTE_AND_COMMA(_node_id, _prop, _idx) \
NRFX_GPIOTE_INSTANCE(NRF_DT_GPIOTE_INST_BY_IDX(_node_id, _prop, _idx)),
&GPIOTE_NRFX_INST_BY_NODE(NRF_DT_GPIOTE_NODE_BY_IDX(_node_id, _prop, _idx))
static const struct pwm_config pwm_nrf_sw_0_config = {
COND_CODE_1(USE_RTC, (.rtc), (.timer)) = GENERATOR_ADDR,

206
drivers/pwm/pwm_nrfx.c
View File

@@ -3,6 +3,9 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_pwm
#include <nrfx_pwm.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/pm/device.h>
@@ -18,31 +21,12 @@
LOG_MODULE_REGISTER(pwm_nrfx, CONFIG_PWM_LOG_LEVEL);
/* NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED can be undefined or defined
* to 0 or 1, hence the use of #if IS_ENABLED().
*/
#if IS_ENABLED(NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED)
#define ANOMALY_109_EGU_IRQ_CONNECT(idx) _EGU_IRQ_CONNECT(idx)
#define _EGU_IRQ_CONNECT(idx) \
extern void nrfx_egu_##idx##_irq_handler(void); \
IRQ_CONNECT(DT_IRQN(DT_NODELABEL(egu##idx)), \
DT_IRQ(DT_NODELABEL(egu##idx), priority), \
nrfx_isr, nrfx_egu_##idx##_irq_handler, 0)
#else
#define ANOMALY_109_EGU_IRQ_CONNECT(idx)
#endif
#define PWM(dev_idx) DT_NODELABEL(pwm##dev_idx)
#define PWM_PROP(dev_idx, prop) DT_PROP(PWM(dev_idx), prop)
#define PWM_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(PWM(idx), prop)
#define PWM_NRFX_CH_POLARITY_MASK BIT(15)
#define PWM_NRFX_CH_COMPARE_MASK BIT_MASK(15)
#define PWM_NRFX_CH_VALUE(compare_value, inverted) \
(compare_value | (inverted ? 0 : PWM_NRFX_CH_POLARITY_MASK))
struct pwm_nrfx_config {
nrfx_pwm_t pwm;
nrfx_pwm_config_t initial_config;
nrf_pwm_sequence_t seq;
const struct pinctrl_dev_config *pcfg;
@@ -53,12 +37,49 @@ struct pwm_nrfx_config {
};
struct pwm_nrfx_data {
nrfx_pwm_t pwm;
uint32_t period_cycles;
/* Bit mask indicating channels that need the PWM generation. */
uint8_t pwm_needed;
uint8_t prescaler;
bool stop_requested;
};
#if NRF_ERRATA_STATIC_CHECK(52, 109)
/* Forward-declare pwm_nrfx_<inst>_data structs to be able to access nrfx_pwm_t needed for the
* workaround.
*/
#define _PWM_DATA_STRUCT_NAME_GET(inst) pwm_nrfx_##inst##_data
#define _PWM_DATA_STRUCT_DECLARE(inst) static struct pwm_nrfx_data _PWM_DATA_STRUCT_NAME_GET(inst);
DT_INST_FOREACH_STATUS_OKAY(_PWM_DATA_STRUCT_DECLARE);
/* Create an array of pointers to all active PWM instances to loop over them in an EGU interrupt
* handler.
*/
#define _PWM_DATA_STRUCT_PWM_PTR_COMMA_GET(inst) &_PWM_DATA_STRUCT_NAME_GET(inst).pwm,
static nrfx_pwm_t *pwm_instances[] = {
DT_INST_FOREACH_STATUS_OKAY(_PWM_DATA_STRUCT_PWM_PTR_COMMA_GET)
};
/* Define an interrupt handler for the EGU instance used by the workaround which calls
* nrfx_pwm_nrf52_anomaly_109_handler for all active PWM instances.
*/
void anomaly_109_egu_handler(void)
{
for (int i = 0; i < ARRAY_SIZE(pwm_instances); i++) {
nrfx_pwm_nrf52_anomaly_109_handler(pwm_instances[i]);
}
}
#define ANOMALY_109_EGU_IRQ_CONNECT(idx) _EGU_IRQ_CONNECT(idx)
#define _EGU_IRQ_CONNECT(idx) \
IRQ_CONNECT(DT_IRQN(DT_NODELABEL(egu##idx)), \
DT_IRQ(DT_NODELABEL(egu##idx), priority), \
anomaly_109_egu_handler, 0, 0)
#else
#define ANOMALY_109_EGU_IRQ_CONNECT(idx)
#endif
/* Ensure the pwm_needed bit mask can accommodate all available channels. */
#if (NRF_PWM_CHANNEL_COUNT > 8)
#error "Current implementation supports maximum 8 channels."
@@ -71,9 +92,9 @@ static uint16_t *seq_values_ptr_get(const struct device *dev)
return (uint16_t *)config->seq.values.p_raw;
}
static void pwm_handler(nrfx_pwm_evt_type_t event_type, void *p_context)
static void pwm_handler(nrfx_pwm_event_type_t event, void *p_context)
{
ARG_UNUSED(event_type);
ARG_UNUSED(event);
ARG_UNUSED(p_context);
}
@@ -111,7 +132,7 @@ static bool pwm_period_check_and_set(const struct device *dev,
data->period_cycles = period_cycles;
data->prescaler = prescaler;
nrf_pwm_configure(config->pwm.p_reg,
nrf_pwm_configure(data->pwm.p_reg,
data->prescaler,
config->initial_config.count_mode,
(uint16_t)countertop);
@@ -126,10 +147,9 @@ static bool pwm_period_check_and_set(const struct device *dev,
return false;
}
static bool channel_psel_get(uint32_t channel, uint32_t *psel,
const struct pwm_nrfx_config *config)
static bool channel_psel_get(uint32_t channel, uint32_t *psel, struct pwm_nrfx_data *data)
{
*psel = nrf_pwm_pin_get(config->pwm.p_reg, (uint8_t)channel);
*psel = nrf_pwm_pin_get(data->pwm.p_reg, (uint8_t)channel);
return (((*psel & PWM_PSEL_OUT_CONNECT_Msk) >> PWM_PSEL_OUT_CONNECT_Pos)
== PWM_PSEL_OUT_CONNECT_Connected);
@@ -137,12 +157,12 @@ static bool channel_psel_get(uint32_t channel, uint32_t *psel,
static int stop_pwm(const struct device *dev)
{
const struct pwm_nrfx_config *config = dev->config;
struct pwm_nrfx_data *data = dev->data;
/* Don't wait here for the peripheral to actually stop. Instead,
* ensure it is stopped before starting the next playback.
*/
nrfx_pwm_stop(&config->pwm, false);
* ensure it is stopped before starting the next playback.
*/
nrfx_pwm_stop(&data->pwm, false);
return 0;
}
@@ -218,7 +238,7 @@ static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
if (!needs_pwm) {
uint32_t psel;
if (channel_psel_get(channel, &psel, config)) {
if (channel_psel_get(channel, &psel, data)) {
uint32_t out_level = (pulse_cycles == 0) ? 0 : 1;
if (inverted) {
@@ -257,7 +277,7 @@ static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
* and till that moment, it ignores any start requests,
* so ensure here that it is stopped.
*/
while (!nrfx_pwm_stopped_check(&config->pwm)) {
while (!nrfx_pwm_stopped_check(&data->pwm)) {
}
}
@@ -266,7 +286,7 @@ static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
* until another playback is requested (new values will be
* loaded then) or the PWM peripheral is stopped.
*/
nrfx_pwm_simple_playback(&config->pwm, &config->seq, 1,
nrfx_pwm_simple_playback(&data->pwm, &config->seq, 1,
NRFX_PWM_FLAG_NO_EVT_FINISHED);
}
@@ -291,6 +311,8 @@ static DEVICE_API(pwm, pwm_nrfx_drv_api_funcs) = {
static int pwm_resume(const struct device *dev)
{
const struct pwm_nrfx_config *config = dev->config;
struct pwm_nrfx_data *data = dev->data;
uint8_t initially_inverted = 0;
(void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
@@ -298,7 +320,7 @@ static int pwm_resume(const struct device *dev)
for (size_t i = 0; i < NRF_PWM_CHANNEL_COUNT; i++) {
uint32_t psel;
if (channel_psel_get(i, &psel, config)) {
if (channel_psel_get(i, &psel, data)) {
/* Mark channels as inverted according to what initial
* state of their outputs has been set by pinctrl (high
* idle state means that the channel is inverted).
@@ -320,6 +342,7 @@ static int pwm_resume(const struct device *dev)
static int pwm_suspend(const struct device *dev)
{
const struct pwm_nrfx_config *config = dev->config;
struct pwm_nrfx_data *data = dev->data;
int ret = stop_pwm(dev);
@@ -328,7 +351,7 @@ static int pwm_suspend(const struct device *dev)
return ret;
}
while (!nrfx_pwm_stopped_check(&config->pwm)) {
while (!nrfx_pwm_stopped_check(&data->pwm)) {
}
memset(dev->data, 0, sizeof(struct pwm_nrfx_data));
@@ -354,7 +377,9 @@ static int pwm_nrfx_pm_action(const struct device *dev,
static int pwm_nrfx_init(const struct device *dev)
{
const struct pwm_nrfx_config *config = dev->config;
nrfx_err_t err;
struct pwm_nrfx_data *data = dev->data;
int err;
ANOMALY_109_EGU_IRQ_CONNECT(NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE);
@@ -362,71 +387,70 @@ static int pwm_nrfx_init(const struct device *dev)
(void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
}
err = nrfx_pwm_init(&config->pwm, &config->initial_config, pwm_handler, dev->data);
if (err != NRFX_SUCCESS) {
err = nrfx_pwm_init(&data->pwm, &config->initial_config, pwm_handler, dev->data);
if (err < 0) {
LOG_ERR("Failed to initialize device: %s", dev->name);
return -EBUSY;
return err;
}
return pm_device_driver_init(dev, pwm_nrfx_pm_action);
}
#define PWM_MEM_REGION(idx) DT_PHANDLE(PWM(idx), memory_regions)
#define PWM_MEM_REGION(inst) DT_PHANDLE(DT_DRV_INST(inst), memory_regions)
#define PWM_MEMORY_SECTION(idx) \
COND_CODE_1(PWM_HAS_PROP(idx, memory_regions), \
#define PWM_MEMORY_SECTION(inst) \
COND_CODE_1(DT_NODE_HAS_PROP(DT_DRV_INST(inst), memory_regions), \
(__attribute__((__section__(LINKER_DT_NODE_REGION_NAME( \
PWM_MEM_REGION(idx)))))), \
PWM_MEM_REGION(inst)))))), \
())
#define PWM_GET_MEM_ATTR(idx) \
COND_CODE_1(PWM_HAS_PROP(idx, memory_regions), \
(DT_PROP_OR(PWM_MEM_REGION(idx), zephyr_memory_attr, 0)), (0))
#define PWM_GET_MEM_ATTR(inst) \
COND_CODE_1(DT_NODE_HAS_PROP(DT_DRV_INST(inst), memory_regions), \
(DT_PROP_OR(PWM_MEM_REGION(inst), zephyr_memory_attr, 0)), (0))
#define PWM_NRFX_DEVICE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(PWM(idx)); \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(PWM(idx)); \
static struct pwm_nrfx_data pwm_nrfx_##idx##_data; \
static uint16_t pwm_##idx##_seq_values[NRF_PWM_CHANNEL_COUNT] \
PWM_MEMORY_SECTION(idx); \
PINCTRL_DT_DEFINE(PWM(idx)); \
static const struct pwm_nrfx_config pwm_nrfx_##idx##_config = { \
.pwm = NRFX_PWM_INSTANCE(idx), \
.initial_config = { \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.base_clock = NRF_PWM_CLK_1MHz, \
.count_mode = (PWM_PROP(idx, center_aligned) \
? NRF_PWM_MODE_UP_AND_DOWN \
: NRF_PWM_MODE_UP), \
.top_value = 1000, \
.load_mode = NRF_PWM_LOAD_INDIVIDUAL, \
.step_mode = NRF_PWM_STEP_TRIGGERED, \
}, \
.seq.values.p_raw = pwm_##idx##_seq_values, \
.seq.length = NRF_PWM_CHANNEL_COUNT, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(PWM(idx)), \
.clock_freq = COND_CODE_1(DT_CLOCKS_HAS_IDX(PWM(idx), 0), \
(DT_PROP(DT_CLOCKS_CTLR(PWM(idx)), clock_frequency)), \
(16ul * 1000ul * 1000ul)), \
IF_ENABLED(CONFIG_DCACHE, \
(.mem_attr = PWM_GET_MEM_ATTR(idx),)) \
}; \
static int pwm_nrfx_init##idx(const struct device *dev) \
{ \
IRQ_CONNECT(DT_IRQN(PWM(idx)), DT_IRQ(PWM(idx), priority), \
nrfx_isr, nrfx_pwm_##idx##_irq_handler, 0); \
return pwm_nrfx_init(dev); \
}; \
PM_DEVICE_DT_DEFINE(PWM(idx), pwm_nrfx_pm_action); \
DEVICE_DT_DEFINE(PWM(idx), \
pwm_nrfx_init##idx, PM_DEVICE_DT_GET(PWM(idx)), \
&pwm_nrfx_##idx##_data, \
&pwm_nrfx_##idx##_config, \
POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
&pwm_nrfx_drv_api_funcs)
#define PWM_NRFX_DEFINE(inst) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(DT_DRV_INST(inst)); \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(DT_DRV_INST(inst)); \
static struct pwm_nrfx_data pwm_nrfx_##inst##_data = { \
.pwm = NRFX_PWM_INSTANCE(DT_INST_REG_ADDR(inst)), \
}; \
static uint16_t pwm_##inst##_seq_values[NRF_PWM_CHANNEL_COUNT] \
PWM_MEMORY_SECTION(inst); \
PINCTRL_DT_INST_DEFINE(inst); \
static const struct pwm_nrfx_config pwm_nrfx_##inst##_config = { \
.initial_config = { \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.base_clock = NRF_PWM_CLK_1MHz, \
.count_mode = (DT_INST_PROP(inst, center_aligned) \
? NRF_PWM_MODE_UP_AND_DOWN \
: NRF_PWM_MODE_UP), \
.top_value = 1000, \
.load_mode = NRF_PWM_LOAD_INDIVIDUAL, \
.step_mode = NRF_PWM_STEP_TRIGGERED, \
}, \
.seq.values.p_raw = pwm_##inst##_seq_values, \
.seq.length = NRF_PWM_CHANNEL_COUNT, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.clock_freq = COND_CODE_1(DT_INST_CLOCKS_HAS_IDX(inst, 0), \
(DT_PROP(DT_INST_CLOCKS_CTLR(inst), clock_frequency)), \
(16ul * 1000ul * 1000ul)), \
IF_ENABLED(CONFIG_DCACHE, \
(.mem_attr = PWM_GET_MEM_ATTR(inst),)) \
}; \
static int pwm_nrfx_init##inst(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), \
nrfx_pwm_irq_handler, &pwm_nrfx_##inst##_data.pwm, 0); \
return pwm_nrfx_init(dev); \
}; \
PM_DEVICE_DT_INST_DEFINE(inst, pwm_nrfx_pm_action); \
DEVICE_DT_INST_DEINIT_DEFINE(inst, \
pwm_nrfx_init##inst, NULL, \
PM_DEVICE_DT_INST_GET(inst), \
&pwm_nrfx_##inst##_data, \
&pwm_nrfx_##inst##_config, \
POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
&pwm_nrfx_drv_api_funcs)
#define COND_PWM_NRFX_DEVICE(unused, prefix, i, _) \
IF_ENABLED(CONFIG_HAS_HW_NRF_PWM##prefix##i, (PWM_NRFX_DEVICE(prefix##i);))
NRFX_FOREACH_PRESENT(PWM, COND_PWM_NRFX_DEVICE, (), (), _)
DT_INST_FOREACH_STATUS_OKAY(PWM_NRFX_DEFINE)

7
drivers/sensor/nordic/qdec_nrfx/Kconfig
View File

@@ -5,12 +5,7 @@ config QDEC_NRFX
bool "Nordic QDEC nrfx driver"
default y
depends on DT_HAS_NORDIC_NRF_QDEC_ENABLED
select NRFX_QDEC0 if HAS_HW_NRF_QDEC0
select NRFX_QDEC1 if HAS_HW_NRF_QDEC1
select NRFX_QDEC20 if HAS_HW_NRF_QDEC20
select NRFX_QDEC21 if HAS_HW_NRF_QDEC21
select NRFX_QDEC130 if HAS_HW_NRF_QDEC130
select NRFX_QDEC131 if HAS_HW_NRF_QDEC131
select NRFX_QDEC
select PINCTRL
help
Enable support for nrfx QDEC driver for nRF MCU series.

144
drivers/sensor/nordic/qdec_nrfx/qdec_nrfx.c
View File

@@ -43,6 +43,7 @@ BUILD_ASSERT(NRF_QDEC_SAMPLEPER_16384US == SAMPLEPER_16384US,
"Different SAMPLEPER register values in devicetree binding and nRF HAL");
struct qdec_nrfx_data {
nrfx_qdec_t qdec;
int32_t fetched_acc;
int32_t acc;
bool overflow;
@@ -51,7 +52,6 @@ struct qdec_nrfx_data {
};
struct qdec_nrfx_config {
nrfx_qdec_t qdec;
nrfx_qdec_config_t config;
void (*irq_connect)(void);
const struct pinctrl_dev_config *pcfg;
@@ -78,7 +78,6 @@ static void accumulate(struct qdec_nrfx_data *data, int32_t acc)
static int qdec_nrfx_sample_fetch(const struct device *dev,
enum sensor_channel chan)
{
const struct qdec_nrfx_config *config = dev->config;
struct qdec_nrfx_data *data = dev->data;
int32_t acc;
uint32_t accdbl;
@@ -87,7 +86,7 @@ static int qdec_nrfx_sample_fetch(const struct device *dev,
return -ENOTSUP;
}
nrfx_qdec_accumulators_read(&config->qdec, &acc, &accdbl);
nrfx_qdec_accumulators_read(&data->qdec, &acc, &accdbl);
accumulate(data, acc);
@@ -212,8 +211,9 @@ static DEVICE_API(sensor, qdec_nrfx_driver_api) = {
static void qdec_pm_suspend(const struct device *dev)
{
const struct qdec_nrfx_config *config = dev->config;
struct qdec_nrfx_data *dev_data = dev->data;
nrfx_qdec_disable(&config->qdec);
nrfx_qdec_disable(&dev_data->qdec);
qdec_nrfx_gpio_ctrl(dev, false);
(void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
@@ -222,10 +222,11 @@ static void qdec_pm_suspend(const struct device *dev)
static void qdec_pm_resume(const struct device *dev)
{
const struct qdec_nrfx_config *config = dev->config;
struct qdec_nrfx_data *dev_data = dev->data;
(void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
qdec_nrfx_gpio_ctrl(dev, true);
nrfx_qdec_enable(&config->qdec);
nrfx_qdec_enable(&dev_data->qdec);
}
static int qdec_nrfx_pm_action(const struct device *dev, enum pm_device_action action)
@@ -251,13 +252,15 @@ static int qdec_nrfx_pm_action(const struct device *dev, enum pm_device_action a
static int qdec_nrfx_init(const struct device *dev)
{
const struct qdec_nrfx_config *config = dev->config;
nrfx_err_t nerr;
struct qdec_nrfx_data *dev_data = dev->data;
int nerr;
config->irq_connect();
nerr = nrfx_qdec_init(&config->qdec, &config->config, qdec_nrfx_event_handler, (void *)dev);
if (nerr != NRFX_SUCCESS) {
return (nerr == NRFX_ERROR_INVALID_STATE) ? -EBUSY : -EFAULT;
nerr = nrfx_qdec_init(&dev_data->qdec, &config->config, qdec_nrfx_event_handler,
(void *)dev);
if (nerr != 0) {
return -EALREADY;
}
/* End up in suspend state. */
@@ -269,9 +272,6 @@ static int qdec_nrfx_init(const struct device *dev)
return pm_device_driver_init(dev, qdec_nrfx_pm_action);
}
#define QDEC(idx) DT_NODELABEL(qdec##idx)
#define QDEC_PROP(idx, prop) DT_PROP(QDEC(idx), prop)
/* Macro determines PM actions interrupt safety level.
*
* Requesting/releasing QDEC device may be ISR safe, but it cannot be reliably known whether
@@ -279,78 +279,56 @@ static int qdec_nrfx_init(const struct device *dev)
* no longer ISR safe. This macro let's us check if we will be requesting/releasing
* power domains and determines PM device ISR safety value.
*/
#define QDEC_PM_ISR_SAFE(idx) \
COND_CODE_1( \
UTIL_AND( \
IS_ENABLED(CONFIG_PM_DEVICE_POWER_DOMAIN), \
UTIL_AND( \
DT_NODE_HAS_PROP(QDEC(idx), power_domains), \
DT_NODE_HAS_STATUS_OKAY(DT_PHANDLE(QDEC(idx), power_domains)) \
) \
), \
(0), \
(PM_DEVICE_ISR_SAFE) \
#define QDEC_PM_ISR_SAFE(inst) \
COND_CODE_1( \
UTIL_AND( \
IS_ENABLED(CONFIG_PM_DEVICE_POWER_DOMAIN), \
UTIL_AND(DT_INST_NODE_HAS_PROP(inst, power_domains), \
DT_NODE_HAS_STATUS_OKAY(DT_INST_PHANDLE(inst, power_domains))) \
), \
(0), \
(PM_DEVICE_ISR_SAFE) \
)
#define SENSOR_NRFX_QDEC_DEVICE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(QDEC(idx)); \
BUILD_ASSERT(QDEC_PROP(idx, steps) > 0, \
"Wrong QDEC"#idx" steps setting in dts. Only positive number valid"); \
BUILD_ASSERT(QDEC_PROP(idx, steps) <= 2048, \
"Wrong QDEC"#idx" steps setting in dts. Overflow possible"); \
static void irq_connect##idx(void) \
{ \
IRQ_CONNECT(DT_IRQN(QDEC(idx)), DT_IRQ(QDEC(idx), priority), \
nrfx_isr, nrfx_qdec_##idx##_irq_handler, 0); \
} \
static struct qdec_nrfx_data qdec_##idx##_data; \
PINCTRL_DT_DEFINE(QDEC(idx)); \
static struct qdec_nrfx_config qdec_##idx##_config = { \
.qdec = NRFX_QDEC_INSTANCE(idx), \
.config = { \
.reportper = NRF_QDEC_REPORTPER_40, \
.sampleper = DT_STRING_TOKEN(QDEC(idx), nordic_period), \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.ledpre = QDEC_PROP(idx, led_pre), \
.ledpol = NRF_QDEC_LEPOL_ACTIVE_HIGH, \
.reportper_inten = true, \
}, \
.irq_connect = irq_connect##idx, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(QDEC(idx)), \
.enable_pin = DT_PROP_OR(QDEC(idx), enable_pin, NRF_QDEC_PIN_NOT_CONNECTED), \
.steps = QDEC_PROP(idx, steps), \
}; \
PM_DEVICE_DT_DEFINE(QDEC(idx), qdec_nrfx_pm_action, QDEC_PM_ISR_SAFE(idx)); \
SENSOR_DEVICE_DT_DEFINE(QDEC(idx), \
qdec_nrfx_init, \
PM_DEVICE_DT_GET(QDEC(idx)), \
&qdec_##idx##_data, \
&qdec_##idx##_config, \
POST_KERNEL, \
CONFIG_SENSOR_INIT_PRIORITY, \
#define SENSOR_NRFX_QDEC_DEVICE(inst) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(DT_DRV_INST(inst)); \
BUILD_ASSERT(DT_INST_PROP(inst, steps) > 0, \
"Wrong QDEC"#inst" steps setting in dts. Only positive number valid"); \
BUILD_ASSERT(DT_INST_PROP(inst, steps) <= 2048, \
"Wrong QDEC"#inst" steps setting in dts. Overflow possible"); \
static struct qdec_nrfx_data qdec_##inst##_data = { \
.qdec = NRFX_QDEC_INSTANCE(DT_INST_REG_ADDR(inst)), \
}; \
static void irq_connect##inst(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), \
nrfx_qdec_irq_handler, &qdec_##inst##_data.qdec, 0); \
} \
PINCTRL_DT_DEFINE(DT_DRV_INST(inst)); \
static struct qdec_nrfx_config qdec_##inst##_config = { \
.config = { \
.reportper = NRF_QDEC_REPORTPER_40, \
.sampleper = DT_STRING_TOKEN(DT_DRV_INST(inst), nordic_period), \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.ledpre = DT_INST_PROP(inst, led_pre), \
.ledpol = NRF_QDEC_LEPOL_ACTIVE_HIGH, \
.reportper_inten = true, \
}, \
.irq_connect = irq_connect##inst, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_DRV_INST(inst)), \
.enable_pin = DT_PROP_OR( \
DT_DRV_INST(inst), enable_pin, NRF_QDEC_PIN_NOT_CONNECTED), \
.steps = DT_INST_PROP(inst, steps), \
}; \
PM_DEVICE_DT_INST_DEFINE(inst, qdec_nrfx_pm_action, QDEC_PM_ISR_SAFE(inst)); \
SENSOR_DEVICE_DT_DEFINE(DT_DRV_INST(inst), \
qdec_nrfx_init, \
PM_DEVICE_DT_INST_GET(inst), \
&qdec_##inst##_data, \
&qdec_##inst##_config, \
POST_KERNEL, \
CONFIG_SENSOR_INIT_PRIORITY, \
&qdec_nrfx_driver_api)
#ifdef CONFIG_HAS_HW_NRF_QDEC0
SENSOR_NRFX_QDEC_DEVICE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_QDEC1
SENSOR_NRFX_QDEC_DEVICE(1);
#endif
#ifdef CONFIG_HAS_HW_NRF_QDEC20
SENSOR_NRFX_QDEC_DEVICE(20);
#endif
#ifdef CONFIG_HAS_HW_NRF_QDEC21
SENSOR_NRFX_QDEC_DEVICE(21);
#endif
#ifdef CONFIG_HAS_HW_NRF_QDEC130
SENSOR_NRFX_QDEC_DEVICE(130);
#endif
#ifdef CONFIG_HAS_HW_NRF_QDEC131
SENSOR_NRFX_QDEC_DEVICE(131);
#endif
DT_INST_FOREACH_STATUS_OKAY(SENSOR_NRFX_QDEC_DEVICE)

30
drivers/serial/Kconfig.nrfx
View File

@@ -189,37 +189,25 @@ nrfx_uart_num = 137
rsource "Kconfig.nrfx_uart_instance"
endif
config NRFX_TIMER0
config NRFX_TIMER
default y
depends on UART_0_NRF_HW_ASYNC_TIMER = 0 \
|| UART_1_NRF_HW_ASYNC_TIMER = 0 \
|| UART_2_NRF_HW_ASYNC_TIMER = 0 \
|| UART_3_NRF_HW_ASYNC_TIMER = 0
config NRFX_TIMER1
default y
depends on UART_0_NRF_HW_ASYNC_TIMER = 1 \
|| UART_3_NRF_HW_ASYNC_TIMER = 0 \
|| UART_0_NRF_HW_ASYNC_TIMER = 1 \
|| UART_1_NRF_HW_ASYNC_TIMER = 1 \
|| UART_2_NRF_HW_ASYNC_TIMER = 1 \
|| UART_3_NRF_HW_ASYNC_TIMER = 1
config NRFX_TIMER2
default y
depends on UART_0_NRF_HW_ASYNC_TIMER = 2 \
|| UART_3_NRF_HW_ASYNC_TIMER = 1 \
|| UART_0_NRF_HW_ASYNC_TIMER = 2 \
|| UART_1_NRF_HW_ASYNC_TIMER = 2 \
|| UART_2_NRF_HW_ASYNC_TIMER = 2 \
|| UART_3_NRF_HW_ASYNC_TIMER = 2
config NRFX_TIMER3
default y
depends on UART_0_NRF_HW_ASYNC_TIMER = 3 \
|| UART_3_NRF_HW_ASYNC_TIMER = 2 \
|| UART_0_NRF_HW_ASYNC_TIMER = 3 \
|| UART_1_NRF_HW_ASYNC_TIMER = 3 \
|| UART_2_NRF_HW_ASYNC_TIMER = 3 \
|| UART_3_NRF_HW_ASYNC_TIMER = 3
config NRFX_TIMER4
default y
depends on UART_0_NRF_HW_ASYNC_TIMER = 4 \
|| UART_3_NRF_HW_ASYNC_TIMER = 3 \
|| UART_0_NRF_HW_ASYNC_TIMER = 4 \
|| UART_1_NRF_HW_ASYNC_TIMER = 4 \
|| UART_2_NRF_HW_ASYNC_TIMER = 4 \
|| UART_3_NRF_HW_ASYNC_TIMER = 4

75
drivers/serial/uart_nrfx_uarte.c
View File

@@ -187,8 +187,8 @@ struct uarte_async_rx_cbwt {
uint8_t *anomaly_byte_dst;
uint8_t anomaly_byte;
#endif
nrfx_gppi_handle_t ppi_h;
uint8_t bounce_idx;
uint8_t ppi_ch;
bool in_irq;
bool discard_fifo;
};
@@ -217,7 +217,7 @@ struct uarte_async_rx {
int32_t timeout_slab; /* rx_timeout divided by RX_TIMEOUT_DIV */
int32_t timeout_left; /* Current time left until user callback */
union {
uint8_t ppi;
nrfx_gppi_handle_t ppi;
uint32_t cnt;
} cnt;
/* Flag to ensure that RX timeout won't be executed during ENDRX ISR */
@@ -264,11 +264,12 @@ struct uarte_nrfx_data {
#endif
#ifdef UARTE_ANY_ASYNC
struct uarte_async_cb *async;
nrfx_timer_t timer;
#endif
atomic_val_t poll_out_lock;
atomic_t flags;
#ifdef UARTE_ENHANCED_POLL_OUT
uint8_t ppi_ch_endtx;
nrfx_gppi_handle_t ppi_h_endtx;
#endif
};
@@ -388,7 +389,6 @@ struct uarte_nrfx_config {
size_t bounce_buf_swap_len;
struct uarte_async_rx_cbwt *cbwt_data;
#endif
nrfx_timer_t timer;
uint8_t *tx_cache;
uint8_t *rx_flush_buf;
#endif
@@ -457,7 +457,7 @@ static void uarte_disable_locked(const struct device *dev, uint32_t dis_mask)
#if defined(UARTE_ANY_ASYNC) && !defined(CONFIG_UART_NRFX_UARTE_ENHANCED_RX)
if (data->async && HW_RX_COUNTING_ENABLED(config)) {
nrfx_timer_disable(&config->timer);
nrfx_timer_disable(&data->timer);
/* Timer/counter value is reset when disabled. */
data->async->rx.total_byte_cnt = 0;
data->async->rx.total_user_byte_cnt = 0;
@@ -604,7 +604,7 @@ static int uarte_nrfx_configure(const struct device *dev,
struct uarte_nrfx_data *data = dev->data;
nrf_uarte_config_t uarte_cfg;
#if defined(UARTE_CONFIG_STOP_Msk)
#if NRF_UARTE_HAS_STOP_MODES
switch (cfg->stop_bits) {
case UART_CFG_STOP_BITS_1:
uarte_cfg.stop = NRF_UARTE_STOP_ONE;
@@ -636,7 +636,7 @@ static int uarte_nrfx_configure(const struct device *dev,
return -ENOTSUP;
}
#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
#if NRF_UARTE_HAS_PARITY_TYPES
uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
switch (cfg->parity) {
@@ -646,7 +646,7 @@ static int uarte_nrfx_configure(const struct device *dev,
case UART_CFG_PARITY_EVEN:
uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
break;
#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
#if NRF_UARTE_HAS_PARITY_TYPES
case UART_CFG_PARITY_ODD:
uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_ODD;
@@ -765,7 +765,7 @@ static void uarte_periph_enable(const struct device *dev)
#ifdef UARTE_ANY_ASYNC
if (data->async) {
if (HW_RX_COUNTING_ENABLED(config)) {
const nrfx_timer_t *timer = &config->timer;
nrfx_timer_t *timer = &data->timer;
nrfx_timer_enable(timer);
@@ -954,31 +954,30 @@ static int uarte_nrfx_rx_counting_init(const struct device *dev)
if (HW_RX_COUNTING_ENABLED(cfg)) {
nrfx_timer_config_t tmr_config = NRFX_TIMER_DEFAULT_CONFIG(
NRF_TIMER_BASE_FREQUENCY_GET(cfg->timer.p_reg));
NRF_TIMER_BASE_FREQUENCY_GET(data->timer.p_reg));
uint32_t evt_addr = nrf_uarte_event_address_get(uarte, NRF_UARTE_EVENT_RXDRDY);
uint32_t tsk_addr = nrfx_timer_task_address_get(&cfg->timer, NRF_TIMER_TASK_COUNT);
uint32_t tsk_addr = nrfx_timer_task_address_get(&data->timer, NRF_TIMER_TASK_COUNT);
tmr_config.mode = NRF_TIMER_MODE_COUNTER;
tmr_config.bit_width = NRF_TIMER_BIT_WIDTH_32;
ret = nrfx_timer_init(&cfg->timer,
ret = nrfx_timer_init(&data->timer,
&tmr_config,
timer_handler);
if (ret != NRFX_SUCCESS) {
if (ret != 0) {
LOG_ERR("Timer already initialized");
return -EINVAL;
}
nrfx_timer_clear(&cfg->timer);
nrfx_timer_clear(&data->timer);
ret = nrfx_gppi_channel_alloc(&data->async->rx.cnt.ppi);
if (ret != NRFX_SUCCESS) {
ret = nrfx_gppi_conn_alloc(evt_addr, tsk_addr, &data->async->rx.cnt.ppi);
if (ret < 0) {
LOG_ERR("Failed to allocate PPI Channel");
nrfx_timer_uninit(&cfg->timer);
return -EINVAL;
nrfx_timer_uninit(&data->timer);
return ret;
}
nrfx_gppi_channel_endpoints_setup(data->async->rx.cnt.ppi, evt_addr, tsk_addr);
nrfx_gppi_channels_enable(BIT(data->async->rx.cnt.ppi));
nrfx_gppi_conn_enable(data->async->rx.cnt.ppi);
} else {
nrf_uarte_int_enable(uarte, NRF_UARTE_INT_RXDRDY_MASK);
}
@@ -1609,18 +1608,17 @@ static int cbwt_uarte_async_init(const struct device *dev)
NRF_UARTE_INT_RXTO_MASK;
uint32_t evt = nrf_uarte_event_address_get(cfg->uarte_regs, NRF_UARTE_EVENT_RXDRDY);
uint32_t tsk = nrf_timer_task_address_get(cfg->timer_regs, NRF_TIMER_TASK_COUNT);
nrfx_err_t ret;
int ret;
nrf_timer_mode_set(cfg->timer_regs, NRF_TIMER_MODE_COUNTER);
nrf_timer_bit_width_set(cfg->timer_regs, NRF_TIMER_BIT_WIDTH_32);
ret = nrfx_gppi_channel_alloc(&cbwt_data->ppi_ch);
if (ret != NRFX_SUCCESS) {
return -ENOMEM;
ret = nrfx_gppi_conn_alloc(evt, tsk, &cbwt_data->ppi_h);
if (ret < 0) {
return ret;
}
nrfx_gppi_channel_endpoints_setup(cbwt_data->ppi_ch, evt, tsk);
nrfx_gppi_channels_enable(BIT(cbwt_data->ppi_ch));
nrfx_gppi_conn_enable(cbwt_data->ppi_h);
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
cbwt_data->bounce_buf_swap_len = cfg->bounce_buf_swap_len;
@@ -2117,7 +2115,7 @@ static void rx_timeout(struct k_timer *timer)
NRF_UARTE_INT_ENDRX_MASK);
if (HW_RX_COUNTING_ENABLED(cfg)) {
read = nrfx_timer_capture(&cfg->timer, 0);
read = nrfx_timer_capture(&data->timer, 0);
} else {
read = async_rx->cnt.cnt;
}
@@ -3001,18 +2999,17 @@ static DEVICE_API(uart, uart_nrfx_uarte_driver_api) = {
static int endtx_stoptx_ppi_init(NRF_UARTE_Type *uarte,
struct uarte_nrfx_data *data)
{
nrfx_err_t ret;
int ret;
ret = nrfx_gppi_channel_alloc(&data->ppi_ch_endtx);
if (ret != NRFX_SUCCESS) {
ret = nrfx_gppi_conn_alloc(
nrf_uarte_event_address_get(uarte, NRF_UARTE_EVENT_ENDTX),
nrf_uarte_task_address_get(uarte, NRF_UARTE_TASK_STOPTX), &data->ppi_h_endtx);
if (ret < 0) {
LOG_ERR("Failed to allocate PPI Channel");
return -EIO;
return ret;
}
nrfx_gppi_channel_endpoints_setup(data->ppi_ch_endtx,
nrf_uarte_event_address_get(uarte, NRF_UARTE_EVENT_ENDTX),
nrf_uarte_task_address_get(uarte, NRF_UARTE_TASK_STOPTX));
nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
nrfx_gppi_conn_enable(data->ppi_h_endtx);
return 0;
}
@@ -3091,7 +3088,7 @@ static void uarte_pm_suspend(const struct device *dev)
#if !defined(CONFIG_UART_NRFX_UARTE_ENHANCED_RX)
if (data->async && HW_RX_COUNTING_ENABLED(cfg)) {
nrfx_timer_disable(&cfg->timer);
nrfx_timer_disable(&data->timer);
/* Timer/counter value is reset when disabled. */
data->async->rx.total_byte_cnt = 0;
data->async->rx.total_user_byte_cnt = 0;
@@ -3413,6 +3410,9 @@ static int uarte_instance_deinit(const struct device *dev)
(.uart_config = UARTE_CONFIG(idx),)) \
IF_ENABLED(CONFIG_UART_##idx##_ASYNC, \
(.async = &uarte##idx##_async,)) \
IF_ENABLED(CONFIG_UART_##idx##_NRF_HW_ASYNC, \
(.timer = NRFX_TIMER_INSTANCE(NRF_TIMER_INST_GET( \
CONFIG_UART_##idx##_NRF_HW_ASYNC_TIMER)),)) \
IF_ENABLED(CONFIG_UART_##idx##_INTERRUPT_DRIVEN, \
(.int_driven = &uarte##idx##_int_driven,)) \
}; \
@@ -3454,9 +3454,6 @@ static int uarte_instance_deinit(const struct device *dev)
.rx_flush_buf = uarte##idx##_flush_buf,)) \
IF_ENABLED(CONFIG_UARTE_NRFX_UARTE_COUNT_BYTES_WITH_TIMER, \
(UARTE_COUNT_BYTES_WITH_TIMER_CONFIG(idx))) \
IF_ENABLED(CONFIG_UART_##idx##_NRF_HW_ASYNC, \
(.timer = NRFX_TIMER_INSTANCE( \
CONFIG_UART_##idx##_NRF_HW_ASYNC_TIMER),)) \
}; \
UARTE_DIRECT_ISR_DECLARE(idx) \
static int uarte_##idx##_init(const struct device *dev) \

64
drivers/spi/Kconfig.nrfx
View File

@@ -22,73 +22,13 @@ config SPI_NRFX_SPI
config SPI_NRFX_SPIM
def_bool y
depends on DT_HAS_NORDIC_NRF_SPIM_ENABLED
select NRFX_SPIM0 if HAS_HW_NRF_SPIM0
select NRFX_SPIM1 if HAS_HW_NRF_SPIM1
select NRFX_SPIM2 if HAS_HW_NRF_SPIM2
select NRFX_SPIM3 if HAS_HW_NRF_SPIM3
select NRFX_SPIM4 if HAS_HW_NRF_SPIM4
select NRFX_SPIM00 if HAS_HW_NRF_SPIM00
select NRFX_SPIM01 if HAS_HW_NRF_SPIM01
select NRFX_SPIM20 if HAS_HW_NRF_SPIM20
select NRFX_SPIM21 if HAS_HW_NRF_SPIM21
select NRFX_SPIM22 if HAS_HW_NRF_SPIM22
select NRFX_SPIM23 if HAS_HW_NRF_SPIM23
select NRFX_SPIM24 if HAS_HW_NRF_SPIM24
select NRFX_SPIM30 if HAS_HW_NRF_SPIM30
select NRFX_SPIM120 if HAS_HW_NRF_SPIM120
select NRFX_SPIM121 if HAS_HW_NRF_SPIM121
select NRFX_SPIM130 if HAS_HW_NRF_SPIM130
select NRFX_SPIM131 if HAS_HW_NRF_SPIM131
select NRFX_SPIM132 if HAS_HW_NRF_SPIM132
select NRFX_SPIM133 if HAS_HW_NRF_SPIM133
select NRFX_SPIM134 if HAS_HW_NRF_SPIM134
select NRFX_SPIM135 if HAS_HW_NRF_SPIM135
select NRFX_SPIM136 if HAS_HW_NRF_SPIM136
select NRFX_SPIM137 if HAS_HW_NRF_SPIM137
select NRFX_SPIM
config SPI_NRFX_SPIS
def_bool y
depends on DT_HAS_NORDIC_NRF_SPIS_ENABLED
select SPI_SLAVE
select NRFX_SPIS0 if HAS_HW_NRF_SPIS0
select NRFX_SPIS1 if HAS_HW_NRF_SPIS1
select NRFX_SPIS2 if HAS_HW_NRF_SPIS2
select NRFX_SPIS3 if HAS_HW_NRF_SPIS3
select NRFX_SPIS00 if HAS_HW_NRF_SPIS00
select NRFX_SPIS01 if HAS_HW_NRF_SPIS01
select NRFX_SPIS20 if HAS_HW_NRF_SPIS20
select NRFX_SPIS21 if HAS_HW_NRF_SPIS21
select NRFX_SPIS22 if HAS_HW_NRF_SPIS22
select NRFX_SPIS23 if HAS_HW_NRF_SPIS23
select NRFX_SPIS24 if HAS_HW_NRF_SPIS24
select NRFX_SPIS30 if HAS_HW_NRF_SPIS30
select NRFX_SPIS120 if HAS_HW_NRF_SPIS120
select NRFX_SPIS130 if HAS_HW_NRF_SPIS130
select NRFX_SPIS131 if HAS_HW_NRF_SPIS131
select NRFX_SPIS132 if HAS_HW_NRF_SPIS132
select NRFX_SPIS133 if HAS_HW_NRF_SPIS133
select NRFX_SPIS134 if HAS_HW_NRF_SPIS134
select NRFX_SPIS135 if HAS_HW_NRF_SPIS135
select NRFX_SPIS136 if HAS_HW_NRF_SPIS136
select NRFX_SPIS137 if HAS_HW_NRF_SPIS137
config SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
depends on SOC_NRF52832
select NRFX_PPI
bool "Allow enabling the SPIM driver despite PAN 58"
help
Allow enabling the nRF SPI Master with EasyDMA, despite
Product Anomaly Notice 58 (SPIM: An additional byte is
clocked out when RXD.MAXCNT == 1 and TXD.MAXCNT <= 1).
Without this override, the SPI Master is only available
without EasyDMA. Note that the 'SPIM' and 'SPIS' drivers
use EasyDMA, while the 'SPI' driver does not.
When used in conjunction with nRF SPIM Devicetree property
'anomaly-58-workaround' a workaround can be enabled per SPIM
instance. If you are certain that transactions with
RXD.MAXCNT == 1 and TXD.MAXCNT <= 1 will NOT be executed
then nRF52832 PPI and GPIOTE resources can be saved by not
enabling 'anomaly-58-workaround' via the Devicetree.
select NRFX_SPIS
config SPI_NRFX_RAM_BUFFER_SIZE
int "Size of RAM buffers for SPIM peripherals"

14
drivers/spi/spi_nrfx_common.c
View File

@@ -7,7 +7,7 @@
#include "spi_nrfx_common.h"
#include <zephyr/kernel.h>
int spi_nrfx_wake_init(const nrfx_gpiote_t *gpiote, uint32_t wake_pin)
int spi_nrfx_wake_init(nrfx_gpiote_t *gpiote, uint32_t wake_pin)
{
nrf_gpio_pin_pull_t pull_config = NRF_GPIO_PIN_PULLDOWN;
uint8_t ch;
@@ -20,23 +20,23 @@ int spi_nrfx_wake_init(const nrfx_gpiote_t *gpiote, uint32_t wake_pin)
.p_trigger_config = &trigger_config,
.p_handler_config = NULL,
};
nrfx_err_t res;
int res;
res = nrfx_gpiote_channel_alloc(gpiote, &ch);
if (res != NRFX_SUCCESS) {
return -ENODEV;
if (res < 0) {
return res;
}
res = nrfx_gpiote_input_configure(gpiote, wake_pin, &input_config);
if (res != NRFX_SUCCESS) {
if (res < 0) {
nrfx_gpiote_channel_free(gpiote, ch);
return -EIO;
return res;
}
return 0;
}
int spi_nrfx_wake_request(const nrfx_gpiote_t *gpiote, uint32_t wake_pin)
int spi_nrfx_wake_request(nrfx_gpiote_t *gpiote, uint32_t wake_pin)
{
nrf_gpiote_event_t trigger_event = nrfx_gpiote_in_event_get(gpiote, wake_pin);
uint32_t start_cycles;

16
drivers/spi/spi_nrfx_common.h
View File

@@ -9,16 +9,18 @@
#include <stdint.h>
#include <nrfx_gpiote.h>
#include <gpiote_nrfx.h>
#include <zephyr/drivers/gpio/gpio_nrf.h>
#define WAKE_PIN_NOT_USED UINT32_MAX
#define WAKE_GPIOTE_INSTANCE(node_id) \
COND_CODE_1(DT_NODE_HAS_PROP(node_id, wake_gpios), \
(NRFX_GPIOTE_INSTANCE( \
NRF_DT_GPIOTE_INST(node_id, wake_gpios))), \
({0}))
#define WAKE_GPIOTE_NODE(node_id) \
COND_CODE_1(DT_NODE_HAS_PROP(node_id, wake_gpios), \
(&GPIOTE_NRFX_INST_BY_NODE(DT_PHANDLE(DT_PHANDLE(node_id, wake_gpios), \
gpiote_instance))), \
(NULL))
int spi_nrfx_wake_init(const nrfx_gpiote_t *gpiote, uint32_t wake_pin);
int spi_nrfx_wake_request(const nrfx_gpiote_t *gpiote, uint32_t wake_pin);
int spi_nrfx_wake_init(nrfx_gpiote_t *gpiote, uint32_t wake_pin);
int spi_nrfx_wake_request(nrfx_gpiote_t *gpiote, uint32_t wake_pin);
#endif /* ZEPHYR_DRIVERS_SPI_NRFX_COMMON_H_ */

19
drivers/spi/spi_nrfx_spi.c
View File

@@ -31,8 +31,8 @@ struct spi_nrfx_config {
nrfx_spi_config_t def_config;
void (*irq_connect)(void);
const struct pinctrl_dev_config *pcfg;
nrfx_gpiote_t *wake_gpiote;
uint32_t wake_pin;
nrfx_gpiote_t wake_gpiote;
};
static void event_handler(const nrfx_spi_evt_t *p_event, void *p_context);
@@ -91,7 +91,7 @@ static int configure(const struct device *dev,
const struct spi_nrfx_config *dev_config = dev->config;
struct spi_context *ctx = &dev_data->ctx;
nrfx_spi_config_t config;
nrfx_err_t result;
int result;
uint32_t sck_pin;
if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) {
@@ -149,8 +149,8 @@ static int configure(const struct device *dev,
result = nrfx_spi_init(&dev_config->spi, &config,
event_handler, dev_data);
if (result != NRFX_SUCCESS) {
LOG_ERR("Failed to initialize nrfx driver: %08x", result);
if (result != 0) {
LOG_ERR("Failed to initialize nrfx driver: %d", result);
return -EIO;
}
@@ -183,7 +183,6 @@ static void transfer_next_chunk(const struct device *dev)
if (chunk_len > 0) {
nrfx_spi_xfer_desc_t xfer;
nrfx_err_t result;
dev_data->chunk_len = chunk_len;
@@ -191,8 +190,8 @@ static void transfer_next_chunk(const struct device *dev)
xfer.tx_length = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
xfer.p_rx_buffer = ctx->rx_buf;
xfer.rx_length = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
result = nrfx_spi_xfer(&dev_config->spi, &xfer, 0);
if (result == NRFX_SUCCESS) {
error = nrfx_spi_xfer(&dev_config->spi, &xfer, 0);
if (error == 0) {
return;
}
@@ -241,7 +240,7 @@ static int transceive(const struct device *dev,
dev_data->busy = true;
if (dev_config->wake_pin != WAKE_PIN_NOT_USED) {
error = spi_nrfx_wake_request(&dev_config->wake_gpiote,
error = spi_nrfx_wake_request(dev_config->wake_gpiote,
dev_config->wake_pin);
if (error == -ETIMEDOUT) {
LOG_WRN("Waiting for WAKE acknowledgment timed out");
@@ -395,7 +394,7 @@ static int spi_nrfx_init(const struct device *dev)
}
if (dev_config->wake_pin != WAKE_PIN_NOT_USED) {
err = spi_nrfx_wake_init(&dev_config->wake_gpiote, dev_config->wake_pin);
err = spi_nrfx_wake_init(dev_config->wake_gpiote, dev_config->wake_pin);
if (err == -ENODEV) {
LOG_ERR("Failed to allocate GPIOTE channel for WAKE");
return err;
@@ -458,9 +457,9 @@ static int spi_nrfx_init(const struct device *dev)
}, \
.irq_connect = irq_connect##idx, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(SPI(idx)), \
.wake_gpiote = WAKE_GPIOTE_NODE(SPI(idx)), \
.wake_pin = NRF_DT_GPIOS_TO_PSEL_OR(SPI(idx), wake_gpios, \
WAKE_PIN_NOT_USED), \
.wake_gpiote = WAKE_GPIOTE_INSTANCE(SPI(idx)), \
}; \
BUILD_ASSERT(!DT_NODE_HAS_PROP(SPI(idx), wake_gpios) || \
!(DT_GPIO_FLAGS(SPI(idx), wake_gpios) & GPIO_ACTIVE_LOW), \

292
drivers/spi/spi_nrfx_spim.c
View File

@@ -4,6 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_spim
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/spi/rtio.h>
#include <zephyr/cache.h>
@@ -13,9 +15,6 @@
#include <zephyr/mem_mgmt/mem_attr.h>
#include <soc.h>
#include <dmm.h>
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
#include <nrfx_ppi.h>
#endif
#ifdef CONFIG_SOC_NRF5340_CPUAPP
#include <hal/nrf_clock.h>
#endif
@@ -30,31 +29,12 @@ LOG_MODULE_REGISTER(spi_nrfx_spim, CONFIG_SPI_LOG_LEVEL);
#include "spi_context.h"
#include "spi_nrfx_common.h"
#if defined(CONFIG_SOC_NRF52832) && !defined(CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58)
#error This driver is not available by default for nRF52832 because of Product Anomaly 58 \
(SPIM: An additional byte is clocked out when RXD.MAXCNT == 1 and TXD.MAXCNT <= 1). \
Use CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58=y to override this limitation.
#endif
#if (CONFIG_SPI_NRFX_RAM_BUFFER_SIZE > 0)
#define SPI_BUFFER_IN_RAM 1
#endif
/*
* We use NODELABEL here because the nrfx API requires us to call
* functions which are named according to SoC peripheral instance
* being operated on. Since DT_INST() makes no guarantees about that,
* it won't work.
*/
#define SPIM(idx) DT_NODELABEL(spi##idx)
#define SPIM_PROP(idx, prop) DT_PROP(SPIM(idx), prop)
#define SPIM_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(SPIM(idx), prop)
/* Execute macro f(x) for all instances. */
#define SPIM_FOR_EACH_INSTANCE(f, sep, off_code, ...) \
NRFX_FOREACH_PRESENT(SPIM, f, sep, off_code, __VA_ARGS__)
struct spi_nrfx_data {
nrfx_spim_t spim;
struct spi_context ctx;
const struct device *dev;
size_t chunk_len;
@@ -64,35 +44,25 @@ struct spi_nrfx_data {
uint8_t *tx_buffer;
uint8_t *rx_buffer;
#endif
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
bool anomaly_58_workaround_active;
uint8_t ppi_ch;
uint8_t gpiote_ch;
#endif
};
struct spi_nrfx_config {
nrfx_spim_t spim;
uint32_t max_freq;
nrfx_spim_config_t def_config;
void (*irq_connect)(void);
uint16_t max_chunk_len;
const struct pinctrl_dev_config *pcfg;
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
bool anomaly_58_workaround;
#endif
nrfx_gpiote_t *wake_gpiote;
uint32_t wake_pin;
nrfx_gpiote_t wake_gpiote;
void *mem_reg;
};
static void event_handler(const nrfx_spim_evt_t *p_event, void *p_context);
static void event_handler(const nrfx_spim_event_t *p_event, void *p_context);
static inline void finalize_spi_transaction(const struct device *dev, bool deactivate_cs)
{
struct spi_nrfx_data *dev_data = dev->data;
const struct spi_nrfx_config *dev_config = dev->config;
void *reg = dev_config->spim.p_reg;
void *reg = dev_data->spim.p_reg;
if (deactivate_cs) {
spi_context_cs_control(&dev_data->ctx, false);
@@ -165,7 +135,7 @@ static int configure(const struct device *dev,
struct spi_context *ctx = &dev_data->ctx;
uint32_t max_freq = dev_config->max_freq;
nrfx_spim_config_t config;
nrfx_err_t result;
int result;
uint32_t sck_pin;
if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) {
@@ -223,22 +193,22 @@ static int configure(const struct device *dev,
config.mode = get_nrf_spim_mode(spi_cfg->operation);
config.bit_order = get_nrf_spim_bit_order(spi_cfg->operation);
sck_pin = nrfy_spim_sck_pin_get(dev_config->spim.p_reg);
sck_pin = nrfy_spim_sck_pin_get(dev_data->spim.p_reg);
if (sck_pin != NRF_SPIM_PIN_NOT_CONNECTED) {
nrfy_gpio_pin_write(sck_pin, spi_cfg->operation & SPI_MODE_CPOL ? 1 : 0);
}
if (dev_data->initialized) {
nrfx_spim_uninit(&dev_config->spim);
nrfx_spim_uninit(&dev_data->spim);
dev_data->initialized = false;
}
result = nrfx_spim_init(&dev_config->spim, &config,
result = nrfx_spim_init(&dev_data->spim, &config,
event_handler, (void *)dev);
if (result != NRFX_SUCCESS) {
LOG_ERR("Failed to initialize nrfx driver: %08x", result);
return -EIO;
if (result < 0) {
LOG_ERR("Failed to initialize nrfx driver: %d", result);
return result;
}
dev_data->initialized = true;
@@ -248,89 +218,6 @@ static int configure(const struct device *dev,
return 0;
}
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
static const nrfx_gpiote_t gpiote = NRFX_GPIOTE_INSTANCE(0);
/*
* Brief Workaround for transmitting 1 byte with SPIM.
*
* Derived from the setup_workaround_for_ftpan_58() function from
* the nRF52832 Rev 1 Errata v1.6 document anomaly 58 workaround.
*
* Warning Must not be used when transmitting multiple bytes.
*
* Warning After this workaround is used, the user must reset the PPI
* channel and the GPIOTE channel before attempting to transmit multiple
* bytes.
*/
static void anomaly_58_workaround_setup(const struct device *dev)
{
struct spi_nrfx_data *dev_data = dev->data;
const struct spi_nrfx_config *dev_config = dev->config;
NRF_SPIM_Type *spim = dev_config->spim.p_reg;
uint32_t ppi_ch = dev_data->ppi_ch;
uint32_t gpiote_ch = dev_data->gpiote_ch;
uint32_t eep = (uint32_t)&gpiote.p_reg->EVENTS_IN[gpiote_ch];
uint32_t tep = (uint32_t)&spim->TASKS_STOP;
dev_data->anomaly_58_workaround_active = true;
/* Create an event when SCK toggles */
nrf_gpiote_event_configure(gpiote.p_reg, gpiote_ch, spim->PSEL.SCK,
GPIOTE_CONFIG_POLARITY_Toggle);
nrf_gpiote_event_enable(gpiote.p_reg, gpiote_ch);
/* Stop the spim instance when SCK toggles */
nrf_ppi_channel_endpoint_setup(NRF_PPI, ppi_ch, eep, tep);
nrf_ppi_channel_enable(NRF_PPI, ppi_ch);
/* The spim instance cannot be stopped mid-byte, so it will finish
* transmitting the first byte and then stop. Effectively ensuring
* that only 1 byte is transmitted.
*/
}
static void anomaly_58_workaround_clear(struct spi_nrfx_data *dev_data)
{
uint32_t ppi_ch = dev_data->ppi_ch;
uint32_t gpiote_ch = dev_data->gpiote_ch;
if (dev_data->anomaly_58_workaround_active) {
nrf_ppi_channel_disable(NRF_PPI, ppi_ch);
nrf_gpiote_task_disable(gpiote.p_reg, gpiote_ch);
dev_data->anomaly_58_workaround_active = false;
}
}
static int anomaly_58_workaround_init(const struct device *dev)
{
struct spi_nrfx_data *dev_data = dev->data;
const struct spi_nrfx_config *dev_config = dev->config;
nrfx_err_t err_code;
dev_data->anomaly_58_workaround_active = false;
if (dev_config->anomaly_58_workaround) {
err_code = nrfx_ppi_channel_alloc(&dev_data->ppi_ch);
if (err_code != NRFX_SUCCESS) {
LOG_ERR("Failed to allocate PPI channel");
return -ENODEV;
}
err_code = nrfx_gpiote_channel_alloc(&gpiote, &dev_data->gpiote_ch);
if (err_code != NRFX_SUCCESS) {
LOG_ERR("Failed to allocate GPIOTE channel");
return -ENODEV;
}
LOG_DBG("PAN 58 workaround enabled for %s: ppi %u, gpiote %u",
dev->name, dev_data->ppi_ch, dev_data->gpiote_ch);
}
return 0;
}
#endif
static void finish_transaction(const struct device *dev, int error)
{
struct spi_nrfx_data *dev_data = dev->data;
@@ -361,7 +248,6 @@ static void transfer_next_chunk(const struct device *dev)
if (chunk_len > 0) {
nrfx_spim_xfer_desc_t xfer;
nrfx_err_t result;
const uint8_t *tx_buf = ctx->tx_buf;
uint8_t *rx_buf = ctx->rx_buf;
@@ -371,7 +257,7 @@ static void transfer_next_chunk(const struct device *dev)
#ifdef SPI_BUFFER_IN_RAM
if (spi_context_tx_buf_on(ctx) &&
!nrf_dma_accessible_check(&dev_config->spim.p_reg, tx_buf)) {
!nrf_dma_accessible_check(&dev_data->spim.p_reg, tx_buf)) {
if (chunk_len > CONFIG_SPI_NRFX_RAM_BUFFER_SIZE) {
chunk_len = CONFIG_SPI_NRFX_RAM_BUFFER_SIZE;
@@ -382,7 +268,7 @@ static void transfer_next_chunk(const struct device *dev)
}
if (spi_context_rx_buf_on(ctx) &&
!nrf_dma_accessible_check(&dev_config->spim.p_reg, rx_buf)) {
!nrf_dma_accessible_check(&dev_data->spim.p_reg, rx_buf)) {
if (chunk_len > CONFIG_SPI_NRFX_RAM_BUFFER_SIZE) {
chunk_len = CONFIG_SPI_NRFX_RAM_BUFFER_SIZE;
@@ -409,26 +295,9 @@ static void transfer_next_chunk(const struct device *dev)
goto in_alloc_failed;
}
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
if (xfer.rx_length == 1 && xfer.tx_length <= 1) {
if (dev_config->anomaly_58_workaround) {
anomaly_58_workaround_setup(dev);
} else {
LOG_WRN("Transaction aborted since it would trigger "
"nRF52832 PAN 58");
error = -EIO;
}
}
#endif
error = nrfx_spim_xfer(&dev_data->spim, &xfer, 0);
if (error == 0) {
result = nrfx_spim_xfer(&dev_config->spim, &xfer, 0);
if (result == NRFX_SUCCESS) {
return;
}
error = -EIO;
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
anomaly_58_workaround_clear(dev_data);
#endif
return;
}
/* On nrfx_spim_xfer() error */
@@ -442,7 +311,7 @@ out_alloc_failed:
finish_transaction(dev, error);
}
static void event_handler(const nrfx_spim_evt_t *p_event, void *p_context)
static void event_handler(const nrfx_spim_event_t *p_event, void *p_context)
{
const struct device *dev = p_context;
struct spi_nrfx_data *dev_data = dev->data;
@@ -457,10 +326,6 @@ static void event_handler(const nrfx_spim_evt_t *p_event, void *p_context)
return;
}
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
anomaly_58_workaround_clear(dev_data);
#endif
if (spi_context_tx_buf_on(&dev_data->ctx)) {
dmm_buffer_out_release(dev_config->mem_reg,
(void **)p_event->xfer_desc.p_tx_buffer);
@@ -497,7 +362,7 @@ static int transceive(const struct device *dev,
{
struct spi_nrfx_data *dev_data = dev->data;
const struct spi_nrfx_config *dev_config = dev->config;
void *reg = dev_config->spim.p_reg;
void *reg = dev_data->spim.p_reg;
int error;
pm_device_runtime_get(dev);
@@ -509,7 +374,7 @@ static int transceive(const struct device *dev,
dev_data->busy = true;
if (dev_config->wake_pin != WAKE_PIN_NOT_USED) {
error = spi_nrfx_wake_request(&dev_config->wake_gpiote,
error = spi_nrfx_wake_request(dev_config->wake_gpiote,
dev_config->wake_pin);
if (error == -ETIMEDOUT) {
LOG_WRN("Waiting for WAKE acknowledgment timed out");
@@ -539,7 +404,7 @@ static int transceive(const struct device *dev,
/* Abort the current transfer by deinitializing
* the nrfx driver.
*/
nrfx_spim_uninit(&dev_config->spim);
nrfx_spim_uninit(&dev_data->spim);
dev_data->initialized = false;
/* Make sure the transaction is finished (it may be
@@ -554,9 +419,6 @@ static int transceive(const struct device *dev,
#else
dev_data->ctx.ready = 0;
#endif /* CONFIG_MULTITHREADING */
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
anomaly_58_workaround_clear(dev_data);
#endif
} else if (error) {
finalize_spi_transaction(dev, true);
}
@@ -629,6 +491,7 @@ static int spim_resume(const struct device *dev)
{
const struct spi_nrfx_config *dev_config = dev->config;
struct spi_nrfx_data *dev_data = dev->data;
(void)dev_data;
(void)pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
/* nrfx_spim_init() will be called at configuration before
@@ -646,13 +509,15 @@ static void spim_suspend(const struct device *dev)
{
const struct spi_nrfx_config *dev_config = dev->config;
struct spi_nrfx_data *dev_data = dev->data;
int err;
if (dev_data->initialized) {
nrfx_spim_uninit(&dev_config->spim);
nrfx_spim_uninit(&dev_data->spim);
dev_data->initialized = false;
}
spi_context_cs_put_all(&dev_data->ctx);
err = spi_context_cs_put_all(&dev_data->ctx);
(void)err;
(void)pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_SLEEP);
}
@@ -682,7 +547,7 @@ static int spi_nrfx_init(const struct device *dev)
(void)pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_SLEEP);
if (dev_config->wake_pin != WAKE_PIN_NOT_USED) {
err = spi_nrfx_wake_init(&dev_config->wake_gpiote, dev_config->wake_pin);
err = spi_nrfx_wake_init(dev_config->wake_gpiote, dev_config->wake_pin);
if (err == -ENODEV) {
LOG_ERR("Failed to allocate GPIOTE channel for WAKE");
return err;
@@ -702,12 +567,6 @@ static int spi_nrfx_init(const struct device *dev)
spi_context_unlock_unconditionally(&dev_data->ctx);
#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
err = anomaly_58_workaround_init(dev);
if (err < 0) {
return err;
}
#endif
return pm_device_driver_init(dev, spim_nrfx_pm_action);
}
@@ -734,81 +593,74 @@ static int spi_nrfx_deinit(const struct device *dev)
}
#endif
#define SPI_NRFX_SPIM_EXTENDED_CONFIG(idx) \
#define SPI_NRFX_SPIM_EXTENDED_CONFIG(inst) \
IF_ENABLED(NRFX_SPIM_EXTENDED_ENABLED, \
(.dcx_pin = NRF_SPIM_PIN_NOT_CONNECTED, \
COND_CODE_1(SPIM_PROP(idx, rx_delay_supported), \
(.rx_delay = SPIM_PROP(idx, rx_delay),), \
COND_CODE_1(DT_INST_PROP(inst, rx_delay_supported), \
(.rx_delay = DT_INST_PROP(inst, rx_delay),), \
()) \
))
#define SPI_NRFX_SPIM_DEFINE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(SPIM(idx)); \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(SPIM(idx)); \
static void irq_connect##idx(void) \
{ \
IRQ_CONNECT(DT_IRQN(SPIM(idx)), DT_IRQ(SPIM(idx), priority), \
nrfx_isr, nrfx_spim_##idx##_irq_handler, 0); \
} \
#define SPI_NRFX_SPIM_DEFINE(inst) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(DT_DRV_INST(inst)); \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(DT_DRV_INST(inst)); \
IF_ENABLED(SPI_BUFFER_IN_RAM, \
(static uint8_t spim_##idx##_tx_buffer \
(static uint8_t spim_##inst##_tx_buffer \
[CONFIG_SPI_NRFX_RAM_BUFFER_SIZE] \
DMM_MEMORY_SECTION(SPIM(idx)); \
static uint8_t spim_##idx##_rx_buffer \
DMM_MEMORY_SECTION(DT_DRV_INST(inst)); \
static uint8_t spim_##inst##_rx_buffer \
[CONFIG_SPI_NRFX_RAM_BUFFER_SIZE] \
DMM_MEMORY_SECTION(SPIM(idx));)) \
static struct spi_nrfx_data spi_##idx##_data = { \
DMM_MEMORY_SECTION(DT_DRV_INST(inst));)) \
static struct spi_nrfx_data spi_##inst##_data = { \
.spim = NRFX_SPIM_INSTANCE(DT_INST_REG_ADDR(inst)), \
IF_ENABLED(CONFIG_MULTITHREADING, \
(SPI_CONTEXT_INIT_LOCK(spi_##idx##_data, ctx),)) \
(SPI_CONTEXT_INIT_LOCK(spi_##inst##_data, ctx),)) \
IF_ENABLED(CONFIG_MULTITHREADING, \
(SPI_CONTEXT_INIT_SYNC(spi_##idx##_data, ctx),)) \
SPI_CONTEXT_CS_GPIOS_INITIALIZE(SPIM(idx), ctx) \
(SPI_CONTEXT_INIT_SYNC(spi_##inst##_data, ctx),)) \
SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(inst), ctx) \
IF_ENABLED(SPI_BUFFER_IN_RAM, \
(.tx_buffer = spim_##idx##_tx_buffer, \
.rx_buffer = spim_##idx##_rx_buffer,)) \
.dev = DEVICE_DT_GET(SPIM(idx)), \
(.tx_buffer = spim_##inst##_tx_buffer, \
.rx_buffer = spim_##inst##_rx_buffer,)) \
.dev = DEVICE_DT_GET(DT_DRV_INST(inst)), \
.busy = false, \
}; \
PINCTRL_DT_DEFINE(SPIM(idx)); \
static const struct spi_nrfx_config spi_##idx##z_config = { \
.spim = { \
.p_reg = (NRF_SPIM_Type *)DT_REG_ADDR(SPIM(idx)), \
.drv_inst_idx = NRFX_SPIM##idx##_INST_IDX, \
}, \
.max_freq = SPIM_PROP(idx, max_frequency), \
static void irq_connect##inst(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), \
nrfx_spim_irq_handler, &spi_##inst##_data.spim, 0); \
} \
PINCTRL_DT_INST_DEFINE(inst); \
static const struct spi_nrfx_config spi_##inst##z_config = { \
.max_freq = DT_INST_PROP(inst, max_frequency), \
.def_config = { \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.ss_pin = NRF_SPIM_PIN_NOT_CONNECTED, \
.orc = SPIM_PROP(idx, overrun_character), \
SPI_NRFX_SPIM_EXTENDED_CONFIG(idx) \
.orc = DT_INST_PROP(inst, overrun_character), \
SPI_NRFX_SPIM_EXTENDED_CONFIG(inst) \
}, \
.irq_connect = irq_connect##idx, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(SPIM(idx)), \
.max_chunk_len = BIT_MASK(SPIM_PROP(idx, easydma_maxcnt_bits)),\
COND_CODE_1(CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58, \
(.anomaly_58_workaround = \
SPIM_PROP(idx, anomaly_58_workaround),), \
()) \
.wake_pin = NRF_DT_GPIOS_TO_PSEL_OR(SPIM(idx), wake_gpios, \
.irq_connect = irq_connect##inst, \
.max_chunk_len = BIT_MASK( \
DT_INST_PROP(inst, easydma_maxcnt_bits)), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.wake_gpiote = WAKE_GPIOTE_NODE(DT_DRV_INST(inst)), \
.wake_pin = NRF_DT_GPIOS_TO_PSEL_OR(DT_DRV_INST(inst), \
wake_gpios, \
WAKE_PIN_NOT_USED), \
.wake_gpiote = WAKE_GPIOTE_INSTANCE(SPIM(idx)), \
.mem_reg = DMM_DEV_TO_REG(SPIM(idx)), \
.mem_reg = DMM_DEV_TO_REG(DT_DRV_INST(inst)), \
}; \
BUILD_ASSERT(!SPIM_HAS_PROP(idx, wake_gpios) || \
!(DT_GPIO_FLAGS(SPIM(idx), wake_gpios) & GPIO_ACTIVE_LOW),\
BUILD_ASSERT(!DT_INST_NODE_HAS_PROP(inst, wake_gpios) || \
!(DT_GPIO_FLAGS(DT_DRV_INST(inst), wake_gpios) & \
GPIO_ACTIVE_LOW), \
"WAKE line must be configured as active high"); \
PM_DEVICE_DT_DEFINE(SPIM(idx), spim_nrfx_pm_action); \
SPI_DEVICE_DT_DEINIT_DEFINE(SPIM(idx), \
PM_DEVICE_DT_INST_DEFINE(inst, spim_nrfx_pm_action); \
SPI_DEVICE_DT_INST_DEINIT_DEFINE(inst, \
spi_nrfx_init, \
spi_nrfx_deinit, \
PM_DEVICE_DT_GET(SPIM(idx)), \
&spi_##idx##_data, \
&spi_##idx##z_config, \
PM_DEVICE_DT_INST_GET(inst), \
&spi_##inst##_data, \
&spi_##inst##z_config, \
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
&spi_nrfx_driver_api)
#define COND_NRF_SPIM_DEVICE(unused, prefix, i, _) \
IF_ENABLED(CONFIG_HAS_HW_NRF_SPIM##prefix##i, (SPI_NRFX_SPIM_DEFINE(prefix##i);))
SPIM_FOR_EACH_INSTANCE(COND_NRF_SPIM_DEVICE, (), (), _)
DT_INST_FOREACH_STATUS_OKAY(SPI_NRFX_SPIM_DEFINE)

125
drivers/spi/spi_nrfx_spis.c
View File

@@ -4,6 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_spis
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/spi/rtio.h>
#include <zephyr/drivers/pinctrl.h>
@@ -20,19 +22,8 @@ LOG_MODULE_REGISTER(spi_nrfx_spis, CONFIG_SPI_LOG_LEVEL);
#include "spi_context.h"
/*
* Current factors requiring use of DT_NODELABEL:
*
* - HAL design (requirement of drv_inst_idx in nrfx_spis_t)
* - Name-based HAL IRQ handlers, e.g. nrfx_spis_0_irq_handler
*/
#define SPIS_NODE(idx) \
COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(spis##idx)), (spis##idx), (spi##idx))
#define SPIS(idx) DT_NODELABEL(SPIS_NODE(idx))
#define SPIS_PROP(idx, prop) DT_PROP(SPIS(idx), prop)
#define SPIS_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(SPIS(idx), prop)
struct spi_nrfx_data {
nrfx_spis_t spis;
struct spi_context ctx;
const struct device *dev;
#ifdef CONFIG_MULTITHREADING
@@ -44,7 +35,6 @@ struct spi_nrfx_data {
};
struct spi_nrfx_config {
nrfx_spis_t spis;
nrfx_spis_config_t config;
void (*irq_connect)(void);
uint16_t max_buf_len;
@@ -82,7 +72,6 @@ static inline nrf_spis_bit_order_t get_nrf_spis_bit_order(uint16_t operation)
static int configure(const struct device *dev,
const struct spi_config *spi_cfg)
{
const struct spi_nrfx_config *dev_config = dev->config;
struct spi_nrfx_data *dev_data = dev->data;
struct spi_context *ctx = &dev_data->ctx;
@@ -124,7 +113,7 @@ static int configure(const struct device *dev,
ctx->config = spi_cfg;
nrf_spis_configure(dev_config->spis.p_reg,
nrf_spis_configure(dev_data->spis.p_reg,
get_nrf_spis_mode(spi_cfg->operation),
get_nrf_spis_bit_order(spi_cfg->operation));
@@ -137,7 +126,6 @@ static int prepare_for_transfer(const struct device *dev,
{
const struct spi_nrfx_config *dev_config = dev->config;
struct spi_nrfx_data *dev_data = dev->data;
nrfx_err_t result;
uint8_t *dmm_tx_buf;
uint8_t *dmm_rx_buf;
int err;
@@ -163,11 +151,10 @@ static int prepare_for_transfer(const struct device *dev,
goto in_alloc_failed;
}
result = nrfx_spis_buffers_set(&dev_config->spis,
err = nrfx_spis_buffers_set(&dev_data->spis,
dmm_tx_buf, tx_buf_len,
dmm_rx_buf, rx_buf_len);
if (result != NRFX_SUCCESS) {
err = -EIO;
if (err != 0) {
goto buffers_set_failed;
}
@@ -255,7 +242,7 @@ static int transceive(const struct device *dev,
if (dev_config->wake_gpio.port) {
wait_for_wake(dev_data, dev_config);
nrf_spis_enable(dev_config->spis.p_reg);
nrf_spis_enable(dev_data->spis.p_reg);
}
error = prepare_for_transfer(dev,
@@ -285,7 +272,7 @@ static int transceive(const struct device *dev,
}
if (dev_config->wake_gpio.port) {
nrf_spis_disable(dev_config->spis.p_reg);
nrf_spis_disable(dev_data->spis.p_reg);
}
}
@@ -339,7 +326,7 @@ static DEVICE_API(spi, spi_nrfx_driver_api) = {
.release = spi_nrfx_release,
};
static void event_handler(const nrfx_spis_evt_t *p_event, void *p_context)
static void event_handler(const nrfx_spis_event_t *p_event, void *p_context)
{
const struct device *dev = p_context;
struct spi_nrfx_data *dev_data = dev->data;
@@ -367,9 +354,10 @@ static void event_handler(const nrfx_spis_evt_t *p_event, void *p_context)
static void spi_nrfx_suspend(const struct device *dev)
{
const struct spi_nrfx_config *dev_config = dev->config;
struct spi_nrfx_data *dev_data = dev->data;
if (dev_config->wake_gpio.port == NULL) {
nrf_spis_disable(dev_config->spis.p_reg);
nrf_spis_disable(dev_data->spis.p_reg);
}
(void)pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_SLEEP);
@@ -378,11 +366,12 @@ static void spi_nrfx_suspend(const struct device *dev)
static void spi_nrfx_resume(const struct device *dev)
{
const struct spi_nrfx_config *dev_config = dev->config;
struct spi_nrfx_data *dev_data = dev->data;
(void)pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
if (dev_config->wake_gpio.port == NULL) {
nrf_spis_enable(dev_config->spis.p_reg);
nrf_spis_enable(dev_data->spis.p_reg);
}
}
@@ -408,18 +397,17 @@ static int spi_nrfx_init(const struct device *dev)
{
const struct spi_nrfx_config *dev_config = dev->config;
struct spi_nrfx_data *dev_data = dev->data;
nrfx_err_t result;
int err;
/* This sets only default values of mode and bit order. The ones to be
* actually used are set in configure() when a transfer is prepared.
*/
result = nrfx_spis_init(&dev_config->spis, &dev_config->config,
err = nrfx_spis_init(&dev_data->spis, &dev_config->config,
event_handler, (void *)dev);
if (result != NRFX_SUCCESS) {
if (err != 0) {
LOG_ERR("Failed to initialize device: %s", dev->name);
return -EBUSY;
return err;
}
/* When the WAKE line is used, the SPIS peripheral is enabled
@@ -430,7 +418,7 @@ static int spi_nrfx_init(const struct device *dev)
* with the SPIS peripheral enabled, significantly reduces idle
* power consumption.
*/
nrf_spis_disable(dev_config->spis.p_reg);
nrf_spis_disable(dev_data->spis.p_reg);
if (dev_config->wake_gpio.port) {
if (!gpio_is_ready_dt(&dev_config->wake_gpio)) {
@@ -463,59 +451,54 @@ static int spi_nrfx_init(const struct device *dev)
return pm_device_driver_init(dev, spi_nrfx_pm_action);
}
#define SPI_NRFX_SPIS_DEFINE(idx) \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(SPIS(idx)); \
static void irq_connect##idx(void) \
{ \
IRQ_CONNECT(DT_IRQN(SPIS(idx)), DT_IRQ(SPIS(idx), priority), \
nrfx_isr, nrfx_spis_##idx##_irq_handler, 0); \
} \
static struct spi_nrfx_data spi_##idx##_data = { \
#define SPI_NRFX_SPIS_DEFINE(inst) \
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(DT_DRV_INST(inst)); \
static struct spi_nrfx_data spi_##inst##_data = { \
.spis = NRFX_SPIS_INSTANCE(DT_INST_REG_ADDR(inst)), \
IF_ENABLED(CONFIG_MULTITHREADING, \
(SPI_CONTEXT_INIT_LOCK(spi_##idx##_data, ctx),)) \
(SPI_CONTEXT_INIT_LOCK(spi_##inst##_data, ctx),)) \
IF_ENABLED(CONFIG_MULTITHREADING, \
(SPI_CONTEXT_INIT_SYNC(spi_##idx##_data, ctx),)) \
.dev = DEVICE_DT_GET(SPIS(idx)), \
(SPI_CONTEXT_INIT_SYNC(spi_##inst##_data, ctx),)) \
.dev = DEVICE_DT_GET(DT_DRV_INST(inst)), \
IF_ENABLED(CONFIG_MULTITHREADING, \
(.wake_sem = Z_SEM_INITIALIZER( \
spi_##idx##_data.wake_sem, 0, 1),)) \
spi_##inst##_data.wake_sem, 0, 1),)) \
}; \
PINCTRL_DT_DEFINE(SPIS(idx)); \
static const struct spi_nrfx_config spi_##idx##z_config = { \
.spis = { \
.p_reg = (NRF_SPIS_Type *)DT_REG_ADDR(SPIS(idx)), \
.drv_inst_idx = NRFX_SPIS##idx##_INST_IDX, \
}, \
static void irq_connect##inst(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), \
nrfx_spis_irq_handler, &spi_##inst##_data.spis, 0); \
} \
PINCTRL_DT_INST_DEFINE(inst); \
static const struct spi_nrfx_config spi_##inst##z_config = { \
.config = { \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.mode = NRF_SPIS_MODE_0, \
.bit_order = NRF_SPIS_BIT_ORDER_MSB_FIRST, \
.orc = SPIS_PROP(idx, overrun_character), \
.def = SPIS_PROP(idx, def_char), \
.orc = DT_INST_PROP(inst, overrun_character), \
.def = DT_INST_PROP(inst, def_char), \
}, \
.irq_connect = irq_connect##idx, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(SPIS(idx)), \
.max_buf_len = BIT_MASK(SPIS_PROP(idx, easydma_maxcnt_bits)), \
.wake_gpio = GPIO_DT_SPEC_GET_OR(SPIS(idx), wake_gpios, {0}), \
.mem_reg = DMM_DEV_TO_REG(SPIS(idx)), \
.irq_connect = irq_connect##inst, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.max_buf_len = BIT_MASK(DT_INST_PROP(inst, \
easydma_maxcnt_bits)), \
.wake_gpio = GPIO_DT_SPEC_GET_OR(DT_DRV_INST(inst), \
wake_gpios, {0}), \
.mem_reg = DMM_DEV_TO_REG(DT_DRV_INST(inst)), \
}; \
BUILD_ASSERT(!DT_NODE_HAS_PROP(SPIS(idx), wake_gpios) || \
!(DT_GPIO_FLAGS(SPIS(idx), wake_gpios) & GPIO_ACTIVE_LOW),\
BUILD_ASSERT(!DT_INST_NODE_HAS_PROP(inst, wake_gpios) || \
!(DT_GPIO_FLAGS(DT_DRV_INST(inst), wake_gpios) & \
GPIO_ACTIVE_LOW), \
"WAKE line must be configured as active high"); \
PM_DEVICE_DT_DEFINE(SPIS(idx), spi_nrfx_pm_action, PM_DEVICE_ISR_SAFE);\
SPI_DEVICE_DT_DEFINE(SPIS(idx), \
spi_nrfx_init, \
PM_DEVICE_DT_GET(SPIS(idx)), \
&spi_##idx##_data, \
&spi_##idx##z_config, \
POST_KERNEL, \
CONFIG_SPI_INIT_PRIORITY, \
&spi_nrfx_driver_api)
PM_DEVICE_DT_INST_DEFINE(inst, spi_nrfx_pm_action, PM_DEVICE_ISR_SAFE);\
SPI_DEVICE_DT_INST_DEFINE(inst, \
spi_nrfx_init, \
PM_DEVICE_DT_INST_GET(inst), \
&spi_##inst##_data, \
&spi_##inst##z_config, \
POST_KERNEL, \
CONFIG_SPI_INIT_PRIORITY, \
&spi_nrfx_driver_api)
/* Macro creates device instance if it is enabled in devicetree. */
#define SPIS_DEVICE(periph, prefix, id, _) \
IF_ENABLED(CONFIG_HAS_HW_NRF_SPIS##prefix##id, (SPI_NRFX_SPIS_DEFINE(prefix##id);))
/* Macro iterates over nrfx_spis instances enabled in the nrfx_config.h. */
NRFX_FOREACH_ENABLED(SPIS, SPIS_DEVICE, (), (), _)
DT_INST_FOREACH_STATUS_OKAY(SPI_NRFX_SPIS_DEFINE)

2
drivers/timer/Kconfig.nrf_rtc
View File

@@ -10,7 +10,7 @@ config NRF_RTC_TIMER
depends on !$(dt_nodelabel_enabled,rtc1) && !DT_HAS_NORDIC_NRF_GRTC_ENABLED
select TICKLESS_CAPABLE
select SYSTEM_TIMER_HAS_DISABLE_SUPPORT
select NRFX_PPI if SOC_NRF52832
select NRFX_GPPI if SOC_NRF52832
default y if SYS_CLOCK_EXISTS
help
This module implements a kernel device driver for the nRF Real Time

75
drivers/timer/nrf_grtc_timer.c
View File

@@ -94,23 +94,12 @@ static inline uint64_t counter_sub(uint64_t a, uint64_t b)
static inline uint64_t counter(void)
{
uint64_t now;
nrfx_grtc_syscounter_get(&now);
return now;
return nrfx_grtc_syscounter_get();
}
static inline int get_comparator(uint32_t chan, uint64_t *cc)
{
nrfx_err_t result;
result = nrfx_grtc_syscounter_cc_value_read(chan, cc);
if (result != NRFX_SUCCESS) {
if (result != NRFX_ERROR_INVALID_PARAM) {
return -EAGAIN;
}
return -EPERM;
}
return 0;
return nrfx_grtc_syscounter_cc_value_read(chan, cc);
}
/*
@@ -177,14 +166,14 @@ static void sys_clock_timeout_handler(int32_t id, uint64_t cc_val, void *p_conte
int32_t z_nrf_grtc_timer_chan_alloc(void)
{
uint8_t chan;
nrfx_err_t err_code;
int err_code;
/* Prevent allocating all available channels - one must be left for system purposes. */
if (ext_channels_allocated >= EXT_CHAN_COUNT) {
return -ENOMEM;
}
err_code = nrfx_grtc_channel_alloc(&chan);
if (err_code != NRFX_SUCCESS) {
if (err_code < 0) {
return -ENOMEM;
}
ext_channels_allocated++;
@@ -194,9 +183,9 @@ int32_t z_nrf_grtc_timer_chan_alloc(void)
void z_nrf_grtc_timer_chan_free(int32_t chan)
{
IS_CHANNEL_ALLOWED_ASSERT(chan);
nrfx_err_t err_code = nrfx_grtc_channel_free(chan);
int err_code = nrfx_grtc_channel_free(chan);
if (err_code == NRFX_SUCCESS) {
if (err_code == 0) {
ext_channels_allocated--;
}
}
@@ -253,19 +242,13 @@ int z_nrf_grtc_timer_compare_read(int32_t chan, uint64_t *val)
static int compare_set_nolocks(int32_t chan, uint64_t target_time,
z_nrf_grtc_timer_compare_handler_t handler, void *user_data)
{
nrfx_err_t result;
__ASSERT_NO_MSG(target_time < COUNTER_SPAN);
nrfx_grtc_channel_t user_channel_data = {
.handler = handler,
.p_context = user_data,
.channel = chan,
};
result = nrfx_grtc_syscounter_cc_absolute_set(&user_channel_data, target_time, true);
if (result != NRFX_SUCCESS) {
return -EPERM;
}
return 0;
return nrfx_grtc_syscounter_cc_absolute_set(&user_channel_data, target_time, true);
}
static int compare_set(int32_t chan, uint64_t target_time,
@@ -318,7 +301,6 @@ int z_nrf_grtc_timer_capture_prepare(int32_t chan)
.p_context = NULL,
.channel = chan,
};
nrfx_err_t result;
IS_CHANNEL_ALLOWED_ASSERT(chan);
@@ -326,19 +308,12 @@ int z_nrf_grtc_timer_capture_prepare(int32_t chan)
* (makes CCEN=1). COUNTER_SPAN is used so as not to fire an event unnecessarily
* - it can be assumed that such a large value will never be reached.
*/
result = nrfx_grtc_syscounter_cc_absolute_set(&user_channel_data, COUNTER_SPAN, false);
if (result != NRFX_SUCCESS) {
return -EPERM;
}
return 0;
return nrfx_grtc_syscounter_cc_absolute_set(&user_channel_data, COUNTER_SPAN, false);
}
int z_nrf_grtc_timer_capture_read(int32_t chan, uint64_t *captured_time)
{
uint64_t capt_time;
nrfx_err_t result;
int result;
IS_CHANNEL_ALLOWED_ASSERT(chan);
@@ -348,16 +323,10 @@ int z_nrf_grtc_timer_capture_read(int32_t chan, uint64_t *captured_time)
*/
return -EBUSY;
}
result = nrfx_grtc_syscounter_cc_value_read(chan, &capt_time);
if (result != NRFX_SUCCESS) {
return -EPERM;
}
result = nrfx_grtc_syscounter_cc_value_read(chan, captured_time);
__ASSERT_NO_MSG(*captured_time < COUNTER_SPAN);
__ASSERT_NO_MSG(capt_time < COUNTER_SPAN);
*captured_time = capt_time;
return 0;
return result;
}
uint64_t z_nrf_grtc_timer_startup_value_get(void)
@@ -372,7 +341,7 @@ int z_nrf_grtc_wakeup_prepare(uint64_t wake_time_us)
return -ENOTSUP;
}
nrfx_err_t err_code;
int err_code;
static struct k_spinlock lock;
static uint8_t systemoff_channel;
uint64_t now = counter();
@@ -396,9 +365,9 @@ int z_nrf_grtc_wakeup_prepare(uint64_t wake_time_us)
k_spinlock_key_t key = k_spin_lock(&lock);
err_code = nrfx_grtc_channel_alloc(&systemoff_channel);
if (err_code != NRFX_SUCCESS) {
if (err_code < 0) {
k_spin_unlock(&lock, key);
return -ENOMEM;
return err_code;
}
(void)nrfx_grtc_syscounter_cc_int_disable(systemoff_channel);
ret = compare_set(systemoff_channel,
@@ -481,7 +450,7 @@ void sys_clock_disable(void)
static int sys_clock_driver_init(void)
{
nrfx_err_t err_code;
int err_code;
#if defined(CONFIG_GEN_SW_ISR_TABLE)
IRQ_CONNECT(DT_IRQN(GRTC_NODE), DT_IRQ(GRTC_NODE, priority), nrfx_isr,
@@ -505,19 +474,19 @@ static int sys_clock_driver_init(void)
#endif
err_code = nrfx_grtc_init(0);
if (err_code != NRFX_SUCCESS) {
return -EPERM;
if (err_code < 0) {
return err_code;
}
#if defined(CONFIG_NRF_GRTC_START_SYSCOUNTER)
err_code = nrfx_grtc_syscounter_start(true, &system_clock_channel_data.channel);
if (err_code != NRFX_SUCCESS) {
return err_code == NRFX_ERROR_NO_MEM ? -ENOMEM : -EPERM;
if (err_code < 0) {
return err_code;
}
#else
err_code = nrfx_grtc_channel_alloc(&system_clock_channel_data.channel);
if (err_code != NRFX_SUCCESS) {
return -ENOMEM;
if (err_code < 0) {
return err_code;
}
#endif /* CONFIG_NRF_GRTC_START_SYSCOUNTER */

15
drivers/timer/nrf_rtc_timer.c
View File

@@ -23,7 +23,7 @@
#define CUSTOM_COUNTER_BIT_WIDTH 1
#define WRAP_CH 0
#define SYS_CLOCK_CH 1
#include "nrfx_ppi.h"
#include "helpers/nrfx_gppi.h"
#else
#define CUSTOM_COUNTER_BIT_WIDTH 0
#define SYS_CLOCK_CH 0
@@ -806,8 +806,8 @@ static int sys_clock_driver_init(void)
alloc_mask &= ~BIT(WRAP_CH);
nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(WRAP_CH);
nrfx_err_t result;
nrf_ppi_channel_t ch;
int result;
nrfx_gppi_handle_t handle;
nrfy_rtc_event_enable(RTC, NRF_RTC_CHANNEL_INT_MASK(WRAP_CH));
nrfy_rtc_cc_set(RTC, WRAP_CH, COUNTER_MAX);
@@ -817,12 +817,11 @@ static int sys_clock_driver_init(void)
evt_addr = nrfy_rtc_event_address_get(RTC, evt);
task_addr = nrfy_rtc_task_address_get(RTC, NRF_RTC_TASK_CLEAR);
result = nrfx_ppi_channel_alloc(&ch);
if (result != NRFX_SUCCESS) {
return -ENODEV;
result = nrfx_gppi_conn_alloc(evt_addr, task_addr, &handle);
if (result < 0) {
return result;
}
(void)nrfx_ppi_channel_assign(ch, evt_addr, task_addr);
(void)nrfx_ppi_channel_enable(ch);
nrfx_gppi_conn_enable(handle);
#endif
return 0;
}

1
drivers/usb/common/nrf_usbd_common/nrf_usbd_common_errata.h
View File

@@ -12,7 +12,6 @@
#define NRF_USBD_COMMON_ERRATA_H__
#include <nrfx.h>
#include <nrf_erratas.h>
#ifndef NRF_USBD_COMMON_ERRATA_ENABLE
/**

2
drivers/usb/udc/udc_dwc2_vendor_quirks.h
View File

@@ -328,7 +328,7 @@ DT_INST_FOREACH_STATUS_OKAY(QUIRK_NRF_USBHS_DEFINE)
#define USBHS_DT_WRAPPER_REG_ADDR(n) UINT_TO_POINTER(DT_INST_REG_ADDR_BY_NAME(n, wrapper))
#include <nrf.h>
#include <nrfx.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>

10
drivers/watchdog/Kconfig.nrfx
View File

@@ -7,15 +7,7 @@ config WDT_NRFX
bool "nRF WDT nrfx driver"
default y
depends on DT_HAS_NORDIC_NRF_WDT_ENABLED
select NRFX_WDT0 if HAS_HW_NRF_WDT0
select NRFX_WDT1 if HAS_HW_NRF_WDT1
select NRFX_WDT30 if HAS_HW_NRF_WDT30
select NRFX_WDT31 if HAS_HW_NRF_WDT31
select NRFX_WDT010 if HAS_HW_NRF_WDT010
select NRFX_WDT011 if HAS_HW_NRF_WDT011
select NRFX_WDT130 if HAS_HW_NRF_WDT130
select NRFX_WDT131 if HAS_HW_NRF_WDT131
select NRFX_WDT132 if HAS_HW_NRF_WDT132
select NRFX_WDT
help
Enable support for nrfx WDT driver for nRF MCU series.

145
drivers/watchdog/wdt_nrfx.c
View File

@@ -4,6 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_wdt
#include <zephyr/kernel.h>
#include <zephyr/sys/math_extras.h>
#include <nrfx_wdt.h>
@@ -19,6 +21,7 @@ LOG_MODULE_REGISTER(wdt_nrfx);
#endif
struct wdt_nrfx_data {
nrfx_wdt_t wdt;
wdt_callback_t m_callbacks[NRF_WDT_CHANNEL_NUMBER];
uint32_t m_timeout;
uint8_t m_allocated_channels;
@@ -28,15 +31,10 @@ struct wdt_nrfx_data {
#endif
};
struct wdt_nrfx_config {
nrfx_wdt_t wdt;
};
static int wdt_nrf_setup(const struct device *dev, uint8_t options)
{
const struct wdt_nrfx_config *config = dev->config;
struct wdt_nrfx_data *data = dev->data;
nrfx_err_t err_code;
int err_code;
nrfx_wdt_config_t wdt_config = {
.reload_value = data->m_timeout
@@ -54,13 +52,13 @@ static int wdt_nrf_setup(const struct device *dev, uint8_t options)
wdt_config.behaviour |= NRF_WDT_BEHAVIOUR_RUN_HALT_MASK;
}
err_code = nrfx_wdt_reconfigure(&config->wdt, &wdt_config);
err_code = nrfx_wdt_reconfigure(&data->wdt, &wdt_config);
if (err_code != NRFX_SUCCESS) {
return -EBUSY;
if (err_code < 0) {
return err_code;
}
nrfx_wdt_enable(&config->wdt);
nrfx_wdt_enable(&data->wdt);
data->enabled = true;
return 0;
@@ -69,23 +67,22 @@ static int wdt_nrf_setup(const struct device *dev, uint8_t options)
static int wdt_nrf_disable(const struct device *dev)
{
#if NRFX_WDT_HAS_STOP
const struct wdt_nrfx_config *config = dev->config;
struct wdt_nrfx_data *data = dev->data;
nrfx_err_t err_code;
int err_code;
int channel_id;
err_code = nrfx_wdt_stop(&config->wdt);
err_code = nrfx_wdt_stop(&data->wdt);
if (err_code != NRFX_SUCCESS) {
if (err_code < 0) {
/* This can only happen if wdt_nrf_setup() is not called first. */
return -EFAULT;
return err_code;
}
#if defined(WDT_NRFX_SYNC_STOP)
k_sem_take(&data->sync_stop, K_FOREVER);
#endif
nrfx_wdt_channels_free(&config->wdt);
nrfx_wdt_channels_free(&data->wdt);
for (channel_id = 0; channel_id < data->m_allocated_channels; channel_id++) {
data->m_callbacks[channel_id] = NULL;
@@ -103,9 +100,8 @@ static int wdt_nrf_disable(const struct device *dev)
static int wdt_nrf_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
const struct wdt_nrfx_config *config = dev->config;
struct wdt_nrfx_data *data = dev->data;
nrfx_err_t err_code;
int err_code;
nrfx_wdt_channel_id channel_id;
if (data->enabled) {
@@ -125,10 +121,10 @@ static int wdt_nrf_install_timeout(const struct device *dev,
* in all nRF chips can use reload values (determining
* the timeout) from range 0xF-0xFFFFFFFF given in 32768 Hz
* clock ticks. This makes the allowed range of 0x1-0x07CFFFFF
* in milliseconds. Check if the provided value is within
* this range.
* in milliseconds, defined using NRF_WDT_RR_VALUE_MS symbol.
* Check if the provided value is within this range.
*/
if ((cfg->window.max == 0U) || (cfg->window.max > 0x07CFFFFF)) {
if ((cfg->window.max == 0U) || (cfg->window.max > NRF_WDT_RR_VALUE_MS)) {
return -EINVAL;
}
@@ -138,11 +134,11 @@ static int wdt_nrf_install_timeout(const struct device *dev,
return -EINVAL;
}
err_code = nrfx_wdt_channel_alloc(&config->wdt,
err_code = nrfx_wdt_channel_alloc(&data->wdt,
&channel_id);
if (err_code == NRFX_ERROR_NO_MEM) {
return -ENOMEM;
if (err_code == -ENOMEM) {
return err_code;
}
if (cfg->callback != NULL) {
@@ -155,7 +151,6 @@ static int wdt_nrf_install_timeout(const struct device *dev,
static int wdt_nrf_feed(const struct device *dev, int channel_id)
{
const struct wdt_nrfx_config *config = dev->config;
struct wdt_nrfx_data *data = dev->data;
if ((channel_id >= data->m_allocated_channels) || (channel_id < 0)) {
@@ -166,7 +161,7 @@ static int wdt_nrf_feed(const struct device *dev, int channel_id)
return -EAGAIN;
}
nrfx_wdt_channel_feed(&config->wdt,
nrfx_wdt_channel_feed(&data->wdt,
(nrfx_wdt_channel_id)channel_id);
return 0;
@@ -205,84 +200,46 @@ static void wdt_event_handler(const struct device *dev, nrf_wdt_event_t event_ty
#define WDT(idx) DT_NODELABEL(wdt##idx)
#define WDT_NRFX_WDT_IRQ(idx) \
#define WDT_NRFX_WDT_IRQ(inst) \
COND_CODE_1(CONFIG_WDT_NRFX_NO_IRQ, \
(), \
(IRQ_CONNECT(DT_IRQN(WDT(idx)), DT_IRQ(WDT(idx), priority), \
nrfx_isr, nrfx_wdt_##idx##_irq_handler, 0)))
(IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), \
nrfx_wdt_irq_handler, &wdt_##inst##_data.wdt, 0)))
#define WDT_NRFX_WDT_DEVICE(idx) \
static void wdt_##idx##_event_handler(nrf_wdt_event_t event_type, \
uint32_t requests, \
void *p_context) \
#define WDT_NRFX_WDT_DEVICE(inst) \
static void wdt_##inst##_event_handler(nrf_wdt_event_t event_type, \
uint32_t requests, \
void *p_context) \
{ \
wdt_event_handler(DEVICE_DT_GET(WDT(idx)), event_type, \
wdt_event_handler(DEVICE_DT_INST_GET(inst), event_type, \
requests, p_context); \
} \
static int wdt_##idx##_init(const struct device *dev) \
static struct wdt_nrfx_data wdt_##inst##_data = { \
.wdt = NRFX_WDT_INSTANCE(DT_INST_REG_ADDR(inst)), \
IF_ENABLED(WDT_NRFX_SYNC_STOP, \
(.sync_stop = Z_SEM_INITIALIZER( \
wdt_##inst##_data.sync_stop, 0, 1),)) \
}; \
static int wdt_##inst##_init(const struct device *dev) \
{ \
const struct wdt_nrfx_config *config = dev->config; \
nrfx_err_t err_code; \
WDT_NRFX_WDT_IRQ(idx); \
err_code = nrfx_wdt_init(&config->wdt, \
int err_code; \
struct wdt_nrfx_data *data = dev->data; \
WDT_NRFX_WDT_IRQ(inst); \
err_code = nrfx_wdt_init(&data->wdt, \
NULL, \
IS_ENABLED(CONFIG_WDT_NRFX_NO_IRQ) \
? NULL \
: wdt_##idx##_event_handler, \
: wdt_##inst##_event_handler, \
NULL); \
if (err_code != NRFX_SUCCESS) { \
return -EBUSY; \
} \
return 0; \
return err_code; \
} \
static struct wdt_nrfx_data wdt_##idx##_data = { \
IF_ENABLED(WDT_NRFX_SYNC_STOP, \
(.sync_stop = Z_SEM_INITIALIZER( \
wdt_##idx##_data.sync_stop, 0, 1),)) \
}; \
static const struct wdt_nrfx_config wdt_##idx##z_config = { \
.wdt = NRFX_WDT_INSTANCE(idx), \
}; \
DEVICE_DT_DEFINE(WDT(idx), \
wdt_##idx##_init, \
NULL, \
&wdt_##idx##_data, \
&wdt_##idx##z_config, \
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&wdt_nrfx_driver_api)
DEVICE_DT_INST_DEFINE(inst, \
wdt_##inst##_init, \
NULL, \
&wdt_##inst##_data, \
NULL, \
PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&wdt_nrfx_driver_api)
#ifdef CONFIG_HAS_HW_NRF_WDT0
WDT_NRFX_WDT_DEVICE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT1
WDT_NRFX_WDT_DEVICE(1);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT30
WDT_NRFX_WDT_DEVICE(30);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT31
WDT_NRFX_WDT_DEVICE(31);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT010
WDT_NRFX_WDT_DEVICE(010);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT011
WDT_NRFX_WDT_DEVICE(011);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT130
WDT_NRFX_WDT_DEVICE(130);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT131
WDT_NRFX_WDT_DEVICE(131);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT132
WDT_NRFX_WDT_DEVICE(132);
#endif
DT_INST_FOREACH_STATUS_OKAY(WDT_NRFX_WDT_DEVICE)

2
dts/arm/nordic/nrf52805.dtsi
View File

@@ -6,7 +6,7 @@
#include <arm/armv7-m.dtsi>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/dt-bindings/regulator/nrf5x.h>
/ {

8
dts/arm/nordic/nrf52810.dtsi
View File

@@ -1,8 +1,12 @@
/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/dt-bindings/regulator/nrf5x.h>
/ {

2
dts/arm/nordic/nrf52811.dtsi
View File

@@ -6,7 +6,7 @@
#include <arm/armv7-m.dtsi>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/dt-bindings/regulator/nrf5x.h>
/ {

8
dts/arm/nordic/nrf52832.dtsi
View File

@@ -1,8 +1,12 @@
/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2017 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/dt-bindings/regulator/nrf5x.h>
/ {

2
dts/arm/nordic/nrf52833.dtsi
View File

@@ -6,7 +6,7 @@
#include <arm/armv7-m.dtsi>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-v3.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/dt-bindings/regulator/nrf5x.h>
/ {

8
dts/arm/nordic/nrf52840.dtsi
View File

@@ -1,8 +1,12 @@
/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2017 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-v3.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/dt-bindings/regulator/nrf5x.h>
/ {

2
dts/arm/nordic/nrf5340_cpuapp.dtsi
View File

@@ -6,7 +6,7 @@
#include <arm/armv8-m.dtsi>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-v3.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
/ {
cpus {

2
dts/arm/nordic/nrf5340_cpuappns.dtsi
View File

@@ -8,7 +8,7 @@
#include <arm/armv8-m.dtsi>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-v3.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
/ {
cpus {

2
dts/arm/nordic/nrf91.dtsi
View File

@@ -6,7 +6,7 @@
#include <arm/armv8-m.dtsi>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
/ {
cpus {

2
dts/arm/nordic/nrf91ns.dtsi
View File

@@ -6,7 +6,7 @@
#include <arm/armv8-m.dtsi>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
/ {
cpus {

7
dts/bindings/spi/nordic,nrf-spim.yaml
View File

@@ -8,13 +8,6 @@ compatible: "nordic,nrf-spim"
include: ["nordic,nrf-spi-common.yaml", "memory-region.yaml"]
properties:
anomaly-58-workaround:
type: boolean
description: |
Enables the workaround for the nRF52832 SoC SPIM PAN 58 anomaly.
Must be used in conjunction with
CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58=y
rx-delay-supported:
type: boolean
description: |

2
dts/vendor/nordic/nrf54h20.dtsi vendored
View File

@@ -7,7 +7,7 @@
#include <mem.h>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-haltium.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/dt-bindings/clock/nrfs-audiopll.h>
#include <zephyr/dt-bindings/clock/nrf-auxpll.h>
#include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h>

3
dts/vendor/nordic/nrf54l_05_10_15.dtsi vendored
View File

@@ -6,7 +6,7 @@
#include <mem.h>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/dt-bindings/regulator/nrf5x.h>
/delete-node/ &sw_pwm;
@@ -108,6 +108,7 @@
#size-cells = <1>;
ranges = <0x0 0x40000000 0x10000000>;
#else
global_peripherals: peripheral@50000000 {
reg = <0x50000000 0x10000000>;
#address-cells = <1>;

5
dts/vendor/nordic/nrf54lm20a.dtsi vendored
View File

@@ -6,7 +6,7 @@
#include <mem.h>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/dt-bindings/regulator/nrf5x.h>
/delete-node/ &sw_pwm;
@@ -99,6 +99,7 @@
#ifdef USE_NON_SECURE_ADDRESS_MAP
/* intentionally empty because UICR is hardware fixed to Secure */
#else
uicr: uicr@ffd000 {
compatible = "nordic,nrf-uicr";
reg = <0xffd000 0x1000>;
@@ -128,6 +129,7 @@
#size-cells = <1>;
ranges = <0x0 0x40000000 0x10000000>;
#else
global_peripherals: peripheral@50000000 {
reg = <0x50000000 0x10000000>;
ranges = <0x0 0x50000000 0x10000000>;
@@ -763,6 +765,7 @@
#ifdef USE_NON_SECURE_ADDRESS_MAP
/* intentionally empty because WDT30 is hardware fixed to Secure */
#else
wdt30: watchdog@108000 {
compatible = "nordic,nrf-wdt";
reg = <0x108000 0x620>;

2
dts/vendor/nordic/nrf9280.dtsi vendored
View File

@@ -6,7 +6,7 @@
#include <mem.h>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-haltium.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h>
#include <zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h>
#include <zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h>

27
include/zephyr/drivers/gpio/gpio_nrf.h Normal file
View File

@@ -0,0 +1,27 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_NRF_H
#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_NRF_H
#ifdef __cplusplus
extern "C" {
#endif
/** @brief Get pointer to GPIOTE driver instance
* associated with specified port device node.
*
* @param port Pointer to port device node.
*
* @return Pointer to GPIOTE driver instance. NULL if not found.
*/
void *gpio_nrf_gpiote_by_port_get(const struct device *port);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_NRF_H */

19
include/zephyr/dt-bindings/adc/nrf-saadc-haltium.h
View File

@@ -1,19 +0,0 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2025 Nordic Semiconductor ASA
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_HALTIUM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_HALTIUM_H_
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#define NRF_SAADC_AIN8 9
#define NRF_SAADC_AIN9 10
#define NRF_SAADC_AIN10 11
#define NRF_SAADC_AIN11 12
#define NRF_SAADC_AIN12 13
#define NRF_SAADC_AIN13 14
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_HALTIUM_H_ */

15
include/zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h
View File

@@ -1,15 +0,0 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Nordic Semiconductor ASA
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_NRF54L_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_NRF54L_H_
#include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
#define NRF_SAADC_AVDD 10
#define NRF_SAADC_DVDD 11
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_NRF54L_H_ */

14
include/zephyr/dt-bindings/adc/nrf-saadc-v2.h
View File

@@ -1,14 +0,0 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Nordic Semiconductor ASA
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V2_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V2_H_
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#define NRF_SAADC_VDD 9
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V2_H_ */

14
include/zephyr/dt-bindings/adc/nrf-saadc-v3.h
View File

@@ -1,14 +0,0 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Nordic Semiconductor ASA
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V3_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V3_H_
#include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
#define NRF_SAADC_VDDHDIV5 13
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V3_H_ */

41
include/zephyr/dt-bindings/adc/nrf-saadc.h
View File

@@ -7,6 +7,21 @@
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_H_
#define NRF_SAADC_AIN0 0
#define NRF_SAADC_AIN1 1
#define NRF_SAADC_AIN2 2
#define NRF_SAADC_AIN3 3
#define NRF_SAADC_AIN4 4
#define NRF_SAADC_AIN5 5
#define NRF_SAADC_AIN6 6
#define NRF_SAADC_AIN7 7
#define NRF_SAADC_AIN8 8
#define NRF_SAADC_AIN9 9
#define NRF_SAADC_AIN10 10
#define NRF_SAADC_AIN11 11
#define NRF_SAADC_AIN12 12
#define NRF_SAADC_AIN13 13
/**
* @brief Short ADC negative input to ground
*
@@ -30,14 +45,22 @@
* zephyr,input-positive = <NRF_SAADC_AIN3>;
* @endcode
*/
#define NRF_SAADC_GND 0
#define NRF_SAADC_AIN0 1
#define NRF_SAADC_AIN1 2
#define NRF_SAADC_AIN2 3
#define NRF_SAADC_AIN3 4
#define NRF_SAADC_AIN4 5
#define NRF_SAADC_AIN5 6
#define NRF_SAADC_AIN6 7
#define NRF_SAADC_AIN7 8
#define NRF_SAADC_GND (NRF_SAADC_AIN_VDD_SHIM_OFFSET - 1)
#define NRF_SAADC_AIN_VDD_SHIM_OFFSET 128
#define NRF_SAADC_VDD (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 0)
#define NRF_SAADC_VDDDIV2 (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 1)
#define NRF_SAADC_AVDD (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 2)
#define NRF_SAADC_DVDD (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 3)
#define NRF_SAADC_VDDHDIV5 (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 4)
#define NRF_SAADC_VDDL (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 5)
#define NRF_SAADC_DECB (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 6)
#define NRF_SAADC_VSS (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 7)
#define NRF_SAADC_VDDAO3V0 (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 8)
#define NRF_SAADC_VDDAO1V8 (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 9)
#define NRF_SAADC_VDDAO0V8 (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 10)
#define NRF_SAADC_VDDRF (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 11)
#define NRF_SAADC_VBAT (NRF_SAADC_AIN_VDD_SHIM_OFFSET + 12)
#define NRF_SAADC_AIN_DISABLED 255 /* UINT8_MAX */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_H_ */

6
include/zephyr/dt-bindings/comparator/nrf-comp.h
View File

@@ -15,7 +15,9 @@
#define NRF_COMP_AIN5 5 /** AIN5 external input */
#define NRF_COMP_AIN6 6 /** AIN6 external input */
#define NRF_COMP_AIN7 7 /** AIN7 external input */
#define NRF_COMP_AIN_VDD_DIV2 8 /** VDD / 2 */
#define NRF_COMP_AIN_VDDH_DIV5 9 /** VDDH / 5 */
#define NRF_COMP_AIN_VDD_SHIM_OFFSET 128
#define NRF_COMP_AIN_VDD_DIV2 (NRF_COMP_AIN_VDD_SHIM_OFFSET + 1)
#define NRF_COMP_AIN_VDDH_DIV5 (NRF_COMP_AIN_VDD_SHIM_OFFSET + 4)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_COMP_H_ */

2
modules/hal_nordic/nrf_802154/sl_opensource/platform/nrf_802154_clock_zephyr.c
View File

@@ -9,7 +9,7 @@
#include <stddef.h>
#include <compiler_abstraction.h>
#include <nrfx.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <nrf_sys_event.h>

49
modules/hal_nordic/nrfx/CMakeLists.txt
View File

@@ -11,16 +11,30 @@ if(NOT DEFINED NRFX_DIR)
set(NRFX_DIR ${ZEPHYR_CURRENT_MODULE_DIR}/nrfx CACHE PATH "nrfx Directory")
endif()
if(NOT DEFINED CONFIG_SOC_NORDIC_BSP_NAME)
message(FATAL_ERROR "CONFIG_SOC_NORDIC_BSP_NAME has to be defined.")
endif()
set(INC_DIR ${NRFX_DIR}/drivers/include)
set(SRC_DIR ${NRFX_DIR}/drivers/src)
set(MDK_DIR ${NRFX_DIR}/mdk)
set(HELPERS_DIR ${NRFX_DIR}/helpers)
if(DEFINED CONFIG_SOC_NORDIC_BSP_PATH_OVERRIDE)
set(BSP_DIR ${ZEPHYR_CURRENT_MODULE_DIR}/${CONFIG_SOC_NORDIC_BSP_PATH_OVERRIDE}/${CONFIG_SOC_NORDIC_BSP_NAME})
else()
set(BSP_DIR ${NRFX_DIR}/bsp/${CONFIG_SOC_NORDIC_BSP_NAME})
endif()
set(MDK_DIR ${BSP_DIR}/mdk)
zephyr_include_directories(${NRFX_DIR})
zephyr_include_directories(${INC_DIR})
zephyr_include_directories(${MDK_DIR})
zephyr_include_directories(${BSP_DIR})
zephyr_include_directories(${BSP_DIR}/templates)
zephyr_include_directories(.)
include(${BSP_DIR}/zephyr/nrfx.cmake OPTIONAL)
# Define MDK defines globally
zephyr_compile_definitions_ifdef(CONFIG_SOC_SERIES_NRF51X NRF51)
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF51822_QFAA NRF51422_XXAA)
@@ -112,16 +126,27 @@ zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF92X ${MDK_DIR}/system_nrf92.c
zephyr_library_sources(nrfx_glue.c)
zephyr_library_sources(${HELPERS_DIR}/nrfx_flag32_allocator.c)
zephyr_library_sources_ifdef(CONFIG_HAS_NORDIC_RAM_CTRL ${HELPERS_DIR}/nrfx_ram_ctrl.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_GPPI ${HELPERS_DIR}/nrfx_gppi_dppi.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_GPPI ${HELPERS_DIR}/nrfx_gppi_ppi.c)
if(CONFIG_NRFX_GPPI AND NOT CONFIG_NRFX_GPPI_V1)
zephyr_library_sources_ifdef(CONFIG_HAS_HW_NRF_PPI ${HELPERS_DIR}/nrfx_gppi_ppi.c)
if(CONFIG_SOC_SERIES_NRF54LX OR CONFIG_HAS_HW_NRF_DPPIC)
zephyr_library_sources(${HELPERS_DIR}/nrfx_gppi_dppi.c)
endif()
zephyr_library_sources_ifdef(CONFIG_SOC_COMPATIBLE_NRF54LX ${BSP_DIR}/soc/interconnect/nrfx_gppi_lumos.c)
endif()
zephyr_library_sources_ifdef(CONFIG_NRFX_PRS ${SRC_DIR}/prs/nrfx_prs.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_ADC ${SRC_DIR}/nrfx_adc.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_CLOCK ${SRC_DIR}/nrfx_clock.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_CLOCK ${SRC_DIR}/nrfx_clock_hfclk.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_CLOCK ${SRC_DIR}/nrfx_clock_hfclkaudio.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_CLOCK ${SRC_DIR}/nrfx_clock_hfclk192m.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_CLOCK ${SRC_DIR}/nrfx_clock_lfclk.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_CLOCK ${SRC_DIR}/nrfx_clock_xo.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_CLOCK ${SRC_DIR}/nrfx_clock_xo24m.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_COMP ${SRC_DIR}/nrfx_comp.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_CRACEN ${SRC_DIR}/nrfx_cracen.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_DPPI ${SRC_DIR}/nrfx_dppi.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_EGU ${SRC_DIR}/nrfx_egu.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_GPIOTE ${SRC_DIR}/nrfx_gpiote.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_GRTC ${SRC_DIR}/nrfx_grtc.c)
@@ -133,8 +158,6 @@ zephyr_library_sources_ifdef(CONFIG_NRFX_NFCT ${SRC_DIR}/nrfx_nfct.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_NVMC ${SRC_DIR}/nrfx_nvmc.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_PDM ${SRC_DIR}/nrfx_pdm.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_POWER ${SRC_DIR}/nrfx_power.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_PPI ${SRC_DIR}/nrfx_ppi.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_PPIB ${SRC_DIR}/nrfx_ppib.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_PWM ${SRC_DIR}/nrfx_pwm.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_QDEC ${SRC_DIR}/nrfx_qdec.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_QSPI ${SRC_DIR}/nrfx_qspi.c)
@@ -195,15 +218,9 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_DISABLE_FICR_TRIMCNF NRF_DIS
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE NRF_SKIP_GLITCHDETECTOR_DISABLE)
zephyr_compile_definitions_ifndef(CONFIG_SOC_NRF54L_ANOMALY_56_WORKAROUND NRF54L_CONFIGURATION_56_ENABLE=0)
if(CONFIG_SOC_COMPATIBLE_NRF54LX AND CONFIG_NRFX_GPPI)
zephyr_library_sources(${HELPERS_DIR}/nrfx_gppi_dppi_ppib_lumos.c)
zephyr_library_sources(${NRFX_DIR}/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib.c)
endif()
if(CONFIG_SOC_SERIES_NRF54HX AND CONFIG_NRFX_GPPI)
zephyr_library_sources(${HELPERS_DIR}/nrfx_gppi_dppi_ppib.c)
zephyr_library_sources(${NRFX_DIR}/soc/interconnect/apb/nrfx_interconnect_apb.c)
zephyr_library_sources(${NRFX_DIR}/soc/interconnect/ipct/nrfx_interconnect_ipct.c)
if(CONFIG_SOC_SERIES_NRF54HX AND CONFIG_NRFX_GPPI_V1)
zephyr_library_sources(${HELPERS_DIR}/internal/nrfx_gppiv1_ipct.c)
zephyr_library_sources(${HELPERS_DIR}/internal/nrfx_gppiv1_shim.c)
endif()
# Get the SVD file for the current SoC

968
modules/hal_nordic/nrfx/Kconfig
View File

File diff suppressed because it is too large Load Diff

12
modules/hal_nordic/nrfx/Kconfig.logging
View File

@@ -16,10 +16,6 @@ config NRFX_COMP_LOG
bool "COMP driver logging"
depends on NRFX_COMP
config NRFX_DPPI_LOG
bool "DPPI driver logging"
depends on NRFX_DPPI
config NRFX_EGU_LOG
bool "EGU driver logging"
depends on NRFX_EGU
@@ -64,14 +60,6 @@ config NRFX_POWER_LOG
bool "POWER driver logging"
depends on NRFX_POWER
config NRFX_PPI_LOG
bool "PPI driver logging"
depends on NRFX_PPI
config NRFX_PPIB_LOG
bool "PPIB driver logging"
depends on NRFX_PPIB
config NRFX_PRS_LOG
bool "PRS driver logging"
depends on NRFX_PRS

84
modules/hal_nordic/nrfx/nrfx_config.h
View File

@@ -8,8 +8,8 @@
#define NRFX_CONFIG_H__
/* Define nrfx API version used in Zephyr. */
#define NRFX_CONFIG_API_VER_MAJOR 3
#define NRFX_CONFIG_API_VER_MINOR 12
#define NRFX_CONFIG_API_VER_MAJOR 4
#define NRFX_CONFIG_API_VER_MINOR 0
#define NRFX_CONFIG_API_VER_MICRO 0
/* Macros used in zephyr-specific config files. */
@@ -29,83 +29,5 @@
#endif
/* Use defaults for undefined symbols. */
#include <templates/nrfx_config_common.h>
#if defined(NRF51)
#include <templates/nrfx_config_nrf51.h>
#elif defined(NRF52805_XXAA)
#include <templates/nrfx_config_nrf52805.h>
#elif defined(NRF52810_XXAA)
#include <templates/nrfx_config_nrf52810.h>
#elif defined(NRF52811_XXAA)
#include <templates/nrfx_config_nrf52811.h>
#elif defined(NRF52820_XXAA)
#include <templates/nrfx_config_nrf52820.h>
#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
#include <templates/nrfx_config_nrf52832.h>
#elif defined(NRF52833_XXAA)
#include <templates/nrfx_config_nrf52833.h>
#elif defined(NRF52840_XXAA)
#include <templates/nrfx_config_nrf52840.h>
#elif defined(NRF5340_XXAA_APPLICATION)
#include <templates/nrfx_config_nrf5340_application.h>
#elif defined(NRF5340_XXAA_NETWORK)
#include <templates/nrfx_config_nrf5340_network.h>
#elif defined(NRF54H20_XXAA) && defined(NRF_APPLICATION)
#include <templates/nrfx_config_nrf54h20_application.h>
#elif defined(NRF54H20_XXAA) && defined(NRF_RADIOCORE)
#include <templates/nrfx_config_nrf54h20_radiocore.h>
#elif defined(NRF54H20_XXAA) && defined(NRF_PPR)
#include <templates/nrfx_config_nrf54h20_ppr.h>
#elif defined(NRF54H20_XXAA) && defined(NRF_FLPR)
#include <templates/nrfx_config_nrf54h20_flpr.h>
#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_APPLICATION)
#include <templates/nrfx_config_nrf54h20_enga_application.h>
#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_RADIOCORE)
#include <templates/nrfx_config_nrf54h20_enga_radiocore.h>
#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_PPR)
#include <templates/nrfx_config_nrf54h20_enga_ppr.h>
#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_FLPR)
#include <templates/nrfx_config_nrf54h20_enga_flpr.h>
#elif defined(NRF54H20_ENGB_XXAA) && defined(NRF_APPLICATION)
#include <templates/nrfx_config_nrf54h20_engb_application.h>
#elif defined(NRF54H20_ENGB_XXAA) && defined(NRF_RADIOCORE)
#include <templates/nrfx_config_nrf54h20_engb_radiocore.h>
#elif defined(NRF54H20_ENGB_XXAA) && defined(NRF_PPR)
#include <templates/nrfx_config_nrf54h20_engb_ppr.h>
#elif defined(NRF54H20_ENGB_XXAA) && defined(NRF_FLPR)
#include <templates/nrfx_config_nrf54h20_engb_flpr.h>
#elif defined(NRF54L05_XXAA) && defined(NRF_APPLICATION)
#include <templates/nrfx_config_nrf54l05_application.h>
#elif defined(NRF54L05_XXAA) && defined(NRF_FLPR)
#include <templates/nrfx_config_nrf54l05_flpr.h>
#elif defined(NRF54L10_XXAA) && defined(NRF_APPLICATION)
#include <templates/nrfx_config_nrf54l10_application.h>
#elif defined(NRF54L10_XXAA) && defined(NRF_FLPR)
#include <templates/nrfx_config_nrf54l10_flpr.h>
#elif defined(NRF54L15_XXAA) && defined(NRF_APPLICATION)
#include <templates/nrfx_config_nrf54l15_application.h>
#elif defined(NRF54L15_XXAA) && defined(NRF_FLPR)
#include <templates/nrfx_config_nrf54l15_flpr.h>
#elif defined(NRF54LM20A_ENGA_XXAA) && defined(NRF_APPLICATION)
#include <templates/nrfx_config_nrf54lm20a_enga_application.h>
#elif defined(NRF54LM20A_ENGA_XXAA) && defined(NRF_FLPR)
#include <templates/nrfx_config_nrf54lm20a_enga_flpr.h>
#elif defined(NRF54LV10A_ENGA_XXAA) && defined(NRF_APPLICATION)
#include <templates/nrfx_config_nrf54lv10a_enga_application.h>
#elif defined(NRF54LV10A_ENGA_XXAA) && defined(NRF_FLPR)
#include <templates/nrfx_config_nrf54lv10a_enga_flpr.h>
#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA)
#include <templates/nrfx_config_nrf91.h>
#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_APPLICATION)
#include <templates/nrfx_config_nrf9230_engb_application.h>
#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_RADIOCORE)
#include <templates/nrfx_config_nrf9230_engb_radiocore.h>
#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_PPR)
#include <templates/nrfx_config_nrf9230_engb_ppr.h>
#elif defined(NRF9230_ENGB_XXAA) && defined(NRF_FLPR)
#include <templates/nrfx_config_nrf9230_engb_flpr.h>
#else
#include "nrfx_config_ext.h"
#endif
#include "nrfx_templates_config.h"
#endif // NRFX_CONFIG_H__

40
modules/hal_nordic/nrfx/nrfx_glue.c
View File

@@ -6,11 +6,11 @@
#include <nrfx.h>
#include <zephyr/kernel.h>
#include <soc/nrfx_coredep.h>
#include <lib/nrfx_coredep.h>
void nrfx_isr(const void *irq_handler)
{
((nrfx_irq_handler_t)irq_handler)();
((nrfx_irq_handler_t)irq_handler)(NULL);
}
void nrfx_busy_wait(uint32_t usec_to_wait)
@@ -22,26 +22,22 @@ void nrfx_busy_wait(uint32_t usec_to_wait)
}
}
char const *nrfx_error_string_get(nrfx_err_t code)
char const *nrfx_error_string_get(int code)
{
#define NRFX_ERROR_STRING_CASE(code) case code: return #code
switch (code) {
NRFX_ERROR_STRING_CASE(NRFX_SUCCESS);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_INTERNAL);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_NO_MEM);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_NOT_SUPPORTED);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_INVALID_PARAM);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_INVALID_STATE);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_INVALID_LENGTH);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_TIMEOUT);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_FORBIDDEN);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_NULL);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_INVALID_ADDR);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_BUSY);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_ALREADY);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_DRV_TWI_ERR_OVERRUN);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_DRV_TWI_ERR_ANACK);
NRFX_ERROR_STRING_CASE(NRFX_ERROR_DRV_TWI_ERR_DNACK);
default: return "unknown";
switch (-code) {
case 0: return STRINGIFY(0);
case ECANCELED: return STRINGIFY(ECANCELED);
case ENOMEM: return STRINGIFY(ENOMEM);
case ENOTSUP: return STRINGIFY(ENOTSUP);
case EINVAL: return STRINGIFY(EINVAL);
case EINPROGRESS: return STRINGIFY(EINPROGRESS);
case E2BIG: return STRINGIFY(E2BIG);
case ETIMEDOUT: return STRINGIFY(ETIMEDOUT);
case EPERM: return STRINGIFY(EPERM);
case EFAULT: return STRINGIFY(EFAULT);
case EACCES: return STRINGIFY(EACCES);
case EBUSY: return STRINGIFY(EBUSY);
case EALREADY: return STRINGIFY(EALREADY);
default: return "unknown";
}
}

585
modules/hal_nordic/nrfx/nrfx_kconfig.h
View File

@@ -81,54 +81,8 @@
#ifdef CONFIG_NRFX_CRACEN
#define NRFX_CRACEN_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI
#define NRFX_DPPI_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI_LOG
#define NRFX_DPPI_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI0
#define NRFX_DPPI0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI00
#define NRFX_DPPI00_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI10
#define NRFX_DPPI10_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI20
#define NRFX_DPPI20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI30
#define NRFX_DPPI30_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI020
#define NRFX_DPPI020_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI120
#define NRFX_DPPI120_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI130
#define NRFX_DPPI130_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI131
#define NRFX_DPPI131_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI132
#define NRFX_DPPI132_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI133
#define NRFX_DPPI133_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI134
#define NRFX_DPPI134_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI135
#define NRFX_DPPI135_ENABLED 1
#endif
#ifdef CONFIG_NRFX_DPPI136
#define NRFX_DPPI136_ENABLED 1
#ifdef CONFIG_NRFX_CRACEN_BSIM_SUPPORT
#define NRFX_CRACEN_BSIM_SUPPORT 1
#endif
#ifdef CONFIG_NRFX_EGU
@@ -224,12 +178,6 @@
#ifdef CONFIG_NRFX_I2S_LOG
#define NRFX_I2S_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_I2S0
#define NRFX_I2S0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_I2S20
#define NRFX_I2S20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_IPC
#define NRFX_IPC_ENABLED 1
@@ -272,15 +220,6 @@
#ifdef CONFIG_NRFX_PDM_LOG
#define NRFX_PDM_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PDM0
#define NRFX_PDM0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PDM20
#define NRFX_PDM20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PDM21
#define NRFX_PDM21_ENABLED 1
#endif
#ifdef CONFIG_NRFX_POWER
#define NRFX_POWER_ENABLED 1
@@ -289,44 +228,6 @@
#define NRFX_POWER_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPI
#define NRFX_PPI_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPI_LOG
#define NRFX_PPI_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPIB
#define NRFX_PPIB_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPIB_LOG
#define NRFX_PPIB_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPIB00
#define NRFX_PPIB00_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPIB01
#define NRFX_PPIB01_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPIB10
#define NRFX_PPIB10_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPIB11
#define NRFX_PPIB11_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPIB20
#define NRFX_PPIB20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPIB21
#define NRFX_PPIB21_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPIB22
#define NRFX_PPIB22_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PPIB30
#define NRFX_PPIB30_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PRS
#define NRFX_PRS_ENABLED 1
#endif
@@ -355,42 +256,6 @@
#ifdef CONFIG_NRFX_PWM_LOG
#define NRFX_PWM_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM0
#define NRFX_PWM0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM1
#define NRFX_PWM1_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM2
#define NRFX_PWM2_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM3
#define NRFX_PWM3_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM20
#define NRFX_PWM20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM21
#define NRFX_PWM21_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM22
#define NRFX_PWM22_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM120
#define NRFX_PWM120_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM130
#define NRFX_PWM130_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM131
#define NRFX_PWM131_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM132
#define NRFX_PWM132_ENABLED 1
#endif
#ifdef CONFIG_NRFX_PWM133
#define NRFX_PWM133_ENABLED 1
#endif
#ifdef CONFIG_NRFX_QDEC
#define NRFX_QDEC_ENABLED 1
@@ -398,24 +263,6 @@
#ifdef CONFIG_NRFX_QDEC_LOG
#define NRFX_QDEC_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_QDEC0
#define NRFX_QDEC0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_QDEC1
#define NRFX_QDEC1_ENABLED 1
#endif
#ifdef CONFIG_NRFX_QDEC20
#define NRFX_QDEC20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_QDEC21
#define NRFX_QDEC21_ENABLED 1
#endif
#ifdef CONFIG_NRFX_QDEC130
#define NRFX_QDEC130_ENABLED 1
#endif
#ifdef CONFIG_NRFX_QDEC131
#define NRFX_QDEC131_ENABLED 1
#endif
#ifdef CONFIG_NRFX_QSPI
#define NRFX_QSPI_ENABLED 1
@@ -486,23 +333,11 @@
#ifdef CONFIG_NRFX_SPIM_LOG
#define NRFX_SPIM_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM0
#define NRFX_SPIM0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM1
#define NRFX_SPIM1_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM2
#define NRFX_SPIM2_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM3
#define NRFX_SPIM3_ENABLED 1
#ifdef CONFIG_NRF52_ANOMALY_198_WORKAROUND
#define NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED 1
#define NRF52_ERRATA_198_ENABLE_WORKAROUND 1
#endif
#endif
#ifdef CONFIG_NRFX_SPIM4
#define NRFX_SPIM4_ENABLED 1
#ifdef CONFIG_NRF52_ANOMALY_58_WORKAROUND
#define NRF52_ERRATA_58_ENABLE_WORKAROUND 1
#endif
#define NRFX_SPIM_DT_HAS_RX_DELAY(node) DT_PROP(node, rx_delay_supported) +
@@ -513,130 +348,12 @@
#endif
#endif
#ifdef CONFIG_NRFX_SPIM00
#define NRFX_SPIM00_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM01
#define NRFX_SPIM01_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM20
#define NRFX_SPIM20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM21
#define NRFX_SPIM21_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM22
#define NRFX_SPIM22_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM23
#define NRFX_SPIM23_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM24
#define NRFX_SPIM24_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM30
#define NRFX_SPIM30_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM120
#define NRFX_SPIM120_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM121
#define NRFX_SPIM121_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM130
#define NRFX_SPIM130_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM131
#define NRFX_SPIM131_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM132
#define NRFX_SPIM132_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM133
#define NRFX_SPIM133_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM134
#define NRFX_SPIM134_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM135
#define NRFX_SPIM135_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM136
#define NRFX_SPIM136_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIM137
#define NRFX_SPIM137_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS
#define NRFX_SPIS_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS_LOG
#define NRFX_SPIS_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS0
#define NRFX_SPIS0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS1
#define NRFX_SPIS1_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS2
#define NRFX_SPIS2_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS3
#define NRFX_SPIS3_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS00
#define NRFX_SPIS00_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS01
#define NRFX_SPIS01_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS20
#define NRFX_SPIS20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS21
#define NRFX_SPIS21_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS22
#define NRFX_SPIS22_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS23
#define NRFX_SPIS23_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS24
#define NRFX_SPIS24_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS30
#define NRFX_SPIS30_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS120
#define NRFX_SPIS120_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS130
#define NRFX_SPIS130_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS131
#define NRFX_SPIS131_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS132
#define NRFX_SPIS132_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS133
#define NRFX_SPIS133_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS134
#define NRFX_SPIS134_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS135
#define NRFX_SPIS135_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS136
#define NRFX_SPIS136_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SPIS137
#define NRFX_SPIS137_ENABLED 1
#endif
#ifdef CONFIG_NRFX_SYSTICK
#define NRFX_SYSTICK_ENABLED 1
@@ -659,84 +376,6 @@
#ifdef CONFIG_NRFX_TIMER
#define NRFX_TIMER_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER_LOG
#define NRFX_TIMER_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER0
#define NRFX_TIMER0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER1
#define NRFX_TIMER1_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER2
#define NRFX_TIMER2_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER3
#define NRFX_TIMER3_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER4
#define NRFX_TIMER4_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER00
#define NRFX_TIMER00_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER10
#define NRFX_TIMER10_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER20
#define NRFX_TIMER20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER21
#define NRFX_TIMER21_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER22
#define NRFX_TIMER22_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER23
#define NRFX_TIMER23_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER24
#define NRFX_TIMER24_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER020
#define NRFX_TIMER020_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER021
#define NRFX_TIMER021_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER022
#define NRFX_TIMER022_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER120
#define NRFX_TIMER120_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER121
#define NRFX_TIMER121_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER130
#define NRFX_TIMER130_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER131
#define NRFX_TIMER131_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER132
#define NRFX_TIMER132_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER133
#define NRFX_TIMER133_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER134
#define NRFX_TIMER134_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER135
#define NRFX_TIMER135_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER136
#define NRFX_TIMER136_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TIMER137
#define NRFX_TIMER137_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWI
#define NRFX_TWI_ENABLED 1
@@ -757,68 +396,11 @@
#ifdef CONFIG_NRFX_TWIM_LOG
#define NRFX_TWIM_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM0
#define NRFX_TWIM0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM1
#define NRFX_TWIM1_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM2
#define NRFX_TWIM2_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM3
#define NRFX_TWIM3_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM20
#define NRFX_TWIM20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM21
#define NRFX_TWIM21_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM22
#define NRFX_TWIM22_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM23
#define NRFX_TWIM23_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM24
#define NRFX_TWIM24_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM30
#define NRFX_TWIM30_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM120
#define NRFX_TWIM120_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM130
#define NRFX_TWIM130_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM131
#define NRFX_TWIM131_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM132
#define NRFX_TWIM132_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM133
#define NRFX_TWIM133_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM134
#define NRFX_TWIM134_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM135
#define NRFX_TWIM135_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM136
#define NRFX_TWIM136_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIM137
#define NRFX_TWIM137_ENABLED 1
#endif
#ifdef CONFIG_NRF52_ANOMALY_219_WORKAROUND
#define NRFX_TWIM_NRF52_ANOMALY_219_WORKAROUND_ENABLED 1
#define NRF52_ERRATA_219_ENABLE_WORKAROUND 1
#endif
#ifdef CONFIG_SOC_NRF53_ANOMALY_47_WORKAROUND
#define NRFX_TWIM_NRF53_ANOMALY_47_WORKAROUND_ENABLED 1
#define NRF53_ERRATA_47_ENABLE_WORKAROUND 1
#endif
#ifdef CONFIG_NRFX_TWIS
@@ -827,60 +409,6 @@
#ifdef CONFIG_NRFX_TWIS_LOG
#define NRFX_TWIS_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS0
#define NRFX_TWIS0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS1
#define NRFX_TWIS1_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS2
#define NRFX_TWIS2_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS3
#define NRFX_TWIS3_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS20
#define NRFX_TWIS20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS21
#define NRFX_TWIS21_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS22
#define NRFX_TWIS22_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS23
#define NRFX_TWIS23_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS24
#define NRFX_TWIS24_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS30
#define NRFX_TWIS30_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS130
#define NRFX_TWIS130_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS131
#define NRFX_TWIS131_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS132
#define NRFX_TWIS132_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS133
#define NRFX_TWIS133_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS134
#define NRFX_TWIS134_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS135
#define NRFX_TWIS135_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS136
#define NRFX_TWIS136_ENABLED 1
#endif
#ifdef CONFIG_NRFX_TWIS137
#define NRFX_TWIS137_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UART
#define NRFX_UART_ENABLED 1
@@ -898,66 +426,6 @@
#ifdef CONFIG_NRFX_UARTE_LOG
#define NRFX_UARTE_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE0
#define NRFX_UARTE0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE1
#define NRFX_UARTE1_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE2
#define NRFX_UARTE2_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE3
#define NRFX_UARTE3_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE00
#define NRFX_UARTE00_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE20
#define NRFX_UARTE20_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE21
#define NRFX_UARTE21_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE22
#define NRFX_UARTE22_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE23
#define NRFX_UARTE23_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE24
#define NRFX_UARTE24_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE30
#define NRFX_UARTE30_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE120
#define NRFX_UARTE120_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE130
#define NRFX_UARTE130_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE131
#define NRFX_UARTE131_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE132
#define NRFX_UARTE132_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE133
#define NRFX_UARTE133_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE134
#define NRFX_UARTE134_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE135
#define NRFX_UARTE135_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE136
#define NRFX_UARTE136_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE137
#define NRFX_UARTE137_ENABLED 1
#endif
#ifdef CONFIG_NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG
#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 1
#endif
@@ -987,50 +455,13 @@
#ifdef CONFIG_NRFX_WDT_LOG
#define NRFX_WDT_CONFIG_LOG_ENABLED 1
#endif
#ifdef CONFIG_NRFX_WDT0
#define NRFX_WDT0_ENABLED 1
#endif
#ifdef CONFIG_NRFX_WDT1
#define NRFX_WDT1_ENABLED 1
#endif
#ifdef CONFIG_NRFX_WDT30
#define NRFX_WDT30_ENABLED 1
#endif
#ifdef CONFIG_NRFX_WDT31
#define NRFX_WDT31_ENABLED 1
#endif
#ifdef CONFIG_NRFX_WDT010
#define NRFX_WDT010_ENABLED 1
#endif
#ifdef CONFIG_NRFX_WDT011
#define NRFX_WDT011_ENABLED 1
#endif
#ifdef CONFIG_NRFX_WDT130
#define NRFX_WDT130_ENABLED 1
#endif
#ifdef CONFIG_NRFX_WDT131
#define NRFX_WDT131_ENABLED 1
#endif
#ifdef CONFIG_NRFX_WDT132
#define NRFX_WDT132_ENABLED 1
#endif
#ifdef CONFIG_NRF52_ANOMALY_109_WORKAROUND
#define NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1
#define NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1
#define NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1
#define NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1
#define NRF52_ERRATA_109_ENABLE_WORKAROUND 1
#define NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE \
CONFIG_NRF52_ANOMALY_109_WORKAROUND_EGU_INSTANCE
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_dppic_global) || \
DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_dppic_local)
#ifndef NRFX_DPPI_ENABLED
#define NRFX_DPPI_ENABLED 1
#endif
#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_dppic_global) || ... */
/* If local or global DPPIC peripherals are used, provide the following macro
* definitions required by the interconnect/ipct layer:
* - NRFX_IPCTx_PUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num)

2
modules/hal_nordic/nrfx/nrfx_log.h
View File

@@ -126,7 +126,7 @@ LOG_MODULE_REGISTER(NRFX_MODULE_PREFIX, NRFX_MODULE_LOG_LEVEL);
* @return String containing the textual representation of the error code.
*/
#define NRFX_LOG_ERROR_STRING_GET(error_code) nrfx_error_string_get(error_code)
extern char const *nrfx_error_string_get(nrfx_err_t code);
extern char const *nrfx_error_string_get(int code);
/** @} */

93
modules/nrf_wifi/bus/qspi_if.c
View File

@@ -18,7 +18,6 @@
#include <zephyr/drivers/wifi/nrf_wifi/bus/qspi_if.h>
#include <soc.h>
#include <nrf_erratas.h>
#include <nrfx_qspi.h>
#include <hal/nrf_clock.h>
#include <hal/nrf_gpio.h>
@@ -296,17 +295,17 @@ static inline int qspi_get_lines_read(uint8_t lines)
return ret;
}
nrfx_err_t _nrfx_qspi_read(void *p_rx_buffer, size_t rx_buffer_length, uint32_t src_address)
int _nrfx_qspi_read(void *p_rx_buffer, size_t rx_buffer_length, uint32_t src_address)
{
return nrfx_qspi_read(p_rx_buffer, rx_buffer_length, src_address);
}
nrfx_err_t _nrfx_qspi_write(void const *p_tx_buffer, size_t tx_buffer_length, uint32_t dst_address)
int _nrfx_qspi_write(void const *p_tx_buffer, size_t tx_buffer_length, uint32_t dst_address)
{
return nrfx_qspi_write(p_tx_buffer, tx_buffer_length, dst_address);
}
nrfx_err_t _nrfx_qspi_init(nrfx_qspi_config_t const *p_config, nrfx_qspi_handler_t handler,
int _nrfx_qspi_init(nrfx_qspi_config_t const *p_config, nrfx_qspi_handler_t handler,
void *p_context)
{
NRF_QSPI_Type *p_reg = NRF_QSPI;
@@ -319,7 +318,7 @@ nrfx_err_t _nrfx_qspi_init(nrfx_qspi_config_t const *p_config, nrfx_qspi_handler
/* LOG_DBG("%04x : IFTIMING", p_reg->IFTIMING & qspi_cfg->RDC4IO); */
/* ACTIVATE task fails for slave bitfile so ignore it */
return NRFX_SUCCESS;
return 0;
}
@@ -339,32 +338,6 @@ NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(QSPI_IF_BUS_NODE);
IF_ENABLED(CONFIG_PINCTRL, (PINCTRL_DT_DEFINE(QSPI_IF_BUS_NODE)));
/**
* @brief Converts NRFX return codes to the zephyr ones
*/
static inline int qspi_get_zephyr_ret_code(nrfx_err_t res)
{
switch (res) {
case NRFX_SUCCESS:
return 0;
case NRFX_ERROR_INVALID_PARAM:
case NRFX_ERROR_INVALID_ADDR:
return -EINVAL;
case NRFX_ERROR_INVALID_STATE:
return -ECANCELED;
#if NRF53_ERRATA_159_ENABLE_WORKAROUND
case NRFX_ERROR_FORBIDDEN:
LOG_ERR("nRF5340 anomaly 159 conditions detected");
LOG_ERR("Set the CPU clock to 64 MHz before starting QSPI operation");
return -ECANCELED;
#endif
case NRFX_ERROR_BUSY:
case NRFX_ERROR_TIMEOUT:
default:
return -EBUSY;
}
}
static inline struct qspi_nor_data *get_dev_data(const struct device *dev)
{
return dev->data;
@@ -431,11 +404,11 @@ static inline void qspi_trans_unlock(const struct device *dev)
#endif /* CONFIG_MULTITHREADING */
}
static inline void qspi_wait_for_completion(const struct device *dev, nrfx_err_t res)
static inline void qspi_wait_for_completion(const struct device *dev, int res)
{
struct qspi_nor_data *dev_data = get_dev_data(dev);
if (res == NRFX_SUCCESS) {
if (res == 0) {
#ifdef CONFIG_MULTITHREADING
k_sem_take(&dev_data->sync, K_FOREVER);
#else /* CONFIG_MULTITHREADING */
@@ -469,7 +442,7 @@ static inline void _qspi_complete(struct qspi_nor_data *dev_data)
qspi_complete(dev_data);
}
static inline void _qspi_wait_for_completion(const struct device *dev, nrfx_err_t res)
static inline void _qspi_wait_for_completion(const struct device *dev, int res)
{
if (!qspi_cfg->easydma) {
return;
@@ -499,7 +472,6 @@ static bool qspi_initialized;
static int qspi_device_init(const struct device *dev)
{
struct qspi_nor_data *dev_data = get_dev_data(dev);
nrfx_err_t res;
int ret = 0;
if (!IS_ENABLED(CONFIG_NRF70_QSPI_LOW_POWER)) {
@@ -517,8 +489,7 @@ static int qspi_device_init(const struct device *dev)
#endif
if (!qspi_initialized) {
res = nrfx_qspi_init(&QSPIconfig, qspi_handler, dev_data);
ret = qspi_get_zephyr_ret_code(res);
ret = nrfx_qspi_init(&QSPIconfig, qspi_handler, dev_data);
NRF_QSPI->IFTIMING |= qspi_cfg->RDC4IO;
qspi_initialized = (ret == 0);
}
@@ -543,7 +514,7 @@ static void _qspi_device_uninit(const struct device *dev)
#endif
if (last) {
while (nrfx_qspi_mem_busy_check() != NRFX_SUCCESS) {
while (nrfx_qspi_mem_busy_check() != 0) {
if (IS_ENABLED(CONFIG_MULTITHREADING)) {
k_msleep(50);
} else {
@@ -632,7 +603,7 @@ static int qspi_send_cmd(const struct device *dev, const struct qspi_cmd *cmd, b
int res = nrfx_qspi_cinstr_xfer(&cinstr_cfg, tx_buf, rx_buf);
qspi_unlock(dev);
return qspi_get_zephyr_ret_code(res);
return res;
}
/* RDSR wrapper. Negative value is error. */
@@ -740,16 +711,13 @@ static int qspi_nrfx_configure(const struct device *dev)
k_busy_wait(BASE_CLOCK_SWITCH_DELAY_US);
#endif
nrfx_err_t res = _nrfx_qspi_init(&QSPIconfig, qspi_handler, dev_data);
int ret = _nrfx_qspi_init(&QSPIconfig, qspi_handler, dev_data);
#if defined(CONFIG_SOC_SERIES_NRF53X)
/* Restore the default /4 divider after the QSPI initialization. */
nrf_clock_hfclk192m_div_set(NRF_CLOCK, NRF_CLOCK_HFCLK_DIV_4);
k_busy_wait(BASE_CLOCK_SWITCH_DELAY_US);
#endif
int ret = qspi_get_zephyr_ret_code(res);
if (ret == 0) {
/* Set QE to match transfer mode. If not using quad
* it's OK to leave QE set, but doing so prevents use
@@ -806,7 +774,7 @@ static int qspi_nrfx_configure(const struct device *dev)
return ret;
}
static inline nrfx_err_t read_non_aligned(const struct device *dev, int addr, void *dest,
static inline int read_non_aligned(const struct device *dev, int addr, void *dest,
size_t size)
{
uint8_t __aligned(WORD_SIZE) buf[WORD_SIZE * 2];
@@ -833,7 +801,7 @@ static inline nrfx_err_t read_non_aligned(const struct device *dev, int addr, vo
flash_suffix = size - flash_prefix - flash_middle;
}
nrfx_err_t res = NRFX_SUCCESS;
int res = 0;
/* read from aligned flash to aligned memory */
if (flash_middle != 0) {
@@ -841,7 +809,7 @@ static inline nrfx_err_t read_non_aligned(const struct device *dev, int addr, vo
_qspi_wait_for_completion(dev, res);
if (res != NRFX_SUCCESS) {
if (res != 0) {
return res;
}
@@ -857,7 +825,7 @@ static inline nrfx_err_t read_non_aligned(const struct device *dev, int addr, vo
_qspi_wait_for_completion(dev, res);
if (res != NRFX_SUCCESS) {
if (res != 0) {
return res;
}
@@ -870,7 +838,7 @@ static inline nrfx_err_t read_non_aligned(const struct device *dev, int addr, vo
_qspi_wait_for_completion(dev, res);
if (res != NRFX_SUCCESS) {
if (res != 0) {
return res;
}
@@ -891,31 +859,28 @@ static int qspi_nor_read(const struct device *dev, int addr, void *dest, size_t
return 0;
}
int rc = qspi_device_init(dev);
int ret = qspi_device_init(dev);
if (rc != 0) {
if (ret != 0) {
goto out;
}
qspi_lock(dev);
nrfx_err_t res = read_non_aligned(dev, addr, dest, size);
ret = read_non_aligned(dev, addr, dest, size);
qspi_unlock(dev);
rc = qspi_get_zephyr_ret_code(res);
out:
qspi_device_uninit(dev);
return rc;
return ret;
}
/* addr aligned, sptr not null, slen less than 4 */
static inline nrfx_err_t write_sub_word(const struct device *dev, int addr, const void *sptr,
static inline int write_sub_word(const struct device *dev, int addr, const void *sptr,
size_t slen)
{
uint8_t __aligned(4) buf[4];
nrfx_err_t res;
int res;
/* read out the whole word so that unchanged data can be
* written back
@@ -923,7 +888,7 @@ static inline nrfx_err_t write_sub_word(const struct device *dev, int addr, cons
res = _nrfx_qspi_read(buf, sizeof(buf), addr);
_qspi_wait_for_completion(dev, res);
if (res == NRFX_SUCCESS) {
if (res == 0) {
memcpy(buf, sptr, slen);
res = _nrfx_qspi_write(buf, sizeof(buf), addr);
_qspi_wait_for_completion(dev, res);
@@ -948,11 +913,9 @@ static int qspi_nor_write(const struct device *dev, int addr, const void *src, s
return -EINVAL;
}
nrfx_err_t res = NRFX_SUCCESS;
int res = qspi_device_init(dev);
int rc = qspi_device_init(dev);
if (rc != 0) {
if (res != 0) {
goto out;
}
@@ -970,11 +933,9 @@ static int qspi_nor_write(const struct device *dev, int addr, const void *src, s
qspi_unlock(dev);
qspi_trans_unlock(dev);
rc = qspi_get_zephyr_ret_code(res);
out:
qspi_device_uninit(dev);
return rc;
return res;
}
/**
@@ -1460,7 +1421,7 @@ int qspi_enable_encryption(uint8_t *key)
memcpy(qspi_cfg->p_cfg.key, key, 16);
err = nrfx_qspi_dma_encrypt(&qspi_cfg->p_cfg);
if (err != NRFX_SUCCESS) {
if (err != 0) {
LOG_ERR("nrfx_qspi_dma_encrypt failed: %d", err);
return -EIO;
}

2
modules/trusted-firmware-m/nordic/include/tfm_read_ranges.h
View File

@@ -9,7 +9,7 @@
#include <tfm_ioctl_core_api.h>
#include <nrf.h>
#include <nrfx.h>
#ifdef NRF_FICR_S_BASE

59
samples/boards/nordic/nrfx/src/main.c
View File

@@ -36,33 +36,33 @@ int main(void)
{
LOG_INF("nrfx_gpiote sample on %s", CONFIG_BOARD);
nrfx_err_t err;
int rv;
uint8_t in_channel, out_channel;
uint8_t ppi_channel;
const nrfx_gpiote_t gpiote = NRFX_GPIOTE_INSTANCE(GPIOTE_INST);
nrfx_gppi_handle_t ppi_handle;
static nrfx_gpiote_t gpiote = NRFX_GPIOTE_INSTANCE(NRF_GPIOTE_INST_GET(GPIOTE_INST));
/* Connect GPIOTE instance IRQ to irq handler */
IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority), nrfx_isr,
NRFX_CONCAT(nrfx_gpiote_, GPIOTE_INST, _irq_handler), 0);
IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority), nrfx_gpiote_irq_handler,
&gpiote, 0);
/* Initialize GPIOTE (the interrupt priority passed as the parameter
* here is ignored, see nrfx_glue.h).
*/
err = nrfx_gpiote_init(&gpiote, 0);
if (err != NRFX_SUCCESS) {
LOG_ERR("nrfx_gpiote_init error: 0x%08X", err);
rv = nrfx_gpiote_init(&gpiote, 0);
if (rv != 0) {
LOG_ERR("nrfx_gpiote_init error: %d", rv);
return 0;
}
err = nrfx_gpiote_channel_alloc(&gpiote, &in_channel);
if (err != NRFX_SUCCESS) {
LOG_ERR("Failed to allocate in_channel, error: 0x%08X", err);
rv = nrfx_gpiote_channel_alloc(&gpiote, &in_channel);
if (rv != 0) {
LOG_ERR("Failed to allocate in_channel, error: %d", rv);
return 0;
}
err = nrfx_gpiote_channel_alloc(&gpiote, &out_channel);
if (err != NRFX_SUCCESS) {
LOG_ERR("Failed to allocate out_channel, error: 0x%08X", err);
rv = nrfx_gpiote_channel_alloc(&gpiote, &out_channel);
if (rv != 0) {
LOG_ERR("Failed to allocate out_channel, error: %d", rv);
return 0;
}
@@ -83,10 +83,10 @@ int main(void)
.p_handler_config = &handler_config
};
err = nrfx_gpiote_input_configure(&gpiote, INPUT_PIN, &input_config);
rv = nrfx_gpiote_input_configure(&gpiote, INPUT_PIN, &input_config);
if (err != NRFX_SUCCESS) {
LOG_ERR("nrfx_gpiote_input_configure error: 0x%08X", err);
if (rv != 0) {
LOG_ERR("nrfx_gpiote_input_configure error: %d", rv);
return 0;
}
@@ -103,11 +103,11 @@ int main(void)
.polarity = NRF_GPIOTE_POLARITY_TOGGLE,
.init_val = 1,
};
err = nrfx_gpiote_output_configure(&gpiote, OUTPUT_PIN,
rv = nrfx_gpiote_output_configure(&gpiote, OUTPUT_PIN,
&output_config,
&task_config);
if (err != NRFX_SUCCESS) {
LOG_ERR("nrfx_gpiote_output_configure error: 0x%08X", err);
if (rv != 0) {
LOG_ERR("nrfx_gpiote_output_configure error: %d", rv);
return 0;
}
@@ -116,23 +116,20 @@ int main(void)
LOG_INF("nrfx_gpiote initialized");
/* Allocate a (D)PPI channel. */
err = nrfx_gppi_channel_alloc(&ppi_channel);
if (err != NRFX_SUCCESS) {
LOG_ERR("nrfx_gppi_channel_alloc error: 0x%08X", err);
return 0;
}
/* Configure endpoints of the channel so that the input pin event is
* connected with the output pin OUT task. This means that each time
* the button is pressed, the LED pin will be toggled.
*/
nrfx_gppi_channel_endpoints_setup(ppi_channel,
nrfx_gpiote_in_event_address_get(&gpiote, INPUT_PIN),
nrfx_gpiote_out_task_address_get(&gpiote, OUTPUT_PIN));
rv = nrfx_gppi_conn_alloc(nrfx_gpiote_in_event_address_get(&gpiote, INPUT_PIN),
nrfx_gpiote_out_task_address_get(&gpiote, OUTPUT_PIN),
&ppi_handle);
if (rv < 0) {
LOG_ERR("nrfx_gppi_conn_alloc error: %d", rv);
return 0;
}
/* Enable the channel. */
nrfx_gppi_channels_enable(BIT(ppi_channel));
nrfx_gppi_conn_enable(ppi_handle);
LOG_INF("(D)PPI configured, leaving main()");
return 0;

4
samples/boards/nordic/nrfx_prs/prj.conf
View File

@@ -1,8 +1,8 @@
# This is needed for using SPIM2 and UARTE2 via nrfx drivers and for switching
# between those peripherals, as they share the same ID and hence cannot be used
# simultaneously.
CONFIG_NRFX_SPIM2=y
CONFIG_NRFX_UARTE2=y
CONFIG_NRFX_SPIM=y
CONFIG_NRFX_UARTE=y
CONFIG_NRFX_PRS_BOX_2=y
# This is needed for using another SPIM instance via the Zephyr SPI driver.

41
samples/boards/nordic/nrfx_prs/src/main.c
View File

@@ -28,12 +28,13 @@
*/
#define SPI_DEV_NODE DT_NODELABEL(spi1)
static nrfx_spim_t spim = NRFX_SPIM_INSTANCE(2);
static nrfx_uarte_t uarte = NRFX_UARTE_INSTANCE(2);
static nrfx_spim_t spim = NRFX_SPIM_INSTANCE(NRF_SPIM2);
static nrfx_uarte_t uarte = NRFX_UARTE_INSTANCE(NRF_UARTE2);
static bool spim_initialized;
static bool uarte_initialized;
static volatile size_t received;
static K_SEM_DEFINE(transfer_finished, 0, 1);
void nrfx_prs_box_2_irq_handler(void);
static enum {
PERFORM_TRANSFER,
@@ -111,7 +112,7 @@ static bool init_buttons(void)
return true;
}
static void spim_handler(const nrfx_spim_evt_t *p_event, void *p_context)
static void spim_handler(const nrfx_spim_event_t *p_event, void *p_context)
{
if (p_event->type == NRFX_SPIM_EVENT_DONE) {
k_sem_give(&transfer_finished);
@@ -121,7 +122,6 @@ static void spim_handler(const nrfx_spim_evt_t *p_event, void *p_context)
static bool switch_to_spim(void)
{
int ret;
nrfx_err_t err;
uint32_t sck_pin;
PINCTRL_DT_DEFINE(SPIM_NODE);
@@ -162,9 +162,9 @@ static bool switch_to_spim(void)
nrfy_gpio_pin_write(sck_pin, (spim_config.mode <= NRF_SPIM_MODE_1) ? 0 : 1);
}
err = nrfx_spim_init(&spim, &spim_config, spim_handler, NULL);
if (err != NRFX_SUCCESS) {
printk("nrfx_spim_init() failed: 0x%08x\n", err);
ret = nrfx_spim_init(&spim, &spim_config, spim_handler, NULL);
if (ret != 0) {
printk("nrfx_spim_init() failed: %d", ret);
return false;
}
@@ -176,7 +176,7 @@ static bool switch_to_spim(void)
static bool spim_transfer(const uint8_t *tx_data, size_t tx_data_len,
uint8_t *rx_buf, size_t rx_buf_size)
{
nrfx_err_t err;
int err;
nrfx_spim_xfer_desc_t xfer_desc = {
.p_tx_buffer = tx_data,
.tx_length = tx_data_len,
@@ -185,8 +185,8 @@ static bool spim_transfer(const uint8_t *tx_data, size_t tx_data_len,
};
err = nrfx_spim_xfer(&spim, &xfer_desc, 0);
if (err != NRFX_SUCCESS) {
printk("nrfx_spim_xfer() failed: 0x%08x\n", err);
if (err != 0) {
printk("nrfx_spim_xfer() failed: %d\n", err);
return false;
}
@@ -213,7 +213,6 @@ static void uarte_handler(const nrfx_uarte_event_t *p_event, void *p_context)
static bool switch_to_uarte(void)
{
int ret;
nrfx_err_t err;
PINCTRL_DT_DEFINE(UARTE_NODE);
@@ -244,9 +243,9 @@ static bool switch_to_uarte(void)
return ret;
}
err = nrfx_uarte_init(&uarte, &uarte_config, uarte_handler);
if (err != NRFX_SUCCESS) {
printk("nrfx_uarte_init() failed: 0x%08x\n", err);
ret = nrfx_uarte_init(&uarte, &uarte_config, uarte_handler);
if (ret != 0) {
printk("nrfx_uarte_init() failed: %d\n", ret);
return false;
}
@@ -258,23 +257,23 @@ static bool switch_to_uarte(void)
static bool uarte_transfer(const uint8_t *tx_data, size_t tx_data_len,
uint8_t *rx_buf, size_t rx_buf_size)
{
nrfx_err_t err;
int err;
err = nrfx_uarte_rx_buffer_set(&uarte, rx_buf, rx_buf_size);
if (err != NRFX_SUCCESS) {
printk("nrfx_uarte_rx_buffer_set() failed: 0x%08x\n", err);
if (err != 0) {
printk("nrfx_uarte_rx_buffer_set() failed: %d\n", err);
return false;
}
err = nrfx_uarte_rx_enable(&uarte, NRFX_UARTE_RX_ENABLE_STOP_ON_END);
if (err != NRFX_SUCCESS) {
printk("nrfx_uarte_rx_enable() failed: 0x%08x\n", err);
if (err != 0) {
printk("nrfx_uarte_rx_enable() failed: %d\n", err);
return false;
}
err = nrfx_uarte_tx(&uarte, tx_data, tx_data_len, 0);
if (err != NRFX_SUCCESS) {
printk("nrfx_uarte_tx() failed: 0x%08x\n", err);
if (err != 0) {
printk("nrfx_uarte_tx() failed: %d\n", err);
return false;
}

3
samples/drivers/led/led_strip/boards/nrf52dk_nrf52832.conf
View File

@@ -1,3 +0,0 @@
# This driver only uses spi_write() with the SPIM instance it allocates,
# so PAN 58 doesn't matter, because the RX length is always 0.
CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58=y

1
samples/net/zperf/src/nrf5340_cpu_boost.c
View File

@@ -22,7 +22,6 @@ static int nrf53_cpu_boost(void)
/* For optimal performance, the CPU frequency should be set to 128 MHz */
err = nrfx_clock_divider_set(NRF_CLOCK_DOMAIN_HFCLK, NRF_CLOCK_HFCLK_DIV_1);
err -= NRFX_ERROR_BASE_NUM;
if (err != 0) {
LOG_WRN("Failed to set 128 MHz: %d", err);
}

2
samples/subsys/usb/uac2_explicit_feedback/boards/nrf5340dk_nrf5340_cpuapp.conf
View File

@@ -1,2 +1,2 @@
#Enable timer for asynchronous feedback
CONFIG_NRFX_TIMER2=y
CONFIG_NRFX_TIMER=y

2
samples/subsys/usb/uac2_explicit_feedback/boards/nrf54h20dk_nrf54h20_cpuapp.conf
View File

@@ -1,4 +1,4 @@
# Enable timer for asynchronous feedback
CONFIG_NRFX_GPPI=y
CONFIG_NRFX_TIMER131=y
CONFIG_NRFX_TIMER=y
CONFIG_NRFX_GPIOTE130=y

91
samples/subsys/usb/uac2_explicit_feedback/src/feedback_nrf.c
View File

@@ -8,8 +8,8 @@
#include <zephyr/logging/log.h>
#include "feedback.h"
#include <nrfx_dppi.h>
#include <nrfx_gpiote.h>
#include <gpiote_nrfx.h>
#include <nrfx_timer.h>
#include <hal/nrf_gpio.h>
#include <helpers/nrfx_gppi.h>
@@ -60,11 +60,10 @@ static inline void feedback_target_init(void)
#error "Unsupported target"
#endif
static const nrfx_gpiote_t gpiote =
NRFX_GPIOTE_INSTANCE(FEEDBACK_GPIOTE_INSTANCE_NUMBER);
#define FEEDBACK_GPIOTE_NODE DT_NODELABEL(UTIL_CAT(gpiote, FEEDBACK_GPIOTE_INSTANCE_NUMBER))
static const nrfx_timer_t feedback_timer_instance =
NRFX_TIMER_INSTANCE(FEEDBACK_TIMER_INSTANCE_NUMBER);
static nrfx_timer_t feedback_timer_instance =
NRFX_TIMER_INSTANCE(NRF_TIMER_INST_GET(FEEDBACK_TIMER_INSTANCE_NUMBER));
/* See 5.12.4.2 Feedback in Universal Serial Bus Specification Revision 2.0 for
* more information about the feedback. There is a direct implementation of the
@@ -118,11 +117,11 @@ static struct feedback_ctx {
};
} fb_ctx;
static nrfx_err_t feedback_edge_counter_setup(void)
static int feedback_edge_counter_setup(void)
{
nrfx_err_t err;
uint8_t feedback_gpiote_channel;
uint8_t feedback_gppi_channel;
nrfx_gppi_handle_t feedback_gppi_handle;
nrfx_gpiote_t *gpiote = &GPIOTE_NRFX_INST_BY_NODE(FEEDBACK_GPIOTE_NODE);
nrfx_gpiote_trigger_config_t trigger_config = {
.trigger = NRFX_GPIOTE_TRIGGER_TOGGLE,
.p_in_channel = &feedback_gpiote_channel,
@@ -132,14 +131,17 @@ static nrfx_err_t feedback_edge_counter_setup(void)
.p_pull_config = &pull,
.p_trigger_config = &trigger_config,
};
int err;
uint32_t eep = nrfx_gpiote_in_event_address_get(gpiote, FEEDBACK_PIN);
uint32_t tep = nrfx_timer_task_address_get(&feedback_timer_instance, NRF_TIMER_TASK_COUNT);
err = nrfx_gpiote_channel_alloc(&gpiote, &feedback_gpiote_channel);
if (err != NRFX_SUCCESS) {
err = nrfx_gpiote_channel_alloc(gpiote, &feedback_gpiote_channel);
if (err != 0) {
return err;
}
nrfx_gpiote_input_configure(&gpiote, FEEDBACK_PIN, &input_pin_config);
nrfx_gpiote_trigger_enable(&gpiote, FEEDBACK_PIN, false);
nrfx_gpiote_input_configure(gpiote, FEEDBACK_PIN, &input_pin_config);
nrfx_gpiote_trigger_enable(gpiote, FEEDBACK_PIN, false);
/* Configure TIMER in COUNTER mode */
const nrfx_timer_config_t cfg = {
@@ -151,30 +153,26 @@ static nrfx_err_t feedback_edge_counter_setup(void)
};
err = nrfx_timer_init(&feedback_timer_instance, &cfg, NULL);
if (err != NRFX_SUCCESS) {
if (err != 0) {
LOG_ERR("nrfx timer init error (sample clk feedback) - Return value: %d", err);
return err;
}
/* Subscribe TIMER COUNT task to GPIOTE IN event */
err = nrfx_gppi_channel_alloc(&feedback_gppi_channel);
if (err != NRFX_SUCCESS) {
LOG_ERR("gppi_channel_alloc failed with: %d\n", err);
err = nrfx_gppi_conn_alloc(eep, tep, &feedback_gppi_handle);
if (err < 0) {
LOG_ERR("gppi_conn_alloc failed with: %d\n", err);
return err;
}
nrfx_gppi_channel_endpoints_setup(feedback_gppi_channel,
nrfx_gpiote_in_event_address_get(&gpiote, FEEDBACK_PIN),
nrfx_timer_task_address_get(&feedback_timer_instance, NRF_TIMER_TASK_COUNT));
nrfx_gppi_conn_enable(feedback_gppi_handle);
nrfx_gppi_channels_enable(BIT(feedback_gppi_channel));
return NRFX_SUCCESS;
return 0;
}
static nrfx_err_t feedback_relative_timer_setup(void)
static int feedback_relative_timer_setup(void)
{
nrfx_err_t err;
int err;
const nrfx_timer_config_t cfg = {
.frequency = NRFX_MHZ_TO_HZ(16UL),
.mode = NRF_TIMER_MODE_TIMER,
@@ -184,7 +182,7 @@ static nrfx_err_t feedback_relative_timer_setup(void)
};
err = nrfx_timer_init(&feedback_timer_instance, &cfg, NULL);
if (err != NRFX_SUCCESS) {
if (err != 0) {
LOG_ERR("nrfx timer init error (relative timer) - Return value: %d", err);
}
@@ -193,9 +191,13 @@ static nrfx_err_t feedback_relative_timer_setup(void)
struct feedback_ctx *feedback_init(void)
{
nrfx_err_t err;
uint8_t usbd_sof_gppi_channel;
uint8_t i2s_framestart_gppi_channel;
nrfx_gppi_handle_t usbd_sof_gppi_handle;
nrfx_gppi_handle_t i2s_framestart_gppi_handle;
int err;
uint32_t tsk1 = nrfx_timer_capture_task_address_get(&feedback_timer_instance,
FEEDBACK_TIMER_USBD_SOF_CAPTURE);
uint32_t tsk2 = nrfx_timer_capture_task_address_get(&feedback_timer_instance,
FEEDBACK_TIMER_I2S_FRAMESTART_CAPTURE);
feedback_target_init();
@@ -207,40 +209,31 @@ struct feedback_ctx *feedback_init(void)
err = feedback_relative_timer_setup();
}
if (err != NRFX_SUCCESS) {
if (err != 0) {
return &fb_ctx;
}
/* Subscribe TIMER CAPTURE task to USBD SOF event */
err = nrfx_gppi_channel_alloc(&usbd_sof_gppi_channel);
if (err != NRFX_SUCCESS) {
LOG_ERR("gppi_channel_alloc failed with: %d\n", err);
err = nrfx_gppi_conn_alloc(USB_SOF_EVENT_ADDRESS, tsk1, &usbd_sof_gppi_handle);
if (err < 0) {
LOG_ERR("gppi_conn_alloc failed with: %d\n", err);
return &fb_ctx;
}
nrfx_gppi_channel_endpoints_setup(usbd_sof_gppi_channel,
USB_SOF_EVENT_ADDRESS,
nrfx_timer_capture_task_address_get(&feedback_timer_instance,
FEEDBACK_TIMER_USBD_SOF_CAPTURE));
nrfx_gppi_fork_endpoint_setup(usbd_sof_gppi_channel,
nrfx_timer_task_address_get(&feedback_timer_instance,
NRF_TIMER_TASK_CLEAR));
nrfx_gppi_ep_attach(nrfx_timer_task_address_get(&feedback_timer_instance,
NRF_TIMER_TASK_CLEAR),
usbd_sof_gppi_handle);
nrfx_gppi_channels_enable(BIT(usbd_sof_gppi_channel));
nrfx_gppi_conn_enable(usbd_sof_gppi_handle);
/* Subscribe TIMER CAPTURE task to I2S FRAMESTART event */
err = nrfx_gppi_channel_alloc(&i2s_framestart_gppi_channel);
if (err != NRFX_SUCCESS) {
LOG_ERR("gppi_channel_alloc failed with: %d\n", err);
err = nrfx_gppi_conn_alloc(I2S_FRAMESTART_EVENT_ADDRESS, tsk2, &i2s_framestart_gppi_handle);
if (err < 0) {
LOG_ERR("gppi_conn_alloc failed with: %d\n", err);
return &fb_ctx;
}
nrfx_gppi_channel_endpoints_setup(i2s_framestart_gppi_channel,
I2S_FRAMESTART_EVENT_ADDRESS,
nrfx_timer_capture_task_address_get(&feedback_timer_instance,
FEEDBACK_TIMER_I2S_FRAMESTART_CAPTURE));
nrfx_gppi_channels_enable(BIT(i2s_framestart_gppi_channel));
nrfx_gppi_conn_enable(i2s_framestart_gppi_handle);
/* Enable feedback timer */
nrfx_timer_enable(&feedback_timer_instance);

2
samples/subsys/usb/uac2_implicit_feedback/boards/nrf5340dk_nrf5340_cpuapp.conf
View File

@@ -1,2 +1,2 @@
#Enable timer for asynchronous feedback
CONFIG_NRFX_TIMER2=y
CONFIG_NRFX_TIMER=y

2
samples/subsys/usb/uac2_implicit_feedback/boards/nrf54h20dk_nrf54h20_cpuapp.conf
View File

@@ -1,3 +1,3 @@
# Enable timer for asynchronous feedback
CONFIG_NRFX_GPPI=y
CONFIG_NRFX_TIMER131=y
CONFIG_NRFX_TIMER=y

47
samples/subsys/usb/uac2_implicit_feedback/src/feedback_nrf.c
View File

@@ -7,8 +7,6 @@
#include <stdlib.h>
#include <zephyr/logging/log.h>
#include "feedback.h"
#include <nrfx_dppi.h>
#include <nrfx_timer.h>
#include <helpers/nrfx_gppi.h>
@@ -51,8 +49,8 @@ static inline void feedback_target_init(void)
#error "Unsupported target"
#endif
static const nrfx_timer_t feedback_timer_instance =
NRFX_TIMER_INSTANCE(FEEDBACK_TIMER_INSTANCE_NUMBER);
static nrfx_timer_t feedback_timer_instance =
NRFX_TIMER_INSTANCE(NRF_TIMER_INST_GET(FEEDBACK_TIMER_INSTANCE_NUMBER));
/* While it might be possible to determine I2S FRAMESTART to USB SOF offset
* entirely in software, the I2S API lacks appropriate timestamping. Therefore
@@ -78,9 +76,9 @@ static struct feedback_ctx {
struct feedback_ctx *feedback_init(void)
{
nrfx_err_t err;
uint8_t usbd_sof_gppi_channel;
uint8_t i2s_framestart_gppi_channel;
int err;
nrfx_gppi_handle_t usbd_sof_gppi_handle;
nrfx_gppi_handle_t i2s_framestart_gppi_handle;
const nrfx_timer_config_t cfg = {
.frequency = NRFX_MHZ_TO_HZ(16UL),
.mode = NRF_TIMER_MODE_TIMER,
@@ -88,47 +86,40 @@ struct feedback_ctx *feedback_init(void)
.interrupt_priority = NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY,
.p_context = NULL,
};
uint32_t tsk1 = nrfx_timer_capture_task_address_get(&feedback_timer_instance,
FEEDBACK_TIMER_USBD_SOF_CAPTURE);
uint32_t tsk2 = nrfx_timer_task_address_get(&feedback_timer_instance, NRF_TIMER_TASK_CLEAR);
uint32_t tsk3 = nrfx_timer_capture_task_address_get(&feedback_timer_instance,
FEEDBACK_TIMER_I2S_FRAMESTART_CAPTURE);
feedback_target_init();
feedback_reset_ctx(&fb_ctx);
err = nrfx_timer_init(&feedback_timer_instance, &cfg, NULL);
if (err != NRFX_SUCCESS) {
if (err != 0) {
LOG_ERR("nrfx timer init error - Return value: %d", err);
return &fb_ctx;
}
/* Subscribe TIMER CAPTURE task to USBD SOF event */
err = nrfx_gppi_channel_alloc(&usbd_sof_gppi_channel);
if (err != NRFX_SUCCESS) {
err = nrfx_gppi_conn_alloc(USB_SOF_EVENT_ADDRESS, tsk1, &usbd_sof_gppi_handle);
if (err < 0) {
LOG_ERR("gppi_channel_alloc failed with: %d\n", err);
return &fb_ctx;
}
nrfx_gppi_channel_endpoints_setup(usbd_sof_gppi_channel,
USB_SOF_EVENT_ADDRESS,
nrfx_timer_capture_task_address_get(&feedback_timer_instance,
FEEDBACK_TIMER_USBD_SOF_CAPTURE));
nrfx_gppi_fork_endpoint_setup(usbd_sof_gppi_channel,
nrfx_timer_task_address_get(&feedback_timer_instance,
NRF_TIMER_TASK_CLEAR));
nrfx_gppi_channels_enable(BIT(usbd_sof_gppi_channel));
nrfx_gppi_ep_attach(tsk2, usbd_sof_gppi_handle);
nrfx_gppi_conn_enable(usbd_sof_gppi_handle);
/* Subscribe TIMER CAPTURE task to I2S FRAMESTART event */
err = nrfx_gppi_channel_alloc(&i2s_framestart_gppi_channel);
if (err != NRFX_SUCCESS) {
LOG_ERR("gppi_channel_alloc failed with: %d\n", err);
err = nrfx_gppi_conn_alloc(I2S_FRAMESTART_EVENT_ADDRESS, tsk3, &i2s_framestart_gppi_handle);
if (err < 0) {
LOG_ERR("gppi_conn_alloc failed with: %d\n", err);
return &fb_ctx;
}
nrfx_gppi_channel_endpoints_setup(i2s_framestart_gppi_channel,
I2S_FRAMESTART_EVENT_ADDRESS,
nrfx_timer_capture_task_address_get(&feedback_timer_instance,
FEEDBACK_TIMER_I2S_FRAMESTART_CAPTURE));
nrfx_gppi_channels_enable(BIT(i2s_framestart_gppi_channel));
nrfx_gppi_conn_enable(i2s_framestart_gppi_handle);
/* Enable feedback timer */
nrfx_timer_enable(&feedback_timer_instance);

1
scripts/ci/check_compliance.py
View File

@@ -1595,6 +1595,7 @@ flagged.
"SHIFT",
"SINGLE_APPLICATION_SLOT", # Used in sysbuild for MCUboot configuration
"SINGLE_APPLICATION_SLOT_RAM_LOAD", # Used in sysbuild for MCUboot configuration
"SOC_NORDIC_BSP_PATH_OVERRIDE", # Used in modules/hal_nordic/nrfx/CMakeLists.txt
"SOC_SDKNG_UNSUPPORTED", # Used in modules/hal_nxp/mcux/CMakeLists.txt
"SOC_SERIES_", # Used as regex in scripts/utils/board_v1_to_v2.py
"SOC_WATCH", # Issue 13749

5
soc/nordic/CMakeLists.txt
View File

@@ -45,6 +45,9 @@ if(CONFIG_BUILD_WITH_TFM)
)
endif()
add_subdirectory(${SOC_SERIES})
if(CONFIG_SOC_NORDIC_BSP_NAME STREQUAL "stable")
add_subdirectory(${SOC_SERIES})
endif()
add_subdirectory(common)
add_subdirectory_ifdef(CONFIG_NRF_IRONSIDE ironside)

8
soc/nordic/Kconfig
View File

@@ -48,6 +48,14 @@ config SOC_FAMILY_NORDIC_NRF
select SOC_RESET_HOOK
select CMSIS_CORE_HAS_SYSTEM_CORE_CLOCK if ARM
if SOC_COMPATIBLE_NRF
config SOC_NORDIC_BSP_NAME
string
default "stable"
endif # SOC_COMPATIBLE_NRF
if SOC_FAMILY_NORDIC_NRF
rsource "common/Kconfig.peripherals"

5
soc/nordic/common/CMakeLists.txt
View File

@@ -31,6 +31,10 @@ if(CONFIG_HAS_NORDIC_DMM)
zephyr_library_sources(dmm.c)
endif()
if(CONFIG_NRFX_GPPI AND NOT CONFIG_NRFX_GPPI_V1)
zephyr_library_sources(gppi_init.c)
endif()
if(CONFIG_TFM_PARTITION_PLATFORM)
zephyr_library_sources(soc_secure.c)
zephyr_library_include_directories(
@@ -41,3 +45,4 @@ endif()
zephyr_library_sources_ifdef(CONFIG_NRF_SYS_EVENT nrf_sys_event.c)
zephyr_library_sources_ifdef(CONFIG_SOC_NRF_FORCE_CONSTLAT nrf_constlat.c)
zephyr_library_sources_ifdef(CONFIG_MRAM_LATENCY mram_latency.c)
zephyr_library_sources(gpiote_nrfx.c)

339
soc/nordic/common/Kconfig.peripherals
View File

@@ -96,12 +96,6 @@ config HAS_HW_NRF_GPIOTE131
config HAS_HW_NRF_GRTC
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GRTC))
config HAS_HW_NRF_I2S0
def_bool $(dt_nodelabel_enabled_with_compat,i2s0,$(DT_COMPAT_NORDIC_NRF_I2S))
config HAS_HW_NRF_I2S20
def_bool $(dt_nodelabel_enabled_with_compat,i2s20,$(DT_COMPAT_NORDIC_NRF_I2S))
config HAS_HW_NRF_KMU
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_KMU))
@@ -127,75 +121,12 @@ config HAS_HW_NRF_NVMC_PE
config HAS_HW_NRF_OSCILLATORS
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_OSCILLATORS))
config HAS_HW_NRF_PDM0
def_bool $(dt_nodelabel_enabled_with_compat,pdm0,$(DT_COMPAT_NORDIC_NRF_PDM))
config HAS_HW_NRF_PDM20
def_bool $(dt_nodelabel_enabled_with_compat,pdm20,$(DT_COMPAT_NORDIC_NRF_PDM))
config HAS_HW_NRF_PDM21
def_bool $(dt_nodelabel_enabled_with_compat,pdm21,$(DT_COMPAT_NORDIC_NRF_PDM))
config HAS_HW_NRF_POWER
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_POWER))
config HAS_HW_NRF_PPI
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_PPI))
config HAS_HW_NRF_PWM0
def_bool $(dt_nodelabel_enabled_with_compat,pwm0,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_PWM1
def_bool $(dt_nodelabel_enabled_with_compat,pwm1,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_PWM2
def_bool $(dt_nodelabel_enabled_with_compat,pwm2,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_PWM3
def_bool $(dt_nodelabel_enabled_with_compat,pwm3,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_PWM20
def_bool $(dt_nodelabel_enabled_with_compat,pwm20,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_PWM21
def_bool $(dt_nodelabel_enabled_with_compat,pwm21,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_PWM22
def_bool $(dt_nodelabel_enabled_with_compat,pwm22,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_PWM120
def_bool $(dt_nodelabel_enabled_with_compat,pwm120,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_PWM130
def_bool $(dt_nodelabel_enabled_with_compat,pwm130,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_PWM131
def_bool $(dt_nodelabel_enabled_with_compat,pwm131,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_PWM132
def_bool $(dt_nodelabel_enabled_with_compat,pwm132,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_PWM133
def_bool $(dt_nodelabel_enabled_with_compat,pwm133,$(DT_COMPAT_NORDIC_NRF_PWM))
config HAS_HW_NRF_QDEC0
def_bool $(dt_nodelabel_enabled_with_compat,qdec0,$(DT_COMPAT_NORDIC_NRF_QDEC))
config HAS_HW_NRF_QDEC1
def_bool $(dt_nodelabel_enabled_with_compat,qdec1,$(DT_COMPAT_NORDIC_NRF_QDEC))
config HAS_HW_NRF_QDEC20
def_bool $(dt_nodelabel_enabled_with_compat,qdec20,$(DT_COMPAT_NORDIC_NRF_QDEC))
config HAS_HW_NRF_QDEC21
def_bool $(dt_nodelabel_enabled_with_compat,qdec21,$(DT_COMPAT_NORDIC_NRF_QDEC))
config HAS_HW_NRF_QDEC130
def_bool $(dt_nodelabel_enabled_with_compat,qdec130,$(DT_COMPAT_NORDIC_NRF_QDEC))
config HAS_HW_NRF_QDEC131
def_bool $(dt_nodelabel_enabled_with_compat,qdec131,$(DT_COMPAT_NORDIC_NRF_QDEC))
config HAS_HW_NRF_QSPI
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_QSPI))
@@ -253,138 +184,6 @@ config HAS_HW_NRF_SPI1
config HAS_HW_NRF_SPI2
def_bool $(dt_nodelabel_enabled_with_compat,spi2,$(DT_COMPAT_NORDIC_NRF_SPI))
config HAS_HW_NRF_SPIM0
def_bool $(dt_nodelabel_enabled_with_compat,spi0,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM1
def_bool $(dt_nodelabel_enabled_with_compat,spi1,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM2
def_bool $(dt_nodelabel_enabled_with_compat,spi2,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM3
def_bool $(dt_nodelabel_enabled_with_compat,spi3,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM4
def_bool $(dt_nodelabel_enabled_with_compat,spi4,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM00
def_bool $(dt_nodelabel_enabled_with_compat,spi00,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM01
def_bool $(dt_nodelabel_enabled_with_compat,spi01,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM20
def_bool $(dt_nodelabel_enabled_with_compat,spi20,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM21
def_bool $(dt_nodelabel_enabled_with_compat,spi21,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM22
def_bool $(dt_nodelabel_enabled_with_compat,spi22,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM23
def_bool $(dt_nodelabel_enabled_with_compat,spi23,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM24
def_bool $(dt_nodelabel_enabled_with_compat,spi24,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM30
def_bool $(dt_nodelabel_enabled_with_compat,spi30,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM120
def_bool $(dt_nodelabel_enabled_with_compat,spi120,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM121
def_bool $(dt_nodelabel_enabled_with_compat,spi121,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM130
def_bool $(dt_nodelabel_enabled_with_compat,spi130,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM131
def_bool $(dt_nodelabel_enabled_with_compat,spi131,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM132
def_bool $(dt_nodelabel_enabled_with_compat,spi132,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM133
def_bool $(dt_nodelabel_enabled_with_compat,spi133,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM134
def_bool $(dt_nodelabel_enabled_with_compat,spi134,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM135
def_bool $(dt_nodelabel_enabled_with_compat,spi135,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM136
def_bool $(dt_nodelabel_enabled_with_compat,spi136,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIM137
def_bool $(dt_nodelabel_enabled_with_compat,spi137,$(DT_COMPAT_NORDIC_NRF_SPIM))
config HAS_HW_NRF_SPIS0
def_bool $(dt_nodelabel_enabled_with_compat,spi0,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS1
def_bool $(dt_nodelabel_enabled_with_compat,spi1,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS2
def_bool $(dt_nodelabel_enabled_with_compat,spi2,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS3
def_bool $(dt_nodelabel_enabled_with_compat,spi3,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS00
def_bool $(dt_nodelabel_enabled_with_compat,spi00,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS01
def_bool $(dt_nodelabel_enabled_with_compat,spi01,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS20
def_bool $(dt_nodelabel_enabled_with_compat,spi20,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS21
def_bool $(dt_nodelabel_enabled_with_compat,spi21,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS22
def_bool $(dt_nodelabel_enabled_with_compat,spi22,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS23
def_bool $(dt_nodelabel_enabled_with_compat,spi23,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS24
def_bool $(dt_nodelabel_enabled_with_compat,spi24,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS30
def_bool $(dt_nodelabel_enabled_with_compat,spi30,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS120
def_bool $(dt_nodelabel_enabled_with_compat,spis120,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS130
def_bool $(dt_nodelabel_enabled_with_compat,spi130,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS131
def_bool $(dt_nodelabel_enabled_with_compat,spi131,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS132
def_bool $(dt_nodelabel_enabled_with_compat,spi132,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS133
def_bool $(dt_nodelabel_enabled_with_compat,spi133,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS134
def_bool $(dt_nodelabel_enabled_with_compat,spi134,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS135
def_bool $(dt_nodelabel_enabled_with_compat,spi135,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS136
def_bool $(dt_nodelabel_enabled_with_compat,spi136,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPIS137
def_bool $(dt_nodelabel_enabled_with_compat,spi137,$(DT_COMPAT_NORDIC_NRF_SPIS))
config HAS_HW_NRF_SPU
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_SPU))
@@ -499,117 +298,6 @@ config HAS_HW_NRF_TWI0
config HAS_HW_NRF_TWI1
def_bool $(dt_nodelabel_enabled_with_compat,i2c1,$(DT_COMPAT_NORDIC_NRF_TWI))
config HAS_HW_NRF_TWIM0
def_bool $(dt_nodelabel_enabled_with_compat,i2c0,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM1
def_bool $(dt_nodelabel_enabled_with_compat,i2c1,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM2
def_bool $(dt_nodelabel_enabled_with_compat,i2c2,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM3
def_bool $(dt_nodelabel_enabled_with_compat,i2c3,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM20
def_bool $(dt_nodelabel_enabled_with_compat,i2c20,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM21
def_bool $(dt_nodelabel_enabled_with_compat,i2c21,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM22
def_bool $(dt_nodelabel_enabled_with_compat,i2c22,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM23
def_bool $(dt_nodelabel_enabled_with_compat,i2c23,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM24
def_bool $(dt_nodelabel_enabled_with_compat,i2c24,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM30
def_bool $(dt_nodelabel_enabled_with_compat,i2c30,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM120
def_bool $(dt_nodelabel_enabled_with_compat,i2c120,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM130
def_bool $(dt_nodelabel_enabled_with_compat,i2c130,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM131
def_bool $(dt_nodelabel_enabled_with_compat,i2c131,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM132
def_bool $(dt_nodelabel_enabled_with_compat,i2c132,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM133
def_bool $(dt_nodelabel_enabled_with_compat,i2c133,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM134
def_bool $(dt_nodelabel_enabled_with_compat,i2c134,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM135
def_bool $(dt_nodelabel_enabled_with_compat,i2c135,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM136
def_bool $(dt_nodelabel_enabled_with_compat,i2c136,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIM137
def_bool $(dt_nodelabel_enabled_with_compat,i2c137,$(DT_COMPAT_NORDIC_NRF_TWIM))
config HAS_HW_NRF_TWIS0
def_bool $(dt_nodelabel_enabled_with_compat,i2c0,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS1
def_bool $(dt_nodelabel_enabled_with_compat,i2c1,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS2
def_bool $(dt_nodelabel_enabled_with_compat,i2c2,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS3
def_bool $(dt_nodelabel_enabled_with_compat,i2c3,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS20
def_bool $(dt_nodelabel_enabled_with_compat,i2c20,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS21
def_bool $(dt_nodelabel_enabled_with_compat,i2c21,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS22
def_bool $(dt_nodelabel_enabled_with_compat,i2c22,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS23
def_bool $(dt_nodelabel_enabled_with_compat,i2c23,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS24
def_bool $(dt_nodelabel_enabled_with_compat,i2c24,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS30
def_bool $(dt_nodelabel_enabled_with_compat,i2c30,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS130
def_bool $(dt_nodelabel_enabled_with_compat,i2c130,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS131
def_bool $(dt_nodelabel_enabled_with_compat,i2c131,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS132
def_bool $(dt_nodelabel_enabled_with_compat,i2c132,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS133
def_bool $(dt_nodelabel_enabled_with_compat,i2c133,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS134
def_bool $(dt_nodelabel_enabled_with_compat,i2c134,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS135
def_bool $(dt_nodelabel_enabled_with_compat,i2c135,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS136
def_bool $(dt_nodelabel_enabled_with_compat,i2c136,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_TWIS137
def_bool $(dt_nodelabel_enabled_with_compat,i2c137,$(DT_COMPAT_NORDIC_NRF_TWIS))
config HAS_HW_NRF_UART0
def_bool $(dt_nodelabel_enabled_with_compat,uart0,$(DT_COMPAT_NORDIC_NRF_UART))
@@ -681,30 +369,3 @@ config HAS_HW_NRF_USBREG
config HAS_HW_NRF_VMC
def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_VMC))
config HAS_HW_NRF_WDT0
def_bool $(dt_nodelabel_enabled_with_compat,wdt0,$(DT_COMPAT_NORDIC_NRF_WDT))
config HAS_HW_NRF_WDT1
def_bool $(dt_nodelabel_enabled_with_compat,wdt1,$(DT_COMPAT_NORDIC_NRF_WDT))
config HAS_HW_NRF_WDT30
def_bool $(dt_nodelabel_enabled_with_compat,wdt30,$(DT_COMPAT_NORDIC_NRF_WDT))
config HAS_HW_NRF_WDT31
def_bool $(dt_nodelabel_enabled_with_compat,wdt31,$(DT_COMPAT_NORDIC_NRF_WDT))
config HAS_HW_NRF_WDT010
def_bool $(dt_nodelabel_enabled_with_compat,wdt010,$(DT_COMPAT_NORDIC_NRF_WDT))
config HAS_HW_NRF_WDT011
def_bool $(dt_nodelabel_enabled_with_compat,wdt011,$(DT_COMPAT_NORDIC_NRF_WDT))
config HAS_HW_NRF_WDT130
def_bool $(dt_nodelabel_enabled_with_compat,wdt130,$(DT_COMPAT_NORDIC_NRF_WDT))
config HAS_HW_NRF_WDT131
def_bool $(dt_nodelabel_enabled_with_compat,wdt131,$(DT_COMPAT_NORDIC_NRF_WDT))
config HAS_HW_NRF_WDT132
def_bool $(dt_nodelabel_enabled_with_compat,wdt132,$(DT_COMPAT_NORDIC_NRF_WDT))

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