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boards: arm: Create unified fvp_base_revc_2xaem board structure

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Create unified board configuration to replace verbose board naming
with shorter hierarchical structure. This board works with the new
unified fvp_aem SOC series and supports the v8a architecture variant.

This enables board targets like:
- fvp_base_revc_2xaem/v8a (basic ARMv8-A)
- fvp_base_revc_2xaem/v8a/smp (ARMv8-A SMP)
- fvp_base_revc_2xaem/v8a/smp/ns (ARMv8-A SMP non-secure)

This structure replaces the existing overly verbose board designations
with a cleaner, more maintainable organization and provides a foundation
for adding v9a variants.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre
2025-10-02 05:55:22 -04:00
committed by Anas Nashif
parent 934e61bb61
commit c01e0943c0
28 changed files with 105 additions and 72 deletions
Download Patch File Download Diff File Expand all files Collapse all files

0
boards/arm/fvp_base_revc_2xaemv8a/Kconfig → boards/arm/fvp_base_revc_2xaem/Kconfig
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4
boards/arm/fvp_base_revc_2xaemv8a/Kconfig.defconfig → boards/arm/fvp_base_revc_2xaem/Kconfig.defconfig
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@@ -1,9 +1,9 @@
# Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
if BOARD_FVP_BASE_REVC_2XAEMV8A
if BOARD_FVP_BASE_REVC_2XAEM
config BUILD_OUTPUT_BIN
default y
endif # BOARD_FVP_BASE_REVC_2XAEMV8A
endif # BOARD_FVP_BASE_REVC_2XAEM

2
boards/arm/fvp_base_revc_2xaemv8a/Kconfig.fvp_base_revc_2xaemv8a → boards/arm/fvp_base_revc_2xaem/Kconfig.fvp_base_revc_2xaem
View File

@@ -1,5 +1,5 @@
# Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
config BOARD_FVP_BASE_REVC_2XAEMV8A
config BOARD_FVP_BASE_REVC_2XAEM
select SOC_V8A

0
boards/arm/fvp_base_revc_2xaemv8a/board.cmake → boards/arm/fvp_base_revc_2xaem/board.cmake
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10
boards/arm/fvp_base_revc_2xaem/board.yml Normal file
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@@ -0,0 +1,10 @@
board:
name: fvp_base_revc_2xaem
full_name: BASE RevC 2xAEM (Architectural Envelope Model) Fixed Virtual Platform
vendor: arm
socs:
- name: v8a
variants:
- name: smp
variants:
- name: ns

58
boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst → boards/arm/fvp_base_revc_2xaem/doc/index.rst
View File

@@ -1,16 +1,16 @@
.. _fvp_base_revc_2xaemv8a:
.. zephyr:board:: fvp_base_revc_2xaem
ARM BASE RevC AEMv8A Fixed Virtual Platforms
############################################
Arm BASE RevC 2xAEM Fixed Virtual Platforms
###########################################
Overview
********
This board configuration will use ARM Fixed Virtual Platforms(FVP) to emulate
a generic Armv8-A 64-bit hardware platform.
This board configuration will use Arm Fixed Virtual Platforms(FVP) to emulate
a generic AEM (Architectural Envelope Model) hardware platform supporting both
ARMv8-A and ARMv9-A architectures.
This configuration provides support for a generic Armv8-A 64-bit CPU and
these devices:
This configuration provides support for generic AEM CPUs and these devices:
* GICv3 interrupt controller
* ARM architected (Generic) timer
@@ -38,6 +38,16 @@ The following hardware features are supported:
The kernel currently does not support other hardware features on this platform.
Board Variants
==============
The following board targets are available:
* ``fvp_base_revc_2xaem/v8a`` - ARMv8-A (64-bit)
* ``fvp_base_revc_2xaem/v8a/smp`` - ARMv8-A SMP (4 cores)
* ``fvp_base_revc_2xaem/v8a/smp/ns`` - ARMv8-A SMP Non-Secure
* ``fvp_base_revc_2xaem/v9a`` - ARMv9-A (64-bit) [Future]
Devices
========
@@ -72,24 +82,40 @@ Programming
===========
Use this configuration to build basic Zephyr applications and kernel tests in the
ARM FVP emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
Arm FVP emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: fvp_base_revc_2xaemv8a
:board: fvp_base_revc_2xaem/v8a
:goals: build
This will build an image with the synchronization sample app.
This will build an image with the synchronization sample app for ARMv8-A.
Then you can run it with ``west build -t run``.
For SMP variants:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: fvp_base_revc_2xaem/v8a/smp
:goals: build
For SMP Non-Secure variants with TF-A:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: fvp_base_revc_2xaem/v8a/smp/ns
:goals: build
Running Zephyr at EL1NS
***********************
In order to run Zephyr as EL1NS with ``CONFIG_ARMV8_A_NS``, you'll need a proper
Trusted Firmware loaded in the FVP model.
The ARM TF-A for FVP can be used to run Zephyr as preloaded BL33 payload.
The Arm TF-A for FVP can be used to run Zephyr as preloaded BL33 payload.
Checkout and Build the TF-A:
@@ -111,14 +137,8 @@ Debugging
Refer to the detailed overview about :ref:`application_debugging`.
Networking
==========
References
**********
.. target-notes::
1. (ID070919) Arm® Architecture Reference Manual - Armv8, for Armv8-A architecture profile
2. AArch64 Exception and Interrupt Handling
3. https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms
- `Arm Architecture Reference Manual - Armv8 <https://developer.arm.com/documentation/ddi0487/latest>`_
- `Fixed Virtual Platforms <https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms>`_

4
boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts → boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_v8a.dts
View File

@@ -10,12 +10,12 @@
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "FVP Base RevC 2xAEMv8A";
model = "FVP Base RevC 2xAEM ARMv8-A";
chosen {
/*
* The SRAM node is actually located in the
* DRAM region of the FVP Base RevC 2xAEMv8A.
* DRAM region of the FVP Base RevC 2xAEM.
*/
zephyr,sram = &dram0;
zephyr,flash = &flash0;

21
boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_v8a.yaml Normal file
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@@ -0,0 +1,21 @@
identifier: fvp_base_revc_2xaem/v8a
name: FVP Base RevC 2xAEM ARMv8-A
arch: arm64
type: sim
simulation:
- name: armfvp
exec: FVP_Base_RevC-2xAEMvA
toolchain:
- zephyr
- cross-compile
ram: 2048
flash: 64
vendor: arm
supported:
- gpio
- uart
- smp
testing:
ignore_tags:
- net
- bluetooth

0
boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig → boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_v8a_defconfig
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6
boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_v8a_smp.dts Normal file
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@@ -0,0 +1,6 @@
/*
* Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
* SPDX-License-Identifier: Apache-2.0
*/
#include "fvp_base_revc_2xaem_v8a.dts"

12
boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp.yaml → boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_v8a_smp.yaml
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@@ -1,8 +1,8 @@
# Copyright (c) 2025 BayLibre SAS
# SPDX-License-Identifier: Apache-2.0
identifier: fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp
name: FVP Emulation FVP_Base_RevC-2xAEMvA (SMP)
identifier: fvp_base_revc_2xaem/v8a/smp
name: FVP Base RevC 2xAEM ARMv8-A (SMP)
arch: arm64
type: sim
simulation:
@@ -14,3 +14,11 @@ toolchain:
ram: 2048
flash: 64
vendor: arm
supported:
- gpio
- uart
- smp
testing:
ignore_tags:
- net
- bluetooth

0
boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_defconfig → boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_v8a_smp_defconfig
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2
boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.dts → boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_v8a_smp_ns.dts
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@@ -3,4 +3,4 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "fvp_base_revc_2xaemv8a.dts"
#include "fvp_base_revc_2xaem_v8a.dts"

4
boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.yaml → boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_v8a_smp_ns.yaml
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@@ -1,8 +1,8 @@
# Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved.
# SPDX-License-Identifier: Apache-2.0
identifier: fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns
name: FVP Emulation FVP_Base_RevC-2xAEMvA (SMP)
identifier: fvp_base_revc_2xaem/v8a/smp/ns
name: FVP Base RevC 2xAEM ARMv8-A (SMP Non-Secure)
arch: arm64
type: sim
simulation:

0
boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns_defconfig → boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_v8a_smp_ns_defconfig
View File

10
boards/arm/fvp_base_revc_2xaemv8a/board.yml
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@@ -1,10 +0,0 @@
board:
name: fvp_base_revc_2xaemv8a
full_name: BASE RevC AEMv8A Fixed Virtual Platforms
vendor: arm
socs:
- name: v8a
variants:
- name: smp
variants:
- name: ns

16
boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml
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@@ -1,16 +0,0 @@
# Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
identifier: fvp_base_revc_2xaemv8a
name: FVP Emulation FVP_Base_RevC-2xAEMvA
arch: arm64
type: sim
simulation:
- name: armfvp
exec: FVP_Base_RevC-2xAEMvA
toolchain:
- zephyr
- cross-compile
ram: 2048
flash: 64
vendor: arm

6
boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp.dts
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@@ -1,6 +0,0 @@
/*
* Copyright (c) 2025 BayLibre SAS
* SPDX-License-Identifier: Apache-2.0
*/
#include "fvp_base_revc_2xaemv8a.dts"

2
samples/net/dhcpv4_client/README.rst
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@@ -196,7 +196,7 @@ Arm FVP
========
* :zephyr:board:`fvp_baser_aemv8r`
* :ref:`fvp_base_revc_2xaemv8a`
* :zephyr:board:`fvp_base_revc_2xaem`
This sample application running on Arm FVP board can negotiate IP
address from DHCPv4 server running on Arm FVP, so there is no extra

2
tests/arch/arm64/arm64_gicv3_its/testcase.yaml
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@@ -1,5 +1,5 @@
tests:
arch.arm64.gicv3_its:
build_only: true
platform_allow: fvp_base_revc_2xaemv8a
platform_allow: fvp_base_revc_2xaem/v8a
skip: true

2
tests/arch/arm64/arm64_smc_call/testcase.yaml
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@@ -1,6 +1,6 @@
tests:
arch.arm64.smc_call.smc:
platform_allow: fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns
platform_allow: fvp_base_revc_2xaem/v8a/smp/ns
tags:
- arm
- smc

2
tests/kernel/mem_protect/syscalls/src/main.c
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@@ -13,7 +13,7 @@
#define BUF_SIZE 32
#if defined(CONFIG_BOARD_FVP_BASE_REVC_2XAEMV8A)
#if defined(CONFIG_BOARD_FVP_BASE_REVC_2XAEM)
#define SLEEP_MS_LONG 30000
#elif defined(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SIM) || \
defined(CONFIG_BOARD_INTEL_ADSP_ACE40_NVL_SIM)

2
tests/subsys/zbus/dyn_channel/testcase.yaml
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@@ -1,6 +1,6 @@
tests:
message_bus.zbus.dyn_channel.static_and_dynamic_channels:
platform_exclude: fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns
platform_exclude: fvp_base_revc_2xaem/v8a/smp/ns
tags: zbus
integration_platforms:
- native_sim

2
tests/subsys/zbus/hlp_priority_boost/testcase.yaml
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@@ -1,7 +1,7 @@
tests:
message_bus.zbus.hlp_priority_boost:
platform_exclude:
- fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns
- fvp_base_revc_2xaem/v8a/smp/ns
# All Intel Audio DSP platforms have non-coherent cache
# between CPUs. So the zbus_channel struct data goes
# out-of-sync between CPUs with multiple producer and

2
tests/subsys/zbus/integration/testcase.yaml
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@@ -5,7 +5,7 @@ tests:
- qemu_cortex_a9
- hifive_unleashed/fu540/e51
- hifive_unleashed/fu540/u54
- fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns
- fvp_base_revc_2xaem/v8a/smp/ns
tags: zbus
integration_platforms:
- native_sim

4
tests/subsys/zbus/unittests/testcase.yaml
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@@ -1,6 +1,6 @@
tests:
message_bus.zbus.general_unittests:
platform_exclude: fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns
platform_exclude: fvp_base_revc_2xaem/v8a/smp/ns
tags: zbus
integration_platforms:
- native_sim
@@ -13,7 +13,7 @@ tests:
extra_configs:
- CONFIG_CMAKE_LINKER_GENERATOR=y
message_bus.zbus.general_unittests_without_priority_boost:
platform_exclude: fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns
platform_exclude: fvp_base_revc_2xaem/v8a/smp/ns
tags: zbus
integration_platforms:
- native_sim

2
tests/subsys/zbus/user_data/testcase.yaml
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@@ -1,6 +1,6 @@
tests:
message_bus.zbus.user_data.channel_user_data:
platform_exclude: fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns
platform_exclude: fvp_base_revc_2xaem/v8a/smp/ns
tags: zbus
integration_platforms:
- native_sim

2
tests/ztest/error_hook/src/main.c
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@@ -134,7 +134,7 @@ __no_optimization static void trigger_fault_divide_zero(void)
defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || \
defined(CONFIG_BOARD_QEMU_CORTEX_R5) || \
defined(CONFIG_ARMV8_R) || defined(CONFIG_AARCH32_ARMV8_R) || \
defined(CONFIG_BOARD_FVP_BASE_REVC_2XAEMV8A) || \
defined(CONFIG_BOARD_FVP_BASE_REVC_2XAEM) || \
defined(CONFIG_SOC_NSIM_EM11D)
ztest_test_skip();
#endif