michael/zephyr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

soc: litex_vexriscv: Port to HWMv2

Browse Source 
Ports the SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Jamie McCrae
2024-02-14 08:48:27 +00:00
committed by Carles Cufi
parent 1cd4c34654
commit cb9339f88f
6 changed files with 21 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
soc/soc_legacy/riscv/litex_vexriscv/CMakeLists.txt → soc/litex/litex_vexriscv/CMakeLists.txt
View File

@@ -5,8 +5,10 @@
# #
zephyr_sources( zephyr_sources(
${ZEPHYR_BASE}/soc/common/riscv/riscv-privileged/soc_irq.S ${ZEPHYR_BASE}/soc/common/riscv-privileged/soc_irq.S
${ZEPHYR_BASE}/soc/common/riscv/riscv-privileged/vector.S ${ZEPHYR_BASE}/soc/common/riscv-privileged/vector.S
) )
zephyr_include_directories(.)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

7
soc/soc_legacy/riscv/litex_vexriscv/Kconfig.soc → soc/litex/litex_vexriscv/Kconfig
View File

@@ -1,8 +1,7 @@
# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com> # Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
config SOC_RISCV32_LITEX_VEXRISCV config SOC_LITEX_VEXRISCV
bool "LiteX VexRiscv system implementation"
select RISCV select RISCV
select ATOMIC_OPERATIONS_C select ATOMIC_OPERATIONS_C
select INCLUDE_RESET_VECTOR select INCLUDE_RESET_VECTOR
@@ -12,10 +11,10 @@ config SOC_RISCV32_LITEX_VEXRISCV
select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI select RISCV_ISA_EXT_ZIFENCEI
if SOC_RISCV32_LITEX_VEXRISCV if SOC_LITEX_VEXRISCV
config LITEX_CSR_DATA_WIDTH config LITEX_CSR_DATA_WIDTH
int "Select Control/Status register width" int "Select Control/Status register width"
default 32 default 32
endif # SOC_RISCV32_LITEX_VEXRISCV endif # SOC_LITEX_VEXRISCV

7
soc/soc_legacy/riscv/litex_vexriscv/Kconfig.defconfig → soc/litex/litex_vexriscv/Kconfig.defconfig
View File

@@ -1,10 +1,7 @@
# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com> # Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
if SOC_RISCV32_LITEX_VEXRISCV if SOC_LITEX_VEXRISCV
config SOC
default "litex_vexriscv"
config SYS_CLOCK_HW_CYCLES_PER_SEC config SYS_CLOCK_HW_CYCLES_PER_SEC
default 100000000 default 100000000
@@ -12,4 +9,4 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config NUM_IRQS config NUM_IRQS
default 12 default 12
endif # SOC_RISCV32_LITEX_VEXRISCV endif # SOC_LITEX_VEXRISCV

10
soc/litex/litex_vexriscv/Kconfig.soc Normal file
View File

@@ -0,0 +1,10 @@
# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_LITEX_VEXRISCV
bool
help
LiteX VexRiscv system implementation
config SOC
default "litex_vexriscv" if SOC_LITEX_VEXRISCV

0
soc/soc_legacy/riscv/litex_vexriscv/soc.h → soc/litex/litex_vexriscv/soc.h
View File

2
soc/litex/litex_vexriscv/soc.yml Normal file
View File

@@ -0,0 +1,2 @@
socs:
- name: litex_vexriscv