soc: xilinx: zync7000: Remove xilinx from soc series name
Removes the vendor name from a Kconfig symbol Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Jamie McCrae
committed by
Carles Cufi
Carles Cufi
parent
8dfabd56ca
commit
df994e7ee8
@@ -6,7 +6,7 @@
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# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
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#
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config SOC_SERIES_XILINX_XC7ZXXX
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config SOC_SERIES_XC7ZXXX
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select ARM
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select CPU_CORTEX_A9
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select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
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@@ -3,10 +3,10 @@
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_XILINX_XC7ZXXX
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if SOC_SERIES_XC7ZXXX
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# Zephyr does not support SMP on aarch32 yet, so we default to 1 CPU core
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config MP_MAX_NUM_CPUS
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default 1
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endif # SOC_SERIES_XILINX_XC7ZXXX
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endif # SOC_SERIES_XC7ZXXX
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@@ -6,7 +6,7 @@
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# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
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#
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config SOC_SERIES_XILINX_XC7ZXXX
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config SOC_SERIES_XC7ZXXX
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bool
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select SOC_FAMILY_XILINX_ZYNQ7000
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help
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@@ -15,14 +15,14 @@ config SOC_SERIES_XILINX_XC7ZXXX
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config SOC_XILINX_XC7Z010
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bool
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select SOC_SERIES_XILINX_XC7ZXXX
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select SOC_SERIES_XC7ZXXX
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help
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2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
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28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins.
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config SOC_XILINX_XC7Z015
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bool
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select SOC_SERIES_XILINX_XC7ZXXX
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select SOC_SERIES_XC7ZXXX
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help
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2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
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74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins,
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@@ -30,14 +30,14 @@ config SOC_XILINX_XC7Z015
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config SOC_XILINX_XC7Z020
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bool
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select SOC_SERIES_XILINX_XC7ZXXX
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select SOC_SERIES_XC7ZXXX
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help
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2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
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85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins.
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config SOC_XILINX_XC7Z030
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bool
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select SOC_SERIES_XILINX_XC7ZXXX
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select SOC_SERIES_XC7ZXXX
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help
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2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
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125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins,
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@@ -45,7 +45,7 @@ config SOC_XILINX_XC7Z030
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config SOC_XILINX_XC7Z035
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bool
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select SOC_SERIES_XILINX_XC7ZXXX
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select SOC_SERIES_XC7ZXXX
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help
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2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
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275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins,
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@@ -53,7 +53,7 @@ config SOC_XILINX_XC7Z035
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config SOC_XILINX_XC7Z045
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bool
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select SOC_SERIES_XILINX_XC7ZXXX
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select SOC_SERIES_XC7ZXXX
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help
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2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
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350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins,
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@@ -61,14 +61,14 @@ config SOC_XILINX_XC7Z045
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config SOC_XILINX_XC7Z100
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bool
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select SOC_SERIES_XILINX_XC7ZXXX
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select SOC_SERIES_XC7ZXXX
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help
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2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
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444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins,
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up to 16 transceivers.
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config SOC_SERIES
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default "xc7zxxx" if SOC_SERIES_XILINX_XC7ZXXX
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default "xc7zxxx" if SOC_SERIES_XC7ZXXX
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config SOC
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default "xc7z010" if SOC_XILINX_XC7Z010
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@@ -6,7 +6,7 @@
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# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
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#
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config SOC_SERIES_XILINX_XC7ZXXXS
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config SOC_SERIES_XC7ZXXXS
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select ARM
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select CPU_CORTEX_A9
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select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
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@@ -3,9 +3,9 @@
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_XILINX_XC7ZXXXS
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if SOC_SERIES_XC7ZXXXS
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config MP_MAX_NUM_CPUS
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default 1
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endif # SOC_SERIES_XILINX_XC7ZXXXS
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endif # SOC_SERIES_XC7ZXXXS
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@@ -6,7 +6,7 @@
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# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
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#
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config SOC_SERIES_XILINX_XC7ZXXXS
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config SOC_SERIES_XC7ZXXXS
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bool
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select SOC_FAMILY_XILINX_ZYNQ7000
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help
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@@ -15,14 +15,14 @@ config SOC_SERIES_XILINX_XC7ZXXXS
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config SOC_XILINX_XC7Z007S
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bool
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select SOC_SERIES_XILINX_XC7ZXXXS
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select SOC_SERIES_XC7ZXXXS
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help
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1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
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23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins.
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config SOC_XILINX_XC7Z012S
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bool
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select SOC_SERIES_XILINX_XC7ZXXXS
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select SOC_SERIES_XC7ZXXXS
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help
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1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
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55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins,
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@@ -30,13 +30,13 @@ config SOC_XILINX_XC7Z012S
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config SOC_XILINX_XC7Z014S
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bool
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select SOC_SERIES_XILINX_XC7ZXXXS
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select SOC_SERIES_XC7ZXXXS
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help
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1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
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65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins.
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config SOC_SERIES
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default "xc7zxxxs" if SOC_SERIES_XILINX_XC7ZXXXS
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default "xc7zxxxs" if SOC_SERIES_XC7ZXXXS
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config SOC
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default "xc7z007s" if SOC_XILINX_XC7Z007S
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