soc: rk3568: Port to HWMv2

Ports the rk3568 SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

soc/arm64/rockchip/rk3568/CMakeLists.txt

@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)

soc/arm64/rockchip/rk3568/Kconfig.series

@@ -1,10 +0,0 @@
-# Copyright 2022 HNU-ESNL
-# Copyright 2022 openEuler SIG-Zephyrs
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_RK3568
-	bool "Rockchip RK3568 Series"
-	select ARM64
-	select SOC_FAMILY_ROCKCHIP
-	help
-	  Enable support for RK3568 Series.

soc/arm64/rockchip/rk3568/linker.ld

@@ -1,7 +0,0 @@
-/*
- * Copyright 2020 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/arch/arm64/scripts/linker.ld>

soc/v2/rockchip/CMakeLists.txt

@@ -0,0 +1,7 @@
+#
+# Copyright 2021 Huawei France Technologies SASU
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+add_subdirectory(${SOC_SERIES})

soc/v2/rockchip/Kconfig

@@ -0,0 +1,7 @@
+#
+# Copyright 2021 Huawei France Technologies SASU
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+rsource "*/Kconfig"

soc/v2/rockchip/Kconfig.defconfig

@@ -0,0 +1,11 @@
+#
+# Copyright 2021 Huawei France Technologies SASU
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_FAMILY_ROCKCHIP
+
+rsource "*/Kconfig.defconfig"
+
+endif

soc/v2/rockchip/Kconfig.soc

@@ -0,0 +1,13 @@
+#
+# Copyright 2021 Huawei France Technologies SASU
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_FAMILY_ROCKCHIP
+	bool
+
+config SOC_FAMILY
+	default "rockchip" if SOC_FAMILY_ROCKCHIP
+
+rsource "*/Kconfig.soc"

soc/v2/rockchip/rk3568/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

soc/v2/rockchip/rk3568/Kconfig

@@ -2,15 +2,8 @@
 # Copyright 2022 openEuler SIG-Zephyr
 # SPDX-License-Identifier: Apache-2.0
 
-choice
-prompt "Rockchip RK3568 SoC"
-depends on SOC_SERIES_RK3568
-
-config SOC_RK3568
-	bool "Rockchip rk3568"
+config SOC_SERIES_RK3568
 	select ARM64
 	select CPU_CORTEX_A55
 	select ARM_ARCH_TIMER
 	select GIC_V3
-
-endchoice

soc/v2/rockchip/rk3568/Kconfig.defconfig

@@ -4,9 +4,6 @@
 
 if SOC_SERIES_RK3568
 
-config SOC_SERIES
-	default "rk3568"
-
-source "soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568"
+rsource "Kconfig.defconfig.rk3568"
 
 endif # SOC_SERIES_RK3568

soc/v2/rockchip/rk3568/Kconfig.defconfig.rk3568

@@ -4,9 +4,6 @@
 
 if SOC_RK3568
 
-config SOC
-	default "rk3568"
-
 config FLASH_SIZE
 	default 0
 

soc/v2/rockchip/rk3568/Kconfig.soc

@@ -0,0 +1,20 @@
+# Copyright 2022 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyr
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RK3568
+	bool
+	select SOC_FAMILY_ROCKCHIP
+
+config SOC_RK3568
+	bool
+	select SOC_SERIES_RK3568
+
+config SOC
+	default "rk3568" if SOC_RK3568
+
+config SOC_SERIES
+	default "rk3568" if SOC_RK3568
+
+config SOC_PART_NUMBER
+	default "RK3568" if SOC_SERIES_RK3568

soc/v2/rockchip/soc.yml

@@ -0,0 +1,4 @@
+series:
+- name: rk3568
+  socs:
+  - name: rk3568