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drivers: flash: stm32g0: Implement option_bytes_write|read API

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Implementation based on STM32G4 series.

This is a preparation to enable reading and writing the RDP bits.

Signed-off-by: Martin Jäger <martin@libre.solar>
This commit is contained in:
Martin Jäger
2025-07-15 18:12:42 +02:00
committed by Chris Friedt
parent 50ac559152
commit faf661e907
2 changed files with 45 additions and 0 deletions
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1
drivers/flash/flash_stm32_ex_op.c
View File

@@ -331,6 +331,7 @@ int flash_stm32_ex_op(const struct device *dev, uint16_t code,
#if defined(CONFIG_FLASH_STM32_OPTION_BYTES) && ( \
defined(CONFIG_DT_HAS_ST_STM32F4_FLASH_CONTROLLER_ENABLED) || \
defined(CONFIG_DT_HAS_ST_STM32F7_FLASH_CONTROLLER_ENABLED) || \
defined(CONFIG_DT_HAS_ST_STM32G0_FLASH_CONTROLLER_ENABLED) || \
defined(CONFIG_DT_HAS_ST_STM32G4_FLASH_CONTROLLER_ENABLED) || \
defined(CONFIG_DT_HAS_ST_STM32L4_FLASH_CONTROLLER_ENABLED))
case FLASH_STM32_EX_OP_OPTB_READ:

44
drivers/flash/flash_stm32g0x.c
View File

@@ -15,6 +15,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
#include <zephyr/device.h>
#include <string.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/init.h>
#include <soc.h>
@@ -195,6 +196,49 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
return rc;
}
int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask,
uint32_t value)
{
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
int rc;
if (regs->CR & FLASH_CR_OPTLOCK) {
return -EIO;
}
if ((regs->OPTR & mask) == value) {
return 0;
}
rc = flash_stm32_wait_flash_idle(dev);
if (rc < 0) {
return rc;
}
regs->OPTR = (regs->OPTR & ~mask) | value;
regs->CR |= FLASH_CR_OPTSTRT;
/* Make sure previous write is completed. */
barrier_dsync_fence_full();
rc = flash_stm32_wait_flash_idle(dev);
if (rc < 0) {
return rc;
}
/* Force the option byte loading */
regs->CR |= FLASH_CR_OBL_LAUNCH;
return flash_stm32_wait_flash_idle(dev);
}
uint32_t flash_stm32_option_bytes_read(const struct device *dev)
{
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
return regs->OPTR;
}
/*
* The address space is always continuous, even though a subset of G0 SoCs has
* two flash banks.