soc: nxp: convert iMX6 SoloX core to HWMv2

Convert iMX6 SoloX core to HWMv2. This port currently only supports the
M4 core (as it did in HWMv1)

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>

soc/nxp/imx/imx6sx/CMakeLists.txt

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018, NXP
+# Copyright 2018,2024 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -9,4 +9,6 @@ zephyr_sources(
   soc_clk_freq.c
 )
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/nxp/imx/imx6sx/Kconfig

@@ -0,0 +1,18 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_IMX6SX
+	select ARM
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select HAS_IMX_HAL
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
+	select CLOCK_CONTROL
+
+config SOC_MCIMX6X_M4
+	select HAS_IMX_HAL
+	select HAS_IMX_GPIO
+	select HAS_IMX_EPIT
+	select HAS_IMX_I2C
+	select HAS_IMX_IOMUXC

soc/nxp/imx/imx6sx/Kconfig.defconfig

@@ -0,0 +1,18 @@
+# i.MX 6SoloX core series
+
+# Copyright 2018,2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_IMX6SX
+
+config NUM_IRQS
+	# must be >= the highest interrupt number used
+	default 128
+
+config PINCTRL_IMX
+	default y if HAS_IMX_IOMUXC
+	depends on PINCTRL
+
+rsource "Kconfig.defconfig.*"
+
+endif # SOC_SERIES_IMX6SX

soc/nxp/imx/imx6sx/Kconfig.defconfig.mcimx6x_m4

@@ -1,13 +1,10 @@
 # i.MX 6SoloX
 
-# Copyright (c) 2018, NXP
+# Copyright 2018,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_MCIMX6X_M4
 
-config SOC
-	default "mcimx6x"
-
 config FPU
 	default y
 

soc/nxp/imx/imx6sx/Kconfig.soc

@@ -1,23 +1,28 @@
-# i.MX 6SoloX M4 core series
+# i.MX 6SoloX core series
 
-# Copyright (c) 2018, NXP
+# Copyright 2018,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-choice
+
-	prompt "i.MX 6SoloX Selection"
+config SOC_SERIES_IMX6SX
-	depends on SOC_SERIES_IMX_6X_M4
+	bool
+	select SOC_FAMILY_NXP_IMX
+
+config SOC_MCIMX6X
+	bool
+	select SOC_SERIES_IMX6SX
 
 config SOC_MCIMX6X_M4
-	bool "SOC_MCIMX6X_M4"
+	select SOC_MCIMX6X
-	select HAS_IMX_HAL
+	bool
-	select HAS_IMX_GPIO
+	help
-	select HAS_IMX_EPIT
+	  NXP iMX6 SoloX M4 core
-	select HAS_IMX_I2C
-	select HAS_IMX_IOMUXC
 
-endchoice
+config SOC_SERIES
+	default "imx6sx" if SOC_SERIES_IMX6SX
 
-if SOC_SERIES_IMX_6X_M4
+config SOC
+	default "mcimx6x" if SOC_MCIMX6X
 
 config SOC_PART_NUMBER_MCIMX6X1EVK10AB
 	bool
@@ -61,8 +66,7 @@ config SOC_PART_NUMBER_MCIMX6X4EVM10AB
 config SOC_PART_NUMBER_MCIMX6X4EVM10AC
 	bool
 
-config SOC_PART_NUMBER_IMX_6X_M4
+config SOC_PART_NUMBER
-	string
 	default "MCIMX6X1EVK10AB" if SOC_PART_NUMBER_MCIMX6X1EVK10AB
 	default "MCIMX6X1EVK10AC" if SOC_PART_NUMBER_MCIMX6X1EVK10AC
 	default "MCIMX6X3EVK10AB" if SOC_PART_NUMBER_MCIMX6X3EVK10AB
@@ -77,9 +81,3 @@ config SOC_PART_NUMBER_IMX_6X_M4
 	default "MCIMX6X3EVN10AC" if SOC_PART_NUMBER_MCIMX6X3EVN10AC
 	default "MCIMX6X4EVM10AB" if SOC_PART_NUMBER_MCIMX6X4EVM10AB
 	default "MCIMX6X4EVM10AC" if SOC_PART_NUMBER_MCIMX6X4EVM10AC
-	help
-	  This string holds the full part number of the SoC. It is a hidden option
-	  that you should not set directly. The part number selection choice defines
-	  the default value for this string.
-
-endif # SOC_SERIES_IMX_6X_M4

soc/nxp/imx/soc.yml

@@ -44,3 +44,9 @@ family:
       cpuclusters:
       - name: a55
       - name: m33
+  - name: imx6sx
+    socs:
+    - name: mcimx6x
+      cpuclusters:
+      - name: a9
+      - name: m4

soc/soc_legacy/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.series

@@ -1,21 +0,0 @@
-# i.MX 6SoloX M4 core series
-
-# Copyright (c) 2018, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_IMX_6X_M4
-
-config SOC_SERIES
-	default "mcimx6x_m4"
-
-config NUM_IRQS
-	# must be >= the highest interrupt number used
-	default 128
-
-config PINCTRL_IMX
-	default y if HAS_IMX_IOMUXC
-	depends on PINCTRL
-
-source "soc/soc_legacy/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4"
-
-endif # SOC_SERIES_IMX_6X_M4

soc/soc_legacy/arm/nxp_imx/mcimx6x_m4/Kconfig.series

@@ -1,17 +0,0 @@
-# i.MX 6SoloX M4 core series
-
-# Copyright (c) 2018, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_IMX_6X_M4
-	bool "i.MX 6SoloX M4 Core Series"
-	select ARM
-	select CPU_CORTEX_M4
-	select CPU_CORTEX_M_HAS_DWT
-	select HAS_IMX_HAL
-	select SOC_FAMILY_IMX
-	select CPU_HAS_FPU
-	select CPU_HAS_ARM_MPU
-	select CLOCK_CONTROL
-	help
-	  Enable support for M4 core of i.MX 6SoloX MCU series