The K_TIMEOUT_SUM() macro is intended as a means to add two
k_timeout_t values together. This may be useful for a developer
applying an exponential backoff algorithm.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Test had forever loop that was attempting to read k_timer_remaining_ticks
while system tick did not change. If target has relatively fast system
clock then it might be impossible.
Tweak test to repeat few times and if k_timer_remaining_ticks is not
read in the known tick then range is used to validate correctness of
the returned value.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Adjusting CONFIG_SYS_CLOCK_TICKS_PER_SEC as core is to slow too run
the test with the default system clock frequency.
Signed-off-by: Paweł Pelikan <pawel.pelikan@nordicsemi.no>
Fix format specifiers that did not match the argument type.
Use %zu format specifier for size_t type to ensure compatibility
with both 32-bit and 64-bit platforms. Escape percent signs in
format strings using %% to prevent warnings about unknown format
specifiers.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
requests < 2.32.4 is subject to GHSA-9hjg-9r4m-mvj7
pyyaml < 5.4 is subject to GHSA-8q59-q68h-6hv4
pyyaml < 5.1 is subject to GHSA-rprw-h62v-c2w7
protobuf < 5.29.5 is subject to GHSA-8qvm-5x2c-j2w7
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Adding overlays for Infineon kit_psc3m5_evk board to kernel/common,
kernel/timer/timer_error_case and kernel/timer/timer_api tests
when run in secure mode. These tests require more memory than
the board assigns to secure mode by default.
Signed-off-by: John Batch <john.batch@infineon.com>
Remove possibility to run tests on nrf54l09pdk as this is
an obsolete board that is going to be removed.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
max_stddev calculation was previously patched to be more at least
1 system clock cycle to cover for platforms that use higher frequency
system clock (32kHz). On that platform (nRF52) system clock frequency
was the same as tick frequency but on nRF54x that is no longer true.
Initially, the intention was to use 1 system tick and not cycle.
Fixing it now.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Remove duplicated test configuration after
nrf54l20pdk/nrf54l20/cpuxxx was renamed to
nrf54lm20dk/nrf54lm20a/cpuxxx.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
When CONFIG_TIMEOUT_64BIT is y, positive values are relative/delta
timeouts and negative values are absolute timeouts, except
for two special values. -1 is K_WAIT_FOREVER and 0 is K_NO_WAIT.
The reserved value of -1 means INT64_MAX is not a valid argument
to K_TIMEOUT_ABS_TICKS(), but there was no check. If a literal
was passed, a preprocessor/compiler warning would be generated
for overflow, but if a variable was passed as the argument,
then the code would compile but not work correctly since the
absolute timeout would be changed to a relative one. One
example of this is task_wdt_init() if no channels are enabled.
Rather than just fixing task_wdt, and trying to find other cases
in an adhoc way, this CL changes K_TIMEOUT_ABS_TICKS() to
limit the larges value to (INT64_MAX-1). It does so silently,
but given the range of int64_t, there should be no practical
difference.
Also, change the implementation for Z_IS_TIMEOUT_RELATIVE() to
fix the case where INT64_MAX relative timeout was being
improperly reported as being not a relative timeout. This was
again due to the -1 reserved value.
Add some tests for these changes to the timer_api test.
Signed-off-by: Mike J. Chen <mjchen@google.com>
When CONFIG_ZTEST_ASSERT_VERBOSE is 0, the array round_s is not
being used by zassert_true(). So mark it __maybe_unused to
avoid compiler warnings.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fix issues reported by string validation which was added to strings
used in zassert macros.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The new Nordic platforms use GRTC instead of RTC
as the system timer.
Also the nrf54h20 CPUPPR target does not have enough memory
to execute the `timer_behavior` test.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Add return value to z_add_timeout. It returns system tick when timeout
will expire.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Validate that `K_TIMEOUT_ABS_SEC` works the same way as the other
absolute timeout construction macros.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Some platforms were excluded due to issues that were fixed or resolved
themselves. Enable those platforms again and remove the comments related
to the issues.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Type case CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC to uint32_t
while defining sys_clock_hw_cycles_per_sec_runtime_get()
to extend the range of frequency to 0xffffffff.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Make sure we install packages with no issues, some of the issues being
reporting on packages we might install using pip:
Warn: Project is vulnerable to: PYSEC-2019-41 / GHSA-qfc5-mcwq-26q8
Warn: Project is vulnerable to: PYSEC-2014-14 / GHSA-652x-xj99-gmcc
Warn: Project is vulnerable to: GHSA-9wx4-h78v-vm56
Warn: Project is vulnerable to: PYSEC-2014-13 / GHSA-cfj3-7x9c-4p3h
Warn: Project is vulnerable to: PYSEC-2018-28 / GHSA-x84v-xcm2-53pg
Warn: Project is vulnerable to: PYSEC-2017-74
Warn: Project is vulnerable to: GHSA-55x5-fj6c-h6m8
Warn: Project is vulnerable to: PYSEC-2014-9 / GHSA-57qw-cc2g-pv5p
Warn: Project is vulnerable to: PYSEC-2021-19 / GHSA-jq4v-f5q6-mjqq
Warn: Project is vulnerable to: GHSA-pgww-xf46-h92r
Warn: Project is vulnerable to: PYSEC-2022-230 / GHSA-wrxv-2j5q-m38w
Warn: Project is vulnerable to: PYSEC-2018-12 / GHSA-xp26-p53h-6h2p
Warn: Project is vulnerable to: PYSEC-2024-4 / GHSA-2mqj-m65w-jghx
Warn: Project is vulnerable to: PYSEC-2023-165 / GHSA-cwvm-v4w8-q58c
Warn: Project is vulnerable to: PYSEC-2022-42992 / GHSA-hcpj-qp55-gfph
Warn: Project is vulnerable to: PYSEC-2023-137 / GHSA-pr76-5cm5-w9cj
Warn: Project is vulnerable to: PYSEC-2023-161 / GHSA-wfm5-v35h-vwf4
Warn: Project is vulnerable to: GHSA-3f63-hfp8-52jq
Warn: Project is vulnerable to: GHSA-44wm-f244-xhp3
Warn: Project is vulnerable to: GHSA-56pw-mpj4-fxww
Warn: Project is vulnerable to: GHSA-j7hp-h8jx-5ppr
Warn: Project is vulnerable to: PYSEC-2023-175
Warn: Project is vulnerable to: PYSEC-2018-34 / GHSA-2fc2-6r4j-p65h
Warn: Project is vulnerable to: PYSEC-2021-856 / GHSA-5545-2q6w-2gh6
Warn: Project is vulnerable to: PYSEC-2019-108 / GHSA-9fq2-x9r6-wfmf
Warn: Project is vulnerable to: PYSEC-2018-33 / GHSA-cw6w-4rcx-xphc
Warn: Project is vulnerable to: PYSEC-2021-857 / GHSA-f7c7-j99h-c22f
Warn: Project is vulnerable to: GHSA-fpfv-jqm9-f5jm
Warn: Project is vulnerable to: PYSEC-2017-1 / GHSA-frgw-fgh6-9g52
Warn: Project is vulnerable to: GHSA-c6fm-rgw4-8q73
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Test test_timer_remaining is comparing time captured by k_busy_wait and
k_timer_remaining_ticks. Test was accepting 1 tick difference between
those two. If system clock frequency is low (e.g. 100 Hz) 1 tick is a
long time but if system clock is high then 1 tick may not cover for
processing latency. Instead of using fixed 1 tick test is now converting
100 us to ticks (ceiling) to cover for cases where system clock is high.
100 us processing latency time is an arbitrary value.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Test test_one_tick_timer_train was failing due not being able to
execute enough 1 tick timeouts. Decrease system ticks frequency
to make the test pass.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Adjust testcase.yaml files to changes in Twister schema which
now allows multiple recording patterns ('record: regex:').
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Currently the timer_behavior test uses fabs.
Since the C library functions being used in the kernel
is restricted in Rule A.4 in the Coding Standard
We should probably not use these functions in tests either.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
Test test_one_tick_timer_train was failing due not being able to
execute enough 1 tick timeouts. Decrease system ticks frequency
to make the test pass.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Adjust default number of test samples which is based on SRAM size.
Test is using 8*TIMER_TEST_SAMPLES and with previous defaults for
the device with 64k RAM it was using 56k of test data leaving only
8k RAM and that was easily not enough. Adjust conditions to
take less samples when SRAM_SIZE is equal to the threshold.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
sqrtf() is used for floats but the argument and resulting
variable are both doubles. LLVM would complain about
implicit conversion from float to double. So use sqrt()
instead as it is used with doubles.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Like in C test. If MAX STDDEV is lower than single clock cycle then
set it to a single clock cycle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
If frequency of the system clock is lower then deviation may exceed
default value (10us). Instead of adjusting the default value, test is
rounding up expected standard deviation to a single clock cycle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
`checkpatch.pl` requires that dts sources are indented with tabs,
fix all the spaces that slipped in while checkpatch wasn't watching.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Fix incomplete test log capture when the external tool is used
and Twister Pytest Harness script ends without reading output
from the last test case running on the device.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Additional logging of kernel.timer.timer_behavior_external test case
statistics for timer drift, variance, etc. as JSON-formatted records
to make easier data collection and its further analysis.
These log records will be processed by the Twister Harness recording
feature which captures and parses timer statistics from the log output,
then composes it into twister.json and recording.csv files.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Additional logging of kernel.timer.timer test case statistics for
timer drift, variance, etc. as JSON-formatted records to make easier
data collection and its further analysis.
These log records will be processed by the Twister Harness recording
feature which captures and parses timer statistics from the log output,
then composes it into twister.json and recording.csv files.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
32-bit multiplication overflows for the 130000 ppm value used currently
on Nordic SoCs and the duration that is configured to 100000 us.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
On Nordic SoCs, the clock that drives the system timer and the one that
is used in busy-waiting may be significantly skewed, so the test cases
that compare durations derived from those two clocks need to take into
account a proper threshold. After the `z_timeout_expires` function was
corrected in 3d29c9fe54, it turned out
that the threshold was missing in one check and the related test case
started to fail on nRF platforms. This patch adds that threshold there.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Align grpcio version with logic2-automation package fixing its fail
on Channel.unary_unary() call with missing _registered_method argument..
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Let's also explicitly test that absolute timeouts trigger
at the correct time, even if the kernel has not seen
system clock timer announcements for a while.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
There might be a deviation of 30.5 microseconds (1 cycle) due to the
calculation deviation between free run and event timers. This commit
increases stdev to 33 for ite platform.
Fix#67833
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
