The new node is called "npu_cache".
This way a possibility is offered to choose - thru an overlay - if to
enable the NPU cache or not.
This new node has a dependency with node "npu", so the NPU cache's
status is taken into account only in case node "npu" has status "okay".
Default status value of "npu_cache" is "okay"
(i.e. enable the NPU cache).
Signed-off-by: Wolfgang Betz <wolfgang.betz@st.com>
RIF configuration is now done at soc init time in a centralized
way so it is no more necessary for drivers to perform this
configuration.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Use STM32_CLOCK_INFO(), STM32_DT_INST_CLOCK_INFO(),
STM32_CLOCK_INFO_BY_NAME() and STM32_DT_INST_CLOCK_INFO_BY_NAME()
helper macros in STM32 drivers.
Using these macros ensure the clock division factor is properly
populated according to DT information. Prior these changes some
drivers only got the bus and bits position information and missed
the clock division information which is fine only when this division
factor information is 0.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add the description of NPU Cache (aka cacheaxi) to allow configuring
them in NPU Cache driver.
I intentionally chose this over creating a new dedicated node as
the exclusive user is NPU Cache and this could be done as part of
NPU driver initialization.
Update the NPU driver to take those into account as part of its init
routine.
Signed-off-by: Mickael Guene <mickael.guene@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
