b84bdbcee3
The new node is called "npu_cache". This way a possibility is offered to choose - thru an overlay - if to enable the NPU cache or not. This new node has a dependency with node "npu", so the NPU cache's status is taken into account only in case node "npu" has status "okay". Default status value of "npu_cache" is "okay" (i.e. enable the NPU cache). Signed-off-by: Wolfgang Betz <wolfgang.betz@st.com>
69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_npu
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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/* Read-only driver configuration */
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struct npu_stm32_cfg {
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/* Clock configuration. */
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struct stm32_pclken pclken_npu;
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struct stm32_pclken pclken_cacheaxi;
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/* Reset configuration */
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const struct reset_dt_spec reset_npu;
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const struct reset_dt_spec reset_cacheaxi;
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};
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static int npu_stm32_init(const struct device *dev)
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{
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const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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const struct npu_stm32_cfg *cfg = dev->config;
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if (!device_is_ready(clk)) {
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return -ENODEV;
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}
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if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken_npu) != 0) {
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return -EIO;
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}
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if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken_cacheaxi) != 0) {
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return -EIO;
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}
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if (!device_is_ready(cfg->reset_npu.dev)) {
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return -ENODEV;
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}
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/* Reset timer to default state using RCC */
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(void)reset_line_toggle_dt(&cfg->reset_npu);
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(void)reset_line_toggle_dt(&cfg->reset_cacheaxi);
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return 0;
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}
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static const struct npu_stm32_cfg npu_stm32_cfg = {
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.pclken_npu = STM32_DT_INST_CLOCK_INFO(0),
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.reset_npu = RESET_DT_SPEC_INST_GET(0),
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/*
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* Even if npu_cache node is disabled, its clocks must be enabled for NPU operation.
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* This is why we need to get clock and reset line from the npu_cache node.
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*/
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.pclken_cacheaxi = STM32_CLOCK_INFO(0, DT_NODELABEL(npu_cache)),
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.reset_cacheaxi = RESET_DT_SPEC_GET(DT_NODELABEL(npu_cache)),
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};
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DEVICE_DT_INST_DEFINE(0, npu_stm32_init, NULL, NULL, &npu_stm32_cfg, POST_KERNEL,
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CONFIG_STM32N6_NPU_INIT_PRIORITY, NULL);
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