release: Zephyr 1.13.0

Bump version to 1.13.0 final.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.gitignore

@@ -11,15 +11,17 @@ build
 build-*
 cscope.*
 .dir
+
+/*.patch
+
+# The .cache directory will be used to cache toolchain capabilities if
+# no suitable out-of-tree directory is found.
+.cache
+
 outdir
 outdir-*
 scripts/basic/fixdep
 scripts/gen_idt/gen_idt
-scripts/kconfig/conf
-scripts/kconfig/mconf
-scripts/kconfig/zconf.hash.c
-scripts/kconfig/zconf.lex.c
-scripts/kconfig/zconf.tab.c
 doc/_build
 doc/doxygen
 doc/xml
@@ -30,8 +32,7 @@ doc/latex
 doc/themes/zephyr-docs-theme
 sanity-out/
 scripts/grub
-doc/reference/kconfig/CONFIG_*
-doc/reference/kconfig/index.rst
+doc/reference/kconfig/*.rst
 doc/doc.warnings
 tags
 .project
@@ -39,3 +40,6 @@ tags
 .xxproject
 .envrc
 .vscode
+
+# Disables the warning about the changed behavior for Kconfig defaults
+hide-defaults-note

.known-issues/doc/bluetooth.conf

@@ -3,7 +3,7 @@
 #
 # FIXME: all these should match the relative filename
 #
-^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
 ^[ \t]*$
 ^[ \t]*\^$
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
@@ -15,7 +15,7 @@
 #
 # bt_gatt_discover_params unnamed struct definition
 #
-^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
@@ -27,7 +27,7 @@
 #
 # Bluetooth GATT unnamed struct definition
 #
-^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
@@ -39,7 +39,7 @@
 #
 # Bluetooth mesh unnamed struct definition
 #
-^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]

.known-issues/doc/display.conf

@@ -4,7 +4,7 @@
 #
 # include
 #
-^(?P<filename>[-._/\w]+/doc/api/display_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]display_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]

.known-issues/doc/duplicate.conf

@@ -0,0 +1,6 @@
+#
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]file_system.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration.
+#
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration.
+#
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]subsystems[/\\]sensor.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration.

.known-issues/doc/kernel.conf

@@ -4,7 +4,7 @@
 #
 # include/kernel.h warnings
 #
-^(?P<filename>[-._/\w]+/doc/api/kernel_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]kernel_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]

.known-issues/doc/misc.conf

@@ -4,7 +4,7 @@
 #
 # include
 #
-^(?P<filename>[-._/\w]+/doc/api/misc_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]misc_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]

.known-issues/doc/networking.conf

@@ -4,7 +4,7 @@
 #
 # include/net/net_ip.h warnings
 #
-^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
@@ -19,7 +19,7 @@
 #
 # include/net/net_mgmt.h
 #
-^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
@@ -31,7 +31,7 @@
 #
 # include/net/buf.h
 #
-^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
@@ -43,7 +43,7 @@
 #
 # include/net/ieee802154.h
 #
-^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
@@ -52,3 +52,15 @@
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
 ^.*ieee802154_req_params.__unnamed__
 ^[- \t]*\^
+#
+# include/net/net_context.h
+#
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*net_context.options
+^[- \t]*\^
+#
+# include/net/net_stats.h
+#
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*net_stats_tc.[a-z]+
+^[- \t]*\^

.known-issues/doc/uart.conf

@@ -1,7 +1,7 @@
 #
 # UART unnamed struct definition
 #
-^(?P<filename>[-._/\w]+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]api[/\\]io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]

.mailmap

@@ -19,3 +19,4 @@ Naga Raja Rao Tulasi <tulasi.r@tcs.com> <tulasi.r@tcs.com>
 Felipe Neves <ryukokki.felipe@gmail.com> <ryukokki.felipe@gmail.com>
 Amir Kaplan <amir.kaplan@intel.com> <amir.kaplan@intel.com>
 Anas Nashif <anas.nashif@intel.com> <anas.nashif@intel.com>
+Ruud Derwig <Ruud.Derwig@synopsys.com> <Ruud.Derwig@synopsys.com>

.shippable.yml

@@ -4,18 +4,19 @@ compiler: gcc
 
 env:
     global:
-        - SDK=0.9.2
-        - SANITYCHECK_OPTIONS=" --inline-logs"
+        - SDK=0.9.3
+        - SANITYCHECK_OPTIONS=" --inline-logs --enable-coverage "
         - SANITYCHECK_OPTIONS_RETRY="${SANITYCHECK_OPTIONS} --only-failed --outdir=out-2nd-pass"
-        - ZEPHYR_SDK_INSTALL_DIR=/opt/sdk/zephyr-sdk-0.9.2
+        - ZEPHYR_SDK_INSTALL_DIR=/opt/sdk/zephyr-sdk-0.9.3
         - ZEPHYR_TOOLCHAIN_VARIANT=zephyr
-        - MATRIX_BUILDS="4"
-        - MATRIX_BUILDS_EXTRA="4"
+        - MATRIX_BUILDS="5"
+        - MATRIX_BUILDS_EXTRA="5"
     matrix:
         - MATRIX_BUILD="1"
         - MATRIX_BUILD="2"
         - MATRIX_BUILD="3"
         - MATRIX_BUILD="4"
+        - MATRIX_BUILD="5"
 
 build:
     cache: true
@@ -23,7 +24,7 @@ build:
         - ${SHIPPABLE_BUILD_DIR}/ccache
     pre_ci_boot:
         image_name: zephyrprojectrtos/ci
-        image_tag: v0.3
+        image_tag: v0.4-rc7
         pull: true
         options: "-e HOME=/home/buildslave --privileged=true --tty --net=bridge --user buildslave"
 
@@ -34,9 +35,9 @@ build:
           git rebase origin/${PULL_REQUEST_BASE_BRANCH};
         fi
       - source zephyr-env.sh
-      - ccache -c -s --max-size=2000M
+      - ccache -c -s --max-size=5000M
       - >
-          if [ "$MATRIX_BUILD" = "4" -a "$IS_PULL_REQUEST" = "true" ]; then
+          if [ "$MATRIX_BUILD" = "5" -a "$IS_PULL_REQUEST" = "true" ]; then
             export COMMIT_RANGE=origin/${PULL_REQUEST_BASE_BRANCH}..HEAD
             echo "Building a Pull Request";
             echo "- Building Documentation";
@@ -46,9 +47,9 @@ build:
               echo "Documentation build failed";
               exit 1;
             fi
-            if [ -s doc/doc.warnings ]; then
+            if [ -s doc/_build/doc.warnings ]; then
               echo " => New documentation warnings/errors";
-              cp doc/doc.warnings doc.warnings
+              cp doc/_build/doc.warnings doc.warnings
             fi;
             echo "- Verify commit message, coding style, doc build";
             ./scripts/ci/check-compliance.py --commits ${COMMIT_RANGE} || true;
@@ -59,19 +60,19 @@ build:
             ./scripts/ci/get_modified_boards.py --commits origin/${PULL_REQUEST_BASE_BRANCH}..HEAD > modified_boards.args;
 
             if [ -s modified_boards.args ]; then
-              ./scripts/sanitycheck ${SANITYCHECK_OPTIONS} +modified_boards.args --save-tests test_file.txt;
+              ./scripts/sanitycheck ${SANITYCHECK_OPTIONS} +modified_boards.args --save-tests test_file.txt || exit 1;
             fi;
             if [ -s modified_tests.args ]; then
-              ./scripts/sanitycheck ${SANITYCHECK_OPTIONS} +modified_tests.args --save-tests test_file.txt;
+              ./scripts/sanitycheck ${SANITYCHECK_OPTIONS} +modified_tests.args --save-tests test_file.txt || exit 1;
             fi;
             rm -f modified_tests.args modified_boards.args;
           fi;
-      - ./scripts/sanitycheck ${SANITYCHECK_OPTIONS} --save-tests test_file.txt
+      - ./scripts/sanitycheck ${SANITYCHECK_OPTIONS} --save-tests test_file.txt || exit 1
       - ./scripts/sanitycheck ${SANITYCHECK_OPTIONS} --load-tests test_file.txt --subset ${MATRIX_BUILD}/${MATRIX_BUILDS} || ./scripts/sanitycheck ${SANITYCHECK_OPTIONS_RETRY} || ./scripts/sanitycheck ${SANITYCHECK_OPTIONS_RETRY}
       - rm test_file.txt
       - ccache -s
     on_failure:
-      - rm -rf ccache
+      - rm -rf ccache $HOME/.cache/zephyr
       - mkdir -p shippable/testresults
       - mkdir -p shippable/codecoverage
       - source zephyr-env.sh
@@ -79,11 +80,11 @@ build:
          if [ "$MATRIX_BUILD" = "1" ]; then
             gcovr -r ${ZEPHYR_BASE} -x > shippable/codecoverage/coverage.xml;
             lcov --capture --directory sanity-out/native_posix/ --directory sanity-out/unit_testing/ --output-file lcov.pre.info -q --rc lcov_branch_coverage=1;
-            lcov -q --remove lcov.pre.info *generated* -o lcov.info --rc lcov_branch_coverage=1;
+            lcov -q --remove lcov.pre.info mylib.c --remove lcov.pre.info tests/\* --remove lcov.pre.info samples/\* --remove lcov.pre.info ext/\* --remove lcov.pre.info *generated* -o lcov.info --rc lcov_branch_coverage=1;
             rm lcov.pre.info;
             rm -rf sanity-out out-2nd-pass;
             bash <(curl -s https://codecov.io/bash) -f "lcov.info" -X coveragepy -X fixes;
-            rm lcov.info;
+            rm -f lcov.info;
          else
             rm -rf sanity-out out-2nd-pass;
          fi;
@@ -96,7 +97,7 @@ build:
             cp ./scripts/sanity_chk/last_sanity.xml shippable/testresults/;
           fi;
     on_success:
-      - rm -rf ccache
+      - rm -rf ccache $HOME/.cache/zephyr
       - mkdir -p shippable/testresults
       - mkdir -p shippable/codecoverage
       - source zephyr-env.sh
@@ -104,11 +105,11 @@ build:
          if [ "$MATRIX_BUILD" = "1" ]; then
             gcovr -r ${ZEPHYR_BASE} -x > shippable/codecoverage/coverage.xml;
             lcov --capture --directory sanity-out/native_posix/ --directory sanity-out/unit_testing/ --output-file lcov.pre.info -q --rc lcov_branch_coverage=1;
-            lcov -q --remove lcov.pre.info *generated* -o lcov.info --rc lcov_branch_coverage=1;
+            lcov -q --remove lcov.pre.info mylib.c --remove lcov.pre.info tests/\* --remove lcov.pre.info samples/\* --remove lcov.pre.info ext/\* --remove lcov.pre.info *generated* -o lcov.info --rc lcov_branch_coverage=1;
             rm lcov.pre.info;
             rm -rf sanity-out out-2nd-pass;
             bash <(curl -s https://codecov.io/bash) -f "lcov.info" -X coveragepy -X fixes;
-            rm lcov.info;
+            rm -f lcov.info;
          else
             rm -rf sanity-out out-2nd-pass;
          fi;

.uncrustify.cfg

@@ -0,0 +1,79 @@
+indent_with_tabs    = 2     # 1=indent to level only, 2=indent with tabs
+input_tab_size      = 8     # original tab size
+output_tab_size     = 8     # new tab size
+indent_columns      = output_tab_size
+indent_label        = 1     # pos: absolute col, neg: relative column
+indent_switch_case  = 0     # number
+
+#
+# inter-symbol newlines
+#
+
+nl_enum_brace       = remove    # "enum {" vs "enum \n {"
+nl_union_brace      = remove    # "union {" vs "union \n {"
+nl_struct_brace     = remove    # "struct {" vs "struct \n {"
+nl_do_brace         = remove    # "do {" vs "do \n {"
+nl_if_brace         = remove    # "if () {" vs "if () \n {"
+nl_for_brace        = remove    # "for () {" vs "for () \n {"
+nl_else_brace       = remove    # "else {" vs "else \n {"
+nl_while_brace      = remove    # "while () {" vs "while () \n {"
+nl_switch_brace     = remove    # "switch () {" vs "switch () \n {"
+nl_brace_while      = remove    # "} while" vs "} \n while" - cuddle while
+nl_brace_else       = remove    # "} \n else" vs "} else"
+nl_func_var_def_blk = 1
+nl_fcall_brace      = remove    # "list_for_each() {" vs "list_for_each()\n{"
+nl_fdef_brace       = add       # "int foo() {" vs "int foo()\n{"
+
+#
+# Source code modifications
+#
+
+mod_paren_on_return = ignore    # "return 1;" vs "return (1);"
+mod_full_brace_if   = add       # "if() { } else { }" vs "if() else"
+
+#
+# inter-character spacing options
+#
+
+sp_sizeof_paren     = remove    # "sizeof (int)" vs "sizeof(int)"
+sp_before_sparen    = force     # "if (" vs "if("
+sp_after_sparen     = force     # "if () {" vs "if (){"
+sp_inside_braces    = add       # "{ 1 }" vs "{1}"
+sp_inside_braces_struct = add   # "{ 1 }" vs "{1}"
+sp_inside_braces_enum   = add   # "{ 1 }" vs "{1}"
+sp_assign           = add
+sp_arith            = add
+sp_bool             = add
+sp_compare          = add
+sp_assign           = add
+sp_after_comma      = add
+sp_func_def_paren   = remove    # "int foo (){" vs "int foo(){"
+sp_func_call_paren  = remove    # "foo (" vs "foo("
+sp_func_proto_paren = remove    # "int foo ();" vs "int foo();"
+sp_else_brace       = add       # ignore/add/remove/force
+sp_before_ptr_star  = add       # ignore/add/remove/force
+sp_after_ptr_star   = remove    # ignore/add/remove/force
+sp_between_ptr_star = remove    # ignore/add/remove/force
+sp_inside_paren     = remove    # remove spaces inside parens
+sp_paren_paren      = remove    # remove spaces between nested parens
+sp_inside_sparen    = remove    # remove spaces inside parens for if, while and the like
+sp_brace_else       = add       # ignore/add/remove/force
+sp_before_nl_cont   = ignore
+sp_cmt_cpp_start    = add
+sp_brace_typedef    = add       # }typedefd_name -> } typedefd_name
+
+cmt_sp_after_star_cont          = 1
+#
+# Aligning stuff
+#
+
+align_with_tabs     = FALSE     # use tabs to align
+align_on_tabstop    = TRUE      # align on tabstops
+align_enum_equ_span = 4         # '=' in enum definition
+align_struct_init_span  = 0     # align stuff in a structure init '= { }'
+align_right_cmt_span    = 3
+align_nl_cont	    = TRUE
+
+
+
+sp_pp_concat                              = ignore      # ignore/add/remove/force

CMakeLists.txt

@@ -1,3 +1,13 @@
+if(NOT DEFINED ZEPHYR_BINARY_DIR)
+  message(FATAL_ERROR "A user error has occured.
+cmake was invoked with '${CMAKE_CURRENT_LIST_DIR}' specified as the source directory,
+but it must be invoked with an application source directory,
+such as '${CMAKE_CURRENT_LIST_DIR}/samples/hello_world'.
+Debug variables:
+CMAKE_CACHEFILE_DIR: ${CMAKE_CACHEFILE_DIR}
+")
+endif()
+
 project(Zephyr-Kernel VERSION ${PROJECT_VERSION})
 enable_language(C CXX ASM)
 
@@ -56,12 +66,18 @@ zephyr_compile_definitions(
   __ZEPHYR__=1
 )
 
-if(NOT CONFIG_COVERAGE)
+if(NOT CONFIG_NO_OPTIMIZATIONS)
 zephyr_compile_definitions(
   _FORTIFY_SOURCE=2
 )
 endif()
 
+if(BUILD_VERSION)
+  zephyr_compile_definitions(
+    BUILD_VERSION=${BUILD_VERSION}
+  )
+endif()
+
 # We need to set an optimization level.
 # Default to -Os
 # unless CONFIG_NO_OPTIMIZATIONS is set, then it is -O0
@@ -75,11 +91,14 @@ endif()
 set_ifndef(OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG "-O0")
 set_ifndef(OPTIMIZE_FOR_DEBUG_FLAG            "-Og")
 set_ifndef(OPTIMIZE_FOR_SIZE_FLAG             "-Os")
+set_ifndef(OPTIMIZE_FOR_SPEED_FLAG            "-O2")
 
 if(CONFIG_NO_OPTIMIZATIONS)
   set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG})
 elseif(CONFIG_DEBUG_OPTIMIZATIONS)
   set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_DEBUG_FLAG})
+elseif(CONFIG_SPEED_OPTIMIZATIONS)
+  set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_SPEED_FLAG})
 elseif(CONFIG_SIZE_OPTIMIZATIONS)
   set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_SIZE_FLAG}) # Default
 else()
@@ -97,11 +116,10 @@ zephyr_compile_options(
   -ffreestanding
   -Wno-main
   ${NOSTDINC_F}
+  ${TOOLCHAIN_C_FLAGS}
 )
 
 zephyr_compile_options(
-  $<$<COMPILE_LANGUAGE:C>:-std=c99>
-
   $<$<COMPILE_LANGUAGE:CXX>:-std=c++11>
   $<$<COMPILE_LANGUAGE:CXX>:-fcheck-new>
   $<$<COMPILE_LANGUAGE:CXX>:-ffunction-sections>
@@ -205,13 +223,22 @@ if(CONFIG_OVERRIDE_FRAME_POINTER_DEFAULT)
   endif()
 endif()
 
-zephyr_compile_options(${CONFIG_COMPILER_OPT})
+separate_arguments(CONFIG_COMPILER_OPT_AS_LIST UNIX_COMMAND ${CONFIG_COMPILER_OPT})
+zephyr_compile_options(${CONFIG_COMPILER_OPT_AS_LIST})
 
 # TODO: Include arch compiler options at this point.
 
-# TODO: This Clang check is broken
 if(CMAKE_C_COMPILER_ID STREQUAL "Clang")
   zephyr_cc_option(
+    #FIXME: need to fix all of those
+    -Wno-sometimes-uninitialized
+    -Wno-shift-overflow
+    -Wno-missing-braces
+    -Wno-self-assign
+    -Wno-address-of-packed-member
+    -Wno-unused-function
+    -Wno-initializer-overrides
+    -Wno-section
     -Wno-unknown-warning-option
     -Wno-unused-variable
     -Wno-format-invalid-specifier
@@ -224,12 +251,12 @@ else() # GCC assumed
     -Wno-unused-but-set-variable
     -fno-reorder-functions
     )
+
   if(NOT ${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "xcc")
     zephyr_cc_option(-fno-defer-pop)
   endif()
 endif()
 
-zephyr_cc_option_ifdef(CONFIG_DEBUG_SECTION_MISMATCH -fno-inline-functions-called-once)
 zephyr_cc_option_ifdef(CONFIG_STACK_USAGE            -fstack-usage)
 
 zephyr_system_include_directories(${NOSTDINC})
@@ -259,11 +286,9 @@ zephyr_ld_options(
 
 if(CONFIG_HAVE_CUSTOM_LINKER_SCRIPT)
   set(LINKER_SCRIPT ${APPLICATION_SOURCE_DIR}/${CONFIG_CUSTOM_LINKER_SCRIPT})
-  if(NOT EXISTS LINKER_SCRIPT)
+  if(NOT EXISTS ${LINKER_SCRIPT})
     set(LINKER_SCRIPT ${CONFIG_CUSTOM_LINKER_SCRIPT})
-    if(NOT EXISTS LINKER_SCRIPT)
-      message(FATAL_ERROR "CONFIG_HAVE_CUSTOM_LINKER_SCRIPT was set, but no linker script was found at '${CONFIG_CUSTOM_LINKER_SCRIPT}'")
-    endif()
+    assert_exists(CONFIG_CUSTOM_LINKER_SCRIPT)
   endif()
 else()
   # Try a board specific linker file
@@ -322,27 +347,103 @@ add_custom_target(syscall_macros_h_target DEPENDS ${syscall_macros_h})
 add_custom_command(                       OUTPUT  ${syscall_macros_h}
   COMMAND
   ${PYTHON_EXECUTABLE}
-  ${PROJECT_SOURCE_DIR}/scripts/gen_syscall_header.py
+  ${ZEPHYR_BASE}/scripts/gen_syscall_header.py
   > ${syscall_macros_h}
-  DEPENDS ${PROJECT_SOURCE_DIR}/scripts/gen_syscall_header.py
+  DEPENDS ${ZEPHYR_BASE}/scripts/gen_syscall_header.py
   )
 
-# This command is a hack to support commands that are always run. Any
-# target that depends on always_rebuild will always be rebuilt.
-add_custom_command(OUTPUT always_rebuild COMMAND cmake -E echo Building for board ${BOARD})
 
 set(syscall_list_h ${CMAKE_CURRENT_BINARY_DIR}/include/generated/syscall_list.h)
 set(syscalls_json  ${CMAKE_CURRENT_BINARY_DIR}/misc/generated/syscalls.json)
 
+# The syscalls subdirs txt file is constructed by python containing a list of folders to use for
+# dependency handling, including empty folders.
+# Windows:  The list is used to specify DIRECTORY list with CMAKE_CONFIGURE_DEPENDS attribute.
+# Other OS: The list will update whenever a file is added/removed/modified and ensure a re-build.
+set(syscalls_subdirs_txt ${CMAKE_CURRENT_BINARY_DIR}/misc/generated/syscalls_subdirs.txt)
+
+# As syscalls_subdirs_txt is updated whenever a file is modified, this file can not be used for
+# monitoring of added / removed folders. A trigger file is thus used for correct dependency
+# handling. The trigger file will update when a folder is added / removed.
+set(syscalls_subdirs_trigger ${CMAKE_CURRENT_BINARY_DIR}/misc/generated/syscalls_subdirs.trigger)
+
+if(NOT (${CMAKE_HOST_SYSTEM_NAME} STREQUAL Windows))
+  set(syscalls_links --create-links ${CMAKE_CURRENT_BINARY_DIR}/misc/generated/syscalls_links)
+endif()
+
+# When running CMake it must be ensured that all dependencies are correctly acquired.
+execute_process(
+  COMMAND
+  ${PYTHON_EXECUTABLE}
+  ${ZEPHYR_BASE}/scripts/subfolder_list.py
+  --directory        ${ZEPHYR_BASE}/include      # Walk this directory
+  --out-file         ${syscalls_subdirs_txt}     # Write file with discovered folder
+  --trigger          ${syscalls_subdirs_trigger} # Trigger file that is used for json generation
+  ${syscalls_links}                              # If defined, create symlinks for dependencies
+)
+file(STRINGS ${syscalls_subdirs_txt} PARSE_SYSCALLS_PATHS_DEPENDS)
+
+if(${CMAKE_HOST_SYSTEM_NAME} STREQUAL Windows)
+  # On windows only adding/removing files or folders will be reflected in depends.
+  # Hence adding a file requires CMake to re-run to add this file to the file list.
+  set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${PARSE_SYSCALLS_PATHS_DEPENDS})
+
+  # Also On Windows each header file must be monitored as file modifications are not reflected
+  # on directory level.
+  file(GLOB_RECURSE PARSE_SYSCALLS_HEADER_DEPENDS ${ZEPHYR_BASE}/include/*.h)
+else()
+  # The syscall parsing depends on the folders in order to detect add/removed/modified files.
+  # When a folder is removed, CMake will try to find a target that creates that dependency.
+  # This command sets up the target for CMake to find.
+  # Without this code, CMake will fail with the following error:
+  #   <folder> needed by '<target>', missing and no known rule to make it
+  # when a folder is removed.
+  add_custom_command(OUTPUT ${PARSE_SYSCALLS_PATHS_DEPENDS}
+    COMMAND ${CMAKE_COMMAND} -E echo ""
+    COMMENT "Preparing syscall dependency handling"
+  )
+
+  add_custom_command(
+    OUTPUT
+    ${syscalls_subdirs_trigger}
+    COMMAND
+    ${PYTHON_EXECUTABLE}
+    ${ZEPHYR_BASE}/scripts/subfolder_list.py
+    --directory        ${ZEPHYR_BASE}/include      # Walk this directory
+    --out-file         ${syscalls_subdirs_txt}     # Write file with discovered folder
+    --trigger          ${syscalls_subdirs_trigger} # Trigger file that is used for json generation
+    ${syscalls_links}                              # If defined, create symlinks for dependencies
+    DEPENDS ${PARSE_SYSCALLS_PATHS_DEPENDS}
+  )
+
+  # Ensure subdir file always exists when specifying CMake dependency.
+  if(NOT EXISTS ${syscalls_subdirs_txt})
+    file(WRITE ${syscalls_subdirs_txt} "")
+  endif()
+
+  # On other OS'es, modifying a file is reflected on the folder timestamp and hence detected
+  # when using depend on directory level.
+  # Thus CMake only needs to re-run when sub-directories are added / removed, which is indicated
+  # using a trigger file.
+  set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${syscalls_subdirs_txt})
+endif()
+
+# SYSCALL_INCLUDE_DIRECTORY will include the directories that needs to be
+# searched for syscall declarations if CONFIG_APPLICATION_DEFINED_SYSCALL is set
+if(CONFIG_APPLICATION_DEFINED_SYSCALL)
+  set(SYSCALL_INCLUDE_DIRECTORY --include ${APPLICATION_SOURCE_DIR})
+endif()
+
 add_custom_command(
   OUTPUT
   ${syscalls_json}
   COMMAND
   ${PYTHON_EXECUTABLE}
-  ${PROJECT_SOURCE_DIR}/scripts/parse_syscalls.py
-  --include          ${PROJECT_SOURCE_DIR}/include        # Read files from this dir
-  --json-file        ${syscalls_json}                     # Write this file
-  DEPENDS always_rebuild
+  ${ZEPHYR_BASE}/scripts/parse_syscalls.py
+   --include          ${ZEPHYR_BASE}/include        # Read files from this dir
+  ${SYSCALL_INCLUDE_DIRECTORY}
+  --json-file        ${syscalls_json}              # Write this file
+  DEPENDS ${syscalls_subdirs_trigger} ${PARSE_SYSCALLS_HEADER_DEPENDS}
   )
 
 add_custom_target(syscall_list_h_target DEPENDS                ${syscall_list_h})
@@ -350,15 +451,30 @@ add_custom_command(OUTPUT include/generated/syscall_dispatch.c ${syscall_list_h}
   # Also, some files are written to include/generated/syscalls/
   COMMAND
   ${PYTHON_EXECUTABLE}
-  ${PROJECT_SOURCE_DIR}/scripts/gen_syscalls.py
+  ${ZEPHYR_BASE}/scripts/gen_syscalls.py
   --json-file        ${syscalls_json}                     # Read this file
   --base-output      include/generated/syscalls           # Write to this dir
   --syscall-dispatch include/generated/syscall_dispatch.c # Write this file
-  > ${syscall_list_h}                                     # Write stdout to this file
+  --syscall-list     ${syscall_list_h}
   WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
   DEPENDS ${syscalls_json}
   )
 
+set(DRV_VALIDATION ${PROJECT_BINARY_DIR}/include/generated/driver-validation.h)
+add_custom_command(
+  OUTPUT ${DRV_VALIDATION}
+  COMMAND
+  ${PYTHON_EXECUTABLE}
+  ${ZEPHYR_BASE}/scripts/gen_kobject_list.py
+  --validation-output ${DRV_VALIDATION}
+  $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
+  WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
+  )
+add_custom_target(driver_validation_h_target DEPENDS ${DRV_VALIDATION})
+
+include($ENV{ZEPHYR_BASE}/cmake/kobj.cmake)
+gen_kobj(KOBJ_INCLUDE_PATH)
+
 # Generate offsets.c.obj from offsets.c
 # Generate offsets.h     from offsets.c.obj
 
@@ -371,6 +487,8 @@ target_link_libraries(offsets zephyr_interface)
 add_dependencies(     offsets
   syscall_list_h_target
   syscall_macros_h_target
+  driver_validation_h_target
+  kobj_types_h_target
   )
 
 add_custom_command(
@@ -500,20 +618,22 @@ if(CONFIG_APPLICATION_MEMORY)
     list(APPEND ks ${fixed_path})
   endforeach()
 
-  # We are done constructing kernel_object_file_list, now we inject this
-  # information into the linker script through -D's
-  list(LENGTH kernel_object_file_list NUM_KERNEL_OBJECT_FILES)
-  list(APPEND LINKER_SCRIPT_DEFINES -DNUM_KERNEL_OBJECT_FILES=${NUM_KERNEL_OBJECT_FILES})
-  set(i 0)
+  # We are done constructing kernel_object_file_list, now we inject
+  # this list into the linker script through the define
+  # KERNELSPACE_OBJECT_FILES
+  set(def -DKERNELSPACE_OBJECT_FILES=)
   foreach(f ${ks})
-    list(APPEND LINKER_SCRIPT_DEFINES -DKERNEL_OBJECT_FILE_${i}=${f})
-    math(EXPR i "${i}+1")
+    set(def "${def} ${f}")
   endforeach()
+  list(APPEND LINKER_SCRIPT_DEFINES ${def})
 endif() # CONFIG_APPLICATION_MEMORY
 
 # Declare MPU userspace dependencies before the linker scripts to make
 # sure the order of dependencies are met
 if(CONFIG_CPU_HAS_MPU AND CONFIG_USERSPACE)
+	if(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT AND CONFIG_APP_SHARED_MEM )
+    set(APP_SMEM_DEP app_smem_linker)
+  endif()
   if(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT AND CONFIG_APPLICATION_MEMORY)
     set(ALIGN_SIZING_DEP app_sizing_prebuilt linker_app_sizing_script)
   endif()
@@ -579,6 +699,7 @@ add_custom_target(
   linker_script
   DEPENDS
   ${ALIGN_SIZING_DEP} ${PRIV_STACK_DEP}
+  ${APP_SMEM_DEP}
   linker.cmd
   offsets_h
   )
@@ -596,26 +717,29 @@ set_property(TARGET
   ${ZEPHYR_INCLUDE_DIRS}
   )
 
-get_property(E_KERNEL_ENTRY GLOBAL PROPERTY E_KERNEL_ENTRY)
-
 set(zephyr_lnk
   ${LINKERFLAGPREFIX},-Map=${PROJECT_BINARY_DIR}/${KERNEL_MAP_NAME}
   -u_OffsetAbsSyms
   -u_ConfigAbsSyms
-  ${E_KERNEL_ENTRY}
-  ${LINKERFLAGPREFIX},--start-group
   ${LINKERFLAGPREFIX},--whole-archive
   ${ZEPHYR_LIBS_PROPERTY}
   ${LINKERFLAGPREFIX},--no-whole-archive
   kernel
   ${OFFSETS_O_PATH}
-  ${LINKERFLAGPREFIX},--end-group
   ${LIB_INCLUDE_DIR}
   -L${PROJECT_BINARY_DIR}
   ${TOOLCHAIN_LIBS}
   )
 
 if(CONFIG_GEN_ISR_TABLES)
+  if(CONFIG_GEN_SW_ISR_TABLE)
+    list(APPEND GEN_ISR_TABLE_EXTRA_ARG --sw-isr-table)
+  endif()
+
+  if(CONFIG_GEN_IRQ_VECTOR_TABLE)
+    list(APPEND GEN_ISR_TABLE_EXTRA_ARG --vector-table)
+  endif()
+
   # isr_tables.c is generated from zephyr_prebuilt by
   # gen_isr_tables.py
   add_custom_command(
@@ -632,8 +756,7 @@ if(CONFIG_GEN_ISR_TABLES)
     --kernel $<TARGET_FILE:zephyr_prebuilt>
     --intlist isrList.bin
     $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--debug>
-    --sw-isr-table
-    --vector-table
+    ${GEN_ISR_TABLE_EXTRA_ARG}
     DEPENDS zephyr_prebuilt
     )
   set_property(GLOBAL APPEND PROPERTY GENERATED_KERNEL_SOURCE_FILES isr_tables.c)
@@ -679,7 +802,7 @@ if(CONFIG_ARM AND CONFIG_USERSPACE)
     ${GPERF} -C
     --output-file ${PRIV_STACKS_OUTPUT_SRC_PRE}
     ${PRIV_STACKS}
-    DEPENDS priv_stacks
+    DEPENDS priv_stacks ${PRIV_STACKS}
     WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
     )
   add_custom_target(priv_stacks_output_src_pre DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${PRIV_STACKS_OUTPUT_SRC_PRE})
@@ -692,12 +815,13 @@ if(CONFIG_ARM AND CONFIG_USERSPACE)
   add_custom_command(
     OUTPUT ${PRIV_STACKS_OUTPUT_SRC}
     COMMAND
+    ${PYTHON_EXECUTABLE}
     ${PROCESS_PRIV_STACKS_GPERF}
     -i ${PRIV_STACKS_OUTPUT_SRC_PRE}
     -o ${PRIV_STACKS_OUTPUT_SRC}
     -p "struct _k_priv_stack_map"
     $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
-    DEPENDS priv_stacks_output_src_pre
+    DEPENDS priv_stacks_output_src_pre ${PRIV_STACKS_OUTPUT_SRC_PRE}
     WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
     )
   add_custom_target(priv_stacks_output_src DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${PRIV_STACKS_OUTPUT_SRC})
@@ -777,7 +901,7 @@ if(CONFIG_USERSPACE)
     ${PYTHON_EXECUTABLE}
     ${GEN_KOBJ_LIST}
     --kernel $<TARGET_FILE:zephyr_prebuilt>
-    --output ${OBJ_LIST}
+    --gperf-output ${OBJ_LIST}
     $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
     DEPENDS zephyr_prebuilt
     WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
@@ -805,6 +929,7 @@ if(CONFIG_USERSPACE)
   add_custom_command(
     OUTPUT ${OUTPUT_SRC}
     COMMAND
+    ${PYTHON_EXECUTABLE}
     ${PROCESS_GPERF}
     -i ${OUTPUT_SRC_PRE}
     -o ${OUTPUT_SRC}
@@ -873,12 +998,46 @@ get_property(GKSF GLOBAL PROPERTY GENERATED_KERNEL_SOURCE_FILES)
 get_property(TOPT GLOBAL PROPERTY TOPT)
 set_ifndef(  TOPT -T)
 
+get_property(CSTD GLOBAL PROPERTY CSTD)
+set_ifndef(CSTD c99)
+
+zephyr_compile_options(
+  $<$<COMPILE_LANGUAGE:C>:-std=${CSTD}>
+)
+
 configure_file(
      $ENV{ZEPHYR_BASE}/include/arch/arm/cortex_m/scripts/app_data_alignment.ld
      ${PROJECT_BINARY_DIR}/include/generated/app_data_alignment.ld)
 
+configure_file(
+     $ENV{ZEPHYR_BASE}/include/arch/arm/cortex_m/scripts/app_smem.ld
+     ${PROJECT_BINARY_DIR}/include/generated/app_smem.ld)
+
 if(CONFIG_CPU_HAS_MPU AND CONFIG_USERSPACE)
 
+    if(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT AND CONFIG_APP_SHARED_MEM)
+        set(APP_SMEM_LD "${PROJECT_BINARY_DIR}/include/generated/app_smem.ld")
+        set(OBJ_FILE_DIR "${PROJECT_BINARY_DIR}/../")
+
+        add_custom_target(
+          ${APP_SMEM_DEP} ALL
+          DEPENDS app
+          DEPENDS ${PRIV_STACK_DEP}
+         )
+
+        add_custom_command(
+          TARGET ${APP_SMEM_DEP}
+          COMMAND ${PYTHON_EXECUTABLE}
+          ${ZEPHYR_BASE}/scripts/gen_app_partitions.py
+          -d ${OBJ_FILE_DIR}
+          -o ${APP_SMEM_LD}
+          $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
+          WORKING_DIRECTORY ${PROJECT_BINARY_DIR}/
+          COMMENT "Generating power of 2 aligned app_smem linker section"
+         )
+  endif()
+
+
   if(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT AND CONFIG_APPLICATION_MEMORY)
 
     construct_add_custom_command_for_linker_pass(linker_app_sizing custom_command)
@@ -907,7 +1066,7 @@ if(CONFIG_CPU_HAS_MPU AND CONFIG_USERSPACE)
     add_executable(       app_sizing_prebuilt misc/empty_file.c)
     target_link_libraries(app_sizing_prebuilt ${TOPT} ${PROJECT_BINARY_DIR}/linker_app_sizing.cmd ${zephyr_lnk})
     set_property(TARGET   app_sizing_prebuilt PROPERTY LINK_DEPENDS ${PROJECT_BINARY_DIR}/linker_app_sizing.cmd)
-    add_dependencies(     app_sizing_prebuilt linker_app_sizing_script offsets)
+    add_dependencies(     app_sizing_prebuilt linker_app_sizing_script offsets )
 
     add_custom_command(
       TARGET app_sizing_prebuilt
@@ -1009,19 +1168,19 @@ list_append_ifdef(CONFIG_CHECK_LINK_MAP
 list_append_ifdef(
   CONFIG_BUILD_OUTPUT_HEX
   post_build_commands
-  COMMAND ${CMAKE_OBJCOPY} -S -Oihex   -R .comment -R COMMON -R .eh_frame  ${KERNEL_ELF_NAME}    ${KERNEL_HEX_NAME}
+  COMMAND ${CMAKE_OBJCOPY} -S -Oihex --gap-fill 0xFF  -R .comment -R COMMON -R .eh_frame  ${KERNEL_ELF_NAME}    ${KERNEL_HEX_NAME}
   )
 
 list_append_ifdef(
   CONFIG_BUILD_OUTPUT_BIN
   post_build_commands
-  COMMAND ${CMAKE_OBJCOPY} -S -Obinary -R .comment -R COMMON -R .eh_frame  ${KERNEL_ELF_NAME}    ${KERNEL_BIN_NAME}
+  COMMAND ${CMAKE_OBJCOPY} -S -Obinary --gap-fill 0xFF -R .comment -R COMMON -R .eh_frame  ${KERNEL_ELF_NAME}    ${KERNEL_BIN_NAME}
   )
 
 list_append_ifdef(
   CONFIG_BUILD_OUTPUT_S19
   post_build_commands
-  COMMAND ${CMAKE_OBJCOPY} --srec-len 1 --output-target=srec ${KERNEL_ELF_NAME} ${KERNEL_S19_NAME}
+  COMMAND ${CMAKE_OBJCOPY} --gap-fill 0xFF --srec-len 1 --output-target=srec ${KERNEL_ELF_NAME} ${KERNEL_S19_NAME}
   )
 
 list_append_ifdef(
@@ -1067,7 +1226,7 @@ if(CONFIG_OUTPUT_PRINT_MEMORY_USAGE)
 
   set(SAVED_CMAKE_REQUIRED_FLAGS ${CMAKE_REQUIRED_FLAGS})
   set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} ${option}")
-  check_c_compiler_flag("" ${check})
+  zephyr_check_compiler_flag(C "" ${check})
   set(CMAKE_REQUIRED_FLAGS ${SAVED_CMAKE_REQUIRED_FLAGS})
 
   target_link_libraries_ifdef(${check} zephyr_prebuilt ${option})
@@ -1090,11 +1249,11 @@ add_subdirectory(cmake/flash)
 add_subdirectory(cmake/usage)
 add_subdirectory(cmake/reports)
 
-if(CONFIG_ASSERT)
+if(CONFIG_ASSERT AND (NOT CONFIG_FORCE_NO_ASSERT))
   message(WARNING "
       ------------------------------------------------------------
       --- WARNING:  __ASSERT() statements are globally ENABLED ---
-      --- The kernel will run more slowly and uses more memory ---
+      --- The kernel will run more slowly and use more memory  ---
       ------------------------------------------------------------"
 )
 endif()

CODEOWNERS

@@ -3,110 +3,108 @@
 # Do not use wildcard on all source yet
 # *                                        @galak @nashif
 
-# Get all docs reviewed
-*.rst                                    @dbkinder
 .known-issues/*                          @inakypg @nashif
-MAINTAINERS                              @inakypg @nashif
-arch/arc/*                               @cjordan44 @ruuddw
-arch/arc/core/*                          @andrewboie
-arch/arm/*                               @MaureenHelm @galak
+arch/arc/                                @vonhust @ruuddw
+arch/arm/                                @MaureenHelm @galak
 arch/arm/soc/arm/mps2/*                  @fvincenzo
 arch/arm/soc/atmel_sam/sam4s             @fallrisk
 arch/arm/soc/nxp*/                       @MaureenHelm
-arch/arm/soc/st_stm32/*                  @erwango
+arch/arm/soc/st_stm32/                   @erwango
 arch/arm/soc/st_stm32/stm32f4/*          @rsalveti @idlethread
 arch/arm/soc/ti_simplelink/cc32xx        @GAnthony
 arch/arm/soc/ti_simplelink/msp432p4xx    @Mani-Sadhasivam
-arch/nios2/*                             @andrewboie @ramakrishnapallala
-arch/nios2/core/*                        @andrewboie @ramakrishnapallala
-arch/posix/*                             @aescolar-ot
-arch/riscv32                             @fractalclone @kgugala @pgielda
-arch/x86/*                               @andrewboie @youvedeep
+arch/nios2/                              @andrewboie @ramakrishnapallala
+arch/posix/                              @aescolar
+arch/riscv32/                            @fractalclone @kgugala @pgielda
+arch/x86/                                @andrewboie @ramakrishnapallala
 arch/x86/core/*                          @andrewboie
-arch/x86/core/crt0.S                     @youvedeep @nashif
+arch/x86/core/crt0.S                     @ramakrishnapallala @nashif
 arch/x86/soc/intel_quark/quark_d2000/*   @nashif
 arch/x86/soc/intel_quark/quark_se/*      @nashif
 arch/x86/soc/intel_quark/quark_x1000/*   @nashif
-arch/xtensa/*                            @andrewboie @rgundi @andyross
-boards/arc/*                             @cjordan44 @ruuddw
+arch/xtensa/                             @andrewboie @rgundi @andyross
+boards/arc/                              @vonhust @ruuddw
 boards/arc/arduino_101_sss/*             @nashif
-boards/arc/em_starterkit/*               @cjordan44
+boards/arc/em_starterkit/*               @vonhust
 boards/arc/quark_se_c1000_ss_devboard/*  @nashif
 boards/arm/*                             @MaureenHelm @galak
-boards/arm/96b_carbon/*                  @rsalveti @idlethread
-boards/arm/96b_nitrogen/*                @idlethread
-boards/arm/96b_neonkey/*                 @Mani-Sadhasivam
-boards/arm/arduino_101_ble/*             @jhedberg
-boards/arm/cc3220sf_launchxl/*           @GAnthony
-boards/arm/disco_l475_iot1/*             @erwango
-boards/arm/frdm*/*                       @MaureenHelm
-boards/arm/hexiwear*/*                   @MaureenHelm
-boards/arm/lpcxpresso*/*                 @MaureenHelm
-boards/arm/mimxrt*/*                     @MaureenHelm
-boards/arm/mps2_an385/*                  @fvincenzo
-boards/arm/msp_exp432p401r_launchxl/*    @Mani-Sadhasivam
-boards/arm/nrf51_blenano/*               @rsalveti
-boards/arm/nrf52_pca10040/*              @carlescufi
-boards/arm/nucleo_f401re/*               @rsalveti @idlethread
-boards/arm/sam4s_xplained                @fallrisk
-boards/arm/v2m_beetle/*                  @fvincenzo
-boards/arm/olimexino_stm32/*             @ydamigos
-boards/arm/stm32f3_disco/*               @ydamigos
-boards/nios2/*                           @ramakrishnapallala
-boards/nios2/altera_max10/*              @ramakrishnapallala
-boards/posix/*                           @aescolar-ot
-boards/riscv32                           @fractalclone @kgugala @pgielda
-boards/x86/*                             @andrewboie @nashif
-boards/x86/arduino_101/*                 @nashif
-boards/x86/galileo/*                     @nashif
-boards/x86/quark_d2000_crb/*             @nashif
-boards/x86/quark_se_c1000_devboard/*     @nashif
-boards/xtensa/*                          @andrewboie @ramakrishnapallala
+boards/arm/96b_carbon/                   @rsalveti @idlethread
+boards/arm/96b_nitrogen/                 @idlethread
+boards/arm/96b_neonkey/                  @Mani-Sadhasivam
+boards/arm/cc3220sf_launchxl/            @GAnthony
+boards/arm/curie_ble/                    @jhedberg
+boards/arm/disco_l475_iot1/              @erwango
+boards/arm/frdm*/                        @MaureenHelm
+boards/arm/hexiwear*/                    @MaureenHelm
+boards/arm/lpcxpresso*/                  @MaureenHelm
+boards/arm/mimxrt*/                      @MaureenHelm
+boards/arm/mps2_an385/                   @fvincenzo
+boards/arm/msp_exp432p401r_launchxl/     @Mani-Sadhasivam
+boards/arm/nrf51_blenano/                @rsalveti
+boards/arm/nrf52_pca10040/               @carlescufi
+boards/arm/nucleo_f401re/                @rsalveti @idlethread
+boards/arm/sam4s_xplained/               @fallrisk
+boards/arm/v2m_beetle/                   @fvincenzo
+boards/arm/olimexino_stm32/              @ydamigos
+boards/arm/stm32f3_disco/                @ydamigos
+boards/nios2/                            @ramakrishnapallala
+boards/nios2/altera_max10/               @ramakrishnapallala
+boards/posix/                            @aescolar
+boards/riscv32/                          @fractalclone @kgugala @pgielda
+boards/x86/                              @andrewboie @nashif
+boards/x86/arduino_101/                  @nashif
+boards/x86/galileo/                      @nashif
+boards/x86/quark_d2000_crb/              @nashif
+boards/x86/quark_se_c1000_devboard/      @nashif
+boards/xtensa/                           @andrewboie @ramakrishnapallala
 # All cmake related files
-cmake/*                                  @nashif @SebastianBoe
+cmake/                                   @nashif @SebastianBoe
 /CMakeLists.txt                          @nashif @SebastianBoe
-doc/*                                    @dbkinder
-doc/subsystems/bluetooth/*               @sjanc @jhedberg @Vudentz
+doc/                                     @dbkinder
+doc/CMakeLists.txt                       @carlescufi
+doc/scripts/*                            @carlescufi
+doc/subsystems/bluetooth/                @sjanc @jhedberg @Vudentz
 drivers/*/*mcux*                         @MaureenHelm
 drivers/*/*qmsi*                         @nashif
 drivers/*/*stm32*                        @erwango
-drivers/*/*native_posix*                 @aescolar-ot
-drivers/adc/*                            @anangl
-drivers/bluetooth/*                      @sjanc @jhedberg @Vudentz
+drivers/*/*native_posix*                 @aescolar
+drivers/adc/                             @anangl
+drivers/bluetooth/                       @sjanc @jhedberg @Vudentz
 drivers/clock_control/*stm32f4*          @rsalveti @idlethread
-drivers/counter/*                        @anangl
-drivers/ethernet/*                       @jukkar @tbursztyka
-drivers/flash/*                          @nashif
+drivers/counter/                         @anangl
+drivers/ethernet/                        @jukkar @tbursztyka @pfalcon
+drivers/flash/                           @nashif
 drivers/flash/*stm32*                    @superna9999
 drivers/gpio/*stm32*                     @rsalveti @idlethread
 drivers/gpio/gpio_pulpino.c              @fractalclone @kgugala @pgielda
 drivers/ieee802154/*                     @jukkar @tbursztyka
 drivers/interrupt_controller/*           @andrewboie
+drivers/led/*                            @Mani-Sadhasivam
 drivers/led_strip/*                      @mbolivar
 drivers/pinmux/stm32/*                   @rsalveti @idlethread
-drivers/sensor/*                         @bogdan-davidoaia
-drivers/serial/uart_altera_jtag.c        @ramakrishnapallala
+drivers/sensor/                          @bogdan-davidoaia @MaureenHelm
+drivers/serial/uart_altera_jtag_hal.c    @ramakrishnapallala
 drivers/serial/uart_riscv_qemu.c         @fractalclone @kgugala @pgielda
-drivers/net/slip/*                       @jukkar @tbursztyka
+drivers/net/slip.c                       @jukkar @tbursztyka
 drivers/spi/*                            @tbursztyka
 drivers/spi/spi_ll_stm32.*               @superna9999
-drivers/timer/altera_avalon_timer.c      @ramakrishnapallala
+drivers/timer/altera_avalon_timer_hal.c  @ramakrishnapallala
 drivers/timer/pulpino_timer.c            @fractalclone @kgugala @pgielda
 drivers/timer/riscv_machine_timer.c      @fractalclone @kgugala @pgielda
-drivers/usb                              @youvedeep @andyross
+drivers/usb/                             @jfischer-phytec-iot @finikorg
 drivers/usb/device/usb_dc_stm32.c        @ydamigos @loicpoulain
 drivers/i2c/i2c_ll_stm32*                @ldts @ydamigos
-dts/arm/st/*                             @erwango
-ext/fs/*                                 @nashif @ramakrishnapallala
-ext/hal/cmsis/*                          @MaureenHelm @galak
-ext/hal/nordic/mdk/*                     @carlescufi
-ext/hal/nxp/mcux/*                       @MaureenHelm
-ext/hal/qmsi/*                           @nashif
-ext/hal/st/stm32cube/*                   @erwango
-ext/lib/crypto/mbedtls/*                 @nashif
-ext/lib/crypto/tinycrypt/*               @lpereira
+dts/arm/st/                              @erwango
+ext/fs/                                  @nashif @ramakrishnapallala
+ext/hal/cmsis/                           @MaureenHelm @galak
+ext/hal/nordic/                          @carlescufi @anangl
+ext/hal/nxp/                             @MaureenHelm
+ext/hal/qmsi/                            @nashif
+ext/hal/st/stm32cube/                    @erwango
+ext/lib/crypto/mbedtls/                  @nashif
+ext/lib/crypto/tinycrypt/                @lpereira
 include/adc.h                            @anangl
-include/arch/arc/*                       @cjordan44 @ruuddw
+include/arch/arc/*                       @vonhust @ruuddw
 include/arch/arc/arch.h                  @andrewboie
 include/arch/arc/v2/irq.h                @andrewboie
 include/arch/arm/*                       @MaureenHelm @galak
@@ -114,14 +112,14 @@ include/arch/arm/cortex_m/irq.h          @andrewboie
 include/arch/nios2/*                     @andrewboie
 include/arch/nios2/arch.h                @andrewboie
 include/arch/riscv32                     @fractalclone @kgugala @pgielda
-include/arch/x86/*                       @andrewboie @youvedeep
+include/arch/x86/*                       @andrewboie @ramakrishnapallala
 include/arch/x86/arch.h                  @andrewboie
 include/arch/xtensa/*                    @andrewboie
 include/atomic.h                         @andrewboie @andyross
 include/bluetooth/*                      @sjanc @jhedberg @Vudentz
 include/cache.h                          @andrewboie @andyross
 include/counter.h                        @anangl
-include/device.h                         @youvedeep @nashif
+include/device.h                         @ramakrishnapallala @nashif
 include/drivers/bluetooth/*              @sjanc @jhedberg @Vudentz
 include/drivers/ioapic.h                 @andrewboie
 include/drivers/loapic.h                 @andrewboie
@@ -133,6 +131,7 @@ include/irq.h                            @andrewboie @andyross
 include/irq_offload.h                    @andrewboie @andyross
 include/kernel.h                         @andrewboie @andyross
 include/kernel_version.h                 @andrewboie @andyross
+include/led.h                            @Mani-Sadhasivam
 include/led_strip.h                      @mbolivar
 include/linker/linker-defs.h             @andrewboie @andyross
 include/linker/linker-tool-gcc.h         @andrewboie @andyross
@@ -140,9 +139,9 @@ include/linker/linker-tool.h             @andrewboie @andyross
 include/linker/section_tags.h            @andrewboie @andyross
 include/linker/sections.h                @andrewboie @andyross
 include/misc/*                           @andrewboie @andyross
-include/net/*                            @jukkar @tbursztyka
-include/net/buf.h                        @jukkar @jhedberg @tbursztyka
-include/power.h                          @youvedeep @nashif
+include/net/*                            @jukkar @tbursztyka @pfalcon
+include/net/buf.h                        @jukkar @jhedberg @tbursztyka @pfalcon
+include/power.h                          @ramakrishnapallala @nashif
 include/sensor.h                         @bogdan-davidoaia
 include/shared_irq.h                     @andrewboie @andyross
 include/spi.h                            @tbursztyka
@@ -152,22 +151,23 @@ include/sys_io.h                         @andrewboie @andyross
 include/toolchain.h                      @andrewboie @andyross
 include/toolchain/*                      @andrewboie @andyross
 include/zephyr.h                         @andrewboie @andyross
-kernel/*                                 @andrewboie @andyross
-kernel/posix/*				 @youvedeep
-kernel/device.c                          @youvedeep @nashif
-kernel/idle.c                            @youvedeep @nashif
-samples/bluetooth/*                      @sjanc @jhedberg @Vudentz
-samples/boards/quark_se_c1000/power*/*   @youvedeep @nashif
-samples/net/*                            @jukkar @tbursztyka
-samples/net/dns_resolve/*                @jukkar @tbursztyka
+kernel/                                  @andrewboie @andyross
+lib/posix/                            	 @ramakrishnapallala @nniranjhana
+kernel/device.c                          @ramakrishnapallala @nashif
+kernel/idle.c                            @ramakrishnapallala @nashif
+samples/bluetooth/                       @sjanc @jhedberg @Vudentz
+samples/boards/quark_se_c1000/power*/*   @ramakrishnapallala @nashif
+samples/net/                             @jukkar @tbursztyka @pfalcon
+samples/net/dns_resolve/                 @jukkar @tbursztyka @pfalcon
 samples/net/http_server/*                @jukkar @tbursztyka
 samples/net/lwm2m_client/*               @mike-scott
 samples/net/mbedtls_sslclient/*          @jukkar
 samples/net/mqtt_publisher/*             @jukkar @tbursztyka
 samples/net/coap_client/*                @rveerama1
 samples/net/coap_server/*                @rveerama1
+samples/net/sockets/*                    @jukkar @tbursztyka @pfalcon
 samples/sensor/*                         @bogdan-davidoaia
-samples/subsys/usb                       @youvedeep @andyross
+samples/subsys/usb                       @jfischer-phytec-iot @finikorg
 scripts/expr_parser.py                   @andrewboie
 scripts/sanity_chk/*                     @andrewboie
 scripts/sanitycheck                      @andrewboie @nashif
@@ -175,24 +175,31 @@ scripts/support/runner/*                 @mbolivar
 subsys/bluetooth/*                       @sjanc @jhedberg @Vudentz
 subsys/bluetooth/controller/*            @carlescufi @cvinayak
 subsys/fs/*                              @nashif
-subsys/net/buf.c                         @jukkar @jhedberg @tbursztyka
-subsys/net/ip/*                          @jukkar @tbursztyka
-subsys/net/lib/*                         @jukkar @tbursztyka
-subsys/net/lib/dns/*                     @jukkar @tbursztyka
+subsys/net/buf.c                         @jukkar @jhedberg @tbursztyka @pfalcon
+subsys/net/ip/*                          @jukkar @tbursztyka @pfalcon
+subsys/net/lib/*                         @jukkar @tbursztyka @pfalcon
+subsys/net/lib/dns/*                     @jukkar @tbursztyka @pfalcon
 subsys/net/lib/http/*                    @jukkar @tbursztyka
 subsys/net/lib/lwm2m/*                   @mike-scott
 subsys/net/lib/mqtt/*                    @jukkar @tbursztyka
 subsys/net/lib/coap/*                    @rveerama1
-subsys/usb                               @youvedeep @andyross
-tests/bluetooth/*                        @sjanc @jhedberg @Vudentz
-tests/crypto/*                           @lpereira
-tests/crypto/mbedtls/*                   @nashif
-tests/drivers/spi/*                      @tbursztyka
-tests/kernel/*                           @andrewboie @andyross
-tests/net/*                              @jukkar @tbursztyka
-tests/net/buf/*                          @jukkar @jhedberg @tbursztyka
-tests/net/lib/*                          @jukkar @tbursztyka
-tests/net/lib/http_header_fields/*       @jukkar @tbursztyka
-tests/net/lib/mqtt_packet/*              @jukkar @tbursztyka
-tests/net/lib/coap/*                     @rveerama1
-tests/subsys/fs/*                        @nashif @ramakrishnapallala
+subsys/net/lib/sockets/*                 @jukkar @tbursztyka @pfalcon
+subsys/usb/                              @jfischer-phytec-iot @finikorg
+tests/boards/native_posix/*              @aescolar
+tests/bluetooth/                         @sjanc @jhedberg @Vudentz @tarunkum
+tests/posix/                             @nniranjhana
+tests/crypto/                            @lpereira @pswarnak
+tests/crypto/mbedtls/                    @nashif @lpereira
+tests/drivers/spi/                       @tbursztyka
+tests/kernel/                            @andrewboie @andyross @spoorthik @pswarnak @nniranjhana
+tests/net/                               @jukkar @tbursztyka @tarunkum @pfalcon
+tests/net/buf/                           @jukkar @jhedberg @tbursztyka @pfalcon
+tests/net/lib/                           @jukkar @tbursztyka @pfalcon
+tests/net/lib/http_header_fields/        @jukkar @tbursztyka
+tests/net/lib/mqtt_packet/               @jukkar @tbursztyka
+tests/net/lib/coap/                      @rveerama1
+tests/net/socket/                        @jukkar @tbursztyka @pfalcon
+tests/subsys/fs/                         @nashif @ramakrishnapallala
+
+# Get all docs reviewed
+*.rst                                    @dbkinder

CONTRIBUTING.rst

@@ -6,598 +6,34 @@ patches directly to the project.  In our collaborative open source environment,
 standards and methods for submitting changes help reduce the chaos that can result
 from an active development community.
 
-This document explains how to participate in project conversations, log bugs
-and enhancement requests, and submit patches to the project so your patch will
-be accepted quickly in the codebase.
+This document briefly summarizes the full `Contribution
+Guidelines <http://docs.zephyrproject.org/contribute/contribute.html>`_
+documentation.
 
-Licensing
-*********
+* Zephyr uses the permissive open source `Apache 2.0 license`_
+  that allows you to freely use, modify, distribute and sell your own products
+  that include Apache 2.0 licensed software.
 
-Licensing is very important to open source projects. It helps ensure the
-software continues to be available under the terms that the author desired.
+* There are some imported or reused components of the Zephyr project that
+  use other licensing and are clearly identified.
 
-.. _Apache 2.0 license:
-   https://github.com/zephyrproject-rtos/zephyr/blob/master/LICENSE
+* The Developer Certificate of Origin (DCO) process is followed to
+  ensure developers are following licensing criteria for their
+  contributions, and documented with a ``Signed-of-by`` line in commits.
 
-.. _GitHub repo: https://github.com/zephyrproject-rtos/zephyr
+* Zephyr development workflow is supported on Linux, macOS, and Windows,
+  (with a few exceptions).
 
-Zephyr uses the `Apache 2.0 license`_ (as found in the LICENSE file in
-the project's `GitHub repo`_) to strike a balance between open
-contribution and allowing you to use the software however you would like
-to.  The Apache 2.0 license is a permissive open source license that
-allows you to freely use, modify, distribute and sell your own products
-that include Apache 2.0 licensed software.  (For more information about
-this, check out articles such as `Why choose Apache 2.0 licensing`_ and
-`Top 10 Apache License Questions Answered`_).
+* Source code for the project is maintained in the GitHub repo:
+  https://github.com/zephyrproject-rtos/zephyr
 
-.. _Why choose Apache 2.0 licensing:
-   https://www.zephyrproject.org/about/#faq
+* Issue and feature tracking is done using GitHub issues in this repo.
 
-.. _Top 10 Apache License Questions Answered:
-   https://www.whitesourcesoftware.com/whitesource-blog/top-10-apache-license-questions-answered/
+* A Continuous Integration (CI) system runs on every Pull Request (PR)
+  to verify several aspects of the PR including Git commit formatting,
+  Coding Style, sanity checks builds, and documentation builds.
 
-A license tells you what rights you have as a developer, as provided by the
-copyright holder. It is important that the contributor fully understands the
-licensing rights and agrees to them. Sometimes the copyright holder isn't the
-contributor, such as when the contributor is doing work on behalf of a
-company.
+* The `Zephyr devel mailing list`_ is a great place to engage with the
+  community, ask questions, discuss issues, and help each other.
 
-Components using other Licenses
-===============================
-
-There are some imported or reused components of the Zephyr project that
-use other licensing, as described in `Zephyr Licensing`_.
-
-.. _Zephyr Licensing:
-   https://www.zephyrproject.org/doc/LICENSING.html
-
-Importing code into the Zephyr OS from other projects that use a license
-other than the Apache 2.0 license needs to be fully understood in
-context and approved by the Zephyr governing board.
-
-By carefully reviewing potential contributions and also enforcing a
-:ref:`DCO` for contributed code, we can ensure that
-the Zephyr community can develop products with the Zephyr Project
-without concerns over patent or copyright issues.
-
-See `Contributing non-Apache 2.0 components`_ for more information about
-this contributing and review process for imported components.
-
-.. _Contributing non-Apache 2.0 components:
-   https://www.zephyrproject.org/doc/contribute/contribute_non-apache.html
-
-.. _DCO:
-
-Developer Certification of Origin (DCO)
-***************************************
-
-To make a good faith effort to ensure licensing criteria are met, the Zephyr
-project requires the Developer Certificate of Origin (DCO) process to be
-followed.
-
-The DCO is an attestation attached to every contribution made by every
-developer. In the commit message of the contribution, (described more fully
-later in this document), the developer simply adds a ``Signed-off-by``
-statement and thereby agrees to the DCO.
-
-When a developer submits a patch, it is a commitment that the contributor has
-the right to submit the patch per the license.  The DCO agreement is shown
-below and at http://developercertificate.org/.
-
-.. code-block:: none
-
-    Developer's Certificate of Origin 1.1
-
-    By making a contribution to this project, I certify that:
-
-    (a) The contribution was created in whole or in part by me and I
-        have the right to submit it under the open source license
-        indicated in the file; or
-
-    (b) The contribution is based upon previous work that, to the
-        best of my knowledge, is covered under an appropriate open
-        source license and I have the right under that license to
-        submit that work with modifications, whether created in whole
-        or in part by me, under the same open source license (unless
-        I am permitted to submit under a different license), as
-        Indicated in the file; or
-
-    (c) The contribution was provided directly to me by some other
-        person who certified (a), (b) or (c) and I have not modified
-        it.
-
-    (d) I understand and agree that this project and the contribution
-        are public and that a record of the contribution (including
-        all personal information I submit with it, including my
-        sign-off) is maintained indefinitely and may be redistributed
-        consistent with this project or the open source license(s)
-        involved.
-
-DCO Sign-Off Methods
-====================
-
-The DCO requires a sign-off message in the following format appear on each
-commit in the pull request::
-
-   Signed-off-by: Zephyrus Zephyr <zephyrus@zephyrproject.org>
-
-The DCO text can either be manually added to your commit body, or you can add
-either ``-s`` or ``--signoff`` to your usual Git commit commands. If you forget
-to add the sign-off you can also amend a previous commit with the sign-off by
-running ``git commit --amend -s``. If you've pushed your changes to GitHub
-already you'll need to force push your branch after this with ``git push -f``.
-
-Prerequisites
-*************
-
-.. _Zephyr Project website: https://zephyrproject.org
-
-As a contributor, you'll want to be familiar with the Zephyr project, how to
-configure, install, and use it as explained in the `Zephyr Project website`_
-and how to set up your development environment as introduced in the Zephyr
-`Getting Started Guide`_.
-
-.. _Getting Started Guide:
-   https://www.zephyrproject.org/doc/getting_started/getting_started.html
-
-You should be familiar with common developer tools such as Git and CMake, and
-platforms such as GitHub.
-
-If you haven't already done so, you'll need to create a (free) GitHub account
-on http://github.com and have Git tools available on your development system.
-
-.. note::
-   The Zephyr development workflow supports all 3 major operating systems
-   (Linux, macOS, and Windows) but some of the tools used in the sections below
-   are only available on Linux and macOS. On Windows, instead of running these
-   tools yourself, you will need to rely on the Continuous Integration (CI)
-   service ``shippable``, which runs automatically on GitHub when you submit
-   your Pull Request (PR).  You can see any failure results in the Shippable
-   details link near the end of the PR conversation list. See
-   `Continuous Integration`_ for more information
-
-Repository layout
-*****************
-
-To clone the main Zephyr Project repository use::
-
-    git clone https://github.com/zephyrproject-rtos/zephyr
-
-The Zephyr project directory structure is described in `Source Tree Structure`_
-documentation. In addition to the Zephyr kernel itself, you'll also find the
-sources for technical documentation, sample code, supported board
-configurations, and a collection of subsystem tests.  All of these are
-available for developers to contribute to and enhance.
-
-.. _Source Tree Structure:
-   https://www.zephyrproject.org/doc/kernel/overview/source_tree.html
-
-Pull Requests and Issues
-************************
-
-.. _Zephyr Project Issues: https://github.com/zephyrproject-rtos/zephyr/issues
-
-.. _open pull requests: https://github.com/zephyrproject-rtos/zephyr/pulls
-
-.. _Zephyr-devel mailing list:
-   https://lists.zephyrproject.org/mailman/listinfo/zephyr-devel
-
-Before starting on a patch, first check in our issues `Zephyr Project Issues`_
-system to see what's been reported on the issue you'd like to address.  Have a
-conversation on the `Zephyr-devel mailing list`_ (or the #zephyrproject IRC
-channel on freenode.net) to see what others think of your issue (and proposed
-solution).  You may find others that have encountered the issue you're
-finding, or that have similar ideas for changes or additions.  Send a message
-to the `Zephyr-devel mailing list`_ to introduce and discuss your idea with
-the development community.
-
-Please note that it's common practice on IRC to be away from the
-channel, but still have a client logged in to receive traffic. If you
-ask a question to a particular person and they don't answer, **try
-to stay signed in to the channel** if you can, so they have time to
-respond to you. This is especially important given the many different
-timezones Zephyr developers live in. If you don't get a timely
-response on IRC, try sending a message to the mailing list instead.
-
-It's always a good practice to search for existing or related issues before
-submitting your own. When you submit an issue (bug or feature request), the
-triage team will review and comment on the submission, typically within a few
-business days.
-
-You can find all `open pull requests`_ on GitHub and open `Zephyr Project
-Issues`_ in Github issues.
-
- .. _Continuous Integration:
-
-Continuous Integration (CI)
-***************************
-
-The Zephyr Project operates a Continuous Integration (CI) system that runs on
-every Pull Request (PR) in order to verify several aspects of the PR:
-
-* Git commit formatting
-* Coding Style
-* Sanity Check builds for multiple architectures and boards
-* Documentation build to verify any doc changes
-
-CI is run on the ``shippable`` cloud service and it uses the same tools
-described in the `Contribution Tools`_ section.
-The CI results must be green indicating "All checks have passed" before
-the Pull Request can be merged.  CI is run when the PR is created, and
-again every time the PR is modified with a commit.  You can also force
-the CI system to recheck a PR by adding a comment to the PR saying
-simply ``retest`` in the message (helpful if the CI system fails unexpectedly).
-
-The current status of the CI run can always be found at the bottom of the
-GitHub PR page, below the review status. Depending on the success or failure
-of the run you will see:
-
-* "All checks have passed"
-* "All checks have failed"
-
-In case of failure you can click on the "Details" link presented below the
-failure message in order to navigate to ``shippable`` and inspect the results.
-Once you click on the link you will be taken to the ``shippable`` summary
-results page where a table with all the different builds will be shown. To see
-what build or test failed click on the row that contains the failed (i.e.
-non-green) build and then click on the "Tests" tab to see the console output
-messages indicating the failure.
-
- .. _Contribution Tools:
-
-Contribution Tools and Git Setup
-********************************
-
-Signed-off-by
-=============
-
-The name in the commit message ``Signed-off-by:`` line and your email must
-match the change authorship information. Make sure your :file:`.gitconfig`
-is set up correctly:
-
-.. code-block:: console
-
-   git config --global user.name "David Developer"
-   git config --global user.email "david.developer@company.com"
-
-gitlint
-=======
-
-When you submit a pull request to the project, a series of checks are
-performed to verify your commit messages meet the requirements. The same step
-done during the CI process can be performed locally using the the `gitlint`
-command.
-
-Run `gitlint` locally in your tree and branch where your patches have been
-committed:
-
-.. code-block:: console
-
-     gitlint
-
-Note, gitlint only checks HEAD (the most recent commit), so you should run it
-after each commit, or use the ``--commits`` option to specify a commit range
-covering all the development patches to be submitted.
-
-sanitycheck
-===========
-
-.. note::
-   sanitycheck does not currently run on Windows.
-
-To verify that your changes did not break any tests or samples, please run the
-``sanitycheck`` script locally before submitting your pull request to GitHub. To
-run the same tests the CI system runs, follow these steps from within your
-local Zephyr source working directory:
-
-.. code-block:: console
-
-    source zephyr-env.sh
-    ./scripts/sanitycheck
-
-The above will execute the basic sanitycheck script, which will run various
-kernel tests using the QEMU emulator.  It will also do some build tests on
-various samples with advanced features that can't run in QEMU.
-
-We highly recommend you run these tests locally to avoid any CI
-failures.
-
-uncrustify
-==========
-
-The `uncrustify tool <https://sourceforge.net/projects/uncrustify>`_ can
-be helpful to quickly reformat your source code to our `Coding Style`_
-standards together with a configuration file we've provided:
-
-.. code-block:: bash
-
-   # On Linux/macOS
-   uncrustify --replace --no-backup -l C -c $ZEPHYR_BASE/scripts/uncrustify.cfg my_source_file.c
-   # On Windows
-   uncrustify --replace --no-backup -l C -c %ZEPHYR_BASE%\scripts\uncrustify.cfg my_source_file.c
-
-On Linux systems, you can install uncrustify with
-
-.. code-block:: bash
-
-   sudo apt install uncrustify
-
-For Windows installation instructions see the `sourceforge listing for
-uncrustify <https://sourceforge.net/projects/uncrustify>`_.
-
-Coding Style
-************
-
-Use these coding guidelines to ensure that your development complies with the
-project's style and naming conventions.
-
-.. _Linux kernel coding style:
-   https://kernel.org/doc/html/latest/process/coding-style.html
-
-In general, follow the `Linux kernel coding style`_, with the
-following exceptions:
-
-* Add braces to every ``if`` and ``else`` body, even for single-line code
-  blocks. Use the ``--ignore BRACES`` flag to make *checkpatch* stop
-  complaining.
-* Use spaces instead of tabs to align comments after declarations, as needed.
-* Use C89-style single line comments, ``/*  */``. The C99-style single line
-  comment, ``//``, is not allowed.
-* Use ``/**  */`` for doxygen comments that need to appear in the documentation.
-
-
-The Linux kernel GPL-licensed tool ``checkpatch`` is used to check
-coding style conformity.
-
-.. note::
-   checkpatch does not currently run on Windows.
-
-Checkpatch is available in the scripts directory. To invoke it when committing
-code, make the file *$ZEPHYR_BASE/.git/hooks/pre-commit* executable and edit
-it to contain:
-
-.. code-block:: bash
-
-    #!/bin/sh
-    set -e exec
-    exec git diff --cached | ${ZEPHYR_BASE}/scripts/checkpatch.pl -
-
-.. _Contribution workflow:
-
-Contribution Workflow
-*********************
-
-One general practice we encourage, is to make small,
-controlled changes. This practice simplifies review, makes merging and
-rebasing easier, and keeps the change history clear and clean.
-
-When contributing to the Zephyr Project, it is also important you provide as much
-information as you can about your change, update appropriate documentation,
-and test your changes thoroughly before submitting.
-
-The general GitHub workflow used by Zephyr developers uses a combination of
-command line Git commands and browser interaction with GitHub.  As it is with
-Git, there are multiple ways of getting a task done.  We'll describe a typical
-workflow here:
-
-.. _Create a Fork of Zephyr:
-   https://github.com/zephyrproject-rtos/zephyr#fork-destination-box
-
-#. `Create a Fork of Zephyr`_
-   to your personal account on GitHub. (Click on the fork button in the top
-   right corner of the Zephyr project repo page in GitHub.)
-
-#. On your development computer, clone the fork you just made::
-
-     git clone https://github.com/<your github id>/zephyr
-
-   This would be a good time to let Git know about the upstream repo too::
-
-     git remote add upstream https://github.com/zephyrproject-rtos/zephyr.git
-
-   and verify the remote repos::
-
-     git remote -v
-
-#. Create a topic branch (off of master) for your work (if you're addressing
-   an issue, we suggest including the issue number in the branch name)::
-
-     git checkout master
-     git checkout -b fix_comment_typo
-
-   Some Zephyr subsystems do development work on a separate branch from
-   master so you may need to indicate this in your checkout::
-
-     git checkout -b fix_out_of_date_patch origin/net
-
-#. Make changes, test locally, change, test, test again, ...  (Check out the
-   prior chapter on `sanitycheck`_ as well).
-
-#. When things look good, start the pull request process by adding your changed
-   files::
-
-     git add [file(s) that changed, add -p if you want to be more specific]
-
-   You can see files that are not yet staged using::
-
-     git status
-
-#. Verify changes to be committed look as you expected::
-
-     git diff --cached
-
-#. Commit your changes to your local repo::
-
-     git commit -s
-
-   The ``-s`` option automatically adds your ``Signed-off-by:`` to your commit
-   message.  Your commit will be rejected without this line that indicates your
-   agreement with the `DCO`_.  See the `Commit Guidelines`_ section for
-   specific guidelines for writing your commit messages.
-
-#. Push your topic branch with your changes to your fork in your personal
-   GitHub account::
-
-     git push origin fix_comment_typo
-
-#. In your web browser, go to your forked repo and click on the
-   ``Compare & pull request`` button for the branch you just worked on and
-   you want to open a pull request with.
-
-#. Review the pull request changes, and verify that you are opening a
-   pull request for the appropriate branch. The title and message from your
-   commit message should appear as well.
-
-#. If you're working on a subsystem branch that's not ``master``,
-   you may need to change the intended branch for the pull request
-   here, for example, by changing the base branch from ``master`` to ``net``.
-
-#. GitHub will assign one or more suggested reviewers (based on the
-   CODEOWNERS file in the repo). If you are a project member, you can
-   select additional reviewers now too.
-
-#. Click on the submit button and your pull request is sent and awaits
-   review.  Email will be sent as review comments are made, or you can check
-   on your pull request at https://github.com/zephyrproject-rtos/zephyr/pulls.
-
-#. While you're waiting for your pull request to be accepted and merged, you
-   can create another branch to work on another issue. (Be sure to make your
-   new branch off of master and not the previous branch.)::
-
-     git checkout master
-     git checkout -b fix_another_issue
-
-   and use the same process described above to work on this new topic branch.
-
-#. If reviewers do request changes to your patch, you can interactively rebase
-   commit(s) to fix review issues.  In your development repo::
-
-     git fetch --all
-     git rebase --ignore-whitespace upstream/master
-
-   The ``--ignore-whitespace`` option stops ``git apply`` (called by rebase)
-   from changing any whitespace. Continuing::
-
-     git rebase -i <offending-commit-id>^
-
-   In the interactive rebase editor, replace ``pick`` with ``edit`` to select
-   a specific commit (if there's more than one in your pull request), or
-   remove the line to delete a commit entirely.  Then edit files to fix the
-   issues in the review.
-
-   As before, inspect and test your changes. When ready, continue the
-   patch submission::
-
-     git add [file(s)]
-     git rebase --continue
-
-   Update commit comment if needed, and continue::
-
-     git push --force origin fix_comment_typo
-
-   By force pushing your update, your original pull request will be updated
-   with your changes so you won't need to resubmit the pull request.
-
-#. If the CI run fails, you will need to make changes to your code in order
-   to fix the issues and amend your commits by rebasing as described above.
-   Additional information about the CI system can be found in
-   `Continuous Integration`_.
-
-Commit Guidelines
-*****************
-
-Changes are submitted as Git commits. Each commit message must contain:
-
-* A short and descriptive subject line that is less than 72 characters,
-  followed by a blank line. The subject line must include a prefix that
-  identifies the subsystem being changed, followed by a colon, and a short
-  title, for example:  ``doc: update wiki references to new site``.
-  (If you're updating an existing file, you can use
-  ``git log <filename>`` to see what developers used as the prefix for
-  previous patches of this file.)
-
-* A change description with your logic or reasoning for the changes, followed
-  by a blank line.
-
-* A Signed-off-by line, ``Signed-off-by: <name> <email>`` typically added
-  automatically by using ``git commit -s``
-
-* If the change addresses an issue, include a line of the form::
-
-      Fixes #<issue number>.
-
-
-All changes and topics sent to GitHub must be well-formed, as described above.
-
-Commit Message Body
-===================
-
-When editing the commit message, please briefly explain what your change
-does and why it's needed. A change summary of ``"Fixes stuff"`` will be rejected.
-
-.. warning::
-   An empty change summary body is not permitted. Even for trivial changes, please
-   include a summary body in the commmit message.
-
-The description body of the commit message must include:
-
-* **what** the change does,
-* **why** you chose that approach,
-* **what** assumptions were made, and
-* **how** you know it works -- for example, which tests you ran.
-
-For examples of accepted commit messages, you can refer to the Zephyr GitHub
-`changelog <https://github.com/zephyrproject-rtos/zephyr/commits/master>`__.
-
-Other Commit Expectations
-=========================
-
-* Commits must build cleanly when applied on top of each other, thus avoiding
-  breaking bisectability.
-
-* Commits must pass all CI checks (see `Continuous Integration`_ for more
-  information)
-
-* Each commit must address a single identifiable issue and must be
-  logically self-contained. Unrelated changes should be submitted as
-  separate commits.
-
-* You may submit pull request RFCs (requests for comments) to send work
-  proposals, progress snapshots of your work, or to get early feedback on
-  features or changes that will affect multiple areas in the code base.
-
-Identifying Contribution Origin
-===============================
-
-When adding a new file to the tree, it is important to detail the source of
-origin on the file, provide attributions, and detail the intended usage. In
-cases where the file is an original to Zephyr, the commit message should
-include the following ("Original" is the assumption if no Origin tag is
-present)::
-
-    Origin: Original
-
-In cases where the file is imported from an external project, the commit
-message shall contain details regarding the original project, the location of
-the project, the SHA-id of the origin commit for the file, the intended
-purpose, and if the file will be maintained by the Zephyr project,
-(whether or not the Zephyr project will contain a localized branch or if
-it is a downstream copy).
-
-For example, a copy of a locally maintained import::
-
-    Origin: Contiki OS
-    License: BSD 3-Clause
-    URL: http://www.contiki-os.org/
-    commit: 853207acfdc6549b10eb3e44504b1a75ae1ad63a
-    Purpose: Introduction of networking stack.
-    Maintained-by: Zephyr
-
-For example, a copy of an externally maintained import::
-
-    Origin: Tiny Crypt
-    License: BSD 3-Clause
-    URL: https://github.com/01org/tinycrypt
-    commit: 08ded7f21529c39e5133688ffb93a9d0c94e5c6e
-    Purpose: Introduction of TinyCrypt
-    Maintained-by: External
+.. _Zephyr devel mailing list: https://lists.zephyrproject.org/g/devel

Kconfig.zephyr

@@ -6,17 +6,19 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 #
-config KERNELVERSION
-	string
-	option env="KERNELVERSION"
 
-config ENV_VAR_SYM_BOARD_DIR
-	string
-	option env="ENV_VAR_BOARD_DIR"
+# Include these first so that any properties (e.g. defaults) below can be
+# overriden in *.defconfig files (by defining symbols in multiple locations).
+# After merging all the symbol definitions, Kconfig picks the first property
+# (e.g. the first default) with a satisfied condition.
+#
+# Board defaults should be parsed before SoC defaults, because boards usually
+# overrides SoC values.
+#
+# Note: $ENV_VAR_ARCH and $ENV_VAR_BOARD_DIR might be glob patterns.
+source "$ENV_VAR_BOARD_DIR/Kconfig.defconfig"
+source "arch/$ENV_VAR_ARCH/soc/*/Kconfig.defconfig"
 
-config ENV_VAR_SYM_ARCH
-	string
-	option env="ENV_VAR_ARCH"
 
 source "arch/Kconfig"
 
@@ -26,8 +28,6 @@ source "dts/Kconfig"
 
 source "drivers/Kconfig"
 
-source "net/Kconfig"
-
 source "misc/Kconfig"
 
 source "lib/Kconfig"
@@ -37,13 +37,3 @@ source "subsys/Kconfig"
 source "ext/Kconfig"
 
 source "tests/Kconfig"
-
-#
-# The following are for Kconfig files for default values only.
-# These should be parsed at the end.
-#
-# Board defaults should be parsed after SoC defaults
-# because board usually overrides SoC values.
-#
-source "arch/$ENV_VAR_SYM_ARCH/soc/*/Kconfig.defconfig"
-source "$ENV_VAR_SYM_BOARD_DIR/Kconfig.defconfig"

Makefile

@@ -2,16 +2,15 @@
 # Top level makefile for things not covered by cmake
 #
 
-ifeq ($(VERBOSE),1)
-  Q =
-else
-  Q = @
+ifndef ZEPHYR_BASE
+$(error The ZEPHYR_BASE environment variable must be set)
 endif
 
-MAKEFLAGS += --no-print-directory
-export Q
+BUILDDIR ?= doc/_build
+DOC_TAG ?= development
+SPHINXOPTS ?= -q
 
 # Documentation targets
 # ---------------------------------------------------------------------------
 htmldocs:
-	$(Q)$(MAKE) -C doc htmldocs
+	mkdir -p ${BUILDDIR} && cmake -GNinja -DDOC_TAG=${DOC_TAG} -DSPHINXOPTS=${SPHINXOPTS} -B${BUILDDIR} -Hdoc/ && ninja -C ${BUILDDIR} htmldocs

README.rst

@@ -1,8 +1,12 @@
-Zephyr Project
-##############
 
 .. raw:: html
 
+   <a href="https://www.zephyrproject.org">
+     <p align="center">
+       <img src="doc/images/Zephyr-Project.png">
+     </p>
+   </a>
+
    <a href="https://bestpractices.coreinfrastructure.org/projects/74"><img
    src="https://bestpractices.coreinfrastructure.org/projects/74/badge"></a>
    <img
@@ -18,13 +22,21 @@ resource-constrained systems: from simple embedded environmental sensors and
 LED wearables to sophisticated smart watches and IoT wireless gateways.
 
 The Zephyr kernel supports multiple architectures, including ARM Cortex-M,
-Intel x86, ARC, NIOS II, Tensilica Xtensa, and RISC V, and a large number of
+Intel x86, ARC, Nios II, Tensilica Xtensa, and RISC-V, and a large number of
 `supported boards`_.
 
 .. below included in doc/introduction/introduction.rst
 
 .. start_include_here
 
+Getting Started
+***************
+
+To start developing Zephyr applications refer to the `Getting Started Guide`_
+in the `Zephyr Documentation`_ pages.
+A brief introduction to Zephyr can be found in the  `Zephyr Introduction`_
+page.
+
 Community Support
 *****************
 
@@ -47,8 +59,7 @@ support systems:
 * **Zephyr Project Website**: The https://zephyrproject.org website is the
   central source of information about the Zephyr Project. On this site, you'll
   find background and current information about the project as well as all the
-  relevant links to project material.  For a quick start, refer to the
-  `Zephyr Introduction`_ and `Getting Started Guide`_.
+  relevant links to project material.
 
 * **Releases**: Source code for Zephyr kernel releases are available at
   https://zephyrproject.org/developers/#downloads. On this page,
@@ -68,9 +79,13 @@ support systems:
 
 * **Documentation**: Extensive Project technical documentation is developed
   along with the Zephyr kernel itself, and can be found at
-  https://zephyrproject.org/doc.  Additional documentation is maintained in
+  http://docs.zephyrproject.org.  Additional documentation is maintained in
   the `Zephyr GitHub wiki`_.
 
+* **Cross-reference**: Source code cross-reference for the Zephyr
+  kernel and samples code is available at
+  https://elixir.bootlin.com/zephyr/latest/source.
+
 * **Issue Reporting and Tracking**: Requirements and Issue tracking is done in
   the Github issues system: https://github.com/zephyrproject-rtos/zephyr/issues.
   You can browse through the reported issues and submit issues of your own.
@@ -84,10 +99,12 @@ support systems:
   Security related issue tracking is done in JIRA.  The location of this JIRA
   is https://zephyrprojectsec.atlassian.net.
 
-* **Mailing List**: The `Zephyr Mailing Lists`_ are perhaps the most convenient
+* **Mailing List**: The `Zephyr Development mailing list`_ is perhaps the most convenient
   way to track developer discussions and to ask your own support questions to
-  the Zephyr project community.
-  You can also read through message archives to follow
+  the Zephyr project community.  There are also specific `Zephyr mailing list
+  subgroups`_ for announcements, builds, marketing, and Technical
+  Steering Committee notes, for example.
+  You can read through the message archives to follow
   past posts and discussions, a good thing to do to discover more about the
   Zephyr project.
 
@@ -97,11 +114,13 @@ support systems:
   client or use a client-side application such as pidgin.
 
 
-.. _supported boards: https://www.zephyrproject.org/doc/boards/boards.html
-.. _Zephyr Introduction: https://www.zephyrproject.org/doc/introduction/introducing_zephyr.html
-.. _Getting Started Guide: https://www.zephyrproject.org/doc/getting_started/getting_started.html
-.. _Contribution Guide: https://www.zephyrproject.org/doc/contribute/contribute_guidelines.html
+.. _supported boards: http://docs.zephyrproject.org/boards/boards.html
+.. _Zephyr Documentation: http://docs.zephyrproject.org
+.. _Zephyr Introduction: http://docs.zephyrproject.org/introduction/introducing_zephyr.html
+.. _Getting Started Guide: http://docs.zephyrproject.org/getting_started/getting_started.html
+.. _Contribution Guide: http://docs.zephyrproject.org/contribute/contribute_guidelines.html
 .. _Zephyr GitHub wiki: https://github.com/zephyrproject-rtos/zephyr/wiki
-.. _Zephyr Mailing Lists: https://lists.zephyrproject.org/
-.. _Sample and Demo Code Examples: https://www.zephyrproject.org/doc/samples/samples.html
-.. _Security Overview: https://www.zephyrproject.org/doc/security/security-overview.html
+.. _Zephyr Development mailing list: https://lists.zephyrproject.org/g/devel
+.. _Zephyr mailing list subgroups: https://lists.zephyrproject.org/g/main/subgroups
+.. _Sample and Demo Code Examples: http://docs.zephyrproject.org/samples/samples.html
+.. _Security Overview: http://docs.zephyrproject.org/security/security-overview.html

VERSION

@@ -1,5 +1,5 @@
 VERSION_MAJOR = 1
-VERSION_MINOR = 11
+VERSION_MINOR = 13
 PATCHLEVEL = 0
 VERSION_TWEAK = 0
 EXTRAVERSION =

arch/CMakeLists.txt

@@ -1,2 +1,4 @@
+add_definitions(-D__ZEPHYR_SUPERVISOR__)
+
 add_subdirectory(common)
 add_subdirectory(${ARCH})

arch/Kconfig

@@ -8,6 +8,13 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
+# Include these first so that any properties (e.g. defaults) below can be
+# overriden (by defining symbols in multiple locations)
+
+source "boards/Kconfig"
+# Note: $ENV_VAR_ARCH might be a glob pattern
+source "arch/$ENV_VAR_ARCH/Kconfig"
+
 
 choice
 	prompt "Architecture"
@@ -15,6 +22,7 @@ choice
 
 config ARC
 	bool "ARC architecture"
+	select HAS_DTS
 
 config ARM
 	bool "ARM architecture"
@@ -80,6 +88,7 @@ config USERSPACE
 
 config PRIVILEGED_STACK_SIZE
 	int "Size of privileged stack"
+	default 384 if ARC
 	default 256
 	depends on ARCH_HAS_USERSPACE
 	help
@@ -88,6 +97,12 @@ config PRIVILEGED_STACK_SIZE
 	  this region will be inaccessible from user mode.  During system calls,
 	  this region will be utilized by the system call.
 
+config STACK_GROWS_UP
+	bool "Stack grows towards higher memory addresses"
+	help
+	  Select this option if the architecture has upward growing thread
+	  stacks. This is not common.
+
 config MAX_THREAD_BYTES
 	int "Bytes to use when tracking object thread permissions"
 	default 2
@@ -98,10 +113,21 @@ config MAX_THREAD_BYTES
 	  bitfield (in bytes) and imposes a limit on how many threads can
 	  be created in the system.
 
+config DYNAMIC_OBJECTS
+	bool "Allow kernel objects to be allocated at runtime"
+	depends on USERSPACE
+	help
+	Enabling this option allows for kernel objects to be requested from
+	the calling thread's resource pool, at a slight cost in performance
+	due to the supplemental run-time tables required to validate such
+	objects.
+
+	Objects allocated in this way can be freed with a supervisor-only
+	API call, or when the number of references to that object drops to
+	zero.
+
 config SIMPLE_FATAL_ERROR_HANDLER
-	prompt "Simple system fatal error handler"
-	bool
-	default n
+	bool "Simple system fatal error handler"
 	default y if !MULTITHREADING
 	help
 	  Provides an implementation of _SysFatalErrorHandler() that hard hangs
@@ -114,17 +140,14 @@ menu "Interrupt Configuration"
 # Interrupt related configs
 #
 config GEN_ISR_TABLES
-	bool
-	prompt "Use generated IRQ tables"
-	default n
+	bool "Use generated IRQ tables"
 	help
 	  This option controls whether a platform uses the gen_isr_tables
 	  script to generate its interrupt tables. This mechanism will create
 	  an appropriate hardware vector table and/or software IRQ table.
 
 config GEN_IRQ_VECTOR_TABLE
-	bool
-	prompt "Generate an interrupt vector table"
+	bool "Generate an interrupt vector table"
 	default y
 	depends on GEN_ISR_TABLES
 	help
@@ -136,8 +159,7 @@ config GEN_IRQ_VECTOR_TABLE
 	  supplied by the application or architecture code.
 
 config GEN_SW_ISR_TABLE
-	bool
-	prompt "Generate a software ISR table"
+	bool "Generate a software ISR table"
 	default y
 	depends on GEN_ISR_TABLES
 	help
@@ -161,7 +183,6 @@ config GEN_IRQ_START_VECTOR
 
 config IRQ_OFFLOAD
 	bool "Enable IRQ offload"
-	default n
 	help
 	  Enable irq_offload() API which allows functions to be synchronously
 	  run in interrupt context. Mainly useful for test cases.
@@ -196,7 +217,6 @@ config ARCH_HAS_THREAD_ABORT
 config SYS_POWER_LOW_POWER_STATE_SUPPORTED
 	# Hidden
 	bool
-	default n
 	help
 	  This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
 	  configuration option.
@@ -204,7 +224,6 @@ config SYS_POWER_LOW_POWER_STATE_SUPPORTED
 config SYS_POWER_DEEP_SLEEP_SUPPORTED
 	# Hidden
 	bool
-	default n
 	help
 	  This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
 	  configuration option.
@@ -212,7 +231,6 @@ config SYS_POWER_DEEP_SLEEP_SUPPORTED
 config BOOTLOADER_CONTEXT_RESTORE_SUPPORTED
 	# Hidden
 	bool
-	default n
 	help
 	  This option signifies that the target has options of bootloaders
 	  that support context restore upon resume from deep sleep
@@ -223,7 +241,6 @@ config BOOTLOADER_CONTEXT_RESTORE_SUPPORTED
 
 config CPU_HAS_FPU
 	bool
-	default n
 	help
 	  This option is enabled when the CPU has hardware floating point
 	  unit.
@@ -231,14 +248,12 @@ config CPU_HAS_FPU
 config CPU_HAS_MPU
 	bool
 	# Omit prompt to signify "hidden" option
-	default n
 	help
 	  This option is enabled when the CPU has a Memory Protection Unit (MPU).
 
 config MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
 	bool
 	# Omit prompt to signify "hidden" option
-	default n
 	help
 	  This option is enabled when the MPU requires a power of two alignment
 	  and size for MPU regions.
@@ -248,9 +263,7 @@ menu "Floating Point Options"
 depends on CPU_HAS_FPU
 
 config FLOAT
-	bool
-	prompt "Floating point registers"
-	default n
+	bool "Floating point registers"
 	help
 	  This option allows threads to use the floating point registers.
 	  By default, only a single thread may use the registers.
@@ -259,10 +272,8 @@ config FLOAT
 	  floating point register will get a fatal exception.
 
 config FP_SHARING
-	bool
-	prompt "Floating point register sharing"
+	bool "Floating point register sharing"
 	depends on FLOAT
-	default n
 	help
 	  This option allows multiple threads to use the floating point
 	  registers.
@@ -308,8 +319,3 @@ config BOARD
 	  The Board is the first location where we search for a linker.ld file,
 	  if not found we look for the linker file in
 	  arch/<arch>/soc/<family>/<series>
-
-
-source "arch/$ENV_VAR_SYM_ARCH/Kconfig"
-
-source "boards/Kconfig"

arch/arc/CMakeLists.txt

@@ -10,7 +10,5 @@ zephyr_cc_option(-fno-delete-null-pointer-checks)
 
 zephyr_cc_option_ifdef (CONFIG_LTO         -flto)
 
-set_property(GLOBAL PROPERTY E_KERNEL_ENTRY  -e${CONFIG_KERNEL_ENTRY})
-
 add_subdirectory(soc/${SOC_PATH})
 add_subdirectory(core)

arch/arc/Kconfig

@@ -17,6 +17,10 @@ endchoice
 menu "ARC Options"
 	depends on ARC
 
+# Include these first so that any properties (e.g. defaults) below can be
+# overriden (by defining symbols in multiple locations)
+source "arch/arc/soc/*/Kconfig"
+
 config ARCH
 	default "arc"
 
@@ -40,7 +44,7 @@ menu "ARCv2 Family Options"
 
 config	CPU_ARCV2
 	bool
-	select		ARCH_HAS_STACK_PROTECTION
+	select ARCH_HAS_STACK_PROTECTION
 	select ARCH_HAS_USERSPACE if ARC_CORE_MPU
 	default y
 	help
@@ -55,8 +59,7 @@ config	DATA_ENDIANNESS_LITTLE
 	  implemented as big endian.
 
 config	NUM_IRQ_PRIO_LEVELS
-	int
-	prompt "Number of supported interrupt priority levels"
+	int "Number of supported interrupt priority levels"
 	range 1 16
 	help
 	  Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
@@ -65,8 +68,7 @@ config	NUM_IRQ_PRIO_LEVELS
 	  The BSP must provide a valid default for proper operation.
 
 config	NUM_IRQS
-	int
-	prompt "Upper limit of interrupt numbers/IDs used"
+	int "Upper limit of interrupt numbers/IDs used"
 	range 17 256
 	help
 	  Interrupts available will be 0 to NUM_IRQS-1.
@@ -77,8 +79,7 @@ config	NUM_IRQS
 	  vector table.
 
 config	RGF_NUM_BANKS
-	int
-	prompt "Number of General Purpose Register Banks"
+	int "Number of General Purpose Register Banks"
 	depends on CPU_ARCV2
 	range 1 2
 	default 2
@@ -91,8 +92,7 @@ config	RGF_NUM_BANKS
 	  and restore general purpose registers.
 
 config ARC_FIRQ
-	bool
-	prompt "FIRQ enable"
+	bool "FIRQ enable"
 	default y
 	help
 	  Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts
@@ -110,8 +110,7 @@ config	ARC_STACK_CHECKING
 	  enables code that allows using this debug feature
 
 config	FAULT_DUMP
-	int
-	prompt "Fault dump level"
+	int "Fault dump level"
 	default 2
 	range 0 2
 	help
@@ -126,8 +125,7 @@ config	FAULT_DUMP
 	  0: Off.
 
 config	XIP
-	default n if NSIM
-	default y
+	default y if !UART_NSIM
 
 config GEN_ISR_TABLES
 	default y
@@ -136,24 +134,19 @@ config GEN_IRQ_START_VECTOR
 	default 16
 
 config HARVARD
-	prompt "Harvard Architecture"
-	bool
-	default n
+	bool "Harvard Architecture"
 	help
 	  The ARC CPU can be configured to have two busses;
 	  one for instruction fetching and another that serves as a data bus.
 
 config CODE_DENSITY
-	prompt "Code Density Option"
-	bool
-	default n
+	bool "Code Density Option"
 	help
 	  Enable code density option to get better code density
 
 config ARC_HAS_SECURE
 	bool
 	#  a hidden option
-	default n
 	help
 	  This option is enabled when ARC core supports secure mode
 
@@ -164,7 +157,6 @@ config ARC_MPU_ENABLE
 	bool "Enable MPU"
 	depends on CPU_HAS_MPU
 	select ARC_MPU
-	default n
 	help
 	  Enable MPU
 
@@ -172,68 +164,8 @@ source "arch/arc/core/mpu/Kconfig"
 
 endmenu
 
-if !HAS_DTS
-config ICCM_SIZE
-	int "ICCM Size in kB"
-	help
-	  This option specifies the size of the ICCM in kB.  It is normally set by
-	  the board's defconfig file and the user should generally avoid modifying
-	  it via the menu configuration.
-
-config ICCM_BASE_ADDRESS
-	hex "ICCM Base Address"
-	help
-	  This option specifies the base address of the ICCM on the board.  It is
-	  normally set by the board's defconfig file and the user should generally
-	  avoid modifying it via the menu configuration.
-
-config DCCM_SIZE
-	int "DCCM Size in kB"
-	help
-	  This option specifies the size of the DCCM in kB.  It is normally set by
-	  the board's defconfig file and the user should generally avoid modifying
-	  it via the menu configuration.
-
-config DCCM_BASE_ADDRESS
-	hex "DCCM Base Address"
-	help
-	  This option specifies the base address of the DCCM on the board.  It is
-	  normally set by the board's defconfig file and the user should generally
-	  avoid modifying it via the menu configuration.
-
-config SRAM_SIZE
-	int "SRAM Size in kB"
-	help
-	  This option specifies the size of the SRAM in kB.  It is normally set by
-	  the board's defconfig file and the user should generally avoid modifying
-	  it via the menu configuration.
-
-config SRAM_BASE_ADDRESS
-	hex "SRAM Base Address"
-	help
-	  This option specifies the base address of the SRAM on the board.  It is
-	  normally set by the board's defconfig file and the user should generally
-	  avoid modifying it via the menu configuration.
-
-config FLASH_SIZE
-	int "Flash Size in kB"
-	help
-	  This option specifies the size of the flash in kB.  It is normally set by
-	  the board's defconfig file and the user should generally avoid modifying
-	  it via the menu configuration.
-
-config FLASH_BASE_ADDRESS
-	hex "Flash Base Address"
-	help
-	  This option specifies the base address of the flash on the board.  It is
-	  normally set by the board's defconfig file and the user should generally
-	  avoid modifying it via the menu configuration.
-endif
-
 config CACHE_LINE_SIZE_DETECT
-	bool
-	prompt "Detect d-cache line size at runtime"
-	default n
+	bool "Detect d-cache line size at runtime"
 	help
 	  This option enables querying the d-cache build register for finding
 	  the d-cache line size at the expense of taking more memory and code
@@ -243,8 +175,7 @@ config CACHE_LINE_SIZE_DETECT
 	  option and manually enter the value for CACHE_LINE_SIZE.
 
 config CACHE_LINE_SIZE
-	int
-	prompt "Cache line size" if !CACHE_LINE_SIZE_DETECT
+	int "Cache line size" if !CACHE_LINE_SIZE_DETECT
 	default 32
 	help
 	  Size in bytes of a CPU d-cache line.
@@ -253,12 +184,9 @@ config CACHE_LINE_SIZE
 
 config ARCH_CACHE_FLUSH_DETECT
 	bool
-	default n
 
 config CACHE_FLUSHING
-	bool
-	default n
-	prompt "Enable d-cache flushing mechanism"
+	bool "Enable d-cache flushing mechanism"
 	help
 	  This links in the sys_cache_flush() function, which provides a
 	  way to flush multiple lines of the d-cache.
@@ -267,6 +195,4 @@ config CACHE_FLUSHING
 
 endmenu
 
-source "arch/arc/soc/*/Kconfig"
-
 endmenu

arch/arc/core/CMakeLists.txt

@@ -1,4 +1,6 @@
-zephyr_sources(
+zephyr_library()
+
+zephyr_library_sources(
 	thread.c
 	thread_entry_wrapper.S
 	cpu_idle.S
@@ -17,9 +19,9 @@ zephyr_sources(
 	vector_table.c
 	)
 
-zephyr_sources_ifdef(CONFIG_ARC_FIRQ fast_irq.S)
+zephyr_library_sources_ifdef(CONFIG_ARC_FIRQ fast_irq.S)
 
-zephyr_sources_if_kconfig(irq_offload.c)
-zephyr_sources_ifdef(CONFIG_ATOMIC_OPERATIONS_CUSTOM atomic.c)
-add_subdirectory_ifdef(CONFIG_CPU_HAS_MPU mpu)
-zephyr_sources_ifdef(CONFIG_USERSPACE userspace.S)
+zephyr_library_sources_if_kconfig(irq_offload.c)
+zephyr_library_sources_ifdef(CONFIG_ATOMIC_OPERATIONS_CUSTOM atomic.c)
+add_subdirectory_ifdef(CONFIG_ARC_CORE_MPU mpu)
+zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)

arch/arc/core/cpu_idle.S

@@ -35,9 +35,9 @@ SECTION_VAR(BSS, k_cpu_sleep_mode)
 
 SECTION_FUNC(TEXT, k_cpu_idle)
 
-#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+#ifdef CONFIG_TRACING
 	push_s blink
-	jl    _sys_k_event_logger_enter_sleep
+	jl    z_sys_trace_idle
 	pop_s blink
 #endif
 
@@ -56,9 +56,9 @@ SECTION_FUNC(TEXT, k_cpu_idle)
  */
 SECTION_FUNC(TEXT, k_cpu_atomic_idle)
 
-#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+#ifdef CONFIG_TRACING
 	push_s blink
-	jl    _sys_k_event_logger_enter_sleep
+	jl    z_sys_trace_idle
 	pop_s blink
 #endif
 

arch/arc/core/fast_irq.S

@@ -60,11 +60,19 @@ SECTION_FUNC(TEXT, _firq_enter)
  * This has already been done by _isr_wrapper.
  */
 #ifdef CONFIG_ARC_STACK_CHECKING
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr r2, [_ARC_V2_SEC_STAT]
+	bclr r2, r2, _ARC_V2_SEC_STAT_SSC_BIT
+	/* sflag r2 */
+	/* sflag instruction is not supported in current ARC GNU */
+	.long 0x00bf302f
+#else
 	/* disable stack checking */
 	lr r2, [_ARC_V2_STATUS32]
 	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
 	kflag r2
 #endif
+#endif
 
 #if CONFIG_RGF_NUM_BANKS != 1
 #ifndef CONFIG_FIRQ_NO_LPCC
@@ -123,8 +131,6 @@ firq_nest:
 
 SECTION_FUNC(TEXT, _firq_exit)
 
-	pop sp
-
 #if CONFIG_RGF_NUM_BANKS != 1
 #ifndef CONFIG_FIRQ_NO_LPCC
 	/* restore lp_count, lp_start, lp_end from r23-r25 */
@@ -142,18 +148,15 @@ SECTION_FUNC(TEXT, _firq_exit)
 	bne.d	_firq_no_reschedule
 	st	r0, [r1]
 
+#ifdef CONFIG_STACK_SENTINEL
+	bl _check_stack_sentinel
+#endif
+
 #ifdef CONFIG_PREEMPT_ENABLED
 
 	mov_s r1, _kernel
 	ld_s r2, [r1, _kernel_offset_to_current]
 
-	/*
-	 * Non-preemptible thread ? Do not schedule (see explanation of
-	 * preempt field in kernel_struct.h).
-	 */
-	ldh_s r0, [r2, _thread_offset_to_preempt]
-	brhs r0, _NON_PREEMPT_THRESHOLD, _firq_no_reschedule
-
 	/* Check if the current thread (in r2) is the cached thread */
 	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
 	brne r0, r2, _firq_reschedule
@@ -164,6 +167,8 @@ SECTION_FUNC(TEXT, _firq_exit)
 
 .balign 4
 _firq_no_reschedule:
+	pop sp
+
 	/*
 	 * Keeping this code block close to those that use it allows using brxx
 	 * instruction instead of a pair of cmp and bxx
@@ -207,6 +212,7 @@ _firq_no_reschedule:
 
 .balign 4
 _firq_reschedule:
+	pop sp
 
 #if CONFIG_RGF_NUM_BANKS != 1
 	/*
@@ -245,11 +251,7 @@ _firq_reschedule:
 	st_s r2, [r1, _kernel_offset_to_current]
 
 #ifdef CONFIG_ARC_STACK_CHECKING
-	/* Use stack top and base registers from restored context */
-	ld r3, [r2, _thread_offset_to_stack_base]
-	sr r3, [_ARC_V2_KSTACK_BASE]
-	ld r3, [r2, _thread_offset_to_stack_top]
-	sr r3, [_ARC_V2_KSTACK_TOP]
+	_load_stack_check_regs
 #endif
 	/*
 	 * _load_callee_saved_regs expects incoming thread in r2.

arch/arc/core/fatal.c

@@ -18,10 +18,6 @@
 #include <arch/cpu.h>
 #include <misc/printk.h>
 
-const NANO_ESF _default_esf = {
-	0xdeaddead, /* placeholder */
-};
-
 /**
  *
  * @brief Kernel fatal error handler
@@ -37,14 +33,14 @@ const NANO_ESF _default_esf = {
  *
  * @return This function does not return.
  */
-FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
-							const NANO_ESF *pEsf)
+void _NanoFatalErrorHandler(unsigned int reason, const NANO_ESF *pEsf)
 {
 	switch (reason) {
 	case _NANO_ERR_HW_EXCEPTION:
 		break;
 
-#if defined(CONFIG_STACK_CANARIES) || defined(CONFIG_ARC_STACK_CHECKING)
+#if defined(CONFIG_STACK_CANARIES) || defined(CONFIG_ARC_STACK_CHECKING) \
+	|| defined(CONFIG_STACK_SENTINEL)
 	case _NANO_ERR_STACK_CHK_FAIL:
 		printk("***** Stack Check Fail! *****\n");
 		break;
@@ -66,10 +62,13 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 		printk("**** Unknown Fatal Error %d! ****\n", reason);
 		break;
 	}
-	printk("Current thread ID = %p\n"
-	       "Faulting instruction address = 0x%lx\n",
-	       k_current_get(),
-	       _arc_v2_aux_reg_read(_ARC_V2_ERET));
+
+	printk("Current thread ID = %p\n",  k_current_get());
+
+	if (reason == _NANO_ERR_HW_EXCEPTION) {
+		printk("Faulting instruction address = 0x%lx\n",
+		_arc_v2_aux_reg_read(_ARC_V2_ERET));
+	}
 
 	/*
 	 * Now that the error has been reported, call the user implemented
@@ -80,12 +79,8 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 	 */
 
 	_SysFatalErrorHandler(reason, pEsf);
-
-	for (;;)
-		;
 }
 
-
 FUNC_NORETURN void _arch_syscall_oops(void *ssf_ptr)
 {
 	_SysFatalErrorHandler(_NANO_ERR_KERNEL_OOPS, ssf_ptr);

arch/arc/core/fault.c

@@ -18,6 +18,15 @@
 #include <kernel.h>
 #include <kernel_structs.h>
 #include <misc/printk.h>
+#include <exc_handle.h>
+
+#ifdef CONFIG_USERSPACE
+Z_EXC_DECLARE(z_arch_user_string_nlen);
+
+static const struct z_exc_handle exceptions[] = {
+	Z_EXC_HANDLE(z_arch_user_string_nlen)
+};
+#endif
 
 /*
  * @brief Fault handler
@@ -26,19 +35,36 @@
  * and is responsible only for reporting the error. Once reported, it then
  * invokes the user provided routine _SysFatalErrorHandler() which is
  * responsible for implementing the error handling policy.
- *
- * @return This function does not return.
  */
-void _Fault(void)
+void _Fault(NANO_ESF *esf)
 {
 	u32_t vector, code, parameter;
 	u32_t exc_addr = _arc_v2_aux_reg_read(_ARC_V2_EFA);
 	u32_t ecr = _arc_v2_aux_reg_read(_ARC_V2_ECR);
 
+#ifdef CONFIG_USERSPACE
+	for (int i = 0; i < ARRAY_SIZE(exceptions); i++) {
+		u32_t start = (u32_t)exceptions[i].start;
+		u32_t end = (u32_t)exceptions[i].end;
+
+		if (esf->pc >= start && esf->pc < end) {
+			esf->pc = (u32_t)(exceptions[i].fixup);
+			return;
+		}
+	}
+#endif
+
 	vector = _ARC_V2_ECR_VECTOR(ecr);
 	code =  _ARC_V2_ECR_CODE(ecr);
 	parameter = _ARC_V2_ECR_PARAMETER(ecr);
 
+
+	/* exception raised by kernel */
+	if (vector == 0x9 && parameter == _TRAP_S_CALL_RUNTIME_EXCEPT) {
+		_NanoFatalErrorHandler(esf->r0, esf);
+		return;
+	}
+
 	printk("Exception vector: 0x%x, cause code: 0x%x, parameter 0x%x\n",
 	       vector, code, parameter);
 	printk("Address 0x%x\n", exc_addr);
@@ -47,8 +73,9 @@ void _Fault(void)
 	 * check violation
 	 */
 	if (vector == 6 && parameter == 2) {
-		_NanoFatalErrorHandler(_NANO_ERR_STACK_CHK_FAIL, &_default_esf);
+		_NanoFatalErrorHandler(_NANO_ERR_STACK_CHK_FAIL, esf);
+		return;
 	}
 #endif
-	_NanoFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, &_default_esf);
+	_NanoFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, esf);
 }

arch/arc/core/fault_s.S

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
+ * Copyright (c) 2018 Synopsys.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,9 +16,10 @@
 #include <linker/sections.h>
 #include <arch/cpu.h>
 #include <swap_macros.h>
+#include <syscall.h>
 
 GTEXT(_Fault)
-
+GTEXT(_do_kernel_oops)
 GTEXT(__reset)
 GTEXT(__memory_error)
 GTEXT(__instruction_error)
@@ -32,9 +34,19 @@ GTEXT(__ev_extension)
 GTEXT(__ev_div_zero)
 GTEXT(__ev_dc_error)
 GTEXT(__ev_maligned)
+#ifdef CONFIG_IRQ_OFFLOAD
+GTEXT(_irq_do_offload);
+#endif
 
 GDATA(exc_nest_count)
 
+	.balign 4
+SECTION_VAR(BSS, saved_value)
+	.word 0
+
+/* the necessary stack size for exception handling */
+#define EXCEPTION_STACK_SIZE 384
+
 /*
  * @brief Fault handler installed in the fault and reserved vectors
  */
@@ -47,39 +59,152 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_tlb_miss_d)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_prot_v)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_privilege_v)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_swi)
-#if !defined(CONFIG_IRQ_OFFLOAD) && !defined(CONFIG_USERSPACE)
-SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
-#endif
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_extension)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_div_zero)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_dc_error)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 
+_exc_entry:
+	st sp, [saved_value]
 	/*
-	 * Before invoking exception handler, the kernel switches to an exception
-	 * stack, to save the faulting thread's registers.
-	 * The exception is fatal and all the kernel can do is just print
-	 * a diagnostic message and halt.
+	 * re-use the top part of interrupt stack as exception
+	 * stack. If this top part is used by interrupt handling,
+	 * and exception is raised, then here it's guaranteed that
+	 * exception handling has necessary stack to use
 	 */
+	mov_s sp, _interrupt_stack
+	add sp, sp, EXCEPTION_STACK_SIZE
 
-#ifdef CONFIG_ARC_STACK_CHECKING
-	push_s r2
-	/* disable stack checking */
-	lr r2, [_ARC_V2_STATUS32]
-	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
-	kflag r2
-	pop_s r2
-#endif
-
-	/* save caller saved registers */
+	/*
+	 * save caller saved registers
+	 * this stack frame is set up in exception stack,
+	 * not in the original sp (thread stack or interrupt stack).
+	 * Because the exception may be raised by stack checking or
+	 * mpu protect violation related to stack. If this stack frame
+	 * is setup in original sp, double exception may be raised during
+	 * _create_irq_stack_frame, which is unrecoverable.
+	 */
 	_create_irq_stack_frame
 
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr r0,[_ARC_V2_ERSEC_STAT]
+	st_s r0, [sp, ___isf_t_sec_stat_OFFSET]
+#endif
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, ___isf_t_status32_OFFSET]
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
+
+	/* sp is parameter of _Fault */
+	mov r0, sp
+	jl _Fault
+
+_exc_return:
+
+#ifdef CONFIG_PREEMPT_ENABLED
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+
+	/* check if the current thread needs to be rescheduled */
+	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
+	breq r0, r2, _exc_return_from_exc
+
+	ld_s r2, [r1, _kernel_offset_to_ready_q_cache]
+	st_s r2, [r1, _kernel_offset_to_current]
+
+#ifdef CONFIG_ARC_HAS_SECURE
+	/*
+	 * sync up the ERSEC_STAT.ERM and SEC_STAT.IRM.
+	 * use a fake interrupt return to simulate an exception turn.
+	 * ERM and IRM record which mode the cpu should return, 1: secure
+	 * 0: normal
+	 */
+	lr r3,[_ARC_V2_ERSEC_STAT]
+	btst r3, 31
+	bset.nz r3, r3, 3
+	bclr.z r3, r3, 3
+	/* sflag r3 */
+	/* sflag instruction is not supported in current ARC GNU */
+	.long 0x00ff302f
+#endif
+	/* clear AE bit to forget this was an exception */
+	lr r3, [_ARC_V2_STATUS32]
+	and r3,r3,(~_ARC_V2_STATUS32_AE)
+	kflag r3
+	/* pretend lowest priority interrupt happened to use common handler */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1)) /* use lowest */
+	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+
+	/* Assumption: r2 has current thread */
+	b _rirq_common_interrupt_swap
+#endif
+
+_exc_return_from_exc:
+	ld_s r0, [sp, ___isf_t_pc_OFFSET]
+	sr r0, [_ARC_V2_ERET]
+
+	_pop_irq_stack_frame
+	ld sp, [saved_value]
+	rtie
+
+
+SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
+	/* get the id of trap_s */
+	lr ilink, [_ARC_V2_ECR]
+	and ilink, ilink, 0x3f
+#ifdef CONFIG_USERSPACE
+	cmp ilink, _TRAP_S_CALL_SYSTEM_CALL
+	bne _do_non_syscall_trap
+/* do sys_call */
+	mov ilink, K_SYSCALL_LIMIT
+	cmp r6, ilink
+	blt valid_syscall_id
+
+	mov r0, r6
+	mov r6, K_SYSCALL_BAD
+
+valid_syscall_id:
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr ilink, [_ARC_V2_ERSEC_STAT]
+	push ilink
+#endif
+	lr ilink, [_ARC_V2_ERET]
+	push ilink
+	lr ilink, [_ARC_V2_ERSTATUS]
+	push ilink
+
+
+	bclr ilink, ilink, _ARC_V2_STATUS32_U_BIT
+	sr ilink, [_ARC_V2_ERSTATUS]
+
+	mov ilink, _arc_do_syscall
+	sr ilink, [_ARC_V2_ERET]
+
+	rtie
+
+_do_non_syscall_trap:
+#endif /* CONFIG_USERSPACE */
+#ifdef CONFIG_IRQ_OFFLOAD
+	/*
+	 * IRQ_OFFLOAD is to simulate interrupt handling through exception,
+	 * so its entry is different with normal exception handling, it is
+	 * handled in isr stack
+	 */
+	cmp ilink, _TRAP_S_SCALL_IRQ_OFFLOAD
+	bne _exc_entry
+	/* save caller saved registers */
+	_create_irq_stack_frame
+
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr r0,[_ARC_V2_ERSEC_STAT]
+	st_s r0, [sp, ___isf_t_sec_stat_OFFSET]
+#endif
 	lr r0,[_ARC_V2_ERSTATUS]
 	st_s r0, [sp, ___isf_t_status32_OFFSET]
 	lr r0,[_ARC_V2_ERET]
 	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
 
-#ifndef CONFIG_USERSPACE
 	ld r1, [exc_nest_count]
 	add r0, r1, 1
 	st r0, [exc_nest_count]
@@ -92,130 +217,25 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 	ld sp, [r1, _kernel_offset_to_irq_stack]
 exc_nest_handle:
 	push_s r0
-#endif
 
-	jl _Fault
-
-#ifndef CONFIG_USERSPACE
-	pop sp
-
-	mov	r1, exc_nest_count
-	ld	r0, [r1]
-	sub	r0, r0, 1
-	st 	r0, [r1]
-#endif
-	/* if _Fault returns, restore the registers */
-	_pop_irq_stack_frame
-
-	rtie
-
-#ifdef CONFIG_IRQ_OFFLOAD
-GTEXT(_irq_do_offload);
-#endif
-
-#if defined(CONFIG_IRQ_OFFLOAD) || defined(CONFIG_USERSPACE)
-SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
-#ifdef CONFIG_USERSPACE
-	/* get the id of trap_s */
-	lr ilink, [_ARC_V2_ECR]
-	and ilink, ilink, 0x3f
-	cmp ilink, 0x3
-	bne _do_other_trap
-/* do sys_call */
-	mov ilink, _SYSCALL_LIMIT
-	cmp r6, ilink
-	blt valid_syscall_id
-
-	mov r0, r6
-	mov r6, _SYSCALL_BAD
-
-valid_syscall_id:
-	lr ilink, [_ARC_V2_ERET]
-	push ilink
-	lr ilink, [_ARC_V2_ERSTATUS]
-	push ilink
-
-	bclr ilink, ilink, _ARC_V2_STATUS32_U_BIT
-	sr ilink, [_ARC_V2_ERSTATUS]
-
-	mov ilink, _arc_do_syscall
-	sr ilink, [_ARC_V2_ERET]
-
-	rtie
-
-	/*
-	 * Before invoking exception handler, the kernel switches to an exception
-	 * stack to save the faulting thread's registers.
-	 * The exception is fatal and all the kernel can do is just print
-	 * a diagnostic message and halt.
-	 */
-
-_do_other_trap:
-#endif /* CONFIG_USERSPACE */
-#ifdef CONFIG_ARC_STACK_CHECKING
-	push_s r2
-	/* disable stack checking */
-	lr r2, [_ARC_V2_STATUS32]
-	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
-	kflag r2
-	pop_s r2
-#endif
-
-	/* save caller saved registers */
-	_create_irq_stack_frame
-
-	lr r0,[_ARC_V2_ERSTATUS]
-	st_s r0, [sp, ___isf_t_status32_OFFSET]
-	lr r0,[_ARC_V2_ERET]
-	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
-
-	ld r1, [exc_nest_count]
-	add r0, r1, 1
-	st r0, [exc_nest_count]
-	cmp r1, 0
-
-	bgt.d  trap_nest_handle
-	mov r0, sp
-
-	mov r1, _kernel
-	ld sp, [r1, _kernel_offset_to_irq_stack]
-trap_nest_handle:
-	push_s r0
-
-#ifdef CONFIG_IRQ_OFFLOAD
 	jl _irq_do_offload
-#endif
 
 	pop sp
 
-	/* check if we're a nested interrupt: if so, let the
-	 * interrupted interrupt handle the reschedule
-	 */
 	mov	r1, exc_nest_count
 	ld	r0, [r1]
 	sub	r0, r0, 1
 	cmp	r0, 0
-	beq.d	_trap_check_for_swap
+	bne.d	_exc_return_from_exc
 	st 	r0, [r1]
 
-_trap_return:
-	_pop_irq_stack_frame
-	rtie
-
-.balign 4
-_trap_check_for_swap:
+#ifdef CONFIG_PREEMPT_ENABLED
 	mov_s r1, _kernel
 	ld_s r2, [r1, _kernel_offset_to_current]
-	/*
-	 * Non-preemptible thread ? Do not schedule (see explanation of
-	 * preempt field in kernel_struct.h).
-	 */
-	ldh_s r0, [r2, _thread_offset_to_preempt]
-	brhs r0, _NON_PREEMPT_THRESHOLD, _trap_return
 
 	/* check if the current thread needs to be rescheduled */
 	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
-	breq r0, r2, _trap_return
+	breq r0, r2, _exc_return_from_irqoffload_trap
 
 	_save_callee_saved_regs
 
@@ -225,6 +245,21 @@ _trap_check_for_swap:
 	ld_s r2, [r1, _kernel_offset_to_ready_q_cache]
 	st_s r2, [r1, _kernel_offset_to_current]
 
+#ifdef CONFIG_ARC_HAS_SECURE
+	/*
+	 * sync up the ERSEC_STAT.ERM and SEC_STAT.IRM.
+	 * use a fake interrupt return to simulate an exception turn.
+	 * ERM and IRM record which mode the cpu should return, 1: secure
+	 * 0: normal
+	 */
+	lr r3,[_ARC_V2_ERSEC_STAT]
+	btst r3, 31
+	bset.nz r3, r3, 3
+	bclr.z r3, r3, 3
+	/* sflag r3 */
+	/* sflag instruction is not supported in current ARC GNU */
+	.long 0x00ff302f
+#endif
 	/* clear AE bit to forget this was an exception */
 	lr r3, [_ARC_V2_STATUS32]
 	and r3,r3,(~_ARC_V2_STATUS32_AE)
@@ -236,4 +271,10 @@ _trap_check_for_swap:
 
 	/* Assumption: r2 has current thread */
 	b _rirq_common_interrupt_swap
-#endif /* CONFIG_IRQ_OFFLOAD || CONFIG_USERSPACE */
+#endif
+
+_exc_return_from_irqoffload_trap:
+	_pop_irq_stack_frame
+	rtie
+#endif /* CONFIG_IRQ_OFFLOAD */
+	b _exc_entry

arch/arc/core/irq_manage.c

@@ -38,7 +38,7 @@
 
 void _arch_irq_enable(unsigned int irq)
 {
-	int key = irq_lock();
+	unsigned int key = irq_lock();
 
 	_arc_v2_irq_unit_int_enable(irq);
 	irq_unlock(key);
@@ -55,7 +55,7 @@ void _arch_irq_enable(unsigned int irq)
 
 void _arch_irq_disable(unsigned int irq)
 {
-	int key = irq_lock();
+	unsigned int key = irq_lock();
 
 	_arc_v2_irq_unit_int_disable(irq);
 	irq_unlock(key);
@@ -79,7 +79,7 @@ void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
 {
 	ARG_UNUSED(flags);
 
-	int key = irq_lock();
+	unsigned int key = irq_lock();
 
 	__ASSERT(prio < CONFIG_NUM_IRQ_PRIO_LEVELS,
 		 "invalid priority %d for irq %d", prio, irq);

arch/arc/core/irq_offload.c

@@ -22,13 +22,15 @@ void _irq_do_offload(void)
 
 void irq_offload(irq_offload_routine_t routine, void *parameter)
 {
-	int key;
+	unsigned int key;
 
 	key = irq_lock();
 	offload_routine = routine;
 	offload_param = parameter;
 
-	__asm__ volatile ("trap_s 0");
+	__asm__ volatile ("trap_s %[id]"
+		:
+		: [id] "i"(_TRAP_S_SCALL_IRQ_OFFLOAD) : );
 
 	irq_unlock(key);
 }

arch/arc/core/isr_wrapper.S

@@ -19,6 +19,7 @@
 #include <sw_isr_table.h>
 #include <kernel_structs.h>
 #include <arch/cpu.h>
+#include <swap_macros.h>
 
 GTEXT(_isr_wrapper)
 GTEXT(_isr_demux)
@@ -229,6 +230,43 @@ From RIRQ:
  */
 
 SECTION_FUNC(TEXT, _isr_wrapper)
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	push_s r0
+	push_s blink
+	push_s r13
+	push_s r12
+	push r11
+	push r10
+	push r9
+	push r8
+	push r7
+	push r6
+	push r5
+	push r4
+	push_s r3
+	push_s r2
+	push_s r1
+
+	bl read_timer_start_of_isr
+
+	pop_s r1
+	pop_s r2
+	pop_s r3
+	pop r4
+	pop r5
+	pop r6
+	pop r7
+	pop r8
+	pop r9
+	pop r10
+	pop r11
+	pop_s r12
+	pop_s r13
+	pop_s blink
+	pop_s r0
+
+#endif
+
 #if CONFIG_ARC_FIRQ
 #if CONFIG_RGF_NUM_BANKS == 1
 	st r0,[saved_r0]
@@ -288,34 +326,20 @@ rirq_path:
 	j_s [r2]
 #endif
 #else
+
 	mov r3, _rirq_exit
 	mov r2, _rirq_enter
 	j_s [r2]
 #endif
 
-#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
-GTEXT(_sys_k_event_logger_exit_sleep)
-
-.macro log_sleep_k_event
-	clri r0 /* do not interrupt event logger operations */
-	push_s r0
-	push_s blink
-	jl _sys_k_event_logger_exit_sleep
-	pop_s blink
-	pop_s r0
-	seti r0
-.endm
-#else
-	#define log_sleep_k_event
-#endif
-#if defined(CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT)
-GTEXT(_sys_k_event_logger_interrupt)
+#if defined(CONFIG_TRACING)
+GTEXT(z_sys_trace_isr_enter)
 
 .macro log_interrupt_k_event
 	clri r0 /* do not interrupt event logger operations */
 	push_s r0
 	push_s blink
-	jl _sys_k_event_logger_interrupt
+	jl z_sys_trace_isr_enter
 	pop_s blink
 	pop_s r0
 	seti r0
@@ -356,7 +380,6 @@ SECTION_FUNC(TEXT, _isr_demux)
 	/* r0 is available to be stomped here, and exit_tickless_idle uses it */
 	exit_tickless_idle
 	log_interrupt_k_event
-	log_sleep_k_event
 
 	lr r0, [_ARC_V2_ICAUSE]
 	/* handle software triggered interrupt */
@@ -371,6 +394,42 @@ irq_hint_handled:
 	add3 r0, r1, r0   /* table entries are 8-bytes wide */
 
 	ld_s r1, [r0, 4] /* ISR into r1 */
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	push_s r0
+	push_s blink
+	push_s r13
+	push_s r12
+	push r11
+	push r10
+	push r9
+	push r8
+	push r7
+	push r6
+	push r5
+	push r4
+	push_s r3
+	push_s r2
+	push_s r1
+
+	bl read_timer_end_of_isr
+
+	pop_s r1
+	pop_s r2
+	pop_s r3
+	pop r4
+	pop r5
+	pop r6
+	pop r7
+	pop r8
+	pop r9
+	pop r10
+	pop r11
+	pop_s r12
+	pop_s r13
+	pop_s blink
+	pop_s r0
+
+#endif
 	jl_s.d [r1]
 	ld_s r0, [r0] /* delay slot: ISR parameter into r0  */
 

arch/arc/core/mpu/CMakeLists.txt

@@ -1,2 +1,4 @@
-zephyr_sources_if_kconfig(arc_core_mpu.c)
-zephyr_sources_if_kconfig(arc_mpu.c)
+zephyr_library()
+
+zephyr_library_sources_if_kconfig(arc_core_mpu.c)
+zephyr_library_sources_if_kconfig(arc_mpu.c)

arch/arc/core/mpu/Kconfig

@@ -6,8 +6,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 config ARC_MPU_VER
-	int
-	prompt "ARC MPU version"
+	int "ARC MPU version"
 	range 2 4
 	default 2
 	help
@@ -17,14 +16,12 @@ config ARC_MPU_VER
 config ARC_CORE_MPU
 	bool "ARC Core MPU functionalities"
 	depends on CPU_HAS_MPU
-	default n
 	help
 	  ARC core MPU functionalities
 
 config MPU_STACK_GUARD
 	bool "Thread Stack Guards"
 	depends on ARC_CORE_MPU && !ARC_STACK_CHECKING
-	default n
 	help
 	  Enable thread stack guards via MPU. ARC supports built-in stack protection.
 	  If your core supports that, it is preferred over MPU stack guard
@@ -35,6 +32,5 @@ config ARC_MPU
 	select ARC_CORE_MPU
 	select THREAD_STACK_INFO
 	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if ARC_MPU_VER = 2
-	default n
 	help
 	  Target has ARC MPU (currently only works for EMSK 2.2/2.3 ARCEM7D)

arch/arc/core/mpu/arc_core_mpu.c

@@ -60,6 +60,7 @@ void configure_mpu_stack_guard(struct k_thread *thread)
 		arc_core_mpu_configure(THREAD_STACK_GUARD_REGION,
 			thread->arch.priv_stack_start - STACK_GUARD_SIZE,
 			STACK_GUARD_SIZE);
+		return;
 	}
 #endif
 	arc_core_mpu_configure(THREAD_STACK_GUARD_REGION,

arch/arc/core/mpu/arc_mpu.c

@@ -296,7 +296,8 @@ void arc_core_mpu_enable(void)
 	 * simulate MPU enable
 	 */
 #elif CONFIG_ARC_MPU_VER == 3
-	arc_core_mpu_default(0);
+#define MPU_ENABLE_ATTR   0
+	arc_core_mpu_default(MPU_ENABLE_ATTR);
 #endif
 }
 
@@ -506,7 +507,8 @@ void arc_core_mpu_configure_mem_domain(struct k_mem_domain *mem_domain)
  * it doesn't work for memory domain, because the dynamic region numbers.
  * So be careful to avoid the overlap situation.
  */
-	for (; region_index <  _get_num_regions() - 1; region_index++) {
+	u32_t num_regions = _get_num_regions() - 1;
+	for (; region_index < num_regions; region_index++) {
 #endif
 		if (num_partitions && pparts->size) {
 			SYS_LOG_DBG("set region 0x%x 0x%x 0x%x",

arch/arc/core/offsets/offsets.c

@@ -30,7 +30,12 @@ GEN_OFFSET_SYM(_thread_arch_t, intlock_key);
 GEN_OFFSET_SYM(_thread_arch_t, relinquish_cause);
 GEN_OFFSET_SYM(_thread_arch_t, return_value);
 #ifdef CONFIG_ARC_STACK_CHECKING
-GEN_OFFSET_SYM(_thread_arch_t, stack_base);
+GEN_OFFSET_SYM(_thread_arch_t, k_stack_base);
+GEN_OFFSET_SYM(_thread_arch_t, k_stack_top);
+#ifdef CONFIG_USERSPACE
+GEN_OFFSET_SYM(_thread_arch_t, u_stack_base);
+GEN_OFFSET_SYM(_thread_arch_t, u_stack_top);
+#endif
 #endif
 
 /* ARCv2-specific IRQ stack frame structure member offsets */
@@ -58,6 +63,9 @@ GEN_OFFSET_SYM(_isf_t, ldi_base);
 GEN_OFFSET_SYM(_isf_t, jli_base);
 #endif
 GEN_OFFSET_SYM(_isf_t, pc);
+#ifdef CONFIG_ARC_HAS_SECURE
+GEN_OFFSET_SYM(_isf_t, sec_stat);
+#endif
 GEN_OFFSET_SYM(_isf_t, status32);
 GEN_ABSOLUTE_SYM(___isf_t_SIZEOF, sizeof(_isf_t));
 

arch/arc/core/regular_irq.S

@@ -53,10 +53,18 @@ SECTION_FUNC(TEXT, _rirq_enter)
 
 
 #ifdef CONFIG_ARC_STACK_CHECKING
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr r2, [_ARC_V2_SEC_STAT]
+	bclr r2, r2, _ARC_V2_SEC_STAT_SSC_BIT
+	/* sflag r2 */
+	/* sflag instruction is not supported in current ARC GNU */
+	.long 0x00bf302f
+#else
 	/* disable stack checking */
 	lr r2, [_ARC_V2_STATUS32]
 	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
 	kflag r2
+#endif
 #endif
 	clri
 	ld r1, [exc_nest_count]
@@ -95,6 +103,10 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	bne.d	_rirq_return_from_rirq
 	st	r0, [r1]
 
+#ifdef CONFIG_STACK_SENTINEL
+	bl _check_stack_sentinel
+#endif
+
 #ifdef CONFIG_PREEMPT_ENABLED
 
 	mov r1, _kernel
@@ -105,16 +117,6 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	 * point on until return from interrupt.
 	 */
 
-
-	/*
-	 * Non-preemptible thread ? Do not schedule (see explanation of
-	 * preempt field in kernel_struct.h).
-	 */
-	ldh_s r0, [r2, _thread_offset_to_preempt]
-	mov r3, _NON_PREEMPT_THRESHOLD
-	cmp_s r0, r3
-	bhs.d _rirq_no_reschedule
-
 	/*
 	 * Both (a)reschedule and (b)non-reschedule cases need to load the
 	 * current thread's stack, but don't have to use it until the decision
@@ -149,11 +151,7 @@ _rirq_common_interrupt_swap:
 	/* r2 contains pointer to new thread */
 
 #ifdef CONFIG_ARC_STACK_CHECKING
-	/* Use stack top and base registers from restored context */
-	ld r3, [r2, _thread_offset_to_stack_base]
-	sr r3, [_ARC_V2_KSTACK_BASE]
-	ld r3, [r2, _thread_offset_to_stack_top]
-	sr r3, [_ARC_V2_KSTACK_TOP]
+	_load_stack_check_regs
 #endif
 	/*
 	 * _load_callee_saved_regs expects incoming thread in r2.

arch/arc/core/reset.S

@@ -44,8 +44,18 @@ GTEXT(__start)
 SECTION_FUNC(TEXT,__reset)
 SECTION_FUNC(TEXT,__start)
 
-	/* lock interrupts: will get unlocked when switch to main task */
-	clri
+	/* lock interrupts: will get unlocked when switch to main task
+	 * also make sure the processor in the correct status
+	 */
+	mov r0, 0
+	kflag r0
+
+	/* interrupt related init */
+	sr r0, [_ARC_V2_AUX_IRQ_ACT]
+	sr r0, [_ARC_V2_AUX_IRQ_CTRL]
+	sr r0, [_ARC_V2_AUX_IRQ_HINT]
+
+	/* \todo: MPU init, gp for small data? */
 
 #if CONFIG_USERSPACE
 	lr r0, [_ARC_V2_STATUS32]

arch/arc/core/swap.S

@@ -61,6 +61,21 @@ GDATA(_kernel)
 
 SECTION_FUNC(TEXT, __swap)
 
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+	_save_callee_saved_regs
+	push_s r31
+
+	bl read_timer_start_of_swap
+
+	pop_s r31
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+	_load_callee_saved_regs
+	st sp, [r2, _thread_offset_to_sp]
+#endif
+
 	/* interrupts are locked, interrupt key is in r0 */
 
 	mov r1, _kernel
@@ -85,16 +100,25 @@ SECTION_FUNC(TEXT, __swap)
 	 */
 	lr r3, [_ARC_V2_STATUS32]
 	push_s r3
-#ifdef CONFIG_ARC_STACK_CHECKING
-	/* disable stack checking during swap */
-	bclr r3, r3, _ARC_V2_STATUS32_SC_BIT
-	kflag r3
-#endif
 
 #ifdef CONFIG_ARC_HAS_SECURE
 	lr r3, [_ARC_V2_SEC_STAT]
 	push_s r3
 #endif
+
+#ifdef CONFIG_ARC_STACK_CHECKING
+#ifdef CONFIG_ARC_HAS_SECURE
+	bclr r3, r3, _ARC_V2_SEC_STAT_SSC_BIT
+	/* sflag r3 */
+	/* sflag instruction is not supported in current ARC GNU */
+	.long 0x00ff302f
+#else
+	/* disable stack checking during swap */
+	bclr r3, r3, _ARC_V2_STATUS32_SC_BIT
+	kflag r3
+#endif
+#endif
+
 	push_s blink
 
 	_save_callee_saved_regs
@@ -104,11 +128,7 @@ SECTION_FUNC(TEXT, __swap)
 
 	/* entering here, r2 contains the new current thread */
 #ifdef CONFIG_ARC_STACK_CHECKING
-	/* Use stack top and base registers from restored context */
-	ld r3, [r2, _thread_offset_to_stack_base]
-	sr r3, [_ARC_V2_KSTACK_BASE]
-	ld r3, [r2, _thread_offset_to_stack_top]
-	sr r3, [_ARC_V2_KSTACK_TOP]
+	_load_stack_check_regs
 #endif
 	/* XXX - can be moved to delay slot of _CAUSE_RIRQ ? */
 	st_s r2, [r1, _kernel_offset_to_current]
@@ -148,6 +168,11 @@ _swap_return_from_coop:
 	/* sflag instruction is not supported in current ARC GNU */
 	.long 0x00ff302f
 #endif
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	b _capture_value_for_benchmarking
+#endif
+return_loc:
+
 	pop_s r3    /* status32 into r3 */
 	kflag r3    /* write status32 */
 
@@ -200,4 +225,24 @@ _return_from_exc:
 	ld ilink, [sp, ___isf_t_status32_OFFSET - ___isf_t_pc_OFFSET]
 	sr ilink, [_ARC_V2_ERSTATUS]
 	add_s sp, sp, ___isf_t_status32_OFFSET - ___isf_t_pc_OFFSET + 4
+
 	rtie
+
+
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	.balign 4
+_capture_value_for_benchmarking:
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+	_save_callee_saved_regs
+	push_s blink
+
+	bl read_timer_end_of_swap
+
+	pop_s blink
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+	_load_callee_saved_regs
+	st sp, [r2, _thread_offset_to_sp]
+	b return_loc
+#endif /* CONFIG_EXECUTION_BENCHMARKING */

arch/arc/core/sys_fatal_error_handler.c

@@ -37,23 +37,32 @@
  *
  * @return N/A
  */
-FUNC_NORETURN __weak void _SysFatalErrorHandler(unsigned int reason,
+__weak void _SysFatalErrorHandler(unsigned int reason,
 						const NANO_ESF *pEsf)
 {
 	ARG_UNUSED(pEsf);
 
 #if !defined(CONFIG_SIMPLE_FATAL_ERROR_HANDLER)
+#if defined(CONFIG_STACK_SENTINEL)
+	if (reason == _NANO_ERR_STACK_CHK_FAIL) {
+		goto hang_system;
+	}
+#endif
 	if (reason == _NANO_ERR_KERNEL_PANIC) {
 		goto hang_system;
 	}
-	if (k_is_in_isr() || _is_thread_essential()) {
-		printk("Fatal fault in %s! Spinning...\n",
-		       k_is_in_isr() ? "ISR" : "essential thread");
+
+	if (_is_thread_essential()) {
+		printk("Fatal fault in essential thread! Spinning...\n");
 		goto hang_system;
 	}
+
 	printk("Fatal fault in thread %p! Aborting.\n", _current);
+
 	k_thread_abort(_current);
 
+	return;
+
 hang_system:
 #else
 	ARG_UNUSED(reason);
@@ -62,5 +71,4 @@ hang_system:
 	for (;;) {
 		k_cpu_idle();
 	}
-	CODE_UNREACHABLE;
 }

arch/arc/core/thread.c

@@ -71,20 +71,42 @@ void _new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	_ASSERT_VALID_PRIO(priority, pEntry);
 
 	char *stackEnd;
+	char *stackAdjEnd;
 	struct init_stack_frame *pInitCtx;
 
 #if CONFIG_USERSPACE
+/* adjust stack and stack size */
 #if CONFIG_ARC_MPU_VER == 2
 	stackSize = POW2_CEIL(STACK_SIZE_ALIGN(stackSize));
 #elif CONFIG_ARC_MPU_VER == 3
 	stackSize = ROUND_UP(stackSize, STACK_ALIGN);
-#endif
 #endif
 	stackEnd = pStackMem + stackSize;
 
-#if CONFIG_USERSPACE
+	if (options & K_USER) {
+		thread->arch.priv_stack_start =
+			(u32_t)(stackEnd + STACK_GUARD_SIZE);
+		thread->arch.priv_stack_size =
+			(u32_t)(CONFIG_PRIVILEGED_STACK_SIZE);
+
+		stackAdjEnd = (char *)STACK_ROUND_DOWN(stackEnd + STACK_GUARD_SIZE +
+					CONFIG_PRIVILEGED_STACK_SIZE);
+
+		/* reserve 4 bytes for the start of user sp */
+		stackAdjEnd -= 4;
+		(*(u32_t *)stackAdjEnd) = (u32_t)stackEnd;
+
+#ifdef CONFIG_THREAD_USERSPACE_LOCAL_DATA
+		/* reserve stack space for the userspace local data struct */
+		thread->userspace_local_data =
+			(struct _thread_userspace_local_data *)
+			STACK_ROUND_DOWN(stackEnd - sizeof(*thread->userspace_local_data));
+		/* update the start of user sp */
+		(*(u32_t *)stackAdjEnd) = (u32_t) thread->userspace_local_data;
+#endif
+
+	} else {
 	/* for kernel thread, the privilege stack is merged into thread stack */
-	if (!(options & K_USER)) {
 	/* if MPU_STACK_GUARD is enabled, reserve the the stack area
 	 * |---------------------|    |----------------|
 	 * |  user stack         |    | stack guard    |
@@ -97,20 +119,57 @@ void _new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 		pStackMem += STACK_GUARD_SIZE;
 		stackSize = stackSize + CONFIG_PRIVILEGED_STACK_SIZE;
 		stackEnd += CONFIG_PRIVILEGED_STACK_SIZE + STACK_GUARD_SIZE;
-	}
+
+		thread->arch.priv_stack_start = 0;
+		thread->arch.priv_stack_size = 0;
+
+		stackAdjEnd = (char *)STACK_ROUND_DOWN(stackEnd);
+
+#ifdef CONFIG_THREAD_USERSPACE_LOCAL_DATA
+		/* reserve stack space for the userspace local data struct */
+		stackAdjEnd = (char *)STACK_ROUND_DOWN(stackEnd
+			- sizeof(*thread->userspace_local_data));
+		thread->userspace_local_data =
+			(struct _thread_userspace_local_data *)stackAdjEnd;
 #endif
+	}
+
 	_new_thread_init(thread, pStackMem, stackSize, priority, options);
 
-	/* carve the thread entry struct from the "base" of the stack */
-	pInitCtx = (struct init_stack_frame *)(STACK_ROUND_DOWN(stackEnd) -
-				       sizeof(struct init_stack_frame));
-#if CONFIG_USERSPACE
+
+	/* carve the thread entry struct from the "base" of
+		the privileged stack */
+	pInitCtx = (struct init_stack_frame *)(
+		stackAdjEnd - sizeof(struct init_stack_frame));
+
+	/* fill init context */
+	pInitCtx->status32 = 0;
 	if (options & K_USER) {
 		pInitCtx->pc = ((u32_t)_user_thread_entry_wrapper);
 	} else {
 		pInitCtx->pc = ((u32_t)_thread_entry_wrapper);
 	}
-#else
+
+	/*
+	 * enable US bit, US is read as zero in user mode. This will allow use
+	 * mode sleep instructions, and it enables a form of denial-of-service
+	 * attack by putting the processor in sleep mode, but since interrupt
+	 * level/mask can't be set from user space that's not worse than
+	 * executing a loop without yielding.
+	 */
+	pInitCtx->status32 |= _ARC_V2_STATUS32_US;
+#else /* For no USERSPACE feature */
+	stackEnd = pStackMem + stackSize;
+
+	_new_thread_init(thread, pStackMem, stackSize, priority, options);
+
+	stackAdjEnd = stackEnd;
+
+	pInitCtx = (struct init_stack_frame *)(
+		STACK_ROUND_DOWN(stackAdjEnd) -
+		sizeof(struct init_stack_frame));
+
+	pInitCtx->status32 = 0;
 	pInitCtx->pc = ((u32_t)_thread_entry_wrapper);
 #endif
 
@@ -122,64 +181,49 @@ void _new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	pInitCtx->r1 = (u32_t)parameter1;
 	pInitCtx->r2 = (u32_t)parameter2;
 	pInitCtx->r3 = (u32_t)parameter3;
+
+/* stack check configuration */
+#ifdef CONFIG_ARC_STACK_CHECKING
+#ifdef CONFIG_ARC_HAS_SECURE
+	pInitCtx->sec_stat |= _ARC_V2_SEC_STAT_SSC;
+#else
+	pInitCtx->status32 |= _ARC_V2_STATUS32_SC;
+#endif
+#ifdef CONFIG_USERSPACE
+	if (options & K_USER) {
+		thread->arch.u_stack_top = (u32_t)pStackMem;
+		thread->arch.u_stack_base = (u32_t)stackEnd;
+		thread->arch.k_stack_top =
+			 (u32_t)(stackEnd + STACK_GUARD_SIZE);
+		thread->arch.k_stack_base = (u32_t)
+		(stackEnd + STACK_GUARD_SIZE + CONFIG_PRIVILEGED_STACK_SIZE);
+	} else {
+		thread->arch.k_stack_top = (u32_t)pStackMem;
+		thread->arch.k_stack_base = (u32_t)stackEnd;
+		thread->arch.u_stack_top = 0;
+		thread->arch.u_stack_base = 0;
+	}
+#else
+	thread->arch.k_stack_top = (u32_t) pStackMem;
+	thread->arch.k_stack_base = (u32_t) stackEnd;
+#endif
+#endif
 	/*
-	 * For now set the interrupt priority to 15
-	 * we can leave interrupt enable flag set to 0 as
 	 * seti instruction in the end of the _Swap() will
 	 * enable the interrupts based on intlock_key
 	 * value.
-	 */
-#ifdef CONFIG_ARC_STACK_CHECKING
-	pInitCtx->status32 = _ARC_V2_STATUS32_SC |
-		 _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
-	thread->arch.stack_base = (u32_t) stackEnd;
-#else
-	pInitCtx->status32 = _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
-#endif
-
-#if CONFIG_USERSPACE
-	/*
-	 * enable US bit, US is read as zero in user mode. This will allow use
-	 * mode sleep instructions, and it enables a form of denial-of-service
-	 * attack by putting the processor in sleep mode, but since interrupt
-	 * level/mask can't be set from user space that's not worse than
-	 * executing a loop without yielding.
-	 */
-	pInitCtx->status32 |= _ARC_V2_STATUS32_US;
-
-	if (options & K_USER) {
-		thread->arch.priv_stack_start =
-			(u32_t) (stackEnd + STACK_GUARD_SIZE);
-		thread->arch.priv_stack_size =
-			(u32_t)CONFIG_PRIVILEGED_STACK_SIZE;
-	} else {
-		thread->arch.priv_stack_start = 0;
-		thread->arch.priv_stack_size = 0;
-	}
-#endif
-
-#ifdef CONFIG_THREAD_MONITOR
-	/*
-	 * In debug mode thread->entry give direct access to the thread entry
-	 * and the corresponding parameters.
-	 */
-	thread->entry = (struct __thread_entry *)(pInitCtx);
-#endif
-
-	/*
+	 *
 	 * intlock_key is constructed based on ARCv2 ISA Programmer's
 	 * Reference Manual CLRI instruction description:
 	 * dst[31:6] dst[5] dst[4]       dst[3:0]
 	 *    26'd0    1    STATUS32.IE  STATUS32.E[3:0]
 	 */
-	thread->arch.intlock_key = 0x3F;
+	thread->arch.intlock_key = 0x30 | (_ARC_V2_DEF_IRQ_LEVEL & 0xf);
 	thread->arch.relinquish_cause = _CAUSE_COOP;
 	thread->callee_saved.sp =
 		(u32_t)pInitCtx - ___callee_saved_stack_t_SIZEOF;
 
 	/* initial values in all other regs/k_thread entries are irrelevant */
-
-	thread_monitor_init(thread);
 }
 
 
@@ -188,10 +232,9 @@ void _new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 FUNC_NORETURN void _arch_user_mode_enter(k_thread_entry_t user_entry,
 	void *p1, void *p2, void *p3)
 {
-	_current->base.user_options |= K_USER;
 
 	/*
-	 * ajust the thread stack layout
+	 * adjust the thread stack layout
 	 * |----------------|    |---------------------|
 	 * | stack guard    |    |  user stack         |
 	 * |----------------| to |---------------------|
@@ -204,11 +247,20 @@ FUNC_NORETURN void _arch_user_mode_enter(k_thread_entry_t user_entry,
 	_current->stack_info.size -= CONFIG_PRIVILEGED_STACK_SIZE;
 
 	_current->arch.priv_stack_start =
-			(u32_t) (_current->stack_info.start +
-				 _current->stack_info.size + STACK_GUARD_SIZE);
+			(u32_t)(_current->stack_info.start +
+				_current->stack_info.size + STACK_GUARD_SIZE);
 	_current->arch.priv_stack_size =
 			(u32_t)CONFIG_PRIVILEGED_STACK_SIZE;
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	_current->arch.k_stack_top = _current->arch.priv_stack_start;
+	_current->arch.k_stack_base = _current->arch.priv_stack_start +
+				_current->arch.priv_stack_size;
+	_current->arch.u_stack_top = _current->stack_info.start;
+	_current->arch.u_stack_base = _current->stack_info.start +
+				_current->stack_info.size;
+#endif
+
 	/* possible optimizaiton: no need to load mem domain anymore */
 	/* need to lock cpu here ? */
 	configure_mpu_thread(_current);

arch/arc/core/userspace.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 Synopsys.
+ * Copyright (c) 2018 Synopsys.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,68 +10,70 @@
 #include <kernel_structs.h>
 #include <arch/cpu.h>
 #include <syscall.h>
+#include <swap_macros.h>
 
 .macro clear_scratch_regs
-	mov	r1, 0
-	mov 	r2, 0
-	mov	r3, 0
-	mov	r4, 0
-	mov	r5, 0
-	mov	r6, 0
-	mov	r7, 0
-	mov	r8, 0
-	mov 	r9, 0
-	mov	r10, 0
-	mov	r11, 0
-	mov	r12, 0
-
-	mov 	fp, 0
-	mov 	r29, 0
-	mov 	r30, 0
-	mov	blink, 0
+	mov r1, 0
+	mov r2, 0
+	mov r3, 0
+	mov r4, 0
+	mov r5, 0
+	mov r6, 0
+	mov r7, 0
+	mov r8, 0
+	mov r9, 0
+	mov r10, 0
+	mov r11, 0
+	mov r12, 0
 .endm
 
 .macro clear_callee_regs
-	mov	r25, 0
-	mov	r24, 0
-	mov	r23, 0
-	mov	r22, 0
-	mov	r21, 0
-	mov	r20, 0
-	mov	r19, 0
-	mov	r18, 0
-	mov	r17, 0
-	mov	r16, 0
+	mov r25, 0
+	mov r24, 0
+	mov r23, 0
+	mov r22, 0
+	mov r21, 0
+	mov r20, 0
+	mov r19, 0
+	mov r18, 0
+	mov r17, 0
+	mov r16, 0
 
-	mov	r15, 0
-	mov	r14, 0
-	mov	r13, 0
+	mov r15, 0
+	mov r14, 0
+	mov r13, 0
 .endm
 
 GTEXT(_arc_userspace_enter)
 GTEXT(_arc_do_syscall)
 GTEXT(_user_thread_entry_wrapper)
-
-
-
+GTEXT(z_arch_user_string_nlen)
+GTEXT(z_arch_user_string_nlen_fault_start)
+GTEXT(z_arch_user_string_nlen_fault_end)
+GTEXT(z_arch_user_string_nlen_fixup)
 /*
  * @brief Wrapper for _thread_entry in the case of user thread
+ * The init parameters are in privileged stack
  *
  * @return N/A
  */
 SECTION_FUNC(TEXT, _user_thread_entry_wrapper)
-	/* sp the  user stack pointer,  r0-r4 are in stack */
-	mov r5, sp
-	/* start of privilege stack */
-	add blink, r5, CONFIG_PRIVILEGED_STACK_SIZE+16
+	pop_s r3
+	pop_s r2
+	pop_s r1
+	pop_s r0
+/* the start of user sp is in r5 */
+	pop r5
+/* start of privilege stack in blink */
+	mov blink, sp
 
-	/* r4<- start  of user stack region */
-	mov r0, _kernel
-	ld_s r1, [r0, _kernel_offset_to_current]
-	ld r4, [r1, ___thread_stack_info_t_start_OFFSET]
+	st.aw r0, [r5, -4]
+	st.aw r1, [r5, -4]
+	st.aw r2, [r5, -4]
+	st.aw r3, [r5, -4]
 
 /*
- * when CONFIG_INIT_STACK is enable, stack will be initialized
+ * when CONFIG_INIT_STACKS is enable, stack will be initialized
  * in _new_thread_init.
  */
 	j _arc_go_to_user_space
@@ -89,10 +91,24 @@ SECTION_FUNC(TEXT, _arc_userspace_enter)
 	/*
 	 * In ARCv2, the U bit can only be set through exception return
 	 */
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* disable stack checking as the stack should be initialized */
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr blink, [_ARC_V2_SEC_STAT]
+	bclr blink, blink, _ARC_V2_SEC_STAT_SSC_BIT
+	/* sflag blink */
+	/* sflag instruction is not supported in current ARC GNU */
+	.long 0x07ff302f
+#else
+	lr blink, [_ARC_V2_STATUS32]
+	bclr blink, blink, _ARC_V2_STATUS32_SC_BIT
+	kflag blink
+#endif
+#endif
 	/* the end of user stack in r5 */
 	add r5, r4, r5
 	/* start of privilege stack */
-	add blink, r5, CONFIG_PRIVILEGED_STACK_SIZE
+	add blink, r5, CONFIG_PRIVILEGED_STACK_SIZE+STACK_GUARD_SIZE
 	mov sp, r5
 
 	push_s r0
@@ -112,6 +128,25 @@ _clear_user_stack:
 	cmp r4, r5
 	jlt _clear_user_stack
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+
+	_load_stack_check_regs
+
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr r0, [_ARC_V2_SEC_STAT]
+	bset r0, r0, _ARC_V2_SEC_STAT_SSC_BIT
+	/* sflag r0 */
+	/* sflag instruction is not supported in current ARC GNU */
+	.long 0x003f302f
+#else
+	lr r0, [_ARC_V2_STATUS32]
+	bset r0, r0, _ARC_V2_STATUS32_SC_BIT
+	kflag r0
+#endif
+#endif
+
 _arc_go_to_user_space:
 	lr r0, [_ARC_V2_STATUS32]
 	bset r0, r0, _ARC_V2_STATUS32_U_BIT
@@ -144,6 +179,16 @@ _arc_go_to_user_space:
 
 	clear_scratch_regs
 
+	mov fp, 0
+	mov r29, 0
+	mov r30, 0
+	mov blink, 0
+
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	b _capture_value_for_benchmarking_userspace
+return_loc_userspace_enter:
+#endif /* CONFIG_EXECUTION_BENCHMARKING */
+
 	rtie
 
 /**
@@ -166,24 +211,100 @@ SECTION_FUNC(TEXT, _arc_do_syscall)
 
 	jl [r6]
 
+	/*
+	 * no need to clear callee regs, as they will be saved and restored
+	 * automatically
+	 */
+	clear_scratch_regs
+
+	mov r29, 0
+	mov r30, 0
+
 	pop_s blink
 
 	/* through fake exception return, go back to the caller */
 	kflag _ARC_V2_STATUS32_AE
 
-#ifdef CONFIG_ARC_HAS_SECURE
-	lr r6, [_ARC_V2_SEC_STAT]
-	/* the mode returns from exception return is secure mode */
-	bset r6, r6, 31
-	sr r6, [_ARC_V2_ERSEC_STAT]
-#endif
-	/* the status and return addesss are saved in trap_s handler */
+	/* the status and return address are saved in trap_s handler */
 	pop r6
 	sr r6, [_ARC_V2_ERSTATUS]
 	pop r6
 	sr r6, [_ARC_V2_ERET]
+#ifdef CONFIG_ARC_HAS_SECURE
+	pop r6
+	sr r6, [_ARC_V2_ERSEC_STAT]
+#endif
 
-	/* no nned to clear callee regs */
-	clear_scratch_regs
+	mov r6, 0
 
 	rtie
+
+
+/*
+ * size_t z_arch_user_string_nlen(const char *s, size_t maxsize, int *err_arg)
+ */
+SECTION_FUNC(TEXT, z_arch_user_string_nlen)
+	/* int err; */
+	sub_s sp,sp,0x4
+
+	/* Initial error value (-1 failure), store at [sp,0] */
+	mov_s r3, -1
+	st_s r3, [sp, 0]
+
+	/* Loop setup.
+	 * r12 (position locator) = s - 1
+	 * r0 (length counter return value)) = 0
+	 * lp_count = maxsize + 1
+	 * */
+	sub r12, r0, 0x1
+	mov_s r0, 0
+	add_s r1, r1, 1
+	mov lp_count, r1
+
+strlen_loop:
+z_arch_user_string_nlen_fault_start:
+	/* is the byte at ++r12 a NULL? if so, we're done. Might fault! */
+	ldb.aw r1, [r12, 1]
+
+z_arch_user_string_nlen_fault_end:
+	brne_s r1, 0, not_null
+
+strlen_done:
+	/* Success, set err to 0 */
+	mov_s r1, 0
+	st_s r1, [sp, 0]
+
+z_arch_user_string_nlen_fixup:
+	/* *err_arg = err; Pop stack and return */
+	ld_s r1, [sp, 0]
+	add_s sp, sp, 4
+	j_s.d [blink]
+	st_s r1, [r2, 0]
+
+not_null:
+	/* check if we've hit the maximum, if so we're done. */
+	brne.d.nt lp_count, 0x1, inc_len
+	sub lp_count, lp_count, 0x1
+	b_s strlen_done
+
+inc_len:
+	/* increment length measurement, loop again */
+	add_s r0, r0, 1
+	b_s strlen_loop
+
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	.balign 4
+_capture_value_for_benchmarking_userspace:
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+	_save_callee_saved_regs
+	push_s blink
+
+	bl read_timer_end_of_userspace_enter
+
+	pop_s blink
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+	_load_callee_saved_regs
+	b return_loc_userspace_enter
+#endif

arch/arc/defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARC=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
 CONFIG_CPU_ARCEM4=y
-CONFIG_CPU_ARCV2=y
 CONFIG_ARCV2_INTERRUPT_UNIT=y
 CONFIG_ARCV2_TIMER=y

arch/arc/include/kernel_arch_func.h

@@ -42,20 +42,6 @@ _set_thread_return_value(struct k_thread *thread, unsigned int value)
 	thread->arch.return_value = value;
 }
 
-static ALWAYS_INLINE int _is_in_isr(void)
-{
-	u32_t act = _arc_v2_aux_reg_read(_ARC_V2_AUX_IRQ_ACT);
-#if CONFIG_IRQ_OFFLOAD
-	/* Check if we're in a TRAP_S exception as well */
-	if (_arc_v2_aux_reg_read(_ARC_V2_STATUS32) & _ARC_V2_STATUS32_AE &&
-	    _ARC_V2_ECR_VECTOR(_arc_v2_aux_reg_read(_ARC_V2_ECR)) == EXC_EV_TRAP
-	   ) {
-		return 1;
-	}
-#endif
-	return ((act & 0xffff) != 0);
-}
-
 /**
  *
  * @brief Indicates the interrupt number of the highest priority
@@ -70,6 +56,7 @@ static ALWAYS_INLINE int _INTERRUPT_CAUSE(void)
 	return irq_num;
 }
 
+#define _is_in_isr	_arc_v2_irq_unit_is_in_isr
 
 extern void _thread_entry_wrapper(void);
 extern void _user_thread_entry_wrapper(void);

arch/arc/include/kernel_arch_thread.h

@@ -61,7 +61,12 @@ struct _thread_arch {
 	/* High address of stack region, stack grows downward from this
 	 * location. Usesd for hardware stack checking
 	 */
-	u32_t stack_base;
+	u32_t k_stack_base;
+	u32_t k_stack_top;
+#ifdef CONFIG_USERSPACE
+	u32_t u_stack_base;
+	u32_t u_stack_top;
+#endif
 #endif
 
 #ifdef CONFIG_USERSPACE

arch/arc/include/kernel_event_logger_arch.h

@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2016 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Kernel event logger support for ARM
- */
-
-#ifndef __KERNEL_EVENT_LOGGER_ARCH_H__
-#define __KERNEL_EVENT_LOGGER_ARCH_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Get the identification of the current interrupt.
- *
- * This routine obtain the key of the interrupt that is currently processed
- * if it is called from a ISR context.
- *
- * @return The key of the interrupt that is currently being processed.
- */
-int _sys_current_irq_key_get(void)
-{
-	return _INTERRUPT_CAUSE();
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __KERNEL_EVENT_LOGGER_ARCH_H__ */

arch/arc/include/offsets_short_arch.h

@@ -26,15 +26,21 @@
 #define _thread_offset_to_return_value \
 	(___thread_t_arch_OFFSET + ___thread_arch_t_return_value_OFFSET)
 
-#define _thread_offset_to_stack_base \
-	(___thread_t_arch_OFFSET + ___thread_arch_t_stack_base_OFFSET)
+#define _thread_offset_to_k_stack_base \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_k_stack_base_OFFSET)
+
+#define _thread_offset_to_k_stack_top \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_k_stack_top_OFFSET)
+
+#define _thread_offset_to_u_stack_base \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_u_stack_base_OFFSET)
+
+#define _thread_offset_to_u_stack_top \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_u_stack_top_OFFSET)
 
 #define _thread_offset_to_sp \
 	(___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET)
 
-#define _thread_offset_to_stack_top \
-	(___thread_t_stack_info_OFFSET + ___thread_stack_info_t_start_OFFSET)
-
 /* end - threads */
 
 #endif /* _offsets_short_arch__h_ */

arch/arc/include/swap_macros.h

@@ -242,6 +242,36 @@ extern "C" {
 
 .endm
 
+/*
+ * To use this macor, r2 should have the value of thread struct pointer to
+ * _kernel.current. r3 is a scratch reg.
+ */
+.macro _load_stack_check_regs
+#ifdef CONFIG_ARC_HAS_SECURE
+	ld r3, [r2, _thread_offset_to_k_stack_base]
+	sr r3, [_ARC_V2_S_KSTACK_BASE]
+	ld r3, [r2, _thread_offset_to_k_stack_top]
+	sr r3, [_ARC_V2_S_KSTACK_TOP]
+#ifdef CONFIG_USERSPACE
+	ld r3, [r2, _thread_offset_to_u_stack_base]
+	sr r3, [_ARC_V2_S_USTACK_BASE]
+	ld r3, [r2, _thread_offset_to_u_stack_top]
+	sr r3, [_ARC_V2_S_USTACK_TOP]
+#endif
+#else /* CONFIG_ARC_HAS_SECURE */
+	ld r3, [r2, _thread_offset_to_k_stack_base]
+	sr r3, [_ARC_V2_KSTACK_BASE]
+	ld r3, [r2, _thread_offset_to_k_stack_top]
+	sr r3, [_ARC_V2_KSTACK_TOP]
+#ifdef CONFIG_USERSPACE
+	ld r3, [r2, _thread_offset_to_u_stack_base]
+	sr r3, [_ARC_V2_USTACK_BASE]
+	ld r3, [r2, _thread_offset_to_u_stack_top]
+	sr r3, [_ARC_V2_USTACK_TOP]
+#endif
+#endif /* CONFIG_ARC_HAS_SECURE */
+.endm
+
 #endif /* _ASMLANGUAGE */
 
 #ifdef __cplusplus

arch/arc/include/tracing_arch.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Kernel event logger support for ARM
+ */
+
+#ifndef __KERNEL_TRACING_H__
+#define __KERNEL_TRACING_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get the identification of the current interrupt.
+ *
+ * This routine obtain the key of the interrupt that is currently processed
+ * if it is called from a ISR context.
+ *
+ * @return The key of the interrupt that is currently being processed.
+ */
+int _sys_current_irq_key_get(void)
+{
+	return _INTERRUPT_CAUSE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __KERNEL_TRACING_H__ */

arch/arc/soc/em11d/CMakeLists.txt

@@ -1,14 +0,0 @@
-zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
-
-zephyr_cc_option(-mcpu=em4_fpuda -mno-sdata -mdiv-rem -mswap -mnorm)
-zephyr_cc_option(-mmpy-option=6 -mbarrel-shifter)
-zephyr_cc_option(--param l1-cache-size=16384)
-zephyr_cc_option(--param l1-cache-line-size=32)
-zephyr_cc_option_ifdef(CONFIG_CODE_DENSITY -mcode-density)
-zephyr_cc_option_ifdef(CONFIG_FLOAT -mfpu=fpuda_all)
-
-
-zephyr_sources(
-  soc.c
-  soc_config.c
-  )

arch/arc/soc/em11d/Kconfig.defconfig

@@ -1,63 +0,0 @@
-#
-# Copyright (c) 2014 Wind River Systems, Inc.
-# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-if SOC_EM11D
-
-config SOC
-	default em11d
-
-config NUM_IRQ_PRIO_LEVELS
-	# This processor supports 4 priority levels:
-	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
-	default 4
-
-config NUM_IRQS
-	# must be > the highest interrupt number used
-	default 38 if BOARD_EM_STARTERKIT_R23
-	default 36 if BOARD_EM_STARTERKIT_R22
-
-config RGF_NUM_BANKS
-	default 2
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 20000000
-
-config HARVARD
-	def_bool n
-
-config FLASH_BASE_ADDRESS
-	default 0x00000000
-
-config FLASH_SIZE
-	default 0
-	# em11d has no FLASH so size is 0.
-
-config SRAM_BASE_ADDRESS
-	default 0x10000000
-
-config SRAM_SIZE
-	default 131072
-
-config ICCM_BASE_ADDRESS
-	default 0x00000000
-
-config ICCM_SIZE
-	default 64
-
-config DCCM_BASE_ADDRESS
-	default 0x80000000
-
-config DCCM_SIZE
-	default 64
-
-config CACHE_FLUSHING
-	def_bool y
-
-config FP_FPU_DA
-	def_bool y
-
-endif #SOC_EM11D

arch/arc/soc/em11d/Kconfig.soc

@@ -1,5 +0,0 @@
-
-config SOC_EM11D
-	bool "Synopsys ARC EM11D"
-	select CPU_HAS_FPU
-

arch/arc/soc/em11d/linker.ld

@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Linker script for the Synopsys EM Starterkit v2.2 EM11D platform.
- */
-
-/*
- * DRAM base address and size
- *
- * DRAM includes the exception vector table at reset, which is at
- * the beginning of the region.
- */
-#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
-#define SRAM_SIZE		CONFIG_SRAM_SIZE
-/* TODO: Using SRAM config for now, even though this is really DRAM. */
-
-/* Instruction Closely Coupled Memory (ICCM) base address and size */
-#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
-#define ICCM_SIZE		CONFIG_ICCM_SIZE
-
-/*
- * DCCM base address and size. DCCM is the data memory.
- */
-/* Data Closely Coupled Memory (DCCM) base address and size */
-#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
-#define DCCM_SIZE		CONFIG_DCCM_SIZE
-
-#include <arch/arc/v2/linker.ld>

arch/arc/soc/em11d/soc.h

@@ -1,137 +0,0 @@
-/*
- * Copyright (c) 2016-2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Board configuration macros for EM Starter kit board
- *
- * This header file is used to specify and describe board-level
- * aspects for the target.
- */
-
-#ifndef _SOC__H_
-#define _SOC__H_
-
-#include <misc/util.h>
-
-/* default system clock */
-/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
-#define SYSCLK_DEFAULT_IOSC_HZ			MHZ(50)
-
-
-/* ARC EM Core IRQs */
-#define IRQ_TIMER0				16
-#define IRQ_TIMER1				17
-
-#define IRQ_CORE_DMA_COMPLETE			20
-#define IRQ_CORE_DMA_ERROR			21
-
-#ifndef _ASMLANGUAGE
-
-#include <misc/util.h>
-#include <random/rand32.h>
-
-#define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
-#define ARCV2_TIMER0_INT_PRI			0
-
-#define ARCV2_TIMER1_INT_LVL			IRQ_TIMER1
-#define ARCV2_TIMER1_INT_PRI			1
-
-#define CONFIG_ARCV2_TIMER1_INT_LVL		IRQ_TIMER1
-#define CONFIG_ARCV2_TIMER1_INT_PRI		1
-
-#define INT_ENABLE_ARC				~(0x00000001 << 8)
-#define INT_ENABLE_ARC_BIT_POS			(8)
-
-/* I2C */
-/* I2C_0 is on Pmod2 connector */
-#define I2C_DW_0_BASE_ADDR			0xF0004000
-
-/* I2C_1 is on Pmod4 connector */
-#define I2C_DW_1_BASE_ADDR			0xF0005000
-
-#define I2C_DW_IRQ_FLAGS			0
-
-/* GPIO */
-#define GPIO_DW_0_BASE_ADDR			0xF0002000 /* GPIO 0 : PORTA */
-#define GPIO_DW_0_BITS				32
-#define GPIO_DW_PORT_0_INT_MASK			0 /* n/a */
-#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
-
-#define GPIO_DW_1_BASE_ADDR			0xF000200C /* GPIO 1 : PORTB */
-#define GPIO_DW_1_BITS				9          /* 9 LEDs on board */
-#define GPIO_DW_PORT_1_INT_MASK			0 /* n/a */
-
-#define GPIO_DW_2_BASE_ADDR			0xF0002018 /* GPIO 2 : PORTC */
-#define GPIO_DW_2_BITS				32
-#define GPIO_DW_PORT_2_INT_MASK			0 /* n/a */
-
-#define GPIO_DW_3_BASE_ADDR			0xF0002024 /* GPIO 3 : PORTD */
-#define GPIO_DW_3_BITS				12
-#define GPIO_DW_PORT_3_INT_MASK			0 /* n/a */
-
-/* SPI */
-#define SPI_DW_SPI_CLOCK			SYSCLK_DEFAULT_IOSC_HZ
-
-#define SPI_DW_PORT_0_REGS			0xF0006000
-#define SPI_DW_PORT_1_REGS			0xF0007000
-
-#define SPI_DW_IRQ_FLAGS			0
-
-/*
- * SPI Chip Select Assignments on EM Starter Kit
- *
- *  CS0   Pmod6 - pin 1 - J6
- *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
- *  CS2   Pmod6 - pin 8 - J6
- *  CS3   SDCard (onboard)
- *  CS4   Internal SPI Slave - loopback
- *  CS5   SPI-Flash (onboard)
- */
-
-/*
- * UARTs: UART0 & UART1 & UART2
- */
-#define UART_NS16550_PORT_0_BASE_ADDR		0xF0008000
-#define UART_NS16550_PORT_0_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
-
-#define UART_NS16550_PORT_1_BASE_ADDR		0xF0009000
-#define UART_NS16550_PORT_1_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
-
-#define UART_NS16550_PORT_2_BASE_ADDR		0xF000A000
-#define UART_NS16550_PORT_2_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
-
-#define UART_IRQ_FLAGS				0 /* Default */
-
-/**
- * Peripheral Interrupt Connection Configurations
- */
-#ifdef CONFIG_BOARD_EM_STARTERKIT_R23
-#define GPIO_DW_0_IRQ				24
-#define I2C_DW_0_IRQ				25
-#define I2C_DW_1_IRQ				26
-#define SPI_DW_PORT_0_IRQ			27
-#define SPI_DW_PORT_1_IRQ			28
-#define UART_NS16550_PORT_0_IRQ			29
-#define UART_NS16550_PORT_1_IRQ			30
-#define UART_NS16550_PORT_2_IRQ			31
-#else /* CONFIG_BOARD_EM_STARTERKIT_R23 */
-#define GPIO_DW_0_IRQ				22
-#define I2C_DW_0_IRQ				23
-#define I2C_DW_1_IRQ				24
-#define SPI_DW_PORT_0_IRQ			25
-#define SPI_DW_PORT_1_IRQ			26
-#define UART_NS16550_PORT_0_IRQ			27
-#define UART_NS16550_PORT_1_IRQ			28
-#define UART_NS16550_PORT_2_IRQ			29
-#endif /* !CONFIG_BOARD_EM_STARTERKIT_R23 */
-
-#define GPIO_DW_1_IRQ				0	/* can't interrupt */
-#define GPIO_DW_2_IRQ				0	/* can't interrupt */
-#define GPIO_DW_3_IRQ				0	/* can't interrupt */
-
-#endif /* !_ASMLANGUAGE */
-
-#endif /* _SOC__H_ */

arch/arc/soc/em11d/soc_config.c

@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <device.h>
-#include <init.h>
-#include "soc.h"
-
-
-#ifdef CONFIG_UART_NS16550
-
-static int uart_ns16550_init(struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	/* On ARC EM Starter kit board,
-	 * send the UART the command to clear the interrupt
-	 */
-#ifdef CONFIG_UART_NS16550_PORT_0
-	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
-	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
-#endif /* CONFIG_UART_NS16550_PORT_0 */
-#ifdef CONFIG_UART_NS16550_PORT_1
-	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
-	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
-#endif /* CONFIG_UART_NS16550_PORT_1 */
-
-	return 0;
-}
-
-SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
-#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/em7d/CMakeLists.txt

@@ -1,14 +0,0 @@
-zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
-
-zephyr_cc_option(-mcpu=em4_dmips -mno-sdata)
-zephyr_cc_option(-mdiv-rem -mswap -mnorm)
-zephyr_cc_option(-mmpy-option=6 -mbarrel-shifter)
-zephyr_cc_option(--param l1-cache-size=16384)
-zephyr_cc_option(--param l1-cache-line-size=32)
-
-zephyr_cc_option_ifdef(CONFIG_CODE_DENSITY -mcode-density)
-
-zephyr_sources(
-  soc.c
-  soc_config.c
-  )

arch/arc/soc/em7d/Kconfig.defconfig

@@ -1,86 +0,0 @@
-#
-# Copyright (c) 2014 Wind River Systems, Inc.
-# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-if SOC_EM7D
-
-config SOC
-	default em7d
-
-config NUM_IRQ_PRIO_LEVELS
-	# This processor supports 4 priority levels:
-	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
-	default 4
-
-config NUM_IRQS
-	# must be > the highest interrupt number used
-	default 38 if BOARD_EM_STARTERKIT_R23
-	default 36 if BOARD_EM_STARTERKIT_R22
-
-config ARC_MPU_VER
-	default 3 if BOARD_EM_STARTERKIT_R23
-	default 2 if BOARD_EM_STARTERKIT_R22
-
-config RGF_NUM_BANKS
-	default 1
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 25000000 if BOARD_EM_STARTERKIT_R23
-	default 30000000 if BOARD_EM_STARTERKIT_R22
-
-config HARVARD
-	def_bool y
-
-config ARC_FIRQ
-	def_bool n if BOARD_EM_STARTERKIT_R23
-	def_bool y if BOARD_EM_STARTERKIT_R22
-
-config FLASH_BASE_ADDRESS
-	default 0x00000000
-
-config FLASH_SIZE
-	default 0
-	# em7d has no FLASH so size is 0.
-
-config SRAM_BASE_ADDRESS
-	default 0x10000000
-
-config SRAM_SIZE
-	default 131072
-
-config ICCM_BASE_ADDRESS
-	default 0x00000000
-
-config ICCM_SIZE
-	default 256
-
-config DCCM_BASE_ADDRESS
-	default 0x80000000
-
-config DCCM_SIZE
-	default 128
-
-config CACHE_FLUSHING
-	def_bool y
-
-if (ARC_MPU_VER = 2)
-
-config MAIN_STACK_SIZE
-	default 2048
-
-config IDLE_STACK_SIZE
-	default 2048
-
-if ZTEST
-
-config ZTEST_STACKSIZE
-	default 2048
-
-endif # ZTEST
-
-endif # ARC_MPU_VER
-
-endif #SOC_EM7D

arch/arc/soc/em7d/Kconfig.soc

@@ -1,5 +0,0 @@
-
-config SOC_EM7D
-	bool "Synopsys ARC EM7D"
-	select CPU_HAS_MPU
-	select ARC_HAS_SECURE if BOARD_EM_STARTERKIT_R23

arch/arc/soc/em7d/linker.ld

@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Linker script for the Synopsys EM Starterkit v2.2 EM7D platform.
- */
-
-/*
- * DRAM base address and size
- *
- * DRAM includes the exception vector table at reset, which is at
- * the beginning of the region.
- */
-#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
-#define SRAM_SIZE		CONFIG_SRAM_SIZE
-/* TODO: Using SRAM config for now, even though this is really DRAM. */
-
-/* Instruction Closely Coupled Memory (ICCM) base address and size */
-#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
-#define ICCM_SIZE		CONFIG_ICCM_SIZE
-
-/*
- * DCCM base address and size. DCCM is the data memory.
- */
-/* Data Closely Coupled Memory (DCCM) base address and size */
-#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
-#define DCCM_SIZE		CONFIG_DCCM_SIZE
-
-#include <arch/arc/v2/linker.ld>

arch/arc/soc/em7d/soc.c

@@ -1,14 +0,0 @@
-/* soc.c - system/hardware module for em_starterkit BSP */
-
-/*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * This module provides routines to initialize and support board-level hardware
- * for the ARC EM Starter kit board.
- *
- * Nothing to be done for now.
- */

arch/arc/soc/em7d/soc.h

@@ -1,146 +0,0 @@
-/*
- * Copyright (c) 2016-2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Board configuration macros for EM Starter kit board
- *
- * This header file is used to specify and describe board-level
- * aspects for the target.
- */
-
-#ifndef _SOC__H_
-#define _SOC__H_
-
-#include <misc/util.h>
-
-/* default system clock */
-/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
-#define SYSCLK_DEFAULT_IOSC_HZ			MHZ(50)
-
-
-/* ARC EM Core IRQs */
-#define IRQ_TIMER0				16
-#define IRQ_TIMER1				17
-
-#if defined(CONFIG_BOARD_EM_STARTERKIT_R23) && defined(CONFIG_SOC_EM7D)
-#define IRQ_SEC_TIMER0				20
-#endif /* CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EM7D */
-
-#if defined(CONFIG_BOARD_EM_STARTERKIT_R23) && defined(CONFIG_SOC_EM7D)
-#define IRQ_CORE_DMA_COMPLETE			22
-#define IRQ_CORE_DMA_ERROR			23
-#else /* CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EM7D */
-#define IRQ_CORE_DMA_COMPLETE			20
-#define IRQ_CORE_DMA_ERROR			21
-#endif /* !(CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EM7D) */
-
-#ifndef _ASMLANGUAGE
-
-#include <misc/util.h>
-#include <random/rand32.h>
-
-#define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
-#define ARCV2_TIMER0_INT_PRI			0
-
-#define ARCV2_TIMER1_INT_LVL			IRQ_TIMER1
-#define ARCV2_TIMER1_INT_PRI			1
-
-#define CONFIG_ARCV2_TIMER1_INT_LVL		IRQ_TIMER1
-#define CONFIG_ARCV2_TIMER1_INT_PRI		1
-
-#define INT_ENABLE_ARC				~(0x00000001 << 8)
-#define INT_ENABLE_ARC_BIT_POS			(8)
-
-/* I2C */
-/* I2C_0 is on Pmod2 connector */
-#define I2C_DW_0_BASE_ADDR			0xF0004000
-
-/* I2C_1 is on Pmod4 connector */
-#define I2C_DW_1_BASE_ADDR			0xF0005000
-
-#define I2C_DW_IRQ_FLAGS			0
-
-/* GPIO */
-#define GPIO_DW_0_BASE_ADDR			0xF0002000 /* GPIO 0 : PORTA */
-#define GPIO_DW_0_BITS				32
-#define GPIO_DW_PORT_0_INT_MASK			0 /* n/a */
-#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
-
-#define GPIO_DW_1_BASE_ADDR			0xF000200C /* GPIO 1 : PORTB */
-#define GPIO_DW_1_BITS				9          /* 9 LEDs on board */
-#define GPIO_DW_PORT_1_INT_MASK			0 /* n/a */
-
-#define GPIO_DW_2_BASE_ADDR			0xF0002018 /* GPIO 2 : PORTC */
-#define GPIO_DW_2_BITS				32
-#define GPIO_DW_PORT_2_INT_MASK			0 /* n/a */
-
-#define GPIO_DW_3_BASE_ADDR			0xF0002024 /* GPIO 3 : PORTD */
-#define GPIO_DW_3_BITS				12
-#define GPIO_DW_PORT_3_INT_MASK			0 /* n/a */
-
-/* SPI */
-#define SPI_DW_SPI_CLOCK			SYSCLK_DEFAULT_IOSC_HZ
-
-#define SPI_DW_PORT_0_REGS			0xF0006000
-#define SPI_DW_PORT_1_REGS			0xF0007000
-
-#define SPI_DW_IRQ_FLAGS			0
-
-/*
- * SPI Chip Select Assignments on EM Starter Kit
- *
- *  CS0   Pmod6 - pin 1 - J6
- *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
- *  CS2   Pmod6 - pin 8 - J6
- *  CS3   SDCard (onboard)
- *  CS4   Internal SPI Slave - loopback
- *  CS5   SPI-Flash (onboard)
- */
-
-/*
- * UARTs: UART0 & UART1 & UART2
- */
-#define UART_NS16550_PORT_0_BASE_ADDR		0xF0008000
-#define UART_NS16550_PORT_0_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
-
-#define UART_NS16550_PORT_1_BASE_ADDR		0xF0009000
-#define UART_NS16550_PORT_1_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
-
-#define UART_NS16550_PORT_2_BASE_ADDR		0xF000A000
-#define UART_NS16550_PORT_2_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
-
-#define UART_IRQ_FLAGS				0 /* Default */
-
-/**
- * Peripheral Interrupt Connection Configurations
- */
-#ifdef CONFIG_BOARD_EM_STARTERKIT_R23
-#define GPIO_DW_0_IRQ				24
-#define I2C_DW_0_IRQ				25
-#define I2C_DW_1_IRQ				26
-#define SPI_DW_PORT_0_IRQ			27
-#define SPI_DW_PORT_1_IRQ			28
-#define UART_NS16550_PORT_0_IRQ			29
-#define UART_NS16550_PORT_1_IRQ			30
-#define UART_NS16550_PORT_2_IRQ			31
-#else /* CONFIG_BOARD_EM_STARTERKIT_R23 */
-#define GPIO_DW_0_IRQ				22
-#define I2C_DW_0_IRQ				23
-#define I2C_DW_1_IRQ				24
-#define SPI_DW_PORT_0_IRQ			25
-#define SPI_DW_PORT_1_IRQ			26
-#define UART_NS16550_PORT_0_IRQ			27
-#define UART_NS16550_PORT_1_IRQ			28
-#define UART_NS16550_PORT_2_IRQ			29
-#endif /* !CONFIG_BOARD_EM_STARTERKIT_R23 */
-
-#define GPIO_DW_1_IRQ				0	/* can't interrupt */
-#define GPIO_DW_2_IRQ				0	/* can't interrupt */
-#define GPIO_DW_3_IRQ				0	/* can't interrupt */
-
-#endif /* !_ASMLANGUAGE */
-
-#endif /* _SOC__H_ */

arch/arc/soc/em7d/soc_config.c

@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <device.h>
-#include <init.h>
-#include "soc.h"
-
-
-#ifdef CONFIG_UART_NS16550
-
-static int uart_ns16550_init(struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	/* On ARC EM Starter kit board,
-	 * send the UART the command to clear the interrupt
-	 */
-#ifdef CONFIG_UART_NS16550_PORT_0
-	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
-	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
-#endif /* CONFIG_UART_NS16550_PORT_0 */
-#ifdef CONFIG_UART_NS16550_PORT_1
-	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
-	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
-#endif /* CONFIG_UART_NS16550_PORT_1 */
-
-	return 0;
-}
-
-SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
-#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/em9d/CMakeLists.txt

@@ -1,14 +0,0 @@
-zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
-
-zephyr_cc_option(-mcpu=em4_fpus -mno-sdata -mdiv-rem -mswap -mnorm)
-zephyr_cc_option(-mdiv-rem -mswap -mnorm)
-zephyr_cc_option(-mmpy-option=6 -mbarrel-shifter)
-
-zephyr_cc_option_ifdef(CONFIG_CODE_DENSITY -mcode-density)
-zephyr_cc_option_ifdef(CONFIG_FLOAT -mfpu=fpuda_all)
-
-
-zephyr_sources(
-  soc.c
-  soc_config.c
-  )

arch/arc/soc/em9d/Kconfig.defconfig

@@ -1,58 +0,0 @@
-#
-# Copyright (c) 2014 Wind River Systems, Inc.
-# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-if SOC_EM9D
-
-config SOC
-	default em9d
-
-config NUM_IRQ_PRIO_LEVELS
-	# This processor supports 4 priority levels:
-	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
-	default 4
-
-config NUM_IRQS
-	# must be > the highest interrupt number used
-	default 38 if BOARD_EM_STARTERKIT_R23
-	default 36 if BOARD_EM_STARTERKIT_R22
-
-config RGF_NUM_BANKS
-	default 2
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 20000000
-
-config HARVARD
-	def_bool y
-
-config FLASH_BASE_ADDRESS
-	default 0x00000000
-
-config FLASH_SIZE
-	default 0
-	# em9d has no FLASH so size is 0.
-
-config SRAM_BASE_ADDRESS
-	default 0x00000000
-
-config SRAM_SIZE
-	default 0
-	# em9d has no SRAM so size is 0.
-
-config ICCM_BASE_ADDRESS
-	default 0x00000000
-
-config ICCM_SIZE
-	default 256
-
-config DCCM_BASE_ADDRESS
-	default 0x80000000
-
-config DCCM_SIZE
-	default 128
-
-endif #SOC_EM9D

arch/arc/soc/em9d/Kconfig.soc

@@ -1,4 +0,0 @@
-
-config SOC_EM9D
-	bool "Synopsys ARC EM9D"
-	select CPU_HAS_FPU

arch/arc/soc/em9d/linker.ld

@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Linker script for the Synopsys EM Starterkit v2.2 EM9D platform.
- */
-
-/*
- * ICCM base address and size
- *
- * ICCM includes the exception vector table at reset, which is at
- * the beginning of the region.
- */
-
-/* Instruction Closely Coupled Memory (ICCM) base address and size */
-#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
-#define ICCM_SIZE		CONFIG_ICCM_SIZE
-
-/*
- * DCCM base address and size. DCCM is the data memory.
- */
-/* Data Closely Coupled Memory (DCCM) base address and size */
-#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
-#define DCCM_SIZE		CONFIG_DCCM_SIZE
-
-#include <arch/arc/v2/linker.ld>
-

arch/arc/soc/em9d/soc.c

@@ -1,14 +0,0 @@
-/* soc.c - system/hardware module for em_starterkit BSP */
-
-/*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * This module provides routines to initialize and support board-level hardware
- * for the ARC EM Starter kit board.
- *
- * Nothing to be done for now.
- */

arch/arc/soc/em9d/soc.h

@@ -1,137 +0,0 @@
-/*
- * Copyright (c) 2016-2017 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Board configuration macros for EM Starter kit board
- *
- * This header file is used to specify and describe board-level
- * aspects for the target.
- */
-
-#ifndef _SOC__H_
-#define _SOC__H_
-
-#include <misc/util.h>
-
-/* default system clock */
-/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
-#define SYSCLK_DEFAULT_IOSC_HZ			MHZ(50)
-
-
-/* ARC EM Core IRQs */
-#define IRQ_TIMER0				16
-#define IRQ_TIMER1				17
-
-#define IRQ_CORE_DMA_COMPLETE			20
-#define IRQ_CORE_DMA_ERROR			21
-
-#ifndef _ASMLANGUAGE
-
-#include <misc/util.h>
-#include <random/rand32.h>
-
-#define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
-#define ARCV2_TIMER0_INT_PRI			0
-
-#define ARCV2_TIMER1_INT_LVL			IRQ_TIMER1
-#define ARCV2_TIMER1_INT_PRI			1
-
-#define CONFIG_ARCV2_TIMER1_INT_LVL		IRQ_TIMER1
-#define CONFIG_ARCV2_TIMER1_INT_PRI		1
-
-#define INT_ENABLE_ARC				~(0x00000001 << 8)
-#define INT_ENABLE_ARC_BIT_POS			(8)
-
-/* I2C */
-/* I2C_0 is on Pmod2 connector */
-#define I2C_DW_0_BASE_ADDR			0xF0004000
-
-/* I2C_1 is on Pmod4 connector */
-#define I2C_DW_1_BASE_ADDR			0xF0005000
-
-#define I2C_DW_IRQ_FLAGS			0
-
-/* GPIO */
-#define GPIO_DW_0_BASE_ADDR			0xF0002000 /* GPIO 0 : PORTA */
-#define GPIO_DW_0_BITS				32
-#define GPIO_DW_PORT_0_INT_MASK			0 /* n/a */
-#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
-
-#define GPIO_DW_1_BASE_ADDR			0xF000200C /* GPIO 1 : PORTB */
-#define GPIO_DW_1_BITS				9          /* 9 LEDs on board */
-#define GPIO_DW_PORT_1_INT_MASK			0 /* n/a */
-
-#define GPIO_DW_2_BASE_ADDR			0xF0002018 /* GPIO 2 : PORTC */
-#define GPIO_DW_2_BITS				32
-#define GPIO_DW_PORT_2_INT_MASK			0 /* n/a */
-
-#define GPIO_DW_3_BASE_ADDR			0xF0002024 /* GPIO 3 : PORTD */
-#define GPIO_DW_3_BITS				12
-#define GPIO_DW_PORT_3_INT_MASK			0 /* n/a */
-
-/* SPI */
-#define SPI_DW_SPI_CLOCK			SYSCLK_DEFAULT_IOSC_HZ
-
-#define SPI_DW_PORT_0_REGS			0xF0006000
-#define SPI_DW_PORT_1_REGS			0xF0007000
-
-#define SPI_DW_IRQ_FLAGS			0
-
-/*
- * SPI Chip Select Assignments on EM Starter Kit
- *
- *  CS0   Pmod6 - pin 1 - J6
- *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
- *  CS2   Pmod6 - pin 8 - J6
- *  CS3   SDCard (onboard)
- *  CS4   Internal SPI Slave - loopback
- *  CS5   SPI-Flash (onboard)
- */
-
-/*
- * UARTs: UART0 & UART1 & UART2
- */
-#define UART_NS16550_PORT_0_BASE_ADDR		0xF0008000
-#define UART_NS16550_PORT_0_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
-
-#define UART_NS16550_PORT_1_BASE_ADDR		0xF0009000
-#define UART_NS16550_PORT_1_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
-
-#define UART_NS16550_PORT_2_BASE_ADDR		0xF000A000
-#define UART_NS16550_PORT_2_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
-
-#define UART_IRQ_FLAGS				0 /* Default */
-
-/**
- * Peripheral Interrupt Connection Configurations
- */
-#ifdef CONFIG_BOARD_EM_STARTERKIT_R23
-#define GPIO_DW_0_IRQ				24
-#define I2C_DW_0_IRQ				25
-#define I2C_DW_1_IRQ				26
-#define SPI_DW_PORT_0_IRQ			27
-#define SPI_DW_PORT_1_IRQ			28
-#define UART_NS16550_PORT_0_IRQ			29
-#define UART_NS16550_PORT_1_IRQ			30
-#define UART_NS16550_PORT_2_IRQ			31
-#else /* CONFIG_BOARD_EM_STARTERKIT_R23 */
-#define GPIO_DW_0_IRQ				22
-#define I2C_DW_0_IRQ				23
-#define I2C_DW_1_IRQ				24
-#define SPI_DW_PORT_0_IRQ			25
-#define SPI_DW_PORT_1_IRQ			26
-#define UART_NS16550_PORT_0_IRQ			27
-#define UART_NS16550_PORT_1_IRQ			28
-#define UART_NS16550_PORT_2_IRQ			29
-#endif /* !CONFIG_BOARD_EM_STARTERKIT_R23 */
-
-#define GPIO_DW_1_IRQ				0	/* can't interrupt */
-#define GPIO_DW_2_IRQ				0	/* can't interrupt */
-#define GPIO_DW_3_IRQ				0	/* can't interrupt */
-
-#endif /* !_ASMLANGUAGE */
-
-#endif /* _SOC__H_ */

arch/arc/soc/em9d/soc_config.c

@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <device.h>
-#include <init.h>
-#include "soc.h"
-
-
-#ifdef CONFIG_UART_NS16550
-
-static int uart_ns16550_init(struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	/* On ARC EM Starter kit board,
-	 * send the UART the command to clear the interrupt
-	 */
-#ifdef CONFIG_UART_NS16550_PORT_0
-	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
-	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
-#endif /* CONFIG_UART_NS16550_PORT_0 */
-#ifdef CONFIG_UART_NS16550_PORT_1
-	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
-	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
-#endif /* CONFIG_UART_NS16550_PORT_1 */
-
-	return 0;
-}
-
-SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
-#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/quark_se_c1000_ss/CMakeLists.txt

@@ -1,5 +1,5 @@
-zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
-zephyr_include_directories(${PROJECT_SOURCE_DIR}/arch/x86/soc/intel_quark)
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_include_directories(${ZEPHYR_BASE}/arch/x86/soc/intel_quark)
 
 zephyr_cc_option(-mcpu=quarkse_em -mno-sdata)
 

arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig

@@ -8,7 +8,7 @@
 if SOC_QUARK_SE_C1000_SS
 
 config SOC
-	default quark_se_c1000_ss
+	default "quark_se_c1000_ss"
 
 config NUM_IRQ_PRIO_LEVELS
 	# This processor supports only 2 priority levels:
@@ -28,34 +28,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config HARVARD
 	def_bool n
 
-if !HAS_DTS
-config FLASH_BASE_ADDRESS
-	default 0x40000000
-
-config FLASH_SIZE
-	default 152
-
-config SRAM_BASE_ADDRESS
-	default 0x4000 if NSIM
-	default 0xa8000400
-
-config SRAM_SIZE
-	default 16 if NSIM
-	default 27
-
-config ICCM_BASE_ADDRESS
-	default 0xFFFFFFFF
-
-config ICCM_SIZE
-	default 0
-
-config DCCM_BASE_ADDRESS
-	default 0x80000000
-
-config DCCM_SIZE
-	default 8
-endif
-
 config QMSI
 	def_bool y
 
@@ -67,9 +39,6 @@ if RTC
 config RTC_QMSI
 	def_bool y
 
-config RTC_0_IRQ_PRI
-	default 2
-
 endif # RTC
 
 if PWM
@@ -92,29 +61,9 @@ if GPIO_QMSI
 config GPIO_QMSI_0
 	def_bool y
 
-if GPIO_QMSI_0
-
-config GPIO_QMSI_0_NAME
-	default "GPIO_2"
-
-config GPIO_QMSI_0_IRQ_PRI
-	default 1
-
-endif # GPIO_QMSI_0
-
 config GPIO_QMSI_1
 	def_bool y
 
-if GPIO_QMSI_1
-
-config GPIO_QMSI_1_NAME
-	default "GPIO_3"
-
-config GPIO_QMSI_1_IRQ_PRI
-	default 1
-
-endif # GPIO_QMSI_1
-
 endif # GPIO_QMSI
 
 config GPIO_QMSI_SS
@@ -125,29 +74,9 @@ if GPIO_QMSI_SS
 config GPIO_QMSI_SS_0
 	def_bool y
 
-if GPIO_QMSI_SS_0
-
-config GPIO_QMSI_SS_0_NAME
-	default "GPIO_0"
-
-config GPIO_QMSI_SS_0_IRQ_PRI
-	default 1
-
-endif # GPIO_QMSI_SS_0
-
 config GPIO_QMSI_SS_1
 	def_bool y
 
-if GPIO_QMSI_SS_1
-
-config GPIO_QMSI_SS_1_NAME
-	default "GPIO_1"
-
-config GPIO_QMSI_SS_1_IRQ_PRI
-	default 1
-
-endif # GPIO_QMSI_SS_1
-
 endif # GPIO_QMSI_SS
 
 endif # GPIO
@@ -162,27 +91,9 @@ if I2C_QMSI
 config I2C_0
 	def_bool y
 
-config I2C_0_NAME
-	default "I2C_2"
-
-config I2C_0_IRQ_PRI
-	default 1
-
-config I2C_0_DEFAULT_CFG
-	default 0x12
-
 config I2C_1
 	def_bool y
 
-config I2C_1_NAME
-	default "I2C_3"
-
-config I2C_1_IRQ_PRI
-	default 1
-
-config I2C_1_DEFAULT_CFG
-	default 0x12
-
 config I2C_SDA_SETUP
 	default 2
 
@@ -201,21 +112,9 @@ if I2C_QMSI_SS
 config I2C_SS_0
 	def_bool y
 
-config I2C_SS_0_NAME
-	default "I2C_0"
-
-config I2C_SS_0_DEFAULT_CFG
-	default 0x12
-
 config I2C_SS_1
 	def_bool y
 
-config I2C_SS_1_NAME
-	default "I2C_1"
-
-config I2C_SS_1_DEFAULT_CFG
-	default 0x12
-
 config I2C_SS_SDA_SETUP
 	default 2
 
@@ -227,21 +126,15 @@ endif
 endif # I2C
 
 if ADC
-config ADC_QMSI_SS
+config ADC_DW
 	def_bool y
 endif
 
 if BT_H4
 
-config BT_UART_ON_DEV_NAME
-	default UART_QMSI_0_NAME
-
 config UART_QMSI_0
 	def_bool y
 
-config UART_QMSI_0_BAUDRATE
-	default 1000000
-
 config UART_QMSI_0_HW_FC
 	def_bool y
 
@@ -249,43 +142,44 @@ endif # BT_H4
 
 if UART_QMSI
 
-if UART_QMSI_0
-
-config UART_QMSI_0_IRQ_PRI
-	default 3
-
-endif # UART_QMSI_0
-
 config UART_QMSI_1
 	def_bool y
 
-if UART_QMSI_1
-
-config UART_QMSI_1_IRQ_PRI
-	default 3
-
-endif # UART_QMSI_1
-
 endif # UART_QMSI
 
-if UART_CONSOLE && !HAS_DTS
-
-config UART_CONSOLE_ON_DEV_NAME
-	default "UART_1"
-
-endif
-
 if SPI
 
-config SPI_QMSI
-	def_bool n
+config SPI_DW
+	def_bool y
+
+if SPI_DW
+
+config SPI_DW_FIFO_DEPTH
+	default 7
+
+config CLOCK_CONTROL
+	def_bool y
+
+config CLOCK_CONTROL_QUARK_SE
+	def_bool y
+
+config CLOCK_CONTROL_QUARK_SE_SENSOR
+	def_bool y
 
-if SPI_QMSI
 config SPI_0
 	def_bool y
 
-config SPI_0_NAME
-	default "SPI_2"
+config SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE
+	def_bool n
+
+config SPI_DW_PORT_0_CLOCK_GATE
+	def_bool y
+
+config SPI_DW_PORT_0_CLOCK_GATE_DRV_NAME
+	default CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME
+
+config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
+	default 3
 
 config SPI_0_IRQ_PRI
 	default 1
@@ -293,38 +187,22 @@ config SPI_0_IRQ_PRI
 config SPI_1
 	def_bool y
 
-config SPI_1_NAME
-	default "SPI_3"
+config SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE
+	def_bool n
+
+config SPI_DW_PORT_1_CLOCK_GATE
+	def_bool y
+
+config SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME
+	default CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME
+
+config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
+	default 4
 
 config SPI_1_IRQ_PRI
 	default 1
 
-endif
-
-config SPI_QMSI_SS
-	def_bool y
-
-if SPI_QMSI_SS
-config SPI_SS_0
-	def_bool y
-
-config SPI_SS_0_NAME
-	default "SPI_0"
-
-config SPI_SS_0_IRQ_PRI
-	default 1
-
-config SPI_SS_1
-	def_bool y
-
-config SPI_SS_1_NAME
-	default "SPI_1"
-
-config SPI_SS_1_IRQ_PRI
-	default 1
-
-endif
-
+endif # SPI_DW
 endif # SPI
 
 if AIO_COMPARATOR
@@ -340,7 +218,7 @@ config WDT_QMSI
 	def_bool y
 
 config WDT_0_IRQ_PRI
-	default 2
+	default 0
 
 endif # WATCHDOG
 
@@ -360,7 +238,7 @@ config AON_TIMER_QMSI
 	def_bool y
 
 config AON_TIMER_IRQ_PRI
-	default 2
+	default 0
 
 endif # COUNTER
 

arch/arc/soc/quark_se_c1000_ss/dts.fixup

@@ -3,10 +3,12 @@
 #define CONFIG_UART_QMSI_0_BAUDRATE	INTEL_QMSI_UART_B0002000_CURRENT_SPEED
 #define CONFIG_UART_QMSI_0_NAME		INTEL_QMSI_UART_B0002000_LABEL
 #define CONFIG_UART_QMSI_0_IRQ		INTEL_QMSI_UART_B0002000_IRQ_0
+#define CONFIG_UART_QMSI_0_IRQ_PRI	INTEL_QMSI_UART_B0002000_IRQ_0_PRIORITY
 
 #define CONFIG_UART_QMSI_1_BAUDRATE	INTEL_QMSI_UART_B0002400_CURRENT_SPEED
 #define CONFIG_UART_QMSI_1_NAME		INTEL_QMSI_UART_B0002400_LABEL
 #define CONFIG_UART_QMSI_1_IRQ		INTEL_QMSI_UART_B0002400_IRQ_0
+#define CONFIG_UART_QMSI_1_IRQ_PRI	INTEL_QMSI_UART_B0002400_IRQ_0_PRIORITY
 
 #define SRAM_START			CONFIG_SRAM_BASE_ADDRESS
 #define SRAM_SIZE			CONFIG_SRAM_SIZE
@@ -15,6 +17,61 @@
 #define FLASH_SIZE      		CONFIG_FLASH_SIZE
 
 #define CONFIG_DCCM_BASE_ADDRESS       ARC_DCCM_80000000_BASE_ADDRESS
-#define CONFIG_DCCM_SIZE               ARC_DCCM_80000000_SIZE
+#define CONFIG_DCCM_SIZE               (ARC_DCCM_80000000_SIZE >> 10)
+
+#define CONFIG_I2C_SS_0_NAME		INTEL_QMSI_SS_I2C_80012000_LABEL
+#define CONFIG_I2C_SS_0_ERR_IRQ		INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR
+#define CONFIG_I2C_SS_0_ERR_IRQ_PRI	INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_SS_0_RX_IRQ		INTEL_QMSI_SS_I2C_80012000_IRQ_RX
+#define CONFIG_I2C_SS_0_RX_IRQ_PRI	INTEL_QMSI_SS_I2C_80012000_IRQ_RX_PRIORITY
+#define CONFIG_I2C_SS_0_TX_IRQ		INTEL_QMSI_SS_I2C_80012000_IRQ_TX
+#define CONFIG_I2C_SS_0_TX_IRQ_PRI	INTEL_QMSI_SS_I2C_80012000_IRQ_TX_PRIORITY
+#define CONFIG_I2C_SS_0_STOP_IRQ	INTEL_QMSI_SS_I2C_80012000_IRQ_STOP
+#define CONFIG_I2C_SS_0_STOP_IRQ_PRI	INTEL_QMSI_SS_I2C_80012000_IRQ_STOP_PRIORITY
+#define CONFIG_I2C_SS_0_BITRATE		INTEL_QMSI_SS_I2C_80012000_CLOCK_FREQUENCY
+#define CONFIG_I2C_SS_1_NAME		INTEL_QMSI_SS_I2C_80012100_LABEL
+#define CONFIG_I2C_SS_1_ERR_IRQ		INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR
+#define CONFIG_I2C_SS_1_ERR_IRQ_PRI	INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_SS_1_RX_IRQ		INTEL_QMSI_SS_I2C_80012100_IRQ_RX
+#define CONFIG_I2C_SS_1_RX_IRQ_PRI	INTEL_QMSI_SS_I2C_80012100_IRQ_RX_PRIORITY
+#define CONFIG_I2C_SS_1_TX_IRQ		INTEL_QMSI_SS_I2C_80012100_IRQ_TX
+#define CONFIG_I2C_SS_1_TX_IRQ_PRI	INTEL_QMSI_SS_I2C_80012100_IRQ_TX_PRIORITY
+#define CONFIG_I2C_SS_1_STOP_IRQ	INTEL_QMSI_SS_I2C_80012100_IRQ_STOP
+#define CONFIG_I2C_SS_1_STOP_IRQ_PRI	INTEL_QMSI_SS_I2C_80012100_IRQ_STOP_PRIORITY
+#define CONFIG_I2C_SS_1_BITRATE		INTEL_QMSI_SS_I2C_80012100_CLOCK_FREQUENCY
+
+#define CONFIG_I2C_0_NAME		INTEL_QMSI_I2C_B0002800_LABEL
+#define CONFIG_I2C_0_BITRATE		INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY
+#define CONFIG_I2C_0_IRQ		INTEL_QMSI_I2C_B0002800_IRQ_0
+#define CONFIG_I2C_0_IRQ_PRI		INTEL_QMSI_I2C_B0002800_IRQ_0_PRIORITY
+#define CONFIG_I2C_1_NAME		INTEL_QMSI_I2C_B0002C00_LABEL
+#define CONFIG_I2C_1_BITRATE		INTEL_QMSI_I2C_B0002C00_CLOCK_FREQUENCY
+#define CONFIG_I2C_1_IRQ		INTEL_QMSI_I2C_B0002C00_IRQ_0
+#define CONFIG_I2C_1_IRQ_PRI		INTEL_QMSI_I2C_B0002C00_IRQ_0_PRIORITY
+
+#define CONFIG_RTC_0_NAME		INTEL_QMSI_RTC_B0000400_LABEL
+#define CONFIG_RTC_0_IRQ		INTEL_QMSI_RTC_B0000400_IRQ_0
+#define CONFIG_RTC_0_IRQ_PRI		INTEL_QMSI_RTC_B0000400_IRQ_0_PRIORITY
+
+#define CONFIG_GPIO_QMSI_SS_0_NAME	INTEL_QMSI_SS_GPIO_80017800_LABEL
+#define CONFIG_GPIO_QMSI_SS_0_IRQ	INTEL_QMSI_SS_GPIO_80017800_IRQ_0
+#define CONFIG_GPIO_QMSI_SS_0_IRQ_PRI	INTEL_QMSI_SS_GPIO_80017800_IRQ_0_PRIORITY
+
+#define CONFIG_GPIO_QMSI_SS_1_NAME	INTEL_QMSI_SS_GPIO_80017900_LABEL
+#define CONFIG_GPIO_QMSI_SS_1_IRQ	INTEL_QMSI_SS_GPIO_80017900_IRQ_0
+#define CONFIG_GPIO_QMSI_SS_1_IRQ_PRI	INTEL_QMSI_SS_GPIO_80017900_IRQ_0_PRIORITY
+
+#define CONFIG_GPIO_QMSI_0_NAME		INTEL_QMSI_GPIO_B0000C00_LABEL
+#define CONFIG_GPIO_QMSI_0_IRQ		INTEL_QMSI_GPIO_B0000C00_IRQ_0
+#define CONFIG_GPIO_QMSI_0_IRQ_PRI	INTEL_QMSI_GPIO_B0000C00_IRQ_0_PRIORITY
+#define CONFIG_GPIO_QMSI_1_NAME		INTEL_QMSI_GPIO_B0800B00_LABEL
+#define CONFIG_GPIO_QMSI_1_IRQ		INTEL_QMSI_GPIO_B0800B00_IRQ_0
+#define CONFIG_GPIO_QMSI_1_IRQ_PRI	INTEL_QMSI_GPIO_B0800B00_IRQ_0_PRIORITY
+
+#define CONFIG_ADC_0_IRQ		SNPS_DW_ADC_80015000_IRQ_NORMAL
+#define CONFIG_ADC_IRQ_ERR		SNPS_DW_ADC_80015000_IRQ_ERROR
+#define CONFIG_ADC_0_IRQ_PRI		SNPS_DW_ADC_80015000_IRQ_0_PRIORITY
+#define CONFIG_ADC_0_NAME		SNPS_DW_ADC_80015000_LABEL
+#define CONFIG_ADC_0_BASE_ADDRESS	SNPS_DW_ADC_80015000_BASE_ADDRESS
 
 /* End of SoC Level DTS fixup file */

arch/arc/soc/quark_se_c1000_ss/power.c

@@ -20,7 +20,7 @@
 #if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
 extern void _power_soc_sleep(void);
 extern void _power_soc_deep_sleep(void);
-extern void _power_soc_deep_sleep_2(void);
+extern void _power_soc_lpss_mode(void);
 
 static void _deep_sleep(enum power_states state)
 {
@@ -30,7 +30,7 @@ static void _deep_sleep(enum power_states state)
 	case SYS_POWER_STATE_DEEP_SLEEP_1:
 		_power_soc_sleep();
 		break;
-	case SYS_POWER_STATE_DEEP_SLEEP:
+	case SYS_POWER_STATE_DEEP_SLEEP_2:
 		_power_soc_deep_sleep();
 		break;
 	default:
@@ -43,24 +43,20 @@ void _sys_soc_set_power_state(enum power_states state)
 {
 	switch (state) {
 	case SYS_POWER_STATE_CPU_LPS:
-		qm_ss_power_soc_lpss_enable();
-		qm_ss_power_cpu_ss2();
+		qm_ss_power_cpu_ss1(QM_SS_POWER_CPU_SS1_TIMER_ON);
 		break;
 	case SYS_POWER_STATE_CPU_LPS_1:
 		qm_ss_power_cpu_ss2();
 		break;
-	case SYS_POWER_STATE_CPU_LPS_2:
-		qm_ss_power_cpu_ss1(QM_SS_POWER_CPU_SS1_TIMER_ON);
-		break;
 #if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
 	case SYS_POWER_STATE_DEEP_SLEEP:
-	case SYS_POWER_STATE_DEEP_SLEEP_1:
-		_deep_sleep(state);
-		break;
-	case SYS_POWER_STATE_DEEP_SLEEP_2:
 		qm_ss_power_soc_lpss_enable();
 		qm_power_soc_set_ss_restore_flag();
-		_power_soc_deep_sleep_2();
+		_power_soc_lpss_mode();
+		break;
+	case SYS_POWER_STATE_DEEP_SLEEP_1:
+	case SYS_POWER_STATE_DEEP_SLEEP_2:
+		_deep_sleep(state);
 		break;
 #endif
 	default:
@@ -73,18 +69,14 @@ void _sys_soc_power_state_post_ops(enum power_states state)
 	u32_t limit;
 
 	switch (state) {
-	case SYS_POWER_STATE_CPU_LPS:
-		qm_ss_power_soc_lpss_disable();
 	case SYS_POWER_STATE_CPU_LPS_1:
 		/* Expire the timer as it is disabled in SS2. */
 		limit = _arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT);
 		_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, limit - 1);
-		break;
-	case SYS_POWER_STATE_DEEP_SLEEP:
-	case SYS_POWER_STATE_DEEP_SLEEP_1:
+	case SYS_POWER_STATE_CPU_LPS:
 		__builtin_arc_seti(0);
 		break;
-	case SYS_POWER_STATE_DEEP_SLEEP_2:
+	case SYS_POWER_STATE_DEEP_SLEEP:
 		qm_ss_power_soc_lpss_disable();
 
 		/* If flag is cleared it means the system entered in
@@ -100,6 +92,13 @@ void _sys_soc_power_state_post_ops(enum power_states state)
 			QM_SCSS_GP->gps0 &= ~QM_GPS0_BIT_SENSOR_WAKEUP;
 		}
 		break;
+	case SYS_POWER_STATE_DEEP_SLEEP_1:
+	case SYS_POWER_STATE_DEEP_SLEEP_2:
+		/* Route RTC interrupt to the current core */
+		QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->rtc_0_int_mask);
+		__builtin_arc_seti(0);
+		break;
+		break;
 	default:
 		break;
 	}

arch/arc/soc/quark_se_c1000_ss/soc.h

@@ -132,6 +132,10 @@
 #define I2C_SS_1_STOP_VECTOR				29
 #define I2C_SS_1_STOP_MASK				0x42C
 
+#define CONFIG_I2C_0_IRQ_FLAGS			(IOAPIC_LEVEL | IOAPIC_HIGH)
+#define CONFIG_I2C_1_IRQ_FLAGS			(IOAPIC_LEVEL | IOAPIC_HIGH)
+
+
 /*
  * GPIO
  */
@@ -155,38 +159,57 @@
 #define GPIO_DW_1_IRQ_FLAGS			0
 #endif
 
+#define CONFIG_GPIO_QMSI_0_IRQ_FLAGS		(IOAPIC_EDGE | IOAPIC_HIGH)
+#define CONFIG_GPIO_QMSI_1_IRQ_FLAGS		(IOAPIC_EDGE | IOAPIC_HIGH)
+
 /*
  * UART
  */
-
-#define UART_IRQ_FLAGS                                  0
-
-#define UART_NS16550_PORT_0_BASE_ADDR			0xB0002000
-#define UART_NS16550_PORT_0_IRQ				41
-#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
-#define UART_NS16550_PORT_0_INT_MASK			0x460
-
-#define UART_NS16550_PORT_1_BASE_ADDR			0xB0002400
-#define UART_NS16550_PORT_1_IRQ				42
-#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
-#define UART_NS16550_PORT_1_INT_MASK			0x464
+#define CONFIG_UART_QMSI_0_IRQ_FLAGS                     0
+#define CONFIG_UART_QMSI_1_IRQ_FLAGS                     0
 
 /*
  * SPI
  */
 
-#define SPI_DW_PORT_0_REGS				0x80010000
-#define SPI_DW_PORT_1_REGS				0x80010100
+#ifdef CONFIG_SPI_DW
 
-#define SPI_DW_PORT_0_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x430)
-#define SPI_DW_PORT_0_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x434)
-#define SPI_DW_PORT_0_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x438)
+#define SPI_DW_PORT_0_REGS			0x80010000
+#define SPI_DW_PORT_1_REGS			0x80010100
 
-#define SPI_DW_PORT_1_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x43C)
-#define SPI_DW_PORT_1_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x440)
-#define SPI_DW_PORT_1_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x444)
+#define SPI_DW_PORT_0_ERROR_INT_MASK		(SCSS_REGISTER_BASE + 0x430)
+#define SPI_DW_PORT_0_RX_INT_MASK		(SCSS_REGISTER_BASE + 0x434)
+#define SPI_DW_PORT_0_TX_INT_MASK		(SCSS_REGISTER_BASE + 0x438)
+
+#define SPI_DW_PORT_1_ERROR_INT_MASK		(SCSS_REGISTER_BASE + 0x43C)
+#define SPI_DW_PORT_1_RX_INT_MASK		(SCSS_REGISTER_BASE + 0x440)
+#define SPI_DW_PORT_1_TX_INT_MASK		(SCSS_REGISTER_BASE + 0x444)
+
+#define SPI_DW_IRQ_FLAGS			0
+
+#define SPI_DW_PORT_2_REGS			0xB0001000
+#define SPI_DW_PORT_2_IRQ			IRQ_SPI_MST0_INTR
+#define SPI_DW_PORT_2_INT_MASK			(SCSS_REGISTER_BASE + 0x454)
+
+#define SPI_DW_PORT_3_REGS			0xB0001400
+#define SPI_DW_PORT_3_IRQ			IRQ_SPI_MST1_INTR
+#define SPI_DW_PORT_3_INT_MASK			(SCSS_REGISTER_BASE + 0x458)
+
+#endif /* CONFIG_SPI_DW */
+
+/* Clock */
+#define CLOCK_PERIPHERAL_BASE_ADDR		(SCSS_REGISTER_BASE + 0x18)
+#define CLOCK_EXTERNAL_BASE_ADDR		(SCSS_REGISTER_BASE + 0x24)
+#define CLOCK_SENSOR_BASE_ADDR			(SCSS_REGISTER_BASE + 0x28)
+#define CLOCK_SYSTEM_CLOCK_CONTROL		(SCSS_REGISTER_BASE + \
+						 SCSS_CCU_SYS_CLK_CTL)
+
+/*
+ * RTC
+ */
+
+#define CONFIG_RTC_0_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
 
-#define SPI_DW_IRQ_FLAGS				0
 
 static inline void _quark_se_ss_ready(void)
 {

arch/arc/soc/quark_se_c1000_ss/soc_config.c

@@ -42,26 +42,3 @@ DEVICE_INIT(ipm_console, "ipm_console", ipm_console_sender_init,
 
 #endif /* CONFIG_IPM_CONSOLE_SENDER */
 #endif /* CONFIG_IPM_QUARK_SE */
-
-#ifdef CONFIG_UART_NS16550
-
-static int uart_ns16550_init(struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-#ifdef CONFIG_UART_NS16550_PORT_0
-	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_0_INT_MASK),
-		      INT_ENABLE_ARC_BIT_POS);
-#endif /* CONFIG_UART_NS16550_PORT_0 */
-
-#ifdef CONFIG_UART_NS16550_PORT_1
-	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_1_INT_MASK),
-		      INT_ENABLE_ARC_BIT_POS);
-#endif /* CONFIG_UART_NS16550_PORT_1 */
-
-	return 0;
-}
-
-SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
-#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/quark_se_c1000_ss/soc_power.S

@@ -15,7 +15,7 @@ GTEXT(_sys_soc_resume_from_deep_sleep)
 GTEXT(_power_restore_cpu_context)
 GTEXT(_power_soc_sleep)
 GTEXT(_power_soc_deep_sleep)
-GTEXT(_power_soc_deep_sleep_2)
+GTEXT(_power_soc_lpss_mode)
 
 #define GPS0_REGISTER  0xb0800100
 #define GP0_REGISTER 0xb0800114
@@ -73,7 +73,7 @@ SECTION_FUNC(TEXT, _power_soc_deep_sleep)
 	j @qm_power_soc_deep_sleep
 	/* Does not return */
 
-SECTION_FUNC(TEXT, _power_soc_deep_sleep_2)
+SECTION_FUNC(TEXT, _power_soc_lpss_mode)
 	/*
 	 * Setup 'sleep' instruction operand.
 	 */

arch/arc/soc/quark_se_c1000_ss/soc_power.h

@@ -20,15 +20,12 @@ extern "C" {
 #define GP0_BIT_SLEEP_READY BIT(0)
 
 enum power_states {
-	SYS_POWER_STATE_CPU_LPS,       /* SS2 with LPSS enabled state */
+	SYS_POWER_STATE_CPU_LPS,       /* SS1 state with Timer ON */
 	SYS_POWER_STATE_CPU_LPS_1,     /* SS2 state */
-	SYS_POWER_STATE_CPU_LPS_2,     /* SS1 state with Timer ON */
-	SYS_POWER_STATE_DEEP_SLEEP,    /* DEEP SLEEP state */
+	SYS_POWER_STATE_DEEP_SLEEP,    /* SS2 with LPSS enabled state */
 	SYS_POWER_STATE_DEEP_SLEEP_1,  /* SLEEP state */
-	SYS_POWER_STATE_DEEP_SLEEP_2,  /* Multicore DEEP SLEEP state.
-					* Execution context is saved
-					* and core enters in LPS state.
-					*/
+	SYS_POWER_STATE_DEEP_SLEEP_2,  /* SLEEP state with LPMODE enabled */
+
 	SYS_POWER_STATE_MAX
 };
 
@@ -41,12 +38,12 @@ enum power_states {
  * Wake up considerations:
  * -----------------------
  *
- * SYS_POWER_STATE_CPU_LPS_2: Any interrupt works as wake event.
+ * SYS_POWER_STATE_CPU_LPS: Any interrupt works as wake event.
  *
  * SYS_POWER_STATE_CPU_LPS_1: Any interrupt works as wake event except
  * the ARC TIMER which is disabled.
  *
- * SYS_POWER_STATE_CPU_LPS: SYS_POWER_STATE_DEEP_SLEEP wake events applies.
+ * SYS_POWER_STATE_CPU_LPS_2: SYS_POWER_STATE_DEEP_SLEEP wake events applies.
  *
  * SYS_POWER_STATE_DEEP_SLEEP: Only Always-On peripherals can wake up
  * the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.

arch/arc/soc/snps_emsk/CMakeLists.txt

@@ -0,0 +1,17 @@
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+
+zephyr_cc_option(-mcpu=${GCC_M_CPU})
+zephyr_cc_option(-mno-sdata -mdiv-rem -mswap -mnorm)
+zephyr_cc_option(-mmpy-option=6 -mbarrel-shifter)
+zephyr_cc_option_ifdef(CONFIG_SOC_EMSK_EM7D --param l1-cache-size=16384)
+zephyr_cc_option_ifdef(CONFIG_SOC_EMSK_EM7D --param l1-cache-line-size=32)
+zephyr_cc_option_ifdef(CONFIG_SOC_EMSK_EM11D --param l1-cache-size=16384)
+zephyr_cc_option_ifdef(CONFIG_SOC_EMSK_EM11D --param l1-cache-line-size=32)
+zephyr_cc_option_ifdef(CONFIG_CODE_DENSITY -mcode-density)
+zephyr_cc_option_ifdef(CONFIG_FLOAT -mfpu=fpuda_all)
+
+
+zephyr_sources(
+  soc.c
+  soc_config.c
+  )

arch/arc/soc/snps_emsk/Kconfig

@@ -0,0 +1,29 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_EMSK
+
+choice
+prompt "ARC EM Starter Kit Core Selection"
+default SOC_EMSK_EM7D
+
+config SOC_EMSK_EM7D
+	bool "Synopsys ARC EM7D of EMSK"
+	select CPU_HAS_MPU
+	select ARC_HAS_SECURE if BOARD_EM_STARTERKIT_R23
+
+config SOC_EMSK_EM11D
+	bool "Synopsys ARC EM11D of EMSK"
+	select CPU_HAS_FPU
+
+config SOC_EMSK_EM9D
+	bool "Synopsys ARC EM9D of EMSK"
+	select CPU_HAS_FPU
+
+endchoice
+
+endif #SOC_EMSK

arch/arc/soc/snps_emsk/Kconfig.defconfig

@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_EMSK
+
+config SOC
+	string
+	default "snps_emsk"
+
+source "arch/arc/soc/snps_emsk/Kconfig.defconfig.em7d"
+source "arch/arc/soc/snps_emsk/Kconfig.defconfig.em11d"
+source "arch/arc/soc/snps_emsk/Kconfig.defconfig.em9d"
+
+endif #SOC_EMSK

arch/arc/soc/snps_emsk/Kconfig.defconfig.em11d

@@ -0,0 +1,38 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_EMSK_EM11D
+
+config CPU_EM4_FPUDA
+	def_bool y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 38 if BOARD_EM_STARTERKIT_R23
+	default 36 if BOARD_EM_STARTERKIT_R22
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	def_bool n
+
+config CACHE_FLUSHING
+	def_bool y
+
+config FP_FPU_DA
+	def_bool y
+
+endif #SOC_EMSK_EM11D

arch/arc/soc/snps_emsk/Kconfig.defconfig.em7d

@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_EMSK_EM7D
+
+config CPU_EM4_DMIPS
+	def_bool y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 38 if BOARD_EM_STARTERKIT_R23
+	default 36 if BOARD_EM_STARTERKIT_R22
+
+config ARC_MPU_VER
+	default 3 if BOARD_EM_STARTERKIT_R23
+	default 2 if BOARD_EM_STARTERKIT_R22
+
+config RGF_NUM_BANKS
+	default 1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 25000000 if BOARD_EM_STARTERKIT_R23
+	default 30000000 if BOARD_EM_STARTERKIT_R22
+
+config HARVARD
+	def_bool y
+
+config ARC_FIRQ
+	def_bool n if BOARD_EM_STARTERKIT_R23
+	def_bool y if BOARD_EM_STARTERKIT_R22
+
+config CACHE_FLUSHING
+	def_bool y
+
+if (ARC_MPU_VER = 2)
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+if ZTEST
+
+config ZTEST_STACKSIZE
+	default 2048
+
+endif # ZTEST
+
+endif # ARC_MPU_VER
+
+endif #SOC_EMSK_EM7D

arch/arc/soc/snps_emsk/Kconfig.defconfig.em9d

@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_EMSK_EM9D
+
+config CPU_EM4_FPUS
+	def_bool y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 38 if BOARD_EM_STARTERKIT_R23
+	default 36 if BOARD_EM_STARTERKIT_R22
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	def_bool y
+
+endif #SOC_EMSK_EM9D

arch/arc/soc/snps_emsk/Kconfig.soc

@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_EMSK
+	bool "Synopsys ARC EM Starter Kit SoC"

arch/arc/soc/snps_emsk/dts.fixup

@@ -0,0 +1,101 @@
+/* SoC level DTS fixup file */
+
+/* CCM configuration */
+#define CONFIG_DCCM_BASE_ADDRESS       ARC_DCCM_80000000_BASE_ADDRESS
+#define CONFIG_DCCM_SIZE               (ARC_DCCM_80000000_SIZE >> 10)
+
+#define CONFIG_ICCM_BASE_ADDRESS       ARC_ICCM_0_BASE_ADDRESS
+#define CONFIG_ICCM_SIZE               (ARC_ICCM_0_SIZE >> 10)
+
+/*
+ * UART configuration
+ */
+#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR	NS16550_F0008000_BASE_ADDRESS
+#define CONFIG_UART_NS16550_PORT_0_IRQ		NS16550_F0008000_IRQ_0
+#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ	NS16550_F0008000_CLOCK_FREQUENCY
+#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE	NS16550_F0008000_CURRENT_SPEED
+#define CONFIG_UART_NS16550_PORT_0_NAME		NS16550_F0008000_LABEL
+#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI	NS16550_F0008000_IRQ_0_PRIORITY
+
+#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR	NS16550_F0009000_BASE_ADDRESS
+#define CONFIG_UART_NS16550_PORT_1_IRQ		NS16550_F0009000_IRQ_0
+#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ	NS16550_F0009000_CLOCK_FREQUENCY
+#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE	NS16550_F0009000_CURRENT_SPEED
+#define CONFIG_UART_NS16550_PORT_1_NAME		NS16550_F0009000_LABEL
+#define CONFIG_UART_NS16550_PORT_1_IRQ_PRI	NS16550_F0009000_IRQ_0_PRIORITY
+
+#define CONFIG_UART_NS16550_PORT_2_BASE_ADDR	NS16550_F000A000_BASE_ADDRESS
+#define CONFIG_UART_NS16550_PORT_2_IRQ		NS16550_F000A000_IRQ_0
+#define CONFIG_UART_NS16550_PORT_2_CLK_FREQ	NS16550_F000A000_CLOCK_FREQUENCY
+#define CONFIG_UART_NS16550_PORT_2_BAUD_RATE	NS16550_F000A000_CURRENT_SPEED
+#define CONFIG_UART_NS16550_PORT_2_NAME		NS16550_F000A000_LABEL
+#define CONFIG_UART_NS16550_PORT_2_IRQ_PRI	NS16550_F000A000_IRQ_0_PRIORITY
+
+/*
+ * I2C configuration
+ */
+/* I2C_0 is on Pmod2 connector */
+#define CONFIG_I2C_0_BASE_ADDR 	SNPS_DESIGNWARE_I2C_F0004000_BASE_ADDRESS
+#define CONFIG_I2C_0_BITRATE	SNPS_DESIGNWARE_I2C_F0004000_CLOCK_FREQUENCY
+#define CONFIG_I2C_0_IRQ	SNPS_DESIGNWARE_I2C_F0004000_IRQ_0
+#define CONFIG_I2C_0_IRQ_PRI 	SNPS_DESIGNWARE_I2C_F0004000_IRQ_0_PRIORITY
+#define CONFIG_I2C_0_NAME	SNPS_DESIGNWARE_I2C_F0004000_LABEL
+#define CONFIG_I2C_0_IRQ_FLAGS	0
+
+/* I2C_1 is on Pmod4 connector */
+#define CONFIG_I2C_1_BASE_ADDR 	SNPS_DESIGNWARE_I2C_F0005000_BASE_ADDRESS
+#define CONFIG_I2C_1_BITRATE	SNPS_DESIGNWARE_I2C_F0005000_CLOCK_FREQUENCY
+#define CONFIG_I2C_1_IRQ	SNPS_DESIGNWARE_I2C_F0005000_IRQ_0
+#define CONFIG_I2C_1_IRQ_PRI 	SNPS_DESIGNWARE_I2C_F0005000_IRQ_0_PRIORITY
+#define CONFIG_I2C_1_NAME	SNPS_DESIGNWARE_I2C_F0005000_LABEL
+#define CONFIG_I2C_1_IRQ_FLAGS	0
+
+
+/*
+ * GPIO configuration
+ */
+#define GPIO_DW_0_BASE_ADDR	SNPS_DESIGNWARE_GPIO_F0002000_BASE_ADDRESS
+#define GPIO_DW_0_BITS		SNPS_DESIGNWARE_GPIO_F0002000_BITS
+#define CONFIG_GPIO_DW_0_NAME	SNPS_DESIGNWARE_GPIO_F0002000_LABEL
+#define GPIO_DW_0_IRQ 		SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0
+#define CONFIG_GPIO_DW_0_IRQ_PRI SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0_PRIORITY
+#define GPIO_DW_0_IRQ_FLAGS	0
+
+#define GPIO_DW_1_BASE_ADDR	SNPS_DESIGNWARE_GPIO_F000200C_BASE_ADDRESS
+#define GPIO_DW_1_BITS		SNPS_DESIGNWARE_GPIO_F000200C_BITS
+#define CONFIG_GPIO_DW_1_NAME	SNPS_DESIGNWARE_GPIO_F000200C_LABEL
+#define GPIO_DW_1_IRQ 		SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0
+#define CONFIG_GPIO_DW_1_IRQ_PRI SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0_PRIORITY
+
+#define GPIO_DW_2_BASE_ADDR	SNPS_DESIGNWARE_GPIO_F0002018_BASE_ADDRESS
+#define GPIO_DW_2_BITS		SNPS_DESIGNWARE_GPIO_F0002018_BITS
+#define CONFIG_GPIO_DW_2_NAME	SNPS_DESIGNWARE_GPIO_F0002018_LABEL
+#define GPIO_DW_2_IRQ 		SNPS_DESIGNWARE_GPIO_F0002018_IRQ_0
+#define CONFIG_GPIO_DW_2_IRQ_PRI SNPS_DESIGNWARE_GPIO_F0002018_IRQ_0_PRIORITY
+
+#define GPIO_DW_3_BASE_ADDR	SNPS_DESIGNWARE_GPIO_F0002024_BASE_ADDRESS
+#define GPIO_DW_3_BITS		SNPS_DESIGNWARE_GPIO_F0002024_BITS
+#define CONFIG_GPIO_DW_3_NAME	SNPS_DESIGNWARE_GPIO_F0002024_LABEL
+#define GPIO_DW_3_IRQ 		SNPS_DESIGNWARE_GPIO_F0002024_IRQ_0
+#define CONFIG_GPIO_DW_3_IRQ_PRI SNPS_DESIGNWARE_GPIO_F0002024_IRQ_0_PRIORITY
+
+/*
+ * SPI configuration
+ */
+#define SPI_DW_PORT_0_REGS 	SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS
+#define SPI_DW_PORT_0_IRQ	SNPS_DESIGNWARE_SPI_F0006000_IRQ_0
+#define CONFIG_SPI_0_NAME	SNPS_DESIGNWARE_SPI_F0006000_LABEL
+#define CONFIG_SPI_0_IRQ_PRI  	SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY
+
+
+#define SPI_DW_PORT_1_REGS 	SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS
+#define SPI_DW_PORT_1_IRQ	SNPS_DESIGNWARE_SPI_F0007000_IRQ_0
+#define CONFIG_SPI_1_NAME	SNPS_DESIGNWARE_SPI_F0007000_LABEL
+#define CONFIG_SPI_1_IRQ_PRI  	SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY
+
+#define SPI_DW_IRQ_FLAGS	0
+
+#define SPI_DW_SPI_CLOCK	NS16550_F0009000_CLOCK_FREQUENCY
+
+
+/* End of SoC Level DTS fixup file */

arch/arc/soc/snps_emsk/linker.ld

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit platform.
+ */
+
+#include <generated_dts_board.h>
+
+/*
+ * DRAM base address and size
+ *
+ * DRAM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+#if defined(CONFIG_SRAM_BASE_ADDRESS) && (CONFIG_SRAM_SIZE > 0)
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
+#endif
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#if defined(CONFIG_ICCM_BASE_ADDRESS) && (CONFIG_ICCM_SIZE > 0)
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+#endif
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#if defined(CONFIG_DCCM_BASE_ADDRESS) && (CONFIG_DCCM_SIZE > 0)
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+#endif
+
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/snps_emsk/soc.h

@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+#define SYSCLK_DEFAULT_IOSC_HZ			MHZ(50)
+
+/* ARC EM Core IRQs */
+#define IRQ_TIMER0				16
+#define IRQ_TIMER1				17
+
+#if defined(CONFIG_BOARD_EM_STARTERKIT_R23) && defined(CONFIG_SOC_EMSK_EM7D)
+#define IRQ_SEC_TIMER0				20
+#endif /* CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EMSK_EM7D */
+
+#if defined(CONFIG_BOARD_EM_STARTERKIT_R23) && defined(CONFIG_SOC_EMSK_EM7D)
+#define IRQ_CORE_DMA_COMPLETE			22
+#define IRQ_CORE_DMA_ERROR			23
+#else /* CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EMSK_EM7D */
+#define IRQ_CORE_DMA_COMPLETE			20
+#define IRQ_CORE_DMA_ERROR			21
+#endif /* !(CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EMSK_EM7D) */
+
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <random/rand32.h>
+
+#define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
+#define ARCV2_TIMER0_INT_PRI			0
+
+#define ARCV2_TIMER1_INT_LVL			IRQ_TIMER1
+#define ARCV2_TIMER1_INT_PRI			1
+
+#define INT_ENABLE_ARC				~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS			(8)
+
+/*
+ * UARTs: UART0 & UART1 & UART2
+ */
+#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS	0 /* Default */
+#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS	0 /* Default */
+#define CONFIG_UART_NS16550_PORT_2_IRQ_FLAGS	0 /* Default */
+
+#ifndef CONFIG_HAS_DTS
+/* I2C */
+/* I2C_0 is on Pmod2 connector */
+#define CONFIG_I2C_0_BASE_ADDR			0xF0004000
+#define CONFIG_I2C_0_IRQ_FLAGS			0
+
+/* I2C_1 is on Pmod4 connector */
+#define CONFIG_I2C_1_BASE_ADDR			0xF0005000
+#define CONFIG_I2C_1_IRQ_FLAGS			0
+
+
+/* GPIO */
+#define GPIO_DW_0_BASE_ADDR			0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_BITS				32
+#define GPIO_DW_PORT_0_INT_MASK			0 /* n/a */
+#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
+
+#define GPIO_DW_1_BASE_ADDR			0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_BITS				9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK			0 /* n/a */
+
+#define GPIO_DW_2_BASE_ADDR			0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_BITS				32
+#define GPIO_DW_PORT_2_INT_MASK			0 /* n/a */
+
+#define GPIO_DW_3_BASE_ADDR			0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_BITS				12
+#define GPIO_DW_PORT_3_INT_MASK			0 /* n/a */
+
+/* SPI */
+#define SPI_DW_SPI_CLOCK			SYSCLK_DEFAULT_IOSC_HZ
+
+#define SPI_DW_PORT_0_REGS			0xF0006000
+#define SPI_DW_PORT_1_REGS			0xF0007000
+
+#define SPI_DW_IRQ_FLAGS			0
+
+/*
+ * SPI Chip Select Assignments on EM Starter Kit
+ *
+ *  CS0   Pmod6 - pin 1 - J6
+ *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
+ *  CS2   Pmod6 - pin 8 - J6
+ *  CS3   SDCard (onboard)
+ *  CS4   Internal SPI Slave - loopback
+ *  CS5   SPI-Flash (onboard)
+ */
+
+/**
+ * Peripheral Interrupt Connection Configurations
+ */
+#ifdef CONFIG_BOARD_EM_STARTERKIT_R23
+#define GPIO_DW_0_IRQ				24
+#define CONFIG_I2C_0_IRQ			25
+#define CONFIG_I2C_1_IRQ			26
+#define SPI_DW_PORT_0_IRQ			27
+#define SPI_DW_PORT_1_IRQ			28
+#else /* CONFIG_BOARD_EM_STARTERKIT_R23 */
+#define GPIO_DW_0_IRQ				22
+#define CONFIG_I2C_0_IRQ			23
+#define CONFIG_I2C_1_IRQ			24
+#define SPI_DW_PORT_0_IRQ			25
+#define SPI_DW_PORT_1_IRQ			26
+#endif /* !CONFIG_BOARD_EM_STARTERKIT_R23 */
+
+#define GPIO_DW_1_IRQ				0	/* can't interrupt */
+#define GPIO_DW_2_IRQ				0	/* can't interrupt */
+#define GPIO_DW_3_IRQ				0	/* can't interrupt */
+
+#endif /* CONFIG_HAS_DTS */
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _SOC__H_ */

arch/arc/soc/snps_emsk/soc_config.c

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_write32(0, CONFIG_UART_NS16550_PORT_0_BASE_ADDR+0x4);
+	sys_write32(0, CONFIG_UART_NS16550_PORT_0_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_write32(0, CONFIG_UART_NS16550_PORT_1_BASE_ADDR+0x4);
+	sys_write32(0, CONFIG_UART_NS16550_PORT_1_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/snps_nsim/CMakeLists.txt

@@ -0,0 +1,14 @@
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+
+zephyr_cc_option(-mcpu=${GCC_M_CPU})
+zephyr_cc_option(-mno-sdata -mdiv-rem -mswap -mnorm)
+zephyr_cc_option(-mmpy-option=6 -mbarrel-shifter)
+zephyr_cc_option(--param l1-cache-size=16384)
+zephyr_cc_option(--param l1-cache-line-size=32)
+zephyr_cc_option_ifdef(CONFIG_CODE_DENSITY -mcode-density)
+zephyr_cc_option_ifdef(CONFIG_FLOAT -mfpu=fpuda_all)
+
+zephyr_sources(
+  soc.c
+  soc_config.c
+  )

arch/arc/soc/snps_nsim/Kconfig

@@ -0,0 +1,26 @@
+#
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_NSIM
+
+choice
+prompt "ARC EM Starter Kit Core Selection"
+default SOC_NSIM_EM
+
+config SOC_NSIM_EM
+	bool "Synopsys ARC EM of nsim"
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU
+
+config SOC_NSIM_SEM
+	bool "Synopsys ARC SEM of nsim"
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU
+	select ARC_HAS_SECURE
+
+endchoice
+
+endif #SOC_NSIM

arch/arc/soc/snps_nsim/Kconfig.defconfig

@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_NSIM
+
+config SOC
+	string
+	default "snps_nsim"
+
+config UART_CONSOLE_ON_DEV_NAME
+	string
+	default "UART_0"
+
+source "arch/arc/soc/snps_nsim/Kconfig.defconfig.em"
+source "arch/arc/soc/snps_nsim/Kconfig.defconfig.sem"
+
+endif #SOC_NSIM

arch/arc/soc/snps_nsim/Kconfig.defconfig.em

@@ -0,0 +1,56 @@
+#
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_NSIM_EM
+
+config CPU_EM4_DMIPS
+	def_bool y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 20
+
+config ARC_MPU_VER
+	default 2
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 10000000
+
+config HARVARD
+	def_bool y
+
+config ARC_FIRQ
+	def_bool y
+
+config CACHE_FLUSHING
+	def_bool y
+
+if (ARC_MPU_VER = 2)
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+if ZTEST
+
+config ZTEST_STACKSIZE
+	default 2048
+
+endif # ZTEST
+
+endif # ARC_MPU_VER
+
+endif #SOC_NSIM_EM

arch/arc/soc/snps_nsim/Kconfig.defconfig.sem

@@ -0,0 +1,39 @@
+#
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_NSIM_SEM
+
+config CPU_EM4_DMIPS
+	def_bool y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 22
+
+config ARC_MPU_VER
+	default 3
+
+config RGF_NUM_BANKS
+	default 1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 10000000
+
+config HARVARD
+	def_bool y
+
+config ARC_FIRQ
+	def_bool n
+
+config CACHE_FLUSHING
+	def_bool y
+
+endif #SOC_NSIM_SEM

arch/arc/soc/snps_nsim/Kconfig.soc

@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_NSIM
+	bool "Synopsys NSIM simulator for ARC EM"

arch/arc/soc/snps_nsim/dts.fixup

@@ -0,0 +1,10 @@
+/* SoC level DTS fixup file */
+
+/* CCM configuration */
+#define CONFIG_DCCM_BASE_ADDRESS       ARC_DCCM_80000000_BASE_ADDRESS
+#define CONFIG_DCCM_SIZE               (ARC_DCCM_80000000_SIZE >> 10)
+
+#define CONFIG_ICCM_BASE_ADDRESS       ARC_ICCM_0_BASE_ADDRESS
+#define CONFIG_ICCM_SIZE               (ARC_ICCM_0_SIZE >> 10)
+
+/* End of SoC Level DTS fixup file */

arch/arc/soc/snps_nsim/linker.ld

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit platform.
+ */
+
+#include <generated_dts_board.h>
+
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#if defined(CONFIG_ICCM_BASE_ADDRESS) && (CONFIG_ICCM_SIZE > 0)
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+#endif
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#if defined(CONFIG_DCCM_BASE_ADDRESS) && (CONFIG_DCCM_SIZE > 0)
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+#endif
+
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/snps_nsim/soc.c

@@ -0,0 +1,14 @@
+/* soc.c - system/hardware module for nsim */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the ARC EM Starter kit board.
+ *
+ * Nothing to be done for now.
+ */

arch/arc/soc/snps_nsim/soc.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#include <misc/util.h>
+
+/* ARC EM Core IRQs */
+#define IRQ_TIMER0				16
+#define IRQ_TIMER1				17
+
+#define IRQ_SEC_TIMER0			20
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <random/rand32.h>
+
+#define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
+#define ARCV2_TIMER0_INT_PRI			0
+
+#define ARCV2_TIMER1_INT_LVL			IRQ_TIMER1
+#define ARCV2_TIMER1_INT_PRI			1
+
+#define INT_ENABLE_ARC				~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS			(8)
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _SOC__H_ */

arch/arc/soc/snps_nsim/soc_config.c

@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"