Update version to 1.6.99

Set the stage for 1.7 development

Change-Id: I9f65d5c4ca5ad6c40e1462d73e3db13e4b13ac02
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.checkpatch.conf

@@ -14,4 +14,9 @@
 --ignore PREFER_KERNEL_TYPES
 --ignore AVOID_EXTERNS
 --ignore NETWORKING_BLOCK_COMMENT_STYLE
+--ignore DATE_TIME
+--ignore MINMAX
+--ignore CONST_STRUCT
+--ignore FILE_PATH_CHANGES
 --exclude ext
+--exclude net/ip/contiki

.gitignore

@@ -2,6 +2,7 @@
 *.a
 *.d
 *.cmd
+*.log
 *.pyc
 *.swp
 *.swo
@@ -9,6 +10,7 @@
 cscope.*
 .dir
 outdir
+outdir-*
 scripts/basic/fixdep
 scripts/gen_idt/gen_idt
 scripts/gen_offset_header/gen_offset_header

.known-issues/README

@@ -0,0 +1,55 @@
+This directory contains configuration files to ignore errors found in
+the build and test process which are known to the developers and for
+now can be safely ignored.
+
+To use:
+
+ $ cd zephyr
+ $ make SOMETHING >& result
+ $ scripts/filter-known-issues.py result
+
+It is included in the source tree so if anyone has to submit anything
+that triggers some kind of error that is a false positive, it can
+include the "ignore me" file, properly documented.
+
+Each file can contain one or more multiline Python regular expressions
+(https://docs.python.org/2/library/re.html#regular-expression-syntax)
+that match an error message. Multiple regular expressions are
+separated by comment blocks (that start with #). Note that an empty
+line still is considered part of the multiline regular expression.
+
+For example
+
+---beginning---
+#
+# This testcase always fails, pending fix ZEP-1234
+#
+.*/tests/kernel/grumpy .* FAIL
+#
+# Documentation issue, masks:
+#
+# /home/e/inaky/z/kernel.git/doc/api/io_interfaces.rst:28: WARNING: Invalid definition: Expected identifier in nested name. [error at 19]
+#  struct dev_config::@65  dev_config::bits
+#  -------------------^
+#
+^(?P<filename>.+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^\s+struct dev_config::@[0-9]+  dev_config::bits.*
+^\s+-+\^
+---end---
+
+Note you want to:
+
+- use relateive paths; instead of
+  /home/me/mydir/zephyr/something/somewhere.c you will want
+  ^.*/something/somewhere.c (as they will depend on where it is being
+  built)
+
+- Replace line numbers with [0-9]+, as they will change
+
+- (?P<filename>[-._/\w]+/something/somewhere.c) saves the match on
+  that file path in a "variable" called 'filename' that later you can
+  match with (?P=filename) if you want to match multiple lines of the
+  same error message.
+
+Can get really twisted and interesting in terms of regexps; they are
+powerful, so start small :)

.known-issues/doc/bluetooth.conf

@@ -0,0 +1,38 @@
+#
+# Bluetooth unnamed struct definition
+#
+# FIXME: all these should match the relative filename
+#
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^[ \t]*$
+^[ \t]*\^$
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^[ \t]*$
+^[ \t]*\^$
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]$
+^.*bt_conn_info.__unnamed__.*$
+^[- \t]*\^$
+#
+# bt_gatt_discover_params unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_gatt_discover_params.__unnamed__.*
+^[- \t]*\^
+#
+# Bluetooth GATT unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_gatt_read_params.__unnamed__.*
+^[- \t]*\^

.known-issues/doc/header_footer.conf

@@ -0,0 +1,18 @@
+#
+# KERNELVERSION not being defined in local builds, kill that warning,
+# can ignore it
+#
+^.*/Kconfig.zephyr:[0-9]+: warning: The symbol KERNELVERSION references the non-existent environment variable KERNELVERSION.*
+#
+# Documentation generation, early message
+#
+^cd .* && doxygen doc/doxygen.config
+^srctree=.* SRCARCH=\w+ python scripts/genrest/genrest.py .*$
+# This cuts the sphinx build line; has to be separate because in the
+# middle, we have removed the KERNELVERSION one and a full regex won't match
+^sphinx-build -t \w+ -b html -d [-._/\w]+  -q \. .*
+#
+# Documentation generation, footer message
+#
+^[ \t]*
+^Build finished. The HTML pages are in [-._/\w]+

.known-issues/doc/sensor.conf

@@ -0,0 +1,12 @@
+#
+# Sensor value unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*sensor_value.__unnamed__.*
+^[- \t]*\^

.known-issues/doc/uart.conf

@@ -0,0 +1,15 @@
+#
+# UART unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*uart_device_config.__unnamed__.*
+^[- \t]*\^

.known-issues/make.conf

@@ -0,0 +1,6 @@
+#
+# When filtering output of the build process, ignore lines that don't
+# provide any information that helps the invoker tell if there was an
+# error.
+#
+^make: (Entering|Leaving) directory .*

.known-issues/testcases/block.conf

@@ -0,0 +1,11 @@
+#
+# When executing test cases, ignore the following messages as they are
+# not to be considered hard errors.
+#
+# Block line when test case cannot run in the HW due to server or connection issues
+#
+^BLCK0/[-a-z0-9:]+	(.+)#test @[^/]+/[^:]+:[^:]+: evaluation blocked(.*)$
+#
+# Block line when there is an issue with the YKUSH serial connection
+#
+^BLCK0/[-a-z0-9:]+	(.+)#test @[^/]+/(?P<board>[^:]+):[^:]+: exception: 400: (?P=board): Cannot find YKUSH serial '[A-Z0-9]+'$

.known-issues/testcases/makefile.conf

@@ -0,0 +1,18 @@
+#
+# When executing test cases under TCF, ignore the following messages
+# as they are not to be considered hard errors.
+#
+# TCF is run under make for taking advantage of the jobserver; when
+# the testcase execution fail, make will complain, which we can
+# ignore ('sommersault' was the old name of the target).
+#
+^/tmp/tcf-[a-zA-Z0-9]+.mk:[0-9]+: recipe for target ('tcf-jobserver-run'|'sommersault') failed$
+#
+# More of the same
+#
+^make: \*\*\* \[(tcf-jobserver-run|sommersault)\] Error 1$
+#
+# TCF's summary line. We don't need to consider it to determine if the
+# run failed or passed.
+#
+^[A-Z]+0/\S+:\s+\S+\s+@\S+: [0-9]+ tests \([0-9]+ passed, [0-9]+ failed, [0-9]+ blocked, [0-9]+ skipped\).*$

.known-issues/testcases/skip.conf

@@ -0,0 +1,4 @@
+#
+# Skip line when test case is eliminated due to filters
+#
+^SKIP0/\S+\s+\S+: No targets can be used \(all [0-9]+ selected from [0-9]+ available eliminated by testcase filtering\)$

.mailmap

@@ -11,3 +11,10 @@ Bit Pathe <bitpathe@gmail.com> <bitpathe@gmail.com>
 Carles Cufi <carles.cufi@nordicsemi.no> <carles.cufi@nordicsemi.no>
 Kuo-Lang Tseng <kuo-lang.tseng@intel.com> <kuo-lang.tseng@intel.com>
 Gerardo Aceves <gerardo.aceves@intel.com> <gerardo.aceves@intel.com>
+Evan Couzens <evanx.couzens@intel.com> <evanx.couzens@intel.com>
+Lei Liu <lei.a.liu@intel.com> <lei.a.liu@intel.com>
+Douglas Su <d0u9.su@outlook.com> <d0u9.su@outlook.com>
+Keren Siman-Tov <keren.siman-tov@intel.com> <keren.siman-tov@intel.com>
+Naga Raja Rao Tulasi <tulasi.r@tcs.com> <tulasi.r@tcs.com>
+Felipe Neves <ryukokki.felipe@gmail.com> <ryukokki.felipe@gmail.com>
+Amir Kaplan <amir.kaplan@intel.com> <amir.kaplan@intel.com>

Kbuild

@@ -1,11 +1,5 @@
 # vim: filetype=make
 
-ifneq ($(strip $(CONFIG_MAX_NUM_TASK_IRQS)),)
-ifneq (${CONFIG_MAX_NUM_TASK_IRQS},0)
-TASK_IRQS=y
-endif
-endif
-
 ifneq ("$(wildcard $(MDEF_FILE))","")
 MDEF_FILE_PATH=$(strip $(MDEF_FILE))
 else
@@ -14,6 +8,20 @@ MDEF_FILE_PATH=$(strip $(PROJECT_BASE)/$(MDEF_FILE))
 endif
 endif
 
+ifeq (${CONFIG_NUM_COMMAND_PACKETS},)
+CONFIG_NUM_COMMAND_PACKETS=0
+endif
+ifeq (${CONFIG_NUM_TIMER_PACKETS},)
+CONFIG_NUM_TIMER_PACKETS=0
+endif
+ifeq (${CONFIG_NUM_TASK_PRIORITIES},)
+CONFIG_NUM_TASK_PRIORITIES=$(CONFIG_NUM_PREEMPT_PRIORITIES)
+endif
+
+ifeq ($(ARCH),x86)
+TASKGROUP_SSE="  TASKGROUP SSE"
+endif
+
 define filechk_prj.mdef
 	(echo "% WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY!"; \
 	echo; \
@@ -25,19 +33,9 @@ define filechk_prj.mdef
 	echo "% ==============";\
 	echo "  TASKGROUP EXE";\
 	echo "  TASKGROUP SYS";\
-	echo "  TASKGROUP FPU";\
-	echo "  TASKGROUP SSE";\
+	echo "  TASKGROUP FPU_LEGACY";\
+	echo $(TASKGROUP_SSE);\
 	echo; \
-	if test "$(TASK_IRQS)" = "y"; then \
-		echo "% Task IRQ objects";\
-		echo "% EVENT    NAME              HANDLER"; \
-		echo "% ======================================="; \
-		i=0; \
-		while [ $$i -lt $(CONFIG_MAX_NUM_TASK_IRQS) ]; do \
-			echo "  EVENT    _TaskIrqEvt$$i     NULL"; \
-		i=$$(($$i+1));\
-		done; \
-	fi; \
 	if test -e "$(MDEF_FILE_PATH)"; then \
 		cat $(MDEF_FILE_PATH); \
 	fi;)
@@ -47,8 +45,15 @@ misc/generated/sysgen/prj.mdef:	$(MDEF_FILE_PATH) \
 				include/config/auto.conf FORCE
 	$(call filechk,prj.mdef)
 
-misc/generated/sysgen/kernel_main.c: misc/generated/sysgen/prj.mdef
-	$(Q)$(srctree)/scripts/sysgen $(CURDIR)/misc/generated/sysgen/prj.mdef $(CURDIR)/misc/generated/sysgen/
+sysgen_cmd=$(strip \
+	$(PYTHON) $(srctree)/scripts/sysgen \
+	-i $(CURDIR)/misc/generated/sysgen/prj.mdef \
+	-o $(CURDIR)/misc/generated/sysgen/ \
+)
+
+misc/generated/sysgen/kernel_main.c: misc/generated/sysgen/prj.mdef \
+				     $(srctree)/scripts/sysgen
+	$(Q)$(sysgen_cmd)
 
 define filechk_configs.c
 	(echo "/* file is auto-generated, do not modify ! */"; \
@@ -74,7 +79,7 @@ targets += include/generated/offsets.h
 always := misc/generated/configs.c
 always += include/generated/offsets.h
 
-ifeq ($(CONFIG_MICROKERNEL),y)
+ifeq ($(CONFIG_MDEF),y)
 targets += misc/generated/sysgen/kernel_main.c
 always += misc/generated/sysgen/kernel_main.c
 endif
@@ -87,8 +92,8 @@ OFFSETS_INCLUDE = $(strip \
 		-include $(CURDIR)/include/generated/autoconf.h \
 		-I $(srctree)/include \
 		-I $(CURDIR)/include/generated \
-		-I $(srctree)/kernel/microkernel/include \
-		-I $(srctree)/kernel/nanokernel/include \
+		-I $(srctree)/kernel/unified/include \
+		$(OFFSETS_INCLUDE_KERNEL_LOCATION) \
 		-I $(srctree)/lib/libc/minimal/include \
 		-I $(srctree)/arch/${ARCH}/include )
 

Kconfig.zephyr

@@ -32,14 +32,18 @@ source "misc/Kconfig"
 
 source "lib/Kconfig"
 
+source "subsys/Kconfig"
+
 source "ext/Kconfig"
 
+source "tests/Kconfig"
+
 #
 # The following are for Kconfig files for default values only.
 # These should be parsed at the end.
 #
-# Board defaults should be parsed before SoC defaults
-# because board usually overrides them.
+# Board defaults should be parsed after SoC defaults
+# because board usually overrides SoC values.
 #
-source "boards/*/Kconfig.defconfig"
 source "arch/*/soc/*/Kconfig.defconfig"
+source "boards/*/*/Kconfig.defconfig"

LICENSING.rst

@@ -0,0 +1,66 @@
+.. _zephyr_licensing:
+
+Licensing of Zephyr Project components
+######################################
+
+The Zephyr kernel tree imports or reuses packages, scripts and other
+files that are not covered by the :download:`Apache License
+<../LICENSE>`. In some places there is no LICENSE file or way to put
+a LICENSE file there, so we describe the licensing in this document.
+
+
+- *kconfig* and *kbuild*
+
+  *Origin:* Linux Kernel
+  *Licensing:* *GPLv2*
+
+- *scripts/{checkpatch.pl,checkstack.pl,get_maintainers.pl,spelling.txt}*
+
+  *Origin:* Linux Kernel
+  *Licensing:* *GPLv2*
+
+- *ext/fs/fat/*
+
+  *Origin:* FatFs is a file system based on the FAT file system specification.  This is
+  provided by ELM Chan http://elm-chan.org/fsw/ff/00index_e.html
+
+  *Licensing*:
+
+    Copyright (C) 2016, ChaN, all right reserved.
+
+    FatFs module is an open source software. Redistribution and use of FatFs in
+    source and binary forms, with or without modification, are permitted provided
+    that the following condition is met:
+
+    1. Redistributions of source code must retain the above copyright notice,
+       this condition and the following disclaimer.
+
+    This software is provided by the copyright holder and contributors "AS IS"
+    and any warranties related to this software are DISCLAIMED.
+    The copyright owner or contributors be NOT LIABLE for any damages caused
+    by use of this software.
+
+- *ext/hal/cmsis/*
+
+  *Origin:* https://github.com/ARM-software/CMSIS.git
+
+  *Licensing*: :download:`CMSIS_END_USER_LICENCE_AGREEMENT <../ext/hal/cmsis/CMSIS_END_USER_LICENCE_AGREEMENT.pdf>`
+
+- *ext/hal/ksdk/*
+
+  *Origin:* http://kex.nxp.com
+
+  *Licensing*: 3-clause BSD (see :download:`source
+  <../ext/hal/ksdk/drivers/fsl_rtc.h>`)
+
+- *ext/hal/nordic/*
+
+  *Origin:*
+
+  *Licensing*: 3-clause BSD (see :download:`source <../ext/hal/nordic/mdk/nrf51.h>`)
+
+- *ext/hal/qmsi/*
+
+  *Origin:* https://github.com/quark-mcu/qmsi/releases
+
+  *Licensing*: 3-clause BSD (see :download:`source <../ext/hal/qmsi/include/qm_common.h>`)

MAINTAINERS

@@ -59,32 +59,289 @@ Maintainers List (try to look for most precise areas first)
 
 		-----------------------------------
 
+ARC ARCHITECTURE
+M:	Ruud Derwig <Ruud.Derwig@synopsys.com>
+M:	Chuck Jordan <cjordan@synopsys.com>
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+S:	Supported
+F:	arch/arc/
+F:	include/arch/arc/
+F:	boards/arc/
+
+ARM ARCHITECTURE
+M:	Maureen Helm <maureen.helm@nxp.com>
+M:	Kumar Gala <kumar.gala@linaro.org>
+S:	Supported
+F:	arch/arm/
+F:	include/arch/arm/
+F:	boards/arm/
+
+ARM CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD (CMSIS)
+M:	Maureen Helm <maureen.helm@nxp.com>
+M:	Kumar Gala <kumar.gala@linaro.org>
+S:	Supported
+F:	ext/hal/cmsis/
+
+BOARDS/ARC - ARDUINO 101 SSS
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/arc/arduino_101_sss/
+
+BOARDS/ARC - EM Starterkit
+M:	Chuck Jordan <cjordan@synopsys.com>
+S:	Supported
+F:	boards/arc/em_starterkit/
+
+BOARDS/ARC - QUARK SE C1000 SS Devboard
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/arc/quark_se_c1000_ss_devboard/
+
+BOARDS/ARM - 96Boards CARBON
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	boards/arm/96b_carbon/
+
+BOARDS/ARM - 96Boards NITROGEN
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+S:	Supported
+F:	boards/arm/96b_nitrogen/
+
+BOARDS/ARM - ARDUINO 101 BLE
+M:	Johan Hedberg <johan.hedberg@intel.com>
+S:	Supported
+F:	boards/arm/arduino_101_ble/
+
+BOARDS/ARM - CC3200 LAUNCHXL
+M:      Gil Pitney <gil.pitney@linaro.org>
+S:      Supported
+F:      boards/arm/cc3200_launchxl/
+
+BOARDS/ARM - NXP FRDM-K64F
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	boards/arm/frdm_k64f/
+
+BOARDS/ARM - NXP Hexiwear
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	boards/arm/hexiwear_k64/
+
+BOARDS/ARM - NORDIC NRF51 REDBEAR BLENANO
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	boards/arm/nrf51_blenano/
+
+BOARDS/ARM - NORDIC NRF52 PCA10040
+M:	Carles Cufi <carles.cufi@nordicsemi.no>
+S:	Supported
+F:	boards/arm/nrf52_pca10040/
+
+BOARDS/ARM - NUCLEO-64 F401RE Devboard
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	boards/arm/nucleo_f401re/
+
+BOARDS/ARM - ARM LTD V2M Beetle
+M:	Vincenzo Frascino <vincenzo.frascino@linaro.org>
+S:	Supported
+F:	boards/arm/v2m_beetle/
+
+BOARDS/NIOS2 - ALTERA MAX10
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	boards/nios2/altera_max10/
+
+BOARDS/X86 - ARDUINO 101
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/arduino_101/
+
+BOARDS/X86 - Galileo
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/galileo/
+
+BOARDS/X86 - QUARK D2000 Devboard
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/quark_d2000/
+
+BOARDS/X86 - QUARK SE C1000 Devboard
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/quark_se_c1000/
+
 BLUETOOTH
 M:	Johan Hedberg <johan.hedberg@intel.com>
 M:	Luiz Augusto von Dentz <luiz.dentz@gmail.com>
 M:	Szymon Janc <szymon.janc@gmail.com>
 S:	Supported
-F:	net/bluetooth/
+W:	https://www.zephyrproject.org/doc/subsystems/bluetooth/bluetooth.html
+F:	subsys/bluetooth/
 F:	include/bluetooth/
 F:	drivers/bluetooth/
 F:	samples/bluetooth/
 F:	tests/bluetooth/
+F:	doc/subsystems/bluetooth/
+
+BLUETOOTH CONTROLLER
+M:	Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
+M:	Carles Cufi <carles.cufi@nordicsemi.no>
+S:	Supported
+F:	subsys/bluetooth/controller/
+
+CC3200 SDK
+M:      Gil Pitney <gil.pitney@linaro.org>
+S:      Supported
+F:      ext/hal/cc3200sdk/
+
+CC32XX SOC - TI SIMPLELINK
+M:      Gil Pitney <gil.pitney@linaro.org>
+S:      Supported
+F:      arch/arm/soc/ti_simplelink/
 
 DOCUMENTATION
+M:	Kinder, David <david.b.kinder@intel.com>
 M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
 S:	Supported
 F:	doc/
 
+FILE SYSTEM
+M:	Ramesh Thomas <ramesh.thomas@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	ext/fs/
+F:	subsys/fs/
+F:	include/fs/
+F:	include/fs.h
+F:	samples/fs/
+
 FLASH DRIVER
 M:	Baohong Liu <baohong.liu@intel.com>
 M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
 S:	Supported
 F:	drivers/flash/
 
+INTERRUPTS
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	drivers/interrupt_controller/
+F:	arch/arc/core/
+F:	arch/arm/core/
+F:	arch/nios2/core/
+F:	arch/x86/core/
+F:	include/irq.h
+F:	include/arch/x86/arch.h
+F:	include/arch/arm/cortex_m/irq.h
+F:	include/arch/nios2/arch.h
+F:	include/arch/arc/arch.h
+F:	include/arch/arc/v2/irq.h
+F:	include/drivers/loapic.h
+F:	include/drivers/ioapic.h
+F:	include/drivers/mvic.h
+
+KERNEL CORE
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+M:	Allan Stephens <allan.stephens@windriver.com>
+M:	Andrew Boie <andrew.p.boie@intel.com>
+M:	Andy Ross <andrew.j.ross@intel.com>
+S:	Supported
+F:	kernel/
+F:	include/nanokernel.h
+F:	include/microkernel.h
+F:	include/microkernel/
+F:	include/misc/
+F:	include/toolchain/
+F:	include/atomic.h
+F:	include/cache.h
+F:	include/init.h
+F:	include/irq.h
+F:	include/irq_offload.h
+F:	include/kernel_version.h
+F:	include/linker-defs.h
+F:	include/linker-tool-gcc.h
+F:	include/linker-tool.h
+F:	include/section_tags.h
+F:	include/sections.h
+F:	include/shared_irq.h
+F:	include/sw_isr_table.h
+F:	include/sys_clock.h
+F:	include/sys_io.h
+F:	include/toolchain.h
+F:	include/zephyr.h
+F:	include/kernel.h
+F:	include/legacy.h
+
+KINETIS SOFTWARE DEVELOPMENT KIT (KSDK)
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	ext/hal/ksdk/
+
+KNOWN ISSUES
+M:	Anas Nashif <anas.nashif@intel.com>
+M:	Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+M:	Javier B Perez <javier.b.perez.hernandez@intel.com>
+F:	.known-issues/
+
+
+MAINTAINERS
+M:	Javier B Perez <javier.b.perez.hernandez@intel.com>
+M:	Anas Nashif <anas.nashif@intel.com>
+M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
+S:	Supported
+F:	MAINTAINERS
+
+MBEDTLS
+M:	Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
+M:	Jithu Joseph <jithu.joseph@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	ext/lib/crypto/mbedtls/
+F:	samples/net/mbedtls_sslclient/
+F:	tests/crypto/test_mbedtls/
+
+NETWORKING
+M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/networking/networking.html
+F:	net/ip/
+F:	include/net/
+F:	samples/net/
+F:	tests/net/
+
+NETWORK APPLICATIONS
+M:	Flavio Santes <flavio.santes@intel.com>
+S:	Supported
+F:	samples/net/dns_client/
+F:	samples/net/nats_clients/
+F:	samples/net/paho_mqtt_clients/
+
+NETWORK BUFFERS
+M:	Johan Hedberg <johan.hedberg@intel.com>
+M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/networking/buffers.html
+F:	net/buf.c
+F:	include/net/buf.h
+F:	tests/net/buf/
+
+NIOS II
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	arch/nios2/
+F:	include/arch/nios2/
+F:	drivers/serial/uart_altera_jtag.c
+F:	drivers/timer/altera_avalon_timer.c
+F:	tests/kernel/test_intmath/
+F:	boards/nios2/
+
 NORDIC MDK
 M:	Carles Cufi <carles.cufi@nordicsemi.no>
 S:	Supported
-F:	ext/hal/nordic/mdk
+F:	ext/hal/nordic/mdk/
 
 POWER MANAGEMENT
 M:	Ramesh Thomas <ramesh.thomas@intel.com>
@@ -111,6 +368,21 @@ S:	Supported
 F:	drivers/*/*qmsi*
 F:	drivers/*/*/*qmsi*
 
+QUARK D2000 SOC
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	arch/x86/soc/intel_quark/quark_d2000/
+
+QUARK SE C1000 SOC
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	arch/x86/soc/intel_quark/quark_se_c1000/
+
+QUARK X1000 SOC
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	arch/x86/soc/intel_quark/quark_x1000/
+
 SANITYCHECK
 M:	Andrew Boie <andrew.p.boie@intel.com>
 S:	Supported
@@ -118,13 +390,64 @@ F:	scripts/sanitycheck
 F:	scripts/expr_parser.py
 F:	scripts/sanity_chk/
 
+SENSOR DRIVERS
+M:	Bogdan Davidoaia <bogdan.m.davidoaia@intel.com>
+M:	Laurentiu Palcu <laurentiu.palcu@intel.com>
+M:	Murtaza Alexandru <alexandru.murtaza@intel.com>
+M:	Vlad Dogaru <vlad.dogaru@intel.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/sensor.html
+F:	include/sensor.h
+F:	drivers/sensor/
+F:	samples/sensor/
+
+STM32CUBE SDK
+M:	Erwan Gouriou <erwan.gouriou@linaro.org>
+S:	Supported
+F:	ext/hal/st/stm32cube/
+
+STM32F4X SoC FAMILY and DRIVERS
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	arch/arm/soc/st_stm32/stm32f4/
+F:	drivers/pinmux/stm32/
+F:	drivers/gpio/*stm32*
+F:	drivers/clock_control/*stm32f4*
+
 TINYCRYPT
 M:	Constanza Heath <constanza.m.heath@intel.com>
+M:	Flavio Santes <flavio.santes@intel.com>
 S:	Supported
-F:	ext/lib/crypto/tinycrypt
+F:	ext/lib/crypto/tinycrypt/
+F:	tests/crypto/
+
+USB
+M:	Jithu Joseph <jithu.joseph@intel.com>
+S:	Supported
+F:	subsys/usb
+F:	drivers/usb
+F:	samples/usb
+
+X86 ARCH
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+M:	Allan Stephens <allan.stephens@windriver.com>
+S:	Supported
+F:	arch/x86/
+F:	include/arch/x86/
+F:	boards/x86/
+
+ZOAP
+M:	Vinicius Costa Gomes <vinicius.gomes@intel.com>
+S:	Supported
+F:	lib/iot/zoap/
+F:	samples/net/zoap_client/
+F:	samples/net/zoap_server/
+F:	tests/net/zoap/
 
 THE REST
 M:	Anas Nashif <anas.nashif@intel.com>
+M:	Kumar Gala <kumar.gala@linaro.org>
 L:	devel@lists.zephyrproject.com
 T:	git https://gerrit.zephyrproject.org/r/a/zephyr
 S:	Buried alive in reporters

Makefile

@@ -1,6 +1,6 @@
 VERSION_MAJOR 	   = 1
-VERSION_MINOR 	   = 4
-PATCHLEVEL 	   = 0
+VERSION_MINOR 	   = 6
+PATCHLEVEL 	   = 99
 VERSION_RESERVED   = 0
 EXTRAVERSION       =
 NAME 		   = Zephyr Kernel
@@ -49,6 +49,7 @@ unexport GREP_OPTIONS
 
 DQUOTE = "
 #This comment line is to fix the highlighting of some editors due the quote effect."
+export DQUOTE
 
 # We are using a recursive build, so we need to do a little thinking
 # to get the ordering right.
@@ -102,9 +103,11 @@ endif
 ifeq ($(KBUILD_VERBOSE),1)
   quiet =
   Q =
+  GENIDT_EXTRA_ARGS = -d
 else
   quiet=quiet_
   Q = @
+  GENIDT_EXTRA_ARGS =
 endif
 
 # If the user is running make -s (silent mode), suppress echoing of
@@ -217,7 +220,7 @@ objtree		:= .
 src		:= $(srctree)
 obj		:= $(objtree)
 
-VPATH		:= $(srctree)
+VPATH		:= $(SOURCE_DIR_PARENT) $(srctree)
 
 export srctree objtree VPATH
 
@@ -266,8 +269,8 @@ CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
 	  else if [ -x /bin/bash ]; then echo /bin/bash; \
 	  else echo sh; fi ; fi)
 
-HOSTCC       = gcc
-HOSTCXX      = g++
+HOSTCC       ?= gcc
+HOSTCXX      ?= g++
 HOSTCFLAGS   = -Wall -Wmissing-prototypes -Wstrict-prototypes -O2 -fomit-frame-pointer -std=gnu89
 HOSTCXXFLAGS = -O2
 
@@ -313,8 +316,15 @@ OBJDUMP		= $(CROSS_COMPILE)objdump
 GDB		= $(CROSS_COMPILE)gdb
 READELF		= $(CROSS_COMPILE)readelf
 AWK		= awk
+ifeq ($(PREBUILT_HOST_TOOLS),)
 GENIDT		= scripts/gen_idt/gen_idt
 GENOFFSET_H	= scripts/gen_offset_header/gen_offset_header
+FIXDEP		= scripts/basic/fixdep
+else
+GENIDT		= $(PREBUILT_HOST_TOOLS)/gen_idt
+GENOFFSET_H	= $(PREBUILT_HOST_TOOLS)/gen_offset_header
+FIXDEP		= $(PREBUILT_HOST_TOOLS)/fixdep
+endif
 PERL		= perl
 PYTHON		= python
 CHECK		= sparse
@@ -348,16 +358,18 @@ BOARD_NAME = $(subst $(DQUOTE),,$(CONFIG_BOARD))
 KERNEL_NAME = $(subst $(DQUOTE),,$(CONFIG_KERNEL_BIN_NAME))
 KERNEL_ELF_NAME = $(KERNEL_NAME).elf
 KERNEL_BIN_NAME = $(KERNEL_NAME).bin
+KERNEL_HEX_NAME = $(KERNEL_NAME).hex
 KERNEL_STAT_NAME = $(KERNEL_NAME).stat
 
 export SOC_FAMILY SOC_SERIES SOC_PATH SOC_NAME BOARD_NAME
-export ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME
+export ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME KERNEL_HEX_NAME
 # Use ZEPHYRINCLUDE when you must reference the include/ directory.
 # Needed to be compatible with the O= option
 ZEPHYRINCLUDE    = \
+		-I$(srctree)/kernel/unified/include \
 		-I$(srctree)/arch/$(ARCH)/include \
 		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH) \
-		-I$(srctree)/boards/$(BOARD_NAME) \
+		-I$(srctree)/boards/$(ARCH)/$(BOARD_NAME) \
 		$(if $(KBUILD_SRC), -I$(srctree)/include) \
 		-I$(srctree)/include \
 		-I$(CURDIR)/include/generated \
@@ -365,19 +377,20 @@ ZEPHYRINCLUDE    = \
 		$(USERINCLUDE) \
 		$(STDINCLUDE)
 
-KBUILD_CPPFLAGS := -DKERNEL
+KBUILD_CPPFLAGS := -DKERNEL -D__ZEPHYR__=1
 
 KBUILD_CFLAGS   := -c -g -std=c99 \
 		-fno-asynchronous-unwind-tables \
-		-fno-omit-frame-pointer \
 		-Wall \
+		-Wformat \
+		-Wformat-security \
+		-D_FORTIFY_SOURCE=2 \
 		-Wno-format-zero-length \
 		-Wno-main -ffreestanding
 
 KBUILD_CXXFLAGS   := -c -g -std=c++11 \
 		-fno-reorder-functions \
 		-fno-asynchronous-unwind-tables \
-		-fno-omit-frame-pointer \
 		-fcheck-new \
 		-fno-defer-pop -Wall \
 		-Wno-unused-but-set-variable \
@@ -395,17 +408,33 @@ LDFLAGS += $(call ld-option,-static)
 
 KERNELVERSION = $(VERSION_MAJOR)$(if $(VERSION_MINOR),.$(VERSION_MINOR)$(if $(PATCHLEVEL),.$(PATCHLEVEL)))$(EXTRAVERSION)
 
-export VERSION_MAJOR VERSION_MINOR PATCHLEVEL VERSION_RESERVED EXTRAVERSION
-export KERNELRELEASE KERNELVERSION
-export ARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC CXX
-export CPP AR NM STRIP OBJCOPY OBJDUMP GDB
-export MAKE AWK INSTALLKERNEL PERL PYTHON GENIDT GENOFFSET_H
-export HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS
+exports += VERSION_MAJOR VERSION_MINOR PATCHLEVEL VERSION_RESERVED EXTRAVERSION
+exports += KERNELRELEASE KERNELVERSION
+exports += ARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC CXX
+exports += CPP AR NM STRIP OBJCOPY OBJDUMP GDB
+exports += MAKE AWK INSTALLKERNEL PERL PYTHON GENIDT GENOFFSET_H
+exports += HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS
 
-export KBUILD_CPPFLAGS NOSTDINC_FLAGS ZEPHYRINCLUDE OBJCOPYFLAGS LDFLAGS
-export KBUILD_CFLAGS KBUILD_CXXFLAGS CFLAGS_GCOV KBUILD_AFLAGS AFLAGS_KERNEL
-export KBUILD_ARFLAGS
+exports += KBUILD_CPPFLAGS NOSTDINC_FLAGS ZEPHYRINCLUDE OBJCOPYFLAGS LDFLAGS
+exports += KBUILD_CFLAGS KBUILD_CXXFLAGS CFLAGS_GCOV KBUILD_AFLAGS AFLAGS_KERNEL
+exports += KBUILD_ARFLAGS FIXDEP
 
+# Push the exports to sub-processes
+export $(exports)
+
+# Make the exports available to third-party build systems
+PHONY += outputexports
+outputexports: Makefile.export
+Makefile.export: include/config/auto.conf FORCE
+	$(call filechk,Makefile.export)
+
+define filechk_Makefile.export
+	(echo "# file is auto-generated, do not modify !"; \
+	echo "BOARD=$(BOARD)"; \
+	echo; \
+	$(foreach e,$(exports),echo $(e)=$($(e));) echo; \
+	echo "include $(O)/include/config/auto.conf";)
+endef
 
 # Files to ignore in find ... statements
 
@@ -420,10 +449,14 @@ export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
 
 # Basic helpers built in scripts/
 PHONY += scripts_basic
+ifeq ($(PREBUILT_HOST_TOOLS),)
 scripts_basic:
 	$(Q)$(MAKE) $(build)=scripts/basic
 	$(Q)$(MAKE) $(build)=scripts/gen_idt
 	$(Q)$(MAKE) $(build)=scripts/gen_offset_header
+else
+scripts_basic:
+endif
 
 # To avoid any implicit rule to kick in, define an empty command.
 scripts/basic/%: scripts_basic ;
@@ -515,9 +548,8 @@ PHONY += scripts
 scripts: scripts_basic include/config/auto.conf include/config/tristate.conf
 	$(Q)$(MAKE) $(build)=$(@)
 
-
-core-y := lib/ kernel/ misc/ net/ boards/ arch/ ext/
-drivers-y := drivers/
+# arch/ must be last here so that .gnu.linkonce magic for interrupts/exceptions
+# works as expected
 
 ifneq ($(strip $(MAKEFILE_APP_DIR)),)
 MAKEFILE_APP := $(realpath $(MAKEFILE_APP_DIR)/Makefile.app)
@@ -559,8 +591,14 @@ else
 include/config/auto.conf: ;
 endif # $(dot-config)
 
+# kernel objects are built as a static library
+libs-y := kernel/unified/
+core-y := lib/ misc/ net/ boards/ ext/ subsys/ tests/ arch/
+drivers-y := drivers/
+
 ARCH = $(subst $(DQUOTE),,$(CONFIG_ARCH))
 export ARCH
+
 ifdef ZEPHYR_GCC_VARIANT
 include $(srctree)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
 else
@@ -568,9 +606,8 @@ $(if $(CROSS_COMPILE),, \
      $(error ZEPHYR_GCC_VARIANT is not set. ))
 endif
 
-
--include $(srctree)/lib/Makefile
 -include $(srctree)/ext/Makefile
+-include $(srctree)/lib/Makefile
 
 ifneq ($(CC),)
 ifeq ($(shell $(CC) -v 2>&1 | grep -Ec "clang version|icx version"), 1)
@@ -581,9 +618,6 @@ endif
 export COMPILER
 endif
 
-QEMU_BIN_PATH	?= /usr/bin
-QEMU		= $(QEMU_BIN_PATH)/$(QEMU_$(ARCH))
-
 # The all: target is the default when no target is given on the
 # command line.
 # This allow a user to issue only 'make' to build a kernel including modules
@@ -601,7 +635,7 @@ KBUILD_CFLAGS += $(call cc-option,-fno-reorder-blocks,) \
 endif
 
 ifeq ($(CONFIG_DEBUG),y)
-KBUILD_CFLAGS  += -O0
+KBUILD_CFLAGS  += -Og
 else
 KBUILD_CFLAGS  += -Os
 endif
@@ -612,6 +646,14 @@ else
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector,)
 endif
 
+ifeq ($(CONFIG_OMIT_FRAME_POINTER),y)
+fp_arg := $(call cc-option,-fomit-frame-pointer,)
+else
+fp_arg := $(call cc-option,-fno-omit-frame-pointer,)
+endif
+KBUILD_CFLAGS += $(fp_arg)
+KBUILD_CXXFLAGS += $(fp_arg)
+
 KBUILD_CFLAGS += $(subst $(DQUOTE),,$(CONFIG_COMPILER_OPT))
 
 export LDFLAG_LINKERCMD
@@ -695,10 +737,13 @@ LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)--build-id=none)
 LD_TOOLCHAIN ?= -D__GCC_LINKER_CMD__
 
 ifdef CONFIG_HAVE_CUSTOM_LINKER_SCRIPT
-KBUILD_LDS         := $(subst $(DQUOTE),,$(CONFIG_CUSTOM_LINKER_SCRIPT))
+KBUILD_LDS := $(subst $(DQUOTE),,$(PROJECT_BASE)/$(CONFIG_CUSTOM_LINKER_SCRIPT))
+ifeq ($(wildcard $(KBUILD_LDS)),)
+KBUILD_LDS := $(subst $(DQUOTE),,$(CONFIG_CUSTOM_LINKER_SCRIPT))
+endif
 else
 # Try a board specific linker file
-KBUILD_LDS := $(srctree)/boards/$(BOARD_NAME)/linker.ld
+KBUILD_LDS := $(srctree)/boards/$(ARCH)/$(BOARD_NAME)/linker.ld
 
 # If not available, try an SoC specific linker file
 ifeq ($(wildcard $(KBUILD_LDS)),)
@@ -708,6 +753,14 @@ endif
 
 export LD_TOOLCHAIN KBUILD_LDS
 
+ifdef MAKEFILE_TOOLCHAIN_DO_PASS2
+# KBUILD_CFLAGS known at this point.
+# We can now determine which multilib libraries to use
+include $(srctree)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
+endif
+
+QEMU		= $(addsuffix /,$(QEMU_BIN_PATH))$(QEMU_$(ARCH))
+
 # The all: target is the default when no target is given on the
 # command line.
 # This allow a user to issue only 'make' to build a kernel including modules
@@ -722,22 +775,31 @@ all: $(KERNEL_BIN_NAME) $(KERNEL_STAT_NAME)
 export KBUILD_IMAGE ?= zephyr
 
 zephyr-dirs	:= $(patsubst %/,%,$(filter %/, $(core-y) $(drivers-y) \
-		     $(libs-y) $(app-y)))
+		     $(libs-y)))
 
-zephyr-alldirs	:= $(sort $(zephyr-dirs) $(patsubst %/,%,$(filter %/, \
+# Workaround for some make notdir implementations that require
+# the paramenter not to end in "/".
+zephyr-app-dir-root-name := $(patsubst %/,%, $(SOURCE_DIR))
+
+zephyr-app-dir-root := $(abspath $(patsubst %, %/.., $(SOURCE_DIR)))
+
+zephyr-alldirs	:= $(sort $(zephyr-dirs) $(SOURCE_DIR) $(patsubst %/,%,$(filter %/, \
 		     $(core-) $(drivers-) $(libs-) $(app-))))
 
 core-y		:= $(patsubst %/, %/built-in.o, $(core-y))
-app-y		:= $(patsubst %/, %/built-in.o, $(app-y))
+app-y		:= $(patsubst %, %/built-in.o, $(notdir $(zephyr-app-dir-root-name)))
 drivers-y	:= $(patsubst %/, %/built-in.o, $(drivers-y))
 libs-y1		:= $(patsubst %/, %/lib.a, $(libs-y))
 libs-y2		:= $(patsubst %/, %/built-in.o, $(libs-y))
 libs-y		:= $(libs-y1) $(libs-y2)
 
-export KBUILD_ZEPHYR_MAIN := $(drivers-y) $(libs-y) $(app-y) $(core-y)
+# core-y must be last here. several arches use .gnu.linkonce magic
+# to register interrupt or exception handlers, and defaults under
+# arch/ (part of core-y) must be linked after drivers or libs.
+export KBUILD_ZEPHYR_MAIN := $(drivers-y) $(libs-y) $(core-y)
 export LDFLAGS_zephyr
 
-zephyr-deps := $(KBUILD_LDS) $(KBUILD_ZEPHYR_MAIN)
+zephyr-deps := $(KBUILD_LDS) $(KBUILD_ZEPHYR_MAIN) $(app-y)
 
 ALL_LIBS += $(TOOLCHAIN_LIBS)
 export ALL_LIBS
@@ -747,19 +809,29 @@ LINK_LIBS := $(foreach l,$(ALL_LIBS), -l$(l))
 OUTPUT_FORMAT ?= elf32-i386
 OUTPUT_ARCH ?= i386
 
+quiet_cmd_ar_target = AR      $@
+# Do not put lib.a into libzephyr.a. lib.a files are to be linked separately to
+# the final image
+cmd_ar_target = rm -f $@; $(AR) rcT$(KBUILD_ARFLAGS) $@ \
+	$(filter-out %/lib.a, $(KBUILD_ZEPHYR_MAIN))
+libzephyr.a: $(zephyr-deps)
+	$(call cmd,ar_target)
+
 quiet_cmd_create-lnk = LINK    $@
       cmd_create-lnk =								\
 (										\
 	echo $(LDFLAGS_zephyr); 						\
-	echo "$(LINKFLAGPREFIX)-Map=$(O)/$(KERNEL_NAME).map"; 			\
+	echo "$(LINKFLAGPREFIX)-Map=$(KERNEL_NAME).map"; 			\
 	echo "-L $(objtree)/include/generated";					\
 	echo "-u _OffsetAbsSyms -u _ConfigAbsSyms"; 				\
 	echo "-e __start"; 						 	\
 	echo "$(LINKFLAGPREFIX)--start-group";					\
 	echo "$(LINKFLAGPREFIX)--whole-archive";				\
 	echo "$(KBUILD_ZEPHYR_APP)";						\
+	echo "$(app-y)";							\
+	echo "libzephyr.a";							\
 	echo "$(LINKFLAGPREFIX)--no-whole-archive";         			\
-	echo "$(KBUILD_ZEPHYR_MAIN)";						\
+	echo "$(filter %/lib.a, $(KBUILD_ZEPHYR_MAIN))";			\
 	echo "$(objtree)/arch/$(ARCH)/core/offsets/offsets.o"; 			\
 	echo "$(LINKFLAGPREFIX)--end-group"; 					\
 	echo "$(LIB_INCLUDE_DIR) $(LINK_LIBS)";					\
@@ -771,16 +843,12 @@ $(KERNEL_NAME).lnk: $(zephyr-deps)
 linker.cmd: $(zephyr-deps)
 	$(Q)$(CC) -x assembler-with-cpp -nostdinc -undef -E -P \
 	$(LDFLAG_LINKERCMD) $(LD_TOOLCHAIN) -I$(srctree)/include \
+	-I$(SOURCE_DIR) \
 	-I$(objtree)/include/generated $(EXTRA_LINKER_CMD_OPT) $(KBUILD_LDS) -o $@
 
-final-linker.cmd: $(zephyr-deps)
-	$(Q)$(CC) -x assembler-with-cpp -nostdinc -undef -E -P \
-	$(LDFLAG_LINKERCMD) $(LD_TOOLCHAIN) -DFINAL_LINK -I$(srctree)/include \
-	-I$(objtree)/include/generated $(EXTRA_LINKER_CMD_OPT) $(KBUILD_LDS) -o $@
+PREBUILT_KERNEL = $(KERNEL_NAME)_prebuilt.elf
 
-TMP_ELF = .tmp_$(KERNEL_NAME).prebuilt
-
-$(TMP_ELF): $(zephyr-deps) $(KBUILD_ZEPHYR_APP) linker.cmd $(KERNEL_NAME).lnk
+$(PREBUILT_KERNEL): $(zephyr-deps) libzephyr.a $(KBUILD_ZEPHYR_APP) $(app-y) linker.cmd $(KERNEL_NAME).lnk
 	$(Q)$(CC) -T linker.cmd @$(KERNEL_NAME).lnk -o $@
 
 quiet_cmd_gen_idt = SIDT    $@
@@ -788,27 +856,24 @@ quiet_cmd_gen_idt = SIDT    $@
 (										\
 	$(OBJCOPY) -I $(OUTPUT_FORMAT)  -O binary -j intList $< isrList.bin &&	\
 	$(GENIDT) -i isrList.bin -n $(CONFIG_IDT_NUM_VECTORS) -o staticIdt.bin 	\
-		-b int_vector_alloc.bin -m irq_int_vector_map.bin		\
-		-l $(CONFIG_MAX_IRQ_LINES) &&					\
+		-m irq_int_vector_map.bin					\
+		-l $(CONFIG_MAX_IRQ_LINES) $(GENIDT_EXTRA_ARGS) &&		\
 	$(OBJCOPY) -I binary -B $(OUTPUT_ARCH) -O $(OUTPUT_FORMAT) 		\
 		--rename-section .data=staticIdt staticIdt.bin staticIdt.o &&	\
-	$(OBJCOPY) -I binary -B $(OUTPUT_ARCH) -O $(OUTPUT_FORMAT) 		\
-		--rename-section .data=int_vector_alloc int_vector_alloc.bin	\
-		int_vector_alloc.o &&						\
 	$(OBJCOPY) -I binary -B $(OUTPUT_ARCH) -O $(OUTPUT_FORMAT) 		\
 	--rename-section .data=irq_int_vector_map irq_int_vector_map.bin 	\
 		irq_int_vector_map.o &&						\
-	rm staticIdt.bin irq_int_vector_map.bin int_vector_alloc.bin isrList.bin\
+	rm staticIdt.bin irq_int_vector_map.bin isrList.bin			\
 )
 
-staticIdt.o: $(TMP_ELF)
+staticIdt.o: $(PREBUILT_KERNEL)
 	$(call cmd,gen_idt)
 
 quiet_cmd_lnk_elf = LINK    $@
       cmd_lnk_elf =									\
 (											\
-	$(CC) -T final-linker.cmd @$(KERNEL_NAME).lnk staticIdt.o int_vector_alloc.o 	\
-	irq_int_vector_map.o -o $@;							\
+	$(CC) -T linker.cmd @$(KERNEL_NAME).lnk staticIdt.o				\
+		irq_int_vector_map.o -o $@;						\
 	${OBJCOPY} --change-section-address intList=${CONFIG_PHYS_LOAD_ADDR} $@ elf.tmp;\
 	$(OBJCOPY) -R intList elf.tmp $@;						\
 	rm elf.tmp									\
@@ -822,14 +887,25 @@ ASSERT_WARNING_STR := \
 
 WARN_ABOUT_ASSERT := $(if $(CONFIG_ASSERT),echo -e -n $(ASSERT_WARNING_STR),true)
 
+
+DEPRECATION_WARNING_STR := \
+    "\n      WARNING:  The board '$(BOARD)' is deprecated and will be" \
+    "\n      removed in version $(CONFIG_BOARD_DEPRECATED)\n\n"
+
+WARN_ABOUT_DEPRECATION := $(if $(CONFIG_BOARD_DEPRECATED),echo -e \
+				-n $(DEPRECATION_WARNING_STR),true)
+
 ifeq ($(ARCH),x86)
-$(KERNEL_ELF_NAME): staticIdt.o final-linker.cmd
+$(KERNEL_ELF_NAME): staticIdt.o linker.cmd
 	$(call cmd,lnk_elf)
+	@$(srctree)/scripts/check_link_map.py $(KERNEL_NAME).map
 	@$(WARN_ABOUT_ASSERT)
+	@$(WARN_ABOUT_DEPRECATION)
 else
-$(KERNEL_ELF_NAME): $(TMP_ELF)
-	@cp $(TMP_ELF) $(KERNEL_ELF_NAME)
+$(KERNEL_ELF_NAME): $(PREBUILT_KERNEL)
+	@cp $(PREBUILT_KERNEL) $(KERNEL_ELF_NAME)
 	@$(WARN_ABOUT_ASSERT)
+	@$(WARN_ABOUT_DEPRECATION)
 endif
 
 
@@ -844,6 +920,15 @@ quiet_cmd_gen_bin = BIN     $@
 $(KERNEL_BIN_NAME): $(KERNEL_ELF_NAME)
 	$(call cmd,gen_bin)
 
+quiet_cmd_gen_hex = HEX     $@
+      cmd_gen_hex =                                                         \
+(                                                                           \
+   $(OBJCOPY) -S -O ihex -R .note -R .comment -R COMMON -R .eh_frame $< $@; \
+)
+
+$(KERNEL_HEX_NAME): $(KERNEL_ELF_NAME)
+	$(call cmd,gen_hex)
+
 $(KERNEL_STAT_NAME): $(KERNEL_BIN_NAME) $(KERNEL_ELF_NAME)
 	@$(READELF) -e $(KERNEL_ELF_NAME) > $@
 
@@ -856,7 +941,7 @@ zephyr: $(zephyr-deps) $(KERNEL_BIN_NAME)
 
 # The actual objects are generated when descending,
 # make sure no implicit rule kicks in
-$(sort $(zephyr-deps)): $(zephyr-dirs) ;
+$(sort $(zephyr-deps)): $(zephyr-dirs) zephyr-app-dir ;
 
 # Handle descending into subdirectories listed in $(zephyr-dirs)
 # Preset locale variables to speed up the build process. Limit locale
@@ -868,6 +953,11 @@ PHONY += $(zephyr-dirs)
 $(zephyr-dirs): prepare scripts
 	$(Q)$(MAKE) $(build)=$@
 
+PHONY += zephyr-app-dir
+zephyr-app-dir: prepare scripts
+	$(Q)$(MAKE) $(build)=$(notdir $(zephyr-app-dir-root-name)) \
+		srctree=$(zephyr-app-dir-root)
+
 # Things we need to do before we recursively start building the kernel
 # or the modules are listed in "prepare".
 # A multi level approach is used. prepareN is processed before prepareN-1.
@@ -966,9 +1056,11 @@ CLEAN_DIRS  += $(MODVERDIR)
 CLEAN_FILES += 	misc/generated/sysgen/kernel_main.c \
 		misc/generated/sysgen/sysgen.h \
 		misc/generated/sysgen/prj.mdef \
+		misc/generated/sysgen/micro_private_types.h \
+		misc/generated/sysgen/kernel_main.h \
 		.old_version .tmp_System.map .tmp_version \
 		.tmp_* System.map *.lnk *.map *.elf *.lst \
-		*.bin *.strip staticIdt.o linker.cmd final-linker.cmd
+		*.bin *.hex *.stat *.strip staticIdt.o linker.cmd
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config usr/include include/generated          \
@@ -985,9 +1077,9 @@ clean: rm-dirs  := $(CLEAN_DIRS)
 clean: rm-files := $(CLEAN_FILES)
 clean-dirs      := $(addprefix _clean_, . $(zephyr-alldirs) )
 
-PHONY += $(clean-dirs) clean archclean zephyrclean
-$(clean-dirs):
-	$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@)
+PHONY += clean-dirs-target clean archclean zephyrclean
+clean-dirs-target:
+	$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$(clean-dirs))
 
 clean: archclean
 
@@ -1019,7 +1111,7 @@ distclean: mrproper
 # Brief documentation of the typical targets used
 # ---------------------------------------------------------------------------
 
-boards := $(wildcard $(srctree)/boards/*/*_defconfig)
+boards := $(wildcard $(srctree)/boards/*/*/*_defconfig)
 boards := $(sort $(notdir $(boards)))
 
 kconfig-help:
@@ -1043,8 +1135,11 @@ help:
 	@echo  '  all		  - Build all targets marked with [*]'
 	@echo  '* zephyr	  - Build a zephyr application'
 	@echo  '  qemu		  - Build a zephyr application and run it in qemu'
+	@echo  '  qemugdb         - Same as 'qemu' but start a GDB server on port 1234'
 	@echo  '  flash		  - Build and flash an application'
 	@echo  '  debug		  - Build and debug an application using GDB'
+	@echo  '  ram_report	  - Build and create RAM usage report'
+	@echo  '  rom_report	  - Build and create ROM usage report'
 	@echo  ''
 	@echo  'Supported Boards:'
 	@echo  ''
@@ -1084,7 +1179,7 @@ help-board-dirs := $(addprefix help-,$(board-dirs))
 
 help-boards: $(help-board-dirs)
 
-boards-per-dir = $(sort $(notdir $(wildcard $(srctree)/boards/$*/*_defconfig)))
+boards-per-dir = $(sort $(notdir $(wildcard $(srctree)/boards/*/$*/*_defconfig)))
 
 $(help-board-dirs): help-%:
 	@echo  'Architecture specific targets ($(ARCH) $*):'
@@ -1099,7 +1194,7 @@ $(help-board-dirs): help-%:
 %docs: FORCE
 	$(Q)$(MAKE) -C doc htmldocs
 
-clean: $(clean-dirs)
+clean: clean-dirs-target
 	$(call cmd,rmdirs)
 	$(call cmd,rmfiles)
 	@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
@@ -1161,7 +1256,10 @@ qemu: zephyr
 	$(if $(CONFIG_X86_IAMCU),python $(ZEPHYR_BASE)/scripts/qemu-machine-hack.py $(KERNEL_ELF_NAME))
 	$(Q)$(QEMU) $(QEMU_FLAGS) $(QEMU_EXTRA_FLAGS) -kernel $(KERNEL_ELF_NAME)
 
--include $(srctree)/boards/$(BOARD_NAME)/Makefile.board
+qemugdb: QEMU_EXTRA_FLAGS += -s -S
+qemugdb: qemu
+
+-include $(srctree)/boards/$(ARCH)/$(BOARD_NAME)/Makefile.board
 ifneq ($(FLASH_SCRIPT),)
 flash: zephyr
 	@echo "Flashing $(BOARD_NAME)"

Makefile.inc

@@ -1,19 +1,37 @@
 # vim: filetype=make
 #
 
-DQUOTE = "
-# "
-
-ARCH ?= x86
-
 UNAME := $(shell uname)
 ifeq (MINGW, $(findstring MINGW, $(UNAME)))
+DQUOTE = '
+# '
 PROJECT_BASE ?= $(shell sh -c "pwd -W")
 else
+DQUOTE = "
+# "
 PROJECT_BASE ?= $(CURDIR)
 endif
 
-O ?= $(PROJECT_BASE)/outdir
+ifdef BOARD
+KBUILD_DEFCONFIG_PATH=$(wildcard $(ZEPHYR_BASE)/boards/*/*/$(BOARD)_defconfig)
+ifeq ($(KBUILD_DEFCONFIG_PATH),)
+$(error Board $(BOARD) not found!)
+endif
+else
+$(error BOARD is not defined!)
+endif
+
+# Choose a default output directory if one wasn't supplied.  Note that
+# PRISTINE_O depends on whether this is default or not.  If building
+# in-tree, we want to remove the whole outdir and not just the BOARD
+# specified (thus "pristine").  Out of tree, we can obviously remove
+# only what we were told to build.
+ifndef O
+PRISTINE_O = outdir
+O = $(PROJECT_BASE)/outdir/$(BOARD)
+else
+PRISTINE_O = $(O)
+endif
 
 # Turn O into an absolute path; we call the main Kbuild with $(MAKE) -C
 # which changes the working directory, relative paths don't work right.
@@ -26,24 +44,15 @@ endif
 
 export ARCH MDEF_FILE QEMU_EXTRA_FLAGS PROJECT_BASE
 
-KERNEL_TYPE ?= micro
 override CONF_FILE := $(strip $(subst $(DQUOTE),,$(CONF_FILE)))
 
-ifdef BOARD
-KBUILD_DEFCONFIG_PATH=$(wildcard $(ZEPHYR_BASE)/boards/*/$(BOARD)_defconfig)
-ifeq ($(KBUILD_DEFCONFIG_PATH),)
-$(error Board $(BOARD) not found!)
-endif
-else
-$(error BOARD is not defined!)
-endif
-
 SOURCE_DIR ?= $(PROJECT_BASE)/src/
-override SOURCE_DIR := $(abspath $(SOURCE_DIR))
-# Kbuild doesn't work correctly if SOURCE_DIR is an absolute path
-override SOURCE_DIR := $(subst $(ZEPHYR_BASE),.,$(SOURCE_DIR))/
+override SOURCE_DIR := $(realpath $(SOURCE_DIR))
 override SOURCE_DIR := $(subst \,/,$(SOURCE_DIR))
-export SOURCE_DIR
+override SOURCE_DIR_PARENT := $(patsubst %, %/.., $(SOURCE_DIR))
+override SOURCE_DIR_PARENT := $(abspath $(SOURCE_DIR_PARENT))
+override SOURCE_DIR_PARENT := $(subst \,/,$(SOURCE_DIR_PARENT))
+export SOURCE_DIR SOURCE_DIR_PARENT
 
 ifeq ("$(origin V)", "command line")
   KBUILD_VERBOSE = $(V)
@@ -62,8 +71,8 @@ endif
 
 export CFLAGS
 
-zephyrmake	= @+$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) \
-			PROJECT=$(PROJECT_BASE) SOURCE_DIR=$(SOURCE_DIR) $(2)
+zephyrmake	= +$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) \
+			PROJECT=$(PROJECT_BASE) SOURCE_DIR=$(DQUOTE)$(SOURCE_DIR)$(DQUOTE) $(2)
 
 BOARDCONFIG = $(O)/.board_$(BOARD)
 
@@ -75,9 +84,12 @@ all: $(DOTCONFIG)
 ifeq ($(findstring qemu_,$(BOARD)),)
 qemu:
 	@echo "Emulation not available for this platform"
+qemugdb: qemu
 else
 qemu: $(DOTCONFIG)
 	$(Q)$(call zephyrmake,$(O),$@)
+qemugdb: $(DOTCONFIG)
+	$(Q)$(call zephyrmake,$(O),$@)
 endif
 
 debug:	$(DOTCONFIG)
@@ -87,7 +99,8 @@ flash: $(DOTCONFIG)
 	$(Q)$(call zephyrmake,$(O),$@)
 
 ifeq ($(MAKECMDGOALS),debugserver)
--include $(ZEPHYR_BASE)/boards/$(BOARD)/Makefile.board
+ARCH = $(notdir $(subst /$(BOARD),,$(wildcard $(ZEPHYR_BASE)/boards/*/$(BOARD))))
+-include $(ZEPHYR_BASE)/boards/$(ARCH)/$(BOARD)/Makefile.board
 -include $(ZEPHYR_BASE)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
 BOARD_NAME = $(BOARD)
 export BOARD_NAME
@@ -96,7 +109,7 @@ debugserver: FORCE
 	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/support/$(FLASH_SCRIPT) debugserver
 
 
-initconfig: $(DOTCONFIG)
+initconfig outputexports: $(DOTCONFIG)
 
 $(BOARDCONFIG):
 	@rm -f $(O)/.board_*
@@ -119,15 +132,16 @@ help:
 %:
 	$(Q)$(call zephyrmake,$(O),$@)
 
-KERNEL_CONFIG = $(ZEPHYR_BASE)/kernel/configs/$(KERNEL_TYPE).config
+KERNEL_CONFIG = $(ZEPHYR_BASE)/kernel/configs/unified.config
 
 $(DOTCONFIG): $(BOARDCONFIG) $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
 	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/kconfig/merge_config.sh \
-		-q -m -O $(O) $(KBUILD_DEFCONFIG_PATH) $(KERNEL_CONFIG) $(CONF_FILE)
+		-q -m -O $(O) $(KBUILD_DEFCONFIG_PATH) $(KERNEL_CONFIG) $(CONF_FILE) \
+			      $(wildcard $(O)/*.conf)
 	$(Q)$(MAKE) $(S) -C $(ZEPHYR_BASE) O=$(O) PROJECT=$(PROJECT_BASE) oldnoconfig
 
 pristine:
-	$(Q)rm -rf $(O)
+	$(Q)rm -rf $(PRISTINE_O)
 
 PHONY += FORCE initconfig
 FORCE:

arch/Kconfig

@@ -31,9 +31,11 @@ config ARM
 config X86
 	bool "x86 architecture"
 	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
+	select ATOMIC_OPERATIONS_BUILTIN
 
 config NIOS2
 	bool "Nios II Gen 2 architecture"
+	select ATOMIC_OPERATIONS_C
 
 endchoice
 
@@ -56,6 +58,15 @@ config SYS_POWER_DEEP_SLEEP_SUPPORTED
 	help
 	This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
 	configuration option.
+
+config BOOTLOADER_CONTEXT_RESTORE_SUPPORTED
+	# Hidden
+	bool
+	default n
+	help
+	This option signifies that the target has options of bootloaders
+	that support context restore upon resume from deep sleep
+
 #
 # End hidden PM feature configs
 #

arch/arc/Kconfig

@@ -84,22 +84,6 @@ config	NUM_IRQ_PRIO_LEVELS
 
 	  The BSP must provide a valid default for proper operation.
 
-config	NUM_REGULAR_IRQ_PRIO_LEVELS
-	int
-	prompt "Number of supported regular interrupt priority levels"
-	range 1 16
-	help
-	 This represents the number of Regular Interrupt priorities, which
-	 does NOT include the Fast (FIRQ) priority.
-	 The Regular Interrupt priorities available will be
-
-	  (NUM_IRQ_PRIO_LEVELS - NUM_REGULAR_IRQ_PRIO_LEVELS) to
-	  (NUM_REGULAR_IRQ_PRIO_LEVELS - 1).
-
-	  The maximum value is NUM_IRQ_PRIO_LEVELS.
-
-	  The BSP must provide a valid default for proper operation.
-
 config	NUM_IRQS
 	int
 	prompt "Upper limit of interrupt numbers/IDs used"
@@ -112,6 +96,20 @@ config	NUM_IRQS
 	  The BSP must provide a valid default. This drives the size of the
 	  vector table.
 
+config	RGF_NUM_BANKS
+	int
+	prompt "Number of General Purpose Register Banks"
+	depends on CPU_ARCV2
+	range 1 2
+	default 2
+	help
+	The ARC CPU can be configured to have more than one register
+	bank. If fast interrupts are supported (FIRQ), the 2nd
+	register bank, in the set, will be used by FIRQ interrupts.
+	If fast interrupts are supported but there is only 1
+	register bank, the fast interrupt handler must save
+	and restore general purpose regsiters.
+
 config	FIRQ_STACK_SIZE
 	int
 	prompt "Size of stack for FIRQs (in bytes)"
@@ -135,13 +133,15 @@ config	FAULT_DUMP
 	default 2
 	range 0 2
 	help
-	  Different levels for display information when a fault occurs.
+	Different levels for display information when a fault occurs.
 
-	  2: The default. Display specific and verbose information. Consumes
-	     the most memory (long strings).
-	  1: Display general and short information. Consumes less memory
-	     (short strings).
-	  0: Off.
+	2: The default. Display specific and verbose information. Consumes
+		the most memory (long strings).
+
+	1: Display general and short information. Consumes less memory
+		(short strings).
+
+	0: Off.
 
 config IRQ_OFFLOAD
 	bool "Enable IRQ offload"
@@ -167,56 +167,56 @@ config ICCM_SIZE
 	int "ICCM Size in kB"
 	help
 	This option specifies the size of the ICCM in kB.  It is normally set by
-	the platform's defconfig file and the user should generally avoid modifying
+	the board's defconfig file and the user should generally avoid modifying
 	it via the menu configuration.
 
 config ICCM_BASE_ADDRESS
 	hex "ICCM Base Address"
 	help
-	This option specifies the base address of the ICCM on the platform.  It is
-	normally set by the platform's defconfig file and the user should generally
+	This option specifies the base address of the ICCM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
 	avoid modifying it via the menu configuration.
 
 config DCCM_SIZE
 	int "DCCM Size in kB"
 	help
 	This option specifies the size of the DCCM in kB.  It is normally set by
-	the platform's defconfig file and the user should generally avoid modifying
+	the board's defconfig file and the user should generally avoid modifying
 	it via the menu configuration.
 
 config DCCM_BASE_ADDRESS
 	hex "DCCM Base Address"
 	help
-	This option specifies the base address of the DCCM on the platform.  It is
-	normally set by the platform's defconfig file and the user should generally
+	This option specifies the base address of the DCCM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
 	avoid modifying it via the menu configuration.
 
 config SRAM_SIZE
 	int "SRAM Size in kB"
 	help
 	This option specifies the size of the SRAM in kB.  It is normally set by
-	the platform's defconfig file and the user should generally avoid modifying
+	the board's defconfig file and the user should generally avoid modifying
 	it via the menu configuration.
 
 config SRAM_BASE_ADDRESS
 	hex "SRAM Base Address"
 	help
-	This option specifies the base address of the SRAM on the platform.  It is
-	normally set by the platform's defconfig file and the user should generally
+	This option specifies the base address of the SRAM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
 	avoid modifying it via the menu configuration.
 
 config FLASH_SIZE
 	int "Flash Size in kB"
 	help
 	This option specifies the size of the flash in kB.  It is normally set by
-	the platform's defconfig file and the user should generally avoid modifying
+	the board's defconfig file and the user should generally avoid modifying
 	it via the menu configuration.
 
 config FLASH_BASE_ADDRESS
 	hex "Flash Base Address"
 	help
-	This option specifies the base address of the flash on the platform.  It is
-	normally set by the platform's defconfig file and the user should generally
+	This option specifies the base address of the flash on the board.  It is
+	normally set by the board's defconfig file and the user should generally
 	avoid modifying it via the menu configuration.
 
 config SW_ISR_TABLE
@@ -229,19 +229,6 @@ config SW_ISR_TABLE
 	  a parameter to be passed to the interrupt handlers. Also, invoking
 	  the exeception/interrupt exit stub is automatically done.
 
-	  This has to be enabled for dynamically connecting interrupt handlers
-	  at runtime (SW_ISR_TABLE_DYNAMIC).
-
-config SW_ISR_TABLE_DYNAMIC
-	bool
-	prompt "Allow installing interrupt handlers at runtime"
-	depends on SW_ISR_TABLE
-	default n
-	help
-	  This option enables irq_connect_dynamic(). It moves the ISR table to
-	  SRAM so that it is writable. This has the side-effect of removing
-	  write-protection on the ISR table.
-
 config IRQ_VECTOR_TABLE_CUSTOM
 	bool
 	prompt "Projects provide a custom static IRQ part of vector table"
@@ -282,8 +269,42 @@ config ARCH_HAS_NANO_FIBER_ABORT
 	# omit prompt to signify a "hidden" option
 	default n
 
-endmenu
+config CACHE_LINE_SIZE_DETECT
+	bool
+	prompt "Detect d-cache line size at runtime"
+	default n
+	help
+	This option enables querying the d-cache build register for finding
+	the d-cache line size at the expense of taking more memory and code
+	and a slightly increased boot time.
 
+	If the CPU's d-cache line size is known in advance, disable this
+	option and manually enter the value for CACHE_LINE_SIZE.
+
+config CACHE_LINE_SIZE
+	int
+	prompt "Cache line size" if !CACHE_LINE_SIZE_DETECT
+	default 32
+	help
+	Size in bytes of a CPU d-cache line.
+
+	Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
+
+config ARCH_CACHE_FLUSH_DETECT
+	bool
+	default n
+
+config CACHE_FLUSHING
+	bool
+	default n
+	prompt "Enable d-cache flushing mechanism"
+	help
+	This links in the sys_cache_flush() function, which provides a
+	way to flush multiple lines of the d-cache.
+	If the d-cache is present, set this to y.
+	If the d-cache is NOT present, set this to n.
+
+endmenu
 
 source "arch/arc/soc/*/Kconfig"
 

arch/arc/core/Makefile

@@ -1,10 +1,9 @@
-ccflags-y += -I$(srctree)/kernel/nanokernel/include
+ccflags-y += -I$(srctree)/kernel/unified/include
 ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
-ccflags-y += -I$(srctree)/kernel/microkernel/include
 
 obj-y += thread.o thread_entry_wrapper.o \
 	cpu_idle.o  fast_irq.o  fatal.o  fault.o  \
-	fault_s.o  irq_manage.o  \
+	fault_s.o  irq_manage.o cache.o  \
 	isr_wrapper.o  regular_irq.o  swap_macros.h  swap.o \
 	sys_fatal_error_handler.o
 
@@ -14,9 +13,8 @@ obj-y += prep_c.o \
 
 obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
 
-ifneq ($(CONFIG_ATOMIC_OPERATIONS_C),y)
-obj-y += atomic.o
-endif
-
+# Some ARC cores like the EM4 lack the atomic LLOCK/SCOND and
+# can't use these.
+obj-$(CONFIG_ATOMIC_OPERATIONS_CUSTOM) += atomic.o
 obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
 obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o

arch/arc/core/cache.c

@@ -0,0 +1,184 @@
+/* cache.c - d-cache support for ARC CPUs */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief d-cache manipulation
+ *
+ * This module contains functions for manipulation of the d-cache.
+ */
+
+#include <nanokernel.h>
+#include <arch/cpu.h>
+#include <misc/util.h>
+#include <toolchain.h>
+#include <cache.h>
+#include <linker-defs.h>
+#include <arch/arc/v2/aux_regs.h>
+#include <nano_internal.h>
+#include <misc/__assert.h>
+#include <init.h>
+
+#if defined(CONFIG_CACHE_FLUSHING)
+
+#if (CONFIG_CACHE_LINE_SIZE == 0) && !defined(CONFIG_CACHE_LINE_SIZE_DETECT)
+#error Cannot use this implementation with a cache line size of 0
+#endif
+
+#if defined(CONFIG_CACHE_LINE_SIZE_DETECT)
+#define DCACHE_LINE_SIZE sys_cache_line_size
+#else
+#define DCACHE_LINE_SIZE CONFIG_CACHE_LINE_SIZE
+#endif
+
+#define DC_CTRL_DC_ENABLE            0x0  /* enable d-cache */
+#define DC_CTRL_DC_DISABLE           0x1  /* disable d-cache */
+#define DC_CTRL_INVALID_ONLY         0x0  /* invalid d-cache only */
+#define DC_CTRL_INVALID_FLUSH        0x40 /* invalid and flush d-cache */
+#define DC_CTRL_ENABLE_FLUSH_LOCKED  0x80 /* locked d-cache can be flushed */
+#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0  /* locked d-cache cannot be flushed */
+#define DC_CTRL_FLUSH_STATUS         0x100/* flush status */
+#define DC_CTRL_DIRECT_ACCESS        0x0  /* direct access mode  */
+#define DC_CTRL_INDIRECT_ACCESS      0x20 /* indirect access mode */
+#define DC_CTRL_OP_SUCCEEDED         0x4  /* d-cache operation succeeded */
+
+
+static int dcache_available(void)
+{
+	unsigned long val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+
+	val &= 0xff; /* extract version */
+	return (val == 0)?0:1;
+}
+
+static void dcache_dc_ctrl(uint32_t dcache_en_mask)
+{
+	if (!dcache_available())
+		return;
+	_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, dcache_en_mask);
+}
+
+static void dcache_enable(void)
+{
+	dcache_dc_ctrl(DC_CTRL_DC_ENABLE);
+}
+
+
+/**
+ *
+ * @brief Flush multiple d-cache lines to memory
+ *
+ * No alignment is required for either <start_addr> or <size>, but since
+ * dcache_flush_mlines() iterates on the d-cache lines, a cache line
+ * alignment for both is optimal.
+ *
+ * The d-cache line size is specified either via the CONFIG_CACHE_LINE_SIZE
+ * kconfig option or it is detected at runtime.
+ *
+ * @param start_addr the pointer to start the multi-line flush
+ * @param size the number of bytes that are to be flushed
+ *
+ * @return N/A
+ */
+static void dcache_flush_mlines(uint32_t start_addr, uint32_t size)
+{
+	uint32_t end_addr;
+	unsigned int key;
+
+	if (!dcache_available() || (size == 0)) {
+		return;
+	}
+
+	end_addr = start_addr + size - 1;
+	start_addr &= (uint32_t)(~(DCACHE_LINE_SIZE - 1));
+
+	key = irq_lock(); /* --enter critical section-- */
+
+	do {
+		_arc_v2_aux_reg_write(_ARC_V2_DC_FLDL, start_addr);
+		__asm__ volatile("nop_s");
+		__asm__ volatile("nop_s");
+		__asm__ volatile("nop_s");
+		/* wait for flush completion */
+		do {
+			if ((_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) &
+				DC_CTRL_FLUSH_STATUS) == 0)
+				break;
+		} while (1);
+		start_addr += DCACHE_LINE_SIZE;
+	} while (start_addr <= end_addr);
+
+	irq_unlock(key); /* --exit critical section-- */
+
+}
+
+
+/**
+ *
+ * @brief Flush d-cache lines to main memory
+ *
+ * No alignment is required for either <virt> or <size>, but since
+ * sys_cache_flush() iterates on the d-cache lines, a d-cache line alignment for
+ * both is optimal.
+ *
+ * The d-cache line size is specified either via the CONFIG_CACHE_LINE_SIZE
+ * kconfig option or it is detected at runtime.
+ *
+ * @param start_addr the pointer to start the multi-line flush
+ * @param size the number of bytes that are to be flushed
+ *
+ * @return N/A
+ */
+
+void sys_cache_flush(vaddr_t start_addr, size_t size)
+{
+	dcache_flush_mlines((uint32_t)start_addr, (uint32_t)size);
+}
+
+
+#if defined(CONFIG_CACHE_LINE_SIZE_DETECT)
+size_t sys_cache_line_size;
+static void init_dcache_line_size(void)
+{
+	uint32_t val;
+
+	val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+	__ASSERT((val&0xff) != 0, "d-cache is not present");
+	val = ((val>>16) & 0xf) + 1;
+	val *= 16;
+	sys_cache_line_size = (size_t) val;
+}
+#endif
+
+static int init_dcache(struct device *unused)
+{
+	ARG_UNUSED(unused);
+
+	dcache_enable();
+
+#if defined(CONFIG_CACHE_LINE_SIZE_DETECT)
+	init_dcache_line_size();
+#endif
+
+	return 0;
+}
+
+SYS_INIT(init_dcache, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_CACHE_FLUSHING */
+

arch/arc/core/cpu_idle.S

@@ -23,8 +23,8 @@
 
 #define _ASMLANGUAGE
 
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <sections.h>
 #include <arch/cpu.h>
@@ -33,24 +33,9 @@ GTEXT(nano_cpu_idle)
 GTEXT(nano_cpu_atomic_idle)
 GDATA(nano_cpu_sleep_mode)
 
-#if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
-	GTEXT(_power_save_idle)
-#endif
-
 SECTION_VAR(BSS, nano_cpu_sleep_mode)
 	.word 0
 
-#if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
-.macro enter_tickless_idle
-	/* interrupts are locked when entering here */
-	push_s blink
-	jl _power_save_idle
-	pop_s blink
-.endm
-#else
-	#define enter_tickless_idle
-#endif
-
 /*
  * @brief Put the CPU in low-power mode
  *
@@ -66,7 +51,6 @@ SECTION_FUNC(TEXT, nano_cpu_idle)
 	jl    _sys_k_event_logger_enter_sleep
 	pop_s blink
 #endif
-	enter_tickless_idle
 
 	ld r1, [nano_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
@@ -89,8 +73,6 @@ SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
 	pop_s blink
 #endif
 
-	enter_tickless_idle
-
 	ld r1, [nano_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1

arch/arc/core/fast_irq.S

@@ -25,8 +25,8 @@
 
 #define _ASMLANGUAGE
 
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
 #include "swap_macros.h"
@@ -34,10 +34,24 @@
 GTEXT(_firq_enter)
 GTEXT(_firq_exit)
 GTEXT(_firq_stack_setup)
+
+#if CONFIG_RGF_NUM_BANKS != 1
 GDATA(_firq_stack)
+GTEXT(_is_next_thread_current)
 
 SECTION_VAR(NOINIT, _firq_stack)
 	.space CONFIG_FIRQ_STACK_SIZE
+#else
+GDATA(saved_r0)
+#endif
+
+.macro _firq_return
+#if CONFIG_RGF_NUM_BANKS == 1
+	b _firq_no_reschedule
+#else
+	rtie
+#endif
+.endm
 
 /**
  *
@@ -63,10 +77,13 @@ SECTION_VAR(NOINIT, _firq_stack)
 
 SECTION_FUNC(TEXT, _firq_enter)
 
-	/*
-	 * ATTENTION:
-	 * firq uses a 2nd register bank so GPRs do not need to be saved.
-	 */
+/*
+ * ATTENTION:
+ * If CONFIG_RGF_NUM_BANKS>1, firq uses a 2nd register bank so GPRs do
+ * not need to be saved.
+ * If CONFIG_RGF_NUM_BANKS==1, firq must use the stack to save registers.
+ * This has already been done by _isr_enter.
+ */
 
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* disable stack checking */
@@ -75,6 +92,7 @@ SECTION_FUNC(TEXT, _firq_enter)
 	kflag r2
 #endif
 
+#if CONFIG_RGF_NUM_BANKS != 1
 #ifndef CONFIG_FIRQ_NO_LPCC
 	/*
 	 * Save LP_START/LP_COUNT/LP_END because called handler might use.
@@ -84,6 +102,7 @@ SECTION_FUNC(TEXT, _firq_enter)
 	mov r23,lp_count
 	lr r24, [_ARC_V2_LP_START]
 	lr r25, [_ARC_V2_LP_END]
+#endif
 #endif
 
 	j @_isr_demux
@@ -97,15 +116,17 @@ SECTION_FUNC(TEXT, _firq_enter)
 
 SECTION_FUNC(TEXT, _firq_exit)
 
+#if CONFIG_RGF_NUM_BANKS != 1
 #ifndef CONFIG_FIRQ_NO_LPCC
 	/* restore lp_count, lp_start, lp_end from r23-r25 */
 	mov lp_count,r23
 	sr r24, [_ARC_V2_LP_START]
 	sr r25, [_ARC_V2_LP_END]
+#endif
 #endif
 
-	mov_s r1, _nanokernel
-	ld_s r2, [r1, __tNANO_current_OFFSET]
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
 
 #if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
 	/* check if we're a nested interrupt: if so, let the interrupted
@@ -118,29 +139,80 @@ SECTION_FUNC(TEXT, _firq_exit)
 	 * means that another bit is set so an interrupt was interrupted.
 	 */
 
-	breq r3, 1, _check_if_current_is_the_task
-
-	rtie
+	breq r3, 1, _firq_check_for_swap
 
+	_firq_return
 #endif
 
 .balign 4
-_check_if_current_is_the_task:
+_firq_check_for_swap:
+	/* coop thread ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_prio]
+	brlt r0, 0, _firq_no_reschedule
 
-	ld_s r0, [r2, __tTCS_flags_OFFSET]
-	and.f r0, r0, PREEMPTIBLE
-	bnz _check_if_a_fiber_is_ready
-	rtie
+	/* scheduler locked ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_sched_locked]
+	brgt r0, 0, _firq_no_reschedule
+
+	/* check if the current thread needs to be rescheduled */
+	push_s r2
+	push_s r1
+	push_s blink
+	jl _is_next_thread_current
+	pop_s blink
+	pop_s r1
+	pop_s r2
+#if CONFIG_RGF_NUM_BANKS != 1
+#ifndef CONFIG_FIRQ_NO_LPCC
+	/*
+	 * restore lp_count, lp_start, lp_end from r23-r25 in case
+	 * _is_next_thread_current() routine used them
+	 */
+	mov lp_count,r23
+	sr r24, [_ARC_V2_LP_START]
+	sr r25, [_ARC_V2_LP_END]
+#endif
+#endif
+	breq r0, 0, _firq_reschedule
+	/* fall to no rescheduling */
 
 .balign 4
-_check_if_a_fiber_is_ready:
-	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
-	brne r0, 0, _firq_reschedule
+_firq_no_reschedule:
+	/*
+	 * Keeping this code block close to those that use it allows using brxx
+	 * instruction instead of a pair of cmp and bxx
+	 */
+#if CONFIG_RGF_NUM_BANKS == 1
+	add sp,sp,4 /* don't need r0 from stack */
+	pop_s r1
+	pop_s r2
+	pop_s r3
+	pop r4
+	pop r5
+	pop r6
+	pop r7
+	pop r8
+	pop r9
+	pop r10
+	pop r11
+	pop_s r12
+	pop_s r13
+	pop_s blink
+	pop_s r0
+	sr r0, [_ARC_V2_LP_END]
+	pop_s r0
+	sr r0, [_ARC_V2_LP_START]
+	pop_s r0
+	mov lp_count,r0
+	ld r0,[saved_r0]
+	add sp,sp,8 /* don't need ilink & status32_po from stack */
+#endif
 	rtie
 
 .balign 4
 _firq_reschedule:
 
+#if CONFIG_RGF_NUM_BANKS != 1
 	/*
 	 * We know there is no interrupted interrupt of lower priority at this
 	 * point, so when switching back to register bank 0, it will contain the
@@ -161,28 +233,37 @@ _firq_reschedule:
 	 */
 
 	lr r0, [_ARC_V2_STATUS32_P0]
-	st_s r0, [sp, __tISF_status32_OFFSET]
+	st_s r0, [sp, ___isf_t_status32_OFFSET]
 
-	st ilink, [sp, __tISF_pc_OFFSET] /* ilink into pc */
+	st ilink, [sp, ___isf_t_pc_OFFSET] /* ilink into pc */
+#endif
 
-	mov_s r1, _nanokernel
-	ld_s r2, [r1, __tNANO_current_OFFSET]
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
 
 	_save_callee_saved_regs
 
-	st _CAUSE_FIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
+	st _CAUSE_FIRQ, [r2, _thread_offset_to_relinquish_cause]
 
-	ld_s r2, [r1, __tNANO_fiber_OFFSET]
-
-	st_s r2, [r1, __tNANO_current_OFFSET]
-	ld_s r3, [r2, __tTCS_link_OFFSET]
-	st_s r3, [r1, __tNANO_fiber_OFFSET]
+	/*
+	 * Save needed registers to callee saved ones. It is faster than
+	 * pushing them to stack. It is possible to do since program has
+	 * just saved them and the calling routine will save them in turn
+	 * if it uses them.
+	 */
+	mov_s r13, blink
+	mov_s r14, r1
+	jl _get_next_ready_thread
+	mov_s blink, r13
+	mov_s r1, r14
+	mov_s r2, r0
+	st_s r2, [r1, _kernel_offset_to_current]
 
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
-	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_stack_top]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/*
@@ -191,7 +272,7 @@ _firq_reschedule:
 	 */
 	_load_callee_saved_regs
 
-	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
 
 	breq r3, _CAUSE_RIRQ, _firq_return_from_rirq
 	nop
@@ -203,8 +284,8 @@ _firq_reschedule:
 .balign 4
 _firq_return_from_coop:
 
-	ld_s r3, [r2, __tTCS_intlock_key_OFFSET]
-	st  0, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_intlock_key]
+	st  0, [r2, _thread_offset_to_intlock_key]
 
 	/* pc into ilink */
 	pop_s r0
@@ -222,7 +303,7 @@ _firq_return_from_coop:
 	or.nz r0, r0, _ARC_V2_STATUS32_IE
 	sr r0, [_ARC_V2_STATUS32_P0]
 
-	ld_s r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, _thread_offset_to_return_value]
 	rtie
 
 .balign 4
@@ -235,23 +316,20 @@ _firq_return_from_firq:
 	sr ilink, [_ARC_V2_STATUS32_P0]
 	ld ilink, [sp, -8] /* pc into ilink */
 
-	/* fall through to rtie instruction */
-
-.balign 4
-_firq_no_reschedule:
-
 	/* LP registers are already restored, just switch back to bank 0 */
 	rtie
 
+
 /**
  *
- * @brief Install the FIRQ stack in register bank 1
+ * @brief Install the FIRQ stack in register bank 1 if CONFIG_RGF_NUM_BANK!=1
  *
  * @return N/A
  */
 
 SECTION_FUNC(TEXT, _firq_stack_setup)
 
+#if CONFIG_RGF_NUM_BANKS != 1
 	lr r0, [_ARC_V2_STATUS32]
 	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
 	or r0, r0, _ARC_V2_STATUS32_RB(1)
@@ -267,5 +345,6 @@ SECTION_FUNC(TEXT, _firq_stack_setup)
 	lr r0, [_ARC_V2_STATUS32]
 	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
 	kflag r0
+#endif
 
 	j_s [blink]

arch/arc/core/fatal.c

@@ -22,8 +22,8 @@
  * ARCv2 CPUs.
  */
 
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
 
@@ -75,9 +75,9 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 		PR_EXC("**** Unknown Fatal Error %d! ****\n", reason);
 		break;
 	}
-	PR_EXC("Current thread ID = 0x%x\n"
-	       "Faulting instruction address = 0x%x\n",
-	       sys_thread_self_get(),
+	PR_EXC("Current thread ID = %p\n"
+	       "Faulting instruction address = 0x%lx\n",
+	       k_current_get(),
 	       _arc_v2_aux_reg_read(_ARC_V2_ERET));
 
 	/*

arch/arc/core/fault.c

@@ -23,9 +23,10 @@
 
 #include <toolchain.h>
 #include <sections.h>
+#include <inttypes.h>
 
 #include <nanokernel.h>
-#include <nano_private.h>
+#include <kernel_structs.h>
 
 #ifdef CONFIG_PRINTK
 #include <misc/printk.h>
@@ -60,11 +61,12 @@ void _FaultDump(const NANO_ESF *esf, int fault)
 	uint32_t exc_addr = _arc_v2_aux_reg_read(_ARC_V2_EFA);
 	uint32_t ecr = _arc_v2_aux_reg_read(_ARC_V2_ECR);
 
-	PR_EXC("Exception vector: 0x%x, cause code: 0x%x, parameter 0x%x\n",
+	PR_EXC("Exception vector: 0x%" PRIx32 ", cause code: 0x%" PRIx32
+	       ", parameter 0x%" PRIx32 "\n",
 	       _ARC_V2_ECR_VECTOR(ecr),
 	       _ARC_V2_ECR_CODE(ecr),
 	       _ARC_V2_ECR_PARAMETER(ecr));
-	PR_EXC("Address 0x%x\n", exc_addr);
+	PR_EXC("Address 0x%" PRIx32 "\n", exc_addr);
 #endif
 }
 #endif /* CONFIG_FAULT_DUMP */

arch/arc/core/fault_s.S

@@ -44,18 +44,17 @@ GTEXT(__ev_extension)
 GTEXT(__ev_div_zero)
 GTEXT(__ev_dc_error)
 GTEXT(__ev_maligned)
-GDATA(_firq_stack)
 
 SECTION_VAR(BSS, saved_stack_pointer)
 	.word 0
 
-#if CONFIG_NUM_IRQ_PRIO_LEVELS == 1
-#error "NUM_IRQ_PRIO_LEVELS==1 is not supported."
-/* The code below sets bit 1 in AUX_IRQ_ACT and thus requires
- * priority 0 and 1 at a minimum. Supporting only 1 priority
- * requires a change to this file but also changes to make
- * FIRQ optional.
- */
+#if CONFIG_RGF_NUM_BANKS == 1
+GDATA(_exception_stack)
+SECTION_VAR(NOINIT, _exception_stack)
+	.space 512
+/* note: QUARK_SE_C1000_SS can't afford 512B */
+#else
+GDATA(_firq_stack)
 #endif
 
 /*
@@ -80,10 +79,8 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 
 	/*
 	 * Before invoking exception handler, the kernel switches to an exception
-	 * stack, which is really the FIRQ stack, to save the faulting thread's
-	 * registers. It can use the FIRQ stack because it knows it is unused
-	 * since it is save to assume that if an exception has happened in FIRQ
-	 * handler, the problem is fatal and all the kernel can do is just print
+	 * stack, to save the faulting thread's registers.
+	 * The exception is fatal and all the kernel can do is just print
 	 * a diagnostic message and halt.
 	 */
 
@@ -97,16 +94,21 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 #endif
 
 	st sp, [saved_stack_pointer]
+#if CONFIG_RGF_NUM_BANKS == 1
+	mov_s sp, _exception_stack
+	add sp, sp, 512
+#else
 	mov_s sp, _firq_stack
 	add sp, sp, CONFIG_FIRQ_STACK_SIZE
+#endif
 
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
 	lr r0,[_ARC_V2_ERSTATUS]
-	st_s r0, [sp, __tISF_status32_OFFSET]
+	st_s r0, [sp, ___isf_t_status32_OFFSET]
 	lr r0,[_ARC_V2_ERET]
-	st_s r0, [sp, __tISF_pc_OFFSET] /* eret into pc */
+	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
 
 	jl _Fault
 
@@ -123,10 +125,8 @@ GTEXT(_irq_do_offload);
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	/*
 	 * Before invoking exception handler, the kernel switches to an exception
-	 * stack, which is really the FIRQ stack, to save the faulting thread's
-	 * registers. It can use the FIRQ stack because it knows it is unused
-	 * since it is safe to assume that if an exception has happened in FIRQ
-	 * handler, the problem is fatal and all the kernel can do is just print
+	 * stack to save the faulting thread's registers.
+	 * The exception is fatal and all the kernel can do is just print
 	 * a diagnostic message and halt.
 	 */
 
@@ -139,26 +139,18 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	pop_s r2
 #endif
 
-#ifndef CONFIG_MICROKERNEL
-	st sp, [saved_stack_pointer]
-	mov_s sp, _firq_stack
-	add sp, sp, CONFIG_FIRQ_STACK_SIZE
-#endif
-
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
 	lr r0,[_ARC_V2_ERSTATUS]
-	st_s r0, [sp, __tISF_status32_OFFSET]
+	st_s r0, [sp, ___isf_t_status32_OFFSET]
 	lr r0,[_ARC_V2_ERET]
-	st_s r0, [sp, __tISF_pc_OFFSET] /* eret into pc */
+	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
 
 	jl _irq_do_offload
 
-#ifdef CONFIG_MICROKERNEL
-	mov_s r1, _nanokernel
-	ld_s r2, [r1, __tNANO_current_OFFSET]
-#if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
 	/* check if we're a nested interrupt: if so, let the
 	 * interrupted interrupt handle the reschedule
 	 */
@@ -172,55 +164,58 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 _trap_return:
 	_pop_irq_stack_frame
 	rtie
-#endif
 
 .balign 4
 _trap_check_for_swap:
-	ld_s r0, [r2, __tTCS_flags_OFFSET]
-	and.f r0, r0, PREEMPTIBLE
-	bnz _e_check_if_a_fiber_is_ready
-	b _trap_return
+	/* coop thread ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_prio]
+	brlt r0, 0, _trap_return
 
-.balign 4
-_e_check_if_a_fiber_is_ready:
-	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
-	brne r0, 0, _trap_reschedule
-	b _trap_return
+	/* scheduler locked ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_sched_locked]
+	brgt r0, 0, _trap_return
 
-.balign 4
-_trap_reschedule:
+	/* check if the current thread needs to be rescheduled */
+	push_s r2
+	push_s r1
+	push_s blink
+	jl _is_next_thread_current
+	pop_s blink
+	pop_s r1
+	pop_s r2
+	brne r0, 0, _trap_return
 
 	_save_callee_saved_regs
 
-	st _CAUSE_RIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
+	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
 	/* note: Ok to use _CAUSE_RIRQ since everything is saved */
 
-	ld_s r2, [r1, __tNANO_fiber_OFFSET]
-
-	st_s r2, [r1, __tNANO_current_OFFSET]
-	ld_s r3, [r2, __tTCS_link_OFFSET]
-	st_s r3, [r1, __tNANO_fiber_OFFSET]
+	/*
+	 * Save needed registers to callee saved ones. It is faster than
+	 * pushing registers to stack. It is possible to do since program has
+	 * just saved them and the calling routine will save them in turn
+	 * if it uses them.
+	 */
+	mov_s r13, blink
+	mov_s r14, r0
+	mov_s r15, r1
+	jl _get_next_ready_thread
+	mov_s r2, r0
+	mov_s r1, r15
+	mov_s r0, r14
+	mov_s blink, r13
+	st_s r2, [r1, _kernel_offset_to_current]
 
 	/* clear AE bit to forget this was an exception */
 	lr r3, [_ARC_V2_STATUS32]
 	and r3,r3,(~_ARC_V2_STATUS32_AE)
 	kflag r3
- 	/* pretend priority 1 int happened to use common handler */
+	/* pretend lowest priority interrupt happened to use common handler */
 	lr r3, [_ARC_V2_AUX_IRQ_ACT]
-	or r3,r3,2
+	or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1)) /* use lowest */
 	sr r3, [_ARC_V2_AUX_IRQ_ACT]
 
 	/* Assumption: r2 has current thread */
 	b _rirq_common_interrupt_swap
-#else
-	/* Nanokernel-only just returns from exception */
-
-	/* if _Fault returns, restore the registers */
-	_pop_irq_stack_frame
-
-	/* now restore the stack */
-	ld sp,[saved_stack_pointer]
-	rtie
-#endif
 
 #endif /* CONFIG_IRQ_OFFLOAD */

arch/arc/core/irq_manage.c

@@ -22,9 +22,6 @@
  * Interrupt management:
  *
  * - enabling/disabling
- * - dynamic ISR connecting/replacing
- *
- * SW_ISR_TABLE_DYNAMIC has to be enabled for connecting ISRs at runtime.
  *
  * An IRQ number passed to the @a irq parameters found in this file is a
  * number from 16 to last IRQ number on the platform.
@@ -78,24 +75,23 @@ void _arch_irq_disable(unsigned int irq)
  *
  * @brief Set an interrupt's priority
  *
- * Valid values are from 0 to 15. Interrupts of priority 1 are not masked when
- * interrupts are locked system-wide, so care must be taken when using them. ISR
- * installed with priority 0 interrupts cannot make kernel calls.
- *
- * The priority is verified if ASSERT_ON is enabled.
+ * Lower values take priority over higher values. Special case priorities are
+ * expressed via mutually exclusive flags.
+
+ * The priority is verified if ASSERT_ON is enabled; max priority level
+ * depends on CONFIG_NUM_IRQ_PRIO_LEVELS.
  *
  * @return N/A
  */
 
-void _irq_priority_set(
-	unsigned int irq,
-	unsigned int prio
-)
+void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
+	ARG_UNUSED(flags);
+
 	int key = irq_lock();
 
-	__ASSERT(prio >= 0 && prio < CONFIG_NUM_IRQ_PRIO_LEVELS,
-			 "invalid priority!");
+	__ASSERT(prio < CONFIG_NUM_IRQ_PRIO_LEVELS,
+		 "invalid priority %d for irq %d", prio, irq);
 	_arc_v2_irq_unit_prio_set(irq, prio);
 	irq_unlock(key);
 }
@@ -118,75 +114,3 @@ void _irq_spurious(void *unused)
 		;
 }
 
-#if CONFIG_SW_ISR_TABLE_DYNAMIC
-/*
- * @internal
- *
- * @brief Replace an interrupt handler by another
- *
- * An interrupt's ISR can be replaced at runtime.
- *
- * @return N/A
- */
-
-void _irq_handler_set(
-	unsigned int irq,
-	void (*new)(void *arg),
-	void *arg
-)
-{
-	int key = irq_lock();
-	int index = irq - 16;
-
-	__ASSERT(irq < CONFIG_NUM_IRQS, "IRQ number too high");
-	_sw_isr_table[index].isr = new;
-	_sw_isr_table[index].arg = arg;
-
-	irq_unlock(key);
-}
-
-/*
- * @brief Connect an ISR to an interrupt line
- *
- * @a isr is connected to interrupt line @a irq, a number greater than or equal
- * 16. No prior ISR can have been connected on @a irq interrupt line since the
- * system booted.
- *
- * This routine will hang if another ISR was connected for interrupt line @a irq
- * and ASSERT_ON is enabled; if ASSERT_ON is disabled, it will fail silently.
- *
- * @return the interrupt line number
- */
-
-int _arch_irq_connect_dynamic(
-	unsigned int irq,
-	unsigned int prio,
-	void (*isr)(void *arg),
-	void *arg,
-	uint32_t flags
-)
-{
-	ARG_UNUSED(flags);
-	_irq_handler_set(irq, isr, arg);
-	_irq_priority_set(irq, prio);
-	return irq;
-}
-
-/*
- * @internal
- *
- * @brief Disconnect an ISR from an interrupt line
- *
- * Interrupt line @a irq is disconnected from its ISR and the latter is
- * replaced by _irq_spurious(). irq_disable() should have been called before
- * invoking this routine.
- *
- * @return N/A
- */
-
-void _irq_disconnect(unsigned int irq)
-{
-	_irq_handler_set(irq, _irq_spurious, NULL);
-}
-
-#endif /* CONFIG_SW_ISR_TABLE_DYNAMIC */

arch/arc/core/isr_wrapper.S

@@ -25,18 +25,25 @@
 
 #define _ASMLANGUAGE
 
-#include <offsets.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <sections.h>
 #include <sw_isr_table.h>
-#include <nano_private.h>
+#include <kernel_structs.h>
 #include <arch/cpu.h>
 
 GTEXT(_isr_enter)
 GTEXT(_isr_demux)
 
-#if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
-GTEXT(_power_save_idle_exit)
+#if CONFIG_RGF_NUM_BANKS == 1
+GDATA(saved_r0)
+
+SECTION_VAR(BSS, saved_r0)
+        .word 0
+#endif
+
+#if defined(CONFIG_SYS_POWER_MANAGEMENT)
+GTEXT(_sys_power_save_idle_exit)
 #endif
 
 /*
@@ -61,9 +68,6 @@ IRQ stack frame layout:
 
            status32
               pc
-          [jli_base]
-          [ldi_base]
-          [ei_base]
            lp_count
            lp_start
             lp_end
@@ -74,16 +78,21 @@ IRQ stack frame layout:
 
   low address
 
-  [registers not taken into account in the current implementation]
+Registers not taken into account in the current implementation.
+          jli_base
+          ldi_base
+          ei_base
+          accl
+          acch
 
 The context switch code adopts this standard so that it is easier to follow:
 
-  - r1 contains _nanokernel ASAP and is not overwritten over the lifespan of
+  - r1 contains _kernel ASAP and is not overwritten over the lifespan of
     the functions.
-  - r2 contains _nanokernel.current ASAP, and the incoming thread when we
+  - r2 contains _kernel.current ASAP, and the incoming thread when we
     transition from outgoing thread to incoming thread
 
-Not loading _nanokernel into r0 allows loading _nanokernel without stomping on
+Not loading _kernel into r0 allows loading _kernel without stomping on
 the parameter in r0 in _Swap().
 
 
@@ -92,16 +101,23 @@ official documentation calls the regular interrupts 'IRQs', but the internals
 of the kernel call them 'RIRQs' to differentiate from the 'irq' subsystem,
 which is the interrupt API/layer of abstraction.
 
-FIRQs can be used to allow ISRs to run without having to save any context,
-since they work with a second register bank. However, they can be somewhat more
-limited than RIRQs since the register bank does not copy every possible
-register that is needed to implement all available instructions: an example is
-that the 'loop' registers (lp_count, lp_end, lp_start) are not present in the
-second bank. The kernel thus takes upon itself to save these extra registers,
-if the FIRQ is made known to the kernel. It is possible for a FIRQ to operate
-outside of the kernel, but care must be taken to only use instructions that
-only use the banked registers. RIRQs must always use the kernel's interrupt
-entry and exit mechanisms.
+For FIRQ, there are two cases, depending upon the value of
+CONFIG_RGF_NUM_BANKS.
+
+CONFIG_RGF_NUM_BANKS==1 case:
+Scratch registers are pushed onto the current stack just as they are with
+RIRQ. See the above frame layout. Unlike RIRQ, the status32_p0 and ilink
+registers are where status32 and the program counter are located, so these
+need to be pushed.
+
+CONFIG_RGF_NUM_BANKS!=1 case:
+The FIRQ handler has its own register bank for general purpose registers,
+and thus it doesn't have to save them on a stack. The 'loop' registers
+(lp_count, lp_end, lp_start), however, are not present in the
+second bank. The handler saves these special registers in unused callee saved
+registers (to avoid stack accesses). It is possible to register a FIRQ
+handler that operates outside of the kernel, but care must be taken to only
+use instructions that only use the banked registers.
 
 The kernel is able to handle transitions to and from FIRQ, RIRQ and threads
 (fibers/task). The contexts are saved 'lazily': the minimum amount of work is
@@ -122,14 +138,24 @@ o FIRQ
   the FIRQ does not take a scheduling decision and leaves it the RIRQ to
   handle. This limits the amount of code that has to run at interrupt-level.
 
-  GPRs are banked, loop registers are saved in a global structure upon
-  interrupt entry. If returning to a fiber, loop registers are poppped and the
+  CONFIG_RGF_NUM_BANKS==1 case:
+  Registers are saved on the stack frame just as they are for RIRQ.
+  Context switch can happen just as it does in the RIRQ case, however,
+  if the FIRQ interrupted a RIRQ, the FIRQ will return from interrupt and
+  let the RIRQ do the context switch.  At entry, one register is needed in order
+  to have code to save other registers. r0 is saved first in a global called
+  saved_r0.
+
+  CONFIG_RGF_NUM_BANKS!=1 case:
+  During early initialization, the sp in the 2nd register bank is made to
+  refer to _firq_stack. This allows for the FIRQ handler to use its own stack.
+  GPRs are banked, loop registers are saved in unused callee saved regs upon
+  interrupt entry. If returning to a fiber, loop registers are restored and the
   CPU switches back to bank 0 for the GPRs. If a context switch is
   needed, at this point only are all the registers saved. First, a
   stack frame with the same layout as the automatic RIRQ one is created
   and then the callee-saved GPRs are saved in the TCS. status32_p0 and
   ilink are saved in this case, not status32 and pc.
-
   To create the stack frame, the FIRQ handling code must first go back to using
   bank0 of registers, since that is where the registers containing the exiting
   thread are saved. Care must be taken not to touch any register before saving
@@ -159,8 +185,10 @@ From coop:
 
 From FIRQ:
 
-  The processor is back to using bank0, not bank1 anymore, because it had to
-  save the outgoing context from bank0, and now has to load the incoming one
+  When CONFIG_RGF_NUM_BANKS==1, context switch is done as it is for RIRQ.
+  When CONFIG_RGF_NUM_BANKS!=1, the processor is put back to using bank0,
+  not bank1 anymore, because it had to save the outgoing context from bank0,
+  and now has to load the incoming one
   into bank0.
 
   o to coop
@@ -200,16 +228,55 @@ From RIRQ:
  */
 
 SECTION_FUNC(TEXT, _isr_enter)
+#if CONFIG_RGF_NUM_BANKS == 1
+	st r0,[saved_r0]
+#endif
 	lr r0, [_ARC_V2_AUX_IRQ_ACT]
 	ffs r0, r0
 	cmp r0, 0
-
+#if CONFIG_RGF_NUM_BANKS == 1
+	bnz rirq_path
+	/* 1-register bank FIRQ handling must save registers on stack */
+	lr r0,[_ARC_V2_STATUS32_P0]
+	push_s r0
+	mov r0,ilink
+	push_s r0
+	mov r0,lp_count
+	push_s r0
+	lr r0, [_ARC_V2_LP_START]
+	push_s r0
+	lr r0, [_ARC_V2_LP_END]
+	push_s r0
+	push_s blink
+	push_s r13
+	push_s r12
+	push r11
+	push r10
+	push r9
+	push r8
+	push r7
+	push r6
+	push r5
+	push r4
+	push_s r3
+	push_s r2
+	push_s r1
+	ld r0,[saved_r0]
+	push_s r0
+	mov r3, _firq_exit
+	mov r2, _firq_enter
+	j_s [r2]
+rirq_path:
+	mov r3, _rirq_exit
+	mov r2, _rirq_enter
+	j_s [r2]
+#else
 	mov.z r3, _firq_exit
 	mov.z r2, _firq_enter
 	mov.nz r3, _rirq_exit
 	mov.nz r2, _rirq_enter
-
 	j_s [r2]
+#endif
 
 #ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
 GTEXT(_sys_k_event_logger_exit_sleep)
@@ -242,14 +309,23 @@ GTEXT(_sys_k_event_logger_interrupt)
 	#define log_interrupt_k_event
 #endif
 
-#if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
+#if defined(CONFIG_SYS_POWER_MANAGEMENT)
 .macro exit_tickless_idle
 	clri r0 /* do not interrupt exiting tickless idle operations */
+	push_s r1
 	push_s r0
+	mov_s r1, _kernel
+	ld_s r0, [r1, _kernel_offset_to_idle] /* requested idle duration */
+	breq r0, 0, _skip_sys_power_save_idle_exit
+
+	st 0, [r1, _kernel_offset_to_idle] /* zero idle duration */
 	push_s blink
-	jl _power_save_idle_exit
+	jl _sys_power_save_idle_exit
 	pop_s blink
+
+_skip_sys_power_save_idle_exit:
 	pop_s r0
+	pop_s r1
 	seti r0
 .endm
 #else

arch/arc/core/offsets/offsets.c

@@ -34,74 +34,60 @@
  */
 
 #include <gen_offset.h>
-#include <nano_private.h>
-#include <nano_offsets.h>
+#include <kernel_structs.h>
+#include <kernel_offsets.h>
 
-/* ARCv2-specific tNANO structure member offsets */
-GEN_OFFSET_SYM(tNANO, rirq_sp);
-#ifdef CONFIG_SYS_POWER_MANAGEMENT
-GEN_OFFSET_SYM(tNANO, idle);
-#endif
-
-/* ARCv2-specific struct tcs structure member offsets */
-GEN_OFFSET_SYM(tTCS, intlock_key);
-GEN_OFFSET_SYM(tTCS, relinquish_cause);
-GEN_OFFSET_SYM(tTCS, return_value);
+GEN_OFFSET_SYM(_thread_arch_t, intlock_key);
+GEN_OFFSET_SYM(_thread_arch_t, relinquish_cause);
+GEN_OFFSET_SYM(_thread_arch_t, return_value);
 #ifdef CONFIG_ARC_STACK_CHECKING
-GEN_OFFSET_SYM(tTCS, stack_top);
+GEN_OFFSET_SYM(_thread_arch_t, stack_top);
 #endif
-#ifdef CONFIG_THREAD_CUSTOM_DATA
-GEN_OFFSET_SYM(tTCS, custom_data);
-#endif
-
 
 /* ARCv2-specific IRQ stack frame structure member offsets */
-GEN_OFFSET_SYM(tISF, r0);
-GEN_OFFSET_SYM(tISF, r1);
-GEN_OFFSET_SYM(tISF, r2);
-GEN_OFFSET_SYM(tISF, r3);
-GEN_OFFSET_SYM(tISF, r4);
-GEN_OFFSET_SYM(tISF, r5);
-GEN_OFFSET_SYM(tISF, r6);
-GEN_OFFSET_SYM(tISF, r7);
-GEN_OFFSET_SYM(tISF, r8);
-GEN_OFFSET_SYM(tISF, r9);
-GEN_OFFSET_SYM(tISF, r10);
-GEN_OFFSET_SYM(tISF, r11);
-GEN_OFFSET_SYM(tISF, r12);
-GEN_OFFSET_SYM(tISF, r13);
-GEN_OFFSET_SYM(tISF, blink);
-GEN_OFFSET_SYM(tISF, lp_end);
-GEN_OFFSET_SYM(tISF, lp_start);
-GEN_OFFSET_SYM(tISF, lp_count);
-GEN_OFFSET_SYM(tISF, pc);
-GEN_OFFSET_SYM(tISF, status32);
-GEN_ABSOLUTE_SYM(__tISF_SIZEOF, sizeof(tISF));
+GEN_OFFSET_SYM(_isf_t, r0);
+GEN_OFFSET_SYM(_isf_t, r1);
+GEN_OFFSET_SYM(_isf_t, r2);
+GEN_OFFSET_SYM(_isf_t, r3);
+GEN_OFFSET_SYM(_isf_t, r4);
+GEN_OFFSET_SYM(_isf_t, r5);
+GEN_OFFSET_SYM(_isf_t, r6);
+GEN_OFFSET_SYM(_isf_t, r7);
+GEN_OFFSET_SYM(_isf_t, r8);
+GEN_OFFSET_SYM(_isf_t, r9);
+GEN_OFFSET_SYM(_isf_t, r10);
+GEN_OFFSET_SYM(_isf_t, r11);
+GEN_OFFSET_SYM(_isf_t, r12);
+GEN_OFFSET_SYM(_isf_t, r13);
+GEN_OFFSET_SYM(_isf_t, blink);
+GEN_OFFSET_SYM(_isf_t, lp_end);
+GEN_OFFSET_SYM(_isf_t, lp_start);
+GEN_OFFSET_SYM(_isf_t, lp_count);
+GEN_OFFSET_SYM(_isf_t, pc);
+GEN_OFFSET_SYM(_isf_t, status32);
+GEN_ABSOLUTE_SYM(___isf_t_SIZEOF, sizeof(_isf_t));
 
-/* ARCv2-specific preempt registers structure member offsets */
-GEN_OFFSET_SYM(tPreempt, sp);
-GEN_ABSOLUTE_SYM(__tPreempt_SIZEOF, sizeof(tPreempt));
+GEN_OFFSET_SYM(_callee_saved_t, sp);
+GEN_ABSOLUTE_SYM(___callee_saved_t_SIZEOF, sizeof(_callee_saved_t));
 
-/* ARCv2-specific callee-saved stack */
-GEN_OFFSET_SYM(tCalleeSaved, r13);
-GEN_OFFSET_SYM(tCalleeSaved, r14);
-GEN_OFFSET_SYM(tCalleeSaved, r15);
-GEN_OFFSET_SYM(tCalleeSaved, r16);
-GEN_OFFSET_SYM(tCalleeSaved, r17);
-GEN_OFFSET_SYM(tCalleeSaved, r18);
-GEN_OFFSET_SYM(tCalleeSaved, r19);
-GEN_OFFSET_SYM(tCalleeSaved, r20);
-GEN_OFFSET_SYM(tCalleeSaved, r21);
-GEN_OFFSET_SYM(tCalleeSaved, r22);
-GEN_OFFSET_SYM(tCalleeSaved, r23);
-GEN_OFFSET_SYM(tCalleeSaved, r24);
-GEN_OFFSET_SYM(tCalleeSaved, r25);
-GEN_OFFSET_SYM(tCalleeSaved, r26);
-GEN_OFFSET_SYM(tCalleeSaved, fp);
-GEN_OFFSET_SYM(tCalleeSaved, r30);
-GEN_ABSOLUTE_SYM(__tCalleeSaved_SIZEOF, sizeof(tCalleeSaved));
+GEN_OFFSET_SYM(_callee_saved_stack_t, r13);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r14);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r15);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r16);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r17);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r18);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r19);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r20);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r21);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r22);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r23);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r24);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r25);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r26);
+GEN_OFFSET_SYM(_callee_saved_stack_t, fp);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r30);
+GEN_ABSOLUTE_SYM(___callee_saved_stack_t_SIZEOF, sizeof(_callee_saved_stack_t));
 
-/* size of the struct tcs structure sans save area for floating point regs */
-GEN_ABSOLUTE_SYM(__tTCS_NOFLOAT_SIZEOF, sizeof(tTCS));
+GEN_ABSOLUTE_SYM(_K_THREAD_NO_FLOAT_SIZEOF, sizeof(struct k_thread));
 
 GEN_ABS_SYM_END

arch/arc/core/prep_c.c

@@ -30,53 +30,12 @@
 #include <toolchain.h>
 #include <linker-defs.h>
 #include <arch/arc/v2/aux_regs.h>
-
-/**
- *
- * @brief Clear BSS
- *
- * This routine clears the BSS region, so all bytes are 0.
- *
- * @return N/A
- */
-
-static void bssZero(void)
-{
-	volatile uint32_t *pBSS = (uint32_t *)&__bss_start;
-	unsigned int n;
-
-	for (n = 0; n < (unsigned int)&__bss_num_words; n++) {
-		pBSS[n] = 0;
-	}
-}
-
-/**
- *
- * @brief Copy the data section from ROM to RAM
- *
- * This routine copies the data section from ROM to RAM.
- *
- * @return N/A
- */
-
-#ifdef CONFIG_XIP
-static void dataCopy(void)
-{
-	volatile uint32_t *pROM = (uint32_t *)&__data_rom_start;
-	volatile uint32_t *pRAM = (uint32_t *)&__data_ram_start;
-	unsigned int n;
-
-	for (n = 0; n < (unsigned int)&__data_num_words; n++) {
-		pRAM[n] = pROM[n];
-	}
-}
-#else
-static void dataCopy(void)
-{
-}
-#endif
+#include <kernel_structs.h>
+#include <nano_internal.h>
 
 
+/* XXX - keep for future use in full-featured cache APIs */
+#if 0
 /**
  *
  * @brief Disable the i-cache if present
@@ -122,7 +81,7 @@ static void invalidate_dcache(void)
 	}
 	_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
 }
-
+#endif
 
 /**
  *
@@ -164,11 +123,9 @@ extern FUNC_NORETURN void _Cstart(void);
 
 void _PrepC(void)
 {
-	disable_icache();
-	invalidate_dcache();
 	adjust_vector_table_base();
-	bssZero();
-	dataCopy();
+	_bss_zero();
+	_data_copy();
 	_Cstart();
 	CODE_UNREACHABLE;
 }

arch/arc/core/regular_irq.S

@@ -26,8 +26,8 @@
 
 #define _ASMLANGUAGE
 
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
 #include "swap_macros.h"
@@ -35,12 +35,23 @@
 GTEXT(_rirq_enter)
 GTEXT(_rirq_exit)
 GTEXT(_rirq_common_interrupt_swap)
+GTEXT(_is_next_thread_current)
 
-#if CONFIG_NUM_IRQ_PRIO_LEVELS > 2
-#error "NUM_IRQ_PRIO_LEVELS>2 is not supported."
+#if 0 /* TODO: when FIRQ is not present, all would be regular */
+#define NUM_REGULAR_IRQ_PRIO_LEVELS CONFIG_NUM_IRQ_PRIO_LEVELS
+#else
+#define NUM_REGULAR_IRQ_PRIO_LEVELS (CONFIG_NUM_IRQ_PRIO_LEVELS-1)
+#endif
+/* note: the above define assumes that prio 0 IRQ is for FIRQ, and
+ * that all others are regular interrupts.
+ * TODO: Revist this if FIRQ becomes configurable.
+ */
+
+#if NUM_REGULAR_IRQ_PRIO_LEVELS > 1
+#error "nested regular interrupts are not supported."
 /*
  * Nesting of Regularing interrupts is not yet supported.
- * If your SOC supports more than 2, set this value to 2.
+ * Set CONFIG_NUM_IRQ_PRIO_LEVELS to 2 even if SOC supports more.
  */
 #endif
 
@@ -60,17 +71,17 @@ GTEXT(_rirq_common_interrupt_swap)
 
 SECTION_FUNC(TEXT, _rirq_enter)
 
-	mov r1, _nanokernel
+	mov r1, _kernel
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* disable stack checking */
 	lr r2, [_ARC_V2_STATUS32]
 	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
 	kflag r2
 #endif
-	ld_s r2, [r1, __tNANO_current_OFFSET]
-#if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS == 1
-	st sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
-	ld sp, [r1, __tNANO_rirq_sp_OFFSET]
+	ld_s r2, [r1, _kernel_offset_to_current]
+#if NUM_REGULAR_IRQ_PRIO_LEVELS == 1
+	st sp, [r2, _thread_offset_to_sp]
+	ld sp, [r1, _kernel_offset_to_irq_stack]
 #else
 #error regular irq nesting is not implemented
 #endif
@@ -86,10 +97,17 @@ SECTION_FUNC(TEXT, _rirq_enter)
 
 SECTION_FUNC(TEXT, _rirq_exit)
 
-	mov r1, _nanokernel
-	ld_s r2, [r1, __tNANO_current_OFFSET]
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
 
-#if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS > 1
+	/*
+	 * Lock interrupts to ensure kernel queues do not change from this
+	 * point on until return from interrupt.
+	 */
+
+	clri
+
+#if NUM_REGULAR_IRQ_PRIO_LEVELS > 1
 	/* check if we're a nested interrupt: if so, let the interrupted interrupt
 	 * handle the reschedule */
 
@@ -106,7 +124,7 @@ SECTION_FUNC(TEXT, _rirq_exit)
 
 	cmp r0, r3
 	brgt _rirq_return_from_rirq
-	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
+	ld sp, [r2, _thread_offset_to_sp]
 #endif
 
 	/*
@@ -118,15 +136,47 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	 * b) needs to load it to restore the interrupted context.
 	 */
 
-	ld_s r0, [r2, __tTCS_flags_OFFSET]
-	and.f r0, r0, PREEMPTIBLE
-	bz.d _rirq_no_reschedule
-	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
+	/* coop thread ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_prio]
+	cmp_s r0, 0
+	blt.d _rirq_no_reschedule
+	ld sp, [r2, _thread_offset_to_sp]
 
-	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
-	cmp r0, 0
-	bz.d _rirq_no_reschedule
-	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
+	/* scheduler locked ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_sched_locked]
+#ifdef CONFIG_ARC_STACK_CHECKING
+	brle.d r0, 0,  _rirq_reschedule_check
+	ld sp, [r2, _thread_offset_to_sp]
+	b  _rirq_no_reschedule
+	/* This branch is a bit far */
+_rirq_reschedule_check:
+#else
+	brgt.d r0, 0,  _rirq_no_reschedule
+	ld sp, [r2, _thread_offset_to_sp]
+#endif
+
+	/* check if the current thread needs to be rescheduled */
+	push_s r2
+	push_s r1
+	push_s blink
+	jl _is_next_thread_current
+	pop_s blink
+	pop_s r1
+	pop_s r2
+	brne.d r0, 0, _rirq_no_reschedule
+	ld sp, [r2, _thread_offset_to_sp]
+
+	/*
+	 * Get the next scheduled thread. On _get_next_ready_thread
+	 * return it is stored in r0.
+	 */
+	push_s r2
+	push_s r1
+	push_s blink
+	jl _get_next_ready_thread
+	pop_s blink
+	pop_s r1
+	pop_s r2
 
 .balign 4
 _rirq_reschedule:
@@ -134,22 +184,21 @@ _rirq_reschedule:
 	/* _save_callee_saved_regs expects outgoing thread in r2 */
 	_save_callee_saved_regs
 
-	st _CAUSE_RIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
+	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
 
-	/* incoming fiber is in r0: it becomes the new 'current' */
+	/* incoming thread is in r0: it becomes the new 'current' */
 	mov r2, r0
-	st_s r2, [r1, __tNANO_current_OFFSET]
-	ld_s r3, [r2, __tTCS_link_OFFSET]
-	st_s r3, [r1, __tNANO_fiber_OFFSET]
+	st_s r2, [r1, _kernel_offset_to_current]
 
+.balign 4
 _rirq_common_interrupt_swap:
 	/* r2 contains pointer to new thread */
 
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
-	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_stack_top]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/*
@@ -158,7 +207,7 @@ _rirq_common_interrupt_swap:
 	 */
 	_load_callee_saved_regs
 
-	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
 
 	breq r3, _CAUSE_RIRQ, _rirq_return_from_rirq
 	nop
@@ -174,19 +223,22 @@ _rirq_return_from_coop:
 
 	/* update status32.ie (explanation in firq_exit:_firq_return_from_coop) */
 	ld_s r0, [sp, 4]
-	ld_s r3, [r2, __tTCS_intlock_key_OFFSET]
-	st  0, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_intlock_key]
+	st  0, [r2, _thread_offset_to_intlock_key]
 	cmp r3, 0
 	or.ne r0, r0, _ARC_V2_STATUS32_IE
 	st_s r0, [sp, 4]
 
 	/* carve fake stack */
 
-	sub sp, sp, (__tISF_SIZEOF - 12) /* a) status32/pc are already on the stack
-	                                  * b) a real value will be pushed in r0 */
+	/*
+	 * a) status32/pc are already on the stack
+	 * b) a real value will be pushed in r0
+	 */
+	sub sp, sp, (___isf_t_SIZEOF - 12)
 
 	/* push return value on stack */
-	ld_s r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, _thread_offset_to_return_value]
 	push_s r0
 
 	/*
@@ -195,7 +247,7 @@ _rirq_return_from_coop:
 	 * IRQ prologue. r13 thus has to be set to its correct value in the IRQ
 	 * stack frame.
 	 */
-	st_s r13, [sp, __tISF_r13_OFFSET]
+	st_s r13, [sp, ___isf_t_r13_OFFSET]
 
 	/* stack now has the IRQ stack frame layout, pointing to r0 */
 

arch/arc/core/reset.S

@@ -28,11 +28,26 @@
 #include <sections.h>
 #include <arch/cpu.h>
 
-#ifdef CONFIG_HARVARD
-#define _TOP_OF_MEMORY (CONFIG_DCCM_BASE_ADDRESS + CONFIG_DCCM_SIZE * 1024)
-/* harvard places the initial stack in the dccm memory */
+GDATA(_interrupt_stack)
+GDATA(_firq_stack)
+GDATA(_main_stack)
+
+/* use one of the available interrupt stacks during init */
+
+/* FIRQ only ? */
+#if CONFIG_NUM_IRQ_PRIO_LEVELS == 1
+
+	/* FIRQ, but uses _interrupt_stack ? */
+	#if CONFIG_RGF_NUM_BANKS == 1
+		#define INIT_STACK _interrupt_stack
+		#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
+	#else
+		#define INIT_STACK _firq_stack
+		#define INIT_STACK_SIZE CONFIG_FIRQ_STACK_SIZE
+	#endif
 #else
-#define _TOP_OF_MEMORY (CONFIG_SRAM_BASE_ADDRESS + CONFIG_SRAM_SIZE * 1024)
+	#define INIT_STACK _interrupt_stack
+	#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
 #endif
 
 GTEXT(__reset)
@@ -58,7 +73,56 @@ SECTION_FUNC(TEXT,__start)
 	/* lock interrupts: will get unlocked when switch to main task */
 	clri
 
-	/* setup a stack at the end of MEMORY */
-	mov sp, _TOP_OF_MEMORY
+	mov r1, 1
+
+invalidate_and_disable_icache:
+
+	lr r0, [_ARC_V2_I_CACHE_BUILD]
+	and.f r0, r0, 0xff
+	bz.nd invalidate_dcache
+
+	mov_s r2, 0
+	sr r2, [_ARC_V2_IC_IVIC]
+	/* writing to IC_IVIC needs 3 NOPs */
+	nop
+	nop
+	nop
+	sr r1, [_ARC_V2_IC_CTRL]
+
+invalidate_dcache:
+
+	lr r3, [_ARC_V2_D_CACHE_BUILD]
+	and.f r3, r3, 0xff
+	bz.nd done_cache_invalidate
+
+	sr r1, [_ARC_V2_DC_IVDC]
+
+done_cache_invalidate:
+
+#ifdef CONFIG_INIT_STACKS
+	/*
+	 * use the main stack to call memset on the interrupt stack and the
+	 * FIRQ stack when CONFIG_INIT_STACKS is enabled before switching to
+	 * one of them for the rest of the early boot
+	 */
+	mov sp, _main_stack
+	add sp, sp, CONFIG_MAIN_STACK_SIZE
+
+	mov_s r0, _interrupt_stack
+	mov_s r1, 0xaa
+	mov_s r2, CONFIG_ISR_STACK_SIZE
+	jl memset
+
+#if CONFIG_RGF_NUM_BANKS != 1
+	mov_s r0, _firq_stack
+	mov_s r1, 0xaa
+	mov_s r2, CONFIG_FIRQ_STACK_SIZE
+	jl memset
+#endif
+
+#endif /* CONFIG_INIT_STACKS */
+
+	mov sp, INIT_STACK
+	add sp, sp, INIT_STACK_SIZE
 
 	j @_PrepC

arch/arc/core/swap.S

@@ -26,16 +26,17 @@
 
 #define _ASMLANGUAGE
 
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
 #include <v2/irq.h>
 #include "swap_macros.h"
 
 GTEXT(_Swap)
-
-GDATA(_nanokernel)
+GTEXT(_get_next_ready_thread)
+GDATA(_k_neg_eagain)
+GDATA(_kernel)
 
 /**
  *
@@ -55,8 +56,9 @@ GDATA(_nanokernel)
  * popped when returning from _Swap(), but is not suitable for handling a return
  * from an exception. Thus, the fact that the thread is pending because of a
  * cooperative call to _Swap() has to be recorded via the _CAUSE_COOP code in
- * the relinquish_cause of the thread's tTCS. The _IrqExit()/_FirqExit() code
- * will take care of doing the right thing to restore the thread status.
+ * the relinquish_cause of the thread's k_thread structure. The
+ * _IrqExit()/_FirqExit() code will take care of doing the right thing to
+ * restore the thread status.
  *
  * When _Swap() is invoked, we know the decision to perform a context switch or
  * not has already been taken and a context switch must happen.
@@ -73,12 +75,21 @@ SECTION_FUNC(TEXT, _Swap)
 
 	/* interrupts are locked, interrupt key is in r0 */
 
-	mov r1, _nanokernel
-	ld_s r2, [r1, __tNANO_current_OFFSET]
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
 
 	/* save intlock key */
-	st_s r0, [r2, __tTCS_intlock_key_OFFSET]
-	st _CAUSE_COOP, [r2, __tTCS_relinquish_cause_OFFSET]
+	st_s r0, [r2, _thread_offset_to_intlock_key]
+	st _CAUSE_COOP, [r2, _thread_offset_to_relinquish_cause]
+
+	/*
+         * Carve space for the return value. Setting it to a defafult of
+         * -EAGAIN eliminates the need for the timeout code to set it.
+         * If another value is ever needed, it can be modified with
+         * fiberRtnValueSet().
+         */
+	ld r3, [_k_neg_eagain]
+	st_s r3, [r2, _thread_offset_to_return_value]
 
 	/*
 	 * Save status32 and blink on the stack before the callee-saved registers.
@@ -95,47 +106,37 @@ SECTION_FUNC(TEXT, _Swap)
 
 	_save_callee_saved_regs
 
-	ld_s r2, [r1, __tNANO_fiber_OFFSET]
-	breq r2, 0, _swap_to_the_task
-
-.balign 4
-_swap_to_a_fiber:
-
-	ld_s r3, [r2, __tTCS_link_OFFSET]
-	b.d _finish_swapping_to_thread    /* always execute delay slot */
-	st_s r3, [r1, __tNANO_fiber_OFFSET] /* delay slot */
-
-.balign 4
-_swap_to_the_task:
-
-	ld_s r2, [r1, __tNANO_task_OFFSET]
-
-	/* fall through */
-
-.balign 4
-_finish_swapping_to_thread:
+	/* find out incoming thread (fiber or task) */
 
+	/*
+	 * Save needed registers to callee saved ones. It is faster than
+	 * pushing them to stack. It is possible to do since program has
+	 * just saved them and the calling routine will save them in turn
+	 * if it uses them.
+	 */
+	mov_s r13, blink
+	mov_s r14, r0
+	mov_s r15, r1
+	jl _get_next_ready_thread
+	mov_s r2, r0
+	mov_s r1, r15
+	mov_s r0, r14
+	mov_s blink, r13
 
 	/* entering here, r2 contains the new current thread */
-#if 0
-/* don't save flags in tNANO: slower, error-prone, and might not even give
- * a speed boost where it's supposed to */
-	ld_s r3, [r2, __tTCS_flags_OFFSET]
-	st_s r3, [r1, __tNANO_flags_OFFSET]
-#endif
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
-	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_stack_top]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/* XXX - can be moved to delay slot of _CAUSE_RIRQ ? */
-	st_s r2, [r1, __tNANO_current_OFFSET]
+	st_s r2, [r1, _kernel_offset_to_current]
 
 	_load_callee_saved_regs
 
-	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
 
 	breq r3, _CAUSE_RIRQ, _swap_return_from_rirq
 	nop
@@ -147,9 +148,9 @@ _finish_swapping_to_thread:
 .balign 4
 _swap_return_from_coop:
 
-	ld_s r1, [r2, __tTCS_intlock_key_OFFSET]
-	st  0, [r2, __tTCS_intlock_key_OFFSET]
-	ld_s r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r1, [r2, _thread_offset_to_intlock_key]
+	st  0, [r2, _thread_offset_to_intlock_key]
+	ld_s r0, [r2, _thread_offset_to_return_value]
 
 	lr ilink, [_ARC_V2_STATUS32]
 	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc

arch/arc/core/swap_macros.h

@@ -19,8 +19,8 @@
 #ifndef _SWAP_MACROS__H_
 #define _SWAP_MACROS__H_
 
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
 
@@ -33,53 +33,53 @@ extern "C" {
 /* entering this macro, current is in r2 */
 .macro _save_callee_saved_regs
 
-	sub_s sp, sp, __tCalleeSaved_SIZEOF
+	sub_s sp, sp, ___callee_saved_stack_t_SIZEOF
 
 	/* save regs on stack */
-	st_s r13, [sp, __tCalleeSaved_r13_OFFSET]
-	st_s r14, [sp, __tCalleeSaved_r14_OFFSET]
-	st_s r15, [sp, __tCalleeSaved_r15_OFFSET]
-	st r16, [sp, __tCalleeSaved_r16_OFFSET]
-	st r17, [sp, __tCalleeSaved_r17_OFFSET]
-	st r18, [sp, __tCalleeSaved_r18_OFFSET]
-	st r19, [sp, __tCalleeSaved_r19_OFFSET]
-	st r20, [sp, __tCalleeSaved_r20_OFFSET]
-	st r21, [sp, __tCalleeSaved_r21_OFFSET]
-	st r22, [sp, __tCalleeSaved_r22_OFFSET]
-	st r23, [sp, __tCalleeSaved_r23_OFFSET]
-	st r24, [sp, __tCalleeSaved_r24_OFFSET]
-	st r25, [sp, __tCalleeSaved_r25_OFFSET]
-	st r26, [sp, __tCalleeSaved_r26_OFFSET]
-	st fp,  [sp, __tCalleeSaved_fp_OFFSET]
-	st r30, [sp, __tCalleeSaved_r30_OFFSET]
+	st_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
+	st_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
+	st_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
+	st r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
+	st r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
+	st r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
+	st r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
+	st r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
+	st r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
+	st r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
+	st r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
+	st r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
+	st r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
+	st r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
+	st fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
+	st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
 
 	/* save stack pointer in struct tcs */
-	st sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
+	st sp, [r2, _thread_offset_to_sp]
 .endm
 
 /* entering this macro, current is in r2 */
 .macro _load_callee_saved_regs
 	/* restore stack pointer from struct tcs */
-	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
+	ld sp, [r2, _thread_offset_to_sp]
 
-	ld_s r13, [sp, __tCalleeSaved_r13_OFFSET]
-	ld_s r14, [sp, __tCalleeSaved_r14_OFFSET]
-	ld_s r15, [sp, __tCalleeSaved_r15_OFFSET]
-	ld r16, [sp, __tCalleeSaved_r16_OFFSET]
-	ld r17, [sp, __tCalleeSaved_r17_OFFSET]
-	ld r18, [sp, __tCalleeSaved_r18_OFFSET]
-	ld r19, [sp, __tCalleeSaved_r19_OFFSET]
-	ld r20, [sp, __tCalleeSaved_r20_OFFSET]
-	ld r21, [sp, __tCalleeSaved_r21_OFFSET]
-	ld r22, [sp, __tCalleeSaved_r22_OFFSET]
-	ld r23, [sp, __tCalleeSaved_r23_OFFSET]
-	ld r24, [sp, __tCalleeSaved_r24_OFFSET]
-	ld r25, [sp, __tCalleeSaved_r25_OFFSET]
-	ld r26, [sp, __tCalleeSaved_r26_OFFSET]
-	ld fp,  [sp, __tCalleeSaved_fp_OFFSET]
-	ld r30, [sp, __tCalleeSaved_r30_OFFSET]
+	ld_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
+	ld_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
+	ld_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
+	ld r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
+	ld r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
+	ld r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
+	ld r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
+	ld r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
+	ld r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
+	ld r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
+	ld r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
+	ld r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
+	ld r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
+	ld r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
+	ld fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
+	ld r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
 
-	add_s sp, sp, __tCalleeSaved_SIZEOF
+	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
 
 .endm
 
@@ -89,33 +89,33 @@ extern "C" {
  */
 .macro _create_irq_stack_frame
 
-	sub_s sp, sp, __tISF_SIZEOF
+	sub_s sp, sp, ___isf_t_SIZEOF
 
-	st blink, [sp, __tISF_blink_OFFSET]
+	st blink, [sp, ___isf_t_blink_OFFSET]
 
 	/* store these right away so we can use them if needed */
 
-	st_s r13, [sp, __tISF_r13_OFFSET]
-	st_s r12, [sp, __tISF_r12_OFFSET]
-	st   r11, [sp, __tISF_r11_OFFSET]
-	st   r10, [sp, __tISF_r10_OFFSET]
-	st   r9,  [sp, __tISF_r9_OFFSET]
-	st   r8,  [sp, __tISF_r8_OFFSET]
-	st   r7,  [sp, __tISF_r7_OFFSET]
-	st   r6,  [sp, __tISF_r6_OFFSET]
-	st   r5,  [sp, __tISF_r5_OFFSET]
-	st   r4,  [sp, __tISF_r4_OFFSET]
-	st_s r3,  [sp, __tISF_r3_OFFSET]
-	st_s r2,  [sp, __tISF_r2_OFFSET]
-	st_s r1,  [sp, __tISF_r1_OFFSET]
-	st_s r0,  [sp, __tISF_r0_OFFSET]
+	st_s r13, [sp, ___isf_t_r13_OFFSET]
+	st_s r12, [sp, ___isf_t_r12_OFFSET]
+	st   r11, [sp, ___isf_t_r11_OFFSET]
+	st   r10, [sp, ___isf_t_r10_OFFSET]
+	st   r9,  [sp, ___isf_t_r9_OFFSET]
+	st   r8,  [sp, ___isf_t_r8_OFFSET]
+	st   r7,  [sp, ___isf_t_r7_OFFSET]
+	st   r6,  [sp, ___isf_t_r6_OFFSET]
+	st   r5,  [sp, ___isf_t_r5_OFFSET]
+	st   r4,  [sp, ___isf_t_r4_OFFSET]
+	st_s r3,  [sp, ___isf_t_r3_OFFSET]
+	st_s r2,  [sp, ___isf_t_r2_OFFSET]
+	st_s r1,  [sp, ___isf_t_r1_OFFSET]
+	st_s r0,  [sp, ___isf_t_r0_OFFSET]
 
 	mov r0, lp_count
-	st_s r0, [sp, __tISF_lp_count_OFFSET]
+	st_s r0, [sp, ___isf_t_lp_count_OFFSET]
 	lr r1, [_ARC_V2_LP_START]
 	lr r0, [_ARC_V2_LP_END]
-	st_s r1, [sp, __tISF_lp_start_OFFSET]
-	st_s r0, [sp, __tISF_lp_end_OFFSET]
+	st_s r1, [sp, ___isf_t_lp_start_OFFSET]
+	st_s r0, [sp, ___isf_t_lp_end_OFFSET]
 
 .endm
 
@@ -125,29 +125,29 @@ extern "C" {
  */
 .macro _pop_irq_stack_frame
 
-	ld blink, [sp, __tISF_blink_OFFSET]
+	ld blink, [sp, ___isf_t_blink_OFFSET]
 
-	ld_s r0, [sp, __tISF_lp_count_OFFSET]
+	ld_s r0, [sp, ___isf_t_lp_count_OFFSET]
 	mov lp_count, r0
-	ld_s r1, [sp, __tISF_lp_start_OFFSET]
-	ld_s r0, [sp, __tISF_lp_end_OFFSET]
+	ld_s r1, [sp, ___isf_t_lp_start_OFFSET]
+	ld_s r0, [sp, ___isf_t_lp_end_OFFSET]
 	sr r1, [_ARC_V2_LP_START]
 	sr r0, [_ARC_V2_LP_END]
 
-	ld_s r13, [sp, __tISF_r13_OFFSET]
-	ld_s r12, [sp, __tISF_r12_OFFSET]
-	ld   r11, [sp, __tISF_r11_OFFSET]
-	ld   r10, [sp, __tISF_r10_OFFSET]
-	ld   r9,  [sp, __tISF_r9_OFFSET]
-	ld   r8,  [sp, __tISF_r8_OFFSET]
-	ld   r7,  [sp, __tISF_r7_OFFSET]
-	ld   r6,  [sp, __tISF_r6_OFFSET]
-	ld   r5,  [sp, __tISF_r5_OFFSET]
-	ld   r4,  [sp, __tISF_r4_OFFSET]
-	ld_s r3,  [sp, __tISF_r3_OFFSET]
-	ld_s r2,  [sp, __tISF_r2_OFFSET]
-	ld_s r1,  [sp, __tISF_r1_OFFSET]
-	ld_s r0,  [sp, __tISF_r0_OFFSET]
+	ld_s r13, [sp, ___isf_t_r13_OFFSET]
+	ld_s r12, [sp, ___isf_t_r12_OFFSET]
+	ld   r11, [sp, ___isf_t_r11_OFFSET]
+	ld   r10, [sp, ___isf_t_r10_OFFSET]
+	ld   r9,  [sp, ___isf_t_r9_OFFSET]
+	ld   r8,  [sp, ___isf_t_r8_OFFSET]
+	ld   r7,  [sp, ___isf_t_r7_OFFSET]
+	ld   r6,  [sp, ___isf_t_r6_OFFSET]
+	ld   r5,  [sp, ___isf_t_r5_OFFSET]
+	ld   r4,  [sp, ___isf_t_r4_OFFSET]
+	ld_s r3,  [sp, ___isf_t_r3_OFFSET]
+	ld_s r2,  [sp, ___isf_t_r2_OFFSET]
+	ld_s r1,  [sp, ___isf_t_r1_OFFSET]
+	ld_s r0,  [sp, ___isf_t_r0_OFFSET]
 
 	/*
 	 * All gprs have been reloaded, the only one that is still usable is
@@ -158,7 +158,7 @@ extern "C" {
 	 * status32 differently depending on the execution context they are running
 	 * in (_Swap(), firq or exception).
 	 */
-	add_s sp, sp, __tISF_SIZEOF
+	add_s sp, sp, ___isf_t_SIZEOF
 
 .endm
 

arch/arc/core/sys_fatal_error_handler.c

@@ -24,27 +24,8 @@
 #include <nanokernel.h>
 #include <toolchain.h>
 #include <sections.h>
-
-#ifdef CONFIG_PRINTK
+#include <kernel_structs.h>
 #include <misc/printk.h>
-#define PRINTK(...) printk(__VA_ARGS__)
-#else
-#define PRINTK(...)
-#endif
-
-#ifdef CONFIG_MICROKERNEL
-extern void _TaskAbort(void);
-static inline void nonEssentialTaskAbort(void)
-{
-	PRINTK("Fatal fault in task ! Aborting task.\n");
-	_TaskAbort();
-}
-#define NON_ESSENTIAL_TASK_ABORT() nonEssentialTaskAbort()
-#else
-#define NON_ESSENTIAL_TASK_ABORT() \
-	do {/* nothing */          \
-	} while ((0))
-#endif
 
 /**
  *
@@ -66,28 +47,20 @@ static inline void nonEssentialTaskAbort(void)
  *
  * @return N/A
  */
-void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF * pEsf)
+FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
+					 const NANO_ESF *pEsf)
 {
-	nano_context_type_t curCtx = sys_execution_context_type_get();
-
 	ARG_UNUSED(reason);
 	ARG_UNUSED(pEsf);
 
-	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential()) {
-		PRINTK("Fatal fault in %s ! Spinning...\n",
-		       NANO_CTX_ISR == curCtx
-			       ? "ISR"
-			       : NANO_CTX_FIBER == curCtx ? "essential fiber"
-							  : "essential task");
+	if (k_is_in_isr() || _is_thread_essential()) {
+		printk("Fatal fault in %s! Spinning...\n",
+		       k_is_in_isr() ? "ISR" : "essential thread");
 		for (;;)
 			; /* spin forever */
 	}
+	printk("Fatal fault in thread %p! Aborting.\n", _current);
+	k_thread_abort(_current);
 
-	if (NANO_CTX_FIBER == curCtx) {
-		PRINTK("Fatal fault in fiber ! Aborting fiber.\n");
-		fiber_abort();
-		return;
-	}
-
-	NON_ESSENTIAL_TASK_ABORT();
+	CODE_UNREACHABLE;
 }

arch/arc/core/thread.c

@@ -24,8 +24,8 @@
 
 #include <nanokernel.h>
 #include <toolchain.h>
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <wait_q.h>
 #ifdef CONFIG_INIT_STACKS
 #include <string.h>
@@ -40,46 +40,29 @@ struct init_stack_frame {
 	uint32_t r0;
 };
 
-tNANO _nanokernel = {0};
-
-#if defined(CONFIG_THREAD_MONITOR)
-#define THREAD_MONITOR_INIT(tcs) thread_monitor_init(tcs)
-#else
-#define THREAD_MONITOR_INIT(tcs) \
-	do {/* do nothing */     \
-	} while ((0))
-#endif
-
 #if defined(CONFIG_THREAD_MONITOR)
 /*
- * @brief Initialize thread monitoring support
- *
- * Currently only inserts the new thread in the list of active threads.
- *
- * @return N/A
+ * Add a thread to the kernel's list of active threads.
  */
-
-static ALWAYS_INLINE void thread_monitor_init(struct tcs *tcs)
+static ALWAYS_INLINE void thread_monitor_init(struct k_thread *thread)
 {
 	unsigned int key;
 
-	/*
-	 * Add the newly initialized thread to head of the list of threads.  This
-	 * singly linked list of threads maintains ALL the threads in the system:
-	 * both tasks and fibers regardless of whether they are runnable.
-	 */
-
 	key = irq_lock();
-	tcs->next_thread = _nanokernel.threads;
-	_nanokernel.threads = tcs;
+	thread->next_thread = _kernel.threads;
+	_kernel.threads = thread;
 	irq_unlock(key);
 }
+#else
+#define thread_monitor_init(thread) \
+	do {/* do nothing */     \
+	} while ((0))
 #endif /* CONFIG_THREAD_MONITOR */
 
 /*
  * @brief Initialize a new thread from its stack space
  *
- * The control structure (TCS) is put at the lower address of the stack. An
+ * The thread control structure is put at the lower address of the stack. An
  * initial context, to be "restored" by __return_from_coop(), is put at
  * the other end of the stack, and thus reusable by the stack when not
  * needed anymore.
@@ -96,20 +79,22 @@ static ALWAYS_INLINE void thread_monitor_init(struct tcs *tcs)
  * @param parameter1 first param to entry point
  * @param parameter2 second param to entry point
  * @param parameter3 third param to entry point
- * @param fiber priority, -1 for task
- * @param options is unused (saved for future expansion)
+ * @param priority thread priority
+ * @param options thread options: K_ESSENTIAL
  *
  * @return N/A
  */
-void _new_thread(char *pStackMem, unsigned stackSize,
-		 void *uk_task_ptr, _thread_entry_t pEntry,
+void _new_thread(char *pStackMem, size_t stackSize,
+		 _thread_entry_t pEntry,
 		 void *parameter1, void *parameter2, void *parameter3,
 		 int priority, unsigned options)
 {
+	_ASSERT_VALID_PRIO(priority, pEntry);
+
 	char *stackEnd = pStackMem + stackSize;
 	struct init_stack_frame *pInitCtx;
 
-	struct tcs *tcs = (struct tcs *) pStackMem;
+	struct k_thread *thread = (struct k_thread *) pStackMem;
 
 #ifdef CONFIG_INIT_STACKS
 	memset(pStackMem, 0xaa, stackSize);
@@ -134,32 +119,29 @@ void _new_thread(char *pStackMem, unsigned stackSize,
 	 */
 #ifdef CONFIG_ARC_STACK_CHECKING
 	pInitCtx->status32 = _ARC_V2_STATUS32_SC | _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
-	tcs->stack_top = (uint32_t) stackEnd;
+	thread->arch.stack_top = (uint32_t) stackEnd;
 #else
 	pInitCtx->status32 = _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
 #endif
-	tcs->link = NULL;
-	tcs->flags = priority == -1 ? TASK | PREEMPTIBLE : FIBER;
-	tcs->prio = priority;
+
+	_init_thread_base(&thread->base, priority, K_PRESTART, options);
+
+	/* static threads overwrite them afterwards with real values */
+	thread->init_data = NULL;
+	thread->fn_abort = NULL;
 
 #ifdef CONFIG_THREAD_CUSTOM_DATA
 	/* Initialize custom data field (value is opaque to kernel) */
 
-	tcs->custom_data = NULL;
+	thread->custom_data = NULL;
 #endif
 
 #ifdef CONFIG_THREAD_MONITOR
 	/*
-	 * In debug mode tcs->entry give direct access to the thread entry
+	 * In debug mode thread->entry give direct access to the thread entry
 	 * and the corresponding parameters.
 	 */
-	tcs->entry = (struct __thread_entry *)(pInitCtx);
-#endif
-
-#ifdef CONFIG_MICROKERNEL
-	tcs->uk_task_ptr = uk_task_ptr;
-#else
-	ARG_UNUSED(uk_task_ptr);
+	thread->entry = (struct __thread_entry *)(pInitCtx);
 #endif
 
 	/*
@@ -168,13 +150,12 @@ void _new_thread(char *pStackMem, unsigned stackSize,
 	 * dst[31:6] dst[5] dst[4]       dst[3:0]
 	 *    26'd0    1    STATUS32.IE  STATUS32.E[3:0]
 	 */
-	tcs->intlock_key = 0x3F;
-	tcs->relinquish_cause = _CAUSE_COOP;
-	tcs->preempReg.sp = (uint32_t)pInitCtx - __tCalleeSaved_SIZEOF;
+	thread->arch.intlock_key = 0x3F;
+	thread->arch.relinquish_cause = _CAUSE_COOP;
+	thread->callee_saved.sp =
+		(uint32_t)pInitCtx - ___callee_saved_stack_t_SIZEOF;
 
-	_nano_timeout_tcs_init(tcs);
+	/* initial values in all other regs/k_thread entries are irrelevant */
 
-	/* initial values in all other registers/TCS entries are irrelevant */
-
-	THREAD_MONITOR_INIT(tcs);
+	thread_monitor_init(thread);
 }

arch/arc/defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARC=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
-CONFIG_SOC_GENERIC_ARC=y
 CONFIG_CPU_ARCEM4=y
 CONFIG_CPU_ARCV2=y
 CONFIG_ARCV2_INTERRUPT_UNIT=y

arch/arc/include/kernel_arch_data.h

@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2014-2016 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Private kernel definitions
+ *
+ * This file contains private kernel structures definitions and various
+ * other definitions for the ARCv2 processor architecture.
+ *
+ * This file is also included by assembly language files which must #define
+ * _ASMLANGUAGE before including this header file.  Note that kernel
+ * assembly source files obtains structure offset values via "absolute
+ * symbols" in the offsets.o module.
+ */
+
+#ifndef _kernel_arch_data__h_
+#define _kernel_arch_data__h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <toolchain.h>
+#include <sections.h>
+#include <arch/cpu.h>
+#include <vector_table.h>
+
+#ifndef _ASMLANGUAGE
+#include <kernel.h>
+#include <nano_internal.h>
+#include <stdint.h>
+#include <misc/util.h>
+#include <misc/dlist.h>
+#endif
+
+#ifndef _ASMLANGUAGE
+
+struct _caller_saved {
+	/*
+	 * Saved on the stack as part of handling a regular IRQ or by the
+	 * kernel when calling the FIRQ return code.
+	 */
+};
+
+typedef struct _caller_saved _caller_saved_t;
+
+struct _irq_stack_frame {
+	uint32_t r0;
+	uint32_t r1;
+	uint32_t r2;
+	uint32_t r3;
+	uint32_t r4;
+	uint32_t r5;
+	uint32_t r6;
+	uint32_t r7;
+	uint32_t r8;
+	uint32_t r9;
+	uint32_t r10;
+	uint32_t r11;
+	uint32_t r12;
+	uint32_t r13;
+	uint32_t blink;
+	uint32_t lp_end;
+	uint32_t lp_start;
+	uint32_t lp_count;
+#ifdef CONFIG_CODE_DENSITY
+	/*
+	 * Currently unsupported. This is where those registers are
+	 * automatically pushed on the stack by the CPU when taking a regular
+	 * IRQ.
+	 */
+	uint32_t ei_base;
+	uint32_t ldi_base;
+	uint32_t jli_base;
+#endif
+	uint32_t pc;
+	uint32_t status32;
+};
+
+typedef struct _irq_stack_frame _isf_t;
+
+struct _callee_saved {
+	uint32_t sp; /* r28 */
+};
+typedef struct _callee_saved _callee_saved_t;
+
+/* callee-saved registers pushed on the stack, not in k_thread */
+struct _callee_saved_stack {
+	uint32_t r13;
+	uint32_t r14;
+	uint32_t r15;
+	uint32_t r16;
+	uint32_t r17;
+	uint32_t r18;
+	uint32_t r19;
+	uint32_t r20;
+	uint32_t r21;
+	uint32_t r22;
+	uint32_t r23;
+	uint32_t r24;
+	uint32_t r25;
+	uint32_t r26;
+	uint32_t fp; /* r27 */
+	/* r28 is the stack pointer and saved separately */
+	/* r29 is ILINK and does not need to be saved */
+	uint32_t r30;
+	/*
+	 * No need to save r31 (blink), it's either alread pushed as the pc or
+	 * blink on an irq stack frame.
+	 */
+};
+
+typedef struct _callee_saved_stack _callee_saved_stack_t;
+
+#endif /* _ASMLANGUAGE */
+
+/* stacks */
+
+#define STACK_ALIGN_SIZE 4
+
+#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
+#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
+
+/*
+ * Reason a thread has relinquished control: fibers can only be in the NONE
+ * or COOP state, tasks can be one in the four.
+ */
+#define _CAUSE_NONE 0
+#define _CAUSE_COOP 1
+#define _CAUSE_RIRQ 2
+#define _CAUSE_FIRQ 3
+
+#ifndef _ASMLANGUAGE
+
+struct _thread_arch {
+
+	/* interrupt key when relinquishing control */
+	uint32_t intlock_key;
+
+	/* one of the _CAUSE_xxxx definitions above */
+	int relinquish_cause;
+
+	/* return value from _Swap */
+	unsigned int return_value;
+
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* top of stack for hardware stack checking */
+	uint32_t stack_top;
+#endif
+};
+
+typedef struct _thread_arch _thread_arch_t;
+
+struct _kernel_arch {
+
+	char *rirq_sp; /* regular IRQ stack pointer base */
+
+	/*
+	 * FIRQ stack pointer is installed once in the second bank's SP, so
+	 * there is no need to track it in _kernel.
+	 */
+
+};
+
+typedef struct _kernel_arch _kernel_arch_t;
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _kernel_arch_data__h_ */

arch/arc/include/kernel_arch_func.h

@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2014-2016 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Private kernel definitions
+ *
+ * This file contains private kernel structures definitions and various
+ * other definitions for the ARCv2 processor architecture.
+ *
+ * This file is also included by assembly language files which must #define
+ * _ASMLANGUAGE before including this header file.  Note that kernel
+ * assembly source files obtains structure offset values via "absolute
+ * symbols" in the offsets.o module.
+ */
+
+#ifndef _kernel_arch_func__h_
+#define _kernel_arch_func__h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(_ASMLANGUAGE)
+
+#ifdef CONFIG_CPU_ARCV2
+#include <v2/cache.h>
+#include <v2/irq.h>
+#endif
+
+static ALWAYS_INLINE void nanoArchInit(void)
+{
+	_icache_setup();
+	_irq_setup();
+}
+
+static ALWAYS_INLINE void
+_set_thread_return_value(struct k_thread *thread, unsigned int value)
+{
+	thread->arch.return_value = value;
+}
+
+static ALWAYS_INLINE int _is_in_isr(void)
+{
+	uint32_t act = _arc_v2_aux_reg_read(_ARC_V2_AUX_IRQ_ACT);
+#if CONFIG_IRQ_OFFLOAD
+	/* Check if we're in a TRAP_S exception as well */
+	if (_arc_v2_aux_reg_read(_ARC_V2_STATUS32) & _ARC_V2_STATUS32_AE &&
+	    _ARC_V2_ECR_VECTOR(_arc_v2_aux_reg_read(_ARC_V2_ECR)) == EXC_EV_TRAP
+	   ) {
+		return 1;
+	}
+#endif
+	return ((act & 0xffff) != 0);
+}
+
+/**
+ *
+ * @bried Indicates the interrupt number of the highest priority
+ * active interrupt
+ *
+ * @return IRQ number
+ */
+static ALWAYS_INLINE int _INTERRUPT_CAUSE(void)
+{
+	uint32_t irq_num = _arc_v2_aux_reg_read(_ARC_V2_ICAUSE);
+
+	return irq_num;
+}
+
+
+extern void _thread_entry_wrapper(void);
+
+static inline void _IntLibInit(void)
+{
+	/* nothing needed, here because the kernel requires it */
+}
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _kernel_arch_func__h_ */

arch/arc/include/nano_private.h

@@ -1,304 +0,0 @@
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file
- * @brief Private nanokernel definitions
- *
- * This file contains private nanokernel structures definitions and various
- * other definitions for the ARCv2 processor architecture.
- *
- * This file is also included by assembly language files which must #define
- * _ASMLANGUAGE before including this header file.  Note that nanokernel
- * assembly source files obtains structure offset values via "absolute
- * symbols" in the offsets.o module.
- */
-
-#ifndef _NANO_PRIVATE_H
-#define _NANO_PRIVATE_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <toolchain.h>
-#include <sections.h>
-#include <arch/cpu.h>
-#include <vector_table.h>
-
-#ifndef _ASMLANGUAGE
-#include <nanokernel.h>            /* public nanokernel API */
-#include <../../../kernel/nanokernel/include/nano_internal.h>
-#include <stdint.h>
-#include <misc/util.h>
-#include <misc/dlist.h>
-#endif
-
-#ifndef _ASMLANGUAGE
-
-#ifdef CONFIG_THREAD_MONITOR
-struct __thread_entry {
-	_thread_entry_t pEntry;
-	void *parameter1;
-	void *parameter2;
-	void *parameter3;
-};
-#endif /*CONFIG_THREAD_MONITOR*/
-
-struct coop {
-	/*
-	 * Saved on the stack as part of handling a regular IRQ or by the kernel
-	 * when calling the FIRQ return code.
-	 */
-};
-
-struct irq_stack_frame {
-	uint32_t r0;
-	uint32_t r1;
-	uint32_t r2;
-	uint32_t r3;
-	uint32_t r4;
-	uint32_t r5;
-	uint32_t r6;
-	uint32_t r7;
-	uint32_t r8;
-	uint32_t r9;
-	uint32_t r10;
-	uint32_t r11;
-	uint32_t r12;
-	uint32_t r13;
-	uint32_t blink;
-	uint32_t lp_end;
-	uint32_t lp_start;
-	uint32_t lp_count;
-#ifdef CONFIG_CODE_DENSITY
-	/*
-	 * Currently unsupported. This is where those registers are automatically
-	 * pushed on the stack by the CPU when taking a regular IRQ.
-	 */
-	uint32_t ei_base;
-	uint32_t ldi_base;
-	uint32_t jli_base;
-#endif
-	uint32_t pc;
-	uint32_t status32;
-};
-
-typedef struct irq_stack_frame tISF;
-
-struct preempt {
-	uint32_t sp; /* r28 */
-};
-typedef struct preempt tPreempt;
-
-struct callee_saved {
-	uint32_t r13;
-	uint32_t r14;
-	uint32_t r15;
-	uint32_t r16;
-	uint32_t r17;
-	uint32_t r18;
-	uint32_t r19;
-	uint32_t r20;
-	uint32_t r21;
-	uint32_t r22;
-	uint32_t r23;
-	uint32_t r24;
-	uint32_t r25;
-	uint32_t r26;
-	uint32_t fp; /* r27 */
-	/* r28 is the stack pointer and saved separately */
-	/* r29 is ILINK and does not need to be saved */
-	uint32_t r30;
-	/*
-	 * No need to save r31 (blink), it's either alread pushed as the pc or
-	 * blink on an irq stack frame.
-	 */
-};
-typedef struct callee_saved tCalleeSaved;
-
-#endif /* _ASMLANGUAGE */
-
-/* Bitmask definitions for the struct tcs->flags bit field */
-
-#define FIBER          0x000
-#define TASK           0x001 /* 1 = task, 0 = fiber   */
-
-#define INT_ACTIVE     0x002 /* 1 = execution context is interrupt handler */
-#define EXC_ACTIVE     0x004 /* 1 = executino context is exception handler */
-#define USE_FP         0x010 /* 1 = thread uses floating point unit */
-#define PREEMPTIBLE    0x020 /* 1 = preemptible thread */
-#define ESSENTIAL      0x200 /* 1 = system thread that must not abort */
-#define NO_METRICS     0x400 /* 1 = _Swap() not to update task metrics */
-
-/* stacks */
-
-#define STACK_ALIGN_SIZE 4
-
-#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
-#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
-
-/*
- * Reason a thread has relinquished control: fibers can only be in the NONE
- * or COOP state, tasks can be one in the four.
- */
-#define _CAUSE_NONE 0
-#define _CAUSE_COOP 1
-#define _CAUSE_RIRQ 2
-#define _CAUSE_FIRQ 3
-
-#ifndef _ASMLANGUAGE
-
-struct tcs {
-	struct tcs *link;         /* node in singly-linked list
-				   * _nanokernel.fibers
-				   */
-	uint32_t flags;           /* bitmask of flags above */
-	uint32_t intlock_key;     /* interrupt key when relinquishing control */
-	int relinquish_cause;     /* one of the _CAUSE_xxxx definitions above */
-	unsigned int return_value;/* return value from _Swap */
-	int prio;                 /* fiber priority, -1 for a task */
-#ifdef CONFIG_THREAD_CUSTOM_DATA
-	void *custom_data;        /* available for custom use */
-#endif
-	struct coop coopReg;
-	struct preempt preempReg;
-#ifdef CONFIG_THREAD_MONITOR
-	struct __thread_entry *entry; /* thread entry and parameters description */
-	struct tcs *next_thread;  /* next item in list of ALL fiber+tasks */
-#endif
-#ifdef CONFIG_NANO_TIMEOUTS
-	struct _nano_timeout nano_timeout;
-#endif
-#ifdef CONFIG_ERRNO
-	int errno_var;
-#endif
-#ifdef CONFIG_ARC_STACK_CHECKING
-	uint32_t stack_top;
-#endif
-#ifdef CONFIG_MICROKERNEL
-	void *uk_task_ptr;
-#endif
-};
-
-struct s_NANO {
-	struct tcs *fiber;    /* singly linked list of runnable fibers */
-	struct tcs *task;     /* current task the nanokernel knows about */
-	struct tcs *current;  /* currently scheduled thread (fiber or task) */
-
-#ifdef CONFIG_THREAD_MONITOR
-	struct tcs *threads; /* singly linked list of ALL fiber+tasks */
-#endif
-
-#ifdef CONFIG_FP_SHARING
-	struct tcs *current_fp; /* thread (fiber or task) that owns the FP regs */
-#endif
-
-#ifdef CONFIG_SYS_POWER_MANAGEMENT
-	int32_t idle; /* Number of ticks for kernel idling */
-#endif
-
-	char *rirq_sp; /* regular IRQ stack pointer base */
-
-	/*
-	 * FIRQ stack pointer is installed once in the second bank's SP, so
-	 * there is no need to track it in _nanokernel.
-	 */
-
-#if defined(CONFIG_NANO_TIMEOUTS) || defined(CONFIG_NANO_TIMERS)
-	sys_dlist_t timeout_q;
-	int32_t task_timeout;
-#endif
-};
-
-typedef struct s_NANO tNANO;
-extern tNANO _nanokernel;
-
-#ifdef CONFIG_CPU_ARCV2
-#include <v2/cache.h>
-#include <v2/irq.h>
-#endif
-
-static ALWAYS_INLINE void nanoArchInit(void)
-{
-	_icache_setup();
-	_irq_setup();
-}
-
-/**
- *
- * @brief Set the return value for the specified fiber (inline)
- *
- * The register used to store the return value from a function call invocation
- * to <value>.  It is assumed that the specified <fiber> is pending, and thus
- * the fiber's thread is stored in its struct tcs structure.
- *
- * @return N/A
- */
-static ALWAYS_INLINE void fiberRtnValueSet(struct tcs *fiber, unsigned int value)
-{
-	fiber->return_value = value;
-}
-
-/**
- *
- * @brief Indicates if kernel is handling interrupt
- *
- * @return 1 if interrupt handler is executed, 0 otherwise
- */
-static ALWAYS_INLINE int _IS_IN_ISR(void)
-{
-	uint32_t act = _arc_v2_aux_reg_read(_ARC_V2_AUX_IRQ_ACT);
-#if CONFIG_IRQ_OFFLOAD
-	/* Check if we're in a TRAP_S exception as well */
-	if (_arc_v2_aux_reg_read(_ARC_V2_STATUS32) & _ARC_V2_STATUS32_AE &&
-	    _ARC_V2_ECR_VECTOR(_arc_v2_aux_reg_read(_ARC_V2_ECR)) == EXC_EV_TRAP) {
-		return 1;
-	}
-#endif
-	return ((act & 0xffff) != 0);
-}
-
-/**
- *
- * @bried Indicates the interrupt number of the highest priority
- * active interrupt
- *
- * @return IRQ number
- */
-static ALWAYS_INLINE int _INTERRUPT_CAUSE(void)
-{
-	uint32_t irq_num = _arc_v2_aux_reg_read(_ARC_V2_ICAUSE);
-
-	return irq_num;
-}
-
-
-extern void nanoCpuAtomicIdle(unsigned int);
-extern void _thread_entry_wrapper(void);
-
-static inline void _IntLibInit(void)
-{
-	/* nothing needed, here because the kernel requires it */
-}
-
-#endif /* _ASMLANGUAGE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _NANO_PRIVATE_H */

arch/arc/include/offsets_short_arch.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _offsets_short_arch__h_
+#define _offsets_short_arch__h_
+
+#include <offsets.h>
+
+/* kernel */
+
+/* nothing for now */
+
+/* end - kernel */
+
+/* threads */
+
+#define _thread_offset_to_intlock_key \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_intlock_key_OFFSET)
+
+#define _thread_offset_to_relinquish_cause \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_relinquish_cause_OFFSET)
+
+#define _thread_offset_to_return_value \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_return_value_OFFSET)
+
+#define _thread_offset_to_stack_top \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_stack_top_OFFSET)
+
+#define _thread_offset_to_sp \
+	(___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET)
+
+
+/* end - threads */
+
+#endif /* _offsets_short_arch__h_ */

arch/arc/include/start_task_arch.h

@@ -30,7 +30,7 @@
 #include <sections.h>
 
 #include <micro_private.h>
-#include <nano_private.h>
+#include <kernel_structs.h>
 #include <microkernel/task.h>
 
 #ifdef __cplusplus

arch/arc/include/v2/cache.h

@@ -16,10 +16,10 @@
 
 /**
  * @file
- * @brief Cache helper functions (ARC)
+ * @brief Cache helper functions and defines (ARC)
  *
- * This file contains private nanokernel structures definitions and various
- * other definitions for the ARCv2 processor architecture.
+ * This file contains cache related functions and definitions for the
+ * ARCv2 processor architecture.
  */
 
 #ifndef _ARCV2_CACHE__H_
@@ -33,28 +33,29 @@ extern "C" {
 
 #ifndef _ASMLANGUAGE
 
-#define CACHE_ENABLE 0x00
-#define CACHE_DISABLE 0x01
-#define CACHE_DIRECT 0x00
-#define CACHE_CACHE_CONTROLLED 0x20
+/* i-cache defines for IC_CTRL register */
+#define IC_CACHE_ENABLE   0x00
+#define IC_CACHE_DISABLE  0x01
+#define IC_CACHE_DIRECT   0x00
+#define IC_CACHE_INDIRECT 0x20
 
 /*
- * @brief Sets the I-cache
+ * @brief Initialize the I-cache
  *
- * Enables cache and sets the direct access.
+ * Enables the i-cache and sets it to direct access mode.
  */
 static ALWAYS_INLINE void _icache_setup(void)
 {
 	uint32_t icache_config = (
-		CACHE_DIRECT | /* direct mapping (one-way assoc.) */
-		CACHE_ENABLE   /* i-cache enabled */
+		IC_CACHE_DIRECT | /* direct mapping (one-way assoc.) */
+		IC_CACHE_ENABLE   /* i-cache enabled */
 	);
 	uint32_t val;
 
 	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
 	val &= 0xff;
-	if (val != 0) {
-		/* configure i-cache if present */
+	if (val != 0) { /* is i-cache present? */
+		/* configure i-cache */
 		_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
 	}
 }

arch/arc/include/v2/irq.h

@@ -31,12 +31,13 @@ extern "C" {
 
 #define _ARC_V2_AUX_IRQ_CTRL_BLINK (1 << 9)
 #define _ARC_V2_AUX_IRQ_CTRL_LOOP_REGS (1 << 10)
+#define _ARC_V2_AUX_IRQ_CTRL_LP (1 << 13)
 #define _ARC_V2_AUX_IRQ_CTRL_14_REGS 7
 #define _ARC_V2_AUX_IRQ_CTRL_16_REGS 8
 #define _ARC_V2_AUX_IRQ_CTRL_32_REGS 16
 
-#define _ARC_V2_DEF_IRQ_LEVEL 15
-#define _ARC_V2_WAKE_IRQ_LEVEL 15
+#define _ARC_V2_DEF_IRQ_LEVEL (CONFIG_NUM_IRQ_PRIO_LEVELS-1)
+#define _ARC_V2_WAKE_IRQ_LEVEL _ARC_V2_DEF_IRQ_LEVEL
 
 #ifndef _ASMLANGUAGE
 
@@ -59,7 +60,7 @@ static ALWAYS_INLINE void _irq_setup(void)
 	nano_cpu_sleep_mode = _ARC_V2_WAKE_IRQ_LEVEL;
 	_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_CTRL, aux_irq_ctrl_value);
 
-	_nanokernel.rirq_sp = _interrupt_stack + CONFIG_ISR_STACK_SIZE;
+	_kernel.irq_stack = _interrupt_stack + CONFIG_ISR_STACK_SIZE;
 	_firq_stack_setup();
 }
 

arch/arc/soc/em11d/Kconfig.defconfig

@@ -27,15 +27,13 @@ config NUM_IRQ_PRIO_LEVELS
 	# so this must be 2 for now.
 	default 2
 
-config NUM_REGULAR_IRQ_PRIO_LEVELS
-	# This processor supports 3 Regular Interrupt priority level (1-3).
-	# TODO: But regular irq nesting is not implemented -- so use 1.
-	default 1
-
 config NUM_IRQS
 	# must be > the highest interrupt number used
 	default 36
 
+config RGF_NUM_BANKS
+	default 2
+
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 20000000
 
@@ -50,11 +48,9 @@ config FLASH_SIZE
 	# em11d has no FLASH so size is 0.
 
 config SRAM_BASE_ADDRESS
-	default 0x10000000 if NSIM
 	default 0x10000000
 
 config SRAM_SIZE
-	default 131072 if NSIM
 	default 131072
 
 config ICCM_BASE_ADDRESS
@@ -69,6 +65,9 @@ config DCCM_BASE_ADDRESS
 config DCCM_SIZE
 	default 64
 
+config CACHE_FLUSHING
+	def_bool y
+
 if GPIO
 
 config GPIO_DW

arch/arc/soc/em11d/soc.c

@@ -43,4 +43,4 @@ static int em11d_arc_init(struct device *arg)
 	return 0;
 }
 
-SYS_INIT(em11d_arc_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+SYS_INIT(em11d_arc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em11d/soc.h

@@ -42,12 +42,6 @@
 #include <misc/util.h>
 #include <drivers/rand32.h>
 
-/* ARCv2 timer 0 configuration settings for the system clock */
-#ifdef CONFIG_NANOKERNEL
-#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 20000000 /* 20MHz reference clock */
-#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
-#endif /* CONFIG_NANOKERNEL */
-
 #define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
 #define CONFIG_ARCV2_TIMER0_INT_PRI 0
 
@@ -75,6 +69,7 @@
 #define GPIO_DW_0_IRQ                           22
 #define GPIO_DW_0_BITS                          32
 #define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
 
 #define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
 #define GPIO_DW_1_IRQ                           0          /* can't interrupt */
@@ -94,7 +89,7 @@
 /* undef GPIO_DW_IO_ACCESS .. because memory mapped */
 /* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
 /* undef CONFIG_GPIO_DW_CLOCK_GATE */
-/* undef CONFIG_SOC_QUARK_SE_SS */
+/* undef CONFIG_SOC_QUARK_SE_C1000_SS */
 
 /* SPI */
 
@@ -106,6 +101,8 @@
 #define SPI_DW_PORT_0_IRQ    25
 #define SPI_DW_PORT_1_IRQ    26
 
+#define SPI_DW_IRQ_FLAGS     0
+
 /*
  * SPI Chip Select Assignments on EM Starter Kit
  *
@@ -131,6 +128,7 @@
 #define UART_NS16550_PORT_1_IRQ				28
 #define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
 
+#define UART_IRQ_FLAGS					0 /* Default */
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _BOARD__H_ */

arch/arc/soc/em11d/soc_config.c

@@ -40,6 +40,6 @@ static int uart_ns16550_init(struct device *dev)
 	return 0;
 }
 
-SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
 
 #endif /* CONFIG_UART_NS16550 */

arch/arc/soc/em7d/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/arc/soc/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o

arch/arc/soc/em7d/Kconfig.defconfig

@@ -0,0 +1,259 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_EM7D
+
+config SOC
+	default em7d
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	# TODO: But regular irq nesting is not implemented --
+	# so this must be 2 for now.
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 36
+
+config RGF_NUM_BANKS
+	default 1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 30000000
+
+config HARVARD
+	def_bool n
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config FLASH_SIZE
+	default 0
+	# em7d has no FLASH so size is 0.
+
+config SRAM_BASE_ADDRESS
+	default 0x10000000
+
+config SRAM_SIZE
+	default 131072
+
+config ICCM_BASE_ADDRESS
+	default 0x00000000
+
+config ICCM_SIZE
+	default 256
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 128
+
+config CACHE_FLUSHING
+	def_bool y
+
+if GPIO
+
+config GPIO_DW
+	def_bool y
+
+if GPIO_DW
+
+config GPIO_DW_0
+	def_bool y
+
+if GPIO_DW_0
+
+config GPIO_DW_0_NAME
+	default "GPIO_PORTA"
+
+config GPIO_DW_0_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_0
+
+config GPIO_DW_1
+	def_bool y
+
+if GPIO_DW_1
+
+config GPIO_DW_1_NAME
+	default "GPIO_PORTB"
+
+config GPIO_DW_1_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_1
+
+config GPIO_DW_2
+	def_bool y
+
+if GPIO_DW_2
+
+config GPIO_DW_2_IRQ_PRI
+	default 1
+
+config GPIO_DW_2_NAME
+	default "GPIO_PORTC"
+
+endif # GPIO_DW_2
+
+config GPIO_DW_3
+	def_bool y
+
+if GPIO_DW_3
+
+config GPIO_DW_3_IRQ_PRI
+	default 1
+
+config GPIO_DW_3_NAME
+	default "GPIO_PORTD"
+
+endif # GPIO_DW_3
+
+endif # GPIO_DW
+
+endif # GPIO
+
+if I2C
+
+config I2C_CLOCK_SPEED
+	default 100
+
+config I2C_DW
+	def_bool y
+
+if I2C_DW
+
+config I2C_0
+	def_bool y
+
+if I2C_0
+
+config I2C_0_NAME
+	default "I2C_0"
+config I2C_0_DEFAULT_CFG
+	default 0x3
+config I2C_0_IRQ_PRI
+	default 1
+
+endif # I2C_0
+
+config I2C_1
+	def_bool y
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+config I2C_1_DEFAULT_CFG
+	default 0x3
+config I2C_1_IRQ_PRI
+	default 1
+
+endif # I2C_1
+
+endif # I2C_DW
+
+endif # I2C
+
+if UART_NS16550
+
+config UART_NS16550_PORT_0
+	def_bool n
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_NAME
+	default "UART_0"
+config UART_NS16550_PORT_0_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_0_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_NAME
+	default "UART_1"
+config UART_NS16550_PORT_1_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_1_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_1
+
+endif # UART_NS16550
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_DW
+	def_bool y
+
+if SPI_DW
+
+config SPI_DW_CLOCK_GATE
+	def_bool n
+
+config SPI_DW_FIFO_DEPTH
+	default 32
+
+config SPI_DW_ARC_AUX_REGS
+	def_bool n
+
+config SPI_0
+	def_bool y
+
+if SPI_0
+
+config SPI_0_IRQ_PRI
+	default 0
+
+endif # SPI_0
+
+config SPI_1
+	def_bool y
+
+if SPI_1
+
+config SPI_1_IRQ_PRI
+	default 0
+
+endif # SPI_1
+
+endif # SPI_DW
+
+endif # SPI
+
+endif #SOC_EM7D

arch/arc/soc/em7d/Kconfig.soc

@@ -0,0 +1,3 @@
+
+config SOC_EM7D
+	bool "Synopsys ARC EM7D"

arch/arc/soc/em7d/Makefile

@@ -0,0 +1,2 @@
+soc-cflags = $(call cc-option,-mARCv2EM) \
+                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)

arch/arc/soc/em7d/linker.ld

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit v2.2 EM7D platform.
+ */
+
+/*
+ * DRAM base address and size
+ *
+ * DRAM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
+/* TODO: Using SRAM config for now, even though this is really DRAM. */
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/em7d/soc.c

@@ -0,0 +1,46 @@
+/* soc.c - system/hardware module for em_starterkit BSP */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the ARC EM Starter kit board.
+ */
+
+#include <nanokernel.h>
+#include "soc.h"
+#include <init.h>
+
+
+/**
+ *
+ * @brief perform basic hardware initialization
+ *
+ * Hardware initialized:
+ * - interrupt unit
+ *
+ * RETURNS: N/A
+ */
+static int em7d_arc_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	_arc_v2_irq_unit_init();
+	return 0;
+}
+
+SYS_INIT(em7d_arc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em7d/soc.h

@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+
+
+/* IRQs */
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
+#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+
+#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/* I2C */
+
+/* I2C_0 is on Pmod2 connector */
+#define I2C_DW_0_BASE_ADDR                      0xF0004000
+#define I2C_DW_0_IRQ                            23
+
+
+/* I2C_1 is on Pmod4 connector */
+#define I2C_DW_1_BASE_ADDR                      0xF0005000
+#define I2C_DW_1_IRQ                            24
+
+#define I2C_DW_IRQ_FLAGS			0
+
+/* GPIO */
+#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ                           22
+#define GPIO_DW_0_BITS                          32
+#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
+
+#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_2_BITS                          32
+#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_3_BITS                          12
+#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+
+/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
+/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
+/* undef CONFIG_GPIO_DW_CLOCK_GATE */
+/* undef CONFIG_SOC_QUARK_SE_C1000_SS */
+
+/* SPI */
+
+#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+
+#define SPI_DW_PORT_0_REGS   0xF0006000
+#define SPI_DW_PORT_1_REGS   0xF0007000
+
+#define SPI_DW_PORT_0_IRQ    25
+#define SPI_DW_PORT_1_IRQ    26
+
+#define SPI_DW_IRQ_FLAGS     0
+
+/*
+ * SPI Chip Select Assignments on EM Starter Kit
+ *
+ *  CS0   Pmod6 - pin 1 - J6
+ *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
+ *  CS2   Pmod6 - pin 8 - J6
+ *  CS3   SDCard (onboard)
+ *  CS4   Internal SPI Slave - loopback
+ *  CS5   SPI-Flash (onboard)
+ */
+
+/*
+ * UART
+     UART0 vector 27 0xF0008000
+     UART1 vector 28 0xF0009000
+     UART2 vector 29 0xF000A000
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
+#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
+#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_IRQ_FLAGS					0 /* Default */
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/em7d/soc_config.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/em9d/Kconfig.defconfig

@@ -27,15 +27,13 @@ config NUM_IRQ_PRIO_LEVELS
 	# so this must be 2 for now.
 	default 2
 
-config NUM_REGULAR_IRQ_PRIO_LEVELS
-	# This processor supports 3 Regular Interrupt priority level (1-3).
-	# TODO: But regular irq nesting is not implemented -- so use 1.
-	default 1
-
 config NUM_IRQS
 	# must be > the highest interrupt number used
 	default 36
 
+config RGF_NUM_BANKS
+	default 2
+
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 20000000
 
@@ -50,11 +48,9 @@ config FLASH_SIZE
 	# em9d has no FLASH so size is 0.
 
 config SRAM_BASE_ADDRESS
-	default 0x00000000 if NSIM
 	default 0x00000000
 
 config SRAM_SIZE
-	default 0 if NSIM
 	default 0
 	# em9d has no SRAM so size is 0.
 

arch/arc/soc/em9d/linker.ld

@@ -36,5 +36,5 @@
 #define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
 #define DCCM_SIZE		CONFIG_DCCM_SIZE
 
-#include <arch/arc/v2/linker_harvard.ld>
+#include <arch/arc/v2/linker.ld>
 

arch/arc/soc/em9d/soc.c

@@ -43,4 +43,4 @@ static int em9d_arc_init(struct device *arg)
 	return 0;
 }
 
-SYS_INIT(em9d_arc_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+SYS_INIT(em9d_arc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em9d/soc.h

@@ -42,12 +42,6 @@
 #include <misc/util.h>
 #include <drivers/rand32.h>
 
-/* ARCv2 timer 0 configuration settings for the system clock */
-#ifdef CONFIG_NANOKERNEL
-#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 20000000 /* 20MHz reference clock */
-#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
-#endif /* CONFIG_NANOKERNEL */
-
 #define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
 #define CONFIG_ARCV2_TIMER0_INT_PRI 0
 
@@ -75,6 +69,7 @@
 #define GPIO_DW_0_IRQ                           22
 #define GPIO_DW_0_BITS                          32
 #define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
 
 #define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
 #define GPIO_DW_1_IRQ                           0          /* can't interrupt */
@@ -94,7 +89,7 @@
 /* undef GPIO_DW_IO_ACCESS .. because memory mapped */
 /* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
 /* undef CONFIG_GPIO_DW_CLOCK_GATE */
-/* undef CONFIG_SOC_QUARK_SE_SS */
+/* undef CONFIG_SOC_QUARK_SE_C1000_SS */
 
 /* SPI */
 
@@ -106,6 +101,8 @@
 #define SPI_DW_PORT_0_IRQ    25
 #define SPI_DW_PORT_1_IRQ    26
 
+#define SPI_DW_IRQ_FLAGS     0
+
 /*
  * SPI Chip Select Assignments on EM Starter Kit
  *
@@ -131,6 +128,7 @@
 #define UART_NS16550_PORT_1_IRQ				28
 #define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
 
+#define UART_IRQ_FLAGS					0 /* Default */
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _BOARD__H_ */

arch/arc/soc/em9d/soc_config.c

@@ -40,6 +40,6 @@ static int uart_ns16550_init(struct device *dev)
 	return 0;
 }
 
-SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
 
 #endif /* CONFIG_UART_NS16550 */

arch/arc/soc/quark_se_c1000_ss/Kbuild

@@ -0,0 +1,9 @@
+ccflags-y +=-I$(srctree)/arch/x86/soc/intel_quark
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+ccflags-$(CONFIG_ADC) +=-I$(srctree)/drivers/adc
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o power.o

arch/arc/soc/quark_se_c1000_ss/Kconfig

@@ -0,0 +1,28 @@
+#
+# Copyright (c) 2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if ARC && SOC_QUARK_SE_C1000_SS
+
+if IPM
+config QUARK_SE_SS_IPM_IRQ_PRI
+	int "IPM interrupt priority"
+	default 1
+	help
+	Priority level for interrupts coming in from the inter-processor
+	mailboxes.
+
+endif # IPM
+endif # SOC_QUARK_SE_C1000_SS

arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig

@@ -0,0 +1,270 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2015-2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_QUARK_SE_C1000_SS
+
+config SOC
+	default quark_se_c1000_ss
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports only 2 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 68
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 32000000
+
+config HARVARD
+	def_bool n
+
+config FLASH_BASE_ADDRESS
+	default 0x40000000
+
+config FLASH_SIZE
+	default 152
+
+config SRAM_BASE_ADDRESS
+	default 0x4000 if NSIM
+	default 0xa8000400
+
+config SRAM_SIZE
+	default 16 if NSIM
+	default 24
+
+config ICCM_BASE_ADDRESS
+	default 0xFFFFFFFF
+
+config ICCM_SIZE
+	default 0
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 8
+
+config QMSI
+	def_bool y
+
+config QMSI_BUILTIN
+	def_bool y
+
+if RTC
+
+config RTC_QMSI
+	def_bool y
+
+config RTC_0_IRQ_PRI
+	default 2
+
+endif # RTC
+
+if GPIO
+
+config GPIO_QMSI
+	def_bool y
+
+if GPIO_QMSI
+
+config GPIO_QMSI_0
+	def_bool y
+
+if GPIO_QMSI_0
+
+config GPIO_QMSI_0_IRQ_PRI
+	default 1
+
+endif # GPIO_QMSI_0
+
+config GPIO_QMSI_1
+	def_bool y
+
+if GPIO_QMSI_1
+
+config GPIO_QMSI_1_IRQ_PRI
+	default 1
+
+endif # GPIO_QMSI_1
+
+endif # GPIO_QMSI
+
+config GPIO_QMSI_SS
+	def_bool y
+
+if GPIO_QMSI_SS
+
+config GPIO_QMSI_SS_0
+	def_bool y
+
+if GPIO_QMSI_SS_0
+
+config GPIO_QMSI_SS_0_IRQ_PRI
+	default 1
+
+endif # GPIO_QMSI_SS_0
+
+config GPIO_QMSI_SS_1
+	def_bool y
+
+if GPIO_QMSI_SS_1
+
+config GPIO_QMSI_SS_1_IRQ_PRI
+	default 1
+
+endif # GPIO_QMSI_SS_1
+
+endif # GPIO_QMSI_SS
+
+endif # GPIO
+
+
+if I2C
+
+config I2C_QMSI_SS
+	def_bool y
+
+config I2C_0
+	def_bool y
+
+config I2C_0_NAME
+	default "I2C_0"
+
+config I2C_0_DEFAULT_CFG
+	default 0x12
+
+config I2C_0_IRQ_PRI
+	default 2
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+
+config I2C_1_DEFAULT_CFG
+	default 0x12
+
+config I2C_1_IRQ_PRI
+	default 2
+
+endif # I2C_1
+
+config I2C_SDA_SETUP
+	default 2
+
+config I2C_SS_SDA_HOLD
+	default 10
+
+endif # I2C
+
+if ADC
+config ADC_QMSI_SS
+	def_bool y
+endif
+
+
+if UART_QMSI
+config UART_QMSI_0
+	def_bool y
+
+if UART_QMSI_0
+
+config UART_QMSI_0_IRQ_PRI
+	default 3
+
+endif # UART_QMSI_0
+
+config UART_QMSI_1
+	def_bool y
+
+if UART_QMSI_1
+
+config UART_QMSI_1_IRQ_PRI
+	default 3
+
+endif # UART_QMSI_1
+
+endif # UART_QMSI
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_QMSI_SS
+	def_bool y
+
+config SPI_0
+	def_bool y
+
+config SPI_0_IRQ_PRI
+	default 1
+config SPI_1
+	def_bool y
+
+config SPI_1_IRQ_PRI
+	default 1
+endif # SPI
+
+if AIO_COMPARATOR
+
+config AIO_COMPARATOR_QMSI
+	def_bool y
+
+endif # AIO_COMPARATOR
+
+if WATCHDOG
+
+config WDT_QMSI
+	def_bool y
+
+config WDT_0_IRQ_PRI
+	default 2
+
+endif # WATCHDOG
+
+if DMA
+
+config DMA_QMSI
+	def_bool y
+
+endif # DMA
+
+if COUNTER
+
+config AON_COUNTER_QMSI
+	def_bool y
+
+config AON_TIMER_QMSI
+	def_bool y
+
+config AON_TIMER_IRQ_PRI
+	default 2
+
+endif # COUNTER
+
+endif #SOC_QUARK_SE_C1000_SS

arch/arc/soc/quark_se_c1000_ss/Kconfig.soc

@@ -0,0 +1,5 @@
+
+config SOC_QUARK_SE_C1000_SS
+	bool "Intel Quark SE C1000- Sensor Sub System"
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select HAS_QMSI

arch/arc/soc/quark_se_c1000_ss/Makefile

@@ -0,0 +1,8 @@
+soc-cflags = $(call cc-option,-mARCv2EM) \
+                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)
+soc-aflags = $(soc-cflags)
+soc-cxxflags = $(soc-cflags)
+soc-cflags += -DQM_SENSOR=1
+
+## FIXME
+SOC_SERIES = quark_se

arch/arc/soc/quark_se_c1000_ss/power.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2016 Intel Corporation.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <zephyr.h>
+#include <sys_io.h>
+#include <misc/__assert.h>
+#include <power.h>
+#include <soc_power.h>
+#include <init.h>
+#include <kernel_structs.h>
+
+#include "ss_power_states.h"
+
+#define SLEEP_MODE_CORE_OFF (0x0)
+#define SLEEP_MODE_CORE_TIMERS_RTC_OFF (0x60)
+#define ENABLE_INTERRUPTS (BIT(4) | _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL))
+
+#define ARC_SS1 (SLEEP_MODE_CORE_OFF | ENABLE_INTERRUPTS)
+#define ARC_SS2 (SLEEP_MODE_CORE_TIMERS_RTC_OFF | ENABLE_INTERRUPTS)
+
+/* QMSI does not set the interrupt enable bit in the sleep operand.
+ * For the time being, implement this in Zephyr.
+ * This will be removed once QMSI is fixed.
+ */
+static void enter_arc_state(int mode)
+{
+	/* Enter SSx */
+	__asm__ volatile("sleep %0"
+			: /* No output operands. */
+			: /* Input operands. */
+			"r"(mode));
+}
+
+void _sys_soc_set_power_state(enum power_states state)
+{
+	switch (state) {
+	case SYS_POWER_STATE_CPU_LPS:
+		ss_power_soc_lpss_enable();
+		enter_arc_state(ARC_SS2);
+		break;
+	case SYS_POWER_STATE_CPU_LPS_1:
+		enter_arc_state(ARC_SS2);
+		break;
+	case SYS_POWER_STATE_CPU_LPS_2:
+		enter_arc_state(ARC_SS1);
+		break;
+	case SYS_POWER_STATE_DEEP_SLEEP:
+	case SYS_POWER_STATE_DEEP_SLEEP_1:
+		/* Sleep states are not yet supported for ARC. */
+		break;
+	default:
+		break;
+	}
+}
+
+void _sys_soc_power_state_post_ops(enum power_states state)
+{
+	uint32_t limit;
+
+	switch (state) {
+	case SYS_POWER_STATE_CPU_LPS:
+		ss_power_soc_lpss_disable();
+	case SYS_POWER_STATE_CPU_LPS_1:
+		/* Expire the timer as it is disabled in SS2. */
+		limit = _arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT);
+		_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, limit - 1);
+		break;
+	default:
+		break;
+	}
+}

arch/arc/soc/quark_se_c1000_ss/soc.c

@@ -0,0 +1,48 @@
+/* system.c - system/hardware module for quark_se_ss BSP */
+
+/*
+ * Copyright (c) 2014-2015 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the Quark SE platform.
+ */
+
+#include <nanokernel.h>
+#include "soc.h"
+#include <init.h>
+#include <quark_se/shared_mem.h>
+
+
+/**
+ *
+ * @brief perform basic hardware initialization
+ *
+ * Hardware initialized:
+ * - interrupt unit
+ *
+ * RETURNS: N/A
+ */
+static int quark_se_arc_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	_arc_v2_irq_unit_init();
+	shared_data->flags |= ARC_READY;
+	return 0;
+}
+
+SYS_INIT(quark_se_arc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/quark_se_c1000_ss/soc.h

@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2014-2015 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Board configuration macros for Quark SE Sensor Subsystem
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the Quark SE Sensor Subsystem.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(32)
+
+/* address bases */
+
+#define SCSS_REGISTER_BASE 0xB0800000 /*Sensor Subsystem Base*/
+
+#define PERIPH_ADDR_BASE_ADC 0x80015000 /* ADC */
+
+#define PERIPH_ADDR_BASE_CREG_MST0 0x80018000 /* CREG Master 0 */
+#define PERIPH_ADDR_BASE_CREG_SLV0 0x80018080 /* CREG Slave 0 */
+#define PERIPH_ADDR_BASE_CREG_SLV1 0x80018180 /* CREG Slave 1 */
+
+#define PERIPH_ADDR_BASE_GPIO0 0x80017800 /* GPIO 0 */
+#define PERIPH_ADDR_BASE_GPIO1 0x80017900 /* GPIO 1 */
+
+#define PERIPH_ADDR_BASE_SPI_MST0 0x80010000 /* SPI Master 0 */
+#define PERIPH_ADDR_BASE_SPI_MST1 0x80010100 /* SPI Master 1 */
+
+/* IRQs */
+
+/* The CPU-visible IRQ numbers change between the ARC and IA cores,
+ * and QMSI itself has no easy way to pick the correct one, though it
+ * does have the necessary information to do it ourselves (in the meantime).
+ * This macro will be used by the shim drivers to get the IRQ number to
+ * use, and it should always be called using the QM_IRQ_*_INT macro
+ * provided by QMSI.
+ */
+#define IRQ_GET_NUMBER(_irq) _irq##_VECTOR
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+#define IRQ_I2C0_RX_AVAIL 18
+#define IRQ_I2C0_TX_REQ 19
+#define IRQ_I2C0_STOP_DET 20
+#define IRQ_I2C0_ERR 21
+#define IRQ_I2C1_RX_AVAIL 22
+#define IRQ_I2C1_TX_REQ 23
+#define IRQ_I2C1_STOP_DET 24
+#define IRQ_I2C1_ERR 25
+#define IRQ_SPI0_ERR_INT 30
+#define IRQ_SPI0_RX_AVAIL 31
+#define IRQ_SPI0_TX_REQ 32
+
+#define IRQ_SPI1_ERR_INT 33
+#define IRQ_SPI1_RX_AVAIL 34
+#define IRQ_SPI1_TX_REQ 35
+
+#define IRQ_ADC_ERR 18
+#define IRQ_ADC_IRQ 19
+#define IRQ_GPIO0_INTR 20
+#define IRQ_GPIO1_INTR 21
+#define IRQ_I2C_MST0_INTR 36
+#define IRQ_I2C_MST1_INTR 37
+#define IRQ_SPI_MST0_INTR 38
+#define IRQ_SPI_MST1_INTR 39
+#define IRQ_SPI_SLV_INTR 40
+#define IRQ_UART0_INTR 41
+#define IRQ_UART1_INTR 42
+#define IRQ_I2S_INTR 43
+#define IRQ_GPIO_INTR 44
+#define IRQ_PWM_TIMER_INTR 45
+#define IRQ_USB_INTR 46
+#define IRQ_RTC_INTR 47
+#define IRQ_WDOG_INTR 48
+#define IRQ_DMA_CHAN0 49
+#define IRQ_DMA_CHAN1 50
+#define IRQ_DMA_CHAN2 51
+#define IRQ_DMA_CHAN3 52
+#define IRQ_DMA_CHAN4 53
+#define IRQ_DMA_CHAN5 54
+#define IRQ_DMA_CHAN6 55
+#define IRQ_DMA_CHAN7 56
+#define IRQ_MAILBOXES_INTR 57
+#define IRQ_COMPARATORS_INTR 58
+#define IRQ_SYS_PMU_INTR 59
+#define IRQ_DMA_CHANS_ERR 60
+#define IRQ_INT_SRAM_CTLR 61
+#define IRQ_INT_FLASH0_CTLR 62
+#define IRQ_INT_FLASH1_CTLR 63
+#define IRQ_ALWAYS_ON_TMR 64
+#define IRQ_ADC_PWR 65
+#define IRQ_ADC_CALIB 66
+#define IRQ_ALWAYS_ON_GPIO 67
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/*
+ * I2C
+ */
+#define I2C_SS_0_ERR_VECTOR				22
+#define I2C_SS_0_ERR_MASK				0x410
+#define I2C_SS_0_RX_VECTOR				23
+#define I2C_SS_0_RX_MASK				0x414
+#define I2C_SS_0_TX_VECTOR				24
+#define I2C_SS_0_TX_MASK				0x418
+#define I2C_SS_0_STOP_VECTOR				25
+#define I2C_SS_0_STOP_MASK				0x41C
+
+#define I2C_SS_1_ERR_VECTOR				26
+#define I2C_SS_1_ERR_MASK				0x420
+#define I2C_SS_1_RX_VECTOR				27
+#define I2C_SS_1_RX_MASK				0x424
+#define I2C_SS_1_TX_VECTOR				28
+#define I2C_SS_1_TX_MASK				0x428
+#define I2C_SS_1_STOP_VECTOR				29
+#define I2C_SS_1_STOP_MASK				0x42C
+
+/*
+ * GPIO
+ */
+#define GPIO_DW_IO_ACCESS
+
+#define GPIO_DW_0_BASE_ADDR			0x80017800
+#define GPIO_DW_0_IRQ				20
+#define GPIO_DW_0_BITS				8
+#define GPIO_DW_PORT_0_INT_MASK			(SCSS_REGISTER_BASE + 0x408)
+
+#define GPIO_DW_1_BASE_ADDR			0x80017900
+#define GPIO_DW_1_IRQ				21
+#define GPIO_DW_1_BITS				8
+#define GPIO_DW_PORT_1_INT_MASK			(SCSS_REGISTER_BASE + 0x40C)
+
+#if defined(CONFIG_IOAPIC)
+#define GPIO_DW_0_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
+#define GPIO_DW_1_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
+#endif
+
+/*
+ * UART
+ */
+
+#define UART_IRQ_FLAGS                                  0
+
+#define UART_NS16550_PORT_0_BASE_ADDR			0xB0002000
+#define UART_NS16550_PORT_0_IRQ				41
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_0_INT_MASK			0x460
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xB0002400
+#define UART_NS16550_PORT_1_IRQ				42
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_1_INT_MASK			0x464
+
+/*
+ * SPI
+ */
+
+#define SPI_DW_PORT_0_REGS				0x80010000
+#define SPI_DW_PORT_1_REGS				0x80010100
+
+#define SPI_DW_PORT_0_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x430)
+#define SPI_DW_PORT_0_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x434)
+#define SPI_DW_PORT_0_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x438)
+
+#define SPI_DW_PORT_1_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x43C)
+#define SPI_DW_PORT_1_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x440)
+#define SPI_DW_PORT_1_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x444)
+
+#define SPI_DW_IRQ_FLAGS				0
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/quark_se_c1000_ss/soc_config.c

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+#if CONFIG_IPM_QUARK_SE
+#include <ipm.h>
+#include <ipm/ipm_quark_se.h>
+
+static int arc_quark_se_ipm_init(void)
+{
+	IRQ_CONNECT(QUARK_SE_IPM_INTERRUPT, CONFIG_QUARK_SE_SS_IPM_IRQ_PRI,
+		    quark_se_ipm_isr, NULL, 0);
+	irq_enable(QUARK_SE_IPM_INTERRUPT);
+	return 0;
+}
+
+static struct quark_se_ipm_controller_config_info ipm_controller_config = {
+	.controller_init = arc_quark_se_ipm_init
+};
+DEVICE_AND_API_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
+				NULL, &ipm_controller_config,
+				POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+				&ipm_quark_se_api_funcs);
+
+#if CONFIG_IPM_CONSOLE_SENDER
+#include <console/ipm_console.h>
+QUARK_SE_IPM_DEFINE(quark_se_ipm4, 4, QUARK_SE_IPM_OUTBOUND);
+
+static struct ipm_console_sender_config_info quark_se_ipm_sender_config = {
+	.bind_to = "quark_se_ipm4",
+	.flags = IPM_CONSOLE_PRINTK | IPM_CONSOLE_STDOUT,
+};
+DEVICE_INIT(ipm_console, "ipm_console", ipm_console_sender_init,
+				NULL, &quark_se_ipm_sender_config,
+				POST_KERNEL, CONFIG_IPM_CONSOLE_INIT_PRIORITY);
+
+#endif /* CONFIG_IPM_CONSOLE_SENDER */
+#endif /* CONFIG_IPM_QUARK_SE */
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_0_INT_MASK),
+		      INT_ENABLE_ARC_BIT_POS);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_1_INT_MASK),
+		      INT_ENABLE_ARC_BIT_POS);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/quark_se_c1000_ss/soc_power.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2016 Intel Corporation.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _SOC_POWER_H_
+#define _SOC_POWER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum power_states {
+	SYS_POWER_STATE_CPU_LPS,       /* SS2 with LPSS enabled state */
+	SYS_POWER_STATE_CPU_LPS_1,     /* SS2 state */
+	SYS_POWER_STATE_CPU_LPS_2,     /* SS1 state with Timer ON */
+	SYS_POWER_STATE_DEEP_SLEEP,    /* DEEP SLEEP state */
+	SYS_POWER_STATE_DEEP_SLEEP_1,  /* SLEEP state */
+	SYS_POWER_STATE_MAX
+};
+
+/**
+ * @brief Put processor into low power state
+ *
+ * This function implements the SoC specific details necessary
+ * to put the processor into available power states.
+ *
+ * Wake up considerations:
+ * -----------------------
+ *
+ * SYS_POWER_STATE_CPU_LPS_2: Any interrupt works as wake event.
+ *
+ * SYS_POWER_STATE_CPU_LPS_1: Any interrupt works as wake event except
+ * the ARC TIMER which is disabled.
+ *
+ * SYS_POWER_STATE_CPU_LPS: SYS_POWER_STATE_DEEP_SLEEP wake events applies.
+ *
+ * SYS_POWER_STATE_DEEP_SLEEP: Only Always-On peripherals can wake up
+ * the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.
+ *
+ * SYS_POWER_STATE_DEEP_SLEEP_1: Only Always-On peripherals can wake up
+ * the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.
+ *
+ * Considerations around SYS_POWER_STATE_CPU_LPS (LPSS state):
+ * -----------------------------------------------------------
+ *
+ * LPSS is a common power state between the x86 and ARC.
+ * When the two applications enter SYS_POWER_STATE_CPU_LPS,
+ * the SoC will enter this lower consumption mode.
+ * After wake up, this state can only be entered again
+ * if the ARC wakes up and transitions again to
+ * SYS_POWER_STATE_CPU_LPS. This is not required on the x86 side.
+ */
+void _sys_soc_set_power_state(enum power_states state);
+
+/**
+ * @brief Do any SoC or architecture specific post ops after low power states.
+ *
+ * This function is a place holder to do any operations that may
+ * be needed to be done after deep sleep exits.  Currently it enables
+ * interrupts after resuming from deep sleep. In future, the enabling
+ * of interrupts may be moved into the kernel.
+ */
+void _sys_soc_power_state_post_ops(enum power_states state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC_POWER_H_ */

arch/arc/soc/quark_se_ss/Kbuild

@@ -1,9 +0,0 @@
-ccflags-y +=-I$(srctree)/arch/x86/soc/
-ccflags-y +=-I$(srctree)/include
-ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/drivers
-ccflags-$(CONFIG_ADC) +=-I$(srctree)/drivers/adc
-
-asflags-y := ${ccflags-y}
-
-obj-y = soc.o soc_config.o

arch/arc/soc/quark_se_ss/Kconfig.defconfig

@@ -1,188 +0,0 @@
-#
-# Copyright (c) 2014 Wind River Systems, Inc.
-# Copyright (c) 2015-2016 Intel Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-
-if SOC_QUARK_SE_SS
-
-config SOC
-	default quark_se_ss
-
-config NUM_IRQ_PRIO_LEVELS
-	# This processor supports only 2 priority levels:
-	# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
-	default 2
-
-config NUM_REGULAR_IRQ_PRIO_LEVELS
-	# This processor supports only 1 Regular Interrupt priority level (1).
-	default 1
-
-config NUM_IRQS
-	# must be > the highest interrupt number used
-	default 68
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 32000000
-
-config HARVARD
-	def_bool n
-
-config FLASH_BASE_ADDRESS
-	default 0x40000000
-
-config FLASH_SIZE
-	default 152
-
-config SRAM_BASE_ADDRESS
-	default 0x4000 if NSIM
-	default 0xa8000400
-
-config SRAM_SIZE
-	default 16 if NSIM
-	default 24
-
-config ICCM_BASE_ADDRESS
-	default 0xFFFFFFFF
-
-config ICCM_SIZE
-	default 0
-
-config DCCM_BASE_ADDRESS
-	default 0x80000000
-
-config DCCM_SIZE
-	default 8
-
-config QMSI
-	def_bool y
-
-config QMSI_BUILTIN
-	def_bool y
-
-if GPIO
-
-config GPIO_QMSI_SS
-	def_bool y
-
-if GPIO_QMSI_SS
-
-config GPIO_QMSI_SS_0
-	def_bool y
-
-if GPIO_QMSI_SS_0
-
-config GPIO_QMSI_SS_0_PRI
-	default 1
-
-endif # GPIO_QMSI_SS_0
-
-config GPIO_QMSI_SS_1
-	def_bool y
-
-if GPIO_QMSI_SS_1
-
-config GPIO_QMSI_SS_1_PRI
-	default 1
-
-endif # GPIO_QMSI_SS_1
-
-endif # GPIO_QMSI_SS
-
-endif # GPIO
-
-
-if I2C
-
-config I2C_QMSI_SS
-	def_bool y
-
-config I2C_0
-	def_bool y
-
-config I2C_0_NAME
-	default "I2C_0"
-
-config I2C_0_DEFAULT_CFG
-	default 0x12
-
-config I2C_0_IRQ_PRI
-	default 2
-
-if I2C_1
-
-config I2C_1_NAME
-	default "I2C_1"
-
-config I2C_1_DEFAULT_CFG
-	default 0x12
-
-config I2C_1_IRQ_PRI
-	default 2
-
-endif # I2C_1
-
-
-endif # I2C
-
-
-if UART_QMSI
-config UART_QMSI_0
-	def_bool y
-
-if UART_QMSI_0
-
-config UART_QMSI_0_IRQ_PRI
-	default 3
-
-endif # UART_QMSI_0
-
-config UART_QMSI_1
-	def_bool y
-
-if UART_QMSI_1
-
-config UART_QMSI_1_IRQ_PRI
-	default 3
-
-endif # UART_QMSI_1
-
-endif # UART_QMSI
-
-if UART_CONSOLE
-
-config UART_CONSOLE_ON_DEV_NAME
-	default "UART_1"
-
-endif
-
-if SPI
-
-config SPI_QMSI_SS
-	def_bool y
-
-config SPI_0
-	def_bool y
-
-config SPI_0_IRQ_PRI
-	default 1
-config SPI_1
-	def_bool y
-
-config SPI_1_IRQ_PRI
-	default 1
-endif # SPI
-
-
-endif #SOC_QUARK_SE_ARC

arch/arc/soc/quark_se_ss/Kconfig.soc

@@ -1,5 +0,0 @@
-
-config SOC_QUARK_SE_SS
-	bool "Intel Quark SE - Sensor Sub System"
-	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
-	select HAS_QMSI

arch/arc/soc/quark_se_ss/Makefile

@@ -1,5 +0,0 @@
-soc-cflags = $(call cc-option,-mARCv2EM) \
-                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)
-soc-aflags = $(soc-cflags)
-soc-cxxflags = $(soc-cflags)
-soc-cflags += -DQM_SENSOR=1

arch/arc/soc/quark_se_ss/soc.c

@@ -1,48 +0,0 @@
-/* system.c - system/hardware module for quark_se_ss BSP */
-
-/*
- * Copyright (c) 2014-2015 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * This module provides routines to initialize and support board-level hardware
- * for the Quark SE platform.
- */
-
-#include <nanokernel.h>
-#include "soc.h"
-#include <init.h>
-#include <quark_se/shared_mem.h>
-
-
-/**
- *
- * @brief perform basic hardware initialization
- *
- * Hardware initialized:
- * - interrupt unit
- *
- * RETURNS: N/A
- */
-static int quark_se_arc_init(struct device *arg)
-{
-	ARG_UNUSED(arg);
-
-	_arc_v2_irq_unit_init();
-	shared_data->flags |= ARC_READY;
-	return 0;
-}
-
-SYS_INIT(quark_se_arc_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/quark_se_ss/soc.h

@@ -1,202 +0,0 @@
-/*
- * Copyright (c) 2014-2015 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @brief Board configuration macros for Quark SE Sensor Subsystem
- *
- * This header file is used to specify and describe board-level
- * aspects for the Quark SE Sensor Subsystem.
- */
-
-#ifndef _BOARD__H_
-#define _BOARD__H_
-
-#include <misc/util.h>
-
-/* default system clock */
-
-#define SYSCLK_DEFAULT_IOSC_HZ MHZ(32)
-
-/* address bases */
-
-#define SCSS_REGISTER_BASE 0xB0800000 /*Sensor Subsystem Base*/
-
-#define PERIPH_ADDR_BASE_ADC 0x80015000 /* ADC */
-
-#define PERIPH_ADDR_BASE_CREG_MST0 0x80018000 /* CREG Master 0 */
-#define PERIPH_ADDR_BASE_CREG_SLV0 0x80018080 /* CREG Slave 0 */
-#define PERIPH_ADDR_BASE_CREG_SLV1 0x80018180 /* CREG Slave 1 */
-
-#define PERIPH_ADDR_BASE_GPIO0 0x80017800 /* GPIO 0 */
-#define PERIPH_ADDR_BASE_GPIO1 0x80017900 /* GPIO 1 */
-
-#define PERIPH_ADDR_BASE_SPI_MST0 0x80010000 /* SPI Master 0 */
-#define PERIPH_ADDR_BASE_SPI_MST1 0x80010100 /* SPI Master 1 */
-
-/* IRQs */
-
-#define IRQ_TIMER0 16
-#define IRQ_TIMER1 17
-#define IRQ_I2C0_RX_AVAIL 18
-#define IRQ_I2C0_TX_REQ 19
-#define IRQ_I2C0_STOP_DET 20
-#define IRQ_I2C0_ERR 21
-#define IRQ_I2C1_RX_AVAIL 22
-#define IRQ_I2C1_TX_REQ 23
-#define IRQ_I2C1_STOP_DET 24
-#define IRQ_I2C1_ERR 25
-#define IRQ_SPI0_ERR_INT 30
-#define IRQ_SPI0_RX_AVAIL 31
-#define IRQ_SPI0_TX_REQ 32
-
-#define IRQ_SPI1_ERR_INT 33
-#define IRQ_SPI1_RX_AVAIL 34
-#define IRQ_SPI1_TX_REQ 35
-
-#define IRQ_ADC_ERR 18
-#define IRQ_ADC_IRQ 19
-#define IRQ_GPIO0_INTR 20
-#define IRQ_GPIO1_INTR 21
-#define IRQ_I2C_MST0_INTR 36
-#define IRQ_I2C_MST1_INTR 37
-#define IRQ_SPI_MST0_INTR 38
-#define IRQ_SPI_MST1_INTR 39
-#define IRQ_SPI_SLV_INTR 40
-#define IRQ_UART0_INTR 41
-#define IRQ_UART1_INTR 42
-#define IRQ_I2S_INTR 43
-#define IRQ_GPIO_INTR 44
-#define IRQ_PWM_TIMER_INTR 45
-#define IRQ_USB_INTR 46
-#define IRQ_RTC_INTR 47
-#define IRQ_WDOG_INTR 48
-#define IRQ_DMA_CHAN0 49
-#define IRQ_DMA_CHAN1 50
-#define IRQ_DMA_CHAN2 51
-#define IRQ_DMA_CHAN3 52
-#define IRQ_DMA_CHAN4 53
-#define IRQ_DMA_CHAN5 54
-#define IRQ_DMA_CHAN6 55
-#define IRQ_DMA_CHAN7 56
-#define IRQ_MAILBOXES_INTR 57
-#define IRQ_COMPARATORS_INTR 58
-#define IRQ_SYS_PMU_INTR 59
-#define IRQ_DMA_CHANS_ERR 60
-#define IRQ_INT_SRAM_CTLR 61
-#define IRQ_INT_FLASH0_CTLR 62
-#define IRQ_INT_FLASH1_CTLR 63
-#define IRQ_ALWAYS_ON_TMR 64
-#define IRQ_ADC_PWR 65
-#define IRQ_ADC_CALIB 66
-#define IRQ_ALWAYS_ON_GPIO 67
-
-#ifndef _ASMLANGUAGE
-
-#include <misc/util.h>
-#include <drivers/rand32.h>
-
-/* ARCv2 timer 0 configuration settings for the system clock */
-#ifdef CONFIG_NANOKERNEL
-#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 32000000 /* 32MHz reference clock \
-							*/
-#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
-#endif /* CONFIG_NANOKERNEL */
-
-#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
-#define CONFIG_ARCV2_TIMER0_INT_PRI 0
-
-#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
-#define CONFIG_ARCV2_TIMER1_INT_PRI 1
-
-#define INT_ENABLE_ARC					~(0x00000001 << 8)
-#define INT_ENABLE_ARC_BIT_POS				(8)
-
-/*
- * I2C
- */
-#define I2C_QUARK_SE_SS_0_BASE_ADDR			0x80012000
-#define I2C_SS_0_ERR_VECTOR				22
-#define I2C_SS_0_ERR_MASK				0x410
-#define I2C_SS_0_RX_VECTOR				23
-#define I2C_SS_0_RX_MASK				0x414
-#define I2C_SS_0_TX_VECTOR				24
-#define I2C_SS_0_TX_MASK				0x418
-#define I2C_SS_0_STOP_VECTOR				25
-#define I2C_SS_0_STOP_MASK				0x41C
-
-#define I2C_QUARK_SE_SS_1_BASE_ADDR			0x80012100
-#define I2C_SS_1_ERR_VECTOR				26
-#define I2C_SS_1_ERR_MASK				0x420
-#define I2C_SS_1_RX_VECTOR				27
-#define I2C_SS_1_RX_MASK				0x424
-#define I2C_SS_1_TX_VECTOR				28
-#define I2C_SS_1_TX_MASK				0x428
-#define I2C_SS_1_STOP_VECTOR				29
-#define I2C_SS_1_STOP_MASK				0x42C
-
-/*
- * GPIO
- */
-#define GPIO_DW_IO_ACCESS
-
-#define GPIO_DW_0_BASE_ADDR			0x80017800
-#define GPIO_DW_0_IRQ				20
-#define GPIO_DW_0_BITS				8
-#define GPIO_DW_PORT_0_INT_MASK			(SCSS_REGISTER_BASE + 0x408)
-
-#define GPIO_DW_1_BASE_ADDR			0x80017900
-#define GPIO_DW_1_IRQ				21
-#define GPIO_DW_1_BITS				8
-#define GPIO_DW_PORT_1_INT_MASK			(SCSS_REGISTER_BASE + 0x40C)
-
-#if defined(CONFIG_IOAPIC)
-#define GPIO_DW_0_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
-#define GPIO_DW_1_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
-#endif
-
-/*
- * UART
- */
-#define UART_NS16550_PORT_0_BASE_ADDR			0xB0002000
-#define UART_NS16550_PORT_0_IRQ				41
-#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
-#define UART_NS16550_PORT_0_INT_MASK			0x460
-
-#define UART_NS16550_PORT_1_BASE_ADDR			0xB0002400
-#define UART_NS16550_PORT_1_IRQ				42
-#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
-#define UART_NS16550_PORT_1_INT_MASK			0x464
-
-/*
- * SPI
- */
-
-#define SPI_DW_PORT_0_REGS				0x80010000
-#define SPI_DW_PORT_1_REGS				0x80010100
-
-#define SPI_DW_PORT_0_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x430)
-#define SPI_DW_PORT_0_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x434)
-#define SPI_DW_PORT_0_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x438)
-
-#define SPI_DW_PORT_1_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x43C)
-#define SPI_DW_PORT_1_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x440)
-#define SPI_DW_PORT_1_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x444)
-
-#define SPI_DW_IRQ_FLAGS				0
-
-#endif /* !_ASMLANGUAGE */
-
-#endif /* _BOARD__H_ */

arch/arc/soc/quark_se_ss/soc_config.c

@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2015 Intel Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <device.h>
-#include <init.h>
-#include "soc.h"
-
-#if CONFIG_IPM_QUARK_SE
-#include <ipm.h>
-#include <ipm/ipm_quark_se.h>
-
-static int arc_quark_se_ipm_init(void)
-{
-	IRQ_CONNECT(QUARK_SE_IPM_INTERRUPT, QUARK_SE_IPM_INTERRUPT_PRI,
-		    quark_se_ipm_isr, NULL, 0);
-	irq_enable(QUARK_SE_IPM_INTERRUPT);
-	return 0;
-}
-
-static struct quark_se_ipm_controller_config_info ipm_controller_config = {
-	.controller_init = arc_quark_se_ipm_init
-};
-DEVICE_AND_API_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
-				NULL, &ipm_controller_config,
-				SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-				&ipm_quark_se_api_funcs);
-
-#if CONFIG_IPM_CONSOLE_SENDER
-#include <console/ipm_console.h>
-QUARK_SE_IPM_DEFINE(quark_se_ipm4, 4, QUARK_SE_IPM_OUTBOUND);
-
-struct ipm_console_sender_config_info quark_se_ipm_sender_config = {
-	.bind_to = "quark_se_ipm4",
-	.flags = IPM_CONSOLE_PRINTK | IPM_CONSOLE_STDOUT,
-};
-DEVICE_INIT(ipm_console, "ipm_console", ipm_console_sender_init,
-				NULL, &quark_se_ipm_sender_config,
-				SECONDARY, CONFIG_IPM_CONSOLE_INIT_PRIORITY);
-
-#endif /* CONFIG_IPM_CONSOLE_SENDER */
-#endif /* CONFIG_IPM_QUARK_SE */
-
-#ifdef CONFIG_UART_NS16550
-
-static int uart_ns16550_init(struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-#ifdef CONFIG_UART_NS16550_PORT_0
-	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_0_INT_MASK),
-		      INT_ENABLE_ARC_BIT_POS);
-#endif /* CONFIG_UART_NS16550_PORT_0 */
-
-#ifdef CONFIG_UART_NS16550_PORT_1
-	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_1_INT_MASK),
-		      INT_ENABLE_ARC_BIT_POS);
-#endif /* CONFIG_UART_NS16550_PORT_1 */
-
-	return 0;
-}
-
-SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
-#endif /* CONFIG_UART_NS16550 */

arch/arm/Kconfig

@@ -37,7 +37,7 @@ config ARCH_DEFCONFIG
 
 source "arch/arm/core/Kconfig"
 
-menu "Platform Configuration"
+menu "Board Configuration"
 
 source "arch/arm/soc/*/Kconfig"
 

arch/arm/Makefile

@@ -14,20 +14,38 @@ cflags-cortex-m3 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m3) \
 			$(call cc-option,-mthumb -march=armv7-m)
 cflags-cortex-m4 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m4) \
 			$(call cc-option,-mthumb -march=armv7e-m)
-cflags-cortex-m7 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m7) \
-			$(call cc-option,-mthumb -march=armv7e-m)
+cflags-cortex-m7 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m7)
+
+ifeq ($(CONFIG_FLOAT), y)
+ifeq ($(CONFIG_FP_SOFTABI), y)
+cflags-cortex-m4 += $(call cc-option,-mfloat-abi=softfp -mfpu=fpv4-sp-d16)
+cflags-cortex-m7 += $(call cc-option,-mfloat-abi=softfp -mfpu=fpv5-d16)
+endif
+ifeq ($(CONFIG_FP_HARDABI), y)
+cflags-cortex-m4 += $(call cc-option,-mfloat-abi=hard -mfpu=fpv4-sp-d16)
+cflags-cortex-m7 += $(call cc-option,-mfloat-abi=hard -mfpu=fpv5-d16)
+endif
+endif
+
+aflags-$(CONFIG_CPU_CORTEX_M0) += $(cflags-cortex-m0)
+cflags-$(CONFIG_CPU_CORTEX_M0) += $(cflags-cortex-m0)
+cxxflags-$(CONFIG_CPU_CORTEX_M0) += $(cflags-cortex-m0)
+
+aflags-$(CONFIG_CPU_CORTEX_M0PLUS) += $(cflags-cortex-m0+)
+cflags-$(CONFIG_CPU_CORTEX_M0PLUS) += $(cflags-cortex-m0+)
+cxxflags-$(CONFIG_CPU_CORTEX_M0PLUS) += $(cflags-cortex-m0+)
 
 aflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
 cflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
 cxxflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
-_arm_isa-$(CONFIG_CPU_CORTEX_M3) = armv7-m
 
 aflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
 cflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
 cxxflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
-_arm_isa-$(CONFIG_CPU_CORTEX_M4) = armv7e-m
 
-_CROSS_COMPILE_arm_isa = $(_arm_isa-y)
+aflags-$(CONFIG_CPU_CORTEX_M7) += $(cflags-cortex-m7)
+cflags-$(CONFIG_CPU_CORTEX_M7) += $(cflags-cortex-m7)
+cxxflags-$(CONFIG_CPU_CORTEX_M7) += $(cflags-cortex-m7)
 
 KBUILD_AFLAGS += $(aflags-y)
 KBUILD_CFLAGS += $(cflags-y)

arch/arm/core/Kconfig

@@ -28,9 +28,72 @@ config CPU_CORTEX_M
 	# Omit prompt to signify "hidden" option
 	default n
 	select CPU_CORTEX
+	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
 	help
 	This option signifies the use of a CPU of the Cortex-M family.
 
+config CPU_HAS_SYSTICK
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	help
+	This option is enabled when the CPU has systick timer implemented.
+
+config CPU_HAS_FPU
+	# Hidden config selected by CPU family
+	bool
+	default n
+	help
+	This option is enabled when the CPU has a hardware floating point
+	unit.
+
+menu "Floating Point Options"
+depends on CPU_HAS_FPU
+
+config	FLOAT
+	bool
+	prompt "Floating point registers"
+	default n
+	help
+	This option allows tasks and fibers to use the floating point registers.
+	By default, only a single task or fiber may use the registers.
+
+	Disabling this option means that any task or fiber that uses a
+	floating point register will get a fatal exception.
+
+config	FP_SHARING
+	bool
+	prompt "Floating point register sharing"
+	depends on FLOAT
+	default n
+	help
+	This option allows multiple tasks and fibers to use the floating point
+	registers.
+
+choice
+	prompt "Floating point ABI"
+	default FP_HARDABI
+	depends on FLOAT
+
+config FP_HARDABI
+	bool "Floating point Hard ABI"
+	depends on FLOAT
+	help
+	This option selects the Floating point ABI in which hardware floating
+	point instructions are generated and uses FPU-specific calling
+	conventions
+
+config FP_SOFTABI
+	bool "Floating point Soft ABI"
+	depends on FLOAT
+	help
+	This option selects the Floating point ABI in which hardware floating
+	point instructions are generated but soft-float calling conventions.
+
+endchoice
+
+endmenu
+
 if CPU_CORTEX_M
 source "arch/arm/core/cortex_m/Kconfig"
 endif

arch/arm/core/Makefile

@@ -1,16 +1,14 @@
-ccflags-y += -I$(srctree)/kernel/nanokernel/include
-ccflags-y += -I$(srctree)/kernel/microkernel/include
-
+ccflags-y += -I$(srctree)/kernel/unified/include
 asflags-y := ${ccflags-y}
 
-obj-y = atomic.o exc_exit.o irq_init.o \
-	fiber_abort.o swap.o \
-	fault.o gdb_stub_irq_vector_table.o \
+obj-y = exc_exit.o irq_init.o \
+	swap.o \
+	fault.o \
 	irq_manage.o thread.o cpu_idle.o \
-	fault_s.o gdb_stub.o isr_wrapper.o \
-	fatal.o sys_fatal_error_handler.o
+	fault_s.o isr_wrapper.o \
+	fatal.o sys_fatal_error_handler.o thread_abort.o
 
+obj-$(CONFIG_GDB_INFO) += gdb_stub_irq_vector_table.o gdb_stub.o
 obj-$(CONFIG_CPLUSPLUS) += __aeabi_atexit.o
-obj-$(CONFIG_MICROKERNEL) += task_abort.o
 obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
 obj-$(CONFIG_CPU_CORTEX_M) += cortex_m/

arch/arm/core/atomic.S

@@ -1,415 +0,0 @@
-/*
- * Copyright (c) 2013-2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file
- * @brief ARM atomic operations library
- *
- * This library provides routines to perform a number of atomic operations
- * on a memory location: add, subtract, increment, decrement, bitwise OR,
- * bitwise NOR, bitwise AND, bitwise NAND, set, clear and compare-and-swap.
- */
-
-#define _ASMLANGUAGE
-
-#include <toolchain.h>
-#include <sections.h>
-
-_ASM_FILE_PROLOGUE
-
-/* exports */
-
-GTEXT(atomic_set)
-GTEXT(atomic_get)
-GTEXT(atomic_add)
-GTEXT(atomic_nand)
-GTEXT(atomic_and)
-GTEXT(atomic_or)
-GTEXT(atomic_xor)
-GTEXT(atomic_clear)
-GTEXT(atomic_dec)
-GTEXT(atomic_inc)
-GTEXT(atomic_sub)
-GTEXT(atomic_cas)
-
-/**
- *
- * @brief Atomically clear a memory location
- *
- * This routine atomically clears the contents of <target> and returns the old
- * value that was in <target>.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_clear
- *    (
- *    atomic_t *target	/@ memory location to clear @/
- *    )
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_clear_set, atomic_clear)
-	MOV	r1, #0
-	/* fall through into atomic_set */
-
-/**
- *
- * @brief Atomically set a memory location
- *
- * This routine atomically sets the contents of <target> to <value> and returns
- * the old value that was in <target>.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_set
- *    (
- *    atomic_t *target,	/@ memory location to set @/
- *    atomic_val_t value	/@ set with this value @/
- *    )
- *
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_clear_set, atomic_set)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	STREX	r12, r1, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-
-	BNE	atomic_set	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Get the value of a shared memory atomically
- *
- * This routine atomically retrieves the value in *target
- *
- * long atomic_get
- *     (
- *     atomic_t * target    /@ address of atom to be retrieved @/
- *     )
- *
- * RETURN: value read from address target.
- *
- */
-
-SECTION_FUNC(TEXT, atomic_get)
-	LDR	r0, [r0]
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically increment a memory location
- *
- * This routine atomically increments the value in <target>.  The operation is
- * done using unsigned integer arithmetic.  Various CPU architectures may impose
- * restrictions with regards to the alignment and cache attributes of the
- * atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_inc
- *    (
- *    atomic_t *target,	/@ memory location to increment @/
- *    )
- *
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_inc_add, atomic_inc)
-	MOV	r1, #1
-	/* fall through into atomic_add */
-
-/**
- *
- * @brief Atomically add a value to a memory location
- *
- * This routine atomically adds the contents of <target> and <value>, placing
- * the result in <target>. The operation is done using signed integer arithmetic.
- * Various CPU architectures may impose restrictions with regards to the
- * alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_add
- *    (
- *    atomic_t *target,	/@ memory location to add to @/
- *    atomic_val_t value	/@ value to add @/
- *    )
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_inc_add, atomic_add)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	ADD	r3, r2, r1	/* add word */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-
-	BNE	atomic_add	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically decrement a memory location
- *
- * This routine atomically decrements the value in <target>.  The operation is
- * done using unsigned integer arithmetic.  Various CPU architectures may impose
- * restrictions with regards to the alignment and cache attributes of the
- * atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_dec
- *    (
- *    atomic_t *target,	/@ memory location to decrement @/
- *    )
- *
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_decSub, atomic_dec)
-	MOV   r1, #1
-	/* fall through into atomic_sub */
-
-/**
- *
- * @brief Atomically subtract a value from a memory location
- *
- * This routine atomically subtracts <value> from the contents of <target>,
- * placing the result in <target>.  The operation is done using signed integer
- * arithmetic. Various CPU architectures may impose restrictions with regards to
- * the alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_sub
- *    (
- *    atomic_t *target,	/@ memory location to subtract from @/
- *    atomic_val_t value	/@ value to subtract @/
- *    )
- *
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_decSub, atomic_sub)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	SUB	r3, r2, r1	/* subtract word */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_sub	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically perform a bitwise NAND on a memory location
- *
- * This routine atomically performs a bitwise NAND operation of the contents of
- * <target> and <value>, placing the result in <target>.
- * Various CPU architectures may impose restrictions with regards to the
- * alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_nand
- *    (
- *    atomic_t *target,	/@ memory location to NAND @/
- *    atomic_val_t value	/@ NAND with this value @/
- *    )
- *
- */
-
-SECTION_FUNC(TEXT, atomic_nand)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	AND	r3, r2, r1	/* AND word */
-	MVN	r3, r3		/* invert */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_nand	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically perform a bitwise AND on a memory location
- *
- * This routine atomically performs a bitwise AND operation of the contents of
- * <target> and <value>, placing the result in <target>.
- * Various CPU architectures may impose restrictions with regards to the
- * alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_and
- *    (
- *    atomic_t *target,	/@ memory location to AND @/
- *    atomic_val_t value	/@ AND with this value @/
- *    )
- *
- */
-
-SECTION_FUNC(TEXT, atomic_and)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	AND	r3, r2, r1	/* AND word */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_and	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically perform a bitwise OR on memory location
- *
- * This routine atomically performs a bitwise OR operation of the contents of
- * <target> and <value>, placing the result in <target>.
- * Various CPU architectures may impose restrictions with regards to the
- * alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_or
- *    (
- *    atomic_t *target,	/@ memory location to OR @/
- *    atomic_val_t value	/@ OR with this value @/
- *    )
- *
- */
-
-SECTION_FUNC(TEXT, atomic_or)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	ORR	r3, r2, r1	/* OR word */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_or	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically perform a bitwise XOR on a memory location
- *
- * This routine atomically performs a bitwise XOR operation of the contents of
- * <target> and <value>, placing the result in <target>.
- * Various CPU architectures may impose restrictions with regards to the
- * alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_xor
- *    (
- *    atomic_t *target,	/@ memory location to XOR @/
- *    atomic_val_t value	/@ XOR with this value @/
- *    )
- *
- */
-
-SECTION_FUNC(TEXT, atomic_xor)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	EOR	r3, r2, r1	/* XOR word */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_xor	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically compare-and-swap the contents of a memory location
- *
- * This routine performs an atomic compare-and-swap. testing that the contents of
- * <target> contains <oldValue>, and if it does, setting the value of <target>
- * to <newValue>. Various CPU architectures may impose restrictions with regards
- * to the alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return 1 if the swap is actually executed, 0 otherwise.
- *
- * ERRNO: N/A
- *
- * int atomic_cas
- *    (
- *    atomic_t *target,	        /@ memory location to compare-and-swap @/
- *    atomic_val_t oldValue,	/@ compare to this value @/
- *    atomic_val_t newValue,	/@ swap with this value @/
- *    )
- *
- */
-
-SECTION_FUNC(TEXT, atomic_cas)
-
-	LDREX	r3, [r0]	/* load the value and mark exclusive access */
-	CMP	r3, r1		/* if (*target != oldValue) */
-	ITT NE
-	    MOVNE	r0, #0		/*     return FALSE */
-	    MOVNE	pc, lr
-	STREX	r12, r2, [r0]	/* try to store if equal */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_cas	/* if not, retry */
-
-	MOV	r0, #1		/* return TRUE if swap occurred */
-	MOV	pc, lr

arch/arm/core/cortex_m/Kconfig

@@ -45,14 +45,38 @@ config ISA_THUMB2
 	technology is featured in the  processor, and in all ARMv7
 	architecture-based processors.
 
+config CPU_CORTEX_M0_M0PLUS
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	select ATOMIC_OPERATIONS_C
+	select ISA_THUMB2
+	help
+	This option signifies the use of either a Cortex-M0 or Cortex-M0+ CPU.
+
 config CPU_CORTEX_M3_M4
 	bool
 	# Omit prompt to signify "hidden" option
 	default n
+	select ATOMIC_OPERATIONS_BUILTIN
 	select ISA_THUMB2
 	help
 	This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU.
 
+config CPU_CORTEX_M0
+	bool
+	# Omit prompt to signify "hidden" option
+	select CPU_CORTEX_M0_M0PLUS
+	help
+	This option signifies the use of a Cortex-M0 CPU
+
+config CPU_CORTEX_M0PLUS
+	bool
+	# Omit prompt to signify "hidden" option
+	select CPU_CORTEX_M0_M0PLUS
+	help
+	This option signifies the use of a Cortex-M0+ CPU
+
 config CPU_CORTEX_M3
 	bool
 	# Omit prompt to signify "hidden" option
@@ -67,6 +91,15 @@ config CPU_CORTEX_M4
 	help
 	This option signifies the use of a Cortex-M4 CPU
 
+config CPU_CORTEX_M7
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	select ATOMIC_OPERATIONS_BUILTIN
+	select ISA_THUMB2
+	help
+	This option signifies the use of a Cortex-M7 CPU
+
 menu "ARM Cortex-M options"
 	depends on CPU_CORTEX_M
 
@@ -79,7 +112,7 @@ config DATA_ENDIANNESS_LITTLE
 	default y
 	help
 	This is driven by the processor implementation, since it is fixed in
-	hardware. The platform should set this value to 'n' if the data is
+	hardware. The board should set this value to 'n' if the data is
 	implemented as big endian.
 
 config STACK_ALIGN_DOUBLE_WORD
@@ -92,16 +125,17 @@ config STACK_ALIGN_DOUBLE_WORD
 
 config NUM_IRQ_PRIO_BITS
 	int
-	#hidden option, implemented by platform
+	#hidden option, implemented by board
 	help
 	Cortex-M chips can implement up to 8 bits of interrupt priorities,
 	for a maximum of 256 priorities. Most chips implement fewer than 8.
 
-	The platform must define the correct value.
+	The board must define the correct value.
 
 config RUNTIME_NMI
 	bool
 	prompt "Attach an NMI handler at runtime"
+	select REBOOT
 	default n
 	help
 	The kernel provides a simple NMI handler that simply hangs in a tight
@@ -119,8 +153,10 @@ config FAULT_DUMP
 
 	2: The default. Display specific and verbose information. Consumes
 		the most memory (long strings).
+
 	1: Display general and short information. Consumes less memory
 		(short strings).
+
 	0: Off.
 
 config XIP
@@ -130,33 +166,33 @@ config SRAM_SIZE
 	int "SRAM Size in kB"
 	help
 	This option specifies the size of the SRAM in kB.  It is normally set by
-	the platform's defconfig file and the user should generally avoid modifying
+	the board's defconfig file and the user should generally avoid modifying
 	it via the menu configuration.
 
 config SRAM_BASE_ADDRESS
 	hex "SRAM Base Address"
 	help
-	This option specifies the base address of the SRAM on the platform.  It is
-	normally set by the platform's defconfig file and the user should generally
+	This option specifies the base address of the SRAM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
 	avoid modifying it via the menu configuration.
 
 config FLASH_SIZE
 	int "Flash Size in kB"
 	help
 	This option specifies the size of the flash in kB.  It is normally set by
-	the platform's defconfig file and the user should generally avoid modifying
+	the board's defconfig file and the user should generally avoid modifying
 	it via the menu configuration.
 
 config FLASH_BASE_ADDRESS
 	hex "Flash Base Address"
 	help
-	This option specifies the base address of the flash on the platform.  It is
-	normally set by the platform's defconfig file and the user should generally
+	This option specifies the base address of the flash on the board.  It is
+	normally set by the board's defconfig file and the user should generally
 	avoid modifying it via the menu configuration.
 endmenu
 
-menu "ARM Cortex-M3/M4 options"
-	depends on CPU_CORTEX_M3_M4
+menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
+	depends on CPU_CORTEX_M0_M0PLUS || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7
 
 config IRQ_OFFLOAD
 	bool "Enable IRQ offload"
@@ -176,26 +212,13 @@ config SW_ISR_TABLE
 	a parameter to be passed to the interrupt handlers. Also, invoking
 	the exeception/interrupt exit stub is automatically done.
 
-	This has to be enabled for dynamically connecting interrupt handlers
-	at runtime (SW_ISR_TABLE_DYNAMIC).
-
-config SW_ISR_TABLE_DYNAMIC
-	bool
-	prompt "Allow installing interrupt handlers at runtime"
-	depends on SW_ISR_TABLE
-	default n
-	help
-	This option enables irq_connect_dynamic(). It moves the ISR table to
-	SRAM so that it is writable. This has the side-effect of removing
-	write-protection on the ISR table.
-
 config IRQ_VECTOR_TABLE_CUSTOM
 	bool
 	prompt "Projects provide a custom static IRQ part of vector table"
 	depends on !SW_ISR_TABLE
 	default n
 	help
-	Projects, not the platform, provide the IRQ part of the vector table.
+	Projects, not the board, provide the IRQ part of the vector table.
 
 	This is the table of interrupt handlers with the best potential
 	performance, but is the less flexible.

arch/arm/core/cortex_m/Makefile

@@ -1,11 +1,12 @@
 ccflags-y +=-I$(srctree)/include/drivers
 ccflags-y +=-I$(srctree)/arch/arm/soc/$(SOC_PATH)
+ccflags-y +=-I$(srctree)/kernel/unified/include
 
 asflags-y = $(ccflags-y)
 
 obj-y = vector_table.o reset.o \
 	nmi_on_reset.o prep_c.o scs.o scb.o nmi.o \
-	exc_manage.o exc_wrapper.o
+	exc_manage.o
 
 obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o
 obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o

arch/arm/core/cortex_m/exc_manage.c

@@ -15,69 +15,34 @@
  */
 
 /**
- * @file dynamic exception management
+ * @file exception related routines
  */
 
-/* can only be used with non-XIP kernels, since they don't have their vector
- * table in the FLASH
- */
-#if !defined(CONFIG_XIP)
-
 #include <nanokernel.h>
 #include <arch/cpu.h>
-#include <misc/__assert.h>
-#include <toolchain.h>
-#include <sections.h>
-#include "vector_table.h"
-
-static inline int exc_can_be_connected(int num)
-{
-	static const uint16_t connectable_exceptions = (
-		(1 << _EXC_MPU_FAULT) |
-		(1 << _EXC_BUS_FAULT) |
-		(1 << _EXC_USAGE_FAULT) |
-		(1 << _EXC_DEBUG) |
-		0
-	);
-
-	return !!(connectable_exceptions & (1 << num));
-}
-
-/*
- * Can be initialized with garbage, it doesn't matter until the wrapper is
- * inserted in the vector table, at which point the relevant entry will contain
- * the pointer to the handler.
- */
-sys_exc_handler_t *_sw_exc_table[_NUM_EXC] __noinit;
-
-extern void _exc_wrapper(void);
-void sys_exc_connect(unsigned int num, sys_exc_handler_t *handler, void *unused)
-{
-	__ASSERT(exc_can_be_connected(num), "not a connectable exception");
-
-	_sw_exc_table[num] = handler;
-
-	/*
-	 * The compiler sets thumb bit (bit0) of the value of the _vector_table
-	 * symbol, probably because it is in the .text section: to get the correct
-	 * offset in the table, mask bit0.
-	 */
-	((void **)(((uint32_t)_vector_table) & 0xfffffffe))[num] = _exc_wrapper;
-}
-
-FUNC_ALIAS(sys_exc_connect, nanoCpuExcConnect, void);
+#include <inttypes.h>
 
 #include <misc/printk.h>
 void sys_exc_esf_dump(NANO_ESF *esf)
 {
-	printk("r0/a1:  %x  ", esf->a1);
-	printk("r1/a2:  %x  ", esf->a2);
-	printk("r2/a3:  %x\n", esf->a3);
-	printk("r3/a4:  %x  ", esf->a4);
-	printk("r12/ip: %x  ", esf->ip);
-	printk("r14/lr: %x\n", esf->lr);
-	printk("r15/pc: %x  ", esf->pc);
-	printk("xpsr:   %x\n", esf->xpsr);
+	printk("r0/a1:  %" PRIx32 "  ", esf->a1);
+	printk("r1/a2:  %" PRIx32 "  ", esf->a2);
+	printk("r2/a3:  %" PRIx32 "\n", esf->a3);
+	printk("r3/a4:  %" PRIx32 "  ", esf->a4);
+	printk("r12/ip: %" PRIx32 "  ", esf->ip);
+	printk("r14/lr: %" PRIx32 "\n", esf->lr);
+	printk("r15/pc: %" PRIx32 "  ", esf->pc);
+	printk("xpsr:   %" PRIx32 "\n", esf->xpsr);
+#ifdef CONFIG_FLOAT
+	for (int i = 0; i < 16; i += 4) {
+		printk("s[%d]:  %" PRIx32 "  s[%d]:  %" PRIx32 "  s[%d]:  %"
+		       PRIx32 "  s[%d]:  %" PRIx32 "\n",
+		       i, (uint32_t)esf->s[i],
+		       i + 1, (uint32_t)esf->s[i + 1],
+		       i + 2, (uint32_t)esf->s[i + 2],
+		       i + 3, (uint32_t)esf->s[i + 3]);
+	}
+	printk("fpscr:  %" PRIx32 "\n", esf->fpscr);
+#endif
 }
 
-#endif /* CONFIG_XIP */

arch/arm/core/cortex_m/exc_wrapper.S

@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2015 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file dynamic exception handler wrapper
- */
-
-#define _ASMLANGUAGE
-
-#include <toolchain.h>
-#include <arch/cpu.h>
-
-_ASM_FILE_PROLOGUE
-
-GDATA(_sw_exc_table)
-GTEXT(_exc_wrapper)
-
-SECTION_FUNC(TEXT, _exc_wrapper)
-
-	_GDB_STUB_EXC_ENTRY
-
-	ldr ip, =_SCS_ICSR
-	ldr ip, [ip]
-	ands.w ip, #_SCS_ICSR_RETTOBASE
-
-	itte eq			/* is the RETTOBASE bit zero ? */
-	mrseq r0, MSP	/* if so, we're not returning to thread mode, thus this
-					 * is a nested exception: the stack frame is on the MSP */
-	addeq.w r0, #4	/* ESF returned here is off by 4 because of the push {r2}
-					 * in_GDB_STUB_EXC_ENTRY */
-	mrsne r0, PSP	/* if not, we are returning to thread mode, thus this is
-					 * not a nested exception: the stack frame is on the PSP */
-
-	/* r0 now contains the pointer to the full ESF */
-
-	push {lr}	/* lr is now the first item on the stack */
-
-	ldr r1, =_sw_exc_table
-
-	mrs r2, IPSR	/* get exception number */
-
-	/* find and call handler: table is 4-bytes wide, shift index by 2 */
-	ldr r1, [r1, r2, LSL #2]
-	blx r1
-
-	pop {lr}
-
-	/* exception return is done in _ExcExit(), including _GDB_STUB_EXC_EXIT */
-	b _ExcExit
-
-	.end

arch/arm/core/cortex_m/nmi.c

@@ -26,6 +26,7 @@
 #include <nanokernel.h>
 #include <arch/cpu.h>
 #include <misc/printk.h>
+#include <misc/reboot.h>
 #include <toolchain.h>
 #include <sections.h>
 
@@ -51,7 +52,8 @@ static _NmiHandler_t handler = _SysNmiOnReset;
 static void _DefaultHandler(void)
 {
 	printk("NMI received! Rebooting...\n");
-	_ScbSystemReset();
+	/* In ARM implementation sys_reboot ignores the parameter */
+	sys_reboot(0);
 }
 
 /**

arch/arm/core/cortex_m/prep_c.c

@@ -30,53 +30,11 @@
 #include <stdint.h>
 #include <toolchain.h>
 #include <linker-defs.h>
-
-/**
- *
- * @brief Clear BSS
- *
- * This routine clears the BSS region, so all bytes are 0.
- *
- * @return N/A
- */
-
-static void bssZero(void)
-{
-	volatile uint32_t *pBSS = (uint32_t *)&__bss_start;
-	unsigned int n;
-
-	for (n = 0; n < (unsigned int)&__bss_num_words; n++) {
-		pBSS[n] = 0;
-	}
-}
-
-/**
- *
- * @brief Copy the data section from ROM to RAM
- *
- * This routine copies the data section from ROM to RAM.
- *
- * @return N/A
- */
+#include <nano_internal.h>
 
 #ifdef CONFIG_XIP
-static void dataCopy(void)
-{
-	volatile uint32_t *pROM = (uint32_t *)&__data_rom_start;
-	volatile uint32_t *pRAM = (uint32_t *)&__data_ram_start;
-	unsigned int n;
-
-	for (n = 0; n < (unsigned int)&__data_num_words; n++) {
-		pRAM[n] = pROM[n];
-	}
-}
-
 static inline void relocate_vector_table(void) { /* do nothing */ }
 #else
-static void dataCopy(void)
-{
-}
-
 static inline void relocate_vector_table(void)
 {
 	/* vector table is already in SRAM, just point to it */
@@ -84,6 +42,44 @@ static inline void relocate_vector_table(void)
 }
 #endif
 
+#ifdef CONFIG_FLOAT
+static inline void enable_floating_point(void)
+{
+	/*
+	 * Upon reset, the Co-Processor Access Control Register is 0x00000000.
+	 * Enable CP10 and CP11 coprocessors to enable floating point.
+	 */
+	__scs.cpacr.val = (_SCS_CPACR_CP10_FULL_ACCESS |
+				_SCS_CPACR_CP11_FULL_ACCESS);
+
+	/*
+	 * Upon reset, the FPU Context Control Register is 0xC0000000
+	 * (both Automatic and Lazy state preservation is enabled).
+	 * Disable lazy state preservation so the volatile FP registers are
+	 * always saved on exception.
+	 */
+	__scs.fpu.ccr.val = (_SCS_FPU_CCR_ASPEN_ENABLE |
+				_SCS_FPU_CCR_LSPEN_DISABLE);
+
+	/*
+	 * Although automatic state preservation is enabled, the processor
+	 * does not automatically save the volatile FP registers until they
+	 * have first been touched. Perform a dummy move operation so that
+	 * the stack frames are created as expected before any task or fiber
+	 * context switching can occur.
+	 */
+	__asm__ volatile(
+		"vmov s0, s0;\n\t"
+		"dsb;\n\t"
+		"isb;\n\t"
+		);
+}
+#else
+static inline void enable_floating_point(void)
+{
+}
+#endif
+
 extern FUNC_NORETURN void _Cstart(void);
 /**
  *
@@ -97,8 +93,9 @@ extern FUNC_NORETURN void _Cstart(void);
 void _PrepC(void)
 {
 	relocate_vector_table();
-	bssZero();
-	dataCopy();
+	enable_floating_point();
+	_bss_zero();
+	_data_copy();
 	_Cstart();
 	CODE_UNREACHABLE;
 }

arch/arm/core/cortex_m/reset.S

@@ -27,12 +27,14 @@
 #include <toolchain.h>
 #include <sections.h>
 #include <arch/cpu.h>
-#include <offsets.h>
+#include <offsets_short.h>
 #include "vector_table.h"
 
 _ASM_FILE_PROLOGUE
 
 GTEXT(__reset)
+GTEXT(memset)
+GDATA(_interrupt_stack)
 
 /**
  *
@@ -70,23 +72,36 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
 #endif
 
     /* lock interrupts: will get unlocked when switch to main task */
+#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
+    cpsid i
+#else /* CONFIG_CPU_CORTEX_M3_M4 */
     movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
     msr BASEPRI, r0
-
-    /*
-     * Set PSP and use it to boot without using MSP, so that it
-     * gets set to _interrupt_stack during nanoInit().
-     */
-    ldr r0, =__CORTEXM_BOOT_PSP
-    msr PSP, r0
-    movs.n r0, #2	/* switch to using PSP (bit1 of CONTROL reg) */
-    msr CONTROL, r0
+#endif
 
 #ifdef CONFIG_WDOG_INIT
     /* board-specific watchdog initialization is necessary */
     bl _WdogInit
 #endif
 
+#ifdef CONFIG_INIT_STACKS
+    ldr r0, =_interrupt_stack
+    ldr r1, =0xaa
+    ldr r2, =CONFIG_ISR_STACK_SIZE
+    bl memset
+#endif
+
+    /*
+     * Set PSP and use it to boot without using MSP, so that it
+     * gets set to _interrupt_stack during nanoInit().
+     */
+    ldr r0, =_interrupt_stack
+    ldr r1, =CONFIG_ISR_STACK_SIZE
+    adds r0, r0, r1
+    msr PSP, r0
+    movs.n r0, #2	/* switch to using PSP (bit1 of CONTROL reg) */
+    msr CONTROL, r0
+
     b _PrepC
 
 #if defined(CONFIG_SOC_TI_LM3S6965_QEMU)
@@ -124,7 +139,7 @@ SECTION_FUNC(TEXT,_force_exit_one_nested_irq)
 		ldrne r2, =_do_software_reboot
 
 	ldr ip, =_interrupt_stack
-	add.w ip, #(__tESF_SIZEOF * 2) /* enough for a stack frame */
+	add.w ip, #(___esf_t_SIZEOF * 2) /* enough for a stack frame */
 	ldr r1, =0xfffffffe
 	and.w r2, r1
 	str r2, [ip, #(6 * 4)]

arch/arm/core/cortex_m/vector_table.S

@@ -36,6 +36,8 @@
 
 _ASM_FILE_PROLOGUE
 
+GDATA(_main_stack)
+
 SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
 
 /* in XIP kernels. the entry point is also the start of the vector table */
@@ -43,11 +45,28 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
 SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
 #endif
 
-    .word __CORTEXM_BOOT_MSP
+    /*
+     * setting the _very_ early boot on the main stack allows to use memset
+     * on the interrupt stack when CONFIG_INIT_STACKS is enabled before
+     * switching to the interrupt stack for the rest of the early boot
+     */
+    .word _main_stack + CONFIG_MAIN_STACK_SIZE
+
     .word __reset
     .word __nmi
 
     .word __hard_fault
+#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
+    .word __reserved
+    .word __reserved
+    .word __reserved
+    .word __reserved
+    .word __reserved
+    .word __reserved
+    .word __reserved
+    .word __reserved	/* SVC not used for now (PendSV used instead) */
+    .word __reserved
+#else /* CONFIG_CPU_CORTEX_M3_M4 */
     .word __mpu_fault
     .word __bus_fault
     .word __usage_fault
@@ -57,6 +76,11 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
     .word __reserved
     .word __svc
     .word __debug_monitor
+#endif
     .word __reserved
     .word __pendsv
+#if defined(CONFIG_CORTEX_M_SYSTICK)
     .word _timer_int_handler
+#else
+    .word __reserved
+#endif

arch/arm/core/cortex_m/vector_table.h

@@ -42,21 +42,19 @@ extern "C" {
 #include <sections.h>
 #include <misc/util.h>
 
-/* location of MSP and PSP upon boot: at the end of SRAM */
-.equ __CORTEXM_BOOT_MSP, (CONFIG_SRAM_BASE_ADDRESS + KB(CONFIG_SRAM_SIZE) - 8)
-.equ __CORTEXM_BOOT_PSP, (__CORTEXM_BOOT_MSP - 0x100)
-
 GTEXT(__start)
 GTEXT(_vector_table)
 
 GTEXT(__reset)
 GTEXT(__nmi)
 GTEXT(__hard_fault)
+#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
 GTEXT(__mpu_fault)
 GTEXT(__bus_fault)
 GTEXT(__usage_fault)
 GTEXT(__svc)
 GTEXT(__debug_monitor)
+#endif
 GTEXT(__pendsv)
 GTEXT(__reserved)
 

arch/arm/core/cpu_idle.S

@@ -22,12 +22,12 @@
 
 #define _ASMLANGUAGE
 
-#include <offsets.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <sections.h>
 #include <arch/cpu.h>
 #ifdef CONFIG_TICKLESS_IDLE
-#include <nano_private.h>
+#include <kernel_structs.h>
 #endif
 
 _ASM_FILE_PROLOGUE
@@ -78,8 +78,8 @@ SECTION_FUNC(TEXT, _CpuIdleInit)
  */
 
 SECTION_FUNC(TEXT, _NanoIdleValGet)
-    ldr r0, =_nanokernel
-    ldr r0, [r0, #__tNANO_idle_OFFSET]
+    ldr r0, =_kernel
+    ldr r0, [r0, #_kernel_offset_to_idle]
     bx lr
 
 /**
@@ -96,9 +96,9 @@ SECTION_FUNC(TEXT, _NanoIdleValGet)
  */
 
 SECTION_FUNC(TEXT, _NanoIdleValClear)
-    ldr r0, =_nanokernel
+    ldr r0, =_kernel
     eors.n r1, r1
-    str r1, [r0, #__tNANO_idle_OFFSET]
+    str r1, [r0, #_kernel_offset_to_idle]
     bx lr
 
 #endif /* CONFIG_SYS_POWER_MANAGEMENT */
@@ -123,12 +123,17 @@ SECTION_FUNC(TEXT, nano_cpu_idle)
 #ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
 	push {lr}
 	bl    _sys_k_event_logger_enter_sleep
-	pop {lr}
+	pop {r0}
+	mov lr, r0
 #endif
 
+#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
+    cpsie i
+#else /* CONFIG_CPU_CORTEX_M3_M4 */
     /* clear BASEPRI so wfi is awakened by incoming interrupts */
     eors.n r0, r0
     msr BASEPRI, r0
+#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
 
     wfi
 
@@ -164,16 +169,10 @@ SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
 #ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
 	push {lr}
 	bl    _sys_k_event_logger_enter_sleep
-	pop {lr}
+	pop {r1}
+	mov lr, r1
 #endif
 
-    /*
-     * r0: interrupt mask from caller
-     * r1: zero, for setting BASEPRI (needs a register)
-     */
-
-    eors.n r1, r1
-
     /*
      * Lock PRIMASK while sleeping: wfe will still get interrupted by incoming
      * interrupts but the CPU will not service them right away.
@@ -185,6 +184,21 @@ SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
      * touched again.
      */
 
+     /* r0: interrupt mask from caller */
+
+#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
+    /* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
+    wfe
+
+    cmp r0, #0
+    bne _irq_disabled
+    cpsie i
+_irq_disabled:
+
+#else /* CONFIG_CPU_CORTEX_M3_M4 */
+    /* r1: zero, for setting BASEPRI (needs a register) */
+    eors.n r1, r1
+
     /* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
     msr BASEPRI, r1
 
@@ -192,4 +206,5 @@ SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
 
     msr BASEPRI, r0
     cpsie i
+#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS  */
     bx lr

arch/arm/core/exc_exit.S

@@ -16,7 +16,7 @@
 
 /**
  * @file
- * @brief ARM CORTEX-M3 exception/interrupt exit API
+ * @brief ARM CORTEX-M exception/interrupt exit API
  *
  *
  * Provides functions for performing kernel handling when exiting exceptions or
@@ -26,8 +26,8 @@
 
 #define _ASMLANGUAGE
 
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
 
@@ -35,15 +35,13 @@ _ASM_FILE_PROLOGUE
 
 GTEXT(_ExcExit)
 GTEXT(_IntExit)
-GDATA(_nanokernel)
+GDATA(_kernel)
+GTEXT(_is_next_thread_current)
 
 #if CONFIG_GDB_INFO
   #define _EXIT_EXC_IF_FIBER_PREEMPTED beq _ExcExitWithGdbStub
 #else
-  _EXIT_EXC_IF_FIBER_PREEMPTED:      .macro
-                                     it eq
-                                     bxeq lr
-                                     .endm
+  #define _EXIT_EXC_IF_FIBER_PREEMPTED beq _EXIT_EXC
 #endif
 #define _EXIT_EXC_IF_FIBER_NOT_READY _EXIT_EXC_IF_FIBER_PREEMPTED
 
@@ -90,17 +88,34 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _IntExit)
 
 SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _ExcExit)
 
-    ldr r1, =_nanokernel
+    ldr r1, =_kernel
 
-    /* is the current thread preemptible (task) ? */
-    ldr r2, [r1, #__tNANO_flags_OFFSET]
-    ands.w r2, #PREEMPTIBLE
-    _EXIT_EXC_IF_FIBER_PREEMPTED
+    ldr r1, [r1, #_kernel_offset_to_current]
+    ldr r2, [r1, #_thread_offset_to_prio]
+    ldr r3, [r1, #_thread_offset_to_sched_locked]
 
-    /* is there a fiber ready ? */
-    ldr r2, [r1, #__tNANO_fiber_OFFSET]
+    /* coop thread ? do not schedule */
     cmp r2, #0
-    _EXIT_EXC_IF_FIBER_NOT_READY
+    blt _EXIT_EXC
+
+    /* scheduler locked ? do not schedule */
+    cmp r3, #0
+    bgt _EXIT_EXC
+
+    push {lr}
+
+    /* _is_next_thread_current must be called with interrupts locked */
+    cpsid i
+    blx _is_next_thread_current
+    cpsie i
+#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
+    pop {r1}
+    mov lr, r1
+#else
+    pop {lr}
+#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS  */
+    cmp r0, #0
+    bne _EXIT_EXC
 
     /* context switch required, pend the PendSV exception */
     ldr r1, =_SCS_ICSR
@@ -111,4 +126,6 @@ _ExcExitWithGdbStub:
 
     _GDB_STUB_EXC_EXIT
 
+_EXIT_EXC:
+
     bx lr

arch/arm/core/fatal.c

@@ -23,9 +23,10 @@
 
 #include <toolchain.h>
 #include <sections.h>
+#include <inttypes.h>
 
 #include <nanokernel.h>
-#include <nano_private.h>
+#include <kernel_structs.h>
 
 #ifdef CONFIG_PRINTK
 #include <misc/printk.h>
@@ -47,6 +48,14 @@ const NANO_ESF _default_esf = {
 	{0xdeaddead}, /* r14/lr */
 	{0xdeaddead}, /* r15/pc */
 	 0xdeaddead,  /* xpsr */
+#ifdef CONFIG_FLOAT
+	{0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead,   /* s0 .. s3 */
+	 0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead,    /* s4 .. s7 */
+	 0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead,    /* s8 .. s11 */
+	 0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead},   /* s12 .. s15 */
+	0xdeaddead,  /* fpscr */
+	0xdeaddead,  /* undefined */
+#endif
 };
 
 /**
@@ -89,10 +98,9 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 		PR_EXC("**** Unknown Fatal Error %d! ****\n", reason);
 		break;
 	}
-	PR_EXC("Current thread ID = 0x%x\n"
-	       "Faulting instruction address = 0x%x\n",
-	       sys_thread_self_get(),
-	       pEsf->pc);
+	PR_EXC("Current thread ID = %p\n"
+	       "Faulting instruction address = 0x%" PRIx32 "\n",
+	       k_current_get(), pEsf->pc);
 
 	/*
 	 * Now that the error has been reported, call the user implemented

arch/arm/core/fault.c

@@ -25,7 +25,8 @@
 #include <sections.h>
 
 #include <nanokernel.h>
-#include <nano_private.h>
+#include <kernel_structs.h>
+#include <inttypes.h>
 
 #ifdef CONFIG_PRINTK
 #include <misc/printk.h>
@@ -63,13 +64,14 @@
  */
 void _FaultDump(const NANO_ESF *esf, int fault)
 {
-	int escalation = 0;
-
-	PR_EXC("Fault! EXC #%d, Thread: %x, instr @ %x\n",
+	PR_EXC("Fault! EXC #%d, Thread: %p, instr @ 0x%" PRIx32 "\n",
 	       fault,
-	       sys_thread_self_get(),
+	       k_current_get(),
 	       esf->pc);
 
+#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
+	int escalation = 0;
+
 	if (3 == fault) { /* hard fault */
 		escalation = _ScbHardFaultIsForced();
 		PR_EXC("HARD FAULT: %s\n",
@@ -77,19 +79,20 @@ void _FaultDump(const NANO_ESF *esf, int fault)
 				  : "Bus fault on vector table read\n");
 	}
 
-	PR_EXC("MMFSR: %x, BFSR: %x, UFSR: %x\n",
+	PR_EXC("MMFSR: 0x%" PRIx32 ", BFSR: 0x%" PRIx32 ", UFSR: 0x%"
+	       PRIx32 "\n",
 	       __scs.scb.cfsr.byte.mmfsr.val,
 	       __scs.scb.cfsr.byte.bfsr.val,
 	       __scs.scb.cfsr.byte.ufsr.val);
 
 	if (_ScbMemFaultIsMmfarValid()) {
-		PR_EXC("MMFAR: %x\n", _ScbMemFaultAddrGet());
+		PR_EXC("MMFAR: 0x%" PRIx32 "\n", _ScbMemFaultAddrGet());
 		if (escalation) {
 			_ScbMemFaultMmfarReset();
 		}
 	}
 	if (_ScbBusFaultIsBfarValid()) {
-		PR_EXC("BFAR: %x\n", _ScbBusFaultAddrGet());
+		PR_EXC("BFAR: 0x%" PRIx32 "\n", _ScbBusFaultAddrGet());
 		if (escalation) {
 			_ScbBusFaultBfarReset();
 		}
@@ -97,6 +100,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
 
 	/* clear USFR sticky bits */
 	_ScbUsageFaultAllFaultsReset();
+#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
 }
 #endif
 
@@ -111,12 +115,13 @@ void _FaultDump(const NANO_ESF *esf, int fault)
  */
 static void _FaultThreadShow(const NANO_ESF *esf)
 {
-	PR_EXC("  Executing thread ID (thread): 0x%x\n"
-	       "  Faulting instruction address:  0x%x\n",
-	       sys_thread_self_get(),
-	       esf->pc);
+	PR_EXC("  Executing thread ID (thread): %p\n"
+	       "  Faulting instruction address:  0x%" PRIx32 "\n",
+	       k_current_get(), esf->pc);
 }
 
+#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
+
 /**
  *
  * @brief Dump MPU fault information
@@ -138,7 +143,8 @@ static void _MpuFault(const NANO_ESF *esf, int fromHardFault)
 	} else if (_ScbMemFaultIsDataAccessViolation()) {
 		PR_EXC("  Data Access Violation\n");
 		if (_ScbMemFaultIsMmfarValid()) {
-			PR_EXC("  Address: 0x%x\n", _ScbMemFaultAddrGet());
+			PR_EXC("  Address: 0x%" PRIx32 "\n",
+			       _ScbMemFaultAddrGet());
 			if (fromHardFault) {
 				_ScbMemFaultMmfarReset();
 			}
@@ -169,7 +175,8 @@ static void _BusFault(const NANO_ESF *esf, int fromHardFault)
 	} else if (_ScbBusFaultIsPrecise()) {
 		PR_EXC("  Precise data bus error\n");
 		if (_ScbBusFaultIsBfarValid()) {
-			PR_EXC("  Address: 0x%x\n", _ScbBusFaultAddrGet());
+			PR_EXC("  Address: 0x%" PRIx32 "\n",
+			       _ScbBusFaultAddrGet());
 			if (fromHardFault) {
 				_ScbBusFaultBfarReset();
 			}
@@ -222,6 +229,21 @@ static void _UsageFault(const NANO_ESF *esf)
 	_ScbUsageFaultAllFaultsReset();
 }
 
+/**
+ *
+ * @brief Dump debug monitor exception information
+ *
+ * See _FaultDump() for example.
+ *
+ * @return N/A
+ */
+static void _DebugMonitor(const NANO_ESF *esf)
+{
+	PR_EXC("***** Debug monitor exception (not implemented) *****\n");
+}
+
+#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
+
 /**
  *
  * @brief Dump hard fault information
@@ -233,6 +255,10 @@ static void _UsageFault(const NANO_ESF *esf)
 static void _HardFault(const NANO_ESF *esf)
 {
 	PR_EXC("***** HARD FAULT *****\n");
+
+#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
+	_FaultThreadShow(esf);
+#else /* CONFIG_CPU_CORTEX_M3_M4 */
 	if (_ScbHardFaultIsBusErrOnVectorRead()) {
 		PR_EXC("  Bus fault on vector table read\n");
 	} else if (_ScbHardFaultIsForced()) {
@@ -245,19 +271,7 @@ static void _HardFault(const NANO_ESF *esf)
 			_UsageFault(esf);
 		}
 	}
-}
-
-/**
- *
- * @brief Dump debug monitor exception information
- *
- * See _FaultDump() for example.
- *
- * @return N/A
- */
-static void _DebugMonitor(const NANO_ESF *esf)
-{
-	PR_EXC("***** Debug monitor exception (not implemented) *****\n");
+#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
 }
 
 /**
@@ -300,6 +314,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
 	case 3:
 		_HardFault(esf);
 		break;
+#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
 	case 4:
 		_MpuFault(esf, 0);
 		break;
@@ -312,6 +327,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
 	case 12:
 		_DebugMonitor(esf);
 		break;
+#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
 	default:
 		_ReservedException(esf, fault);
 		break;

arch/arm/core/fault_s.S

@@ -32,10 +32,12 @@ _ASM_FILE_PROLOGUE
 GTEXT(_Fault)
 
 GTEXT(__hard_fault)
+#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
 GTEXT(__mpu_fault)
 GTEXT(__bus_fault)
 GTEXT(__usage_fault)
 GTEXT(__debug_monitor)
+#endif
 GTEXT(__reserved)
 
 /**
@@ -62,14 +64,32 @@ GTEXT(__reserved)
  */
 
 SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault)
+#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__usage_fault)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__debug_monitor)
+#endif
 SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved)
 
     _GDB_STUB_EXC_ENTRY
 
+#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
+    /* force unlock interrupts */
+    cpsie i
+
+    /* Use EXC_RETURN state to find out if stack frame is on the MSP or PSP */
+    ldr r0, =0x4
+    mov r1, lr
+    tst r1, r0
+    beq _stack_frame_msp
+    mrs r0, PSP
+    bne _stack_frame_endif
+_stack_frame_msp:
+    mrs r0, MSP
+_stack_frame_endif:
+
+#else /* CONFIG_CPU_CORTEX_M3_M4 */
     /* force unlock interrupts */
     eors.n r0, r0
     msr BASEPRI, r0
@@ -84,6 +104,7 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved)
 					 * is a nested exception: the stack frame is on the MSP */
 	mrsne r0, PSP	/* if not, we are returning to thread mode, thus this is
 					 * not a nested exception: the stack frame is on the PSP */
+#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
 
     push {lr}
     bl _Fault

arch/arm/core/fiber_abort.c

@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file
- * @brief ARM Cortex-M fiber_abort() routine
- *
- * The ARM Cortex-M architecture provides its own fiber_abort() to deal with
- * different CPU modes (handler vs thread) when a fiber aborts. When its entry
- * point returns or when it aborts itself, the CPU is in thread mode and must
- * call _Swap() (which triggers a service call), but when in handler mode, the
- * CPU must exit handler mode to cause the context switch, and thus must queue
- * the PendSV exception.
- */
-
-#ifdef CONFIG_MICROKERNEL
-#include <microkernel.h>
-#include <micro_private_types.h>
-#endif
-
-#include <nano_private.h>
-#include <toolchain.h>
-#include <sections.h>
-#include <nanokernel.h>
-#include <arch/cpu.h>
-
-/**
- *
- * @brief Abort the currently executing fiber
- *
- * Possible reasons for a fiber aborting:
- *
- * - the fiber explicitly aborts itself by calling this routine
- * - the fiber implicitly aborts by returning from its entry point
- * - the fiber encounters a fatal exception
- *
- * @return N/A
- */
-
-void fiber_abort(void)
-{
-	_thread_exit(_nanokernel.current);
-	if (_ScbIsInThreadMode()) {
-		_nano_fiber_swap();
-	} else {
-		_ScbPendsvSet();
-	}
-}