release: bump version to Zephyr 2.2.1

Update version to 2.2.1

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>

.editorconfig

@@ -9,6 +9,7 @@ charset = utf-8
 end_of_line = lf
 insert_final_newline = true
 trim_trailing_whitespace = true
+max_line_length = 80
 
 # C
 [*.{c,h}]

.github/workflows/doc-build.yml

@@ -30,8 +30,8 @@ jobs:
     - name: install-pip
       run: |
         pip3 install setuptools
-        pip3 install 'breathe>=4.9.1' 'docutils>=0.14' \
-                     'sphinx>=1.7.5' sphinx_rtd_theme sphinx-tabs \
+        pip3 install 'breathe>=4.9.1,<4.15.0' 'docutils>=0.14' \
+                     'sphinx>=1.7.5,<3.0' sphinx_rtd_theme sphinx-tabs \
                      sphinxcontrib-svg2pdfconverter 'west>=0.6.2'
         pip3 install pyelftools
 

.github/workflows/doc-publish.yml

@@ -61,8 +61,8 @@ jobs:
     - name: install-pip
       run: |
         pip3 install setuptools
-        pip3 install 'breathe>=4.9.1' 'docutils>=0.14' \
-                     'sphinx>=1.7.5' sphinx_rtd_theme sphinx-tabs \
+        pip3 install 'breathe>=4.9.1,<4.15.0' 'docutils>=0.14' \
+                     'sphinx>=1.7.5,<3.0' sphinx_rtd_theme sphinx-tabs \
                      sphinxcontrib-svg2pdfconverter 'west>=0.6.2'
         pip3 install pyelftools
 

CODEOWNERS

@@ -347,7 +347,7 @@
 /samples/                                 @nashif
 /samples/basic/minimal/                   @carlescufi
 /samples/basic/servo_motor/*microbit*     @jhe
-/lib/updatehub/                           @chtavares592 @otavio
+/lib/updatehub/                           @nandojve @otavio
 /samples/bluetooth/                       @jhedberg @Vudentz @joerchan
 /samples/boards/intel_s1000_crb/          @sathishkuttan @dcpleung @nashif
 /samples/display/                         @vanwinkeljan
@@ -361,7 +361,7 @@
 /samples/net/mqtt_publisher/              @jukkar @tbursztyka
 /samples/net/sockets/coap_*/              @rveerama1
 /samples/net/sockets/                     @jukkar @tbursztyka @pfalcon
-/samples/net/updatehub/                   @chtavares592 @otavio
+/samples/net/updatehub/                   @nandojve @otavio
 /samples/sensor/                          @MaureenHelm
 /samples/shields/                         @avisconti
 /samples/subsys/logging/                  @nordic-krch @jakub-uC

VERSION

@@ -1,5 +1,5 @@
 VERSION_MAJOR = 2
 VERSION_MINOR = 2
-PATCHLEVEL = 0
+PATCHLEVEL = 1
 VERSION_TWEAK = 0
-EXTRAVERSION = rc2
+EXTRAVERSION =

arch/arc/core/fault_s.S

@@ -206,7 +206,7 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	/* do sys_call */
 	mov_s ilink, K_SYSCALL_LIMIT
 	cmp r6, ilink
-	blt valid_syscall_id
+	blo valid_syscall_id
 
 	mov_s r0, r6
 	mov_s r6, K_SYSCALL_BAD

arch/arm/core/aarch32/cortex_m/mpu/Kconfig

@@ -16,7 +16,7 @@ config ARM_MPU
 	  MCU implements Memory Protection Unit.
 
 	  Notes:
-	  The ARMv6-M and ARMv8-M MPU architecture requires a power-of-two
+	  The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
 	  alignment of MPU region base address and size.
 
 	  The NXP MPU as well as the ARMv8-M MPU do not require MPU regions

arch/arm/core/aarch32/cortex_m/mpu/arm_mpu_v7_internal.h

@@ -9,6 +9,8 @@
 #define ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_
 
 
+#include <sys/math_extras.h>
+
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
 #include <logging/log.h>
 
@@ -200,6 +202,7 @@ static inline int is_in_region(u32_t r_index, u32_t start, u32_t size)
 	u32_t r_addr_start;
 	u32_t r_size_lshift;
 	u32_t r_addr_end;
+	u32_t end;
 
 	/* Lock IRQs to ensure RNR value is correct when reading RBAR, RASR. */
 	unsigned int key;
@@ -216,7 +219,12 @@ static inline int is_in_region(u32_t r_index, u32_t start, u32_t size)
 			MPU_RASR_SIZE_Pos) + 1;
 	r_addr_end = r_addr_start + (1UL << r_size_lshift) - 1;
 
-	if (start >= r_addr_start && (start + size - 1) <= r_addr_end) {
+	size = size == 0 ? 0 : size - 1;
+	if (u32_add_overflow(start, size, &end)) {
+		return 0;
+	}
+
+	if ((start >= r_addr_start) && (end <= r_addr_end)) {
 		return 1;
 	}
 

arch/arm/core/aarch32/cortex_m/mpu/nxp_mpu.c

@@ -10,6 +10,7 @@
 #include <soc.h>
 #include "arm_core_mpu_dev.h"
 #include <sys/__assert.h>
+#include <sys/math_extras.h>
 #include <linker/linker-defs.h>
 
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
@@ -428,11 +429,17 @@ static inline int is_in_region(u32_t r_index, u32_t start, u32_t size)
 {
 	u32_t r_addr_start;
 	u32_t r_addr_end;
+	u32_t end;
 
 	r_addr_start = SYSMPU->WORD[r_index][0];
 	r_addr_end = SYSMPU->WORD[r_index][1];
 
-	if (start >= r_addr_start && (start + size - 1) <= r_addr_end) {
+	size = size == 0 ? 0 : size - 1;
+	if (u32_add_overflow(start, size, &end)) {
+		return 0;
+	}
+
+	if ((start >= r_addr_start) && (end <= r_addr_end)) {
 		return 1;
 	}
 

arch/arm/core/aarch32/prep_c.c

@@ -76,11 +76,18 @@ void __weak relocate_vector_table(void)
 
 #endif /* CONFIG_CPU_CORTEX_M_HAS_VTOR */
 
-#ifdef CONFIG_FLOAT
-static inline void enable_floating_point(void)
+#if defined(CONFIG_CPU_HAS_FPU)
+static inline void z_arm_floating_point_init(void)
 {
 	/*
-	 * Upon reset, the Co-Processor Access Control Register is 0x00000000.
+	 * Upon reset, the Co-Processor Access Control Register is, normally,
+	 * 0x00000000. However, it might be left un-cleared by firmware running
+	 * before Zephyr boot.
+	 */
+	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
+
+#if defined(CONFIG_FLOAT)
+	/*
 	 * Enable CP10 and CP11 Co-Processors to enable access to floating
 	 * point registers.
 	 */
@@ -135,12 +142,23 @@ static inline void enable_floating_point(void)
 	 * will be activated (FPCA bit on the CONTROL register) in the presence
 	 * of floating point instructions.
 	 */
-}
-#else
-static inline void enable_floating_point(void)
-{
-}
+
+#endif /* CONFIG_FLOAT */
+
+	/*
+	 * Upon reset, the CONTROL.FPCA bit is, normally, cleared. However,
+	 * it might be left un-cleared by firmware running before Zephyr boot.
+	 * We must clear this bit to prevent errors in exception unstacking.
+	 *
+	 * Note:
+	 * In Sharing FP Registers mode CONTROL.FPCA is cleared before switching
+	 * to main, so it may be skipped here (saving few boot cycles).
+	 */
+#if !defined(CONFIG_FLOAT) || !defined(CONFIG_FP_SHARING)
+	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
 #endif
+}
+#endif /* CONFIG_CPU_HAS_FPU */
 
 extern FUNC_NORETURN void z_cstart(void);
 /**
@@ -154,7 +172,9 @@ extern FUNC_NORETURN void z_cstart(void);
 void z_arm_prep_c(void)
 {
 	relocate_vector_table();
-	enable_floating_point();
+#if defined(CONFIG_CPU_HAS_FPU)
+	z_arm_floating_point_init();
+#endif
 	z_bss_zero();
 	z_data_copy();
 #if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)

arch/arm/core/aarch32/swap_helper.S

@@ -508,7 +508,10 @@ _do_syscall:
     ldr ip, =K_SYSCALL_LIMIT
     cmp r6, ip
 #endif
-    blt valid_syscall_id
+    /* The supplied syscall_id must be lower than the limit
+     * (Requires unsigned integer comparison)
+     */
+    blo valid_syscall_id
 
     /* bad syscall id.  Set arg1 to bad id and set call_id to SYSCALL_BAD */
     str r6, [r0]

arch/xtensa/core/xtensa-asm2-util.S

@@ -163,6 +163,10 @@ _restore_context:
 	wsr.LEND a0
 	l32i a0, a1, BSA_LCOUNT_OFF
 	wsr.LCOUNT a0
+#endif
+#if XCHAL_HAVE_S32C1I
+	l32i a0, a1, BSA_SCOMPARE1_OFF
+	wsr.SCOMPARE1 a0
 #endif
 	rsync
 

arch/xtensa/include/xtensa-asm2-context.h

@@ -34,6 +34,8 @@
  * SP-52  Saved LEND special register (if loops enabled)
  * SP-56  Saved LCOUNT special register (if loops enabled)
  *
+ * SP-60  Saved SCOMPARE special register (if S32C1I enabled)
+ *
  *       (The above fixed-size region is known as the "base save area" in the
  *        code below)
  *
@@ -62,12 +64,25 @@
  * original/interrupted stack pointer.
  */
 
+#define BASE_SAVE_AREA_SIZE_COMMON	44
+
 #if XCHAL_HAVE_LOOPS
-#define BASE_SAVE_AREA_SIZE 56
+#define BASE_SAVE_AREA_SIZE_LOOPS	12
 #else
-#define BASE_SAVE_AREA_SIZE 44
+#define BASE_SAVE_AREA_SIZE_LOOPS	0
 #endif
 
+#if XCHAL_HAVE_S32C1I
+#define BASE_SAVE_AREA_SIZE_SCOMPARE	4
+#else
+#define BASE_SAVE_AREA_SIZE_SCOMPARE	0
+#endif
+
+#define BASE_SAVE_AREA_SIZE \
+	(BASE_SAVE_AREA_SIZE_COMMON + \
+	 BASE_SAVE_AREA_SIZE_LOOPS + \
+	 BASE_SAVE_AREA_SIZE_SCOMPARE)
+
 #define BSA_A3_OFF	(BASE_SAVE_AREA_SIZE - 20)
 #define BSA_A2_OFF	(BASE_SAVE_AREA_SIZE - 24)
 #define BSA_SCRATCH_OFF	(BASE_SAVE_AREA_SIZE - 28)
@@ -79,4 +94,9 @@
 #define BSA_LEND_OFF	(BASE_SAVE_AREA_SIZE - 52)
 #define BSA_LCOUNT_OFF	(BASE_SAVE_AREA_SIZE - 56)
 
+#define BSA_SCOMPARE1_OFF \
+			(BASE_SAVE_AREA_SIZE - \
+			 (BASE_SAVE_AREA_SIZE_COMMON + \
+			  BASE_SAVE_AREA_SIZE_LOOPS + 4))
+
 #endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_CONTEXT_H_ */

arch/xtensa/include/xtensa-asm2-s.h

@@ -110,6 +110,10 @@
 	rsr.LCOUNT a0
 	s32i a0, a1, BSA_LCOUNT_OFF
 #endif
+#if XCHAL_HAVE_S32C1I
+	rsr.SCOMPARE1 a0
+	s32i a0, a1, BSA_SCOMPARE1_OFF
+#endif
 .endm
 
 /*

boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml

@@ -8,5 +8,3 @@ toolchain:
   - zephyr
   - gnuarmemb
   - xtools
-supported:
-  - hwinfo

boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.yaml

@@ -8,5 +8,3 @@ toolchain:
   - zephyr
   - gnuarmemb
   - xtools
-supported:
-  - hwinfo

boards/arm/arduino_due/arduino_due_defconfig

@@ -11,3 +11,4 @@ CONFIG_SERIAL=y
 CONFIG_UART_SAM=y
 CONFIG_UART_SAM_PORT_0=y
 CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK=y
+CONFIG_WDT_DISABLE_AT_BOOT=y

boards/arm/arduino_zero/arduino_zero.yaml

@@ -8,5 +8,3 @@ toolchain:
   - zephyr
   - gnuarmemb
   - xtools
-supported:
-  - hwinfo

boards/arm/atsamd20_xpro/atsamd20_xpro.yaml

@@ -8,5 +8,3 @@ toolchain:
   - zephyr
   - gnuarmemb
   - xtools
-supported:
-  - hwinfo

boards/arm/atsamr21_xpro/atsamr21_xpro.dts

@@ -81,7 +81,7 @@
 		compatible = "atmel,rf2xx";
 		reg = <0x0>;
 		label = "RF2XX_0";
-		spi-max-frequency = <8000000>;
+		spi-max-frequency = <6000000>;
 		irq-gpios = <&portb 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
 		reset-gpios = <&portb 15 GPIO_ACTIVE_LOW>;
 		slptr-gpios = <&porta 20 GPIO_ACTIVE_HIGH>;

boards/arm/atsamr21_xpro/atsamr21_xpro.yaml

@@ -17,4 +17,3 @@ supported:
   - i2c
   - ieee802154
   - usb_device
-  - hwinfo

boards/arm/frdm_k64f/frdm_k64f.yaml

@@ -13,7 +13,6 @@ supported:
   - can
   - counter
   - gpio
-  - hwinfo
   - i2c
   - netif:eth
   - nvs

boards/arm/frdm_k82f/frdm_k82f.yaml

@@ -11,7 +11,6 @@ flash: 256
 supported:
   - arduino_gpio
   - gpio
-  - hwinfo
   - i2c
   - nvs
   - pwm

boards/arm/frdm_kl25z/frdm_kl25z.yaml

@@ -16,6 +16,5 @@ supported:
   - adc
   - arduino_gpio
   - gpio
-  - hwinfo
   - i2c
   - usb_device

boards/arm/frdm_kw41z/frdm_kw41z.yaml

@@ -11,7 +11,6 @@ supported:
   - arduino_gpio
   - counter
   - gpio
-  - hwinfo
   - i2c
   - ieee802154
   - spi

boards/arm/hexiwear_k64/hexiwear_k64.yaml

@@ -10,7 +10,6 @@ supported:
   - adc
   - ble
   - gpio
-  - hwinfo
   - i2c
   - pwm
   - spi

boards/arm/hexiwear_kw40z/hexiwear_kw40z.yaml

@@ -8,8 +8,6 @@ toolchain:
   - zephyr
   - gnuarmemb
   - xtools
-supported:
-  - hwinfo
 testing:
   ignore_tags:
     - net

boards/arm/mimxrt1010_evk/mimxrt1010_evk.yaml

@@ -16,6 +16,5 @@ ram: 32
 flash: 16384
 supported:
   - i2c
-  - hwinfo
   - counter
   - usb_device

boards/arm/mimxrt1015_evk/mimxrt1015_evk.yaml

@@ -18,6 +18,5 @@ supported:
   - arduino_gpio
   - counter
   - gpio
-  - hwinfo
   - i2c
   - usb_device

boards/arm/mimxrt1020_evk/mimxrt1020_evk.yaml

@@ -18,7 +18,6 @@ supported:
   - arduino_gpio
   - counter
   - gpio
-  - hwinfo
   - i2c
   - netif:eth
   - usb_device

boards/arm/mimxrt1050_evk/mimxrt1050_evk.yaml

@@ -19,7 +19,6 @@ supported:
   - counter
   - display
   - gpio
-  - hwinfo
   - i2c
   - netif:eth
   - sdhc

boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.yaml

@@ -19,7 +19,6 @@ supported:
   - counter
   - display
   - gpio
-  - hwinfo
   - i2c
   - netif:eth
   - sdhc

boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml

@@ -19,7 +19,6 @@ supported:
   - counter
   - display
   - gpio
-  - hwinfo
   - i2c
   - netif:eth
   - usb_device

boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.yaml

@@ -19,7 +19,6 @@ supported:
   - counter
   - display
   - gpio
-  - hwinfo
   - i2c
   - netif:eth
   - usb_device

boards/arm/mimxrt1064_evk/mimxrt1064_evk.yaml

@@ -19,7 +19,6 @@ supported:
   - counter
   - display
   - gpio
-  - hwinfo
   - i2c
   - netif:eth
   - pwm

boards/arm/mm_swiftio/mm_swiftio.yaml

@@ -15,5 +15,4 @@ toolchain:
 ram: 32768
 flash: 8192
 supported:
-  - hwinfo
   - counter

boards/arm/nucleo_g474re/board.cmake

@@ -1,4 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
-board_runner_args(pyocd "--target=stm32g474retx")
+
+# use target=stm32g474rbtx instead of stm32g474retx
+# to allow board re-flashing (see PR #23230)
+board_runner_args(pyocd "--target=stm32g474rbtx")
 
 include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

boards/arm/nucleo_g474re/nucleo_g474re.yaml

@@ -6,8 +6,8 @@ toolchain:
   - zephyr
   - gnuarmemb
   - xtools
-ram: 32
-flash: 128
+ram: 128
+flash: 512
 supported:
   - arduino_gpio
   - arduino_i2c

boards/arm/qemu_cortex_r5/doc/index.rst

@@ -0,0 +1,111 @@
+.. _qemu_cortex_r5:
+
+ARM Cortex-R5 Emulation (QEMU)
+##############################
+
+Overview
+********
+
+This board configuration will use QEMU to emulate the Xilinx Zynq UltraScale+
+(ZynqMP) platform.
+
+.. figure:: qemu_cortex_r5.png
+   :width: 600px
+   :align: center
+   :alt: Qemu
+
+   Qemu (Credit: qemu.org)
+
+This configuration provides support for an ARM Cortex-R5 CPU and these devices:
+
+* ARM PL-390 Generic Interrupt Controller
+* Xilinx Zynq TTC (Cadence TTC)
+* Xilinx Zynq UART
+
+.. note::
+   This board configuration makes no claims about its suitability for use
+   with an actual ZCU102 hardware system, or any other hardware system.
+
+Hardware
+********
+Supported Features
+==================
+
+The following hardware features are supported:
+
++--------------+------------+----------------------+
+| Interface    | Controller | Driver/Component     |
++==============+============+======================+
+| GIC          | on-chip    | generic interrupt    |
+|              |            | controller           |
++--------------+------------+----------------------+
+| TTC          | on-chip    | system timer         |
++--------------+------------+----------------------+
+| UART         | on-chip    | serial port          |
++--------------+------------+----------------------+
+
+The kernel currently does not support other hardware features on this platform.
+
+Devices
+========
+System Timer
+------------
+
+This board configuration uses a system timer tick frequency of 1000 Hz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+on-chip UART0.
+
+Known Problems or Limitations
+==============================
+
+The following platform features are unsupported:
+
+* Dual-redundant Core Lock-step (DCLS) execution is not emulated.
+* Xilinx Zynq TTC driver does not support tickless mode operation.
+
+Programming and Debugging
+*************************
+
+Use this configuration to run basic Zephyr applications and kernel tests in the
+QEMU emulated environment, for example, with the :ref:`synchronization_sample`:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: qemu_cortex_r5
+   :goals: run
+
+This will build an image with the synchronization sample app, boot it using
+QEMU, and display the following console output:
+
+.. code-block:: console
+
+        *** Booting Zephyr OS build v2.2.0  ***
+        threadA: Hello World from qemu_cortex_r5!
+        threadB: Hello World from qemu_cortex_r5!
+        threadA: Hello World from qemu_cortex_r5!
+        threadB: Hello World from qemu_cortex_r5!
+        threadA: Hello World from qemu_cortex_r5!
+        threadB: Hello World from qemu_cortex_r5!
+        threadA: Hello World from qemu_cortex_r5!
+        threadB: Hello World from qemu_cortex_r5!
+        threadA: Hello World from qemu_cortex_r5!
+        threadB: Hello World from qemu_cortex_r5!
+
+Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
+
+Debugging
+=========
+
+Refer to the detailed overview about :ref:`application_debugging`.
+
+References
+**********
+
+1. ARMv7-A and ARMv7-R Architecture Reference Manual (ARM DDI 0406C ID051414)
+2. Cortex-R5 and Cortex-R5F Technical Reference Manual (ARM DDI 0460C ID021511)
+3. Zynq UltraScale+ Device Technical Reference Manual (UG1085)

boards/arm/sam4e_xpro/sam4e_xpro_defconfig

@@ -12,3 +12,4 @@ CONFIG_BOARD_SAM4E_XPRO=y
 CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK=y
 CONFIG_GPIO_SAM=y
 CONFIG_GPIO=y
+CONFIG_WDT_DISABLE_AT_BOOT=y

boards/arm/sam4s_xplained/sam4s_xplained_defconfig

@@ -11,3 +11,4 @@ CONFIG_UART_SAM_PORT_0=y
 CONFIG_BOARD_SAM4S_XPLAINED=y
 CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK=y
 CONFIG_GPIO=y
+CONFIG_WDT_DISABLE_AT_BOOT=y

boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig

@@ -13,4 +13,5 @@ CONFIG_SERIAL=y
 CONFIG_USART_SAM=y
 CONFIG_USART_SAM_PORT_1=y
 CONFIG_BOARD_SAM_E70_XPLAINED=y
+CONFIG_WDT_DISABLE_AT_BOOT=y
 CONFIG_BUILD_OUTPUT_HEX=y

boards/arm/sam_v71_xult/sam_v71_xult_defconfig

@@ -12,3 +12,4 @@ CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_USART_SAM=y
 CONFIG_USART_SAM_PORT_1=y
+CONFIG_WDT_DISABLE_AT_BOOT=y

boards/arm/twr_ke18f/twr_ke18f.yaml

@@ -12,7 +12,6 @@ supported:
   - adc
   - can
   - counter
-  - hwinfo
   - i2c
   - pwm
   - spi

boards/arm/twr_kv58f220m/twr_kv58f220m.yaml

@@ -9,5 +9,4 @@ toolchain:
 ram: 256
 flash: 1024
 supported:
-  - hwinfo
   - i2c

boards/arm/usb_kw24d512/usb_kw24d512.yaml

@@ -9,7 +9,6 @@ toolchain:
   - gnuarmemb
   - xtools
 supported:
-  - hwinfo
   - ieee802154
   - usb_device
   - watchdog

doc/conf.py

@@ -527,12 +527,10 @@ html_context = {
     'theme_logo_only': False,
     'current_version': version,
     'versions': (("latest", "/"),
+                 ("2.2.0", "/2.2.0/"),
                  ("2.1.0", "/2.1.0/"),
                  ("2.0.0", "/2.0.0/"),
                  ("1.14.1", "/1.14.1/"),
-                 ("1.13.0", "/1.13.0/"),
-                 ("1.12.0", "/1.12.0/"),
-                 ("1.11.0", "/1.11.0/"),
                 )
 }
 

doc/development_process/release_process.rst

@@ -239,7 +239,9 @@ steps:
 
     Tagging needs to be done via explicit git commands and not via GitHub's release
     interface.  The GitHub release interface does not generate annotated tags (it
-    generates 'lightweight' tags regardless of release or pre-release).
+    generates 'lightweight' tags regardless of release or pre-release). You should
+    also upload your gpg public key to your GitHub account, since the instructions
+    below involve creating signed tags.
 
 .. tabs::
 
@@ -263,8 +265,7 @@ steps:
         #. Tag and push the version, using an annotated tag::
 
             $ git pull
-            $ git tag -a v1.11.0-rc1
-            <Use "Zephyr 1.11.0-rc1" as the tag annotation>
+            $ git tag -m "Zephyr 1.11.0-rc1" -s v1.11.0-rc1
             $ git push git@github.com:zephyrproject-rtos/zephyr.git v1.11.0-rc1
 
         #. Create a shortlog of changes between the previous release (use
@@ -273,7 +274,7 @@ steps:
             $ git shortlog v1.10.0..v1.11.0-rc1
 
         #. Find the new tag at the top of the releases page and edit the release
-           with the ``Edit`` button with the following:
+           with the ``Draft a new release`` button with the following:
 
             * Name it ``Zephyr 1.11.0-rc1``
             * Copy the shortlog into the release notes textbox (*don't forget
@@ -306,16 +307,14 @@ steps:
         #. Tag and push the version, using two annotated tags::
 
             $ git pull
-            $ git tag -a v1.11.0
-            <Use "Zephyr 1.11.0" as the tag annotation>
+            $ git tag -m "Zephyr 1.11.0" -s v1.11.0
             $ git push git@github.com:zephyrproject-rtos/zephyr.git v1.11.0
 
-            $ git tag -a zephyr-v1.11.0
-            <Use "Zephyr 1.11.0" as the tag annotation>
+            $ git tag -m "Zephyr 1.11.0" -s zephyr-v1.11.0
             $ git push git@github.com:zephyrproject-rtos/zephyr.git zephyr-v1.11.0
 
         #. Find the new tag at the top of the releases page and edit the release
-           with the ``Edit`` button with the following:
+           with the ``Draft a new release`` button with the following:
 
             * Name it ``Zephyr 1.11.0``
             * Copy the full content of ``docs/releases/release-notes-1.11.rst``

doc/getting_started/index.rst

@@ -42,7 +42,7 @@ tools. First, make sure your development system OS is updated:
 
    .. group-tab:: macOS
 
-      On macOS Mojave, you can manually check for updates by choosing
+      On macOS Mojave or later, you can manually check for updates by choosing
       System Preferences from the Apple menu, then clicking Software Update (and
       click Update Now if there are). For other macOS versions, see the
       `Update macOS topic in Apple support
@@ -306,15 +306,15 @@ including: compiler, assembler, linker, and their dependencies.
          .. code-block:: bash
 
             cd ~
-            wget https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v0.11.1/zephyr-sdk-0.11.1-setup.run
+            wget https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v0.11.2/zephyr-sdk-0.11.2-setup.run
 
       #. Run the installation binary, installing the SDK in your home
-         folder :file:`~/zephyr-sdk-0.11.1`:
+         folder :file:`~/zephyr-sdk-0.11.2`:
 
          .. code-block:: bash
 
-            chmod +x zephyr-sdk-0.11.1-setup.run
-            ./zephyr-sdk-0.11.1-setup.run -- -d ~/zephyr-sdk-0.11.1
+            chmod +x zephyr-sdk-0.11.2-setup.run
+            ./zephyr-sdk-0.11.2-setup.run -- -d ~/zephyr-sdk-0.11.2
 
       #. Set environment variables to let the build system know where to
          find the toolchain programs:
@@ -322,7 +322,7 @@ including: compiler, assembler, linker, and their dependencies.
          .. code-block:: bash
 
             export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
-            export ZEPHYR_SDK_INSTALL_DIR=~/zephyr-sdk-0.11.1
+            export ZEPHYR_SDK_INSTALL_DIR=~/zephyr-sdk-0.11.2
 
       The SDK contains a udev rules file that provides information
       needed to identify boards and grant hardware access permission to flash
@@ -361,6 +361,12 @@ The sample :ref:`blinky-sample` blinks an LED on the target board.  By
 building and running it, we can verify that the environment and tools
 are properly set up for Zephyr development.
 
+   .. note:: This sample is compatible with most boards supported by
+      Zephyr, but not all of them. See the :ref:`blinky sample requirements
+      <blinky-sample-requirements>` for more information. If this sample is not
+      compatible with your board, a good alternative to try is the
+      :ref:`Hello World sample <hello_world>`.
+
 #. Set build environment variables:
 
    .. tabs::

doc/getting_started/installation_linux.rst

@@ -237,19 +237,19 @@ Follow these steps to install the Zephyr SDK:
 
    .. code-block:: console
 
-      wget https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v0.11.1/zephyr-sdk-0.11.1-setup.run
+      wget https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v0.11.2/zephyr-sdk-0.11.2-setup.run
 
-   (You can change *0.11.1* to another version if needed; the `Zephyr
+   (You can change *0.11.2* to another version if needed; the `Zephyr
    Downloads`_ page contains all available SDK releases.)
 
 #. Run the installation binary, installing the SDK at
-   :file:`~/zephyr-sdk-0.11.1`:
+   :file:`~/zephyr-sdk-0.11.2`:
 
    .. code-block:: console
 
       cd <sdk download directory>
-      chmod +x zephyr-sdk-0.11.1-setup.run
-      ./zephyr-sdk-0.11.1-setup.run -- -d ~/zephyr-sdk-0.11.1
+      chmod +x zephyr-sdk-0.11.2-setup.run
+      ./zephyr-sdk-0.11.2-setup.run -- -d ~/zephyr-sdk-0.11.2
 
    You can pick another directory if you want. If this fails, make sure
    Zephyr's dependencies were installed as described in `Install Requirements
@@ -258,7 +258,7 @@ Follow these steps to install the Zephyr SDK:
 #. Set these :ref:`environment variables <env_vars>`:
 
    - set :envvar:`ZEPHYR_TOOLCHAIN_VARIANT` to ``zephyr``
-   - set :envvar:`ZEPHYR_SDK_INSTALL_DIR` to :file:`$HOME/zephyr-sdk-0.11.1`
+   - set :envvar:`ZEPHYR_SDK_INSTALL_DIR` to :file:`$HOME/zephyr-sdk-0.11.2`
      (or wherever you chose to install the SDK)
 
 If you ever want to uninstall the SDK, just remove the directory where you

doc/getting_started/installation_mac.rst

@@ -1,54 +1,40 @@
-.. _installing_zephyr_mac:
+.. _mac-setup-alts:
 
-Install macOS Host Dependencies
-###############################
+macOS alternative setup instructions
+####################################
 
-This section describes how to set up a Zephyr development environment on macOS.
+.. _mac-gatekeeper:
 
-These instructions have been tested on the following macOS versions:
+Important note about Gatekeeper
+*******************************
 
-* Mac OS X 10.11 (El Capitan)
-* macOS Sierra 10.12
+Starting with macOS 10.15 Catalina, applications launched from the macOS
+Terminal application (or any other terminal emulator) are subject to the same
+system security policies that are applied to applications launched from the
+Dock. This means that if you download executable binaries using a web browser,
+macOS will not let you execute those from the Terminal by default. In order to
+get around this issue you can take two different approaches:
 
-Update Your Operating System
-****************************
+* Run ``xattr -r -d com.apple.quarantine /path/to/folder`` where
+  ``path/to/folder`` is the path to the enclosing folder where the executables
+  you want to run are located.
 
-Before proceeding with the build, ensure your OS is up to date.
+* Open "System Preferences" -> "Security and Privacy" -> "Privacy" and then
+  scroll down to "Developer Tools". Then unlock the lock to be able to make
+  changes and check the checkbox corresponding to your terminal emulator of
+  choice. This will apply to any executable being launched from such terminal
+  program.
 
-.. _mac_requirements:
+Note that this section does **not** apply to executables installed with
+Homebrew, since those are automatically un-quarantined by ``brew`` itself. This
+is however relevant for most :ref:`third_party_x_compilers`.
 
-Install Requirements and Dependencies
-*************************************
-
-.. NOTE FOR DOCS AUTHORS: DO NOT PUT DOCUMENTATION BUILD DEPENDENCIES HERE.
-
-   This section is for dependencies to build Zephyr binaries, *NOT* this
-   documentation. If you need to add a dependency only required for building
-   the docs, add it to doc/README.rst. (This change was made following the
-   introduction of LaTeX->PDF support for the docs, as the texlive footprint is
-   massive and not needed by users not building PDF documentation.)
-
-Zephyr requires Python 3, while macOS only provides a Python 2
-installation. After following these instructions, the version of Python 2
-provided by macOS in ``/usr/bin/`` will sit alongside the Python 3 installation
-from Homebrew in ``/usr/local/bin``.
-
-First, install :program:`Homebrew` by following instructions on the `Homebrew
-site`_. Homebrew is a free and open-source package management system that
-simplifies the installation of software on macOS.  While installing Homebrew,
-you may be prompted to install additional missing dependencies; please follow
-any such instructions as well.
-
-Now install these host dependencies with the ``brew`` command:
-
-.. code-block:: console
-
-   brew install cmake ninja gperf ccache dfu-util qemu dtc python3
-
-.. _Homebrew site: https://brew.sh/
+.. _macOS Gatekeeper: https://en.wikipedia.org/wiki/Gatekeeper_(macOS)
 
 Additional notes for MacPorts users
 ***********************************
 
-While MacPorts is not officially supported in this guide, it is possible to use MacPorts instead of Homebrew to get all the required dependencies on macOS.
-Note also that you may need to install ``rust`` and ``cargo`` for the Python dependencies to install correctly.
+While MacPorts is not officially supported in this guide, it is possible to use
+MacPorts instead of Homebrew to get all the required dependencies on macOS.
+Note also that you may need to install ``rust`` and ``cargo`` for the Python
+dependencies to install correctly.

doc/getting_started/installation_win.rst

@@ -1,106 +1,12 @@
-.. _installing_zephyr_win:
+.. _win-setup-alts:
 
-Install Windows Host Dependencies
-#################################
+Windows alternative setup instructions
+######################################
 
-This guide was tested on Windows versions 7, 8.1, and 10.
+.. _win-wsl:
 
-Update Your Operating System
-****************************
-
-Before proceeding with the build, ensure that you are running your
-Windows system with the latest updates installed.
-
-.. _windows_requirements:
-
-Install Requirements and Dependencies
-*************************************
-
-.. NOTE FOR DOCS AUTHORS: DO NOT PUT DOCUMENTATION BUILD DEPENDENCIES HERE.
-
-   This section is for dependencies to build Zephyr binaries, *NOT* this
-   documentation. If you need to add a dependency only required for building
-   the docs, add it to doc/README.rst. (This change was made following the
-   introduction of LaTeX->PDF support for the docs, as the texlive footprint is
-   massive and not needed by users not building PDF documentation.)
-
-There are 2 different ways of developing for Zephyr on Microsoft Windows:
-
-#. :ref:`windows_install_native` (recommended)
-#. :ref:`windows_install_wsl`
-
-The first option is fully Windows native; the other requires emulation layers
-that may result in slower build times.
-
-.. _windows_install_native:
-
-Option 1: Windows Command Prompt
-================================
-
-These instructions assume you are using the ``cmd.exe`` command prompt. Some of
-the details, such as setting environment variables, may differ if you are using
-PowerShell.
-
-The easiest way to install the native Windows dependencies is to first install
-`Chocolatey`_, a package manager for Windows.  If you prefer to install
-dependencies manually, you can also download the required programs from their
-respective websites.
-
-.. note::
-   Chocolatey will properly set up your environment so tools can be
-   found on your PATH.  If you install programs manually, be sure to
-   verify the programs can also be found on your PATH.  For example,
-   you may need to add ``C:\\Program Files\Git\bin`` after manually
-   installing Git for Windows.
-
-.. note::
-   There are multiple ``set`` statements in this tutorial. You can avoid
-   typing them every time by placing them inside a ``.cmd`` file and
-   running that every time you open a command prompt.
-
-#. If you're behind a corporate firewall, you'll likely need to specify a
-   proxy to get access to internet resources:
-
-   .. code-block:: console
-
-      set HTTP_PROXY=http://user:password@proxy.mycompany.com:1234
-      set HTTPS_PROXY=http://user:password@proxy.mycompany.com:1234
-
-#. Install :program:`Chocolatey` by following the instructions on the
-   `Chocolatey install`_ page.
-
-#. Open a command prompt (``cmd.exe``) as an **Administrator** (press the
-   Windows key, type "cmd.exe" in the prompt, then right-click the result and
-   choose "Run as Administrator").
-
-#. Optionally disable global confirmation to avoid having to confirm
-   installation of individual programs:
-
-   .. code-block:: console
-
-      choco feature enable -n allowGlobalConfirmation
-
-#. Install CMake:
-
-   .. code-block:: console
-
-      choco install cmake --installargs 'ADD_CMAKE_TO_PATH=System'
-
-#. Install the rest of the tools:
-
-   .. code-block:: console
-
-      choco install git python ninja dtc-msys2 gperf
-
-#. Close the Administrator command prompt window.
-
-.. NOTE FOR DOCS AUTHORS: as a reminder, do *NOT* put dependencies for building
-   the documentation itself here.
-
-.. _windows_install_wsl:
-
-Option 2: Windows 10 WSL (Windows Subsystem for Linux)
-======================================================
+Windows 10 WSL (Windows Subsystem for Linux)
+********************************************
 
 If you are running a recent version of Windows 10 you can make use of the
 built-in functionality to natively run Ubuntu binaries directly on a standard
@@ -126,7 +32,5 @@ command-prompt. This allows you to use software such as the :ref:`Zephyr SDK
 .. NOTE FOR DOCS AUTHORS: as a reminder, do *NOT* put dependencies for building
    the documentation itself here.
 
-.. _Chocolatey: https://chocolatey.org/
-.. _Chocolatey install: https://chocolatey.org/install
 .. _Install the Windows Subsystem for Linux (WSL): https://msdn.microsoft.com/en-us/commandline/wsl/install_guide
 .. _Zephyr Issue 10420: https://github.com/zephyrproject-rtos/zephyr/issues/10420

doc/getting_started/toolchain_3rd_party_x_compilers.rst

@@ -22,9 +22,9 @@ GNU ARM Embedded
 
    .. warning::
 
-	  The GNU ARM Embedded Toolchain for Windows, version **8-2018-q4-major**
-	  has a `critical bug <https://github.com/zephyrproject-rtos/zephyr/issues/12257>`_
-	  and should not be used. Toolchain version **7-2018-q2-update** is known to work.
+      On macOS Catalina or later you might need to :ref:`change a security
+      policy <mac-gatekeeper>` for the toolchain to be able to run from the
+      terminal.
 
 #. :ref:`Set these environment variables <env_vars>`:
 

doc/glossary.rst

@@ -65,14 +65,14 @@ Glossary of Terms
       The set of Zephyr-supplied files that implement the Zephyr kernel,
       including its core services, device drivers, network stack, and so on.
 
+   SoC
+      `System on a chip`_
+
    west
       A multi-repo meta-tool developed for the Zephyr project. See :ref:`west`.
 
    west installation
-      A directory on your system with a :file:`.west` subdirectory and
-      a :term:`west manifest repository`. You clone the Zephyr source
-      code onto your system by creating a west installation using the
-      ``west init`` command. See :ref:`west-multi-repo`.
+      A term for a :term:`west workspace` used prior to west 0.7.
 
    west manifest
       A YAML file named :file:`west.yml` which describes projects, or the Git
@@ -85,7 +85,15 @@ Glossary of Terms
       :term:`west manifest`. Its location is given by the :ref:`manifest.path
       configuration option <west-config-index>`. See :ref:`west-multi-repo`.
 
+   west workspace
+      A directory on your system with a :file:`.west` subdirectory and
+      a :term:`west manifest repository`. You clone the Zephyr source
+      code onto your system by creating a west workspace using the
+      ``west init`` command. See :ref:`west-multi-repo`.
+
    XIP
       (eXecute In Place) a method of executing programs directly from long
       term storage rather than copying it into RAM, saving writable memory for
       dynamic data and not the static program code.
+
+.. _System on a chip: https://en.wikipedia.org/wiki/System_on_a_chip

doc/guides/dts/intro.rst

@@ -271,6 +271,8 @@ reg
     ``reg = <0x40003000 0x1000>;`` means the register map occupies 0x1000 bytes
     in the memory map.
 
+.. _devicetree-in-out-files:
+
 Input and output files
 **********************
 

doc/guides/dts/macros.rst

@@ -587,9 +587,9 @@ example ``DT_<node>_CLOCK_CONTROLLER_0`` instead of
 
    This inconsistency might be fixed in the future.
 
-In addition, if the clock controller node has a ``fixed-clock`` property, it is
-expected to also have a ``clock-frequency`` property giving the frequency, and
-an additional macro is generated:
+If a ``clocks`` controller node has a ``"fixed-clock"`` compatible, it
+must also have a ``clock-frequency`` property giving its frequency in Hertz.
+In this case, an additional macro is generated:
 
 .. code-block:: none
 

doc/guides/porting/board_porting.rst

@@ -3,40 +3,26 @@
 Board Porting Guide
 ###################
 
-When building an application you must specify the target hardware and
-the exact board or model. Specifying the board name results in a binary that
-is suited for the target hardware by selecting the right Zephyr features and
-components and setting the right Zephyr configuration for that specific target
-hardware.
+To add Zephyr support for a new :term:`board`, you at least need a *board
+directory* with various files in it. Files in the board directory inherit
+support for at least one SoC and all of its features. Therefore, Zephyr must
+support your :term:`SoC` as well.
 
-A board is defined as a special configuration of an SoC with possible additional
-components.
-For example, a board might have sensors and flash memory implemented as
-additional features on top of what the SoC provides. Such additional hardware is
-configured and referenced in the Zephyr board configuration.
+Boards, SoCs, etc.
+******************
 
-The board implements at least one SoC and thus inherits all of the features
-that are provided by the SoC. When porting a board to Zephyr, you should
-first make sure the SoC is implemented in Zephyr.
+Zephyr's hardware support hierarchy has these layers, from most to least
+specific:
 
-Hardware Configuration Hierarchy
-********************************
+- Board: a particular CPU instance and its peripherals in a concrete hardware
+  specification
+- SoC: the exact system on a chip the board's CPU is part of
+- SoC series: a smaller group of tightly related SoCs
+- SoC family: a wider group of SoCs with similar characteristics
+- CPU core: a particular CPU in an architecture
+- Architecture: an instruction set architecture
 
-Hardware definitions in Zephyr follow a well-defined hierarchy of configurations
-and layers, below are the layers from top to bottom:
-
-- Board
-- SoC
-- SoC Series
-- SoC Family
-- CPU Core
-- Architecture
-
-This design contributes to code reuse and implementation of device drivers and
-features at the bottom of the hierarchy making a board configuration as simple
-as a selection of features that are implemented by the underlying layers. The
-figures below shows this hierarchy with a few example of boards currently
-available in the source tree:
+You can visualize the hierarchy like this:
 
 .. figure:: board/hierarchy.png
    :width: 500px
@@ -45,131 +31,429 @@ available in the source tree:
 
    Configuration Hierarchy
 
+Here are some examples. Notice how the SoC series and family levels are
+not always used.
 
-Hierarchy Example
+.. list-table::
+   :header-rows: 1
 
-+------------+-----------+--------------+------------+--------------+---------+
-|Board       |FRDM K64F  |nRF52 NITROGEN|nRF51XX     |Quark SE C1000|Arduino  |
-|            |           |              |            |Devboard      |101      |
-+============+===========+==============+============+==============+=========+
-|SOC         |MK64F12    |nRF52832      |nRF51XX     |Quark SE C1000|Curie    |
-+------------+-----------+--------------+------------+--------------+---------+
-|SOC Series  |Kinetis K6x|Nordic NRF52  |Nordic NRF51|Quark SE      |Quark SE |
-|            |Series     |              |            |              |         |
-+------------+-----------+--------------+------------+--------------+---------+
-|SOC Family  |NXP Kinetis|Nordic NRF5   |Nordic NRF5 |Quark         |Quark    |
-+------------+-----------+--------------+------------+--------------+---------+
-|CPU Core    |Cortex-M4  |Cortex-M4     |Cortex-M0   |Lakemont      |Lakemont |
-+------------+-----------+--------------+------------+--------------+---------+
-|Architecture|ARM        |ARM           |ARM         |x86           |x86      |
-+------------+-----------+--------------+------------+--------------+---------+
+   * - Board
+     - SoC
+     - SoC series
+     - SoC family
+     - CPU core
+     - Architecture
+   * - :ref:`nrf52_pca10040 <nrf52_pca10040>`
+     - nRF52832
+     - nRF52
+     - Nordic nRF5
+     - Arm Cortex-M4
+     - Arm
+   * - :ref:`frdm_k64f <frdm_k64f>`
+     - MK64F12
+     - Kinetis K6x
+     - NXP Kinetis
+     - Arm Cortex-M4
+     - Arm
+   * - :ref:`stm32h474i_disco <stm32h747i_disco_board>`
+     - STM32H747XI
+     - STM32H7
+     - STMicro STM32
+     - Arm Cortex-M7
+     - Arm
+   * - :ref:`rv32m1_vega_ri5cy <rv32m1_vega>`
+     - RV32M1
+     - (Not used)
+     - (Not used)
+     - RI5CY
+     - RISC-V
 
+Make sure your SoC is supported
+*******************************
+
+Start by making sure your SoC is supported by Zephyr. If it is, it's time to
+:ref:`create-your-board-directory`. If you don't know, try:
+
+- checking :ref:`boards` for names that look relevant, and reading individual
+  board documentation to find out for sure.
+- asking your SoC vendor
+
+If you need to add SoC, CPU core, or even architecture support, this is the
+wrong page, but here is some general advice.
 
 Architecture
 ============
-If your CPU architecture is already supported by Zephyr, there is no
-architecture work involved in porting to your board.  If your CPU architecture
-is not supported by the Zephyr kernel, you can add support by following the
-instructions available at :ref:`architecture_porting_guide`.
+
+See :ref:`architecture_porting_guide`.
 
 CPU Core
 ========
 
-Some OS code depends on the CPU core that your board is using. For
-example, a given CPU core has a specific assembly language instruction set, and
-may require special cross compiler or compiler settings to use the appropriate
-instruction set.
+CPU core support files go in ``core`` subdirectories under :zephyr_file:`arch`,
+e.g. :zephyr_file:`arch/x86/core`.
 
-If your CPU architecture is already supported by Zephyr, there is no CPU core
-work involved in porting to your platform or board. You need only to select the
-appropriate CPU in your configuration and the rest will be taken care of by the
-configuration system in Zephyr which will select the features implemented
-by the corresponding CPU.
-
-Platform
-========
-
-This layer implements most of the features that need porting and is split into
-three layers to allow for code reuse when dealing with implementations with
-slight differences.
-
-SoC Family
-----------
-
-This layer is a container of all SoCs of the same class that, for example
-implement one single type of CPU core but differ in peripherals and features.
-The base hardware will in most cases be the same across all SoCs and MCUs of
-this family.
-
-SoC Series
-----------
-
-Moving closer to the SoC, the series is derived from an SoC family. A series is
-defined by a feature set that serves the purpose of distinguishing different
-SoCs belonging to the same family.
+See :ref:`gs_toolchain` for information about toolchains (compiler, linker,
+etc.) supported by Zephyr. If you need to support a new toolchain,
+:ref:`build_overview` is a good place to start learning about the build system.
+Please reach out to the community if you are looking for advice or want to
+collaborate on toolchain support.
 
 SoC
----
+===
 
-Finally, an SoC is actual hardware component that is physically available on a
-board.
+Zephyr SoC support files are in architecture-specific subdirectories of
+:zephyr_file:`soc`. They are generally grouped by SoC family.
 
-Board
-=====
+When adding a new SoC family or series for a vendor that already has SoC
+support within Zephyr, please try to extract common functionality into shared
+files to avoid duplication. If there is no support for your vendor yet, you can
+add it in a new directory ``zephyr/soc/<YOUR-ARCH>/<YOUR-SOC>``; please use
+self-explanatory directory names.
 
-A board implements an SoC with all its features, together with peripherals
-available on the board that differentiates the board with additional interfaces
-and features not available in the SoC.
+.. _create-your-board-directory:
 
-A board port on Zephyr typically consists of two parts:
+Create your board directory
+***************************
 
-- A hardware description (usually done by device tree), which specifies embedded
-  SoC reference, connectors and any other hardware components such as LEDs,
-  buttons, sensors or communication peripherals (USB, BLE controller, ...).
+Once you've found an existing board that uses your SoC, you can usually start
+by copy/pasting its board directory and changing its contents for your
+hardware.
 
-- A software configuration (done using Kconfig) of features and peripheral
-  drivers. This default board configuration is subordinated to features
-  activation which is application responsibility. Though, it should also enable
-  a minimal set of features common to many applications and to applicable
-  project-provided :ref:`samples-and-demos`.
+You need to give your board a unique name. Run ``west boards`` for a list of
+names that are already taken, and pick something new. Let's say your board is
+called ``plank`` (please don't actually use that name).
 
+Start by creating the board directory ``zephyr/boards/<ARCH>/plank``, where
+``<ARCH>`` is your SoC's architecture subdirectory. (You don't have to put your
+board directory in the zephyr repository, but it's the easiest way to get
+started. See :ref:`custom_board_definition` for documentation on moving your
+board directory to a separate repository once it's working.)
+
+Your board directory should look like this:
+
+.. code-block:: none
+
+   boards/<ARCH>/plank
+   ├── board.cmake
+   ├── CMakeLists.txt
+   ├── doc
+   │   ├── plank.png
+   │   └── index.rst
+   ├── Kconfig.board
+   ├── Kconfig.defconfig
+   ├── plank_defconfig
+   ├── plank.dts
+   └── plank.yaml
+
+Replace ``plank`` with your board's name, of course.
+
+The mandatory files are:
+
+#. :file:`plank.dts`: a hardware description in :ref:`devicetree` format. This
+   declares your SoC, connectors, and any other hardware components such as
+   LEDs, buttons, sensors, or communication peripherals (USB, BLE controller,
+   etc).
+
+#. :file:`Kconfig.board`, :file:`Kconfig.defconfig`, :file:`plank_defconfig`:
+   software configuration in :ref:`kconfig` formats. This provides default
+   settings for software features and peripheral drivers.
+
+The optional files are:
+
+- :file:`board.cmake`: used for :ref:`flash-and-debug-support`
+- :file:`CMakeLists.txt`: if you need to add additional source files to
+  your build.
+
+  One common use for this file is to add a :file:`pinmux.c` file in your board
+  directory to the build, which configures pin controllers at boot time. In
+  that case, :file:`CMakeLists.txt` usually looks like this:
+
+  .. code-block:: cmake
+
+     if(CONFIG_PINMUX)
+       zephyr_library()
+       zephyr_library_sources(pinmux.c)
+       zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+     endif()
+
+- :file:`doc/index.rst`, :file:`doc/plank.png`: documentation for and a picture
+  of your board. You only need this if you're :ref:`contributing-your-board` to
+  Zephyr.
+- :file:`plank.yaml`: a YAML file with miscellaneous metadata used by the
+  :ref:`sanitycheck_script`.
 
 .. _default_board_configuration:
 
-Default board configuration
-***************************
+Write your devicetree
+*********************
 
-When porting Zephyr to a board, you must provide the board's default
-Kconfig configuration, which is used in application builds unless explicitly
-overridden.
+The devicetree file :file:`boards/<ARCH>/plank/plank.dts` describes your board
+hardware in the Devicetree Source (DTS) format (as usual, change ``plank`` to
+your board's name). If you're new to devicetree, see :ref:`devicetree-intro`.
+
+In general, :file:`plank.dts` should look like this:
+
+.. code-block:: none
+
+   /dts-v1/;
+   #include <your_soc_vendor/your_soc.dtsi>
+
+   / {
+   	model = "A human readable name";
+   	compatible = "yourcompany,plank";
+
+   	chosen {
+   		zephyr,console = &your_uart_console;
+   		zephyr,sram = &your_memory_node;
+   		/* other chosen settings  for your hardware */
+   	};
+
+   	/*
+   	 * Your board-specific hardware: buttons, LEDs, sensors, etc.
+   	 */
+
+   	leds {
+   		compatible = "gpio-leds";
+   		led0: led_0 {
+   			gpios = < /* GPIO your LED is hooked up to */ >;
+   			label = "LED 0";
+   		};
+   		/* ... other LEDs ... */
+   	};
+
+   	buttons {
+   		compatible = "gpio-keys";
+   		/* ... your button definitions ... */
+   	};
+
+   	/* These aliases are provided for compatibility with samples */
+   	aliases {
+   		led0 = &led0; /* now you support the blinky sample! */
+   		/* other aliases go here */
+   	};
+   };
+
+   &some_peripheral_you_want_to_enable { /* like a GPIO or SPI controller */
+   	status = "okay";
+   };
+
+   &another_peripheral_you_want {
+   	status = "okay";
+   };
+
+If you're in a hurry, simple hardware can usually be supported by copy/paste
+followed by trial and error. If you want to understand details, you will need
+to read the rest of the devicetree documentation and the devicetree
+specification.
+
+Write Kconfig files
+*******************
+
+Zephyr uses the Kconfig language to configure software features. Your board
+needs to provide some Kconfig settings before you can compile a Zephyr
+application for it.
 
 Setting Kconfig configuration values is documented in detail in
-:ref:`setting_configuration_values`, which you should go through. Note that the
-default board configuration might involve both :file:`<BOARD>_defconfig` and
-:file:`Kconfig.defconfig` files. The rest of this section contains some
-board-specific guidelines.
+:ref:`setting_configuration_values`.
 
-In order to provide consistency across the various boards and ease the work of
-users providing applications that are not board specific, the following
-guidelines should be followed when porting a board. Unless explicitly stated,
-peripherals should be disabled by default.
+There are three mandatory Kconfig files in the board directory for a board
+named ``plank``:
 
-- Configure and enable a working clock configuration, along with a tick source.
+.. code-block:: none
+
+   boards/<ARCH>/plank
+   ├── Kconfig.board
+   ├── Kconfig.defconfig
+   └── plank_defconfig
+
+:file:`Kconfig.board`
+  Included by :zephyr_file:`boards/Kconfig` to include your board
+  in the list of options.
+
+  This should at least contain a definition for a ``BOARD_PLANK`` option,
+  which looks something like this:
+
+  .. code-block:: none
+
+     config BOARD_PLANK
+     	bool "Plank board"
+     	depends on SOC_SERIES_YOUR_SOC_SERIES_HERE
+     	select SOC_PART_NUMBER_ABCDEFGH
+
+:file:`Kconfig.defconfig`
+  Board-specific default values for Kconfig options.
+
+  The entire file should be inside an ``if BOARD_PLANK`` / ``endif`` pair of
+  lines, like this:
+
+  .. code-block:: none
+
+     if BOARD_PLANK
+
+     # Always set CONFIG_BOARD here. This isn't meant to be customized,
+     # but is set as a "default" due to Kconfig language restrictions.
+     config BOARD
+     	default "plank"
+
+     # Other options you want enabled by default go next. Examples:
+
+     config FOO
+     	default y
+
+     if NETWORKING
+     config SOC_ETHERNET_DRIVER
+     	default y
+     endif # NETWORKING
+
+     endif # BOARD_PLANK
+
+:file:`plank_defconfig`
+  A Kconfig fragment that is merged as-is into the final build directory
+  :file:`.config` whenever an application is compiled for your board.
+
+  You should at least select your board's SOC and do any mandatory settings for
+  your system clock, console, etc. The results are architecture-specific, but
+  typically look something like this:
+
+  .. code-block:: none
+
+     CONFIG_SOC_${VENDOR_XYZ3000}=y                      /* select your SoC */
+     CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000   /* set up your clock, etc */
+     CONFIG_SERIAL=y
+
+Build, test, and fix
+********************
+
+Now it's time to build and test the application(s) you want to run on your
+board until you're satisfied.
+
+For example:
+
+.. code-block:: console
+
+   west build -b plank samples/hello_world
+   west flash
+
+For ``west flash`` to work, see :ref:`flash-and-debug-support` below. You can
+also just flash :file:`build/zephyr/zephyr.elf`, :file:`zephyr.hex`, or
+:file:`zephyr.bin` with any other tools you prefer.
+
+.. _porting-general-recommendations:
+
+General recommendations
+***********************
+
+For consistency and to make it easier for users to build generic applications
+that are not board specific for your board, please follow these guidelines
+while porting.
+
+- Unless explicitly recommended otherwise by this section, leave peripherals
+  and their drivers disabled by default.
+
+- Configure and enable a system clock, along with a tick source.
 
 - Provide pin and driver configuration that matches the board's valuable
   components such as sensors, buttons or LEDs, and communication interfaces
   such as USB, Ethernet connector, or Bluetooth/Wi-Fi chip.
 
-- When a well-known connector is present (such as used on an Arduino or
-  96board), configure pins to fit this connector.
+- If your board uses a well-known connector standard (like Arduino, Mikrobus,
+  Grove, or 96Boards connectors), add connector nodes to your DTS and configure
+  pin muxes accordingly.
 
 - Configure components that enable the use of these pins, such as
-  configuring an SPI instance for Arduino SPI.
+  configuring an SPI instance to use the usual Arduino SPI pins.
 
-- If available, configure and enable a serial output for the console.
+- If available, configure and enable a serial output for the console
+  using the ``zephyr,console`` chosen node in the devicetree.
 
-- Propose and configure a default network interface.
+- If your board supports networking, configure a default interface.
 
-- Enable all GPIO ports.
+- Enable all GPIO ports connected to peripherals or expansion connectors.
 
 - If available, enable pinmux and interrupt controller drivers.
+
+.. _flash-and-debug-support:
+
+Flash and debug support
+***********************
+
+Zephyr supports :ref:`west-build-flash-debug` via west extension commands.
+
+To add ``west flash`` and ``west debug`` support for your board, you need to
+create a :file:`board.cmake` file in your board directory. This file's job is
+to configure a "runner" for your board. (There's nothing special you need to
+do to get ``west build`` support for your board.)
+
+"Runners" are Zephyr-specific Python classes that wrap :ref:`flash and debug
+host tools <debug-host-tools>` and integrate with west and the zephyr build
+system to support ``west flash`` and related commands. Each runner supports
+flashing, debugging, or both. You need to configure the arguments to these
+Python scripts in your :file:`board.cmake` to support those commands like this
+example :file:`board.cmake`:
+
+.. code-block:: cmake
+
+   board_runner_args(nrfjprog "--nrf-family=NRF52")
+   board_runner_args(jlink "--device=nrf52" "--speed=4000")
+   board_runner_args(pyocd "--target=nrf52" "--frequency=4000000")
+
+   include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
+   include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+   include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
+
+This example configures the ``nrfjprog``, ``jlink``, and ``pyocd`` runners.
+
+.. warning::
+
+   Runners usually have names which match the tools they wrap, so the ``jlink``
+   runner wraps Segger's J-Link tools, and so on. But the runner command line
+   options like ``--speed`` etc. are specific to the Python scripts.
+
+For more details:
+
+- Run ``west flash --context`` to see a list of available runners which support
+  flashing, and ``west flash --context -r <RUNNER>`` to view the specific options
+  available for an individual runner.
+- Run ``west debug --context`` and ``west debug --context <RUNNER>`` to get
+  the same output for runners which support debugging.
+- Run ``west flash --help`` and ``west debug --help`` for top-level options
+  for flashing and debugging.
+- See :ref:`west-runner` for Python APIs.
+- Look for :file:`board.cmake` files for other boards similar to your own for
+  more examples.
+
+To see what a ``west flash`` or ``west debug`` command is doing exactly, run it
+in verbose mode:
+
+.. code-block:: sh
+
+   west --verbose flash
+   west --verbose debug
+
+Verbose mode prints any host tool commands the runner uses.
+
+The order of the ``include()`` calls in your :file:`board.cmake` matters. The
+first ``include`` sets the default runner if it's not already set. For example,
+including ``nrfjprog.board.cmake`` first means that ``nrjfprog`` is the default
+flash runner for this board. Since ``nrfjprog`` does not support debugging,
+``jlink`` is the default debug runner.
+
+.. _contributing-your-board:
+
+Contributing your board
+***********************
+
+If you want to contribute your board to Zephyr, first -- thanks!
+
+There are some extra things you'll need to do:
+
+#. Make sure you've followed all the :ref:`porting-general-recommendations`.
+   They are requirements for boards included with Zephyr.
+
+#. Add documentation for your board using the template file
+   :zephyr_file:`doc/templates/board.tmpl`. See :ref:`zephyr_doc` for
+   information on how to build your documentation before submitting
+   your pull request.
+
+#. Prepare a pull request adding your board which follows the
+   :ref:`contribute_guidelines`.

doc/guides/porting/index.rst

@@ -3,9 +3,7 @@
 Porting
 #######
 
-This section contains details regarding porting the Zephyr kernel to new
-architectures, SoCs and boards. This section also describes the standard
-API interfaces supported by Zephyr.
+These pages document how to port Zephyr to new hardware.
 
 .. toctree::
    :maxdepth: 1

doc/guides/test/sanitycheck.rst

@@ -91,7 +91,6 @@ required for best test coverage for this specific board:
     - gpio
     - usb_device
     - watchdog
-    - hwinfo
     - can
     - pwm
   testing:

doc/guides/west/build-flash-debug.rst

@@ -532,8 +532,8 @@ For example, to print usage information about the ``jlink`` runner::
 
 .. _west-runner:
 
-Implementation Details
-**********************
+runners package API
+*******************
 
 The flash and debug commands are implemented as west *extension
 commands*: that is, they are west commands whose source code lives

doc/guides/west/config.rst

@@ -45,12 +45,12 @@ There are three types of configuration file:
      combination of :envvar:`%HOMEDRIVE%` and :envvar:`%HOMEPATH%`.
 
 3. **Local**: Settings in this file affect west's behavior for the
-   current :term:`west installation`. The file is :file:`.west/config`, relative
-   to the installation's root directory.
+   current :term:`west workspace`. The file is :file:`.west/config`, relative
+   to the workspace's root directory.
 
 A setting in a file which appears lower down on this list overrides an earlier
 setting. For example, if ``color.ui`` is ``true`` in the system's configuration
-file, but ``false`` in the installation's, then the final value is
+file, but ``false`` in the workspace's, then the final value is
 ``false``. Similarly, settings in the user configuration file override system
 settings, and so on.
 
@@ -76,11 +76,11 @@ To set ``manifest.path`` to :file:`some-other-manifest`:
 
 Doing the above means that commands like ``west update`` will look for the
 :term:`west manifest` inside the :file:`some-other-manifest` directory
-(relative to the installation root directory) instead of the directory given to
+(relative to the workspace root directory) instead of the directory given to
 ``west init``, so be careful!
 
 To read ``zephyr.base``, the value which will be used as ``ZEPHYR_BASE`` if it
-is unset in the calling environment (also relative to the installation root):
+is unset in the calling environment (also relative to the workspace root):
 
 .. code-block:: console
 
@@ -101,7 +101,7 @@ zephyr``.)
 
 To set ``color.ui`` to ``false`` in the global (user-wide) configuration file,
 so that west will no longer print colored output for that user when run in any
-installation:
+workspace:
 
 .. code-block:: console
 
@@ -136,7 +136,7 @@ commands are documented in the pages for those commands.
    * - ``commands.allow_extensions``
      - Boolean, default ``true``, disables :ref:`west-extensions` if ``false``
    * - ``manifest.path``
-     - String, relative path from the :term:`west installation` root directory
+     - String, relative path from the :term:`west workspace` root directory
        to the manifest repository used by ``west update`` and other commands
        which parse the manifest. Set locally by ``west init``.
    * - ``update.fetch``

doc/guides/west/extensions.rst

@@ -41,7 +41,8 @@ globally for whenever you run west, use:
 
    west config --global commands.allow_extensions false
 
-If you want to, you can then re-enable them in a particular installation with:
+If you want to, you can then re-enable them in a particular :term:`west
+workspace` with:
 
 .. code-block:: console
 

doc/guides/west/manifest.rst

@@ -18,7 +18,7 @@ introduction and command overview, see :ref:`west-multi-repo`.
 Multiple Repository Model
 *************************
 
-West's view of the repositories in a :term:`west installation`, and their
+West's view of the repositories in a :term:`west workspace`, and their
 history, looks like the following figure (though some parts of this example are
 specific to upstream Zephyr's use of west):
 
@@ -32,7 +32,7 @@ specific to upstream Zephyr's use of west):
 The history of the manifest repository is the line of Git commits which is
 "floating" on top of the gray plane. Parent commits point to child commits
 using solid arrows. The plane below contains the Git commit history of the
-repositories in the installation, with each project repository boxed in by a
+repositories in the workspace, with each project repository boxed in by a
 rectangle. Parent/child commit relationships in each repository are also shown
 with solid arrows.
 
@@ -124,7 +124,7 @@ example, you might use ``git@example.com:base1`` if ``remote1`` supported Git
 over SSH as well. Anything acceptable to Git will work.
 
 The ``projects`` subsection contains a sequence describing the project
-repositories in the west installation. Every project has a unique name. You can
+repositories in the west workspace. Every project has a unique name. You can
 specify what Git remote URLs to use when cloning and fetching the projects,
 what revisions to track, and where the project should be stored on the local
 file system.
@@ -157,7 +157,7 @@ In this manifest:
   with a ``/`` and the project ``name`` to form the URL.
 
   Locally, this project will be cloned at path ``extra/project-1`` relative to
-  the west installation's root directory, since it has an explicit ``path``
+  the west workspace's root directory, since it has an explicit ``path``
   attribute with this value.
 
   Since the project has no ``revision`` specified, ``master`` is used by
@@ -208,7 +208,7 @@ The list of project keys and their usage follows. Sometimes we'll refer to the
   A project revision can be a branch, tag, or SHA. The default ``revision`` is
   ``master`` if not otherwise specified.
 - ``path``: Optional. Relative path specifying where to clone the repository
-  locally, relative to the top directory in the west installation. If missing,
+  locally, relative to the top directory in the west workspace. If missing,
   the project's ``name`` is used as a directory name.
 - ``clone-depth``: Optional. If given, a positive integer which creates a
   shallow history in the cloned repository limited to the given number of
@@ -254,7 +254,7 @@ The ``self`` subsection can be used to control the behavior of the
 manifest repository itself. Its value is a map with the following keys:
 
 - ``path``: Optional. The path to clone the manifest repository into, relative
-  to the west installation's root directory. If not given, the basename of the
+  to the west workspace's root directory. If not given, the basename of the
   path component in the manifest repository URL will be used by default.  For
   example, if the URL is ``https://git.example.com/project-repo``, the manifest
   repository would be cloned to the directory :file:`project-repo`.
@@ -411,7 +411,7 @@ You have a source code repository you want to use with Zephyr v1.14.1 LTS.  You
 want to maintain the whole thing using west. You don't want to modify any of
 the mainline repositories.
 
-In other words, the west installation you want looks like this:
+In other words, the west workspace you want looks like this:
 
 .. code-block:: none
 
@@ -441,7 +441,7 @@ You can do this with the following :file:`my-repo/west.yml`:
          revision: v1.14.1
          import: true
 
-You can then create the installation on your computer like this, assuming
+You can then create the workspace on your computer like this, assuming
 ``my-repo`` is hosted at ``https://git.example.com/my-repo``:
 
 .. code-block:: console
@@ -480,7 +480,7 @@ master`` for the zephyr repository:
          revision: master
          import: true
 
-You can create the installation in the same way:
+You can create the workspace in the same way:
 
 .. code-block:: console
 
@@ -711,7 +711,7 @@ Example 2.3: Continuous Integration overrides
 ---------------------------------------------
 
 Your continuous integration system needs to fetch and test multiple
-repositories in your west installation from a developer's forks instead of your
+repositories in your west workspace from a developer's forks instead of your
 mainline development trees, to see if the changes all work well together.
 
 Starting with :ref:`west-manifest-ex2.2`, the CI scripts add a
@@ -890,7 +890,7 @@ Example 3.3: Downstream with path blacklist
 -------------------------------------------
 
 Here's an example showing how to blacklist all vendor HALs from mainline by
-common path prefix in the installation, add your own version for the chip
+common path prefix in the workspace, add your own version for the chip
 you're targeting, and keep everything else.
 
 .. code-block:: yaml

doc/guides/west/moving-to-west.rst

@@ -37,13 +37,13 @@ instead. See :ref:`west-troubleshooting` for advice on common issues.
    The name :file:`zephyrproject` is recommended, but you can choose any name
    with no spaces anywhere in the path.
 
-#. Create a :ref:`west installation <west-installation>` using the zephyr
+#. Create a :ref:`west workspace <west-workspace>` using the zephyr
    repository as a local manifest repository::
 
      west init -l zephyr
 
    This creates :file:`zephyrproject/.west`, marking the root of your
-   installation, and does some other setup. It will not change the contents of
+   workspace, and does some other setup. It will not change the contents of
    the zephyr repository in any way.
 
 #. Clone the rest of the repositories used by zephyr::

doc/guides/west/repo-tool.rst

@@ -14,19 +14,20 @@ rationale, and motivation.
    multi-repo work, not to replace it. For tasks that only operate on one
    repository, just use plain Git commands.
 
-.. _west-installation:
+.. _west-workspace:
 
 Introduction
 ************
 
 West's built-in commands allow you to work with projects composed of multiple
 Git repositories installed under a common parent directory, which we call a
-*west installation*. This works similarly to `Git Submodules
+*west workspace* (before west 0.7, this was called a *west installation*). This
+works similarly to `Git Submodules
 <https://git-scm.com/book/en/v2/Git-Tools-Submodules>`_ and Google's `repo
 <https://gerrit.googlesource.com/git-repo/>`_.
 
-A west installation is the result of running the ``west init`` command, which
-is described in more detail below. For upstream Zephyr, the installation looks
+A west workspace is the result of running the ``west init`` command, which
+is described in more detail below. For upstream Zephyr, the workspace looks
 like this:
 
 .. code-block:: none
@@ -43,34 +44,34 @@ like this:
    ├── net-tools
    └── [ ... other projects ...]
 
-Above, :file:`zephyrproject` is the name of the west installation's root
+Above, :file:`zephyrproject` is the name of the west workspace's root
 directory. This name is just an example -- it could be anything, like ``z``,
-``my-zephyr-installation``, etc.  The file :file:`.west/config` is the
-installation's :ref:`local configuration file <west-config>`.
+``my-zephyr-workspace``, etc.  The file :file:`.west/config` is the
+workspace's :ref:`local configuration file <west-config>`.
 
-Every west installation contains exactly one *manifest repository*, which is a
+Every west workspace contains exactly one *manifest repository*, which is a
 Git repository containing a file named :file:`west.yml`, which is the *west
 manifest*. The location of the manifest repository is given by the
 :ref:`manifest.path configuration option <west-config-index>` in the local
 configuration file. The manifest file, along with west's configuration files,
-controls the installation's behavior. For upstream Zephyr, :file:`zephyr` is
+controls the workspace's behavior. For upstream Zephyr, :file:`zephyr` is
 the manifest repository, but you can configure west to use any Git repository
-in the installation as the manifest repository. The only requirement is that it
+in the workspace as the manifest repository. The only requirement is that it
 contains a valid manifest file. See :ref:`west-manifests` for more details on
 what this means.
 
 Both of the :file:`tinycbor` and :file:`net-tools` directories are *projects*
-managed by west, and configured in the manifest file. A west installation can
+managed by west, and configured in the manifest file. A west workspace can
 contain arbitrarily many projects. As shown above, projects can be located
-anywhere in the installation. They don't have to be subdirectories of the
+anywhere in the workspace. They don't have to be subdirectories of the
 manifest directory, and they can be inside of arbitrary subdirectories inside
-the installation's root directory. By default, the Zephyr build system uses
-west to get the locations of all the projects in the installation, so any code
+the workspace's root directory. By default, the Zephyr build system uses
+west to get the locations of all the projects in the workspace, so any code
 they contain can be used by applications. This behavior can be overridden using
 the ``ZEPHYR_MODULES`` CMake variable; see
 :zephyr_file:`cmake/zephyr_module.cmake` for details.
 
-Finally, any repository managed by a west installation can contain
+Finally, any repository managed by a west workspace can contain
 :ref:`extension commands <west-extensions>`, which are extra west commands
 provided by that project. This includes the manifest repository and any project
 repository.
@@ -78,82 +79,180 @@ repository.
 Topologies supported
 ********************
 
-The following three source code topologies supported by west:
+The following are example source code topologies supported by west.
 
-* **T1**: Star topology with zephyr as the manifest repository:
+- T1: star topology, zephyr is the manifest repository
+- T2: star topology, a Zephyr application is the manifest repository
+- T3: forest topology, freestanding manifest repository
 
-  - The zephyr repository acts as the central repository and includes a
-    complete list of projects used upstream
-  - Default (upstream) configuration
-  - Analogy with existing mechanisms: Git sub-modules with zephyr as the
-    super-project
-  - See :ref:`west-installation` for how mainline Zephyr is an example
-    of this topology
+T1: Star topology, zephyr is the manifest repository
+====================================================
 
-* **T2**: Star topology with an application repository as the manifest
-  repository:
+- The zephyr repository acts as the central repository and specifies
+  its :ref:`modules` in its :file:`west.yml`
+- Analogy with existing mechanisms: Git submodules with zephyr as the
+  super-project
 
-  - A repository containing a Zephyr application acts as the central repository
-    and includes a complete list of other projects, including the zephyr
-    repository, required to build it
-  - Useful for those focused on a single application
-  - Analogy with existing mechanisms: Git sub-modules with the application as
-    the super-project, zephyr and other projects as sub-modules
-  - An installation using this topology could look like this:
+This is the default. See :ref:`west-workspace` for how mainline Zephyr is an
+example of this topology.
 
-    .. code-block:: none
+.. _west-t2:
 
-       app-manifest-installation
-       ├── application
-       │   ├── CMakeLists.txt
-       │   ├── prj.conf
-       │   ├── src
-       │   │   └── main.c
-       │   └── west.yml
-       ├── modules
-       │   └── lib
-       │       └── tinycbor
-       └── zephyr
+T2: Star topology, application is the manifest repository
+=========================================================
 
-* **T3**: Forest topology:
+- Useful for those focused on a single application
+- A repository containing a Zephyr application acts as the central repository
+  and names other projects required to build it in its :file:`west.yml`. This
+  includes the zephyr repository and any modules.
+- Analogy with existing mechanisms: Git submodules with the application as
+  the super-project, zephyr and other projects as submodules
 
-  - A dedicated manifest repository which contains no Zephyr source code,
-    and specifies a list of projects all at the same "level"
-  - Useful for downstream distributions with no "central" repository
-  - Analogy with existing mechanisms: Google repo-based source distribution
-  - An installation using this topology could look like this:
+A workspace using this topology looks like this:
 
-    .. code-block:: none
+.. code-block:: none
 
-       forest
-       ├── app1
-       │   ├── CMakeLists.txt
-       │   ├── prj.conf
-       │   └── src
-       │       └── main.c
-       ├── app2
-       │   ├── CMakeLists.txt
-       │   ├── prj.conf
-       │   └── src
-       │       └── main.c
-       ├── manifest-repo
-       │   └── west.yml
-       ├── modules
-       │   └── lib
-       │       └── tinycbor
-       └── zephyr
+   west-workspace
+   ├── application
+   │   ├── CMakeLists.txt
+   │   ├── prj.conf
+   │   ├── src
+   │   │   └── main.c
+   │   └── west.yml
+   ├── modules
+   │   └── lib
+   │       └── tinycbor
+   └── zephyr
+
+Here is an example :file:`application/west.yml` which uses
+:ref:`west-manifest-import`, available since west 0.7, to import Zephyr v2.2.0
+and its modules into the application manifest file:
+
+.. code-block:: yaml
+
+   # Example T2 west.yml, using manifest imports.
+   manifest:
+     remotes:
+       - name: zephyrproject-rtos
+         url-base: https://github.com/zephyrproject-rtos
+     projects:
+       - name: zephyr
+         remote: zephyrproject-rtos
+         revision: v2.2.0
+         import: true
+     self:
+       path: application
+
+You can still selectively "override" individual Zephyr modules if you use
+``import:`` in this way; see :ref:`west-manifest-ex1.3` for an example.
+
+Another way to do the same thing is to copy/paste :file:`zephyr/west.yml`
+to :file:`application/west.yml`, adding an entry for the zephyr
+project itself, like this:
+
+.. code-block:: yaml
+
+   # Equivalent to the above, but with manually maintained Zephyr modules.
+   manifest:
+     remotes:
+       - name: zephyrproject-rtos
+         url-base: https://github.com/zephyrproject-rtos
+     defaults:
+       remote: zephyrproject-rtos
+     projects:
+       - name: zephyr
+         revision: v2.2.0
+         west-commands: scripts/west-commands.yml
+       - name: net-tools
+         revision: some-sha-goes-here
+         path: tools/net-tools
+       # ... other Zephyr modules go here ...
+     self:
+       path: application
+
+(The ``west-commands`` is there for :ref:`west-build-flash-debug` and other
+Zephyr-specific :ref:`west-extensions`. It's not necessary when using
+``import``.)
+
+The main advantage to using ``import`` is not having to track the revisions of
+imported projects separately. In the above example, using ``import`` means
+Zephyr's :ref:`module <modules>` versions are automatically determined from the
+:file:`zephyr/west.yml` revision, instead of having to be copy/pasted (and
+maintained) on their own.
+
+T3: Forest topology
+===================
+
+- Useful for those supporting multiple independent applications or downstream
+  distributions with no "central" repository
+- A dedicated manifest repository which contains no Zephyr source code,
+  and specifies a list of projects all at the same "level"
+- Analogy with existing mechanisms: Google repo-based source distribution
+
+A workspace using this topology looks like this:
+
+.. code-block:: none
+
+   west-workspace
+   ├── app1
+   │   ├── CMakeLists.txt
+   │   ├── prj.conf
+   │   └── src
+   │       └── main.c
+   ├── app2
+   │   ├── CMakeLists.txt
+   │   ├── prj.conf
+   │   └── src
+   │       └── main.c
+   ├── manifest-repo
+   │   └── west.yml
+   ├── modules
+   │   └── lib
+   │       └── tinycbor
+   └── zephyr
+
+Here is an example T3 :file:`manifest-repo/west.yml` which uses
+:ref:`west-manifest-import`, available since west 0.7, to import Zephyr
+v2.2.0 and its modules, then add the ``app1`` and ``app2`` projects:
+
+.. code-block:: yaml
+
+   manifest:
+     remotes:
+       - name: zephyrproject-rtos
+         url-base: https://github.com/zephyrproject-rtos
+       - name: your-git-server
+         url-base: https://git.example.com/your-company
+     defaults:
+       remote: your-git-server
+     projects:
+       - name: zephyr
+         remote: zephyrproject-rtos
+         revision: v2.2.0
+         import: true
+       - name: app1
+         revision: SOME_SHA_OR_BRANCH_OR_TAG
+       - name: app2
+         revision: ANOTHER_SHA_OR_BRANCH_OR_TAG
+     self:
+       path: manifest-repo
+
+You can also do this "by hand" by copy/pasting :file:`zephyr/west.yml`
+as shown :ref:`above <west-t2>` for the T2 topology, with the same caveats.
 
 .. _west-struct:
 
 West Structure
 **************
 
-West's code is distributed via PyPI in a `namespace package`_ named ``west``.
-See :ref:`west-apis` for API documentation.
+West's code is distributed via PyPI in a Python package named ``west``. See
+:ref:`west-apis` for API documentation.
 
-This distribution also includes a launcher executable, also named ``west``. When
-west is installed, the launcher is placed by :file:`pip3` somewhere in the
-user's ``PATH``. This is the command-line entry point.
+This distribution also includes a launcher executable, also named ``west``.
+When west is installed, the launcher is placed by :file:`pip3` somewhere in the
+user's filesystem (exactly where depends on the operating system, but should be
+on the ``PATH`` :ref:`environment variable <env_vars>`). This launcher is the
+command-line entry point.
 
 .. _west-manifest-rev:
 
@@ -205,7 +304,7 @@ The ``west init`` and ``west update`` multi-repo commands are the most
 important to understand.
 
 - ``west init [-l] [-m URL] [--mr REVISION] [PATH]``: create a west
-  installation in directory :file:`PATH` (i.e. :file:`.west` etc. will be
+  workspace in directory :file:`PATH` (i.e. :file:`.west` etc. will be
   created there). If the ``PATH`` argument is not given, the current working
   directory is used. This command does not clone any of the projects in the
   manifest; that is done the next time ``west update`` is run.
@@ -213,11 +312,11 @@ important to understand.
   This command can be invoked in two ways:
 
   1. If you already have a local clone of the zephyr repository and want to
-     create a west installation around it, you can use the ``-l`` switch to
+     create a west workspace around it, you can use the ``-l`` switch to
      pass its path to west, as in: ``west init -l path/to/zephyr``. This is
      the only reason to use ``-l``.
 
-  2. Otherwise, omit ``-l`` to create a new installation from a remote manifest
+  2. Otherwise, omit ``-l`` to create a new workspace from a remote manifest
      repository. You can give the manifest URL using the ``-m`` switch, and its
      revision using ``--mr``. For example, invoking west with: ``west init -m
      https://github.com/zephyrproject-rtos/zephyr --mr v1.15.0`` would clone

doc/guides/west/troubleshooting.rst

@@ -16,8 +16,8 @@ If you see this error when running ``west init``:
    (choose from 'init', 'update', 'list', 'manifest', 'diff',
    'status', 'forall', 'config', 'selfupdate', 'help')
 
-Then you have an old version of west installed, and are trying to use it in an
-installation that requires a more recent version.
+Then you have an old version of west installed, and are trying to use it in a
+workspace that requires a more recent version.
 
 The easiest way to resolve this issue is to upgrade west and retry as follows:
 
@@ -29,23 +29,24 @@ The easiest way to resolve this issue is to upgrade west and retry as follows:
    this step.)
 
 #. Completely remove the :file:`zephyrproject/.west` directory (if you don't,
-   you will get the "already in an installation" error message discussed next).
+   you will get the "already in a workspace" error message discussed next).
 
 #. Run ``west init`` again.
 
 "already in an installation"
 ****************************
 
-You may see this error when running ``west init``:
+You may see this error when running ``west init`` with west 0.6:
 
 .. code-block:: none
 
    FATAL ERROR: already in an installation (<some directory>), aborting
 
-If this is unexpected and you're really trying to create a new installation,
+If this is unexpected and you're really trying to create a new west workspace,
 then it's likely that west is using the :envvar:`ZEPHYR_BASE` :ref:`environment
-variable <env_vars>` to locate a west installation elsewhere on your system.
-This is intentional behavior; it allows you to put your Zephyr applications in
-any directory and still use west.
+variable <env_vars>` to locate a workspace elsewhere on your system.
+
+This is intentional; it allows you to put your Zephyr applications in
+any directory and still use west to build, flash, and debug them, for example.
 
 To resolve this issue, unset :envvar:`ZEPHYR_BASE` and try again.

doc/guides/west/without-west.rst

@@ -71,7 +71,7 @@ west commands wrap).
 
 If you want to use these build system targets but do not want to
 install west on your system using ``pip``, it is possible to do so
-by manually creating a :term:`west installation`:
+by manually creating a :term:`west workspace`:
 
 .. code-block:: console
 

doc/reference/runtime_conf/settings/settings.rst

@@ -279,5 +279,22 @@ API Reference
 
 The Settings subsystem APIs are provided by ``settings.h``:
 
+API for general settings usage
+==============================
 .. doxygengroup:: settings
    :project: Zephyr
+
+API for key-name processing
+===========================
+.. doxygengroup:: settings_name_proc
+   :project: Zephyr
+
+API for runtime settings manipulation
+=====================================
+.. doxygengroup:: settings_rt
+   :project: Zephyr
+
+API of backend interface
+========================
+..  doxygengroup:: settings_backend
+   :project: Zephyr

doc/security/index.rst

@@ -14,3 +14,4 @@ for ensuring security is addressed within the Zephyr project.
    secure-coding.rst
    sensor-threat.rst
    hardening-tool.rst
+   vulnerabilities.rst

doc/security/vulnerabilities.rst

@@ -0,0 +1,25 @@
+.. _vulnerabilities:
+
+Vulnerabilities
+###############
+
+This page collects all of the vulnerabilities that are discovered and
+fixed in each release.  It will also often have more details than is
+available in the releases.  Some vulnerabilities are deemed to be
+sensitive, and will not be publically discussed until there is
+sufficient time to fix them.  Because the release notes are locked to
+a version, the information here can be updated after the embargo is
+lifted.
+
+Release 1.14.0 and 2.0.0
+------------------------
+
+The following security vulnerability (CVE) was addressed in this
+release:
+
+* Fixes CVE-2019-9506: The Bluetooth BR/EDR specification up to and
+  including version 5.1 permits sufficiently low encryption key length
+  and does not prevent an attacker from influencing the key length
+  negotiation. This allows practical brute-force attacks (aka "KNOB")
+  that can decrypt traffic and inject arbitrary ciphertext without the
+  victim noticing.

drivers/adc/adc_mchp_xec.c

@@ -168,12 +168,14 @@ static int adc_xec_start_read(struct device *dev,
 
 	/* Setup ADC resolution */
 	reg = adc_regs->sar_control_reg;
-	reg &= ~MCHP_ADC_SAR_CTRL_RES_MASK;
+	reg &= ~(MCHP_ADC_SAR_CTRL_RES_MASK |
+		 (1 << MCHP_ADC_SAR_CTRL_SHIFTD_POS));
 
 	if (sequence->resolution == 12) {
 		reg |= MCHP_ADC_SAR_CTRL_RES_12_BITS;
 	} else if (sequence->resolution == 10) {
 		reg |= MCHP_ADC_SAR_CTRL_RES_10_BITS;
+		reg |= MCHP_ADC_SAR_CTRL_SHIFTD_EN;
 	} else {
 		return -EINVAL;
 	}

drivers/clock_control/clock_stm32g4.c

@@ -29,6 +29,11 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
 	pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
 	pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
 	pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
+
+	/* set power boost mode for sys clock greater than 150MHz */
+	if (sys_clock_hw_cycles_per_sec() >= MHZ(150)) {
+		LL_PWR_EnableRange1BoostMode();
+	}
 }
 #endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
 

drivers/clock_control/clock_stm32l4_wb.c

@@ -30,6 +30,12 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
 	pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
 	pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
 	pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
+#ifdef PWR_CR5_R1MODE
+	/* set power boost mode for sys clock greater than 80MHz */
+	if (sys_clock_hw_cycles_per_sec() >= MHZ(80)) {
+		LL_PWR_EnableRange1BoostMode();
+	}
+#endif /* PWR_CR5_R1MODE */
 }
 #endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
 

drivers/ethernet/Kconfig.sam_gmac

@@ -20,9 +20,14 @@ config ETH_SAM_GMAC_NAME
 	  required by all driver API functions. Device name has to be unique.
 
 config ETH_SAM_GMAC_QUEUES
-	int "Number of hardware TX and RX queues"
+	int "Number of active hardware TX and RX queues"
 	default 1
-	range 1 3
+	range 1 1 if SOC_SERIES_SAM4E
+	range 1 3 if !SOC_SERIES_SAM4E && \
+		     !SOC_ATMEL_SAME70_REVB && \
+		     !SOC_ATMEL_SAMV71_REVB
+	range 1 6 if SOC_ATMEL_SAME70_REVB || \
+		     SOC_ATMEL_SAMV71_REVB
 	help
 	  Select the number of hardware queues used by the driver. Packets will be
 	  routed to appropriate queues based on their priority.
@@ -44,6 +49,9 @@ config ETH_SAM_GMAC_FORCED_QUEUE
 	default 0
 	range 0 1 if ETH_SAM_GMAC_QUEUES = 2
 	range 0 2 if ETH_SAM_GMAC_QUEUES = 3
+	range 0 3 if ETH_SAM_GMAC_QUEUES = 4
+	range 0 4 if ETH_SAM_GMAC_QUEUES = 5
+	range 0 5 if ETH_SAM_GMAC_QUEUES = 6
 	help
 	  Which queue to force the routing to. This affects both the TX and RX queues
 	  setup.

drivers/ethernet/eth_mcux.c

@@ -399,18 +399,29 @@ static void eth_mcux_phy_setup(void)
 {
 #ifdef CONFIG_SOC_SERIES_IMX_RT
 	const u32_t phy_addr = 0U;
-	u32_t status;
+	status_t res;
+	u32_t oms_override;
 
-	/* Prevent PHY entering NAND Tree mode override*/
-	ENET_StartSMIRead(ENET, phy_addr, PHY_OMS_STATUS_REG,
-		kENET_MiiReadValidFrame);
-	status = ENET_ReadSMIData(ENET);
+	/* Disable MII interrupts to prevent triggering PHY events. */
+	ENET_DisableInterrupts(ENET, ENET_EIR_MII_MASK);
 
-	if (status & PHY_OMS_NANDTREE_MASK) {
-		status &= ~PHY_OMS_NANDTREE_MASK;
-		ENET_StartSMIWrite(ENET, phy_addr, PHY_OMS_OVERRIDE_REG,
-			kENET_MiiWriteValidFrame, status);
+	/* Prevent PHY entering NAND Tree mode override. */
+	res = PHY_Read(ENET, phy_addr, PHY_OMS_OVERRIDE_REG, &oms_override);
+	if (res != kStatus_Success) {
+		LOG_WRN("Reading PHY reg failed (status 0x%x)", res);
+	} else {
+		if (oms_override & PHY_OMS_NANDTREE_MASK) {
+			oms_override &= ~PHY_OMS_NANDTREE_MASK;
+			res = PHY_Write(ENET, phy_addr, PHY_OMS_OVERRIDE_REG,
+					oms_override);
+			if (res != kStatus_Success) {
+				LOG_WRN("Writing PHY reg failed (status 0x%x)",
+					res);
+			}
+		}
 	}
+
+	ENET_EnableInterrupts(ENET, ENET_EIR_MII_MASK);
 #endif
 }
 

drivers/ethernet/eth_sam_gmac.c

@@ -66,7 +66,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 	"due to the granularity of RX DMA"
 #endif
 
-#if (CONFIG_ETH_SAM_GMAC_BUF_RX_COUNT + 1) * CONFIG_ETH_SAM_GMAC_QUEUES \
+#if (CONFIG_ETH_SAM_GMAC_BUF_RX_COUNT + 1) * GMAC_ACTIVE_QUEUE_NUM \
 	> CONFIG_NET_BUF_RX_COUNT
 #error Not enough RX buffers to allocate descriptors for each HW queue
 #endif
@@ -75,49 +75,269 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 /* RX descriptors list */
 static struct gmac_desc rx_desc_que0[MAIN_QUEUE_RX_DESC_COUNT]
 	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#if GMAC_PRIORITY_QUEUE_NUM >= 1
 static struct gmac_desc rx_desc_que1[PRIORITY_QUEUE1_RX_DESC_COUNT]
 	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 2
 static struct gmac_desc rx_desc_que2[PRIORITY_QUEUE2_RX_DESC_COUNT]
 	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 3
+static struct gmac_desc rx_desc_que3[PRIORITY_QUEUE3_RX_DESC_COUNT]
+	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 4
+static struct gmac_desc rx_desc_que4[PRIORITY_QUEUE4_RX_DESC_COUNT]
+	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 5
+static struct gmac_desc rx_desc_que5[PRIORITY_QUEUE5_RX_DESC_COUNT]
+	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#endif
+
 /* TX descriptors list */
 static struct gmac_desc tx_desc_que0[MAIN_QUEUE_TX_DESC_COUNT]
 	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#if GMAC_PRIORITY_QUEUE_NUM >= 1
 static struct gmac_desc tx_desc_que1[PRIORITY_QUEUE1_TX_DESC_COUNT]
 	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 2
 static struct gmac_desc tx_desc_que2[PRIORITY_QUEUE2_TX_DESC_COUNT]
 	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 3
+static struct gmac_desc tx_desc_que3[PRIORITY_QUEUE3_TX_DESC_COUNT]
+	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 4
+static struct gmac_desc tx_desc_que4[PRIORITY_QUEUE4_TX_DESC_COUNT]
+	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 5
+static struct gmac_desc tx_desc_que5[PRIORITY_QUEUE5_TX_DESC_COUNT]
+	__nocache __aligned(GMAC_DESC_ALIGNMENT);
+#endif
 
 /* RX buffer accounting list */
 static struct net_buf *rx_frag_list_que0[MAIN_QUEUE_RX_DESC_COUNT];
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 static struct net_buf *rx_frag_list_que1[PRIORITY_QUEUE1_RX_DESC_COUNT];
 #endif
-#if GMAC_PRIORITY_QUEUE_NO == 2
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 2
 static struct net_buf *rx_frag_list_que2[PRIORITY_QUEUE2_RX_DESC_COUNT];
 #endif
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 3
+static struct net_buf *rx_frag_list_que3[PRIORITY_QUEUE3_RX_DESC_COUNT];
+#endif
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 4
+static struct net_buf *rx_frag_list_que4[PRIORITY_QUEUE4_RX_DESC_COUNT];
+#endif
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 5
+static struct net_buf *rx_frag_list_que5[PRIORITY_QUEUE5_RX_DESC_COUNT];
+#endif
+
 #if GMAC_MULTIPLE_TX_PACKETS == 1
 /* TX buffer accounting list */
 static struct net_buf *tx_frag_list_que0[MAIN_QUEUE_TX_DESC_COUNT];
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 static struct net_buf *tx_frag_list_que1[PRIORITY_QUEUE1_TX_DESC_COUNT];
 #endif
-#if GMAC_PRIORITY_QUEUE_NO == 2
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 2
 static struct net_buf *tx_frag_list_que2[PRIORITY_QUEUE2_TX_DESC_COUNT];
 #endif
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 3
+static struct net_buf *tx_frag_list_que3[PRIORITY_QUEUE3_TX_DESC_COUNT];
+#endif
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 4
+static struct net_buf *tx_frag_list_que4[PRIORITY_QUEUE4_TX_DESC_COUNT];
+#endif
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 5
+static struct net_buf *tx_frag_list_que5[PRIORITY_QUEUE5_TX_DESC_COUNT];
+#endif
+
 #if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
 /* TX frames accounting list */
 static struct net_pkt *tx_frame_list_que0[CONFIG_NET_PKT_TX_COUNT + 1];
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 static struct net_pkt *tx_frame_list_que1[CONFIG_NET_PKT_TX_COUNT + 1];
 #endif
-#if GMAC_PRIORITY_QUEUE_NO == 2
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 2
 static struct net_pkt *tx_frame_list_que2[CONFIG_NET_PKT_TX_COUNT + 1];
 #endif
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 3
+static struct net_pkt *tx_frame_list_que3[CONFIG_NET_PKT_TX_COUNT + 1];
+#endif
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 4
+static struct net_pkt *tx_frame_list_que4[CONFIG_NET_PKT_TX_COUNT + 1];
+#endif
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 5
+static struct net_pkt *tx_frame_list_que5[CONFIG_NET_PKT_TX_COUNT + 1];
+#endif
 #endif
 #endif
 
 #define MODULO_INC(val, max) {val = (++val < max) ? val : 0; }
 
+static int rx_descriptors_init(Gmac *gmac, struct gmac_queue *queue);
+static void tx_descriptors_init(Gmac *gmac, struct gmac_queue *queue);
+static int nonpriority_queue_init(Gmac *gmac, struct gmac_queue *queue);
+
+#if GMAC_PRIORITY_QUEUE_NUM >= 1
+static inline void set_receive_buf_queue_pointer(
+	Gmac *gmac,
+	struct gmac_queue *queue)
+{
+	/* Set Receive Buffer Queue Pointer Register */
+	if (queue->que_idx == GMAC_QUE_0) {
+		gmac->GMAC_RBQB = (u32_t)queue->rx_desc_list.buf;
+	} else {
+		gmac->GMAC_RBQBAPQ[queue->que_idx - 1] =
+			(u32_t)queue->rx_desc_list.buf;
+	}
+}
+
+static inline void disable_all_priority_queue_interrupt(Gmac *gmac)
+{
+	u32_t idx;
+
+	for (idx = 0; idx < GMAC_PRIORITY_QUEUE_NUM; idx++) {
+		gmac->GMAC_IDRPQ[idx] = UINT32_MAX;
+		(void)gmac->GMAC_ISRPQ[idx];
+	}
+}
+
+static int priority_queue_init(Gmac *gmac, struct gmac_queue *queue)
+{
+	int result;
+	int queue_index;
+
+	__ASSERT_NO_MSG(queue->rx_desc_list.len > 0);
+	__ASSERT_NO_MSG(queue->tx_desc_list.len > 0);
+	__ASSERT(!((u32_t)queue->rx_desc_list.buf & ~GMAC_RBQB_ADDR_Msk),
+		 "RX descriptors have to be word aligned");
+	__ASSERT(!((u32_t)queue->tx_desc_list.buf & ~GMAC_TBQB_ADDR_Msk),
+		 "TX descriptors have to be word aligned");
+
+	/* Extract queue index for easier referencing */
+	queue_index = queue->que_idx - 1;
+
+	/* Setup descriptor lists */
+	result = rx_descriptors_init(gmac, queue);
+	if (result < 0) {
+		return result;
+	}
+
+	tx_descriptors_init(gmac, queue);
+
+#if GMAC_MULTIPLE_TX_PACKETS == 0
+	k_sem_init(&queue->tx_sem, 0, 1);
+#else
+	k_sem_init(&queue->tx_desc_sem, queue->tx_desc_list.len - 1,
+		   queue->tx_desc_list.len - 1);
+#endif
+
+	/* Setup RX buffer size for DMA */
+	gmac->GMAC_RBSRPQ[queue_index] =
+		GMAC_RBSRPQ_RBS(CONFIG_NET_BUF_DATA_SIZE >> 6);
+
+	/* Set Receive Buffer Queue Pointer Register */
+	gmac->GMAC_RBQBAPQ[queue_index] = (u32_t)queue->rx_desc_list.buf;
+	/* Set Transmit Buffer Queue Pointer Register */
+	gmac->GMAC_TBQBAPQ[queue_index] = (u32_t)queue->tx_desc_list.buf;
+
+	/* Enable RX/TX completion and error interrupts */
+	gmac->GMAC_IERPQ[queue_index] = GMAC_INTPQ_EN_FLAGS;
+
+	queue->err_rx_frames_dropped = 0U;
+	queue->err_rx_flushed_count = 0U;
+	queue->err_tx_flushed_count = 0U;
+
+	LOG_INF("Queue %d activated", queue->que_idx);
+
+	return 0;
+}
+
+static int priority_queue_init_as_idle(Gmac *gmac, struct gmac_queue *queue)
+{
+	struct gmac_desc_list *rx_desc_list = &queue->rx_desc_list;
+	struct gmac_desc_list *tx_desc_list = &queue->tx_desc_list;
+
+	__ASSERT(!((u32_t)rx_desc_list->buf & ~GMAC_RBQB_ADDR_Msk),
+		 "RX descriptors have to be word aligned");
+	__ASSERT(!((u32_t)tx_desc_list->buf & ~GMAC_TBQB_ADDR_Msk),
+		 "TX descriptors have to be word aligned");
+	__ASSERT((rx_desc_list->len == 1U) && (tx_desc_list->len == 1U),
+		 "Priority queues are currently not supported, descriptor "
+		 "list has to have a single entry");
+
+	/* Setup RX descriptor lists */
+	/* Take ownership from GMAC and set the wrap bit */
+	rx_desc_list->buf[0].w0 = GMAC_RXW0_WRAP;
+	rx_desc_list->buf[0].w1 = 0U;
+	/* Setup TX descriptor lists */
+	tx_desc_list->buf[0].w0 = 0U;
+	/* Take ownership from GMAC and set the wrap bit */
+	tx_desc_list->buf[0].w1 = GMAC_TXW1_USED | GMAC_TXW1_WRAP;
+
+	/* Set Receive Buffer Queue Pointer Register */
+	gmac->GMAC_RBQBAPQ[queue->que_idx - 1] = (u32_t)rx_desc_list->buf;
+	/* Set Transmit Buffer Queue Pointer Register */
+	gmac->GMAC_TBQBAPQ[queue->que_idx - 1] = (u32_t)tx_desc_list->buf;
+
+	LOG_INF("Queue %d set to idle", queue->que_idx);
+
+	return 0;
+}
+
+static int queue_init(Gmac *gmac, struct gmac_queue *queue)
+{
+	if (queue->que_idx == GMAC_QUE_0) {
+		return nonpriority_queue_init(gmac, queue);
+	} else if (queue->que_idx <= GMAC_ACTIVE_PRIORITY_QUEUE_NUM) {
+		return priority_queue_init(gmac, queue);
+	} else {
+		return priority_queue_init_as_idle(gmac, queue);
+	}
+}
+
+#else
+
+static inline void set_receive_buf_queue_pointer(
+	Gmac *gmac,
+	struct gmac_queue *queue)
+{
+	gmac->GMAC_RBQB = (u32_t)queue->rx_desc_list.buf;
+}
+
+static int queue_init(Gmac *gmac, struct gmac_queue *queue)
+{
+	return nonpriority_queue_init(gmac, queue);
+}
+
+#define disable_all_queue_interrupt(gmac)
+
+#endif
+
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
+static int eth_sam_gmac_setup_qav(Gmac *gmac, int queue_id, bool enable);
+
+static inline void eth_sam_gmac_init_qav(Gmac *gmac)
+{
+	u32_t idx;
+
+	for (idx = GMAC_QUE_1; idx <= GMAC_ACTIVE_PRIORITY_QUEUE_NUM; idx++) {
+		eth_sam_gmac_setup_qav(gmac, idx, true);
+	}
+}
+
+#else
+
+#define eth_sam_gmac_init_qav(gmac)
+
+#endif
+
 /*
  * Cache helpers
  */
@@ -611,13 +831,7 @@ static void rx_error_handler(Gmac *gmac, struct gmac_queue *queue)
 		queue->rx_desc_list.buf[i].w0 &= ~GMAC_RXW0_OWNERSHIP;
 	}
 
-	/* Set Receive Buffer Queue Pointer Register */
-	if (queue->que_idx == 0) {
-		gmac->GMAC_RBQB = (u32_t)queue->rx_desc_list.buf;
-	} else {
-		gmac->GMAC_RBQBAPQ[queue->que_idx - 1] =
-			(u32_t)queue->rx_desc_list.buf;
-	}
+	set_receive_buf_queue_pointer(gmac, queue);
 
 	/* Restart reception */
 	gmac->GMAC_NCR |=  GMAC_NCR_RXEN;
@@ -652,11 +866,11 @@ static int get_mck_clock_divisor(u32_t mck)
 	return mck_divisor;
 }
 
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 static int eth_sam_gmac_setup_qav(Gmac *gmac, int queue_id, bool enable)
 {
 	/* Verify queue id */
-	if (queue_id < 1 || queue_id > GMAC_PRIORITY_QUEUE_NO) {
+	if (queue_id < GMAC_QUE_1 || queue_id > GMAC_ACTIVE_PRIORITY_QUEUE_NUM) {
 		return -EINVAL;
 	}
 
@@ -680,7 +894,7 @@ static int eth_sam_gmac_setup_qav(Gmac *gmac, int queue_id, bool enable)
 static int eth_sam_gmac_get_qav_status(Gmac *gmac, int queue_id, bool *enabled)
 {
 	/* Verify queue id */
-	if (queue_id < 1 || queue_id > GMAC_PRIORITY_QUEUE_NO) {
+	if (queue_id < GMAC_QUE_1 || queue_id > GMAC_ACTIVE_PRIORITY_QUEUE_NUM) {
 		return -EINVAL;
 	}
 
@@ -699,7 +913,7 @@ static int eth_sam_gmac_setup_qav_idle_slope(Gmac *gmac, int queue_id,
 	u32_t cbscr_val;
 
 	/* Verify queue id */
-	if (queue_id < 1 || queue_id > GMAC_PRIORITY_QUEUE_NO) {
+	if (queue_id < GMAC_QUE_1 || queue_id > GMAC_ACTIVE_PRIORITY_QUEUE_NUM) {
 		return -EINVAL;
 	}
 
@@ -742,7 +956,7 @@ static int eth_sam_gmac_get_qav_idle_slope(Gmac *gmac, int queue_id,
 					   unsigned int *idle_slope)
 {
 	/* Verify queue id */
-	if (queue_id < 1 || queue_id > GMAC_PRIORITY_QUEUE_NO) {
+	if (queue_id < GMAC_QUE_1 || queue_id > GMAC_ACTIVE_PRIORITY_QUEUE_NUM) {
 		return -EINVAL;
 	}
 
@@ -792,7 +1006,7 @@ static int eth_sam_gmac_setup_qav_delta_bandwidth(Gmac *gmac, int queue_id,
 	u32_t idle_slope;
 
 	/* Verify queue id */
-	if (queue_id < 1 || queue_id > GMAC_PRIORITY_QUEUE_NO) {
+	if (queue_id < GMAC_QUE_1 || queue_id > GMAC_ACTIVE_PRIORITY_QUEUE_NUM) {
 		return -EINVAL;
 	}
 
@@ -857,12 +1071,10 @@ static int gmac_init(Gmac *gmac, u32_t gmac_ncfgr_val)
 
 	/* Disable all interrupts */
 	gmac->GMAC_IDR = UINT32_MAX;
-	gmac->GMAC_IDRPQ[GMAC_QUE_1 - 1] = UINT32_MAX;
-	gmac->GMAC_IDRPQ[GMAC_QUE_2 - 1] = UINT32_MAX;
 	/* Clear all interrupts */
 	(void)gmac->GMAC_ISR;
-	(void)gmac->GMAC_ISRPQ[GMAC_QUE_1 - 1];
-	(void)gmac->GMAC_ISRPQ[GMAC_QUE_2 - 1];
+	disable_all_priority_queue_interrupt(gmac);
+
 	/* Setup Hash Registers - enable reception of all multicast frames when
 	 * GMAC_NCFGR_MTIHEN is set.
 	 */
@@ -888,10 +1100,9 @@ static int gmac_init(Gmac *gmac, u32_t gmac_ncfgr_val)
 	/* Enable Qav if priority queues are used, and setup the default delta
 	 * bandwidth according to IEEE802.1Qav (34.3.1)
 	 */
-#if GMAC_PRIORITY_QUEUE_NO == 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM == 1
 	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 1, 75);
-	eth_sam_gmac_setup_qav(gmac, 1, true);
-#elif GMAC_PRIORITY_QUEUE_NO == 2
+#elif GMAC_ACTIVE_PRIORITY_QUEUE_NUM == 2
 	/* For multiple priority queues, 802.1Qav suggests using 75% for the
 	 * highest priority queue, and 0% for the lower priority queues.
 	 * This is because the lower priority queues are supposed to be using
@@ -904,10 +1115,25 @@ static int gmac_init(Gmac *gmac, u32_t gmac_ncfgr_val)
 	 */
 	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 1, 25);
 	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 2, 50);
-	eth_sam_gmac_setup_qav(gmac, 1, true);
-	eth_sam_gmac_setup_qav(gmac, 2, true);
+#elif GMAC_ACTIVE_PRIORITY_QUEUE_NUM == 3
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 1, 25);
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 2, 25);
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 3, 25);
+#elif GMAC_ACTIVE_PRIORITY_QUEUE_NUM == 4
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 1, 21);
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 2, 18);
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 3, 18);
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 4, 18);
+#elif GMAC_ACTIVE_PRIORITY_QUEUE_NUM == 5
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 1, 15);
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 2, 15);
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 3, 15);
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 4, 15);
+	eth_sam_gmac_setup_qav_delta_bandwidth(gmac, 5, 15);
 #endif
 
+	eth_sam_gmac_init_qav(gmac);
+
 	return 0;
 }
 
@@ -991,100 +1217,6 @@ static int nonpriority_queue_init(Gmac *gmac, struct gmac_queue *queue)
 	return 0;
 }
 
-static int priority_queue_init(Gmac *gmac, struct gmac_queue *queue)
-{
-	int result;
-	int queue_index;
-
-	__ASSERT_NO_MSG(queue->rx_desc_list.len > 0);
-	__ASSERT_NO_MSG(queue->tx_desc_list.len > 0);
-	__ASSERT(!((u32_t)queue->rx_desc_list.buf & ~GMAC_RBQB_ADDR_Msk),
-		 "RX descriptors have to be word aligned");
-	__ASSERT(!((u32_t)queue->tx_desc_list.buf & ~GMAC_TBQB_ADDR_Msk),
-		 "TX descriptors have to be word aligned");
-
-	/* Extract queue index for easier referencing */
-	queue_index = queue->que_idx - 1;
-
-	/* Setup descriptor lists */
-	result = rx_descriptors_init(gmac, queue);
-	if (result < 0) {
-		return result;
-	}
-
-	tx_descriptors_init(gmac, queue);
-
-#if GMAC_MULTIPLE_TX_PACKETS == 0
-	k_sem_init(&queue->tx_sem, 0, 1);
-#else
-	k_sem_init(&queue->tx_desc_sem, queue->tx_desc_list.len - 1,
-		   queue->tx_desc_list.len - 1);
-#endif
-
-	/* Setup RX buffer size for DMA */
-	gmac->GMAC_RBSRPQ[queue_index] =
-		GMAC_RBSRPQ_RBS(CONFIG_NET_BUF_DATA_SIZE >> 6);
-
-	/* Set Receive Buffer Queue Pointer Register */
-	gmac->GMAC_RBQBAPQ[queue_index] = (u32_t)queue->rx_desc_list.buf;
-	/* Set Transmit Buffer Queue Pointer Register */
-	gmac->GMAC_TBQBAPQ[queue_index] = (u32_t)queue->tx_desc_list.buf;
-
-	/* Enable RX/TX completion and error interrupts */
-	gmac->GMAC_IERPQ[queue_index] = GMAC_INTPQ_EN_FLAGS;
-
-	queue->err_rx_frames_dropped = 0U;
-	queue->err_rx_flushed_count = 0U;
-	queue->err_tx_flushed_count = 0U;
-
-	LOG_INF("Queue %d activated", queue->que_idx);
-
-	return 0;
-}
-
-static int priority_queue_init_as_idle(Gmac *gmac, struct gmac_queue *queue)
-{
-	struct gmac_desc_list *rx_desc_list = &queue->rx_desc_list;
-	struct gmac_desc_list *tx_desc_list = &queue->tx_desc_list;
-
-	__ASSERT(!((u32_t)rx_desc_list->buf & ~GMAC_RBQB_ADDR_Msk),
-		 "RX descriptors have to be word aligned");
-	__ASSERT(!((u32_t)tx_desc_list->buf & ~GMAC_TBQB_ADDR_Msk),
-		 "TX descriptors have to be word aligned");
-	__ASSERT((rx_desc_list->len == 1U) && (tx_desc_list->len == 1U),
-		 "Priority queues are currently not supported, descriptor "
-		 "list has to have a single entry");
-
-	/* Setup RX descriptor lists */
-	/* Take ownership from GMAC and set the wrap bit */
-	rx_desc_list->buf[0].w0 = GMAC_RXW0_WRAP;
-	rx_desc_list->buf[0].w1 = 0U;
-	/* Setup TX descriptor lists */
-	tx_desc_list->buf[0].w0 = 0U;
-	/* Take ownership from GMAC and set the wrap bit */
-	tx_desc_list->buf[0].w1 = GMAC_TXW1_USED | GMAC_TXW1_WRAP;
-
-	/* Set Receive Buffer Queue Pointer Register */
-	gmac->GMAC_RBQBAPQ[queue->que_idx - 1] = (u32_t)rx_desc_list->buf;
-	/* Set Transmit Buffer Queue Pointer Register */
-	gmac->GMAC_TBQBAPQ[queue->que_idx - 1] = (u32_t)tx_desc_list->buf;
-
-	LOG_INF("Queue %d set to idle", queue->que_idx);
-
-	return 0;
-}
-
-static int queue_init(Gmac *gmac, struct gmac_queue *queue)
-{
-	if (queue->que_idx == 0) {
-		return nonpriority_queue_init(gmac, queue);
-	} else if (queue->que_idx <= GMAC_PRIORITY_QUEUE_NO) {
-		return priority_queue_init(gmac, queue);
-	} else {
-		return priority_queue_init_as_idle(gmac, queue);
-	}
-}
-
 static struct net_pkt *frame_get(struct gmac_queue *queue)
 {
 	struct gmac_desc_list *rx_desc_list = &queue->rx_desc_list;
@@ -1270,19 +1402,28 @@ static void eth_rx(struct gmac_queue *queue)
 }
 
 #if !defined(CONFIG_ETH_SAM_GMAC_FORCE_QUEUE) && \
-	((CONFIG_ETH_SAM_GMAC_QUEUES != NET_TC_TX_COUNT) || \
+	((GMAC_ACTIVE_QUEUE_NUM != NET_TC_TX_COUNT) || \
 	((NET_TC_TX_COUNT != NET_TC_RX_COUNT) && defined(CONFIG_NET_VLAN)))
 static int priority2queue(enum net_priority priority)
 {
 	static const u8_t queue_priority_map[] = {
-#if CONFIG_ETH_SAM_GMAC_QUEUES == 1
+#if GMAC_ACTIVE_QUEUE_NUM == 1
 		0, 0, 0, 0, 0, 0, 0, 0
 #endif
-#if CONFIG_ETH_SAM_GMAC_QUEUES == 2
+#if GMAC_ACTIVE_QUEUE_NUM == 2
 		0, 0, 0, 0, 1, 1, 1, 1
 #endif
-#if CONFIG_ETH_SAM_GMAC_QUEUES == 3
+#if GMAC_ACTIVE_QUEUE_NUM == 3
 		0, 0, 0, 0, 1, 1, 2, 2
+#endif
+#if GMAC_ACTIVE_QUEUE_NUM == 4
+		0, 0, 0, 0, 1, 1, 2, 3
+#endif
+#if GMAC_ACTIVE_QUEUE_NUM == 5
+		0, 0, 0, 0, 1, 2, 3, 4
+#endif
+#if GMAC_ACTIVE_QUEUE_NUM == 6
+		0, 0, 0, 1, 2, 3, 4, 5
 #endif
 	};
 
@@ -1328,7 +1469,7 @@ static int eth_tx(struct device *dev, struct net_pkt *pkt)
 #if defined(CONFIG_ETH_SAM_GMAC_FORCE_QUEUE)
 	/* Route eveything to the forced queue */
 	queue = &dev_data->queue_list[CONFIG_ETH_SAM_GMAC_FORCED_QUEUE];
-#elif CONFIG_ETH_SAM_GMAC_QUEUES == CONFIG_NET_TC_TX_COUNT
+#elif GMAC_ACTIVE_QUEUE_NUM == CONFIG_NET_TC_TX_COUNT
 	/* Prefer to chose queue based on its traffic class */
 	queue = &dev_data->queue_list[net_tx_priority2tc(pkt_prio)];
 #else
@@ -1521,7 +1662,7 @@ static void queue0_isr(void *arg)
 	}
 }
 
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 static inline void priority_queue_isr(void *arg, unsigned int queue_idx)
 {
 	struct device *const dev = (struct device *const)arg;
@@ -1572,20 +1713,41 @@ static inline void priority_queue_isr(void *arg, unsigned int queue_idx)
 }
 #endif
 
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 static void queue1_isr(void *arg)
 {
 	priority_queue_isr(arg, 1);
 }
 #endif
 
-#if GMAC_PRIORITY_QUEUE_NO == 2
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 2
 static void queue2_isr(void *arg)
 {
 	priority_queue_isr(arg, 2);
 }
 #endif
 
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 3
+static void queue3_isr(void *arg)
+{
+	priority_queue_isr(arg, 3);
+}
+#endif
+
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 4
+static void queue4_isr(void *arg)
+{
+	priority_queue_isr(arg, 4);
+}
+#endif
+
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 5
+static void queue5_isr(void *arg)
+{
+	priority_queue_isr(arg, 5);
+}
+#endif
+
 static int eth_initialize(struct device *dev)
 {
 	const struct eth_sam_dev_cfg *const cfg = DEV_CFG(dev);
@@ -1702,7 +1864,7 @@ static void eth0_iface_init(struct net_if *iface)
 			     NET_LINK_ETHERNET);
 
 	/* Initialize GMAC queues */
-	for (i = 0; i < GMAC_QUEUE_NO; i++) {
+	for (i = GMAC_QUE_0; i < GMAC_QUEUE_NUM; i++) {
 		result = queue_init(cfg->regs, &dev_data->queue_list[i]);
 		if (result < 0) {
 			LOG_ERR("Unable to initialize ETH queue%d", i);
@@ -1710,14 +1872,14 @@ static void eth0_iface_init(struct net_if *iface)
 		}
 	}
 
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 #if defined(CONFIG_ETH_SAM_GMAC_FORCE_QUEUE)
 	for (i = 0; i < CONFIG_NET_TC_RX_COUNT; ++i) {
 		cfg->regs->GMAC_ST1RPQ[i] =
 			GMAC_ST1RPQ_DSTCM(i) |
 			GMAC_ST1RPQ_QNB(CONFIG_ETH_SAM_GMAC_FORCED_QUEUE);
 	}
-#elif CONFIG_ETH_SAM_GMAC_QUEUES == NET_TC_RX_COUNT
+#elif GMAC_ACTIVE_QUEUE_NUM == NET_TC_RX_COUNT
 	/* If TC configuration is compatible with HW configuration, setup the
 	 * screening registers based on the DS/TC values.
 	 * Map them 1:1 - TC 0 -> Queue 0, TC 1 -> Queue 1 etc.
@@ -1779,13 +1941,13 @@ static enum ethernet_hw_caps eth_sam_gmac_get_capabilities(struct device *dev)
 		ETHERNET_PTP |
 #endif
 		ETHERNET_PRIORITY_QUEUES |
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 		ETHERNET_QAV |
 #endif
 		ETHERNET_LINK_100BASE_T;
 }
 
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 static int eth_sam_gmac_set_qav_param(struct device *dev,
 				      enum ethernet_config_type type,
 				      const struct ethernet_config *config)
@@ -1833,7 +1995,7 @@ static int eth_sam_gmac_set_config(struct device *dev,
 				   const struct ethernet_config *config)
 {
 	switch (type) {
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 	case ETHERNET_CONFIG_TYPE_QAV_PARAM:
 		return eth_sam_gmac_set_qav_param(dev, type, config);
 #endif
@@ -1844,7 +2006,7 @@ static int eth_sam_gmac_set_config(struct device *dev,
 	return -ENOTSUP;
 }
 
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 static int eth_sam_gmac_get_qav_param(struct device *dev,
 				      enum ethernet_config_type type,
 				      struct ethernet_config *config)
@@ -1879,7 +2041,7 @@ static int eth_sam_gmac_get_qav_param(struct device *dev,
 		return eth_sam_gmac_get_qav_delta_bandwidth(gmac, queue_id,
 							    delta_bandwidth);
 	case ETHERNET_QAV_PARAM_TYPE_TRAFFIC_CLASS:
-#if CONFIG_ETH_SAM_GMAC_QUEUES == NET_TC_TX_COUNT
+#if GMAC_ACTIVE_QUEUE_NUM == NET_TC_TX_COUNT
 		config->qav_param.traffic_class = queue_id;
 		return 0;
 #else
@@ -1900,9 +2062,9 @@ static int eth_sam_gmac_get_config(struct device *dev,
 {
 	switch (type) {
 	case ETHERNET_CONFIG_TYPE_PRIORITY_QUEUES_NUM:
-		config->priority_queues_num = GMAC_PRIORITY_QUEUE_NO;
+		config->priority_queues_num = GMAC_ACTIVE_PRIORITY_QUEUE_NUM;
 		return 0;
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 	case ETHERNET_CONFIG_TYPE_QAV_PARAM:
 		return eth_sam_gmac_get_qav_param(dev, type, config);
 #endif
@@ -1943,17 +2105,35 @@ static void eth0_irq_config(void)
 		    DEVICE_GET(eth0_sam_gmac), 0);
 	irq_enable(GMAC_IRQn);
 
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 	IRQ_CONNECT(GMAC_Q1_IRQn, CONFIG_ETH_SAM_GMAC_IRQ_PRI, queue1_isr,
 		    DEVICE_GET(eth0_sam_gmac), 0);
 	irq_enable(GMAC_Q1_IRQn);
 #endif
 
-#if GMAC_PRIORITY_QUEUE_NO == 2
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 2
 	IRQ_CONNECT(GMAC_Q2_IRQn, CONFIG_ETH_SAM_GMAC_IRQ_PRI, queue2_isr,
 		    DEVICE_GET(eth0_sam_gmac), 0);
 	irq_enable(GMAC_Q2_IRQn);
 #endif
+
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 3
+	IRQ_CONNECT(GMAC_Q3_IRQn, CONFIG_ETH_SAM_GMAC_IRQ_PRI, queue3_isr,
+		    DEVICE_GET(eth0_sam_gmac), 0);
+	irq_enable(GMAC_Q3_IRQn);
+#endif
+
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 4
+	IRQ_CONNECT(GMAC_Q4_IRQn, CONFIG_ETH_SAM_GMAC_IRQ_PRI, queue4_isr,
+		    DEVICE_GET(eth0_sam_gmac), 0);
+	irq_enable(GMAC_Q4_IRQn);
+#endif
+
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 5
+	IRQ_CONNECT(GMAC_Q5_IRQn, CONFIG_ETH_SAM_GMAC_IRQ_PRI, queue5_isr,
+		    DEVICE_GET(eth0_sam_gmac), 0);
+	irq_enable(GMAC_Q5_IRQn);
+#endif
 }
 
 static const struct soc_gpio_pin pins_eth0[] = PINS_GMAC0;
@@ -1978,7 +2158,8 @@ static struct eth_sam_dev_data eth0_data = {
 		CONFIG_ETH_SAM_GMAC_MAC5,
 	},
 #endif
-	.queue_list = {{
+	.queue_list = {
+		{
 			.que_idx = GMAC_QUE_0,
 			.rx_desc_list = {
 				.buf = rx_desc_que0,
@@ -2001,6 +2182,7 @@ static struct eth_sam_dev_data eth0_data = {
 			},
 #endif
 #endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 1
 		}, {
 			.que_idx = GMAC_QUE_1,
 			.rx_desc_list = {
@@ -2011,7 +2193,7 @@ static struct eth_sam_dev_data eth0_data = {
 				.buf = tx_desc_que1,
 				.len = ARRAY_SIZE(tx_desc_que1),
 			},
-#if GMAC_PRIORITY_QUEUE_NO >= 1
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
 			.rx_frag_list = rx_frag_list_que1,
 #if GMAC_MULTIPLE_TX_PACKETS == 1
 			.tx_frag_list = {
@@ -2026,6 +2208,8 @@ static struct eth_sam_dev_data eth0_data = {
 #endif
 #endif
 #endif
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 2
 		}, {
 			.que_idx = GMAC_QUE_2,
 			.rx_desc_list = {
@@ -2036,7 +2220,7 @@ static struct eth_sam_dev_data eth0_data = {
 				.buf = tx_desc_que2,
 				.len = ARRAY_SIZE(tx_desc_que2),
 			},
-#if GMAC_PRIORITY_QUEUE_NO == 2
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 2
 			.rx_frag_list = rx_frag_list_que2,
 #if GMAC_MULTIPLE_TX_PACKETS == 1
 			.tx_frag_list = {
@@ -2050,6 +2234,88 @@ static struct eth_sam_dev_data eth0_data = {
 			}
 #endif
 #endif
+#endif
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 3
+		}, {
+			.que_idx = GMAC_QUE_3,
+			.rx_desc_list = {
+				.buf = rx_desc_que3,
+				.len = ARRAY_SIZE(rx_desc_que3),
+			},
+			.tx_desc_list = {
+				.buf = tx_desc_que3,
+				.len = ARRAY_SIZE(tx_desc_que3),
+			},
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 3
+			.rx_frag_list = rx_frag_list_que3,
+#if GMAC_MULTIPLE_TX_PACKETS == 1
+			.tx_frag_list = {
+				.buf = (u32_t *)tx_frag_list_que3,
+				.len = ARRAY_SIZE(tx_frag_list_que3),
+			},
+#if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
+			.tx_frames = {
+				.buf = (u32_t *)tx_frame_list_que3,
+				.len = ARRAY_SIZE(tx_frame_list_que3),
+			}
+#endif
+#endif
+#endif
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 4
+		}, {
+			.que_idx = GMAC_QUE_4,
+			.rx_desc_list = {
+				.buf = rx_desc_que4,
+				.len = ARRAY_SIZE(rx_desc_que4),
+			},
+			.tx_desc_list = {
+				.buf = tx_desc_que4,
+				.len = ARRAY_SIZE(tx_desc_que4),
+			},
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 4
+			.rx_frag_list = rx_frag_list_que4,
+#if GMAC_MULTIPLE_TX_PACKETS == 1
+			.tx_frag_list = {
+				.buf = (u32_t *)tx_frag_list_que4,
+				.len = ARRAY_SIZE(tx_frag_list_que4),
+			},
+#if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
+			.tx_frames = {
+				.buf = (u32_t *)tx_frame_list_que4,
+				.len = ARRAY_SIZE(tx_frame_list_que4),
+			}
+#endif
+#endif
+#endif
+#endif
+#if GMAC_PRIORITY_QUEUE_NUM >= 5
+		}, {
+			.que_idx = GMAC_QUE_5,
+			.rx_desc_list = {
+				.buf = rx_desc_que5,
+				.len = ARRAY_SIZE(rx_desc_que5),
+			},
+			.tx_desc_list = {
+				.buf = tx_desc_que5,
+				.len = ARRAY_SIZE(tx_desc_que5),
+			},
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 5
+			.rx_frag_list = rx_frag_list_que5,
+#if GMAC_MULTIPLE_TX_PACKETS == 1
+			.tx_frag_list = {
+				.buf = (u32_t *)tx_frag_list_que5,
+				.len = ARRAY_SIZE(tx_frag_list_que5),
+			},
+#if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
+			.tx_frames = {
+				.buf = (u32_t *)tx_frame_list_que5,
+				.len = ARRAY_SIZE(tx_frame_list_que5),
+			}
+#endif
+#endif
+#endif
 #endif
 		}
 	},

drivers/ethernet/eth_sam_gmac_priv.h

@@ -27,34 +27,71 @@
 #define GMAC_FRAME_SIZE_MAX (GMAC_MTU + 18)
 
 /** Cache alignment */
-#define GMAC_DCACHE_ALIGNMENT             32
+#define GMAC_DCACHE_ALIGNMENT           32
 /** Memory alignment of the RX/TX Buffer Descriptor List */
-#define GMAC_DESC_ALIGNMENT               4
+#define GMAC_DESC_ALIGNMENT             4
 /** Total number of queues supported by GMAC hardware module */
-#define GMAC_QUEUE_NO                     3
+#if defined(CONFIG_SOC_ATMEL_SAME70_REVB) || \
+	defined(CONFIG_SOC_ATMEL_SAMV71_REVB)
+#define GMAC_QUEUE_NUM                  6
+#elif !defined(CONFIG_SOC_SERIES_SAM4E)
+#define GMAC_QUEUE_NUM                  3
+#else
+#define GMAC_QUEUE_NUM                  1
+#endif
+#define GMAC_PRIORITY_QUEUE_NUM         (GMAC_QUEUE_NUM - 1)
+#if (GMAC_PRIORITY_QUEUE_NUM >= 1)
+BUILD_ASSERT_MSG(ARRAY_SIZE(GMAC->GMAC_TBQBAPQ) + 1 == GMAC_QUEUE_NUM,
+		 "GMAC_QUEUE_NUM doesn't match soc header");
+#endif
 /** Number of priority queues used */
-#define GMAC_PRIORITY_QUEUE_NO            (CONFIG_ETH_SAM_GMAC_QUEUES - 1)
+#define GMAC_ACTIVE_QUEUE_NUM           (CONFIG_ETH_SAM_GMAC_QUEUES)
+#define GMAC_ACTIVE_PRIORITY_QUEUE_NUM  (GMAC_ACTIVE_QUEUE_NUM - 1)
 
 /** RX descriptors count for main queue */
-#define MAIN_QUEUE_RX_DESC_COUNT CONFIG_ETH_SAM_GMAC_BUF_RX_COUNT
+#define MAIN_QUEUE_RX_DESC_COUNT        CONFIG_ETH_SAM_GMAC_BUF_RX_COUNT
 /** TX descriptors count for main queue */
-#define MAIN_QUEUE_TX_DESC_COUNT (CONFIG_NET_BUF_TX_COUNT + 1)
+#define MAIN_QUEUE_TX_DESC_COUNT        (CONFIG_NET_BUF_TX_COUNT + 1)
 
 /** RX/TX descriptors count for priority queues */
-#if GMAC_PRIORITY_QUEUE_NO == 2
-#define PRIORITY_QUEUE2_RX_DESC_COUNT         MAIN_QUEUE_RX_DESC_COUNT
-#define PRIORITY_QUEUE2_TX_DESC_COUNT         MAIN_QUEUE_TX_DESC_COUNT
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1
+#define PRIORITY_QUEUE1_RX_DESC_COUNT   MAIN_QUEUE_RX_DESC_COUNT
+#define PRIORITY_QUEUE1_TX_DESC_COUNT   MAIN_QUEUE_TX_DESC_COUNT
 #else
-#define PRIORITY_QUEUE2_RX_DESC_COUNT         1
-#define PRIORITY_QUEUE2_TX_DESC_COUNT         1
+#define PRIORITY_QUEUE1_RX_DESC_COUNT   1
+#define PRIORITY_QUEUE1_TX_DESC_COUNT   1
 #endif
 
-#if GMAC_PRIORITY_QUEUE_NO >= 1
-#define PRIORITY_QUEUE1_RX_DESC_COUNT         MAIN_QUEUE_RX_DESC_COUNT
-#define PRIORITY_QUEUE1_TX_DESC_COUNT         MAIN_QUEUE_TX_DESC_COUNT
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 2
+#define PRIORITY_QUEUE2_RX_DESC_COUNT   MAIN_QUEUE_RX_DESC_COUNT
+#define PRIORITY_QUEUE2_TX_DESC_COUNT   MAIN_QUEUE_TX_DESC_COUNT
 #else
-#define PRIORITY_QUEUE1_RX_DESC_COUNT         1
-#define PRIORITY_QUEUE1_TX_DESC_COUNT         1
+#define PRIORITY_QUEUE2_RX_DESC_COUNT   1
+#define PRIORITY_QUEUE2_TX_DESC_COUNT   1
+#endif
+
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 3
+#define PRIORITY_QUEUE3_RX_DESC_COUNT   MAIN_QUEUE_RX_DESC_COUNT
+#define PRIORITY_QUEUE3_TX_DESC_COUNT   MAIN_QUEUE_TX_DESC_COUNT
+#else
+#define PRIORITY_QUEUE3_RX_DESC_COUNT   1
+#define PRIORITY_QUEUE3_TX_DESC_COUNT   1
+#endif
+
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 4
+#define PRIORITY_QUEUE4_RX_DESC_COUNT   MAIN_QUEUE_RX_DESC_COUNT
+#define PRIORITY_QUEUE4_TX_DESC_COUNT   MAIN_QUEUE_TX_DESC_COUNT
+#else
+#define PRIORITY_QUEUE4_RX_DESC_COUNT   1
+#define PRIORITY_QUEUE4_TX_DESC_COUNT   1
+#endif
+
+#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 5
+#define PRIORITY_QUEUE5_RX_DESC_COUNT   MAIN_QUEUE_RX_DESC_COUNT
+#define PRIORITY_QUEUE5_TX_DESC_COUNT   MAIN_QUEUE_TX_DESC_COUNT
+#else
+#define PRIORITY_QUEUE5_RX_DESC_COUNT   1
+#define PRIORITY_QUEUE5_TX_DESC_COUNT   1
 #endif
 
 /*
@@ -147,6 +184,9 @@ enum queue_idx {
 	GMAC_QUE_0,  /** Main queue */
 	GMAC_QUE_1,  /** Priority queue 1 */
 	GMAC_QUE_2,  /** Priority queue 2 */
+	GMAC_QUE_3,  /** Priority queue 3 */
+	GMAC_QUE_4,  /** Priority queue 4 */
+	GMAC_QUE_5,  /** Priority queue 5 */
 };
 
 /** Minimal ring buffer implementation */
@@ -217,7 +257,7 @@ struct eth_sam_dev_data {
 	struct device *ptp_clock;
 #endif
 	u8_t mac_addr[6];
-	struct gmac_queue queue_list[GMAC_QUEUE_NO];
+	struct gmac_queue queue_list[GMAC_QUEUE_NUM];
 };
 
 #define DEV_CFG(dev) \

drivers/gpio/gpio_handlers.c

@@ -71,6 +71,8 @@ static inline int z_vrfy_gpio_pin_interrupt_configure(struct device *port,
 static inline int z_vrfy_gpio_enable_callback(struct device *port,
 					     gpio_pin_t pin)
 {
+	Z_OOPS(Z_SYSCALL_DRIVER_GPIO(port, enable_callback));
+
 	return z_impl_gpio_enable_callback((struct device *)port, pin);
 }
 #include <syscalls/gpio_enable_callback_mrsh.c>
@@ -78,12 +80,16 @@ static inline int z_vrfy_gpio_enable_callback(struct device *port,
 static inline int z_vrfy_gpio_disable_callback(struct device *port,
 					      gpio_pin_t pin)
 {
+	Z_OOPS(Z_SYSCALL_DRIVER_GPIO(port, disable_callback));
+
 	return z_impl_gpio_disable_callback((struct device *)port, pin);
 }
 #include <syscalls/gpio_disable_callback_mrsh.c>
 
 static inline int z_vrfy_gpio_get_pending_int(struct device *dev)
 {
+	Z_OOPS(Z_SYSCALL_DRIVER_GPIO(dev, get_pending_int));
+
 	return z_impl_gpio_get_pending_int((struct device *)dev);
 }
 #include <syscalls/gpio_get_pending_int_mrsh.c>

drivers/hwinfo/Kconfig

@@ -10,6 +10,9 @@ menuconfig HWINFO
 
 if HWINFO
 
+config HWINFO_HAS_DRIVER
+	bool
+
 config HWINFO_SHELL
 	bool "Enable HWINFO Shell"
 	depends on SHELL
@@ -20,14 +23,15 @@ config HWINFO_STM32
 	bool "STM32 hwinfo"
 	default y
 	depends on SOC_FAMILY_STM32
-	select USE_STM32_LL_UTILS
+	select HWINFO_HAS_DRIVER
 	help
 	  Enable STM32 hwinfo driver.
 
 config HWINFO_NRF
 	bool "NRF device ID"
 	default y
-	depends on SOC_FAMILY_NRF
+	depends on SOC_FAMILY_NRF && !TRUSTED_EXECUTION_NONSECURE
+	select HWINFO_HAS_DRIVER
 	help
 	  Enable Nordic NRF hwinfo driver.
 
@@ -35,6 +39,7 @@ config HWINFO_MCUX_SIM
 	bool "NXP kinetis device ID"
 	default y
 	depends on HAS_MCUX_SIM
+	select HWINFO_HAS_DRIVER
 	help
 	  Enable NXP kinetis mcux hwinfo driver.
 
@@ -42,6 +47,7 @@ config HWINFO_IMXRT
 	bool "NXP i.mx RT device ID"
 	default y
 	depends on SOC_SERIES_IMX_RT
+	select HWINFO_HAS_DRIVER
 	help
 	  Enable NXP i.mx RT hwinfo driver.
 
@@ -49,6 +55,7 @@ config HWINFO_SAM
 	bool "Atmel SAM device ID"
 	default y
 	depends on SOC_FAMILY_SAM
+	select HWINFO_HAS_DRIVER
 	help
 	  Enable Atmel SAM hwinfo driver.
 
@@ -56,6 +63,7 @@ config HWINFO_SAM0
 	bool "Atmel SAM0 device ID"
 	default y
 	depends on SOC_FAMILY_SAM0
+	select HWINFO_HAS_DRIVER
 	help
 	  Enable Atmel SAM0 hwinfo driver.
 
@@ -63,6 +71,7 @@ config HWINFO_ESP32
 	bool "ESP32 device ID"
 	default y
 	depends on SOC_ESP32
+	select HWINFO_HAS_DRIVER
 	help
 	  Enable ESP32 hwinfo driver.
 
@@ -70,6 +79,7 @@ config HWINFO_LITEX
 	bool "LiteX device ID"
 	default y
 	depends on SOC_RISCV32_LITEX_VEXRISCV
+	select HWINFO_HAS_DRIVER
 	help
 	  Enable LiteX hwinfo driver
 endif

drivers/hwinfo/hwinfo_sam.c

@@ -73,7 +73,13 @@ static int hwinfo_sam_init(struct device *arg)
 
 	/* Disable code loop optimization and sequential code optimization. */
 	fmr = efc->EEFC_FMR;
+
+#ifndef CONFIG_SOC_SERIES_SAM3X
 	efc->EEFC_FMR = (fmr & (~EEFC_FMR_CLOE)) | EEFC_FMR_SCOD;
+#else
+	/* SAM3x does not have loop optimization (EEFC_FMR_CLOE) */
+	efc->EEFC_FMR |= EEFC_FMR_SCOD;
+#endif
 
 	/* Read the device ID using code in RAM */
 	hwinfo_sam_read_device_id();

drivers/ieee802154/ieee802154_rf2xx.c

@@ -1,7 +1,7 @@
 /* ieee802154_rf2xx.c - ATMEL RF2XX IEEE 802.15.4 Driver */
 
 /*
- * Copyright (c) 2019 Gerson Fernando Budke
+ * Copyright (c) 2019-2020 Gerson Fernando Budke
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -77,16 +77,6 @@ static inline void trx_isr_handler(struct device *port,
 	k_sem_give(&ctx->trx_isr_lock);
 }
 
-static void trx_isr_timeout(struct k_timer *timer_id)
-{
-	struct rf2xx_context *ctx = (struct rf2xx_context *)
-				    k_timer_user_data_get(timer_id);
-
-	k_mutex_lock(&ctx->phy_mutex, K_FOREVER);
-	ctx->trx_state = RF2XX_TRX_PHY_STATE_IDLE;
-	k_mutex_unlock(&ctx->phy_mutex);
-}
-
 static void rf2xx_trx_set_state(struct device *dev,
 				enum rf2xx_trx_state_cmd_t state)
 {
@@ -104,6 +94,30 @@ static void rf2xx_trx_set_state(struct device *dev,
 		  RF2XX_TRX_PHY_STATUS_MASK));
 }
 
+static void rf2xx_trx_set_tx_state(struct device *dev)
+{
+	u8_t status;
+
+	/**
+	 * Ensures that RX automatically ACK will be sent when requested.
+	 * Datasheet: Chapter 7.2.3 RX_AACK_ON – Receive with Automatic ACK
+	 * Datasheet: Figure 7-13. Timing Example of an RX_AACK Transaction
+	 * for Slotted Operation.
+	 *
+	 * This will create a spin lock that wait transceiver be free from
+	 * current receive frame process
+	 */
+	do {
+		status = (rf2xx_iface_reg_read(dev, RF2XX_TRX_STATUS_REG) &
+			  RF2XX_TRX_PHY_STATUS_MASK);
+	} while (status == RF2XX_TRX_PHY_STATUS_BUSY_RX_AACK ||
+		 status == RF2XX_TRX_PHY_STATUS_STATE_TRANSITION);
+
+	rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_TRX_OFF);
+	rf2xx_iface_reg_read(dev, RF2XX_IRQ_STATUS_REG);
+	rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_TX_ARET_ON);
+}
+
 static void rf2xx_trx_set_rx_state(struct device *dev)
 {
 	rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_TRX_OFF);
@@ -131,8 +145,12 @@ static void rf2xx_trx_rx(struct device *dev)
 	 * This obligate the driver to have rx_buf statically allocated with
 	 * RX2XX_MAX_FRAME_SIZE.
 	 */
-	rf2xx_iface_frame_read(dev, rx_buf, RX2XX_FRAME_HEADER_SIZE);
-	pkt_len = rx_buf[RX2XX_FRAME_PHR_INDEX];
+	if (ctx->trx_model != RF2XX_TRX_MODEL_231) {
+		pkt_len = ctx->rx_phr;
+	} else {
+		rf2xx_iface_frame_read(dev, rx_buf, RX2XX_FRAME_HEADER_SIZE);
+		pkt_len = rx_buf[RX2XX_FRAME_PHR_INDEX];
+	}
 
 	if (pkt_len < RX2XX_FRAME_MIN_PHR_SIZE) {
 		LOG_ERR("invalid RX frame length");
@@ -190,6 +208,53 @@ static void rf2xx_trx_rx(struct device *dev)
 				K_THREAD_STACK_SIZEOF(ctx->trx_stack));
 	}
 }
+
+static void rf2xx_process_rx_frame(struct device *dev)
+{
+	struct rf2xx_context *ctx = dev->driver_data;
+
+	if (ctx->trx_model != RF2XX_TRX_MODEL_231) {
+		rf2xx_trx_rx(dev);
+	} else {
+		/* Ensures that automatically ACK will be sent
+		 * when requested
+		 */
+		while (rf2xx_iface_reg_read(dev, RF2XX_TRX_STATUS_REG) ==
+		       RF2XX_TRX_PHY_STATUS_BUSY_RX_AACK) {
+			;
+		};
+
+		/* Set PLL_ON to avoid transceiver receive
+		 * new data until finish reading process
+		 */
+		rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_PLL_ON);
+		rf2xx_trx_rx(dev);
+		rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_RX_AACK_ON);
+	}
+}
+
+static void rf2xx_process_tx_frame(struct device *dev)
+{
+	struct rf2xx_context *ctx = dev->driver_data;
+
+	ctx->trx_trac = (rf2xx_iface_reg_read(dev, RF2XX_TRX_STATE_REG) >>
+			 RF2XX_TRAC_STATUS) & 7;
+	k_sem_give(&ctx->trx_tx_sync);
+	rf2xx_trx_set_rx_state(dev);
+}
+
+static void rf2xx_process_trx_end(struct device *dev)
+{
+	u8_t trx_status = (rf2xx_iface_reg_read(dev, RF2XX_TRX_STATUS_REG) &
+			   RF2XX_TRX_PHY_STATUS_MASK);
+
+	if (trx_status == RF2XX_TRX_PHY_STATUS_TX_ARET_ON) {
+		rf2xx_process_tx_frame(dev);
+	} else {
+		rf2xx_process_rx_frame(dev);
+	}
+}
+
 static void rf2xx_thread_main(void *arg)
 {
 	struct device *dev = INT_TO_POINTER(arg);
@@ -198,9 +263,9 @@ static void rf2xx_thread_main(void *arg)
 
 	while (true) {
 		k_sem_take(&ctx->trx_isr_lock, K_FOREVER);
-		k_mutex_lock(&ctx->phy_mutex, K_FOREVER);
 
 		isr_status = rf2xx_iface_reg_read(dev, RF2XX_IRQ_STATUS_REG);
+
 		/*
 		 *  IRQ_7 (BAT_LOW) Indicates a supply voltage below the
 		 *    programmed threshold. 9.5.4
@@ -228,39 +293,12 @@ static void rf2xx_thread_main(void *arg)
 		 *  IRQ_0 (PLL_LOCK) Indicates PLL lock.
 		 */
 		if (isr_status & (1 << RF2XX_RX_START)) {
-			ctx->trx_state = RF2XX_TRX_PHY_BUSY_RX;
-			k_timer_start(&ctx->trx_isr_timeout, K_MSEC(10), 0);
-		} else if (isr_status & (1 << RF2XX_TRX_END)) {
-			if (ctx->trx_state == RF2XX_TRX_PHY_BUSY_RX) {
-				/* Ensures that automatically ACK will be sent
-				 * when requested
-				 */
-				while (rf2xx_iface_reg_read(dev,
-							    RF2XX_TRX_STATUS_REG) ==
-				       RF2XX_TRX_PHY_STATUS_BUSY_RX_AACK) {
-				};
-
-				/* Set PLL_ON to avoid transceiver receive
-				 * new data until finish reading process
-				 */
-				rf2xx_trx_set_state(dev,
-						    RF2XX_TRX_PHY_STATE_CMD_PLL_ON);
-				k_timer_stop(&ctx->trx_isr_timeout);
-				rf2xx_trx_rx(dev);
-				rf2xx_trx_set_state(dev,
-						    RF2XX_TRX_PHY_STATE_CMD_RX_AACK_ON);
-				/*if (ctx->trx_state == RF2XX_TRX_PHY_BUSY_TX)*/
-			} else {
-				ctx->trx_trac =
-					(rf2xx_iface_reg_read(dev,
-							      RF2XX_TRX_STATE_REG) >>
-					 RF2XX_TRAC_STATUS) & 7;
-				k_sem_give(&ctx->trx_tx_sync);
-				rf2xx_trx_set_rx_state(dev);
+			if (ctx->trx_model != RF2XX_TRX_MODEL_231) {
+				rf2xx_iface_sram_read(dev, 0, &ctx->rx_phr, 1);
 			}
-			ctx->trx_state = RF2XX_TRX_PHY_STATE_IDLE;
+		} else if (isr_status & (1 << RF2XX_TRX_END)) {
+			rf2xx_process_trx_end(dev);
 		}
-		k_mutex_unlock(&ctx->phy_mutex);
 	}
 }
 
@@ -434,37 +472,14 @@ static int rf2xx_tx(struct device *dev,
 	ARG_UNUSED(pkt);
 
 	struct rf2xx_context *ctx = dev->driver_data;
-	bool abort = true;
 	int response = 0;
 
-	k_mutex_lock(&ctx->phy_mutex, K_FOREVER);
-	/* Reset semaphore in case ACK was received after timeout */
+	rf2xx_trx_set_tx_state(dev);
+	rf2xx_iface_reg_read(dev, RF2XX_IRQ_STATUS_REG);
+
 	k_sem_reset(&ctx->trx_tx_sync);
-
-	if (ctx->trx_state == RF2XX_TRX_PHY_STATE_IDLE) {
-		ctx->trx_state = RF2XX_TRX_PHY_BUSY_TX;
-		abort = false;
-
-		/**
-		 * Set extended TX mode
-		 * Datasheet: chapter 7.2 Extended Operating Mode
-		 */
-		rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_TX_ARET_ON);
-		rf2xx_iface_reg_read(dev, RF2XX_IRQ_STATUS_REG);
-		rf2xx_iface_frame_write(dev, frag->data, frag->len);
-		rf2xx_iface_phy_tx_start(dev);
-	}
-
-	k_mutex_unlock(&ctx->phy_mutex);
-
-	if (abort) {
-		LOG_DBG("TX Abort, TRX isn't idle!");
-		return -EBUSY;
-	}
-
-	/**
-	 * Wait transceiver...
-	 */
+	rf2xx_iface_frame_write(dev, frag->data, frag->len);
+	rf2xx_iface_phy_tx_start(dev);
 	k_sem_take(&ctx->trx_tx_sync, K_FOREVER);
 
 	switch (ctx->trx_trac) {
@@ -506,11 +521,11 @@ static int rf2xx_start(struct device *dev)
 	const struct rf2xx_config *conf = dev->config->config_info;
 	struct rf2xx_context *ctx = dev->driver_data;
 
-	k_mutex_lock(&ctx->phy_mutex, K_FOREVER);
+	rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_TRX_OFF);
+	rf2xx_iface_reg_read(dev, RF2XX_IRQ_STATUS_REG);
 	gpio_pin_interrupt_configure(ctx->irq_gpio, conf->irq.pin,
 				     GPIO_INT_EDGE_TO_ACTIVE);
 	rf2xx_trx_set_rx_state(dev);
-	k_mutex_unlock(&ctx->phy_mutex);
 
 	return 0;
 }
@@ -520,11 +535,10 @@ static int rf2xx_stop(struct device *dev)
 	const struct rf2xx_config *conf = dev->config->config_info;
 	struct rf2xx_context *ctx = dev->driver_data;
 
-	k_mutex_lock(&ctx->phy_mutex, K_FOREVER);
 	gpio_pin_interrupt_configure(ctx->irq_gpio, conf->irq.pin,
 				     GPIO_INT_DISABLE);
 	rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_TRX_OFF);
-	k_mutex_unlock(&ctx->phy_mutex);
+	rf2xx_iface_reg_read(dev, RF2XX_IRQ_STATUS_REG);
 
 	return 0;
 }
@@ -545,8 +559,6 @@ static int power_on_and_setup(struct device *dev)
 	struct rf2xx_context *ctx = dev->driver_data;
 	u8_t config;
 
-	ctx->trx_state = RF2XX_TRX_PHY_STATE_IDLE;
-
 	rf2xx_iface_phy_rst(dev);
 
 	/* Sync transceiver state */
@@ -721,11 +733,8 @@ static int rf2xx_init(struct device *dev)
 
 	LOG_DBG("\nInitialize RF2XX Transceiver\n");
 
-	k_mutex_init(&ctx->phy_mutex);
 	k_sem_init(&ctx->trx_tx_sync, 0, 1);
 	k_sem_init(&ctx->trx_isr_lock, 0, 1);
-	k_timer_init(&ctx->trx_isr_timeout, trx_isr_timeout, NULL);
-	k_timer_user_data_set(&ctx->trx_isr_timeout, ctx);
 
 	if (configure_gpios(dev) != 0) {
 		LOG_ERR("Configuring GPIOS failed");
@@ -860,12 +869,10 @@ static struct ieee802154_radio_api rf2xx_radio_api = {
 		.spi.cs.devname = DT_INST_##n##_ATMEL_RF2XX_CS_GPIOS_CONTROLLER,   \
 		.spi.cs.pin = DT_INST_##n##_ATMEL_RF2XX_CS_GPIOS_PIN,		   \
 		.spi.cs.flags = DT_INST_##n##_ATMEL_RF2XX_CS_GPIOS_FLAGS,	   \
-	}
+	};
 
 #define IEEE802154_RF2XX_DEVICE_DATA(n)			   \
-	static struct rf2xx_context rf2xx_ctx_data_##n = { \
-		.trx_state = RF2XX_TRX_PHY_STATE_INITIAL,  \
-	}
+	static struct rf2xx_context rf2xx_ctx_data_##n;
 
 #define IEEE802154_RF2XX_RAW_DEVICE_INIT(n)	   \
 	DEVICE_AND_API_INIT(			   \

drivers/ieee802154/ieee802154_rf2xx.h

@@ -1,7 +1,7 @@
 /* ieee802154_rf2xx.h - IEEE 802.15.4 Driver definition for ATMEL RF2XX */
 
 /*
- * Copyright (c) 2019 Gerson Fernando Budke
+ * Copyright (c) 2019-2020 Gerson Fernando Budke
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -65,14 +65,6 @@ enum rf2xx_trx_state_trac_t {
 	RF2XX_TRX_PHY_STATE_TRAC_INVALID                = 0x07,
 };
 
-enum rf2xx_trx_state_t {
-	RF2XX_TRX_PHY_STATE_INITIAL,
-	RF2XX_TRX_PHY_STATE_IDLE,
-	RF2XX_TRX_PHY_STATE_SLEEP,
-	RF2XX_TRX_PHY_BUSY_RX,
-	RF2XX_TRX_PHY_BUSY_TX,
-};
-
 enum rf2xx_trx_model_t {
 	RF2XX_TRX_MODEL_INV     = 0x00,
 	RF2XX_TRX_MODEL_230     = 0x02,
@@ -127,11 +119,8 @@ struct rf2xx_context {
 			      CONFIG_IEEE802154_RF2XX_RX_STACK_SIZE);
 	struct k_sem trx_isr_lock;
 	struct k_sem trx_tx_sync;
-	struct k_timer trx_isr_timeout;
-	struct k_mutex phy_mutex;
 
 	enum rf2xx_trx_model_t trx_model;
-	enum rf2xx_trx_state_t trx_state;
 	enum rf2xx_trx_state_trac_t trx_trac;
 
 	u8_t mac_addr[8];
@@ -139,6 +128,7 @@ struct rf2xx_context {
 	u8_t pkt_ed;
 	s8_t trx_rssi_base;
 	u8_t trx_version;
+	u8_t rx_phr;
 };
 
 #endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_H_ */

drivers/ieee802154/ieee802154_rf2xx_iface.c

@@ -1,7 +1,7 @@
 /* ieee802154_rf2xx_iface.c - ATMEL RF2XX IEEE 802.15.4 Interface */
 
 /*
- * Copyright (c) 2019 Gerson Fernando Budke
+ * Copyright (c) 2019-2020 Gerson Fernando Budke
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -248,3 +248,49 @@ void rf2xx_iface_frame_write(struct device *dev,
 	LOG_DBG("Frame W: PhyStatus: %02X. length: %02X", status, length);
 	LOG_HEXDUMP_DBG(data, length, "payload");
 }
+
+void rf2xx_iface_sram_read(struct device *dev,
+			    u8_t address,
+			    u8_t *data,
+			    u8_t length)
+{
+	const struct rf2xx_context *ctx = dev->driver_data;
+	u8_t cmd = RF2XX_RF_CMD_SRAM_R;
+	u8_t status[2];
+
+	const struct spi_buf tx_buf[2] = {
+		{
+			.buf = &cmd,
+			.len = 1
+		},
+		{
+			.buf = &address,
+			.len = 1
+		},
+	};
+	const struct spi_buf_set tx = {
+		.buffers = tx_buf,
+		.count = 2
+	};
+	const struct spi_buf rx_buf[2] = {
+		{
+			.buf = status,
+			.len = 2
+		},
+		{
+			.buf = data,
+			.len = length
+		},
+	};
+	const struct spi_buf_set rx = {
+		.buffers = rx_buf,
+		.count = 2
+	};
+
+	if (spi_transceive(ctx->spi, &ctx->spi_cfg, &tx, &rx) != 0) {
+		LOG_ERR("Failed to exec rf2xx_sram_read");
+	}
+
+	LOG_DBG("SRAM R: length: %02X, status: %02X", length, status[0]);
+	LOG_HEXDUMP_DBG(data, length, "content");
+}

drivers/ieee802154/ieee802154_rf2xx_iface.h

@@ -1,7 +1,7 @@
 /* ieee802154_rf2xx_iface.h - ATMEL RF2XX transceiver interface */
 
 /*
- * Copyright (c) 2019 Gerson Fernando Budke
+ * Copyright (c) 2019-2020 Gerson Fernando Budke
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -107,4 +107,19 @@ void rf2xx_iface_frame_write(struct device *dev,
 			     u8_t *data,
 			     u8_t length);
 
+/**
+ * @brief Reads sram data from the transceiver
+ *
+ * This function reads the sram data of the transceiver.
+ *
+ * @param[in]   dev     Transceiver device instance
+ * @param[in]   address Start address to be read
+ * @param[out]  data    Pointer to the location to store data
+ * @param[in]   length  Number of bytes to be read from the sram space
+ */
+void rf2xx_iface_sram_read(struct device *dev,
+			    u8_t address,
+			    u8_t *data,
+			    u8_t length);
+
 #endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_IFACE_H_ */

drivers/kscan/kscan_handlers.c

@@ -19,12 +19,16 @@ static inline int z_vrfy_kscan_config(struct device *dev,
 
 static inline int z_vrfy_kscan_disable_callback(struct device *dev);
 {
+	Z_OOPS(Z_SYSCALL_DRIVER_KSCAN(dev, disable_callback));
+
 	return z_impl_kscan_disable_callback((struct device *)dev);
 }
 #include <syscalls/kscan_disable_callback_mrsh.c>
 
 static int z_vrfy_kscan_enable_callback(struct device *dev);
 {
+	Z_OOPS(Z_SYSCALL_DRIVER_KSCAN(dev, enable_callback));
+
 	return z_impl_kscan_enable_callback((struct device *)dev);
 }
 #include <syscalls/kscan_enable_callback_mrsh.c>

drivers/serial/uart_sam0.c

@@ -940,7 +940,7 @@ static const struct uart_driver_api uart_sam0_driver_api = {
 #define UART_SAM0_IRQ_HANDLER_FUNC(n)					\
 	.irq_config_func = uart_sam0_irq_config_##n,
 
-#ifdef DT_ATMEL_SAM0_UART_0_IRQ_3
+#ifdef DT_INST_0_ATMEL_SAM0_UART_IRQ_3
 #define UART_SAM0_IRQ_HANDLER(n)					\
 static void uart_sam0_irq_config_##n(struct device *dev)		\
 {									\

drivers/timer/riscv_machine_timer.c

@@ -83,7 +83,8 @@ static void timer_isr(void *arg)
 int z_clock_driver_init(struct device *device)
 {
 	IRQ_CONNECT(RISCV_MACHINE_TIMER_IRQ, 0, timer_isr, NULL, 0);
-	set_mtimecmp(mtime() + CYC_PER_TICK);
+	last_count = mtime();
+	set_mtimecmp(last_count + CYC_PER_TICK);
 	irq_enable(RISCV_MACHINE_TIMER_IRQ);
 	return 0;
 }

drivers/watchdog/Kconfig

@@ -14,13 +14,8 @@ if WATCHDOG
 
 config WDT_DISABLE_AT_BOOT
 	bool "Disable at boot"
-	default y
 	help
-	  Disable watchdog at Zephyr system startup for the SoCs that enable
-	  the watchdog by default after reset.
-
-	  Note that disabling this configuration option does not enable the
-	  watchdog for the SoCs that boot with the watchdog disabled.
+	  Disable watchdog at Zephyr system startup.
 
 module = WDT
 module-str = watchdog

drivers/watchdog/wdt_iwdg_stm32.c

@@ -114,17 +114,20 @@ static int iwdg_stm32_install_timeout(struct device *dev,
 
 	tickstart = k_uptime_get_32();
 
-	while (LL_IWDG_IsReady(iwdg) == 0) {
-		/* Wait until WVU, RVU, PVU are reset before updating  */
+	LL_IWDG_EnableWriteAccess(iwdg);
+
+	LL_IWDG_SetPrescaler(iwdg, prescaler);
+	LL_IWDG_SetReloadCounter(iwdg, reload);
+
+	/* Wait for the update operation completed */
+	while (LL_IWDG_IsReady(iwdg) != 0) {
 		if ((k_uptime_get_32() - tickstart) > IWDG_DEFAULT_TIMEOUT) {
 			return -ENODEV;
 		}
 	}
 
-	LL_IWDG_EnableWriteAccess(iwdg);
-
-	LL_IWDG_SetPrescaler(iwdg, prescaler);
-	LL_IWDG_SetReloadCounter(iwdg, reload);
+	/* Reload counter just before leaving */
+	LL_IWDG_ReloadCounter(iwdg);
 
 	return 0;
 }

dts/arm/atmel/sam3x.dtsi

@@ -35,6 +35,17 @@
 	};
 
 	soc {
+		/* Only used for HWINFO device ID */
+		flash-controller@400e0a00 {
+			compatible = "atmel,sam-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x400e0a00 0x200>;
+			peripheral-id = <6>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		wdog: watchdog@400e1a50 {
 			compatible = "atmel,sam-watchdog";
 			reg = <0x400e1a50 0xc>;

dts/arm/atmel/sam4e.dtsi

@@ -34,6 +34,17 @@
 	};
 
 	soc {
+		/* Only used for HWINFO device ID */
+		flash-controller@400e0a00 {
+			compatible = "atmel,sam-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x400e0a00 0x200>;
+			peripheral-id = <6>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		wdog: watchdog@400e1850 {
 			compatible = "atmel,sam-watchdog";
 			reg = <0x400e1850 0x10>;

dts/arm/atmel/sam4s.dtsi

@@ -35,6 +35,17 @@
 	};
 
 	soc {
+		/* Only used for HWINFO device ID */
+		flash-controller@400e0a00 {
+			compatible = "atmel,sam-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x400e0a00 0x200>;
+			peripheral-id = <6>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		wdog: watchdog@400e1450 {
 			compatible = "atmel,sam-watchdog";
 			reg = <0x400e1450 0xc>;

include/bluetooth/bluetooth.h

@@ -322,6 +322,7 @@ struct bt_le_adv_param {
   */
 #define BT_LE_ADV_PARAM(_options, _int_min, _int_max) \
 		((struct bt_le_adv_param[]) { { \
+			.id = BT_ID_DEFAULT, \
 			.options = (_options), \
 			.interval_min = (_int_min), \
 			.interval_max = (_int_max), \

include/bluetooth/gatt.h

@@ -817,10 +817,11 @@ ssize_t bt_gatt_attr_read_cpf(struct bt_conn *conn,
 #define BT_GATT_ATTRIBUTE(_uuid, _perm, _read, _write, _value)		\
 {									\
 	.uuid = _uuid,							\
-	.perm = _perm,							\
 	.read = _read,							\
 	.write = _write,						\
 	.user_data = _value,						\
+	.handle = 0,							\
+	.perm = _perm,							\
 }
 
 /** @brief Notification complete result callback.

include/drivers/hwinfo.h

@@ -39,7 +39,9 @@ extern "C" {
  * @param buffer  Buffer to write the ID to.
  * @param length  Max length of the buffer.
  *
- * @retval size of the device ID copied or negative on error.
+ * @retval size of the device ID copied.
+ * @retval -ENOTSUP if there is no implementation for the particular device.
+ * @retval any negative value on driver specific errors.
  */
 __syscall ssize_t hwinfo_get_device_id(u8_t *buffer, size_t length);
 

include/sys/arch_interface.h

@@ -578,6 +578,8 @@ void arch_mem_domain_destroy(struct k_mem_domain *domain);
  * if the supplied memory buffer spans multiple enabled memory management
  * regions (even if all such regions permit user access).
  *
+ * @warning 0 size buffer has undefined behavior.
+ *
  * @param addr start address of the buffer
  * @param size the size of the buffer
  * @param write If nonzero, additionally check if the area is writable.

include/sys/math_extras.h

@@ -28,6 +28,7 @@
  * true if the operation overflowed.
  */
 /**@{*/
+static bool u16_add_overflow(u16_t a, u16_t b, u16_t *result);
 static bool u32_add_overflow(u32_t a, u32_t b, u32_t *result);
 static bool u64_add_overflow(u64_t a, u64_t b, u64_t *result);
 static bool size_add_overflow(size_t a, size_t b, size_t *result);
@@ -40,6 +41,7 @@ static bool size_add_overflow(size_t a, size_t b, size_t *result);
  * true if the operation overflowed.
  */
 /**@{*/
+static bool u16_mul_overflow(u16_t a, u16_t b, u16_t *result);
 static bool u32_mul_overflow(u32_t a, u32_t b, u32_t *result);
 static bool u64_mul_overflow(u64_t a, u64_t b, u64_t *result);
 static bool size_mul_overflow(size_t a, size_t b, size_t *result);

include/sys/math_extras_impl.h

@@ -29,6 +29,11 @@
 #endif
 
 #if use_builtin(__builtin_add_overflow)
+static inline bool u16_add_overflow(u16_t a, u16_t b, u16_t *result)
+{
+	return __builtin_add_overflow(a, b, result);
+}
+
 static inline bool u32_add_overflow(u32_t a, u32_t b, u32_t *result)
 {
 	return __builtin_add_overflow(a, b, result);
@@ -44,6 +49,15 @@ static inline bool size_add_overflow(size_t a, size_t b, size_t *result)
 	return __builtin_add_overflow(a, b, result);
 }
 #else /* !use_builtin(__builtin_add_overflow) */
+static inline bool u16_add_overflow(u16_t a, u16_t b, u16_t *result)
+{
+	u16_t c = a + b;
+
+	*result = c;
+
+	return c < a;
+}
+
 static inline bool u32_add_overflow(u32_t a, u32_t b, u32_t *result)
 {
 	u32_t c = a + b;
@@ -73,6 +87,11 @@ static inline bool size_add_overflow(size_t a, size_t b, size_t *result)
 #endif /* use_builtin(__builtin_add_overflow) */
 
 #if use_builtin(__builtin_mul_overflow)
+static inline bool u16_mul_overflow(u16_t a, u16_t b, u16_t *result)
+{
+	return __builtin_mul_overflow(a, b, result);
+}
+
 static inline bool u32_mul_overflow(u32_t a, u32_t b, u32_t *result)
 {
 	return __builtin_mul_overflow(a, b, result);
@@ -88,6 +107,15 @@ static inline bool size_mul_overflow(size_t a, size_t b, size_t *result)
 	return __builtin_mul_overflow(a, b, result);
 }
 #else /* !use_builtin(__builtin_mul_overflow) */
+static inline bool u16_mul_overflow(u16_t a, u16_t b, u16_t *result)
+{
+	u16_t c = a * b;
+
+	*result = c;
+
+	return a != 0 && (c / a) != b;
+}
+
 static inline bool u32_mul_overflow(u32_t a, u32_t b, u32_t *result)
 {
 	u32_t c = a * b;