release: Zephyr 2.7.3

Set version to 2.7.3

Fixes #49354

Signed-off-by: Christopher Friedt <cfriedt@fb.com>

.github/workflows/backport_issue_check.yml

@@ -0,0 +1,30 @@
+name: Backport Issue Check
+
+on:
+  pull_request_target:
+    branches:
+      - v*-branch
+
+jobs:
+  backport:
+    name: Backport Issue Check
+    runs-on: ubuntu-latest
+
+    steps:
+      - name: Check out source code
+        uses: actions/checkout@v2
+
+      - name: Install Python dependencies
+        run: |
+          sudo pip3 install -U setuptools wheel pip
+          pip3 install -U pygithub
+
+      - name: Run backport issue checker
+        env:
+          GITHUB_TOKEN: ${{ secrets.ZB_GITHUB_TOKEN }}
+        run: |
+          ./scripts/release/list_backports.py \
+            -o ${{ github.event.repository.owner.login }} \
+            -r ${{ github.event.repository.name }} \
+            -b ${{ github.event.pull_request.base.ref }} \
+            -p ${{ github.event.pull_request.number }}

.github/workflows/bluetooth-tests-publish.yaml

@@ -0,0 +1,29 @@
+name: Publish Bluetooth Tests Results
+
+on:
+  workflow_run:
+    workflows: ["Bluetooth Tests"]
+    types:
+      - completed
+jobs:
+  bluetooth-test-results:
+    name: "Publish Bluetooth Test Results"
+    runs-on: ubuntu-latest
+    if: github.event.workflow_run.conclusion != 'skipped'
+
+    steps:
+      - name: Download artifacts
+        uses: dawidd6/action-download-artifact@v2
+        with:
+          workflow: bluetooth-tests.yaml
+          run_id: ${{ github.event.workflow_run.id }}
+
+      - name: Publish Bluetooth Test Results
+        uses: EnricoMi/publish-unit-test-result-action@v1
+        with:
+          check_name: Bluetooth Test Results
+          comment_mode: off
+          commit: ${{ github.event.workflow_run.head_sha }}
+          event_file: event/event.json
+          event_name: ${{ github.event.workflow_run.event }}
+          files: "bluetooth-test-results/**/bsim_results.xml"

.github/workflows/bluetooth-tests.yaml

@@ -1,7 +1,7 @@
 name: Bluetooth Tests
 
 on:
-  pull_request_target:
+  pull_request:
     paths:
       - "west.yml"
       - "subsys/bluetooth/**"
@@ -39,9 +39,6 @@ jobs:
 
       - name: checkout
         uses: actions/checkout@v2
-        with:
-          ref: ${{ github.event.pull_request.head.sha }}
-          fetch-depth: 0
 
       - name: west setup
         run: |
@@ -60,26 +57,15 @@ jobs:
         if: always()
         uses: actions/upload-artifact@v2
         with:
-          name: Bluetooth Test Results
-          path: ./bsim_bt_out/bsim_results.xml
+          name: bluetooth-test-results
+          path: |
+            ./bsim_bt_out/bsim_results.xml
+            ${{ github.event_path }}
 
-  bluetooth-test-results:
-    name: "Publish Bluetooth Test Results"
-    needs: bluetooth-test-build
-    runs-on: ubuntu-20.04
-      # the build-and-test job might be skipped, we don't need to run this job then
-    if: success() || failure()
-
-    steps:
-      - name: Download Artifacts
-        uses: actions/download-artifact@v2
+      - name: Upload Event Details
+        if: always()
+        uses: actions/upload-artifact@v2
         with:
-          path: artifacts
-
-      - name: Publish Bluetooth Test Results
-        uses: EnricoMi/publish-unit-test-result-action@v1
-        with:
-          check_name: Bluetooth Test Results
-          github_token: ${{ secrets.GITHUB_TOKEN }}
-          files: "**/bsim_results.xml"
-          comment_mode: off
+          name: event
+          path: |
+            ${{ github.event_path }}

.github/workflows/clang.yaml

@@ -39,6 +39,7 @@ jobs:
         with:
           ref: ${{ github.event.pull_request.head.sha }}
           fetch-depth: 0
+          persist-credentials: false
 
       - name: Environment Setup
         run: |

.github/workflows/manifest.yml

@@ -15,6 +15,7 @@ jobs:
           path: zephyrproject/zephyr
           ref: ${{ github.event.pull_request.head.sha }}
           fetch-depth: 0
+          persist-credentials: false
 
       - name: Manifest
         uses: zephyrproject-rtos/action-manifest@2f1ad2908599d4fe747f886f9d733dd7eebae4ef

.github/workflows/twister.yaml

@@ -49,6 +49,7 @@ jobs:
         with:
           ref: ${{ github.event.pull_request.head.sha }}
           fetch-depth: 0
+          persist-credentials: false
 
       - name: Environment Setup
         if: github.event_name == 'pull_request_target'
@@ -137,6 +138,7 @@ jobs:
         with:
           ref: ${{ github.event.pull_request.head.sha }}
           fetch-depth: 0
+          persist-credentials: false
 
       - name: Environment Setup
         run: |

CMakeLists.txt

@@ -1385,6 +1385,17 @@ if(CONFIG_OUTPUT_PRINT_MEMORY_USAGE)
   endif()
 endif()
 
+if(NOT CONFIG_EXCEPTIONS)
+  set(eh_frame_section ".eh_frame")
+else()
+  set(eh_frame_section "")
+endif()
+set(remove_sections_argument_list "")
+foreach(section .comment COMMON ${eh_frame_section})
+  list(APPEND remove_sections_argument_list
+    $<TARGET_PROPERTY:bintools,elfconvert_flag_section_remove>${section})
+endforeach()
+
 if(CONFIG_BUILD_OUTPUT_HEX OR BOARD_FLASH_RUNNER STREQUAL openocd)
   get_property(elfconvert_formats TARGET bintools PROPERTY elfconvert_formats)
   if(ihex IN_LIST elfconvert_formats)
@@ -1394,9 +1405,7 @@ if(CONFIG_BUILD_OUTPUT_HEX OR BOARD_FLASH_RUNNER STREQUAL openocd)
               $<TARGET_PROPERTY:bintools,elfconvert_flag>
               ${GAP_FILL}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_outtarget>ihex
-              $<TARGET_PROPERTY:bintools,elfconvert_flag_section_remove>.comment
-              $<TARGET_PROPERTY:bintools,elfconvert_flag_section_remove>COMMON
-              $<TARGET_PROPERTY:bintools,elfconvert_flag_section_remove>.eh_frame
+              ${remove_sections_argument_list}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_infile>${KERNEL_ELF_NAME}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_outfile>${KERNEL_HEX_NAME}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_final>
@@ -1418,9 +1427,7 @@ if(CONFIG_BUILD_OUTPUT_BIN)
               $<TARGET_PROPERTY:bintools,elfconvert_flag>
               ${GAP_FILL}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_outtarget>binary
-              $<TARGET_PROPERTY:bintools,elfconvert_flag_section_remove>.comment
-              $<TARGET_PROPERTY:bintools,elfconvert_flag_section_remove>COMMON
-              $<TARGET_PROPERTY:bintools,elfconvert_flag_section_remove>.eh_frame
+              ${remove_sections_argument_list}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_infile>${KERNEL_ELF_NAME}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_outfile>${KERNEL_BIN_NAME}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_final>

VERSION

@@ -1,5 +1,5 @@
 VERSION_MAJOR = 2
 VERSION_MINOR = 7
-PATCHLEVEL = 1
+PATCHLEVEL = 3
 VERSION_TWEAK = 0
 EXTRAVERSION =

arch/arm/core/aarch32/cortex_m/fault.c

@@ -849,7 +849,7 @@ static inline z_arch_esf_t *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_ret
 	bool *nested_exc)
 {
 	bool alternative_state_exc = false;
-	z_arch_esf_t *ptr_esf;
+	z_arch_esf_t *ptr_esf = NULL;
 
 	*nested_exc = false;
 

arch/arm/core/aarch32/cortex_m/timing.c

@@ -40,7 +40,7 @@ static inline uint64_t z_arm_dwt_freq_get(void)
 	/* SysTick and DWT both run at CPU frequency,
 	 * reflected in the system timer HW cycles/sec.
 	 */
-	return CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
+	return sys_clock_hw_cycles_per_sec();
 #else
 	static uint64_t dwt_frequency;
 	uint32_t cyc_start, cyc_end;

arch/arm/include/aarch32/cortex_m/stack.h

@@ -26,7 +26,7 @@
 extern "C" {
 #endif
 
-extern K_KERNEL_STACK_ARRAY_DEFINE(z_interrupt_stacks, CONFIG_MP_NUM_CPUS,
+K_KERNEL_STACK_ARRAY_EXTERN(z_interrupt_stacks, CONFIG_MP_NUM_CPUS,
 				   CONFIG_ISR_STACK_SIZE);
 
 /**

arch/arm64/core/isr_wrapper.S

@@ -101,9 +101,28 @@ spurious_continue:
 	 * x0: 1st thread in the ready queue
 	 * x1: _current thread
 	 */
+
+#ifdef CONFIG_SMP
+	/*
+	 * 2 possibilities here:
+	 *  - x0 != NULL (implies x0 != x1): we need to context switch and set
+	 *    the switch_handle in the context switch code
+	 *  - x0 == NULL: no context switch
+	 */
+	cmp	x0, #0x0
+	bne	switch
+
+	/*
+	 * No context switch. Restore x0 from x1 (they are the same thread).
+	 * See also comments to z_arch_get_next_switch_handle()
+	 */
+	mov	x0, x1
+	b	exit
+switch:
+#else
 	cmp	x0, x1
 	beq	exit
-
+#endif
 	/* Switch thread */
 	bl	z_arm64_context_switch
 

arch/arm64/core/reset.c

@@ -129,7 +129,11 @@ void z_arm64_el2_init(void)
 
 	zero_cntvoff_el2();		/* Set 64-bit virtual timer offset to 0 */
 	zero_cnthctl_el2();
+#ifdef CONFIG_CPU_AARCH64_CORTEX_R
+	zero_cnthps_ctl_el2();
+#else
 	zero_cnthp_ctl_el2();
+#endif
 	/*
 	 * Enable this if/when we use the hypervisor timer.
 	 * write_cnthp_cval_el2(~(uint64_t)0);

arch/arm64/core/thread.c

@@ -124,9 +124,28 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 
 void *z_arch_get_next_switch_handle(struct k_thread **old_thread)
 {
+	/*
+	 * When returning from this function we will have the current thread
+	 * onto the stack to be popped in x1 and the next thread in x0 returned
+	 * from z_get_next_switch_handle() (see isr_wrapper.S)
+	 */
 	*old_thread =  _current;
 
+#ifdef CONFIG_SMP
+	/*
+	 * XXX: see thread in #41840 and #40795
+	 *
+	 * The scheduler API requires a complete switch handle here, but arm64
+	 * optimizes things such that the callee-save registers are still
+	 * unsaved here (they get written out in z_arm64_context_switch()
+	 * below).  So pass a NULL instead, which the scheduler will store into
+	 * the thread switch_handle field.  The resulting thread won't be
+	 * switched into until we write that ourselves.
+	 */
+	return z_get_next_switch_handle(NULL);
+#else
 	return z_get_next_switch_handle(*old_thread);
+#endif
 }
 
 #ifdef CONFIG_USERSPACE

arch/x86/core/CMakeLists.txt

@@ -6,6 +6,7 @@ zephyr_library()
 zephyr_library_sources(cpuhalt.c)
 zephyr_library_sources(prep_c.c)
 zephyr_library_sources(fatal.c)
+zephyr_library_sources(cpuid.c)
 zephyr_library_sources(spec_ctrl.c)
 
 zephyr_library_sources_ifdef(CONFIG_X86_MEMMAP memmap.c)

arch/x86/core/cpuid.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <cpuid.h> /* Header provided by the toolchain. */
+
+#include <kernel_structs.h>
+#include <arch/x86/cpuid.h>
+#include <kernel.h>
+
+uint32_t z_x86_cpuid_extended_features(void)
+{
+	uint32_t eax, ebx, ecx = 0U, edx;
+
+	if (__get_cpuid(CPUID_EXTENDED_FEATURES_LVL,
+			&eax, &ebx, &ecx, &edx) == 0) {
+		return 0;
+	}
+
+	return edx;
+}
+
+#define INITIAL_APIC_ID_SHIFT (24)
+#define INITIAL_APIC_ID_MASK (0xFF)
+
+uint8_t z_x86_cpuid_get_current_physical_apic_id(void)
+{
+	uint32_t eax, ebx, ecx, edx;
+
+	if (IS_ENABLED(CONFIG_X2APIC)) {
+		/* leaf 0x1F should be used first prior to using 0x0B */
+		if (__get_cpuid(CPUID_EXTENDED_TOPOLOGY_ENUMERATION_V2,
+				&eax, &ebx, &ecx, &edx) == 0) {
+			if (__get_cpuid(CPUID_EXTENDED_TOPOLOGY_ENUMERATION,
+					&eax, &ebx, &ecx, &edx) == 0) {
+				return 0;
+			}
+		}
+	} else {
+		if (__get_cpuid(CPUID_BASIC_INFO_1,
+				&eax, &ebx, &ecx, &edx) == 0) {
+			return 0;
+		}
+
+		edx = (ebx >> INITIAL_APIC_ID_SHIFT);
+	}
+
+	return (uint8_t)(edx & INITIAL_APIC_ID_MASK);
+}

arch/x86/core/ia32/thread.c

@@ -114,4 +114,18 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	thread->arch.excNestCount = 0;
 #endif /* CONFIG_LAZY_FPU_SHARING */
 	thread->arch.flags = 0;
+
+	/*
+	 * When "eager FPU sharing" mode is enabled, FPU registers must be
+	 * initialised at the time of thread creation because the floating-point
+	 * context is always active and no further FPU initialisation is performed
+	 * later.
+	 */
+#if defined(CONFIG_EAGER_FPU_SHARING)
+	thread->arch.preempFloatReg.floatRegsUnion.fpRegs.fcw = 0x037f;
+	thread->arch.preempFloatReg.floatRegsUnion.fpRegs.ftw = 0xffff;
+#if defined(CONFIG_X86_SSE)
+	thread->arch.preempFloatReg.floatRegsUnion.fpRegsEx.mxcsr = 0x1f80;
+#endif /* CONFIG_X86_SSE */
+#endif /* CONFIG_EAGER_FPU_SHARING */
 }

arch/x86/core/pcie.c

@@ -16,6 +16,8 @@
 #include <kernel_arch_func.h>
 #include <device.h>
 #include <drivers/pcie/msi.h>
+#include <drivers/interrupt_controller/sysapic.h>
+#include <arch/x86/cpuid.h>
 #endif
 
 /* PCI Express Extended Configuration Mechanism (MMIO) */
@@ -179,12 +181,15 @@ static bool get_vtd(void)
 
 /* these functions are explained in include/drivers/pcie/msi.h */
 
+#define MSI_MAP_DESTINATION_ID_SHIFT 12
+#define MSI_RH BIT(3)
+
 uint32_t pcie_msi_map(unsigned int irq,
 		      msi_vector_t *vector)
 {
 	uint32_t map;
-
 	ARG_UNUSED(irq);
+
 #if defined(CONFIG_INTEL_VTD_ICTL)
 #if !defined(CONFIG_PCIE_MSI_X)
 	if (vector != NULL) {
@@ -197,7 +202,15 @@ uint32_t pcie_msi_map(unsigned int irq,
 #endif
 #endif
 	{
-		map = 0xFEE00000U; /* standard delivery to BSP local APIC */
+		uint32_t dest_id;
+
+		dest_id = z_x86_cpuid_get_current_physical_apic_id() <<
+			MSI_MAP_DESTINATION_ID_SHIFT;
+
+		/* Directing to current physical CPU (may not be BSP)
+		 * Destination ID - RH 1 - DM 0
+		 */
+		map = 0xFEE00000U | dest_id | MSI_RH;
 	}
 
 	return map;

arch/x86/core/spec_ctrl.c

@@ -4,13 +4,12 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <cpuid.h> /* Header provided by the toolchain. */
-
 #include <init.h>
 #include <kernel_structs.h>
 #include <kernel_arch_data.h>
 #include <kernel_arch_func.h>
 #include <arch/x86/msr.h>
+#include <arch/x86/cpuid.h>
 #include <kernel.h>
 
 /*
@@ -18,31 +17,13 @@
  * https://software.intel.com/security-software-guidance/api-app/sites/default/files/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
  */
 
-#define CPUID_EXTENDED_FEATURES_LVL 7
-
-/* Bits to check in CPUID extended features */
-#define CPUID_SPEC_CTRL_SSBD	BIT(31)
-#define CPUID_SPEC_CTRL_IBRS	BIT(26)
-
 #if defined(CONFIG_DISABLE_SSBD) || defined(CONFIG_ENABLE_EXTENDED_IBRS)
-static uint32_t cpuid_extended_features(void)
-{
-	uint32_t eax, ebx, ecx = 0U, edx;
-
-	if (__get_cpuid(CPUID_EXTENDED_FEATURES_LVL,
-			&eax, &ebx, &ecx, &edx) == 0) {
-		return 0;
-	}
-
-	return edx;
-}
-
 static int spec_ctrl_init(const struct device *dev)
 {
 	ARG_UNUSED(dev);
 
 	uint32_t enable_bits = 0U;
-	uint32_t cpuid7 = cpuid_extended_features();
+	uint32_t cpuid7 = z_x86_cpuid_extended_features();
 
 #ifdef CONFIG_DISABLE_SSBD
 	if ((cpuid7 & CPUID_SPEC_CTRL_SSBD) != 0U) {

boards/arc/nsim/board.cmake

@@ -12,6 +12,7 @@ endif()
 string(REPLACE "nsim" "mdb" MDB_ARGS "${BOARD}.args")
 if((CONFIG_SOC_NSIM_HS_SMP OR CONFIG_SOC_NSIM_HS6X_SMP))
   board_runner_args(mdb-nsim "--cores=${CONFIG_MP_NUM_CPUS}" "--nsim_args=${MDB_ARGS}")
+  board_runner_args(mdb-hw "--cores=${CONFIG_MP_NUM_CPUS}")
 else()
   board_runner_args(mdb-nsim "--nsim_args=${MDB_ARGS}")
 endif()

boards/arm/bl654_usb/Kconfig.defconfig

@@ -1,6 +1,6 @@
 # BL654 USB adapter board configuration
 
-# Copyright (c) 2021 Laird Connectivity
+# Copyright (c) 2021-2022 Laird Connectivity
 # SPDX-License-Identifier: Apache-2.0
 
 if BOARD_BL654_USB
@@ -13,16 +13,21 @@ config BOARD
 
 # Nordic nRF5 bootloader exists outside of the partitions specified in the
 # DTS file, so we manually override FLASH_LOAD_OFFSET to link the application
-# correctly, after Nordic MBR.
+# correctly, after Nordic MBR, and limit the maximum size to not protude into
+# the bootloader at the end of flash.
 
 # When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION
 # which will make it link into the correct partition specified in DTS file,
-# so no override is necessary.
+# so no override or limit is necessary.
 
 config FLASH_LOAD_OFFSET
 	default 0x1000
 	depends on !USE_DT_CODE_PARTITION
 
+config FLASH_LOAD_SIZE
+	default 0xdf000
+	depends on !USE_DT_CODE_PARTITION
+
 if USB_DEVICE_STACK
 
 config USB_UART_CONSOLE

boards/arm/nucleo_h745zi_q/doc/index.rst

@@ -216,7 +216,7 @@ Run a serial host program to connect with your NUCLEO-H745ZI-Q board.
 
    $ minicom -b 115200 -D /dev/ttyACM0
 
-or use scrreen:
+or use screen:
 
 .. code-block:: console
 
@@ -235,15 +235,20 @@ You should see the following message on the console:
 
    $ Hello World! nucleo_h745zi_q_m7
 
-Blinky example can also be used:
+.. note::
+  Sometimes, flashing is not working. It is necessary to erase the flash
+  (with STM32CubeProgrammer for example) to make it work again.
+
+Similarly, you can build and flash samples on the M4 target. For this, please
+take care of the resource sharing (UART port used for console for instance).
+
+Here is an example for the :ref:`blinky-sample` application on M4 core.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/basic/blinky
-   :board: nucleo_h745zi_q_m7
+   :board: nucleo_h745zi_q_m4
    :goals: build flash
 
-Same way M4 core can be flashed.
-
 .. note::
 
    Flashing both M4 and M7 and pushing RESTART button on the board leads
@@ -261,6 +266,10 @@ You can debug an application in the usual way.  Here is an example for the
    :maybe-skip-config:
    :goals: debug
 
+Debugging with west is currently not available on Cortex M4 side.
+In order to debug a Zephyr application on Cortex M4 side, you can use
+`STM32CubeIDE`_.
+
 .. _Nucleo H745ZI-Q website:
    https://www.st.com/en/evaluation-tools/nucleo-h745zi-q.html
 

boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7_defconfig

@@ -6,6 +6,9 @@ CONFIG_SOC_STM32H745XX=y
 # Board config should be specified since there are 2 possible targets
 CONFIG_BOARD_NUCLEO_H745ZI_Q_M7=y
 
+# Enable the internal SMPS regulator
+CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
+
 # Enable MPU
 CONFIG_ARM_MPU=y
 

boards/arm/nucleo_l552ze_q/doc/nucleol552ze_q.rst

@@ -255,19 +255,17 @@ flashed in the usual way (see :ref:`build_an_application` and
 Flashing
 ========
 
-Nucleo L552ZE Q board includes an ST-LINK/V3E embedded debug tool
-interface. This interface is not yet supported by the openocd version.
-Instead, support can be enabled on pyocd by adding "pack" support with
-the following pyocd command:
+Nucleo L552ZE Q board includes an ST-LINK/V2-1 embedded debug tool
+interface. Support can be enabled on pyocd by adding "pack" support with the
+following pyocd command:
 
 .. code-block:: console
 
    $ pyocd pack --update
    $ pyocd pack --install stm32l552ze
 
-Nucleo L552ZE Q board includes an ST-LINK/V2-1 embedded debug tool
-interface.  This interface is supported by the openocd version
-included in the Zephyr SDK since v0.9.2.
+Alternatively, this interface is supported by the openocd version
+included in the Zephyr SDK since v0.13.1.
 
 Flashing an application to Nucleo L552ZE Q
 ------------------------------------------

boards/arm/nucleo_l552ze_q/support/openocd.cfg

@@ -0,0 +1,19 @@
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+source [find target/stm32l5x.cfg]
+
+# use hardware reset
+reset_config srst_only srst_nogate
+
+$_TARGETNAME configure -event gdb-attach {
+        echo "Debugger attaching: halting execution"
+        reset halt
+        gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+        echo "Debugger detaching: resuming execution"
+        resume
+}

boards/arm/nucleo_wb55rg/board.cmake

@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 board_runner_args(pyocd "--target=stm32wb55rgvx")
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset=hw")
 
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)

boards/arm/nucleo_wb55rg/doc/nucleo_wb55rg.rst

@@ -186,8 +186,9 @@ To operate bluetooth on Nucleo WB55RG, Cortex-M0 core should be flashed with
 a valid STM32WB Coprocessor binaries (either 'Full stack' or 'HCI Layer').
 These binaries are delivered in STM32WB Cube packages, under
 Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/
-To date, interoperability and backward compatibility has been tested and is
-guaranteed up to version 1.5 of STM32Cube package releases.
+For compatibility information with the various versions of these binaries,
+please check `modules/hal/stm32/lib/stm32wb/hci/README <https://github.com/zephyrproject-rtos/hal_stm32/blob/main/lib/stm32wb/hci/README>`__
+in the hal_stm32 repo.
 
 Connections and IOs
 ===================

boards/arm/stm32h735g_disco/stm32h735g_disco_defconfig

@@ -3,6 +3,9 @@
 CONFIG_SOC_SERIES_STM32H7X=y
 CONFIG_SOC_STM32H735XX=y
 
+# Enable the internal SMPS regulator
+CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
+
 # Enable MPU
 CONFIG_ARM_MPU=y
 

boards/arm/stm32h747i_disco/doc/index.rst

@@ -220,24 +220,6 @@ the USB port to prepare it for flashing. Then build and flash your application.
 
 Here is an example for the :ref:`hello_world` application.
 
-.. zephyr-app-commands::
-   :zephyr-app: samples/hello_world
-   :board: stm32h747i_disco_m7
-   :goals: build
-
-Use the following commands to flash either m7 or m4 target:
-
-.. code-block:: console
-
-   $ ./STM32_Programmer_CLI -c port=SWD mode=UR -w <path_to_m7_binary>  0x8000000
-   $ ./STM32_Programmer_CLI -c port=SWD mode=UR -w <path_to_m4_binary>  0x8100000
-
-Alternatively it is possible to flash with OpenOcd but with some restrictions:
-Sometimes, flashing is not working. It is necessary to erase the flash
-(with STM32CubeProgrammer for example) to make it work again.
-Debugging with OpenOCD is currently working for this board only with Cortex M7,
-not Cortex M4.
-
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
    :board: stm32h747i_disco_m7
@@ -255,6 +237,20 @@ You should see the following message on the console:
 
    Hello World! stm32h747i_disco_m7
 
+.. note::
+  Sometimes, flashing is not working. It is necessary to erase the flash
+  (with STM32CubeProgrammer for example) to make it work again.
+
+Similarly, you can build and flash samples on the M4 target. For this, please
+take care of the resource sharing (UART port used for console for instance).
+
+Here is an example for the :ref:`blinky-sample` application on M4 core.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: stm32h747i_disco_m4
+   :goals: build flash
+
 Debugging
 =========
 
@@ -266,6 +262,9 @@ You can debug an application in the usual way.  Here is an example for the
    :board: stm32h747i_disco_m7
    :goals: debug
 
+Debugging with west is currently not available on Cortex M4 side.
+In order to debug a Zephyr application on Cortex M4 side, you can use
+`STM32CubeIDE`_.
 
 .. _STM32H747I-DISCO website:
    http://www.st.com/en/evaluation-tools/stm32h747i-disco.html
@@ -284,3 +283,6 @@ You can debug an application in the usual way.  Here is an example for the
 
 .. _DISCO_H747I modifications for Ethernet:
    https://os.mbed.com/teams/ST/wiki/DISCO_H747I-modifications-for-Ethernet
+
+.. _STM32CubeIDE:
+   https://www.st.com/en/development-tools/stm32cubeide.html

boards/arm/stm32h747i_disco/stm32h747i_disco_m7_defconfig

@@ -9,6 +9,9 @@ CONFIG_BOARD_STM32H747I_DISCO_M7=y
 # enable pinmux
 CONFIG_PINMUX=y
 
+# Enable the internal SMPS regulator
+CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
+
 # enable GPIO
 CONFIG_GPIO=y
 

boards/arm/stm32l562e_dk/doc/index.rst

@@ -252,18 +252,16 @@ Flashing
 ========
 
 STM32L562E-DK Discovery board includes an ST-LINK/V3E embedded debug tool
-interface. This interface is not yet supported by the openocd version.
-Instead, support can be enabled on pyocd by adding "pack" support with
-the following pyocd command:
+interface. Support can be enabled on pyocd by adding "pack" support with the
+following pyocd command:
 
 .. code-block:: console
 
    $ pyocd pack --update
    $ pyocd pack --install stm32l562qe
 
-STM32L562E-DK Discovery board includes an ST-LINK/V2-1 embedded debug tool
-interface.  This interface is supported by the openocd version
-included in the Zephyr SDK since v0.9.2.
+Alternatively, this interface is supported by the openocd version
+included in the Zephyr SDK since v0.13.1.
 
 Flashing an application to STM32L562E-DK Discovery
 --------------------------------------------------

boards/arm/stm32l562e_dk/support/openocd.cfg

@@ -0,0 +1,19 @@
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+source [find target/stm32l5x.cfg]
+
+# use hardware reset
+reset_config srst_only srst_nogate
+
+$_TARGETNAME configure -event gdb-attach {
+        echo "Debugger attaching: halting execution"
+        reset halt
+        gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+        echo "Debugger detaching: resuming execution"
+        resume
+}

boards/arm64/fvp_baser_aemv8r/board.cmake

@@ -3,6 +3,7 @@
 
 set(EMU_PLATFORM armfvp)
 set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R)
+set(ARMFVP_MIN_VERSION 11.16.16)
 
 set(ARMFVP_FLAGS
   -C cluster0.has_aarch64=1

boards/arm64/fvp_baser_aemv8r/doc/index.rst

@@ -27,6 +27,8 @@ To Run the Fixed Virtual Platform simulation tool you must download "Armv8-R AEM
 FVP" from Arm developer [1]_ (This might require the user to register) and
 install it on your host PC.
 
+The current minimum required version of "Armv8-R AEM FVP" is 11.16.16.
+
 Hardware
 ********
 

boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp_defconfig

@@ -33,3 +33,5 @@ CONFIG_PM_CPU_OPS_PSCI=n
 CONFIG_SOC_FVP_AEMV8R_EL2_INIT=y
 
 CONFIG_MP_NUM_CPUS=4
+
+CONFIG_MAX_THREAD_BYTES=3

boards/riscv/esp32c3_devkitm/CMakeLists.txt

@@ -24,6 +24,7 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
     -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}
     -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER}
     -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME}
+    -DPYTHON=${PYTHON_EXECUTABLE}
     BUILD_COMMAND
     ${CMAKE_COMMAND} --build .
     INSTALL_COMMAND ""      # This particular build system has no install command
@@ -35,14 +36,14 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
     BINARY_DIR ${espidf_build_dir}
     CONFIGURE_COMMAND ""
     BUILD_COMMAND
-    python ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
+    ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
     --offset 0x1000 --flash-size 4MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin
     INSTALL_COMMAND ""
     )
 
   if(CONFIG_BUILD_OUTPUT_BIN)
     set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND python ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
+      COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
       ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m
       -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
       ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)

boards/xtensa/esp32/CMakeLists.txt

@@ -23,6 +23,7 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
     -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}
     -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER}
     -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME}
+    -DPYTHON=${PYTHON_EXECUTABLE}
     BUILD_COMMAND
     ${CMAKE_COMMAND} --build .
     INSTALL_COMMAND ""      # This particular build system has no install command
@@ -34,14 +35,14 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
     BINARY_DIR ${espidf_build_dir}
     CONFIGURE_COMMAND ""
     BUILD_COMMAND
-    python ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
+    ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
     --offset 0x1000 --flash-size 4MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin
     INSTALL_COMMAND ""
     )
 
   if(CONFIG_BUILD_OUTPUT_BIN)
     set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND python ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
+      COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
       ARGS --chip esp32 elf2image --flash_mode dio --flash_freq 40m
       -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
       ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)

boards/xtensa/esp32s2_saola/CMakeLists.txt

@@ -23,6 +23,7 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
     -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}
     -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER}
     -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME}
+    -DPYTHON=${PYTHON_EXECUTABLE}
     BUILD_COMMAND
     ${CMAKE_COMMAND} --build .
     INSTALL_COMMAND ""      # This particular build system has no install command
@@ -34,14 +35,14 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
     BINARY_DIR ${espidf_build_dir}
     CONFIGURE_COMMAND ""
     BUILD_COMMAND
-    python ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
+    ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q
     --offset 0x1000 --flash-size 4MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin
     INSTALL_COMMAND ""
     )
 
   if(CONFIG_BUILD_OUTPUT_BIN)
     set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND python ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
+      COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
       ARGS --chip esp32s2 elf2image --flash_mode dio --flash_freq 40m
       -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
       ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)

cmake/emu/armfvp.cmake

@@ -10,6 +10,20 @@ find_program(
   NAMES ${ARMFVP_BIN_NAME}
   )
 
+if ((NOT "${ARMFVP}" STREQUAL "ARMFVP-NOTFOUND") AND (DEFINED ARMFVP_MIN_VERSION))
+  execute_process(
+    COMMAND ${ARMFVP} --version
+    OUTPUT_VARIABLE out
+    OUTPUT_STRIP_TRAILING_WHITESPACE
+  )
+  string(REPLACE "\n" "" out ${out})
+  string(REGEX MATCH "[0-9]+\.[0-9]+\.[0-9]+" armfvp_version ${out})
+  if(${armfvp_version} VERSION_LESS ${ARMFVP_MIN_VERSION})
+    message(WARNING "Found FVP version is \"${armfvp_version}\", "
+      "the minimum required by the current board is \"${ARMFVP_MIN_VERSION}\".")
+  endif()
+endif()
+
 if(CONFIG_ARMV8_A_NS)
   foreach(filetype BL1 FIP)
     if ((NOT DEFINED ARMFVP_${filetype}_FILE) AND (EXISTS "$ENV{ARMFVP_${filetype}_FILE}"))

cmake/host-tools.cmake

@@ -1,6 +1,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
-include(${ZEPHYR_BASE}/cmake/toolchain/zephyr/host-tools.cmake)
+if(ZEPHYR_SDK_HOST_TOOLS)
+  include(${ZEPHYR_BASE}/cmake/toolchain/zephyr/host-tools.cmake)
+endif()
 
 # dtc is an optional dependency
 find_program(

cmake/kconfig.cmake

@@ -90,6 +90,8 @@ endforeach()
 # A list of common environment settings used when invoking Kconfig during CMake
 # configure time or menuconfig and related build target.
 string(REPLACE ";" "\\\;" SHIELD_AS_LIST_ESCAPED "${SHIELD_AS_LIST}")
+# cmake commands are escaped differently
+string(REPLACE ";" "\\;" SHIELD_AS_LIST_ESCAPED_COMMAND "${SHIELD_AS_LIST}")
 
 set(COMMON_KCONFIG_ENV_SETTINGS
   PYTHON_EXECUTABLE=${PYTHON_EXECUTABLE}
@@ -250,7 +252,7 @@ endif()
 execute_process(
   COMMAND ${CMAKE_COMMAND} -E env
   ${COMMON_KCONFIG_ENV_SETTINGS}
-  SHIELD_AS_LIST=${SHIELD_AS_LIST_ESCAPED}
+  SHIELD_AS_LIST=${SHIELD_AS_LIST_ESCAPED_COMMAND}
   ${PYTHON_EXECUTABLE}
   ${ZEPHYR_BASE}/scripts/kconfig/kconfig.py
   --zephyr-base=${ZEPHYR_BASE}

cmake/toolchain/zephyr/0.11/Kconfig

@@ -1,8 +0,0 @@
-# Zephyr 0.11 SDK Toolchain
-
-# Copyright (c) 2020 Linaro Limited.
-# SPDX-License-Identifier: Apache-2.0
-
-config TOOLCHAIN_ZEPHYR_0_11
-	def_bool y
-	select HAS_NEWLIB_LIBC_NANO if (ARC || ARM || RISCV)

cmake/toolchain/zephyr/0.11/generic.cmake

@@ -1,34 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-set(TOOLCHAIN_HOME ${ZEPHYR_SDK_INSTALL_DIR})
-
-set(COMPILER gcc)
-set(LINKER ld)
-set(BINTOOLS gnu)
-
-# Find some toolchain that is distributed with this particular SDK
-
-file(GLOB toolchain_paths
-  LIST_DIRECTORIES true
-  ${TOOLCHAIN_HOME}/xtensa/*/*-zephyr-elf
-  ${TOOLCHAIN_HOME}/*-zephyr-elf
-  ${TOOLCHAIN_HOME}/*-zephyr-eabi
-  )
-
-if(toolchain_paths)
-  list(GET toolchain_paths 0 some_toolchain_path)
-
-  get_filename_component(one_toolchain_root "${some_toolchain_path}" DIRECTORY)
-  get_filename_component(one_toolchain "${some_toolchain_path}" NAME)
-
-  set(CROSS_COMPILE_TARGET ${one_toolchain})
-  set(SYSROOT_TARGET	   ${one_toolchain})
-endif()
-
-if(NOT CROSS_COMPILE_TARGET)
-  message(FATAL_ERROR "Unable to find 'x86_64-zephyr-elf' or any other architecture in ${TOOLCHAIN_HOME}")
-endif()
-
-set(CROSS_COMPILE ${one_toolchain_root}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
-set(SYSROOT_DIR   ${one_toolchain_root}/${SYSROOT_TARGET}/${SYSROOT_TARGET})
-set(TOOLCHAIN_HAS_NEWLIB ON CACHE BOOL "True if toolchain supports newlib")

cmake/toolchain/zephyr/0.11/host-tools.cmake

@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-set(HOST_TOOLS_HOME ${ZEPHYR_SDK_INSTALL_DIR}/sysroots/${TOOLCHAIN_ARCH}-pokysdk-linux)
-
-# Path used for searching by the find_*() functions, with appropriate
-# suffixes added. Ensures that the SDK's host tools will be found when
-# we call, e.g. find_program(QEMU qemu-system-x86)
-list(APPEND CMAKE_PREFIX_PATH ${HOST_TOOLS_HOME}/usr)
-
-# TODO: Use find_* somehow for these as well?
-set_ifndef(QEMU_BIOS            ${HOST_TOOLS_HOME}/usr/share/qemu)
-set_ifndef(OPENOCD_DEFAULT_PATH ${HOST_TOOLS_HOME}/usr/share/openocd/scripts)

cmake/toolchain/zephyr/0.11/target.cmake

@@ -1,53 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-set(CROSS_COMPILE_TARGET_arm        arm-zephyr-eabi)
-set(CROSS_COMPILE_TARGET_arm64   aarch64-zephyr-elf)
-set(CROSS_COMPILE_TARGET_nios2     nios2-zephyr-elf)
-set(CROSS_COMPILE_TARGET_riscv   riscv64-zephyr-elf)
-set(CROSS_COMPILE_TARGET_mips     mipsel-zephyr-elf)
-set(CROSS_COMPILE_TARGET_xtensa   xtensa-zephyr-elf)
-set(CROSS_COMPILE_TARGET_arc         arc-zephyr-elf)
-set(CROSS_COMPILE_TARGET_x86      x86_64-zephyr-elf)
-set(CROSS_COMPILE_TARGET_sparc     sparc-zephyr-elf)
-
-set(CROSS_COMPILE_TARGET ${CROSS_COMPILE_TARGET_${ARCH}})
-set(SYSROOT_TARGET       ${CROSS_COMPILE_TARGET})
-
-if("${ARCH}" STREQUAL "xtensa")
-  # Xtensa GCC needs a different toolchain per SOC
-  if("${SOC_SERIES}" STREQUAL "cavs_v15")
-    set(SR_XT_TC_SOC intel_apl_adsp)
-  elseif("${SOC_SERIES}" STREQUAL "cavs_v18")
-    set(SR_XT_TC_SOC intel_s1000)
-  elseif("${SOC_SERIES}" STREQUAL "cavs_v20")
-    set(SR_XT_TC_SOC intel_s1000)
-  elseif("${SOC_SERIES}" STREQUAL "cavs_v25")
-    set(SR_XT_TC_SOC intel_s1000)
-  elseif("${SOC_SERIES}" STREQUAL "baytrail_adsp")
-    set(SR_XT_TC_SOC intel_byt_adsp)
-  elseif("${SOC_SERIES}" STREQUAL "broadwell_adsp")
-    set(SR_XT_TC_SOC intel_bdw_adsp)
-  elseif("${SOC_SERIES}" STREQUAL "imx8")
-    set(SR_XT_TC_SOC nxp_imx_adsp)
-  elseif("${SOC_SERIES}" STREQUAL "imx8m")
-    set(SR_XT_TC_SOC nxp_imx8m_adsp)
-  else()
-    message(FATAL_ERROR "Not compiler set for SOC_SERIES ${SOC_SERIES}")
- endif()
- set(SYSROOT_DIR ${TOOLCHAIN_HOME}/xtensa/${SR_XT_TC_SOC}/${SYSROOT_TARGET})
- set(CROSS_COMPILE ${TOOLCHAIN_HOME}/xtensa/${SR_XT_TC_SOC}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
-else()
-  # Non-Xtensa SDK toolchains follow a simpler convention
-  set(SYSROOT_DIR   ${TOOLCHAIN_HOME}/${SYSROOT_TARGET}/${SYSROOT_TARGET})
-  set(CROSS_COMPILE ${TOOLCHAIN_HOME}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
-endif()
-
-if("${ARCH}" STREQUAL "x86")
-  if(CONFIG_X86_64)
-    list(APPEND TOOLCHAIN_C_FLAGS -m64)
-    list(APPEND TOOLCHAIN_LD_FLAGS -m64)
-  else()
-    list(APPEND TOOLCHAIN_C_FLAGS -m32)
-    list(APPEND TOOLCHAIN_LD_FLAGS -m32)
-  endif()
-endif()

cmake/toolchain/zephyr/generic.cmake

@@ -1,13 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
-if(${SDK_VERSION} VERSION_LESS_EQUAL 0.11.2)
-  # For backward compatibility with 0.11.1 and 0.11.2
-  # we need to source files from Zephyr repo
-  include(${CMAKE_CURRENT_LIST_DIR}/${SDK_MAJOR_MINOR}/generic.cmake)
+include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/generic.cmake)
 
-  set(TOOLCHAIN_KCONFIG_DIR ${CMAKE_CURRENT_LIST_DIR}/${SDK_MAJOR_MINOR})
-else()
-  include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/generic.cmake)
+set(TOOLCHAIN_KCONFIG_DIR ${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr)
 
-  set(TOOLCHAIN_KCONFIG_DIR ${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr)
-endif()
+message(STATUS "Found toolchain: zephyr ${SDK_VERSION} (${ZEPHYR_SDK_INSTALL_DIR})")

cmake/toolchain/zephyr/host-tools.cmake

@@ -1,55 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-# This is the minimum required version for Zephyr to work (Old style)
-set(REQUIRED_SDK_VER 0.11.1)
-cmake_host_system_information(RESULT TOOLCHAIN_ARCH QUERY OS_PLATFORM)
+include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/host-tools.cmake)
 
-if(NOT DEFINED ZEPHYR_SDK_INSTALL_DIR)
-  # Until https://github.com/zephyrproject-rtos/zephyr/issues/4912 is
-  # resolved we use ZEPHYR_SDK_INSTALL_DIR to determine whether the user
-  # wants to use the Zephyr SDK or not.
-  return()
-endif()
-
-# Cache the Zephyr SDK install dir.
-set(ZEPHYR_SDK_INSTALL_DIR ${ZEPHYR_SDK_INSTALL_DIR} CACHE PATH "Zephyr SDK install directory")
-
-if(NOT DEFINED SDK_VERSION)
-  if(ZEPHYR_TOOLCHAIN_VARIANT AND ZEPHYR_SDK_INSTALL_DIR)
-    # Manual detection for Zephyr SDK 0.11.1 and 0.11.2 for backward compatibility.
-    set(sdk_version_path ${ZEPHYR_SDK_INSTALL_DIR}/sdk_version)
-    if(NOT (EXISTS ${sdk_version_path}))
-      message(FATAL_ERROR
-              "The file '${ZEPHYR_SDK_INSTALL_DIR}/sdk_version' was not found. \
-               Is ZEPHYR_SDK_INSTALL_DIR=${ZEPHYR_SDK_INSTALL_DIR} misconfigured?")
-    endif()
-
-    # Read version as published by the SDK
-    file(READ ${sdk_version_path} SDK_VERSION_PRE1)
-    # Remove any pre-release data, for example 0.10.0-beta4 -> 0.10.0
-    string(REGEX REPLACE "-.*" "" SDK_VERSION_PRE2 ${SDK_VERSION_PRE1})
-    # Strip any trailing spaces/newlines from the version string
-    string(STRIP ${SDK_VERSION_PRE2} SDK_VERSION)
-    string(REGEX MATCH "([0-9]*).([0-9]*)" SDK_MAJOR_MINOR ${SDK_VERSION})
-
-    string(REGEX MATCH "([0-9]+)\.([0-9]+)\.([0-9]+)" SDK_MAJOR_MINOR_MICRO ${SDK_VERSION})
-
-    #at least 0.0.0
-    if(NOT SDK_MAJOR_MINOR_MICRO)
-      message(FATAL_ERROR "sdk version: ${SDK_MAJOR_MINOR_MICRO} improper format.
-      Expected format: x.y.z
-      Check whether the Zephyr SDK was installed correctly.
-    ")
-    endif()
-  endif()
-endif()
-
-message(STATUS "Using toolchain: zephyr ${SDK_VERSION} (${ZEPHYR_SDK_INSTALL_DIR})")
-
-if(${SDK_VERSION} VERSION_LESS_EQUAL 0.11.2)
-  # For backward compatibility with 0.11.1 and 0.11.2
-  # we need to source files from Zephyr repo
-  include(${CMAKE_CURRENT_LIST_DIR}/${SDK_MAJOR_MINOR}/host-tools.cmake)
-else()
-  include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/host-tools.cmake)
-endif()
+message(STATUS "Found host-tools: zephyr ${SDK_VERSION} (${ZEPHYR_SDK_INSTALL_DIR})")

cmake/toolchain/zephyr/target.cmake

@@ -1,18 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-if(${SDK_VERSION} VERSION_LESS_EQUAL 0.11.2)
-  # For backward compatibility with 0.11.1 and 0.11.2
-  # we need to source files from Zephyr repo
-  include(${CMAKE_CURRENT_LIST_DIR}/${SDK_MAJOR_MINOR}/target.cmake)
-elseif(("${ARCH}" STREQUAL "sparc") AND (${SDK_VERSION} VERSION_LESS 0.12))
-  # SDK 0.11.3, 0.11.4 does not have SPARC target support.
-  include(${CMAKE_CURRENT_LIST_DIR}/${SDK_MAJOR_MINOR}/target.cmake)
-else()
-  include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/target.cmake)
-
-  # Workaround, FIXME: Waiting for new SDK.
-  if("${ARCH}" STREQUAL "xtensa")
-    set(SYSROOT_DIR ${TOOLCHAIN_HOME}/xtensa/${SOC_TOOLCHAIN_NAME}/${SYSROOT_TARGET})
-    set(CROSS_COMPILE ${TOOLCHAIN_HOME}/xtensa/${SOC_TOOLCHAIN_NAME}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
-  endif()
-endif()
+include(${ZEPHYR_SDK_INSTALL_DIR}/cmake/zephyr/target.cmake)

cmake/verify-toolchain.cmake

@@ -90,10 +90,6 @@ if(NOT DEFINED ZEPHYR_TOOLCHAIN_VARIANT)
   if (NOT Zephyr-sdk_CONSIDERED_VERSIONS)
     set(error_msg "ZEPHYR_TOOLCHAIN_VARIANT not specified and no Zephyr SDK is installed.\n")
     string(APPEND error_msg "Please set ZEPHYR_TOOLCHAIN_VARIANT to the toolchain to use or install the Zephyr SDK.")
-
-    if(NOT ZEPHYR_TOOLCHAIN_VARIANT AND NOT ZEPHYR_SDK_INSTALL_DIR)
-      set(error_note "Note: If you are using Zephyr SDK 0.11.1 or 0.11.2, remember to set ZEPHYR_SDK_INSTALL_DIR and ZEPHYR_TOOLCHAIN_VARIANT")
-    endif()
   else()
     #  Note: When CMake mimimun version becomes >= 3.17, change this loop into:
     #    foreach(version config IN ZIP_LISTS Zephyr-sdk_CONSIDERED_VERSIONS Zephyr-sdk_CONSIDERED_CONFIGS)
@@ -116,11 +112,17 @@ if(NOT DEFINED ZEPHYR_TOOLCHAIN_VARIANT)
   message(FATAL_ERROR "${error_msg}
 The Zephyr SDK can be downloaded from:
 https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v${TOOLCHAIN_ZEPHYR_MINIMUM_REQUIRED_VERSION}/zephyr-sdk-${TOOLCHAIN_ZEPHYR_MINIMUM_REQUIRED_VERSION}-setup.run
-${error_note}
 ")
 
 endif()
 
+if(DEFINED ZEPHYR_SDK_INSTALL_DIR)
+  # Cache the Zephyr SDK install dir.
+  set(ZEPHYR_SDK_INSTALL_DIR ${ZEPHYR_SDK_INSTALL_DIR} CACHE PATH "Zephyr SDK install directory")
+  # Use the Zephyr SDK host-tools.
+  set(ZEPHYR_SDK_HOST_TOOLS TRUE)
+endif()
+
 if(CMAKE_SCRIPT_MODE_FILE)
   if("${FORMAT}" STREQUAL "json")
     set(json "{\"ZEPHYR_TOOLCHAIN_VARIANT\" : \"${ZEPHYR_TOOLCHAIN_VARIANT}\", ")

doc/_extensions/zephyr/doxyrunner.py

@@ -31,6 +31,9 @@ Configuration options
 - ``doxyrunner_doxyfile``: Path to Doxyfile.
 - ``doxyrunner_outdir``: Doxygen build output directory (inserted to
   ``OUTPUT_DIRECTORY``)
+- ``doxyrunner_outdir_var``: Variable representing the Doxygen build output
+  directory, as used by ``OUTPUT_DIRECTORY``. This can be useful if other
+  Doxygen variables reference to the output directory.
 - ``doxyrunner_fmt``: Flag to indicate if Doxyfile should be formatted.
 - ``doxyrunner_fmt_vars``: Format variables dictionary (name: value).
 - ``doxyrunner_fmt_pattern``: Format pattern.
@@ -132,6 +135,7 @@ def process_doxyfile(
     fmt: bool = False,
     fmt_pattern: Optional[str] = None,
     fmt_vars: Optional[Dict[str, str]] = None,
+    outdir_var: Optional[str] = None,
 ) -> str:
     """Process Doxyfile.
 
@@ -146,6 +150,7 @@ def process_doxyfile(
         fmt: If Doxyfile should be formatted.
         fmt_pattern: Format pattern.
         fmt_vars: Format variables.
+        outdir_var: Variable representing output directory.
 
      Returns:
         Processed Doxyfile content.
@@ -179,6 +184,10 @@ def process_doxyfile(
         if not fmt_pattern or not fmt_vars:
             raise ValueError("Invalid formatting pattern or variables")
 
+        if outdir_var:
+            fmt_vars = fmt_vars.copy()
+            fmt_vars[outdir_var] = outdir.as_posix()
+
         for var, value in fmt_vars.items():
             content = content.replace(fmt_pattern.format(var), value)
 
@@ -349,6 +358,7 @@ def doxygen_build(app: Sphinx) -> None:
         app.config.doxyrunner_fmt,
         app.config.doxyrunner_fmt_pattern,
         app.config.doxyrunner_fmt_vars,
+        app.config.doxyrunner_outdir_var,
     )
 
     logger.info("Checking if Doxygen needs to be run...")
@@ -374,6 +384,7 @@ def setup(app: Sphinx) -> Dict[str, Any]:
     app.add_config_value("doxyrunner_doxygen", "doxygen", "env")
     app.add_config_value("doxyrunner_doxyfile", None, "env")
     app.add_config_value("doxyrunner_outdir", None, "env")
+    app.add_config_value("doxyrunner_outdir_var", None, "env")
     app.add_config_value("doxyrunner_fmt", False, "env")
     app.add_config_value("doxyrunner_fmt_vars", {}, "env")
     app.add_config_value("doxyrunner_fmt_pattern", "@{}@", "env")

doc/_static/css/custom.css

@@ -124,64 +124,27 @@ hr,
     border-color: var(--admonition-attention-title-background-color) !important;
     color: var(--admonition-attention-color) !important;
 }
-.rst-content dl:not(.docutils).class dt,
-.rst-content dl:not(.docutils).function dt,
-.rst-content dl:not(.docutils).method dt,
-.rst-content dl:not(.docutils).attribute dt {
-    width: 100% !important;
-}
-.rst-content dl:not(.docutils).class > dt,
-.rst-content dl:not(.docutils).function > dt,
-.rst-content dl:not(.docutils).method > dt,
-.rst-content dl:not(.docutils).attribute > dt {
-    font-size: 100% !important;
-    font-weight: normal !important;
-    margin-bottom: 16px !important;
-    padding: 6px 8px !important;
-}
-.rst-content dl:not(.docutils) tt.descclassname,
-.rst-content dl:not(.docutils) code.descclassname {
-    color: var(--highlight-type2-color) !important;
-    font-weight: normal !important;
-}
-.rst-content dl:not(.docutils) tt.descname,
-.rst-content dl:not(.docutils) code.descname {
-    color: var(--highlight-function-color) !important;
-    font-weight: normal !important;
-}
-.rst-content dl:not(.docutils) .sig-paren,
-.rst-content dl:not(.docutils) .optional {
-    color: var(--highlight-operator-color) !important;
-    font-weight: normal !important;
-    padding: 0 2px !important;
-}
-.rst-content dl:not(.docutils) .optional {
-    font-style: italic !important;
-}
-.rst-content dl:not(.docutils) .sig-param,
-.rst-content dl:not(.docutils).class dt > em,
-.rst-content dl:not(.docutils).function dt > em,
-.rst-content dl:not(.docutils).method dt > em {
-    color: var(--code-literal-color) !important;
+
+.rst-content dt.sig .k {
+    color: var(--highlight-keyword2-color) !important;
     font-style: normal !important;
-    padding: 0 4px !important;
 }
-.rst-content dl:not(.docutils) .sig-param,
-.rst-content dl:not(.docutils).class dt > code,
-.rst-content dl:not(.docutils).function dt > code,
-.rst-content dl:not(.docutils).method dt > code {
-    padding: 0 4px !important;
-}
-.rst-content dl:not(.docutils) .sig-param,
-.rst-content dl:not(.docutils).class dt > .optional ~ em,
-.rst-content dl:not(.docutils).function dt > .optional ~ em,
-.rst-content dl:not(.docutils).method dt > .optional ~ em {
-    color: var(--highlight-number-color) !important;
-    font-style: italic !important;
-}
-.rst-content dl:not(.docutils).class dt > em.property {
+
+.rst-content dt.sig .kt {
     color: var(--highlight-keyword-color) !important;
+    font-style: normal !important;
 }
+
+.rst-content dt.sig .sig-name .n {
+    color: var(--highlight-function-color) !important;
+}
+
+.rst-content dt.sig .k,
+.rst-content dt.sig .kt,
+.rst-content dt.sig .n {
+    font-weight: normal !important;
+}
+
 .rst-content dl:not(.docutils) dt a.headerlink {
     color: var(--link-color) !important;
 }
@@ -878,16 +841,8 @@ kbd, .kbd {
 
 /* Breathe tweaks */
 
-.rst-content dl.group>dt, .rst-content dl.group>dd>p {
-    display:none !important;
-}
-
-.rst-content dl.group {
-    margin: 0 0 1rem 0;
-}
-
-.rst-content dl.group>dd {
-    margin-left: 0 !important;
+.rst-content .section > dl > dd {
+    margin-left: 0;
 }
 
 .rst-content p.breathe-sectiondef-title {
@@ -895,24 +850,12 @@ kbd, .kbd {
     color: var(--link-color);
 }
 
-.rst-content div.breathe-sectiondef {
-    padding-left: 0 !important;
-}
-
 .rst-content dl:not(.docutils) dl:not(.rst-other-versions) dt {
     background: var(--admonition-note-background-color) !important;
     border-top: none !important;
     border-left: none !important;
 }
 
-.rst-content dl:not(.docutils).c.var .pre {
-  padding-right: 4px;
-}
-
-.rst-content dl:not(.docutils).c.struct .property {
-  padding-right: 4px !important;
-}
-
 /* Misc tweaks */
 
 .rst-columns {

doc/conf.py

@@ -180,6 +180,7 @@ doxyrunner_doxyfile = ZEPHYR_BASE / "doc" / "zephyr.doxyfile.in"
 doxyrunner_outdir = ZEPHYR_BUILD / "doxygen"
 doxyrunner_fmt = True
 doxyrunner_fmt_vars = {"ZEPHYR_BASE": str(ZEPHYR_BASE)}
+doxyrunner_outdir_var = "DOXY_OUT"
 
 # -- Options for Breathe plugin -------------------------------------------
 
@@ -203,6 +204,7 @@ cpp_id_attributes = [
     "__DEPRECATED_MACRO",
     "FUNC_NORETURN",
     "__subsystem",
+    "ALWAYS_INLINE",
 ]
 c_id_attributes = cpp_id_attributes
 

doc/guides/device_mgmt/mcumgr.rst

@@ -209,6 +209,20 @@ on Zephyr. The ones that are supported are described in the following table:
     :kconfig:`CONFIG_THREAD_STACK_INFO` and :kconfig:`CONFIG_INIT_STACKS` options
     must be set.
 
+.. _mcumgr_jlink_ob_virtual_msd:
+
+J-Link Virtual MSD Interaction Note
+***********************************
+
+On boards where a J-Link OB is present which has both CDC and MSC (virtual Mass
+Storage Device, also known as drag-and-drop) support, the MSD functionality can
+prevent mcumgr commands over the CDC UART port from working due to how USB
+endpoints are configured in the J-Link firmware (for example on the Nordic
+``nrf52840dk``) because of limiting the maximum packet size (most likely to occur
+when using image management commands for updating firmware). This issue can be
+resolved by disabling MSD functionality on the J-Link device, follow the
+instructions on :ref:`nordic_segger_msd` to disable MSD support.
+
 .. _image_mgmt:
 
 Image Management

doc/guides/docs/index.rst

@@ -261,7 +261,21 @@ or invoke make with the following target::
    # To generate HTML output without detailed Kconfig
    make html-fast
 
+Linking external Doxygen projects against Zephyr
+************************************************
+
+External projects that build upon Zephyr functionality and wish to refer to
+Zephyr documentation in Doxygen (through the use of @ref), can utilize the
+tag file exported at `zephyr.tag </doxygen/html/zephyr.tag>`_
+
+Once downloaded, the tag file can be used in a custom ``doxyfile.in`` as follows::
+
+   TAGFILES = "/path/to/zephyr.tag=https://docs.zephyrproject.org/latest/doxygen/html/"
+
+For additional information refer to `Doxygen External Documentation`_.
+
 
 .. _reStructuredText: http://sphinx-doc.org/rest.html
 .. _Sphinx: http://sphinx-doc.org/
 .. _Windows Python Path: https://docs.python.org/3/using/windows.html#finding-the-python-executable
+.. _Doxygen External Documentation: https://www.doxygen.nl/manual/external.html

doc/reference/kernel/smp/smp.rst

@@ -297,3 +297,8 @@ Note that while SMP requires :kconfig:`CONFIG_USE_SWITCH`, the reverse is not
 true.  A uniprocessor architecture built with :kconfig:`CONFIG_SMP` set to No might
 still decide to implement its context switching using
 :c:func:`arch_switch`.
+
+API Reference
+**************
+
+.. doxygengroup:: spinlock_apis

doc/reference/networking/can_api.rst

@@ -177,12 +177,12 @@ occurred. It does not block until the message is sent like the example above.
 
 .. code-block:: C
 
-  void tx_irq_callback(uint32_t error_flags, void *arg)
+  void tx_irq_callback(int error, void *arg)
   {
           char *sender = (char *)arg;
 
-          if (error_flags) {
-                  LOG_ERR("Sendig failed [%d]\nSender: %s\n", error_flags, sender);
+          if (error != 0) {
+                  LOG_ERR("Sendig failed [%d]\nSender: %s\n", error, sender);
           }
   }
 

doc/releases/release-notes-2.7.rst

@@ -2,24 +2,186 @@
 
 .. _zephyr_2.7:
 
-.. _zephyr_2.7.1:
+.. _zephyr_2.7.3:
 
-Zephyr 2.7.1
+Zephyr 2.7.3
 ####################
 
 This is an LTS maintenance release with fixes.
 
+Issues Fixed
+************
+
+These GitHub issues were addressed since the previous 2.7.2 tagged
+release:
+
+.. comment  List derived from GitHub Issue query: ...
+   * :github:`issuenumber` - issue title
+
+* :github:`39882` - Bluetooth Host qualification on 2.7 branch
+* :github:`41074` - can_mcan_send sends corrupted CAN frames with a byte-by-byte memcpy implementation
+* :github:`43479` - Bluetooth: Controller: Fix per adv scheduling issue
+* :github:`43694` - drivers: spi: stm32 spi with dma must enable cs after periph
+* :github:`44089` - logging: shell backend: null-deref when logs are dropped
+* :github:`45341` - Add new EHL SKUs for IBECC
+* :github:`45529` - GdbStub get_mem_region bugfix
+* :github:`46621` - drivers: i2c: Infinite recursion in driver unregister function
+* :github:`46698` - sm351 driver faults when using global thread
+* :github:`46706` - add missing checks for segment number
+* :github:`46757` - Bluetooth: Controller: Missing validation of unsupported PHY when performing PHY update
+* :github:`46807` - lib: posix: semaphore: use consistent timebase in sem_timedwait
+* :github:`46822` - L2CAP disconnected packet timing in ecred reconf function
+* :github:`46994` - Incorrect Xtensa toolchain path resolution
+* :github:`47356` - cpp: global static object initialisation may fail for MMU and MPU platforms
+* :github:`47609` - posix: pthread: descriptor leak with pthread_join
+* :github:`47955` - drivers: can: various RTR fixes
+* :github:`48249` - boards: nucleo_wb55rg: documentation BLE binary compatibility issue
+* :github:`48271` - net: Possible net_pkt leak in ipv6 multicast forwarding
+
 Security Vulnerability Related
 ******************************
 
 The following security vulnerabilities (CVEs) were addressed in this
 release:
 
-* (N/A)
+* CVE-2022-2741: Under embargo until 2022-10-14
+
+* CVE-2022-1042: `Zephyr project bug tracker GHSA-j7v7-w73r-mm5x
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-j7v7-w73r-mm5x>`_
+
+* CVE-2022-1041: `Zephyr project bug tracker GHSA-p449-9hv9-pj38
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-p449-9hv9-pj38>`_
+
+* CVE-2021-3966: `Zephyr project bug tracker GHSA-hfxq-3w6x-fv2m
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-hfxq-3w6x-fv2m>`_
 
 More detailed information can be found in:
 https://docs.zephyrproject.org/latest/security/vulnerabilities.html
 
+.. _zephyr_2.7.2:
+
+Zephyr 2.7.2
+####################
+
+This is an LTS maintenance release with fixes.
+
+Issues Fixed
+************
+
+These GitHub issues were addressed since the previous 2.7.1 tagged
+release:
+
+.. comment  List derived from GitHub Issue query: ...
+   * :github:`issuenumber` - issue title
+
+* :github:`23419` - posix: clock: No thread safety clock_getime / clock_settime
+* :github:`30367` - TCP2 does not send our MSS to peer
+* :github:`37389` - nucleo_g0b1re: Swapping image in mcuboot results in hard fault and softbricks the device
+* :github:`38268` - Multiple defects in "Multi Producer Single Consumer Packet Buffer" library
+* :github:`38576` - net shell: self-connecting to TCP might lead to a crash
+* :github:`39184` - HawkBit hash mismatch
+* :github:`39242` - net: sockets: Zephyr Fatal in dns_resolve_cb if dns request was attempted in offline state
+* :github:`39399` - linker: Missing align __itcm_load_start / __dtcm_data_load_start linker symbols
+* :github:`39608` - stm32: lpuart: 9600 baudrate doesn't work
+* :github:`39609` - spi: slave: division by zero in timeout calculation
+* :github:`39660` - poll() not notified when a TLS/TCP connection is closed without TLS close_notify
+* :github:`39687` - sensor: qdec_nrfx: PM callback has incorrect signature
+* :github:`39774` - modem: uart mux reading optimization never used
+* :github:`39882` - Bluetooth Host qualification on 2.7 branch
+* :github:`40163` - Use correct clock frequency for systick+DWT
+* :github:`40464` - Dereferencing NULL with getsockname() on TI Simplelink Platform
+* :github:`40578` - MODBUS RS-485 transceiver support broken on several platforms due to DE race condition
+* :github:`40614` - poll: the code judgment condition is always true
+* :github:`40640` - drivers: usb_dc_native_posix: segfault when using composite USB device
+* :github:`40730` - More power supply modes on STM32H7XX
+* :github:`40775` - stm32: multi-threading broken after #40173
+* :github:`40795` - Timer signal thread execution loop break SMP on ARM64
+* :github:`40925` - mesh_badge not working reel_board_v2
+* :github:`40985` - net: icmpv6: Add support for Route Info option in Router Advertisement
+* :github:`41026` - LoRa: sx126x: DIO1 interrupt left enabled in sleep mode
+* :github:`41077` - console: gsm_mux: could not send more than 128 bytes of data on dlci
+* :github:`41089` - power modes for STM32H7
+* :github:`41095` - libc: newlib: 'gettimeofday' causes stack overflow on non-POSIX builds
+* :github:`41237` - drivers: ieee802154_dw1000: use dedicated workqueue
+* :github:`41240` - logging can get messed up when messages are dropped
+* :github:`41284` - pthread_cond_wait return value incorrect
+* :github:`41339` - stm32, Unable to read UART while checking from Framing error.
+* :github:`41488` - Stall logging on nrf52840
+* :github:`41499` - drivers: iwdg: stm32: WDT_OPT_PAUSE_HALTED_BY_DBG might not work
+* :github:`41503` - including net/socket.h fails with redefinition of struct zsock_timeval (sometimes :-) )
+* :github:`41529` - documentation: generate Doxygen tag file
+* :github:`41536` - Backport STM32 SMPS Support to v2.7.0
+* :github:`41582` - stm32h7: CSI as PLL source is broken
+* :github:`41683` - http_client: Unreliable rsp->body_start pointer
+* :github:`41915` - regression: Build fails after switching logging to V2
+* :github:`41942` - k_delayable_work being used as k_work in work's handler
+* :github:`41952` - Log timestamp overflows when using LOGv2
+* :github:`42164` - tests/bluetooth/tester broken after switch to logging v2
+* :github:`42271` - drivers: can: m_can: The can_set_bitrate() function doesn't work.
+* :github:`42299` - spi: nRF HAL driver asserts when PM is used
+* :github:`42373` - add k_spin_lock() to doxygen prior to v3.0 release
+* :github:`42581` - include: drivers: clock_control: stm32 incorrect DT_PROP is used for xtpre
+* :github:`42615` - Bluetooth: Controller: Missing ticks slot offset calculation in Periodic Advertising event scheduling
+* :github:`42622` - pm: pm_device structure bigger than nessecary when PM_DEVICE_RUNTIME not set
+* :github:`42631` - Unable to identify owner of net_mgmt_lock easily
+* :github:`42825` - MQTT client disconnection (EAGAIN) on publish with big payload
+* :github:`42862` - Bluetooth: L2CAP: Security check on l2cap request is wrong
+* :github:`43117` - Not possible to create more than one shield.
+* :github:`43130` - STM32WL ADC idles / doesn't work
+* :github:`43176` - net/icmpv4: client possible to ddos itself when there's an error for the broadcasted packet
+* :github:`43177` - net: shell: errno not cleared before calling the strtol
+* :github:`43178` - net: ip: route: log_strdup misuse
+* :github:`43179` - net: tcp: forever loop in tcp_resend_data
+* :github:`43180` - net: tcp: possible deadlock in tcp_conn_unref()
+* :github:`43181` - net: sockets: net_pkt leak in accept
+* :github:`43182` - net: arp: ARP retransmission source address selection
+* :github:`43183` - net: mqtt: setsockopt leak on failure
+* :github:`43184` - arm: Wrong macro used for z_interrupt_stacks declaration in stack.h
+* :github:`43185` - arm: cortex-m: uninitialised ptr_esf in get_esf() in fault.c
+* :github:`43470` - wifi: esp_at: race condition on mutex's leading to deadlock
+* :github:`43490` - net: sockets: userspace accept() crashes with NULL addr/addrlen pointer
+* :github:`43548` - gen_relocate_app truncates files on incremental builds
+* :github:`43572` - stm32: wrong clock the LSI freq for stm32l0x mcus
+* :github:`43580` - hl7800: tcp stack freezes on slow response from modem
+* :github:`43807` - Test "cpp.libcxx.newlib.exception" failed on platforms which use zephyr.bin to run tests.
+* :github:`43839` - Bluetooth: controller: missing NULL assign to df_cfg in ll_adv_set
+* :github:`43853` - X86 MSI messages always get to BSP core (need a fix to be backported)
+* :github:`43858` - mcumgr seems to lock up when it receives command for group that does not exist
+* :github:`44107` - The SMP nsim boards are started incorrectly when launching on real HW
+* :github:`44310` - net: gptp: type mismatch calculation error in gptp_mi
+* :github:`44336` - nucleo_wb55rg: stm32cubeprogrammer runner is missing for twister tests
+* :github:`44337` - twister: Miss sn option to stm32cubeprogrgammer runner
+* :github:`44352` - stm32l5x boards missing the openocd runner
+* :github:`44497` - Add guide for disabling MSD on JLink OB devices and link to from smp_svr page
+* :github:`44531` - bl654_usb without mcuboot maximum image size is not limited
+* :github:`44886` - Unable to boot Zephyr on FVP_BaseR_AEMv8R
+* :github:`44902` - x86: FPU registers are not initialised for userspace (eager FPU sharing)
+* :github:`45869` - doc: update requirements
+* :github:`45870` - drivers: virt_ivshmem: Allow multiple instances of ivShMem devices
+* :github:`45871` - ci: split Bluetooth workflow
+* :github:`45872` - ci: make git credentials non-persistent
+* :github:`45873` - soc: esp32: use PYTHON_EXECUTABLE from build system
+
+Security Vulnerability Related
+******************************
+
+The following security vulnerabilities (CVEs) were addressed in this
+release:
+
+* CVE-2021-3966: `Zephyr project bug tracker GHSA-hfxq-3w6x-fv2m
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-hfxq-3w6x-fv2m>`_
+
+More detailed information can be found in:
+https://docs.zephyrproject.org/latest/security/vulnerabilities.html
+
+
+.. _zephyr_2.7.1:
+
+Zephyr 2.7.1
+####################
+
+This is an LTS maintenance release with fixes.
+
 Issues Fixed
 ************
 
@@ -55,6 +217,19 @@ release:
 * :github:`40844` - gen_app_partitions scans object files unrelated to current image
 * :github:`41237` - drivers: ieee802154_dw1000: use dedicated workqueue
 
+Security Vulnerability Related
+******************************
+
+The following security vulnerabilities (CVEs) were addressed in this
+release:
+
+* CVE-2021-3966: `Zephyr project bug tracker GHSA-hfxq-3w6x-fv2m
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-hfxq-3w6x-fv2m>`_
+
+More detailed information can be found in:
+https://docs.zephyrproject.org/latest/security/vulnerabilities.html
+
+
 .. _zephyr_2.7.0:
 
 Zephyr 2.7.0

doc/zephyr.doxyfile.in

@@ -2064,7 +2064,7 @@ TAGFILES               =
 # tag file that is based on the input files it reads. See section "Linking to
 # external documentation" for more information about the usage of tag files.
 
-GENERATE_TAGFILE       =
+GENERATE_TAGFILE       = @DOXY_OUT@/html/zephyr.tag
 
 # If the ALLEXTERNALS tag is set to YES, all external class will be listed in
 # the class index. If set to NO, only the inherited external classes will be

drivers/adc/adc_stm32.c

@@ -319,6 +319,49 @@ static void adc_stm32_calib(const struct device *dev)
 }
 #endif
 
+/*
+ * Enable ADC peripheral, and wait until ready if required by SOC.
+ */
+static int adc_stm32_enable(ADC_TypeDef *adc)
+{
+#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
+	defined(CONFIG_SOC_SERIES_STM32L5X) || \
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G0X) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X) || \
+	defined(CONFIG_SOC_SERIES_STM32WLX)
+
+	if (LL_ADC_IsEnabled(adc) == 1UL) {
+		return 0;
+	}
+
+	LL_ADC_ClearFlag_ADRDY(adc);
+	LL_ADC_Enable(adc);
+
+	/*
+	 * Enabling ADC modules in L4, WB, G0 and G4 series may fail if they are
+	 * still not stabilized, this will wait for a short time to ensure ADC
+	 * modules are properly enabled.
+	 */
+	uint32_t count_timeout = 0;
+
+	while (LL_ADC_IsActiveFlag_ADRDY(adc) == 0) {
+		if (LL_ADC_IsEnabled(adc) == 0UL) {
+			LL_ADC_Enable(adc);
+			count_timeout++;
+			if (count_timeout == 10) {
+				return -ETIMEDOUT;
+			}
+		}
+	}
+#else
+	LL_ADC_Enable(adc);
+#endif
+
+	return 0;
+}
+
+
 static int start_read(const struct device *dev,
 		      const struct adc_sequence *sequence)
 {
@@ -409,9 +452,10 @@ static int start_read(const struct device *dev,
 		return err;
 	}
 
-#if defined(CONFIG_SOC_SERIES_STM32G0X)
+#if defined(CONFIG_SOC_SERIES_STM32G0X) || \
+	defined(CONFIG_SOC_SERIES_STM32WLX)
 	/*
-	 * Errata: Writing ADC_CFGR1 register while ADEN bit is set
+	 * Writing ADC_CFGR1 register while ADEN bit is set
 	 * resets RES[1:0] bitfield. We need to disable and enable adc.
 	 */
 	if (LL_ADC_IsEnabled(adc) == 1UL) {
@@ -420,15 +464,14 @@ static int start_read(const struct device *dev,
 	while (LL_ADC_IsEnabled(adc) == 1UL) {
 	}
 	LL_ADC_SetResolution(adc, resolution);
-	LL_ADC_Enable(adc);
-	while (LL_ADC_IsActiveFlag_ADRDY(adc) != 1UL) {
-	}
+	adc_stm32_enable(adc);
 #elif !defined(CONFIG_SOC_SERIES_STM32F1X) && \
 	!defined(STM32F3X_ADC_V2_5)
 	LL_ADC_SetResolution(adc, resolution);
 #endif
 
-#ifdef CONFIG_SOC_SERIES_STM32L0X
+#if defined(CONFIG_SOC_SERIES_STM32L0X) || \
+	defined(CONFIG_SOC_SERIES_STM32WLX)
 	/*
 	 * setting OVS bits is conditioned to ADC state: ADC must be disabled
 	 * or enabled without conversion on going : disable it, it will stop
@@ -524,11 +567,11 @@ static int start_read(const struct device *dev,
 		break;
 	default:
 		LOG_ERR("Invalid oversampling");
-		LL_ADC_Enable(adc);
+		adc_stm32_enable(adc);
 		return -EINVAL;
 	}
 	/* re-enable ADC after changing the OVS */
-	LL_ADC_Enable(adc);
+	adc_stm32_enable(adc);
 #else
 	if (sequence->oversampling) {
 		LOG_ERR("Oversampling not supported");
@@ -543,7 +586,14 @@ static int start_read(const struct device *dev,
 	!defined(CONFIG_SOC_SERIES_STM32F1X) && \
 	!defined(STM32F3X_ADC_V2_5) && \
 	!defined(CONFIG_SOC_SERIES_STM32L1X)
+
+		/* we cannot calibrate the ADC while the ADC is enabled */
+		LL_ADC_Disable(adc);
+		while (LL_ADC_IsEnabled(adc) == 1UL) {
+		}
 		adc_stm32_calib(dev);
+		/* re-enable ADC after calibration */
+		adc_stm32_enable(adc);
 #else
 		LOG_ERR("Calibration not supported");
 		return -ENOTSUP;
@@ -564,7 +614,7 @@ static int start_read(const struct device *dev,
 #elif defined(CONFIG_SOC_SERIES_STM32F1X)
 	LL_ADC_EnableIT_EOS(adc);
 #elif defined(STM32F3X_ADC_V2_5)
-	LL_ADC_Enable(adc);
+	adc_stm32_enable(adc);
 	LL_ADC_EnableIT_EOS(adc);
 #else
 	LL_ADC_EnableIT_EOCS(adc);
@@ -904,32 +954,10 @@ static int adc_stm32_init(const struct device *dev)
 	}
 #endif
 
-	LL_ADC_Enable(adc);
-
-#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
-	defined(CONFIG_SOC_SERIES_STM32L5X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX) || \
-	defined(CONFIG_SOC_SERIES_STM32G0X) || \
-	defined(CONFIG_SOC_SERIES_STM32G4X) || \
-	defined(CONFIG_SOC_SERIES_STM32H7X) || \
-	defined(CONFIG_SOC_SERIES_STM32WLX)
-	/*
-	 * Enabling ADC modules in L4, WB, G0 and G4 series may fail if they are
-	 * still not stabilized, this will wait for a short time to ensure ADC
-	 * modules are properly enabled.
-	 */
-	uint32_t countTimeout = 0;
-
-	while (LL_ADC_IsActiveFlag_ADRDY(adc) == 0) {
-		if (LL_ADC_IsEnabled(adc) == 0UL) {
-			LL_ADC_Enable(adc);
-			countTimeout++;
-			if (countTimeout == 10) {
-				return -ETIMEDOUT;
-			}
-		}
+	err = adc_stm32_enable(adc);
+	if (err < 0) {
+		return err;
 	}
-#endif
 
 	config->irq_cfg_func();
 

drivers/can/can_loopback.c

@@ -11,6 +11,9 @@
 #include "can_loopback.h"
 
 #include <logging/log.h>
+
+#include "can_utils.h"
+
 LOG_MODULE_DECLARE(can_driver, CONFIG_CAN_LOG_LEVEL);
 
 K_KERNEL_STACK_DEFINE(tx_thread_stack,
@@ -41,13 +44,6 @@ static void dispatch_frame(const struct zcan_frame *frame,
 	filter->rx_cb(&frame_tmp, filter->cb_arg);
 }
 
-static inline int check_filter_match(const struct zcan_frame *frame,
-				     const struct zcan_filter *filter)
-{
-	return ((filter->id & filter->id_mask) ==
-		(frame->id & filter->id_mask));
-}
-
 void tx_thread(void *data_arg, void *arg2, void *arg3)
 {
 	ARG_UNUSED(arg2);
@@ -63,7 +59,7 @@ void tx_thread(void *data_arg, void *arg2, void *arg3)
 		for (int i = 0; i < CONFIG_CAN_MAX_FILTER; i++) {
 			filter = &data->filters[i];
 			if (filter->rx_cb &&
-			    check_filter_match(&frame.frame, &filter->filter)) {
+			    can_utils_filter_match(&frame.frame, &filter->filter) != 0) {
 				dispatch_frame(&frame.frame, filter);
 			}
 		}

drivers/can/can_mcan.c

@@ -23,6 +23,34 @@ LOG_MODULE_DECLARE(can_driver, CONFIG_CAN_LOG_LEVEL);
 #define MCAN_MAX_DLC CAN_MAX_DLC
 #endif
 
+static void memcpy32_volatile(volatile void *dst_, const volatile void *src_,
+			      size_t len)
+{
+	volatile uint32_t *dst = dst_;
+	const volatile uint32_t *src = src_;
+
+	__ASSERT(len % 4 == 0, "len must be a multiple of 4!");
+	len /= sizeof(uint32_t);
+
+	while (len--) {
+		*dst = *src;
+		++dst;
+		++src;
+	}
+}
+
+static void memset32_volatile(volatile void *dst_, uint32_t val, size_t len)
+{
+	volatile uint32_t *dst = dst_;
+
+	__ASSERT(len % 4 == 0, "len must be a multiple of 4!");
+	len /= sizeof(uint32_t);
+
+	while (len--) {
+		*dst++ = val;
+	}
+}
+
 static int can_exit_sleep_mode(struct can_mcan_reg *can)
 {
 	uint32_t start_time;
@@ -149,6 +177,9 @@ int can_mcan_set_timing(const struct can_mcan_config *cfg,
 		return -EIO;
 	}
 
+	/* Configuration Change Enable */
+	can->cccr |= CAN_MCAN_CCCR_CCE;
+
 	can_mcan_configure_timing(can, timing, timing_data);
 
 	ret = can_leave_init_mode(can, K_MSEC(CAN_INIT_TIMEOUT));
@@ -386,12 +417,7 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg,
 	}
 
 	/* No memset because only aligned ptr are allowed */
-	for (uint32_t *ptr = (uint32_t *)msg_ram;
-	     ptr < (uint32_t *)msg_ram +
-		   sizeof(struct can_mcan_msg_sram) / sizeof(uint32_t);
-	     ptr++) {
-		*ptr = 0;
-	}
+	memset32_volatile(msg_ram, 0, sizeof(struct can_mcan_msg_sram));
 
 	return 0;
 }
@@ -483,15 +509,17 @@ static void can_mcan_get_message(struct can_mcan_data *data,
 	uint32_t get_idx, filt_idx;
 	struct zcan_frame frame;
 	can_rx_callback_t cb;
-	volatile uint32_t *src, *dst, *end;
 	int data_length;
 	void *cb_arg;
 	struct can_mcan_rx_fifo_hdr hdr;
+	bool rtr_filter_mask;
+	bool rtr_filter;
 
 	while ((*fifo_status_reg & CAN_MCAN_RXF0S_F0FL)) {
 		get_idx = (*fifo_status_reg & CAN_MCAN_RXF0S_F0GI) >>
 			   CAN_MCAN_RXF0S_F0GI_POS;
-		hdr = fifo[get_idx].hdr;
+		memcpy32_volatile(&hdr, &fifo[get_idx].hdr,
+				  sizeof(struct can_mcan_rx_fifo_hdr));
 
 		if (hdr.xtd) {
 			frame.id = hdr.ext_id;
@@ -511,24 +539,25 @@ static void can_mcan_get_message(struct can_mcan_data *data,
 
 		filt_idx = hdr.fidx;
 
-		/* Check if RTR must match */
-		if ((hdr.xtd && data->ext_filt_rtr_mask & (1U << filt_idx) &&
-		     ((data->ext_filt_rtr >> filt_idx) & 1U) != frame.rtr) ||
-		    (data->std_filt_rtr_mask &  (1U << filt_idx) &&
-		     ((data->std_filt_rtr >> filt_idx) & 1U) != frame.rtr)) {
+		if (hdr.xtd != 0) {
+			rtr_filter_mask = (data->ext_filt_rtr_mask & BIT(filt_idx)) != 0;
+			rtr_filter = (data->ext_filt_rtr & BIT(filt_idx)) != 0;
+		} else {
+			rtr_filter_mask = (data->std_filt_rtr_mask & BIT(filt_idx)) != 0;
+			rtr_filter = (data->std_filt_rtr & BIT(filt_idx)) != 0;
+		}
+
+		if (rtr_filter_mask && (rtr_filter != frame.rtr)) {
+			/* RTR bit does not match filter RTR mask and bit, drop frame */
+			*fifo_ack_reg = get_idx;
 			continue;
 		}
 
 		data_length = can_dlc_to_bytes(frame.dlc);
 		if (data_length <= sizeof(frame.data)) {
 			/* data needs to be written in 32 bit blocks!*/
-			for (src = fifo[get_idx].data_32,
-			     dst = frame.data_32,
-			     end = dst + CAN_DIV_CEIL(data_length, sizeof(uint32_t));
-			     dst < end;
-			     src++, dst++) {
-				*dst = *src;
-			}
+			memcpy32_volatile(frame.data_32, fifo[get_idx].data_32,
+					  ROUND_UP(data_length, sizeof(uint32_t)));
 
 			if (frame.id_type == CAN_STANDARD_IDENTIFIER) {
 				LOG_DBG("Frame on filter %d, ID: 0x%x",
@@ -644,8 +673,6 @@ int can_mcan_send(const struct can_mcan_config *cfg,
 	uint32_t put_idx;
 	int ret;
 	struct can_mcan_mm mm;
-	volatile uint32_t *dst, *end;
-	const uint32_t *src;
 
 	LOG_DBG("Sending %d bytes. Id: 0x%x, ID type: %s %s %s %s",
 		data_length, frame->id,
@@ -693,15 +720,9 @@ int can_mcan_send(const struct can_mcan_config *cfg,
 		tx_hdr.ext_id = frame->id;
 	}
 
-	msg_ram->tx_buffer[put_idx].hdr = tx_hdr;
-
-	for (src = frame->data_32,
-		dst = msg_ram->tx_buffer[put_idx].data_32,
-		end = dst + CAN_DIV_CEIL(data_length, sizeof(uint32_t));
-		dst < end;
-		src++, dst++) {
-		*dst = *src;
-	}
+	memcpy32_volatile(&msg_ram->tx_buffer[put_idx].hdr, &tx_hdr, sizeof(tx_hdr));
+	memcpy32_volatile(msg_ram->tx_buffer[put_idx].data_32, frame->data_32,
+			  ROUND_UP(data_length, 4));
 
 	data->tx_fin_cb[put_idx] = callback;
 	data->tx_fin_cb_arg[put_idx] = callback_arg;
@@ -758,7 +779,8 @@ int can_mcan_attach_std(struct can_mcan_data *data,
 	filter_element.sfce = filter_nr & 0x01 ? CAN_MCAN_FCE_FIFO1 :
 						 CAN_MCAN_FCE_FIFO0;
 
-	msg_ram->std_filt[filter_nr] = filter_element;
+	memcpy32_volatile(&msg_ram->std_filt[filter_nr], &filter_element,
+			 sizeof(struct can_mcan_std_filter));
 
 	k_mutex_unlock(&data->inst_mutex);
 
@@ -817,7 +839,8 @@ static int can_mcan_attach_ext(struct can_mcan_data *data,
 	filter_element.efce = filter_nr & 0x01 ? CAN_MCAN_FCE_FIFO1 :
 						 CAN_MCAN_FCE_FIFO0;
 
-	msg_ram->ext_filt[filter_nr] = filter_element;
+	memcpy32_volatile(&msg_ram->ext_filt[filter_nr], &filter_element,
+			  sizeof(struct can_mcan_ext_filter));
 
 	k_mutex_unlock(&data->inst_mutex);
 
@@ -871,9 +894,6 @@ int can_mcan_attach_isr(struct can_mcan_data *data,
 void can_mcan_detach(struct can_mcan_data *data,
 		     struct can_mcan_msg_sram *msg_ram, int filter_nr)
 {
-	const struct can_mcan_ext_filter ext_filter = {0};
-	const struct can_mcan_std_filter std_filter = {0};
-
 	k_mutex_lock(&data->inst_mutex, K_FOREVER);
 	if (filter_nr >= NUM_STD_FILTER_DATA) {
 		filter_nr -= NUM_STD_FILTER_DATA;
@@ -882,10 +902,12 @@ void can_mcan_detach(struct can_mcan_data *data,
 			return;
 		}
 
-		msg_ram->ext_filt[filter_nr] = ext_filter;
+		memset32_volatile(&msg_ram->ext_filt[filter_nr], 0,
+				  sizeof(struct can_mcan_ext_filter));
 		data->rx_cb_ext[filter_nr] = NULL;
 	} else {
-		msg_ram->std_filt[filter_nr] = std_filter;
+		memset32_volatile(&msg_ram->std_filt[filter_nr], 0,
+				  sizeof(struct can_mcan_std_filter));
 		data->rx_cb_std[filter_nr] = NULL;
 	}
 

drivers/can/can_mcan.h

@@ -48,7 +48,7 @@ struct can_mcan_rx_fifo_hdr {
 	volatile uint32_t res  :  2; /* Reserved */
 	volatile uint32_t fidx :  7; /* Filter Index */
 	volatile uint32_t anmf :  1; /* Accepted non-matching frame */
-} __packed;
+} __packed __aligned(4);
 
 struct can_mcan_rx_fifo {
 	struct can_mcan_rx_fifo_hdr hdr;
@@ -56,7 +56,7 @@ struct can_mcan_rx_fifo {
 		volatile uint8_t  data[64];
 		volatile uint32_t data_32[16];
 	};
-} __packed;
+} __packed __aligned(4);
 
 struct can_mcan_mm {
 	volatile uint8_t idx : 5;
@@ -84,7 +84,7 @@ struct can_mcan_tx_buffer_hdr {
 	volatile uint8_t res2 :  1; /* Reserved */
 	volatile uint8_t efc  :  1; /* Event FIFO control (Store Tx events) */
 	struct can_mcan_mm mm; /* Message marker */
-} __packed;
+} __packed __aligned(4);
 
 struct can_mcan_tx_buffer {
 	struct can_mcan_tx_buffer_hdr hdr;
@@ -92,7 +92,7 @@ struct can_mcan_tx_buffer {
 		volatile uint8_t  data[64];
 		volatile uint32_t data_32[16];
 	};
-} __packed;
+} __packed __aligned(4);
 
 #define CAN_MCAN_TE_TX    0x1 /* TX event */
 #define CAN_MCAN_TE_TXC   0x2 /* TX event in spite of cancellation */
@@ -109,7 +109,7 @@ struct can_mcan_tx_event_fifo {
 	volatile uint8_t fdf   :  1; /* FD Format */
 	volatile uint8_t et    :  2; /* Event type */
 	struct can_mcan_mm mm; /* Message marker */
-} __packed;
+} __packed __aligned(4);
 
 #define CAN_MCAN_FCE_DISABLE    0x0
 #define CAN_MCAN_FCE_FIFO0      0x1
@@ -130,7 +130,7 @@ struct can_mcan_std_filter {
 	volatile uint32_t id1  : 11;
 	volatile uint32_t sfce :  3; /* Filter config */
 	volatile uint32_t sft  :  2; /* Filter type */
-} __packed;
+} __packed __aligned(4);
 
 #define CAN_MCAN_EFT_RANGE_XIDAM 0x0
 #define CAN_MCAN_EFT_DUAL        0x1
@@ -143,7 +143,7 @@ struct can_mcan_ext_filter {
 	volatile uint32_t id2  : 29; /* ID2 for dual or range, mask otherwise */
 	volatile uint32_t res  :  1;
 	volatile uint32_t eft   : 2; /* Filter type */
-} __packed;
+} __packed __aligned(4);
 
 struct can_mcan_msg_sram {
 	volatile struct can_mcan_std_filter std_filt[NUM_STD_FILTER_ELEMENTS];
@@ -153,7 +153,7 @@ struct can_mcan_msg_sram {
 	volatile struct can_mcan_rx_fifo rx_buffer[NUM_RX_BUF_ELEMENTS];
 	volatile struct can_mcan_tx_event_fifo tx_event_fifo[NUM_TX_BUF_ELEMENTS];
 	volatile struct can_mcan_tx_buffer tx_buffer[NUM_TX_BUF_ELEMENTS];
-} __packed;
+} __packed __aligned(4);
 
 struct can_mcan_data {
 	struct k_mutex inst_mutex;

drivers/can/can_mcux_flexcan.c

@@ -253,13 +253,11 @@ static void mcux_flexcan_copy_zfilter_to_mbconfig(const struct zcan_filter *src,
 	if (src->id_type == CAN_STANDARD_IDENTIFIER) {
 		dest->format = kFLEXCAN_FrameFormatStandard;
 		dest->id = FLEXCAN_ID_STD(src->id);
-		*mask = FLEXCAN_RX_MB_STD_MASK(src->id_mask,
-					       src->rtr & src->rtr_mask, 1);
+		*mask = FLEXCAN_RX_MB_STD_MASK(src->id_mask, src->rtr_mask, 1);
 	} else {
 		dest->format = kFLEXCAN_FrameFormatExtend;
 		dest->id = FLEXCAN_ID_EXT(src->id);
-		*mask = FLEXCAN_RX_MB_EXT_MASK(src->id_mask,
-					       src->rtr & src->rtr_mask, 1);
+		*mask = FLEXCAN_RX_MB_EXT_MASK(src->id_mask, src->rtr_mask, 1);
 	}
 
 	if ((src->rtr & src->rtr_mask) == CAN_DATAFRAME) {
@@ -646,6 +644,7 @@ static inline void mcux_flexcan_transfer_rx_idle(const struct device *dev,
 static FLEXCAN_CALLBACK(mcux_flexcan_transfer_callback)
 {
 	struct mcux_flexcan_data *data = (struct mcux_flexcan_data *)userData;
+	const struct mcux_flexcan_config *config = data->dev->config;
 
 	switch (status) {
 	case kStatus_FLEXCAN_UnHandled:
@@ -654,6 +653,7 @@ static FLEXCAN_CALLBACK(mcux_flexcan_transfer_callback)
 		mcux_flexcan_transfer_error_status(data->dev, (uint64_t)result);
 		break;
 	case kStatus_FLEXCAN_TxSwitchToRx:
+		FLEXCAN_TransferAbortReceive(config->base, &data->handle, (uint64_t)result);
 		__fallthrough;
 	case kStatus_FLEXCAN_TxIdle:
 		/* The result field is a MB value which is limited to 32bit value */

drivers/can/can_stm32.c

@@ -56,7 +56,7 @@ static const uint8_t reg_demand[] = {2, 1, 4, 2};
 static void can_stm32_signal_tx_complete(struct can_mailbox *mb)
 {
 	if (mb->tx_callback) {
-		mb->tx_callback(mb->error_flags, mb->callback_arg);
+		mb->tx_callback(mb->error, mb->callback_arg);
 	} else  {
 		k_sem_give(&mb->tx_int_sem);
 	}
@@ -151,7 +151,7 @@ void can_stm32_tx_isr_handler(CAN_TypeDef *can, struct can_stm32_data *data)
 	bus_off = can->ESR & CAN_ESR_BOFF;
 
 	if ((can->TSR & CAN_TSR_RQCP0) | bus_off) {
-		data->mb0.error_flags =
+		data->mb0.error =
 				can->TSR & CAN_TSR_TXOK0 ? CAN_TX_OK  :
 				can->TSR & CAN_TSR_TERR0 ? CAN_TX_ERR :
 				can->TSR & CAN_TSR_ALST0 ? CAN_TX_ARB_LOST :
@@ -163,7 +163,7 @@ void can_stm32_tx_isr_handler(CAN_TypeDef *can, struct can_stm32_data *data)
 	}
 
 	if ((can->TSR & CAN_TSR_RQCP1) | bus_off) {
-		data->mb1.error_flags =
+		data->mb1.error =
 				can->TSR & CAN_TSR_TXOK1 ? CAN_TX_OK  :
 				can->TSR & CAN_TSR_TERR1 ? CAN_TX_ERR :
 				can->TSR & CAN_TSR_ALST1 ? CAN_TX_ARB_LOST :
@@ -175,7 +175,7 @@ void can_stm32_tx_isr_handler(CAN_TypeDef *can, struct can_stm32_data *data)
 	}
 
 	if ((can->TSR & CAN_TSR_RQCP2) | bus_off) {
-		data->mb2.error_flags =
+		data->mb2.error =
 				can->TSR & CAN_TSR_TXOK2 ? CAN_TX_OK  :
 				can->TSR & CAN_TSR_TERR2 ? CAN_TX_ERR :
 				can->TSR & CAN_TSR_ALST2 ? CAN_TX_ARB_LOST :
@@ -688,7 +688,7 @@ int can_stm32_send(const struct device *dev, const struct zcan_frame *msg,
 
 	if (callback == NULL) {
 		k_sem_take(&mb->tx_int_sem, K_FOREVER);
-		return mb->error_flags;
+		return mb->error;
 	}
 
 	return 0;

drivers/can/can_stm32.h

@@ -43,7 +43,7 @@ struct can_mailbox {
 	can_tx_callback_t tx_callback;
 	void *callback_arg;
 	struct k_sem tx_int_sem;
-	uint32_t error_flags;
+	int error;
 };
 
 

drivers/can/socket_can_generic.h

@@ -45,12 +45,12 @@ static inline void socket_can_iface_init(struct net_if *iface)
 	LOG_DBG("Init CAN interface %p dev %p", iface, dev);
 }
 
-static inline void tx_irq_callback(uint32_t error_flags, void *arg)
+static inline void tx_irq_callback(int error, void *arg)
 {
 	char *caller_str = (char *)arg;
-	if (error_flags) {
+	if (error != 0) {
 		LOG_DBG("TX error from %s! error-code: %d",
-			caller_str, error_flags);
+			caller_str, error);
 	}
 }
 

drivers/clock_control/clock_stm32_ll_h7.c

@@ -259,8 +259,28 @@ static uint32_t get_hclk_frequency(void)
 
 static int32_t prepare_regulator_voltage_scale(void)
 {
-	/* Make sure to put the CPU in highest Voltage scale during clock configuration */
+	/* Apply system power supply configuration */
+#if defined(SMPS) && defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
+	LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
+#elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
+	LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
+#else
 	LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
+#endif
+
+	/* Make sure to put the CPU in highest Voltage scale during clock configuration */
 	/* Highest voltage is SCALE0 */
 	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
 	return 0;
@@ -276,7 +296,25 @@ static int32_t optimize_regulator_voltage_scale(uint32_t sysclk_freq)
 	/* LL_PWR_REGULATOR_SCALE3 is lowest power consumption */
 	/* Must be done in accordance to the Maximum allowed frequency vs VOS*/
 	/* See RM0433 page 352 for more details */
+#if defined(SMPS) && defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
+	LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
+#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
+#elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
+	LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
+#else
 	LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
+#endif
 	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
 	return 0;
 }

drivers/console/gsm_mux.c

@@ -387,8 +387,8 @@ static int gsm_mux_send_data_msg(struct gsm_mux *mux, bool cmd,
 		hdr[3] = (size << 1) | EA;
 		pos = 4;
 	} else {
-		hdr[3] = (size >> 7);
-		hdr[4] = (size & 127) << 1;
+		hdr[3] = (size & 127) << 1;
+		hdr[4] = (size >> 7);
 		pos = 5;
 	}
 
@@ -610,7 +610,8 @@ static void ctrl_msg_cleanup(struct gsm_control_msg *entry, bool pending)
 /* T2 timeout is for control message retransmits */
 static void gsm_mux_t2_timeout(struct k_work *work)
 {
-	struct gsm_mux *mux = CONTAINER_OF(work, struct gsm_mux, t2_timer);
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct gsm_mux *mux = CONTAINER_OF(dwork, struct gsm_mux, t2_timer);
 	uint32_t current_time = k_uptime_get_32();
 	struct gsm_control_msg *entry, *next;
 

drivers/display/ssd16xx.c

@@ -636,8 +636,8 @@ static int ssd16xx_controller_init(const struct device *dev)
 
 static int ssd16xx_init(const struct device *dev)
 {
-	const struct ssd16xx_config *config = dev->config;
 	struct ssd16xx_data *driver = dev->data;
+	const struct ssd16xx_config *config = driver->config;
 
 	LOG_DBG("");
 

drivers/edac/edac_ibecc.c

@@ -302,6 +302,12 @@ int edac_ibecc_init(const struct device *dev)
 	case PCIE_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SKU11):
 		__fallthrough;
 	case PCIE_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SKU12):
+		__fallthrough;
+	case PCIE_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SKU13):
+		__fallthrough;
+	case PCIE_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SKU14):
+		__fallthrough;
+	case PCIE_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SKU15):
 		break;
 	default:
 		LOG_ERR("PCI Probe failed");

drivers/edac/ibecc.h

@@ -18,6 +18,9 @@
 #define PCI_DEVICE_ID_SKU10	0x452e
 #define PCI_DEVICE_ID_SKU11	0x4532
 #define PCI_DEVICE_ID_SKU12	0x4518
+#define PCI_DEVICE_ID_SKU13	0x451a
+#define PCI_DEVICE_ID_SKU14	0x4534
+#define PCI_DEVICE_ID_SKU15	0x4536
 
 /* TODO: Move to correct place NMI registers */
 

drivers/ethernet/phy/phy_mii.c

@@ -217,8 +217,9 @@ static void invoke_link_cb(const struct device *dev)
 
 static void monitor_work_handler(struct k_work *work)
 {
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
 	struct phy_mii_dev_data *const data =
-		CONTAINER_OF(work, struct phy_mii_dev_data, monitor_work);
+		CONTAINER_OF(dwork, struct phy_mii_dev_data, monitor_work);
 	const struct device *dev = data->dev;
 	int rc;
 

drivers/flash/flash_stm32.c

@@ -30,17 +30,6 @@ LOG_MODULE_REGISTER(flash_stm32, CONFIG_FLASH_LOG_LEVEL);
 #define STM32_FLASH_TIMEOUT	\
 	(2 * DT_PROP(DT_INST(0, st_stm32_nv_flash), max_erase_time))
 
-#if defined(FLASH_NSSR_NSBSY)		/* For STM32L5x in non-secure mode */
-#define FLASH_SECURITY_NS
-#elif defined(FLASH_SECSR_SECBSY)	/* For STM32L5x in secured mode */
-#error Flash is not supported in secure mode
-#define FLASH_SECURITY_SEC
-#else
-#define FLASH_SECURITY_NA		/* For series which does not have
-					 *  secured or non-secured mode
-					 */
-#endif
-
 static const struct flash_parameters flash_stm32_parameters = {
 	.write_block_size = FLASH_STM32_WRITE_BLOCK_SIZE,
 	/* Some SoCs (L0/L1) use an EEPROM under the hood. Distinguish
@@ -89,37 +78,11 @@ static inline void _flash_stm32_sem_give(const struct device *dev)
 #if !defined(CONFIG_SOC_SERIES_STM32WBX)
 static int flash_stm32_check_status(const struct device *dev)
 {
-	uint32_t const error =
-#if defined(FLASH_FLAG_PGAERR)
-		FLASH_FLAG_PGAERR |
-#endif
-#if defined(FLASH_FLAG_RDERR)
-		FLASH_FLAG_RDERR  |
-#endif
-#if defined(FLASH_FLAG_PGPERR)
-		FLASH_FLAG_PGPERR |
-#endif
-#if defined(FLASH_FLAG_PGSERR)
-		FLASH_FLAG_PGSERR |
-#endif
-#if defined(FLASH_FLAG_OPERR)
-		FLASH_FLAG_OPERR |
-#endif
-#if defined(FLASH_FLAG_PROGERR)
-		FLASH_FLAG_PROGERR |
-#endif
-#if defined(FLASH_FLAG_PGERR)
-		FLASH_FLAG_PGERR |
-#endif
-		FLASH_FLAG_WRPERR;
 
-#if defined(FLASH_SECURITY_NS)
-	if (FLASH_STM32_REGS(dev)->NSSR & error) {
-		LOG_DBG("Status: 0x%08x", FLASH_STM32_REGS(dev)->NSSR & error);
-#else /* FLASH_SECURITY_SEC | FLASH_SECURITY_NA */
-	if (FLASH_STM32_REGS(dev)->SR & error) {
-		LOG_DBG("Status: 0x%08x", FLASH_STM32_REGS(dev)->SR & error);
-#endif /* FLASH_SECURITY_NS */
+	if (FLASH_STM32_REGS(dev)->FLASH_STM32_SR & FLASH_STM32_SR_ERRORS) {
+		LOG_DBG("Status: 0x%08lx",
+			FLASH_STM32_REGS(dev)->FLASH_STM32_SR &
+							FLASH_STM32_SR_ERRORS);
 		return -EIO;
 	}
 
@@ -131,21 +94,21 @@ int flash_stm32_wait_flash_idle(const struct device *dev)
 {
 	int64_t timeout_time = k_uptime_get() + STM32_FLASH_TIMEOUT;
 	int rc;
+	uint32_t busy_flags;
 
 	rc = flash_stm32_check_status(dev);
 	if (rc < 0) {
 		return -EIO;
 	}
-#if defined(FLASH_SECURITY_NS)
-	while ((FLASH_STM32_REGS(dev)->NSSR & FLASH_FLAG_BSY)) {
-#else /* FLASH_SECURITY_SEC | FLASH_SECURITY_NA */
-#if defined(FLASH_SR_BSY1)
-	/* Applicable for STM32G0 series */
-	while ((FLASH_STM32_REGS(dev)->SR & FLASH_SR_BSY1)) {
-#else
-	while ((FLASH_STM32_REGS(dev)->SR & FLASH_SR_BSY)) {
+
+	busy_flags = FLASH_STM32_SR_BUSY;
+
+/* Some Series can't modify FLASH_CR reg while CFGBSY is set. Wait as well */
+#if defined(FLASH_STM32_SR_CFGBSY)
+	busy_flags |= FLASH_STM32_SR_CFGBSY;
 #endif
-#endif /* FLASH_SECURITY_NS */
+
+	while ((FLASH_STM32_REGS(dev)->FLASH_STM32_SR & busy_flags)) {
 		if (k_uptime_get() > timeout_time) {
 			LOG_ERR("Timeout! val: %d", STM32_FLASH_TIMEOUT);
 			return -EIO;

drivers/flash/flash_stm32.h

@@ -33,9 +33,142 @@ struct flash_stm32_priv {
 	/* as flash node property 'write-block-size' */
 #endif
 
+/* Differentiate between arm trust-zone non-secure/secure, and others. */
+#if defined(FLASH_NSSR_NSBSY)		/* For mcu w. TZ in non-secure mode */
+#define FLASH_SECURITY_NS
+#define FLASH_STM32_SR		NSSR
+#elif defined(FLASH_SECSR_SECBSY)	/* For mcu w. TZ  in secured mode */
+#error Flash is not supported in secure mode
+#define FLASH_SECURITY_SEC
+#else
+#define FLASH_SECURITY_NA		/* For series which does not have
+					 *  secured or non-secured mode
+					 */
+#define FLASH_STM32_SR		SR
+#endif
+
+
 #define FLASH_STM32_PRIV(dev) ((struct flash_stm32_priv *)((dev)->data))
 #define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs)
 
+
+/* Redefintions of flags and masks to harmonize stm32 series: */
+#if defined(CONFIG_SOC_SERIES_STM32G0X)
+#if defined(FLASH_FLAG_BSY2)
+#define FLASH_STM32_SR_BUSY	(FLASH_FLAG_BSY1 | FLASH_FLAG_BSY2);
+#else
+#define FLASH_STM32_SR_BUSY	(FLASH_SR_BSY1)
+#endif /* defined(FLASH_FLAG_BSY2) */
+#else
+#define FLASH_STM32_SR_BUSY	(FLASH_FLAG_BSY)
+#endif
+
+#if defined(CONFIG_SOC_SERIES_STM32G0X)
+#define FLASH_STM32_SR_CFGBSY	(FLASH_SR_CFGBSY)
+#elif defined(FLASH_FLAG_CFGBSY)
+#define FLASH_STM32_SR_CFGBSY	(FLASH_FLAG_CFGBSY)
+#endif
+
+#if defined(CONFIG_SOC_SERIES_STM32G0X)
+/* STM32G0 HAL FLASH_FLAG_x don't represent bit-masks, need FLASH_SR_x instead */
+#define FLASH_STM32_SR_OPERR	FLASH_SR_OPERR
+#define FLASH_STM32_SR_PGERR	0
+#define FLASH_STM32_SR_PROGERR	FLASH_SR_PROGERR
+#define FLASH_STM32_SR_WRPERR	FLASH_SR_WRPERR
+#define FLASH_STM32_SR_PGAERR	FLASH_SR_PGAERR
+#define FLASH_STM32_SR_SIZERR	FLASH_SR_SIZERR
+#define FLASH_STM32_SR_PGSERR	FLASH_SR_PGSERR
+#define FLASH_STM32_SR_MISERR	FLASH_SR_MISERR
+#define FLASH_STM32_SR_FASTERR	FLASH_SR_FASTERR
+#if defined(FLASH_SR_RDERR)
+#define FLASH_STM32_SR_RDERR	FLASH_SR_RDERR
+#else
+#define FLASH_STM32_SR_RDERR	0
+#endif
+#define FLASH_STM32_SR_PGPERR	0
+
+#else /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
+#if defined(FLASH_FLAG_OPERR)
+#define FLASH_STM32_SR_OPERR	FLASH_FLAG_OPERR
+#else
+#define FLASH_STM32_SR_OPERR	0
+#endif
+
+#if defined(FLASH_FLAG_PGERR)
+#define FLASH_STM32_SR_PGERR	FLASH_FLAG_PGERR
+#else
+#define FLASH_STM32_SR_PGERR	0
+#endif
+
+#if defined(FLASH_FLAG_PROGERR)
+#define FLASH_STM32_SR_PROGERR	FLASH_FLAG_PROGERR
+#else
+#define FLASH_STM32_SR_PROGERR	0
+#endif
+
+#if defined(FLASH_FLAG_WRPERR)
+#define FLASH_STM32_SR_WRPERR	FLASH_FLAG_WRPERR
+#else
+#define FLASH_STM32_SR_WRPERR	0
+#endif
+
+#if defined(FLASH_FLAG_PGAERR)
+#define FLASH_STM32_SR_PGAERR	FLASH_FLAG_PGAERR
+#else
+#define FLASH_STM32_SR_PGAERR	0
+#endif
+
+#if defined(FLASH_FLAG_SIZERR)
+#define FLASH_STM32_SR_SIZERR	FLASH_FLAG_SIZERR
+#else
+#define FLASH_STM32_SR_SIZERR	0
+#endif
+
+#if defined(FLASH_FLAG_PGSERR)
+#define FLASH_STM32_SR_PGSERR	FLASH_FLAG_PGSERR
+#else
+#define FLASH_STM32_SR_PGSERR	0
+#endif
+
+#if defined(FLASH_FLAG_MISERR)
+#define FLASH_STM32_SR_MISERR	FLASH_FLAG_MISERR
+#else
+#define FLASH_STM32_SR_MISERR	0
+#endif
+
+#if defined(FLASH_FLAG_FASTERR)
+#define FLASH_STM32_SR_FASTERR	FLASH_FLAG_FASTERR
+#else
+#define FLASH_STM32_SR_FASTERR	0
+#endif
+
+#if defined(FLASH_FLAG_RDERR)
+#define FLASH_STM32_SR_RDERR	FLASH_FLAG_RDERR
+#else
+#define FLASH_STM32_SR_RDERR	0
+#endif
+
+#if defined(FLASH_FLAG_PGPERR)
+#define FLASH_STM32_SR_PGPERR	FLASH_FLAG_PGPERR
+#else
+#define FLASH_STM32_SR_PGPERR	0
+#endif
+
+#endif /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
+
+#define FLASH_STM32_SR_ERRORS  (FLASH_STM32_SR_OPERR |			\
+				FLASH_STM32_SR_PGERR |			\
+				FLASH_STM32_SR_PROGERR |		\
+				FLASH_STM32_SR_WRPERR |			\
+				FLASH_STM32_SR_PGAERR |			\
+				FLASH_STM32_SR_SIZERR |			\
+				FLASH_STM32_SR_PGSERR |			\
+				FLASH_STM32_SR_MISERR |			\
+				FLASH_STM32_SR_FASTERR |		\
+				FLASH_STM32_SR_RDERR |			\
+				FLASH_STM32_SR_PGPERR)
+
+
 #ifdef CONFIG_FLASH_PAGE_LAYOUT
 static inline bool flash_stm32_range_exists(const struct device *dev,
 					    off_t offset,

drivers/flash/flash_stm32g0x.c

@@ -21,12 +21,30 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
 #include "flash_stm32.h"
 
 
-#define STM32G0X_PAGE_SHIFT	11
+/* FLASH_DBANK_SUPPORT is defined in the HAL for all G0Bx and G0C1 SoCs,
+ * while only those with 256KiB and 512KiB Flash have two banks.
+ */
+#if defined(FLASH_DBANK_SUPPORT) && (CONFIG_FLASH_SIZE > (128))
+#define STM32G0_DBANK_SUPPORT
+#endif
 
+#if defined(STM32G0_DBANK_SUPPORT)
+#define STM32G0_BANK_COUNT		2
+#define STM32G0_BANK2_START_PAGE_NR	256
+#else
+#define STM32G0_BANK_COUNT		1
+#endif
+
+#define STM32G0_FLASH_SIZE		(FLASH_SIZE)
+#define STM32G0_FLASH_PAGE_SIZE		(FLASH_PAGE_SIZE)
+#define STM32G0_PAGES_PER_BANK		\
+	((STM32G0_FLASH_SIZE / STM32G0_FLASH_PAGE_SIZE) / STM32G0_BANK_COUNT)
 
 /*
  * offset and len must be aligned on 8 for write,
  * positive and not beyond end of flash
+ * On dual-bank SoCs memory accesses starting on the first bank and continuing
+ * beyond the first bank into the second bank are allowed.
  */
 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
 			     uint32_t len,
@@ -36,14 +54,6 @@ bool flash_stm32_valid_range(const struct device *dev, off_t offset,
 		flash_stm32_range_exists(dev, offset, len);
 }
 
-/*
- * STM32G0xx devices can have up to 64 2K pages
- */
-static unsigned int get_page(off_t offset)
-{
-	return offset >> STM32G0X_PAGE_SHIFT;
-}
-
 static inline void flush_cache(FLASH_TypeDef *regs)
 {
 	if (regs->ACR & FLASH_ACR_ICEN) {
@@ -101,11 +111,12 @@ static int write_dword(const struct device *dev, off_t offset, uint64_t val)
 	return rc;
 }
 
-static int erase_page(const struct device *dev, unsigned int page)
+static int erase_page(const struct device *dev, unsigned int offset)
 {
 	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
 	uint32_t tmp;
 	int rc;
+	int page;
 
 	/* if the control register is locked, do not fail silently */
 	if (regs->CR & FLASH_CR_LOCK) {
@@ -125,16 +136,32 @@ static int erase_page(const struct device *dev, unsigned int page)
 	 */
 	flush_cache(regs);
 
-	/* Set the PER bit and select the page you wish to erase */
-	regs->CR |= FLASH_CR_PER;
-	regs->CR &= ~FLASH_CR_PNB_Msk;
-	regs->CR |= ((page % 256) << 3);
-
-	/* Set the STRT bit */
-	regs->CR |= FLASH_CR_STRT;
-
-	/* flush the register write */
 	tmp = regs->CR;
+	page = offset / STM32G0_FLASH_PAGE_SIZE;
+
+#if defined(STM32G0_DBANK_SUPPORT)
+	bool swap_enabled = (regs->OPTR & FLASH_OPTR_nSWAP_BANK) == 0;
+
+	/* big page-nr w/o swap or small page-nr w/ swap indicate bank2 */
+	if ((page >= STM32G0_PAGES_PER_BANK) != swap_enabled) {
+		page = (page % STM32G0_PAGES_PER_BANK) + STM32G0_BANK2_START_PAGE_NR;
+		tmp |= FLASH_CR_BKER;
+		LOG_DBG("Erase page %d on bank 2", page);
+	} else {
+		page = page % STM32G0_PAGES_PER_BANK;
+		tmp &= ~FLASH_CR_BKER;
+		LOG_DBG("Erase page %d on bank 1", page);
+	}
+#endif
+
+	/* Set the PER bit and select the page you wish to erase */
+	tmp |= FLASH_CR_PER;
+	tmp &= ~FLASH_CR_PNB_Msk;
+	tmp |= ((page << FLASH_CR_PNB_Pos) & FLASH_CR_PNB_Msk);
+
+	/* Set the STRT bit and write the reg */
+	tmp |= FLASH_CR_STRT;
+	regs->CR = tmp;
 
 	/* Wait for the BSY bit */
 	rc = flash_stm32_wait_flash_idle(dev);
@@ -148,11 +175,11 @@ int flash_stm32_block_erase_loop(const struct device *dev,
 				 unsigned int offset,
 				 unsigned int len)
 {
-	int i, rc = 0;
+	unsigned int addr = offset;
+	int rc = 0;
 
-	i = get_page(offset);
-	for (; i <= get_page(offset + len - 1) ; ++i) {
-		rc = erase_page(dev, i);
+	for (; addr <= offset + len - 1 ; addr += STM32G0_FLASH_PAGE_SIZE) {
+		rc = erase_page(dev, addr);
 		if (rc < 0) {
 			break;
 		}
@@ -176,6 +203,16 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
 	return rc;
 }
 
+/*
+ * The address space is always continuous, even though a subset of G0 SoCs has
+ * two flash banks.
+ * Only the "physical" flash page-NRs are not continuous on those SoCs.
+ * As a result the page numbers used in the zephyr flash api differs
+ * from the "physical" flash page number.
+ * The first is equal to the address offset divided by the page size, while
+ * "physical" pages are numbered starting with 0 on bank1 and 256 on bank2.
+ * As a result only a single homogeneous flash page layout needs to be defined.
+ */
 void flash_stm32_page_layout(const struct device *dev,
 			     const struct flash_pages_layout **layout,
 			     size_t *layout_size)
@@ -188,10 +225,24 @@ void flash_stm32_page_layout(const struct device *dev,
 	ARG_UNUSED(dev);
 
 	if (stm32g0_flash_layout.pages_count == 0) {
-		stm32g0_flash_layout.pages_count = FLASH_SIZE / FLASH_PAGE_SIZE;
-		stm32g0_flash_layout.pages_size = FLASH_PAGE_SIZE;
+		stm32g0_flash_layout.pages_count =
+				STM32G0_FLASH_SIZE / STM32G0_FLASH_PAGE_SIZE;
+		stm32g0_flash_layout.pages_size = STM32G0_FLASH_PAGE_SIZE;
 	}
 
 	*layout = &stm32g0_flash_layout;
 	*layout_size = 1;
 }
+
+/* Override weak function */
+int  flash_stm32_check_configuration(void)
+{
+#if defined(STM32G0_DBANK_SUPPORT) && (CONFIG_FLASH_SIZE == 256)
+	/* Single bank mode not supported on dual bank SoCs with 256kiB flash */
+	if ((regs->OPTR & FLASH_OPTR_DUAL_BANK) == 0) {
+		LOG_ERR("Single bank configuration not supported by the driver");
+		return -ENOTSUP;
+	}
+#endif
+	return 0;
+}

drivers/i2c/i2c_handlers.c

@@ -71,7 +71,7 @@ static inline int z_vrfy_i2c_slave_driver_register(const struct device *dev)
 static inline int z_vrfy_i2c_slave_driver_unregister(const struct device *dev)
 {
 	Z_OOPS(Z_SYSCALL_OBJ(dev, K_OBJ_DRIVER_I2C));
-	return z_vrfy_i2c_slave_driver_unregister(dev);
+	return z_impl_i2c_slave_driver_unregister(dev);
 }
 #include <syscalls/i2c_slave_driver_unregister_mrsh.c>
 

drivers/lora/sx126x.c

@@ -410,7 +410,10 @@ static void sx126x_dio1_irq_work_handler(struct k_work *work)
 		Radio.IrqProcess();
 	}
 
-	sx126x_dio1_irq_enable(&dev_data);
+	/* Re-enable the interrupt if we are not in sleep mode */
+	if (dev_data.mode != MODE_SLEEP) {
+		sx126x_dio1_irq_enable(&dev_data);
+	}
 }
 
 static int sx126x_lora_init(const struct device *dev)

drivers/modem/hl7800.c

@@ -241,8 +241,8 @@ static const struct mdm_control_pinconfig pinconfig[] = {
 #define MDM_SEND_OK_ENABLED 0
 #define MDM_SEND_OK_DISABLED 1
 
-#define MDM_CMD_SEND_TIMEOUT K_SECONDS(5)
-#define MDM_IP_SEND_RX_TIMEOUT K_SECONDS(60)
+#define MDM_CMD_SEND_TIMEOUT K_SECONDS(6)
+#define MDM_IP_SEND_RX_TIMEOUT K_SECONDS(62)
 #define MDM_SOCK_NOTIF_DELAY K_MSEC(150)
 #define MDM_CMD_CONN_TIMEOUT K_SECONDS(31)
 
@@ -1317,7 +1317,7 @@ static int send_data(struct hl7800_socket *sock, struct net_pkt *pkt)
 	/* Send EOF pattern to terminate data */
 	k_sem_reset(&sock->sock_send_sem);
 	mdm_receiver_send(&ictx.mdm_ctx, EOF_PATTERN, strlen(EOF_PATTERN));
-	ret = k_sem_take(&sock->sock_send_sem, MDM_CMD_SEND_TIMEOUT);
+	ret = k_sem_take(&sock->sock_send_sem, MDM_IP_SEND_RX_TIMEOUT);
 	if (ret == 0) {
 		ret = ictx.last_error;
 	} else if (ret == -EAGAIN) {

drivers/modem/modem_iface_uart.c

@@ -130,8 +130,8 @@ static bool mux_is_active(struct modem_iface *iface)
 	bool active = false;
 
 #if defined(CONFIG_UART_MUX_DEVICE_NAME)
-	const char *mux_name = CONFIG_UART_MUX_DEVICE_NAME;
-	active = (mux_name == iface->dev->name);
+	active = strncmp(CONFIG_UART_MUX_DEVICE_NAME, iface->dev->name,
+			 sizeof(CONFIG_UART_MUX_DEVICE_NAME) - 1) == 0;
 #endif /* CONFIG_UART_MUX_DEVICE_NAME */
 
 	return active;

drivers/sensor/sm351lt/sm351lt.c

@@ -209,9 +209,9 @@ static int sm351lt_init(const struct device *dev)
 	}
 
 #if defined(CONFIG_SM351LT_TRIGGER)
-#if defined(CONFIG_SM351LT_TRIGGER_OWN_THREAD)
 	data->dev = dev;
 
+#if defined(CONFIG_SM351LT_TRIGGER_OWN_THREAD)
 	k_sem_init(&data->gpio_sem, 0, K_SEM_MAX_LIMIT);
 
 	k_thread_create(&data->thread, data->thread_stack,

drivers/serial/uart_sam0.c

@@ -186,7 +186,8 @@ static int uart_sam0_tx_halt(struct uart_sam0_dev_data *dev_data)
 
 static void uart_sam0_tx_timeout(struct k_work *work)
 {
-	struct uart_sam0_dev_data *dev_data = CONTAINER_OF(work,
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct uart_sam0_dev_data *dev_data = CONTAINER_OF(dwork,
 							   struct uart_sam0_dev_data, tx_timeout_work);
 
 	uart_sam0_tx_halt(dev_data);

drivers/serial/uart_stm32.c

@@ -51,6 +51,34 @@ LOG_MODULE_REGISTER(uart_stm32);
 #define UART_STRUCT(dev)					\
 	((USART_TypeDef *)(DEV_CFG(dev))->uconf.base)
 
+#if HAS_LPUART_1
+#ifdef USART_PRESC_PRESCALER
+uint32_t lpuartdiv_calc(const uint64_t clock_rate, const uint16_t presc_idx,
+			const uint32_t baud_rate)
+{
+	uint64_t lpuartdiv;
+
+	lpuartdiv = clock_rate / LPUART_PRESCALER_TAB[presc_idx];
+	lpuartdiv *= LPUART_LPUARTDIV_FREQ_MUL;
+	lpuartdiv += baud_rate / 2;
+	lpuartdiv /= baud_rate;
+
+	return (uint32_t)lpuartdiv;
+}
+#else
+uint32_t lpuartdiv_calc(const uint64_t clock_rate, const uint32_t baud_rate)
+{
+	uint64_t lpuartdiv;
+
+	lpuartdiv = clock_rate * LPUART_LPUARTDIV_FREQ_MUL;
+	lpuartdiv += baud_rate / 2;
+	lpuartdiv /= baud_rate;
+
+	return (uint32_t)lpuartdiv;
+}
+#endif /* USART_PRESC_PRESCALER */
+#endif /* HAS_LPUART_1 */
+
 #define TIMEOUT 1000
 
 #ifdef CONFIG_PM
@@ -92,13 +120,39 @@ static inline void uart_stm32_set_baudrate(const struct device *dev,
 		return;
 	}
 
-
 #if HAS_LPUART_1
 	if (IS_LPUART_INSTANCE(UartInstance)) {
+		uint32_t lpuartdiv;
+#ifdef USART_PRESC_PRESCALER
+		uint8_t presc_idx;
+		uint32_t presc_val;
+
+		for (presc_idx = 0; presc_idx < ARRAY_SIZE(LPUART_PRESCALER_TAB); presc_idx++) {
+			lpuartdiv = lpuartdiv_calc(clock_rate, presc_idx, baud_rate);
+			if (lpuartdiv >= LPUART_BRR_MIN_VALUE && lpuartdiv <= LPUART_BRR_MASK) {
+				break;
+			}
+		}
+
+		if (presc_idx == ARRAY_SIZE(LPUART_PRESCALER_TAB)) {
+			LOG_ERR("Unable to set %s to %d", dev->name, baud_rate);
+			return;
+		}
+
+		presc_val = presc_idx << USART_PRESC_PRESCALER_Pos;
+
+		LL_LPUART_SetPrescaler(UartInstance, presc_val);
+#else
+		lpuartdiv = lpuartdiv_calc(clock_rate, baud_rate);
+		if (lpuartdiv < LPUART_BRR_MIN_VALUE || lpuartdiv > LPUART_BRR_MASK) {
+			LOG_ERR("Unable to set %s to %d", dev->name, baud_rate);
+			return;
+		}
+#endif /* USART_PRESC_PRESCALER */
 		LL_LPUART_SetBaudRate(UartInstance,
 				      clock_rate,
 #ifdef USART_PRESC_PRESCALER
-				      LL_USART_PRESCALER_DIV1,
+				      presc_val,
 #endif
 				      baud_rate);
 	} else {
@@ -473,15 +527,32 @@ static void uart_stm32_poll_out(const struct device *dev,
 					unsigned char c)
 {
 	USART_TypeDef *UartInstance = UART_STRUCT(dev);
+#ifdef CONFIG_PM
+	struct uart_stm32_data *data = DEV_DATA(dev);
+#endif
+	int key;
 
-	/* Wait for TXE flag to be raised */
-	while (!LL_USART_IsActiveFlag_TXE(UartInstance)) {
+	/* Wait for TXE flag to be raised
+	 * When TXE flag is raised, we lock interrupts to prevent interrupts (notably that of usart)
+	 * or thread switch. Then, we can safely send our character. The character sent will be
+	 * interlaced with the characters potentially send with interrupt transmission API
+	 */
+	while (1) {
+		if (LL_USART_IsActiveFlag_TXE(UartInstance)) {
+			key = irq_lock();
+			if (LL_USART_IsActiveFlag_TXE(UartInstance)) {
+				break;
+			}
+			irq_unlock(key);
+		}
 	}
 
 #ifdef CONFIG_PM
-	struct uart_stm32_data *data = DEV_DATA(dev);
 
-	if (!data->tx_poll_stream_on) {
+	/* If an interrupt transmission is in progress, the pm constraint is already managed by the
+	 * call of uart_stm32_irq_tx_[en|dis]able
+	 */
+	if (!data->tx_poll_stream_on && !data->tx_int_stream_on) {
 		data->tx_poll_stream_on = true;
 
 		/* Don't allow system to suspend until stream
@@ -497,6 +568,7 @@ static void uart_stm32_poll_out(const struct device *dev,
 #endif /* CONFIG_PM */
 
 	LL_USART_TransmitData8(UartInstance, (uint8_t)c);
+	irq_unlock(key);
 }
 
 static int uart_stm32_err_check(const struct device *dev)
@@ -520,6 +592,16 @@ static int uart_stm32_err_check(const struct device *dev)
 		err |= UART_ERROR_FRAMING;
 	}
 
+#if !defined(CONFIG_SOC_SERIES_STM32F0X) || defined(USART_LIN_SUPPORT)
+	if (LL_USART_IsActiveFlag_LBD(UartInstance)) {
+		err |= UART_BREAK;
+	}
+
+	if (err & UART_BREAK) {
+		LL_USART_ClearFlag_LBD(UartInstance);
+	}
+#endif
+
 	if (err & UART_ERROR_OVERRUN) {
 		LL_USART_ClearFlag_ORE(UartInstance);
 	}
@@ -531,7 +613,6 @@ static int uart_stm32_err_check(const struct device *dev)
 	if (err & UART_ERROR_FRAMING) {
 		LL_USART_ClearFlag_FE(UartInstance);
 	}
-
 	/* Clear noise error as well,
 	 * it is not represented by the errors enum
 	 */
@@ -556,6 +637,14 @@ static int uart_stm32_fifo_fill(const struct device *dev,
 {
 	USART_TypeDef *UartInstance = UART_STRUCT(dev);
 	uint8_t num_tx = 0U;
+	int key;
+
+	if (!LL_USART_IsActiveFlag_TXE(UartInstance)) {
+		return num_tx;
+	}
+
+	/* Lock interrupts to prevent nested interrupts or thread switch */
+	key = irq_lock();
 
 	while ((size - num_tx > 0) &&
 	       LL_USART_IsActiveFlag_TXE(UartInstance)) {
@@ -565,6 +654,8 @@ static int uart_stm32_fifo_fill(const struct device *dev,
 		LL_USART_TransmitData8(UartInstance, tx_data[num_tx++]);
 	}
 
+	irq_unlock(key);
+
 	return num_tx;
 }
 
@@ -593,25 +684,44 @@ static int uart_stm32_fifo_read(const struct device *dev, uint8_t *rx_data,
 static void uart_stm32_irq_tx_enable(const struct device *dev)
 {
 	USART_TypeDef *UartInstance = UART_STRUCT(dev);
-
 #ifdef CONFIG_PM
 	struct uart_stm32_data *data = DEV_DATA(dev);
+	int key;
+#endif
 
+#ifdef CONFIG_PM
+	key = irq_lock();
 	data->tx_poll_stream_on = false;
+	data->tx_int_stream_on = true;
 	uart_stm32_pm_constraint_set(dev);
 #endif
 	LL_USART_EnableIT_TC(UartInstance);
+
+#ifdef CONFIG_PM
+	irq_unlock(key);
+#endif
 }
 
 static void uart_stm32_irq_tx_disable(const struct device *dev)
 {
 	USART_TypeDef *UartInstance = UART_STRUCT(dev);
+#ifdef CONFIG_PM
+	struct uart_stm32_data *data = DEV_DATA(dev);
+	int key;
+
+	key = irq_lock();
+#endif
 
 	LL_USART_DisableIT_TC(UartInstance);
 
 #ifdef CONFIG_PM
+	data->tx_int_stream_on = false;
 	uart_stm32_pm_constraint_release(dev);
 #endif
+
+#ifdef CONFIG_PM
+	irq_unlock(key);
+#endif
 }
 
 static int uart_stm32_irq_tx_ready(const struct device *dev)
@@ -1234,7 +1344,8 @@ static int uart_stm32_async_tx_abort(const struct device *dev)
 
 static void uart_stm32_async_rx_timeout(struct k_work *work)
 {
-	struct uart_dma_stream *rx_stream = CONTAINER_OF(work,
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct uart_dma_stream *rx_stream = CONTAINER_OF(dwork,
 			struct uart_dma_stream, timeout_work);
 	struct uart_stm32_data *data = CONTAINER_OF(rx_stream,
 			struct uart_stm32_data, dma_rx);
@@ -1251,7 +1362,8 @@ static void uart_stm32_async_rx_timeout(struct k_work *work)
 
 static void uart_stm32_async_tx_timeout(struct k_work *work)
 {
-	struct uart_dma_stream *tx_stream = CONTAINER_OF(work,
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct uart_dma_stream *tx_stream = CONTAINER_OF(dwork,
 			struct uart_dma_stream, timeout_work);
 	struct uart_stm32_data *data = CONTAINER_OF(tx_stream,
 			struct uart_stm32_data, dma_tx);

drivers/serial/uart_stm32.h

@@ -74,6 +74,7 @@ struct uart_stm32_data {
 #endif
 #ifdef CONFIG_PM
 	bool tx_poll_stream_on;
+	bool tx_int_stream_on;
 	bool pm_constraint_on;
 #endif
 };

drivers/spi/spi_ll_stm32.c

@@ -718,11 +718,11 @@ static int transceive_dma(const struct device *dev,
 	/* Set buffers info */
 	spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
 
+	LL_SPI_Enable(spi);
+
 	/* This is turned off in spi_stm32_complete(). */
 	spi_stm32_cs_control(dev, true);
 
-	LL_SPI_Enable(spi);
-
 	while (data->ctx.rx_len > 0 || data->ctx.tx_len > 0) {
 		size_t dma_len;
 

drivers/spi/spi_nrfx_spi.c

@@ -288,8 +288,10 @@ static int spi_nrfx_pm_control(const struct device *dev,
 		break;
 
 	case PM_DEVICE_ACTION_SUSPEND:
-		nrfx_spi_uninit(&config->spi);
-		data->initialized = false;
+		if (data->initialized) {
+			nrfx_spi_uninit(&config->spi);
+			data->initialized = false;
+		}
 		break;
 
 	default:

drivers/spi/spi_nrfx_spim.c

@@ -345,8 +345,10 @@ static int spim_nrfx_pm_control(const struct device *dev,
 		break;
 
 	case PM_DEVICE_ACTION_SUSPEND:
-		nrfx_spim_uninit(&config->spim);
-		data->initialized = false;
+		if (data->initialized) {
+			nrfx_spim_uninit(&config->spim);
+			data->initialized = false;
+		}
 		break;
 
 	default:

drivers/virtualization/virt_ivshmem.c

@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#define DT_DRV_COMPAT qemu_ivshmem
+
 #define LOG_LEVEL CONFIG_IVSHMEM_LOG_LEVEL
 #include <logging/log.h>
 LOG_MODULE_REGISTER(ivshmem);
@@ -223,25 +225,42 @@ static const struct ivshmem_driver_api ivshmem_api = {
 static int ivshmem_init(const struct device *dev)
 {
 	struct ivshmem *data = dev->data;
+	static bool bdf_lookup_done;
 
-	data->bdf = pcie_bdf_lookup(PCIE_ID(IVSHMEM_VENDOR_ID,
-					    IVSHMEM_DEVICE_ID));
-	if (data->bdf == PCIE_BDF_NONE) {
-		LOG_WRN("ivshmem device not found");
+	if ((data->bdf == PCIE_BDF_NONE) && bdf_lookup_done) {
+		LOG_ERR("One instance of ivshmem with pcie_bdf_lookup() already initialized.\n"
+			"Using more than one with PCIE_BDF_NONE parameter might conflict\n"
+			"with already initialized instances.");
 		return -ENOTSUP;
 	}
-
+	if ((data->bdf == PCIE_BDF_NONE) && !bdf_lookup_done) {
+		if (data->dev_ven_id) {
+			data->bdf = pcie_bdf_lookup(data->dev_ven_id);
+		} else {
+			data->bdf = pcie_bdf_lookup(PCIE_ID(IVSHMEM_VENDOR_ID, IVSHMEM_DEVICE_ID));
+		}
+		if (data->bdf == PCIE_BDF_NONE) {
+			LOG_WRN("ivshmem device not found");
+			return -ENOTSUP;
+		}
+	}
 	LOG_DBG("ivshmem found at bdf 0x%x", data->bdf);
+	bdf_lookup_done = true;
 
 	if (!ivshmem_configure(dev)) {
 		return -EIO;
 	}
-
 	return 0;
 }
 
-static struct ivshmem ivshmem_data;
+#define IVSHMEM_DEVICE_INIT(n) \
+	static struct ivshmem ivshmem_data_##n = { \
+		.bdf = DT_INST_REG_ADDR_BY_IDX(n, 0), \
+		.dev_ven_id = DT_INST_REG_SIZE_BY_IDX(n, 0) \
+	}; \
+	DEVICE_DT_INST_DEFINE(n, &ivshmem_init, NULL, \
+			      &ivshmem_data_##n, NULL, \
+			      POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
+			      &ivshmem_api);
 
-DEVICE_DEFINE(ivshmem, CONFIG_IVSHMEM_DEV_NAME,
-	      ivshmem_init, NULL, &ivshmem_data, NULL,
-	      POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &ivshmem_api);
+DT_INST_FOREACH_STATUS_OKAY(IVSHMEM_DEVICE_INIT)

drivers/virtualization/virt_ivshmem.h

@@ -25,6 +25,7 @@ struct ivshmem_param {
 struct ivshmem {
 	DEVICE_MMIO_RAM;
 	pcie_bdf_t bdf;
+	uint32_t dev_ven_id;
 	uintptr_t shmem;
 	size_t size;
 #ifdef CONFIG_IVSHMEM_DOORBELL

drivers/watchdog/wdt_iwdg_stm32.c

@@ -83,6 +83,8 @@ static int iwdg_stm32_setup(const struct device *dev, uint8_t options)
 	if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
 #if defined(CONFIG_SOC_SERIES_STM32F0X)
 		LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
+#elif defined(CONFIG_SOC_SERIES_STM32G0X)
+		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
 #elif defined(CONFIG_SOC_SERIES_STM32L0X)
 		LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
 #endif

drivers/wifi/esp_at/esp.c

@@ -418,7 +418,8 @@ MODEM_CMD_DEFINE(on_cmd_cipsta)
 
 static void esp_ip_addr_work(struct k_work *work)
 {
-	struct esp_data *dev = CONTAINER_OF(work, struct esp_data,
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct esp_data *dev = CONTAINER_OF(dwork, struct esp_data,
 					    ip_addr_work);
 	int ret;
 

drivers/wifi/esp_at/esp_socket.c

@@ -169,6 +169,15 @@ void esp_socket_rx(struct esp_socket *sock, struct net_buf *buf,
 		return;
 	}
 
+#ifdef CONFIG_NET_SOCKETS
+	/* We need to claim the net_context mutex here so that the ordering of
+	 * net_context and socket mutex claims matches the TX code path. Failure
+	 * to do so can lead to deadlocks.
+	 */
+	if (sock->context->cond.lock) {
+		k_mutex_lock(sock->context->cond.lock, K_FOREVER);
+	}
+#endif /* CONFIG_NET_SOCKETS */
 	k_mutex_lock(&sock->lock, K_FOREVER);
 	if (sock->recv_cb) {
 		sock->recv_cb(sock->context, pkt, NULL, NULL,
@@ -179,6 +188,11 @@ void esp_socket_rx(struct esp_socket *sock, struct net_buf *buf,
 		net_pkt_unref(pkt);
 	}
 	k_mutex_unlock(&sock->lock);
+#ifdef CONFIG_NET_SOCKETS
+	if (sock->context->cond.lock) {
+		k_mutex_unlock(sock->context->cond.lock);
+	}
+#endif /* CONFIG_NET_SOCKETS */
 }
 
 void esp_socket_close(struct esp_socket *sock)

drivers/wifi/eswifi/eswifi_socket.c

@@ -91,10 +91,11 @@ static void eswifi_off_read_work(struct k_work *work)
 	int next_timeout_ms = 100;
 	int err, len;
 	char *data;
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
 
 	LOG_DBG("");
 
-	socket = CONTAINER_OF(work, struct eswifi_off_socket, read_work);
+	socket = CONTAINER_OF(dwork, struct eswifi_off_socket, read_work);
 	eswifi = eswifi_socket_to_dev(socket);
 
 	eswifi_lock(eswifi);

dts/arm/st/l0/stm32l0.dtsi

@@ -63,7 +63,7 @@
 		clk_lsi: clk-lsi {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
-			clock-frequency = <DT_FREQ_K(32)>;
+			clock-frequency = <DT_FREQ_K(37)>;
 			status = "disabled";
 		};
 

dts/bindings/virtualization/qemu,ivshmem.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: ivShMem device properties
+
+compatible: "qemu,ivshmem"
+
+include: base.yaml

include/arch/arm64/lib_helpers.h

@@ -56,6 +56,7 @@
 MAKE_REG_HELPER(cntfrq_el0);
 MAKE_REG_HELPER(cnthctl_el2);
 MAKE_REG_HELPER(cnthp_ctl_el2);
+MAKE_REG_HELPER(cnthps_ctl_el2);
 MAKE_REG_HELPER(cntv_ctl_el0)
 MAKE_REG_HELPER(cntv_cval_el0)
 MAKE_REG_HELPER(cntvct_el0);

include/arch/riscv/common/linker.ld

@@ -304,7 +304,7 @@ GROUP_START(ITCM)
 	} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)
 
 	__itcm_size = __itcm_end - __itcm_start;
-	__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);
+	__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);
 
 GROUP_END(ITCM)
 #endif
@@ -339,7 +339,7 @@ GROUP_START(DTCM)
 
 	__dtcm_end = .;
 
-	__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);
+	__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);
 
 GROUP_END(DTCM)
 #endif

include/arch/x86/cpuid.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2022 Intel Corp.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_ARCH_X86_CPUID_H_
+#define ZEPHYR_INCLUDE_ARCH_X86_CPUID_H_
+
+#ifndef _ASMLANGUAGE
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CPUID_BASIC_INFO_1			0x01
+#define CPUID_EXTENDED_FEATURES_LVL		0x07
+#define CPUID_EXTENDED_TOPOLOGY_ENUMERATION	0x0B
+#define CPUID_EXTENDED_TOPOLOGY_ENUMERATION_V2	0x1F
+
+/* Bits to check in CPUID extended features */
+#define CPUID_SPEC_CTRL_SSBD	BIT(31)
+#define CPUID_SPEC_CTRL_IBRS	BIT(26)
+
+uint32_t z_x86_cpuid_extended_features(void);
+
+uint8_t z_x86_cpuid_get_current_physical_apic_id(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _ASMLANGUAGE */
+
+#endif /* ZEPHYR_INCLUDE_ARCH_X86_CPUID_H_ */

include/bluetooth/gatt.h

@@ -1599,6 +1599,13 @@ struct bt_gatt_subscribe_params {
 #endif /* CONFIG_BT_GATT_AUTO_DISCOVER_CCC */
 	/** Subscribe value */
 	uint16_t value;
+#if defined(CONFIG_BT_SMP)
+	/** Minimum required security for received notification. Notifications
+	 * and indications received over a connection with a lower security
+	 * level are silently discarded.
+	 */
+	bt_security_t min_security;
+#endif
 	/** Subscription flags */
 	ATOMIC_DEFINE(flags, BT_GATT_SUBSCRIBE_NUM_FLAGS);
 

include/drivers/can.h

@@ -302,10 +302,10 @@ struct can_timing {
  * @typedef can_tx_callback_t
  * @brief Define the application callback handler function signature
  *
- * @param error_flags status of the performed send operation
+ * @param error status of the performed send operation
  * @param arg argument that was passed when the message was sent
  */
-typedef void (*can_tx_callback_t)(uint32_t error_flags, void *arg);
+typedef void (*can_tx_callback_t)(int error, void *arg);
 
 /**
  * @typedef can_rx_callback_t

include/drivers/clock_control/stm32_clock_control.h

@@ -207,7 +207,7 @@
 #endif
 
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
-#define STM32_PLL_XTPRE		DT_PROP(DT_NODELABEL(pll), xtre)
+#define STM32_PLL_XTPRE		DT_PROP(DT_NODELABEL(pll), xtpre)
 #define STM32_PLL_MULTIPLIER	DT_PROP(DT_NODELABEL(pll), mul)
 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
 	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \
@@ -269,6 +269,7 @@
 #define STM32_PLL_SRC_MSI	DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
 #define STM32_PLL_SRC_MSIS	DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
 #define STM32_PLL_SRC_HSI	DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
+#define STM32_PLL_SRC_CSI	DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
 #define STM32_PLL_SRC_HSE	DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
 #define STM32_PLL_SRC_PLL2	DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
 #else