release: Zephyr 1.8.0

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.gitlint

@@ -35,7 +35,7 @@ words=wip,title
 # (e.g. title-must-not-contain-word).
 #regex=^US[0-9]*
 
-[B1]
+[max-line-length-with-exceptions]
 # B1 = body-max-line-length
 line-length=72
 

Makefile

@@ -1,7 +1,7 @@
 VERSION_MAJOR 	   = 1
-VERSION_MINOR 	   = 7
-PATCHLEVEL 	   = 99
-VERSION_RESERVED   = 0
+VERSION_MINOR 	   = 8
+PATCHLEVEL 	   = 0
+VERSION_RESERVED   =
 EXTRAVERSION       =
 NAME 		   = Zephyr Kernel
 
@@ -27,9 +27,11 @@ UNAME := $(shell uname)
 ifeq (MSYS, $(findstring MSYS, $(UNAME)))
 DISABLE_TRYRUN=y
 HOST_OS=MSYS
+NATIVE_PWD_OPT=-W
 else ifeq (MINGW, $(findstring MINGW, $(UNAME)))
 HOST_OS=MINGW
 PWD_OPT=-W
+NATIVE_PWD_OPT=-W
 DISABLE_TRYRUN=y
 CPATH ?= $(MIGW_DIR)/include
 LIBRARY_PATH ?= $(MINGW_DIR)/lib
@@ -39,7 +41,7 @@ HOST_OS=Linux
 else ifeq (Darwin, $(findstring Darwin, $(UNAME)))
 HOST_OS=Darwin
 endif
-export HOST_OS
+export HOST_OS NATIVE_PWD_OPT
 
 # Avoid funny character set dependencies
 unexport LC_ALL
@@ -577,6 +579,17 @@ ifeq ($(dot-config),1)
 # oldconfig if changes are detected.
 -include include/config/auto.conf.cmd
 
+# Read in DTS derived configuration, if it exists
+#
+# We check to see if the ARCH is correctly sourced before doing the -include
+# The reason for this is due to implicit rules kicking in to create this file.
+# If this occurs before the above auto.conf is sourced correctly, the build
+# will iterate over the dts conf file 2-3 times before settling down to the
+# correct output.
+ifneq ($(ARCH),)
+-include include/generated/generated_dts_board.conf
+endif
+
 # To avoid any implicit rule to kick in, define an empty command
 $(KCONFIG_CONFIG) include/config/auto.conf.cmd: ;
 
@@ -950,28 +963,46 @@ zephyr: $(zephyr-deps) $(KERNEL_BIN_NAME)
 ifeq ($(CONFIG_HAS_DTS),y)
 define filechk_generated_dts_board.h
 	(echo "/* WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY! */"; \
-		$(ZEPHYR_BASE)/scripts/extract_dts_includes.py dts/$(ARCH)/$(BOARD_NAME).dts_compiled $(ZEPHYR_BASE)/dts/$(ARCH)/yaml; \
 		if test -e $(ZEPHYR_BASE)/dts/$(ARCH)/$(BOARD_NAME).fixup; then \
-			echo; echo; \
-			echo "/* Following definitions fixup the generated include */"; \
-			echo; \
-			cat $(ZEPHYR_BASE)/dts/$(ARCH)/$(BOARD_NAME).fixup; \
+			$(ZEPHYR_BASE)/scripts/extract_dts_includes.py \
+				-d dts/$(ARCH)/$(BOARD_NAME).dts_compiled \
+				-y $(ZEPHYR_BASE)/dts/$(ARCH)/yaml \
+				-f $(ZEPHYR_BASE)/dts/$(ARCH)/$(BOARD_NAME).fixup; \
+		else \
+			$(ZEPHYR_BASE)/scripts/extract_dts_includes.py \
+				-d dts/$(ARCH)/$(BOARD_NAME).dts_compiled \
+				-y $(ZEPHYR_BASE)/dts/$(ARCH)/yaml; \
 		fi; \
 		)
 endef
+define filechk_generated_dts_board.conf
+	(echo "# WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY!"; \
+		$(ZEPHYR_BASE)/scripts/extract_dts_includes.py \
+		-d dts/$(ARCH)/$(BOARD_NAME).dts_compiled \
+		-y $(ZEPHYR_BASE)/dts/$(ARCH)/yaml -k; \
+		)
+endef
 else
 define filechk_generated_dts_board.h
 	(echo "/* WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY! */";)
 endef
+define filechk_generated_dts_board.conf
+	(echo "# WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY!";)
+endef
 endif
 
-
 include/generated/generated_dts_board.h: include/config/auto.conf FORCE
 ifeq ($(CONFIG_HAS_DTS),y)
 	$(Q)$(MAKE) $(build)=dts/$(ARCH)
 endif
 	$(call filechk,generated_dts_board.h)
 
+include/generated/generated_dts_board.conf: include/config/auto.conf FORCE
+ifeq ($(CONFIG_HAS_DTS),y)
+	$(Q)$(MAKE) $(build)=dts/$(ARCH)
+endif
+	$(call filechk,generated_dts_board.conf)
+
 dts: include/generated/generated_dts_board.h
 
 # The actual objects are generated when descending,
@@ -1088,7 +1119,8 @@ depend dep:
 # Directories & files removed with 'make clean'
 CLEAN_DIRS  += $(MODVERDIR)
 
-CLEAN_FILES += 	include/generated/generated_dts_board.h \
+CLEAN_FILES += 	include/generated/generated_dts_board.conf \
+		include/generated/generated_dts_board.h \
 		.old_version .tmp_System.map .tmp_version \
 		.tmp_* System.map *.lnk *.map *.elf *.lst \
 		*.bin *.hex *.stat *.strip staticIdt.o linker.cmd \

arch/arc/core/sys_fatal_error_handler.c

@@ -37,8 +37,8 @@
  *
  * @return N/A
  */
-FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
-					 const NANO_ESF *pEsf)
+FUNC_NORETURN __weak void _SysFatalErrorHandler(unsigned int reason,
+						const NANO_ESF *pEsf)
 {
 	ARG_UNUSED(pEsf);
 

arch/arm/core/cortex_m/mpu/Kconfig

@@ -24,7 +24,7 @@ config MPU_STACK_GUARD
 config ARM_MPU
 	bool "ARM MPU Support"
 	depends on CPU_HAS_MPU
-	depends on SOC_FAMILY_ARM || SOC_FAMILY_STM32
+	depends on SOC_FAMILY_ARM || SOC_FAMILY_STM32 || SOC_FAMILY_NRF5
 	select ARM_CORE_MPU
 	default n
 	help

arch/arm/core/cortex_m/mpu/arm_mpu.c

@@ -64,7 +64,8 @@ static void _region_init(u32_t index, u32_t region_addr,
 	/* Select the region you want to access */
 	ARM_MPU_DEV->rnr = index;
 	/* Configure the region */
-	ARM_MPU_DEV->rbar = region_addr | REGION_VALID | index;
+	ARM_MPU_DEV->rbar = (region_addr & REGION_BASE_ADDR_MASK)
+				| REGION_VALID | index;
 	ARM_MPU_DEV->rasr = region_attr | REGION_ENABLE;
 }
 

arch/arm/core/cortex_m/mpu/nxp_mpu.c

@@ -13,24 +13,32 @@
 #include <logging/sys_log.h>
 #include <misc/__assert.h>
 
-static inline u8_t _get_num_regions(void)
-{
-	u32_t type = (SYSMPU->CESR & SYSMPU_CESR_NRGD_MASK)
-			>> SYSMPU_CESR_NRGD_SHIFT;
+#define STACK_GUARD_REGION_SIZE 32
 
+/* NXP MPU Enabled state */
+static u8_t nxp_mpu_enabled;
+
+/**
+ * This internal function is utilized by the MPU driver to parse the intent
+ * type (i.e. THREAD_STACK_REGION) and return the correct parameter set.
+ */
+static inline u32_t _get_region_attr_by_type(u32_t type)
+{
 	switch (type) {
-	case 0:
-		return 8;
-	case 1:
-		return 12;
-	case 2:
-		return 16;
+	case THREAD_STACK_REGION:
+		return 0;
+	case THREAD_STACK_GUARD_REGION:
+		/* The stack guard region has to be not accessible */
+		return REGION_RO_ATTR;
 	default:
-		__ASSERT(0, "Unsupported MPU configuration.");
+		/* Size 0 region */
 		return 0;
 	}
+}
 
-	return NXP_MPU_REGION_NUMBER;
+static inline u8_t _get_num_regions(void)
+{
+	return FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT;
 }
 
 static void _region_init(u32_t index, u32_t region_base,
@@ -48,6 +56,108 @@ static void _region_init(u32_t index, u32_t region_base,
 		    SYSMPU->WORD[index][3]);
 }
 
+/* ARM Core MPU Driver API Implementation for NXP MPU */
+
+/**
+ * @brief enable the MPU
+ */
+void arm_core_mpu_enable(void)
+{
+	if (nxp_mpu_enabled == 0) {
+		/* Enable MPU */
+		SYSMPU->CESR |= SYSMPU_CESR_VLD_MASK;
+
+		nxp_mpu_enabled = 1;
+	}
+}
+
+/**
+ * @brief disable the MPU
+ */
+void arm_core_mpu_disable(void)
+{
+	if (nxp_mpu_enabled == 1) {
+		/* Disable MPU */
+		SYSMPU->CESR &= ~SYSMPU_CESR_VLD_MASK;
+		/* Clear Interrupts */
+		SYSMPU->CESR |=  SYSMPU_CESR_SPERR_MASK;
+
+		nxp_mpu_enabled = 0;
+	}
+}
+
+/**
+ * @brief configure the base address and size for an MPU region
+ *
+ * @param   type    MPU region type
+ * @param   base    base address in RAM
+ * @param   size    size of the region
+ */
+void arm_core_mpu_configure(u8_t type, u32_t base, u32_t size)
+{
+	SYS_LOG_DBG("Region info: 0x%x 0x%x", base, size);
+	/*
+	 * The new MPU regions are are allocated per type after the statically
+	 * configured regions.
+	 */
+	u32_t region_index = mpu_config.num_regions + type;
+	u32_t region_attr = _get_region_attr_by_type(type);
+	u32_t last_region = _get_num_regions() - 1;
+
+	/*
+	 * The NXP MPU manages the permissions of the overlapping regions
+	 * doing the logic OR in between them, hence they can't be used
+	 * for stack/stack guard protection. For this reason the last region of
+	 * the MPU will be reserved.
+	 *
+	 * A consequence of this is that the SRAM is splitted in different
+	 * regions. In example if THREAD_STACK_GUARD_REGION is selected:
+	 * - SRAM before THREAD_STACK_GUARD_REGION: RW
+	 * - SRAM THREAD_STACK_GUARD_REGION: RO
+	 * - SRAM after THREAD_STACK_GUARD_REGION: RW
+	 */
+	/* NXP MPU supports up to 16 Regions */
+	if (region_index > _get_num_regions() - 2) {
+		return;
+	}
+
+	/* Configure SRAM_0 region */
+	/*
+	 * The mpu_config.sram_region contains the index of the region in
+	 * the mpu_config.mpu_regions array but the region 0 on the NXP MPU
+	 * is the background region, so on this MPU the regions are mapped
+	 * starting from 1, hence the mpu_config.sram_region on the data
+	 * structure is mapped on the mpu_config.sram_region + 1 region of
+	 * the MPU.
+	 */
+	_region_init(mpu_config.sram_region + 1,
+		     mpu_config.mpu_regions[mpu_config.sram_region].base,
+		     ENDADDR_ROUND(base),
+		     mpu_config.mpu_regions[mpu_config.sram_region].attr);
+
+	switch (type) {
+	case THREAD_STACK_REGION:
+		break;
+	case THREAD_STACK_GUARD_REGION:
+		_region_init(region_index, base,
+			     ENDADDR_ROUND(base + STACK_GUARD_REGION_SIZE),
+			     region_attr);
+		break;
+	default:
+		break;
+	}
+
+	/* Configure SRAM_1 region */
+	_region_init(last_region,
+		     base + STACK_GUARD_REGION_SIZE,
+		     ENDADDR_ROUND(
+			    mpu_config.mpu_regions[mpu_config.sram_region].end),
+		     mpu_config.mpu_regions[mpu_config.sram_region].attr);
+
+}
+
+/* NXP MPU Driver Initial Setup */
+
 /*
  * @brief MPU default configuration
  *
@@ -75,6 +185,12 @@ static void _nxp_mpu_config(void)
 	/* Disable Region 0 */
 	SYSMPU->WORD[0][2] = 0;
 
+	SYS_LOG_DBG("[0] 0x%08x 0x%08x 0x%08x 0x%08x",
+		    SYSMPU->WORD[0][0],
+		    SYSMPU->WORD[0][1],
+		    SYSMPU->WORD[0][2],
+		    SYSMPU->WORD[0][3]);
+
 	/*
 	 * Configure regions:
 	 * r_index starts from 0 but is passed to region_init as r_index + 1,
@@ -90,6 +206,8 @@ static void _nxp_mpu_config(void)
 	/* Enable MPU */
 	SYSMPU->CESR |= SYSMPU_CESR_VLD_MASK;
 
+	nxp_mpu_enabled = 1;
+
 	/* Make sure that all the registers are set before proceeding */
 	__DSB();
 	__ISB();

arch/arm/core/cortex_m/vector_table.S

@@ -47,7 +47,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
     .word __reserved
     .word __reserved
     .word __reserved
-    .word __reserved	/* SVC not used for now (PendSV used instead) */
+    .word __svc
     .word __reserved
 #elif defined(CONFIG_ARMV7_M)
     .word __mpu_fault

arch/arm/core/cortex_m/vector_table.h

@@ -39,6 +39,7 @@ GTEXT(__reset)
 GTEXT(__nmi)
 GTEXT(__hard_fault)
 #if defined(CONFIG_ARMV6_M)
+GTEXT(__svc)
 #elif defined(CONFIG_ARMV7_M)
 GTEXT(__mpu_fault)
 GTEXT(__bus_fault)

arch/arm/core/exc_exit.S

@@ -24,7 +24,7 @@ _ASM_FILE_PROLOGUE
 GTEXT(_ExcExit)
 GTEXT(_IntExit)
 GDATA(_kernel)
-#ifdef CONFIG_TICKLESS_KERNEL
+#ifdef CONFIG_TIMESLICING
 GTEXT(_update_time_slice_before_swap)
 #endif
 
@@ -58,10 +58,15 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _IntExit)
 
 /* _IntExit falls through to _ExcExit (they are aliases of each other) */
 
-#ifdef CONFIG_TICKLESS_KERNEL
+#ifdef CONFIG_TIMESLICING
     push {lr}
     bl _update_time_slice_before_swap
+#if defined(CONFIG_ARMV6_M)
+    pop {r0}
+    mov lr, r0
+#else
     pop {lr}
+#endif /* CONFIG_ARMV6_M */
 #endif
 
 /**

arch/arm/core/irq_offload.c

@@ -22,9 +22,17 @@ void _irq_do_offload(void)
 
 void irq_offload(irq_offload_routine_t routine, void *parameter)
 {
-	int key;
+#if defined(CONFIG_ARMV6_M) && defined(CONFIG_ASSERT)
+	/* Cortex M0 hardfaults if you make a SVC call with interrupts
+	 * locked.
+	 */
+	unsigned int key;
 
-	key = irq_lock();
+	__asm__ volatile("mrs %0, PRIMASK;" : "=r" (key) : : "memory");
+	__ASSERT(key == 0, "irq_offload called with interrupts locked\n");
+#endif
+
+	k_sched_lock();
 	offload_routine = routine;
 	offload_param = parameter;
 
@@ -34,6 +42,5 @@ void irq_offload(irq_offload_routine_t routine, void *parameter)
 			  : "memory");
 
 	offload_routine = NULL;
-
-	irq_unlock(key);
+	k_sched_unlock();
 }

arch/arm/core/swap.S

@@ -20,12 +20,7 @@
 _ASM_FILE_PROLOGUE
 
 GTEXT(__swap)
-#if defined(CONFIG_ARMV6_M)
-#elif defined(CONFIG_ARMV7_M)
 GTEXT(__svc)
-#else
-#error Unknown ARM architecture
-#endif /* CONFIG_ARMV6_M */
 GTEXT(__pendsv)
 GTEXT(_do_kernel_oops)
 GDATA(_k_neg_eagain)
@@ -47,24 +42,17 @@ GDATA(_kernel)
 
 SECTION_FUNC(TEXT, __pendsv)
 
-#if defined (CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH) || \
-		defined(CONFIG_STACK_SENTINEL)
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH
     /* Register the context switch */
     push {lr}
-
-#ifdef CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH
     bl _sys_k_event_logger_context_switch
-#endif
-#ifdef CONFIG_STACK_SENTINEL
-    bl _check_stack_sentinel
-#endif
 #if defined(CONFIG_ARMV6_M)
     pop {r0}
     mov lr, r0
 #else
     pop {lr}
 #endif /* CONFIG_ARMV6_M */
-#endif /* CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH || CONFIG_STACK_SENTINEL */
+#endif /* CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH  */
 
     /* load _kernel into r1 and current k_thread into r2 */
     ldr r1, =_kernel
@@ -217,6 +205,52 @@ _thread_irq_disabled:
     bx lr
 
 #if defined(CONFIG_ARMV6_M)
+SECTION_FUNC(TEXT, __svc)
+    /* Use EXC_RETURN state to find out if stack frame is on the
+     * MSP or PSP
+     */
+    ldr r0, =0x4
+    mov r1, lr
+    tst r1, r0
+    beq _stack_frame_msp
+    mrs r0, PSP
+    bne _stack_frame_endif
+_stack_frame_msp:
+    mrs r0, MSP
+_stack_frame_endif:
+
+    /* Figure out what SVC call number was invoked */
+    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
+    /* SVC is a two-byte instruction, point to it and read  encoding */
+    subs r1, r1, #2
+    ldrb r1, [r1, #0]
+
+   /*
+    * grab service call number:
+    * 1: irq_offload (if configured)
+    * 2: kernel panic or oops (software generated fatal exception)
+    * Planned implementation of system calls for memory protection will
+    * expand this case.
+    */
+
+    cmp r1, #2
+    beq _oops
+
+#if CONFIG_IRQ_OFFLOAD
+    push {lr}
+    blx _irq_do_offload  /* call C routine which executes the offload */
+    pop {r3}
+    mov lr, r3
+#endif
+
+    /* exception return is done in _IntExit() */
+    b _IntExit
+
+_oops:
+    push {lr}
+    blx _do_kernel_oops
+    pop {pc}
+
 #elif defined(CONFIG_ARMV7_M)
 /**
  *

arch/arm/core/sys_fatal_error_handler.c

@@ -38,12 +38,17 @@
  *
  * @return N/A
  */
-void _SysFatalErrorHandler(unsigned int reason,
+void __weak _SysFatalErrorHandler(unsigned int reason,
 					 const NANO_ESF *pEsf)
 {
 	ARG_UNUSED(pEsf);
 
 #if !defined(CONFIG_SIMPLE_FATAL_ERROR_HANDLER)
+#ifdef CONFIG_STACK_SENTINEL
+	if (reason == _NANO_ERR_STACK_CHK_FAIL) {
+		goto hang_system;
+	}
+#endif
 	if (reason == _NANO_ERR_KERNEL_PANIC) {
 		goto hang_system;
 	}

arch/arm/soc/atmel_sam/sam4s/Kconfig.defconfig.series

@@ -25,6 +25,6 @@ config NUM_IRQS
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	int
-	default 84000000
+	default 120000000
 
 endif # SOC_SERIES_SAM4S

arch/arm/soc/atmel_sam/sam4s/Kconfig.soc

@@ -45,18 +45,9 @@ config SOC_ATMEL_SAM4S_EXT_MAINCK
 	Says n here will use the internal fast RC oscillator
 	running at 12 MHz.
 
-config SOC_ATMEL_SAM4S_MDIV
-	int "MDIV"
-	default 1
-	range 1 4
-	help
-	This divisor defines a ratio between processor clock (HCLK)
-	and master clock (MCK):
-	MCK = HCLK / MDIV
-
 config SOC_ATMEL_SAM4S_PLLA_MULA
 	hex "PLL MULA"
-	default 0x06
+	default 0x09
 	help
 	This is the multiplier (MULA) used by the PLL.
 	The processor clock is (MAINCK * (MULA + 1) / DIVA).
@@ -64,8 +55,8 @@ config SOC_ATMEL_SAM4S_PLLA_MULA
 	Board config file can override this settings
 	for a particular board.
 
-	With default of MULA == 6, and DIVA == 1,
-	PLL is running at 7 times of main clock.
+	With default of MULA == 9, and DIVA == 1,
+	PLL is running at 10 times of main clock.
 
 config SOC_ATMEL_SAM4S_PLLA_DIVA
 	hex "PLL DIVA"
@@ -77,8 +68,8 @@ config SOC_ATMEL_SAM4S_PLLA_DIVA
 	Board config file can override this settings
 	for a particular board.
 
-	With default of MULA == 6, and DIVA == 1,
-	PLL is running at 7 times of main clock.
+	With default of MULA == 9, and DIVA == 1,
+	PLL is running at 10 times of main clock.
 
 config SOC_ATMEL_SAM4S_WAIT_MODE
 	bool "Atmel SAM4S goes to Wait mode instead of Sleep mode"
@@ -89,30 +80,4 @@ config SOC_ATMEL_SAM4S_WAIT_MODE
 	to achieve this, make CPU go to Wait mode instead of Sleep
 	mode while using external crystal oscillator for main clock.
 
-config SOC_ATMEL_SAM4S_PLLB_MULB
-	hex "PLL MULB"
-	default 0x03
-	help
-	This is the multiplier (MULA) used by the PLL.
-	The processor clock is (MAINCK * (MULA + 1) / DIVA).
-
-	Board config file can override this settings
-	for a particular board.
-
-	With default of MULA == 6, and DIVA == 1,
-	PLL is running at 7 times of main clock.
-
-config SOC_ATMEL_SAM4S_PLLB_DIVB
-	hex "PLL DIVB"
-	default 0x01
-	help
-	This is the divider (DIVB) used by the PLL.
-	The processor clock is (MAINCK * (MULB + 1) / DIVB).
-
-	Board config file can override this settings
-	for a particular board.
-
-	With default of MULB == 6, and DIVB == 1,
-	PLL is running at 7 times of main clock.
-
 endif # SOC_SERIES_SAM4S

arch/arm/soc/atmel_sam/sam4s/soc.c

@@ -17,52 +17,9 @@
 #include <device.h>
 #include <init.h>
 #include <soc.h>
-
 #include <arch/cpu.h>
 #include <cortex_m/exc.h>
 
-/*
- * PLL clock = Main * (MULA + 1) / DIVA
- *
- * By default, MULA == 6, DIVA == 1.
- * With main crystal running at 12 MHz,
- * PLL = 12 * (6 + 1) / 1 = 84 MHz
- *
- * With processor clock prescaler at 1,
- * the processor clock is at 84 MHz.
- */
-#define PMC_CKGR_PLLAR_MULA	\
-	((CONFIG_SOC_ATMEL_SAM4S_PLLA_MULA) << 16)
-#define PMC_CKGR_PLLAR_DIVA	\
-	((CONFIG_SOC_ATMEL_SAM4S_PLLA_DIVA) << 0)
-
-/*
- * PLL clock = Main * (MULB + 1) / DIVB
- *
- * By default, MULB == 6, DIVB == 1.
- * With main crystal running at 12 MHz,
- * PLL = 12 * (6 + 1) / 1 = 84 MHz
- *
- * With processor clock prescaler at 1,
- * the processor clock is at 84 MHz.
- */
-#define PMC_CKGR_PLLBR_MULB	\
-	((CONFIG_SOC_ATMEL_SAM4S_PLLB_MULB) << 16)
-#define PMC_CKGR_PLLBR_DIVB	\
-	((CONFIG_SOC_ATMEL_SAM4S_PLLB_DIVB) << 0)
-
-#if CONFIG_SOC_ATMEL_SAM4S_MDIV == 1
-#define SOC_ATMEL_SAM4S_MDIV PMC_MCKR_MDIV_EQ_PCK
-#elif CONFIG_SOC_ATMEL_SAM4S_MDIV == 2
-#define SOC_ATMEL_SAM4S_MDIV PMC_MCKR_MDIV_PCK_DIV2
-#elif CONFIG_SOC_ATMEL_SAM4S_MDIV == 3
-#define SOC_ATMEL_SAM4S_MDIV PMC_MCKR_MDIV_PCK_DIV3
-#elif CONFIG_SOC_ATMEL_SAM4S_MDIV == 4
-#define SOC_ATMEL_SAM4S_MDIV PMC_MCKR_MDIV_PCK_DIV4
-#else
-#error "Invalid CONFIG_SOC_ATMEL_SAM4S_MDIV define value"
-#endif
-
 /**
  * @brief Setup various clock on SoC at boot time.
  *
@@ -77,11 +34,12 @@ static ALWAYS_INLINE void clock_init(void)
 
 #ifdef CONFIG_SOC_ATMEL_SAM4S_EXT_SLCK
 	/* Switch slow clock to the external 32 KHz crystal oscillator. */
-	SUPC->SUPC_CR = SUPC_CR_KEY | SUPC_CR_XTALSEL;
+	SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL;
 
 	/* Wait for oscillator to be stabilized. */
-	while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL))
+	while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) {
 		;
+	}
 
 #endif /* CONFIG_SOC_ATMEL_SAM4S_EXT_SLCK */
 
@@ -93,67 +51,74 @@ static ALWAYS_INLINE void clock_init(void)
 	/* Start the external crystal oscillator. */
 	PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
 			/* Fast RC oscillator frequency is at 4 MHz. */
-			| CKGR_MOR_MOSCRCF_4MHz
+			| CKGR_MOR_MOSCRCF_4_MHz
 			/*
 			 * We select maximum setup time. While start up time
 			 * could be shortened this optimization is not deemed
 			 * critical right now.
 			 */
 			| CKGR_MOR_MOSCXTST(0xFFu)
-			/* RC OSC must stay on. */
-			| PMC_CKGR_MOR_MOSCRCEN
-			| PMC_CKGR_MOR_MOSCXTEN;
+			/* RC oscillator must stay on. */
+			| CKGR_MOR_MOSCRCEN
+			| CKGR_MOR_MOSCXTEN;
 
 	/* Wait for oscillator to be stabilized. */
-	while (!(PMC->PMC_SR & PMC_SR_MOSCXTS))
+	while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
 		;
+	}
 
 	/* Select the external crystal oscillator as the main clock source. */
-	PMC->CKGR_MOR = PMC_CKGR_MOR_KEY
-			| PMC_CKGR_MOR_MOSCRCF_4MHZ
-			| PMC_CKGR_MOR_MOSCRCEN
-			| PMC_CKGR_MOR_MOSCXTEN
-			| PMC_CKGR_MOR_MOSCXTST
-			| PMC_CKGR_MOR_MOSCSEL;
+	PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
+			| CKGR_MOR_MOSCRCF_4_MHz
+			| CKGR_MOR_MOSCRCEN
+			| CKGR_MOR_MOSCXTEN
+			| CKGR_MOR_MOSCXTST(0xFFu)
+			| CKGR_MOR_MOSCSEL;
 
 	/* Wait for external oscillator to be selected. */
-	while (!(PMC->PMC_SR & PMC_INT_MOSCSELS))
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
 		;
+	}
 
-	/* Turn off RC OSC, not used any longer, to save power */
+	/* Turn off RC oscillator, not used any longer, to save power */
 	PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
 			| CKGR_MOR_MOSCSEL
 			| CKGR_MOR_MOSCXTST(0xFFu)
 			| CKGR_MOR_MOSCXTEN;
 
 	/* Wait for the RC oscillator to be turned off. */
-	while (PMC->PMC_SR & PMC_SR_MOSCRCS)
+	while (PMC->PMC_SR & PMC_SR_MOSCRCS) {
 		;
+	}
 
 #ifdef CONFIG_SOC_ATMEL_SAM4S_WAIT_MODE
 	/*
 	 * Instruct CPU to enter Wait mode instead of Sleep mode to
 	 * keep Processor Clock (HCLK) and thus be able to debug
-	 * CPU using JTAG
+	 * CPU using JTAG.
 	 */
 	PMC->PMC_FSMR |= PMC_FSMR_LPM;
 #endif
 #else
-	/*
-	 * Set main fast RC oscillator.
-	 */
+	/* Setup main fast RC oscillator. */
 
 	/*
-	 * NOTE: MOSCREF must be changed only if MOSCRCS is set in the PMC_SR
+	 * NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR
 	 * register, should normally be the case.
 	 */
+	while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
+		;
+	}
+
+	/* Set main fast RC oscillator to 12 MHz. */
 	PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
-			| CKGR_MOR_MOSCRCF_12MHZ
+			| CKGR_MOR_MOSCRCF_12_MHz
 			| CKGR_MOR_MOSCRCEN;
 
 	/* Wait for RC oscillator to stabilize. */
-	while (!(PMC->PMC_SR & PMC_SR_MOSCRCS))
+	while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
 		;
+	}
 #endif /* CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK */
 
 	/*
@@ -165,14 +130,15 @@ static ALWAYS_INLINE void clock_init(void)
 	PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK;
 
 	/* Wait for clock selection to complete. */
-	while (!(PMC->PMC_SR & PMC_SR_MCKRDY))
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
 		;
+	}
 
 	/* Setup PLLA. */
 	PMC->CKGR_PLLAR = CKGR_PLLAR_ONE
-			  | PMC_CKGR_PLLAR_MULA
+			  | CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAM4S_PLLA_MULA)
 			  | CKGR_PLLAR_PLLACOUNT(0x3Fu)
-			  | PMC_CKGR_PLLAR_DIVA;
+			  | CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAM4S_PLLA_DIVA);
 
 	/*
 	 * NOTE: Both MULA and DIVA must be set to a value greater than 0 or
@@ -181,23 +147,9 @@ static ALWAYS_INLINE void clock_init(void)
 	 */
 
 	/* Wait for PLL lock. */
-	while (!(PMC->PMC_SR & PMC_SR_LOCKA))
-		;
-
-	/* Setup PLLB. */
-	PMC->CKGR_PLLBR = PMC_CKGR_PLLBR_MULB
-			  | CKGR_PLLBR_PLLBCOUNT(0x3Fu)
-			  | PMC_CKGR_PLLBR_DIVB;
-
-	/*
-	 * NOTE: Both MULB and DIVB must be set to a value greater than 0 or
-	 * otherwise PLL will be disabled. In this case we would get stuck in
-	 * the following loop.
-	 */
-
-	/* Wait for PLL lock. */
-	while (!(PMC->PMC_SR & PMC_SR_LOCKB))
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
 		;
+	}
 
 	/*
 	 * Final setup of the Master Clock
@@ -205,7 +157,7 @@ static ALWAYS_INLINE void clock_init(void)
 
 	/*
 	 * NOTE: PMC_MCKR must not be programmed in a single write operation.
-	 * If CSS, MDIV or PRES are modified we must wait for MCKRDY bit to be
+	 * If CSS or PRES are modified we must wait for MCKRDY bit to be
 	 * set again.
 	 */
 
@@ -214,24 +166,18 @@ static ALWAYS_INLINE void clock_init(void)
 	PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1;
 
 	/* Wait for Master Clock setup to complete */
-	while (!(PMC->PMC_SR & PMC_SR_MCKRDY))
-		;
-
-	/* Setup divider - Processor Clock (HCLK) / Master Clock (MCK). */
-	reg_val = PMC->PMC_MCKR & ~PMC_MCKR_MDIV_Msk;
-	PMC->PMC_MCKR = reg_val | SOC_ATMEL_SAM4S_MDIV;
-
-	/* Wait for Master Clock setup to complete. */
-	while (!(PMC->PMC_SR & PMC_SR_MCKRDY))
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
 		;
+	}
 
 	/* Finally select PLL as Master Clock source. */
 	reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
 	PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK;
 
 	/* Wait for Master Clock setup to complete. */
-	while (!(PMC->PMC_SR & PMC_SR_MCKRDY))
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
 		;
+	}
 }
 
 /**
@@ -255,14 +201,16 @@ static int atmel_sam4s_init(struct device *arg)
 
 	/*
 	 * Set FWS (Flash Wait State) value before increasing Master Clock
-	 * (MCK) frequency.
-	 * TODO: set FWS based on the actual MCK frequency and VDDIO value
-	 * rather than maximum supported 150 MHz at standard VDDIO=2.7V
+	 * (MCK) frequency. Look at table 44.73 in the SAM4S datasheet.
+	 * This is set to the highest number of read cycles because it won't
+	 * hurt lower clock frequencies. However, a high frequency with too
+	 * few read cycles could cause flash read problems. FWS 5 (6 cycles)
+	 * is the safe setting for all of this SoCs usable frequencies.
+	 * TODO: Add code to handle SAM4SD devices that have 2 EFCs.
 	 */
-	EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
-	EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
+	EFC0->EEFC_FMR = EEFC_FMR_FWS(5);
 
-	/* Setup master clock */
+	/* Setup system clocks. */
 	clock_init();
 
 	/*

arch/arm/soc/atmel_sam/sam4s/soc.h

@@ -36,7 +36,6 @@
 #define SOC_ATMEL_SAM_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
 
 /** Master Clock (MCK) Frequency */
-#define SOC_ATMEL_SAM_MCK_FREQ_HZ \
-		(SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM4S_MDIV)
+#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ
 
 #endif /* _ATMEL_SAM4S_SOC_H_ */

arch/arm/soc/atmel_sam/sam4s/soc_pinmap.h

@@ -10,21 +10,21 @@
  * modules to correctly configure GPIO controller.
  */
 
-#ifndef _ATMEL_SAM_SOC_PINMAP_H_
-#define _ATMEL_SAM_SOC_PINMAP_H_
+#ifndef _ATMEL_SAM4S_SOC_PINMAP_H_
+#define _ATMEL_SAM4S_SOC_PINMAP_H_
 
 #include <soc.h>
 
 /* Universal Asynchronous Receiver Transmitter (UART) */
 
-#define PIN_UART0_RXD {PIO_PA9A_UART0_URXD0,  PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
-#define PIN_UART0_TXD {PIO_PA10A_UART0_UTXD0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
+#define PIN_UART0_RXD {PIO_PA9A_URXD0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
+#define PIN_UART0_TXD {PIO_PA10A_UTXD0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
 
 #define PINS_UART0 {PIN_UART0_RXD, PIN_UART0_TXD}
 
-#define PIN_UART1_RXD {PIO_PB2A_UART1_URXD1,  PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
-#define PIN_UART1_TXD {PIO_PB3A_UART1_UTXD1,  PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
+#define PIN_UART1_RXD {PIO_PB2A_URXD1, PIOB, ID_PIOB, SOC_GPIO_FUNC_A}
+#define PIN_UART1_TXD {PIO_PB3A_UTXD1, PIOB, ID_PIOB, SOC_GPIO_FUNC_A}
 
 #define PINS_UART1 {PIN_UART1_RXD, PIN_UART1_TXD}
 
-#endif /* _ATMEL_SAM_SOC_PINMAP_H_ */
+#endif /* _ATMEL_SAM4S_SOC_PINMAP_H_ */

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.series

@@ -10,6 +10,7 @@ config  SOC_SERIES_NRF52X
 	select CPU_CORTEX_M
 	select CPU_CORTEX_M4
 	select CPU_HAS_FPU
+	select CPU_HAS_MPU
 	select SOC_FAMILY_NRF5
 	select NRF_RTC_TIMER
 	select CLOCK_CONTROL

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.soc

@@ -26,3 +26,11 @@ config SOC_NRF52840_QIAA
 	select SOC_NRF52840
 
 endchoice
+
+config ARM_MPU_NRF52X
+	bool "Enable MPU on nRF52"
+	depends on CPU_HAS_MPU
+	select ARM_MPU
+	default n
+	help
+	  Enable MPU support on Nordic Semiconductor nRF52x series ICs.

arch/arm/soc/nordic_nrf5/nrf52/Makefile

@@ -10,6 +10,7 @@ soc-cflags += -DNRF52840_XXAA
 endif
 
 obj-y += soc.o
+obj-$(CONFIG_ARM_MPU_NRF52X) += mpu_regions.o
 
 zephyr: $(KERNEL_HEX_NAME)
 all: $(KERNEL_HEX_NAME)

arch/arm/soc/nordic_nrf5/nrf52/mpu_mem_cfg.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _NRF52X_MPU_MEM_CFG_H_
+#define _NRF52X_MPU_MEM_CFG_H_
+
+#include <soc.h>
+#include <arch/arm/cortex_m/mpu/arm_mpu.h>
+
+/* Flash Region Definitions */
+#if CONFIG_FLASH_SIZE == 64
+#define REGION_FLASH_SIZE REGION_64K
+#elif CONFIG_FLASH_SIZE == 128
+#define REGION_FLASH_SIZE REGION_128K
+#elif CONFIG_FLASH_SIZE == 256
+#define REGION_FLASH_SIZE REGION_256K
+#elif CONFIG_FLASH_SIZE == 512
+#define REGION_FLASH_SIZE REGION_512K
+#elif CONFIG_FLASH_SIZE == 1024
+#define REGION_FLASH_SIZE REGION_1M
+#elif CONFIG_FLASH_SIZE == 2048
+#define REGION_FLASH_SIZE REGION_2M
+#else
+#error "Unsupported configuration"
+#endif
+
+/* SRAM Region Definitions */
+#if CONFIG_SRAM_SIZE == 32
+#define REGION_SRAM_0_SIZE REGION_32K
+#elif CONFIG_SRAM_SIZE == 64
+#define REGION_SRAM_0_SIZE REGION_64K
+#elif CONFIG_SRAM_SIZE == 128
+#define REGION_SRAM_0_SIZE REGION_128K
+#elif CONFIG_SRAM_SIZE == 256
+#define REGION_SRAM_0_SIZE REGION_256K
+#else
+#error "Unsupported configuration"
+#endif
+
+#endif /* _NRF52X_MPU_MEM_CFG_H_ */

arch/arm/soc/nordic_nrf5/nrf52/mpu_regions.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <arch/arm/cortex_m/mpu/arm_mpu.h>
+
+#include "mpu_mem_cfg.h"
+
+#define XICR_BASE	0x10000000
+#define PERIPH_BASE	0x40000000
+#define M4_PPB_BASE	0xE0000000
+
+static struct arm_mpu_region mpu_regions[] = {
+	/* Region 0 */
+	MPU_REGION_ENTRY("FLASH_0",
+			 CONFIG_FLASH_BASE_ADDRESS,
+			 REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
+	/* Region 1 */
+	MPU_REGION_ENTRY("SRAM_0",
+			 CONFIG_SRAM_BASE_ADDRESS,
+			 REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
+	/* Region 2 */
+	MPU_REGION_ENTRY("FACTUSERCFG_0",
+			 XICR_BASE,
+			 REGION_IO_ATTR(REGION_8K)),
+	/* Region 3 */
+	MPU_REGION_ENTRY("PERIPH_0",
+			 PERIPH_BASE,
+			 REGION_IO_ATTR(REGION_512M)),
+	/* Region 4 */
+	MPU_REGION_ENTRY("PPB_0",
+			 M4_PPB_BASE,
+			 REGION_PPB_ATTR(REGION_64K)),
+};
+
+struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};

arch/arm/soc/nxp_kinetis/k6x/nxp_mpu_regions.c

@@ -46,4 +46,5 @@ static struct nxp_mpu_region mpu_regions[] = {
 struct nxp_mpu_config mpu_config = {
 	.num_regions = ARRAY_SIZE(mpu_regions),
 	.mpu_regions = mpu_regions,
+	.sram_region = 3,
 };

arch/nios2/core/exception.S

@@ -18,6 +18,9 @@ GTEXT(__swap)
 GTEXT(_irq_do_offload)
 GTEXT(_offload_routine)
 #endif
+#ifdef CONFIG_TIMESLICING
+GTEXT(_update_time_slice_before_swap)
+#endif
 
 /* Allows use of r1/at register, otherwise reserved for assembler use */
 .set noat
@@ -145,6 +148,10 @@ on_irq_stack:
 	 */
 	ldw sp, 0(sp)
 
+#ifdef CONFIG_TIMESLICING
+	call _update_time_slice_before_swap
+#endif
+
 	/* Argument to Swap() is estatus since that's the state of the
 	 * status register before the exception happened. When coming
 	 * out of the context switch we need this info to restore

arch/nios2/core/fatal.c

@@ -220,12 +220,17 @@ FUNC_NORETURN void _Fault(const NANO_ESF *esf)
  *
  * @return N/A
  */
-FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
-					 const NANO_ESF *pEsf)
+FUNC_NORETURN __weak void _SysFatalErrorHandler(unsigned int reason,
+						const NANO_ESF *pEsf)
 {
 	ARG_UNUSED(pEsf);
 
 #if !defined(CONFIG_SIMPLE_FATAL_ERROR_HANDLER)
+#ifdef CONFIG_STACK_SENTINEL
+	if (reason == _NANO_ERR_STACK_CHK_FAIL) {
+		goto hang_system;
+	}
+#endif
 	if (reason == _NANO_ERR_KERNEL_PANIC) {
 		goto hang_system;
 	}

arch/nios2/core/swap.S

@@ -59,12 +59,6 @@ SECTION_FUNC(exception.other, __swap)
 
 #if CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH
 	call _sys_k_event_logger_context_switch
-#endif
-#ifdef CONFIG_STACK_SENTINEL
-	call _check_stack_sentinel
-#endif
-#if defined(CONFIG_STACK_SENTINEL) || \
-		defined (CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH)
 	/* restore caller-saved r10 */
 	movhi r10, %hi(_kernel)
 	ori   r10, r10, %lo(_kernel)

arch/riscv32/core/fatal.c

@@ -134,11 +134,17 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
  *
  * @return N/A
  */
-void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF *esf)
+FUNC_NORETURN __weak void _SysFatalErrorHandler(unsigned int reason,
+						const NANO_ESF *esf)
 {
 	ARG_UNUSED(esf);
 
 #if !defined(CONFIG_SIMPLE_FATAL_ERROR_HANDLER)
+#ifdef CONFIG_STACK_SENTINEL
+	if (reason == _NANO_ERR_STACK_CHK_FAIL) {
+		goto hang_system;
+	}
+#endif
 	if (reason == _NANO_ERR_KERNEL_PANIC) {
 		goto hang_system;
 	}

arch/riscv32/core/isr.S

@@ -37,6 +37,10 @@ GTEXT(_sys_k_event_logger_interrupt)
 GTEXT(_offload_routine)
 #endif
 
+#ifdef CONFIG_TIMESLICING
+GTEXT(_update_time_slice_before_swap)
+#endif
+
 /* exports */
 GTEXT(__irq_wrapper)
 
@@ -270,15 +274,15 @@ on_thread_stack:
 	addi t2, t2, -1
 	sw t2, _kernel_offset_to_nested(t1)
 
+	/* Restore thread stack pointer */
+	lw t0, 0x00(sp)
+	addi sp, t0, 0
+
 #ifdef CONFIG_STACK_SENTINEL
 	call _check_stack_sentinel
 	la t1, _kernel
 #endif
 
-	/* Restore thread stack pointer */
-	lw t0, 0x00(sp)
-	addi sp, t0, 0
-
 #ifdef CONFIG_PREEMPT_ENABLED
 	/*
 	 * Check if we need to perform a reschedule
@@ -306,12 +310,12 @@ on_thread_stack:
 #endif /* CONFIG_PREEMPT_ENABLED */
 
 reschedule:
+#if CONFIG_TIMESLICING
+	call _update_time_slice_before_swap
+#endif
 #if CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH
 	call _sys_k_event_logger_context_switch
 #endif /* CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH */
-#ifdef CONFIG_STACK_SENTINEL
-	call _check_stack_sentinel
-#endif
 	/* Get reference to _kernel */
 	la t0, _kernel
 

arch/x86/Makefile.idt

@@ -5,7 +5,7 @@ else
 endif
 
 ifeq ($(PREBUILT_HOST_TOOLS),)
-	GENIDT := $(ZEPHYR_BASE)/scripts/gen_idt/gen_idt
+	GENIDT := scripts/gen_idt/gen_idt
 else
 	GENIDT := $(PREBUILT_HOST_TOOLS)/gen_idt
 endif
@@ -29,7 +29,7 @@ quiet_cmd_gen_idt = SIDT    $@
 )
 
 $(GENIDT):
-	$(Q)$(MAKE) $(build)=$(ZEPHYR_BASE)/scripts/gen_idt
+	$(Q)$(MAKE) $(build)=scripts/gen_idt
 
 staticIdt.o: $(PREBUILT_KERNEL) $(GENIDT)
 	$(call cmd,gen_idt)

arch/x86/core/intstub.S

@@ -30,7 +30,7 @@
 	/* externs */
 
 	GTEXT(__swap)
-#if defined(CONFIG_TICKLESS_KERNEL) && defined(CONFIG_TIMESLICING)
+#if defined(CONFIG_TIMESLICING)
 	GTEXT(_update_time_slice_before_swap)
 #endif
 
@@ -340,8 +340,11 @@ alreadyOnIntStack:
 	popl	%esi
 #endif
 
-#if defined(CONFIG_TICKLESS_KERNEL) && defined(CONFIG_TIMESLICING)
+#if defined(CONFIG_TIMESLICING)
 	call	_update_time_slice_before_swap
+#endif
+#ifdef CONFIG_STACK_SENTINEL
+	call	_check_stack_sentinel
 #endif
 	pushfl			/* push KERNEL_LOCK_KEY argument */
 #ifdef CONFIG_X86_IAMCU
@@ -398,8 +401,9 @@ noReschedule:
 	popl	%esp		/* pop thread stack pointer */
 
 #ifdef CONFIG_STACK_SENTINEL
-	call _check_stack_sentinel
+	call	_check_stack_sentinel
 #endif
+
 	/* fall through to 'nestedInterrupt' */
 
 

arch/x86/core/swap.S

@@ -27,9 +27,6 @@
 
 	/* externs */
 	GDATA(_k_neg_eagain)
-#ifdef CONFIG_STACK_SENTINEL
-	GTEXT(_check_stack_sentinel)
-#endif
 
 /**
  *
@@ -142,9 +139,6 @@ SECTION_FUNC(TEXT, __swap)
 #ifdef CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH
 	/* Register the context switch */
 	call	_sys_k_event_logger_context_switch
-#endif
-#ifdef CONFIG_STACK_SENTINEL
-	call	_check_stack_sentinel
 #endif
 	movl	_kernel_offset_to_ready_q_cache(%edi), %eax
 

arch/x86/core/sys_fatal_error_handler.c

@@ -38,12 +38,17 @@
  *
  * @return This function does not return.
  */
-FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
+FUNC_NORETURN __weak void _SysFatalErrorHandler(unsigned int reason,
 					 const NANO_ESF *pEsf)
 {
 	ARG_UNUSED(pEsf);
 
 #if !defined(CONFIG_SIMPLE_FATAL_ERROR_HANDLER)
+#ifdef CONFIG_STACK_SENTINEL
+	if (reason == _NANO_ERR_STACK_CHK_FAIL) {
+		goto hang_system;
+	}
+#endif
 	if (reason == _NANO_ERR_KERNEL_PANIC) {
 		goto hang_system;
 	}

arch/xtensa/core/fatal.c

@@ -235,12 +235,17 @@ void exit(int return_code)
  *
  * @return N/A
  */
-FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
+FUNC_NORETURN __weak void _SysFatalErrorHandler(unsigned int reason,
 					 const NANO_ESF *pEsf)
 {
 	ARG_UNUSED(pEsf);
 
 #if !defined(CONFIG_SIMPLE_FATAL_ERROR_HANDLER)
+#ifdef CONFIG_STACK_SENTINEL
+	if (reason == _NANO_ERR_STACK_CHK_FAIL) {
+		goto hang_system;
+	}
+#endif
 	if (reason == _NANO_ERR_KERNEL_PANIC) {
 		goto hang_system;
 	}

arch/xtensa/core/swap.S

@@ -82,13 +82,6 @@ __swap:
 #else
 	call4 _sys_k_event_logger_context_switch
 #endif
-#endif
-#ifdef CONFIG_STACK_SENTINEL
-#ifdef __XTENSA_CALL0_ABI__
-	call0 _check_stack_sentinel
-#else
-	call4 _check_stack_sentinel
-#endif
 #endif
 	/* _thread := _kernel.ready_q.cache */
 	l32i a3, a2, KERNEL_OFFSET(ready_q_cache)

boards/arc/em_starterkit/doc/board.rst

@@ -284,4 +284,4 @@ References
 
 .. _Putty website: http://www.putty.org
 
-.. _ARC EM Starter Kit User Guide: https://www.embarc.org/help.html#starterkit
+.. _ARC EM Starter Kit User Guide: https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit

boards/arm/96b_nitrogen/96b_nitrogen_defconfig

@@ -3,6 +3,9 @@ CONFIG_SOC_FAMILY_NRF5=y
 CONFIG_SOC_SERIES_NRF52X=y
 CONFIG_BOARD_96B_NITROGEN=y
 
+# Enable MPU
+CONFIG_ARM_MPU_NRF52X=y
+
 # enable uart driver
 CONFIG_SERIAL=y
 CONFIG_UART_NRF5=y

boards/arm/arduino_due/doc/board.rst

@@ -23,7 +23,10 @@ the processor.
 .. note::
    This configuration is not supported by Arduino.
 
-
+.. image:: img/arduino_due.png
+     :width: 500px
+     :align: center
+     :alt: Arduino Due
 
 Hardware
 ********

boards/arm/bbc_microbit/Makefile.board

@@ -0,0 +1,4 @@
+PYOCD_TARGET = nrf51
+FLASH_SCRIPT=pyocd.sh
+DEBUG_SCRIPT=pyocd.sh
+export PYOCD_TARGET FLASH_SCRIPT

boards/arm/frdm_k64f/Makefile.board

@@ -1,5 +1,5 @@
-FLASH_SCRIPT = openocd.sh
-DEBUG_SCRIPT = openocd.sh
+FLASH_SCRIPT = pyocd.sh
+DEBUG_SCRIPT = pyocd.sh
 
 OPENOCD_LOAD_CMD = "flash write_image erase ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
 OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"

boards/arm/frdm_k64f/doc/frdm_k64f.rst

@@ -204,7 +204,7 @@ application to flash.
    $ cd <zephyr_root_path>
    $ . zephyr-env.sh
    $ cd samples/hello_world/
-   $ make BOARD=frdm_k64f FLASH_SCRIPT=pyocd.sh flash
+   $ make BOARD=frdm_k64f flash
 
 Open a serial terminal (minicom, putty, etc.) with the following settings:
 
@@ -233,7 +233,7 @@ program your Zephyr application to flash. It will leave you at a gdb prompt.
    $ cd <zephyr_root_path>
    $ . zephyr-env.sh
    $ cd samples/hello_world/
-   $ make BOARD=frdm_k64f DEBUG_SCRIPT=pyocd.sh debug
+   $ make BOARD=frdm_k64f debug
 
 
 .. _FRDM-K64F Website:

boards/arm/nrf52840_pca10056/nrf52840_pca10056_defconfig

@@ -4,6 +4,9 @@ CONFIG_SOC_SERIES_NRF52X=y
 CONFIG_SOC_NRF52840_QIAA=y
 CONFIG_BOARD_NRF52840_PCA10056=y
 
+# Enable MPU
+CONFIG_ARM_MPU_NRF52X=y
+
 # enable uart driver
 CONFIG_SERIAL=y
 CONFIG_UART_NRF5=y

boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig

@@ -4,6 +4,9 @@ CONFIG_SOC_SERIES_NRF52X=y
 CONFIG_SOC_NRF52832_QFAA=y
 CONFIG_BOARD_NRF52_BLENANO2=y
 
+# Enable MPU
+CONFIG_ARM_MPU_NRF52X=y
+
 # enable uart driver
 CONFIG_SERIAL=y
 CONFIG_UART_NRF5=y

boards/arm/nrf52_pca10040/nrf52_pca10040_defconfig

@@ -4,6 +4,9 @@ CONFIG_SOC_SERIES_NRF52X=y
 CONFIG_SOC_NRF52832_QFAA=y
 CONFIG_BOARD_NRF52_PCA10040=y
 
+# Enable MPU
+CONFIG_ARM_MPU_NRF52X=y
+
 # enable uart driver
 CONFIG_SERIAL=y
 CONFIG_UART_NRF5=y

boards/arm/sam_e70_xplained/doc/sam_e70_xplained.rst

@@ -9,6 +9,11 @@ Overview
 The SAM E70 Xplained evaluation kit is a development platform to evaluate the
 Atmel SAM E70 series microcontrollers.
 
+.. image:: img/sam_e70_xplained.png
+     :width: 500px
+     :align: center
+     :alt: SAM E70 Xplained
+
 Hardware
 ********
 

boards/boards.rst

@@ -3,6 +3,8 @@
 Supported Boards
 ################
 
+To add support documentation for a new board, please use the template available
+under :file:`doc/templates/board.tmpl`
 
 X86 Boards
 **********
@@ -48,11 +50,3 @@ XTENSA Boards
    :glob:
 
    xtensa/**/*
-
-A list of additional supported boards can be found on the `Zephyr project wiki`_.
-
-To add a new board, please use the template available under
-:file:`doc/templates/board.tmpl`
-
-
-.. _Zephyr project wiki: https://wiki.zephyrproject.org/view/Supported_Boards

boards/x86/galileo/doc/galileo.rst

@@ -343,10 +343,10 @@ At this time, the kernel does not support the following:
 Bibliography
 ************
 
-1. `Intel® Galileo Datasheet`_, Order Number: 329681-001US
+1. `Intel® Galileo Datasheet`_, Order Number: 329681-003US
 
 .. _Intel® Galileo Datasheet:
-   http://www.intel.com/newsroom/kits/quark/galileo/pdfs/Intel_Galileo_Datasheet.pdf
+   https://www.intel.com/content/dam/support/us/en/documents/galileo/sb/galileo_datasheet_329681_003.pdf
 
 2. `Intel® Galileo Board User Guide`_.
 
@@ -356,8 +356,7 @@ Bibliography
 3. `Intel® Quark SoC X1000 Datasheet`_, Order Number: 329676-001US
 
 .. _Intel® Quark SoC X1000 Datasheet:
-   https://communities.intel.com/servlet/JiveServlet/previewBody/
-   21828-102-2-25120/329676_QuarkDatasheet.pdf
+   https://communities.intel.com/servlet/JiveServlet/previewBody/21828-102-2-25120/329676_QuarkDatasheet.pdf
 
 4. `Intel® Quark Core Hardware Reference Manual`_.
 

boards/x86/quark_d2000_crb/quark_d2000_crb_defconfig

@@ -12,5 +12,5 @@ CONFIG_SERIAL=y
 CONFIG_SERIAL_HAS_DRIVER=y
 CONFIG_PRINTK=y
 CONFIG_ISR_STACK_SIZE=256
-CONFIG_MAIN_STACK_SIZE=512
+CONFIG_MAIN_STACK_SIZE=1024
 CONFIG_PINMUX=y

doc/README.rst

@@ -41,8 +41,6 @@ The project's documentation currently comprises the following items:
 * Script-generated material for kernel configuration options based on kconfig
   files found in the source code tree
 
-* Additional material on https://wiki.zephyrproject.org
-
 The reStructuredText files are processed by the Sphinx documentation system,
 and make use of the breathe extension for including the doxygen-generated API
 material.  Additional tools are required to generate the

doc/application/application.rst

@@ -502,7 +502,8 @@ depth is needed. The developer must supply a :file:`Makefile` for the
 Application-specific source code should not use symbol name prefixes that have
 been reserved by the kernel for its own use. For more information, see
 
-`Naming Conventions <https://wiki.zephyrproject.org/view/Coding_conventions#Naming_Conventions>`_.
+`Naming Conventions
+<https://github.com/zephyrproject-rtos/zephyr/wiki/Naming-Conventions>`_.
 
 
 The following requirements apply to all Makefiles in the :file:`src`

doc/contribute/code.rst

@@ -8,7 +8,7 @@ licenses, the naming conventions, the code submission infrastructure, the
 review process and the code documentation can be found on the
 Zephyr Project wiki.
 
-* https://wiki.zephyrproject.org/view/Collaboration_Guidelines
+* https://github.com/zephyrproject-rtos/zephyr/wiki/Contribution-Guide
 
 .. toctree::
    :maxdepth: 1

doc/drivers/drivers.rst

@@ -149,7 +149,7 @@ failures, etc., should be handled by assertions.
 
 When it is appropriate to return error conditions for the caller to check, 0
 should be returned on success and a POSIX errno.h code returned on failure.
-See https://wiki.zephyrproject.org/view/Coding_conventions#Return_Codes for
+See https://github.com/zephyrproject-rtos/zephyr/wiki/Naming-Conventions#return-codes for
 details about this.
 
 A driver implementing a particular subsystem will define the real implementation

doc/dts/device_tree.rst

@@ -0,0 +1,252 @@
+.. _device-tree:
+
+Device Tree in Zephyr
+########################
+
+Introduction to Device Tree
+***************************
+
+Device tree is a way of describing hardware and configuration information
+for boards.  Device tree was adopted for use in the Linux kernel for the
+PowerPC architecture.  However, it is now in use for ARM and other
+architectures.
+
+The device tree is a data structure for dynamically describing hardware
+using a Device Tree Source (DTS) data structure language, and compiled
+into a compact Device Tree Blob (DTB) using a Device Tree Compiler (DTC).
+Rather than hard coding every detail of a board's hardware into the
+operating system, the hardware-describing DTB is passed to the operating
+system at boot time. This allows the same compiled Linux kernel to support
+different hardware configurations within an architecture family (e.g., ARM,
+x86, PowerPC) and moves a significant part of the hardware description out of
+the kernel binary itself.
+
+Traditional usage of device tree involves storing of the Device Tree Blob.
+The DTB is then used during runtime for configuration of device drivers.  In
+Zephyr, the DTS information will be used only during compile time.
+Information about the system is extracted from the compiled DTS and used to
+create the application image.
+
+Device tree uses a specific format to describe the device nodes in a system.
+This format is described in `EPAPR document`_.
+
+.. _EPAPR document: http://www.devicetree.org/specifications-pdf
+
+More device tree information can be found at the `device tree repository`_.
+
+.. _device tree repository: https://git.kernel.org/pub/scm/utils/dtc/dtc.git
+
+
+System build requirements
+*************************
+
+The Zephyr device tree feature requires a device tree compiler (DTC) and Python
+YAML packages.  Refer to the installation guide for your specific host OS.
+
+:ref:`installing_zephyr_win`
+
+:ref:`installation_linux`
+
+:ref:`installing_zephyr_mac`
+
+
+Zephyr and Device Tree
+**********************
+
+In Zephyr, device tree is used to not only describe hardware, but also to
+describe Zephyr-specific configuration information.  The Zephyr-specific
+information is intended to augment the device tree descriptions.  The main
+reason for this is to leverage existing device tree files that a SoC vendor may
+already have defined for a given platform.
+
+Today, configuration in Zephyr comes from a number of different places.  It can
+come from Kconfig files, CMSIS header files, vendor header files, prj.conf
+files, and other miscellaneous sources.  The intent of using device tree is to
+replace or curtail the use of Kconfig files throughout the system, and instead
+use device tree files to describe the configuration of device nodes.  CMSIS and
+vendor header files can be used in conjunction with the device tree to fully
+describe hardware.  Device tree is not intended to replace CMSIS or vendor
+include files.
+
+The device tree files are compiled using the device tree compiler.  The compiler
+runs the .dts file through the C preprocessor to resolve any macro or #defines
+utilized in the file.  The output of the compile is another dts formatted file.
+
+After compilation, a python script extracts information from the compiled device
+tree file using a set of rules specified in YAML files.  The extracted
+information is placed in a header file that is used by the rest of the code as
+the project is compiled.
+
+A temporary fixup file is required for device tree support on most devices.
+This .fixup file resides in the dts architecture directory and has the same
+name as the master .dts file.  The only difference is the suffix is .fixup.
+This fixup file maps the generated include information to the current
+driver/source usage.
+
+Device tree file formats
+************************
+Hardware and software is described inside of device tree files in clear text format.
+These files have the file suffix of .dtsi or .dts.  The .dtsi files are meant to
+be included by other files.  Typically for a given board you have some number of
+.dtsi include files that pull in common device descriptions that are used across
+a given SoC family.
+
+-----------------------------------------
+Example: FRDM K64F Board and Hexiwear K64
+-----------------------------------------
+Both of these boards are based on the same NXP Kinetis SoC family, the K6X.  The
+following shows the include hierarchy for both boards.
+
+dts/arm/frdm_k64.dts includes the following two files::
+
+  dts/arm/nxp/nxp_k6x.dtsi
+  dts/arm/armv7-m.dtsi
+
+dts/arm/hexiwear_k64.dts includes the same two files::
+
+  dts/arm/nxp/nxp_k6x.dtsi
+  dts/arm/armv7-m.dtsi
+
+The board-specific .dts files enable nodes, define the Zephyr-specific items,
+and also adds board-specific changes like gpio/pinmux assignments.  These types
+of things will vary based on the board layout and application use.
+
+Currently supported boards
+**************************
+
+Device tree is currently supported on all ARM targets.  Support for all other
+architectures is to be completed by release 1.9.
+
+Adding support for a board
+**************************
+
+Adding device tree support for a given board requires adding a number of files.
+These files will contain the DTS information that describes a platform, the
+YAML descriptions that define the contents of a given Device Tree peripheral
+node, and also any fixup files required to support the platform.
+
+When writing Device Tree Source files, it is good to separate out common
+peripheral information that could be used across multiple SoC families or
+boards.  DTS files are identified by their file suffix.  A .dtsi suffix denotes
+a DTS file that is used as an include in another DTS file.  A .dts suffix
+denotes the primary DTS file for a given board.
+
+The primary DTS file will contain at a minimum a version line, optional
+includes, and the root node definition.  The root node will contain a model and
+compatible that denotes the unique board described by the .dts file.
+
+--------------------------------
+Device Tree Source File Template
+--------------------------------
+
+.. code::
+
+  /dts-v1/
+  / {
+          model = "Model name for your board";
+          compatible = "compatible for your board";
+          /* rest of file */
+  };
+
+
+One suggestion for starting from scratch on a platform/board is to examine other
+boards and their device tree source files.
+
+The following is a more precise list of required files:
+
+* Base architecture support
+
+  * Add architecture-specific DTS directory, if not already present.
+    Example: dts/arm for ARM.
+  * Add target to dts/<ARCH>/Makefile or create Makefile if not present
+  * Add target specific device tree files for base SoC.  These should be
+    .dtsi files to be included in the board-specific device tree files.
+  * Add target specific YAML files in the dts/<ARCH>/yaml directory.
+    Create the yaml directory if not present.
+
+* SoC family support
+
+  * Add one or more SoC family .dtsi files that describe the hardware
+    for a set of devices.  The file should contain all the relevant
+    nodes and base configuration that would be applicable to all boards
+    utilizing that SoC family.
+  * Add SoC family YAML files that describe the nodes present in the .dtsi file.
+
+* Board specific support
+
+  * Add a board level .dts file that includes the SoC family .dtsi files
+    and enables the nodes required for that specific board.
+  * Board .dts file should specify the SRAM and FLASH devices, if present.
+  * Add board-specific YAML files, if required.  This would occur if the
+    board has additional hardware that is not covered by the SoC family
+    .dtsi/.yaml files.
+
+* Fixup files
+
+  * Fixup files contain mappings from existing Kconfig options to the actual
+    underlying DTS derived configuration #defines.  Fixup files are temporary
+    artifacts until additional DTS changes are made to make them unnecessary.
+
+Adding support for device tree in drivers
+*****************************************
+
+As drivers and other source code is converted over to make use of device tree
+generated information, these drivers may require changes to match the generated
+#define information.
+
+
+Source Tree Hierarchy
+*********************
+
+The device tree files are located in a couple of different directories.  The
+directory split is done based on architecture, and there is also a common
+directory where architecture agnostic device tree and yaml files are located.
+
+Assuming the current working directory is the ZEPHYR_BASE, the directory
+hierarchy looks like the following::
+
+  dts/common/
+  dts/common/yaml
+  dts/<ARCH>/
+  dts/<ARCH>/yaml
+
+The common directories contain a skeleton.dtsi include file that defines the
+address and size cells.  The yaml subdirectory contains common yaml files for
+Zephyr-specific nodes/properties and generic device properties common across
+architectures.
+
+Example: DTS/YAML files for NXP FRDM K64F::
+
+  dts/arm/armv7-m.dtsi
+  dts/arm/k6x/nxp_k6x.dtsi
+  dts/arm/frdm_k64f.dts
+  dts/arm/yaml/arm,v7m-nvic.yaml
+  dts/arm/yaml/k64gpio.yaml
+  dts/arm/yaml/k64pinmux.yaml
+  dts/arm/yaml/k64uart.yaml
+
+YAML definitions for device nodes
+*********************************
+
+Device tree can describe hardware and configuration, but it doesn't tell the
+system which pieces of information are useful, or how to generate configuration
+data from the device tree nodes.  For this, we rely on YAML files to describe
+the contents or definition of a device tree node.
+
+A YAML description must be provided for every device node that is to be a source
+of information for the system.  This YAML description can be used for more than
+one purpose.  It can be used in conjunction with the device tree to generate
+include information.  It can also be used to validate the device tree files
+themselves.  A device tree file can successfully compile and still not contain
+the necessary pieces required to build the rest of the software.  YAML provides
+a means to detect that issue.
+
+YAML files reside in a subdirectory inside the common and architecture-specific
+device tree directories.  A YAML template file is provided to show the required
+format.  This file is located at:
+
+  dts/common/yaml/device_node.yaml.template
+
+YAML files must end in a .yaml suffix.  YAML files are scanned during the
+information extraction phase and are matched to device tree nodes via the
+compatible property.

doc/getting_started/installation_linux.rst

@@ -55,7 +55,7 @@ Install the required packages in a Ubuntu host system with:
 .. code-block:: console
 
    $ sudo apt-get install git make gcc g++ python3-ply ncurses-dev \
-	 python3-yaml python2.7 dfu-util
+	 python3-yaml dfu-util device-tree-compiler
 
 Install the required packages in a Fedora host system with:
 
@@ -64,7 +64,7 @@ Install the required packages in a Fedora host system with:
    $ sudo dnf group install "Development Tools"
    $ sudo dnf install git make gcc glibc-static \
 	 libstdc++-static python3-ply ncurses-devel \
-	 python-yaml python2 dfu-util
+	 python-yaml dfu-util dtc
 
 .. _zephyr_sdk:
 
@@ -87,6 +87,8 @@ following architectures:
 
 * :abbr:`NIOS II`
 
+* :abbr:`Xtensa`
+
 Follow these steps to install the SDK on your Linux host system.
 
 #. Download the latest SDK self-extractable binary.

doc/getting_started/installation_mac.rst

@@ -9,17 +9,17 @@ After completing these steps, you will be able to compile and run your Zephyr
 applications on the following Mac OS version:
 
 * Mac OS X 10.11 (El Capitan)
+* macOS Sierra 10.12
 
-Developing for Zephyr on OS X generally requires you to build the
-toolchain yourself. However, if there is already an OS X toolchain for your
+Developing for Zephyr on macOS generally requires you to build the
+toolchain yourself. However, if there is already an macOS toolchain for your
 target architecture you can use it directly.
 
 Using a 3rd Party toolchain
 ***************************
 
 If a toolchain is available for the architecture you plan to build for, then
-you can use it as explained in:
-:ref:`third_party_x_compilers`.
+you can use it as explained in: :ref:`third_party_x_compilers`.
 
 An example of an available 3rd party toolchain is GCC ARM Embedded for the
 Cortex-M family of cores.
@@ -40,8 +40,8 @@ build for and install tools that the build system requires.
 Before proceeding with the build, ensure your OS is up to date.
 
 First, install the :program:`Homebrew` (The missing package manager for
-OS X). Homebrew is a free and open-source software package management system
-that simplifies the installation of software on Apple's OS X operating
+macOS). Homebrew is a free and open-source software package management system
+that simplifies the installation of software on Apple's macOS operating
 system.
 
 To install :program:`Homebrew`, visit the `Homebrew site`_ and follow the
@@ -53,12 +53,28 @@ missing dependency. If so, follow please follow the instructions provided.
 After Homebrew was successfully installed, install the following tools using
 the brew command line.
 
+Install tools to build Zephyr binaries:
+
 .. code-block:: console
 
-   $ brew install gettext qemu help2man mpfr gmp coreutils wget python3 dfu-util
+   $ brew install dfu-util qemu dtc python3
+   $ pip3 install ply pyyaml
+
+Install tools needed for building the toolchain (if needed):
+
+.. code-block:: console
+
+   $ brew install gettext help2man mpfr gmp coreutils wget
    $ brew tap homebrew/dupes
    $ brew install grep --with-default-names
-   $ pip3 install ply
+
+
+To build the toolchain, you will need the latest version of crosstool-ng (1.23).
+This version was not available via brew when writing this documentation, you can
+however try and see if you get 1.23 installed:
+
+.. code-block:: console
+
    $ brew install crosstool-ng
 
 Alternatively you can install the latest version of :program:`crosstool-ng`
@@ -67,9 +83,9 @@ latest version usually supports the latest released compilers.
 
 .. code-block:: console
 
-   $ wget http://crosstool-ng.org/download/crosstool-ng/crosstool-ng-1.22.0.tar.bz2
-   $ tar xvf crosstool-ng-1.22.0.tar.bz2
-   $ cd crosstool-ng/
+   $ wget http://crosstool-ng.org/download/crosstool-ng/crosstool-ng-1.23.0.tar.bz2
+   $ tar xvf crosstool-ng-1.23.0.tar.bz2
+   $ cd crosstool-ng-1.23.0/
    $ ./configure
    $ make
    $ make install
@@ -92,7 +108,8 @@ Alternatively you can use the script below to create the image:
 .. code-block:: bash
 
    #!/bin/bash
-   ImageName=CrossToolNG ImageNameExt=${ImageName}.sparseimage
+   ImageName=CrossToolNG
+   ImageNameExt=${ImageName}.sparseimage
    diskutil umount force /Volumes/${ImageName} && true
    rm -f ${ImageNameExt} && true
    hdiutil create ${ImageName} -volname ${ImageName} -type SPARSE -size 8g -fs HFSX
@@ -116,15 +133,22 @@ both ARM and X86 that can be used to pre-select the options needed
 for building the toolchain.
 The configuration files can be found in :file:`${ZEPHYR_BASE}/scripts/cross_compiler/`.
 
+Currently the following configurations are provided:
+
+* i586.config: for standard ABI, for example for Galileo and qemu_x86
+* iamcu.config: for IAMCU ABI, for example for the Arduino 101
+* nios2.config: for Nios II boards
+
 .. code-block:: console
 
-   $ cp ${ZEPHYR_BASE}/scripts/cross_compiler/x86.config .config
+   $ cp ${ZEPHYR_BASE}/scripts/cross_compiler/i586.config .config
 
 You can create a toolchain configuration or customize an existing configuration
 yourself using the configuration menus:
 
 .. code-block:: console
 
+   $ export CT_PREFIX=/Volumes/CrossToolNG
    $ ct-ng menuconfig
 
 Verifying the Configuration of the Toolchain

doc/getting_started/installation_win.rst

@@ -20,6 +20,9 @@ Windows system with the latest updates installed.
 Installing Requirements and Dependencies
 ****************************************
 
+Using MSYS2
+===========
+
 The Zephyr development environment on Windows relies on MSYS2, a modern UNIX
 environment for Windows. Follow the steps below to set it up:
 
@@ -34,7 +37,11 @@ environment for Windows. Follow the steps below to set it up:
 
 #. Launch the ``MSYS2 MSYS Shell`` desktop app from your start menu (if it's not still open).
 
-     .. note::
+   .. note::
+
+        Make sure you start ``MSYS2 MSYS Shell``, not ``MSYS2 MinGW Shell``.
+
+   .. note::
         There are multiple ``export`` statements in this tutorial. You can avoid
         typing them every time by placing them at the bottom of your
         ``~/.bash_profile`` file.
@@ -172,8 +179,29 @@ environment for Windows. Follow the steps below to set it up:
     This should check that all the tools and toolchain are set up correctly for
     your own Zephyr development.
 
+Using Windows 10 WSL (Windows Subsystem for Linux)
+==================================================
+
+If you are running a recent version of Windows 10 you can make use of the
+built-in functionality to natively run Ubuntu binaries directly on a standard
+command-prompt. This allows you to install the standard Zephyr SDK and build
+for all supported architectures without the need for a Virtual Machine.
+
+#. Install Windows Subsystem for Linux (WSL) following the instructions on the
+   official Microsoft website: `WSL Installation`_
+
+   .. note::
+         For the Zephyr SDK to function properly you will need Windows 10
+         build 15002 or greater. You can check which Windows 10 build you are
+         running in the "About your PC" section of the System Settings.
+         If you are running an older Windows 10 build you might need to install
+         the Creator's Update.
+
+#. Follow the instructions for Ubuntu detailed in the Zephyr Linux Getting
+   Started Guide which can be found here: :ref:`installation_linux`
 
 .. _GNU ARM Embedded: https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads
 .. _MSYS2 website: http://www.msys2.org/
 .. _ISSM Toolchain: https://software.intel.com/en-us/articles/issm-toolchain-only-download
 .. _Getting Started on Arduino 101 with ISSM: https://software.intel.com/en-us/articles/getting-started-arduino-101genuino-101-with-intel-system-studio-for-microcontrollers
+.. _WSL Installation: https://msdn.microsoft.com/en-us/commandline/wsl/install_guide

doc/index.rst

@@ -35,6 +35,7 @@ Sections
    application/application.rst
    porting/porting.rst
    drivers/drivers.rst
+   dts/device_tree.rst
    subsystems/subsystems.rst
    api/api.rst
    samples/samples.rst
@@ -44,7 +45,6 @@ Sections
    LICENSING.rst
    glossary.rst
 
-You can find further information on the `Zephyr Project Wiki`_.
 
 Indices and Tables
 ******************
@@ -53,7 +53,6 @@ Indices and Tables
 
 * :ref:`search`
 
-.. _Zephyr Project Wiki: https://wiki.zephyrproject.org/view/Main_Page
 .. _Zephyr 1.7.0: https://www.zephyrproject.org/doc/1.7.0/
 .. _Zephyr 1.6.0: https://www.zephyrproject.org/doc/1.6.0/
 .. _Zephyr 1.5.0: https://www.zephyrproject.org/doc/1.5.0/

doc/kernel/other/interrupts.rst

@@ -206,6 +206,130 @@ The following code demonstrates a direct ISR:
        ...
     }
 
+Implementation Details
+======================
+
+Interrupt tables are set up at build time using some special build tools.  The
+details laid out here apply to all architectures except x86, which are
+covered in the `x86 Details`_ section below.
+
+Any invocation of :c:macro:`IRQ_CONNECT` will declare an instance of
+struct _isr_list which is placed in a special .intList section:
+
+.. code-block:: c
+
+    struct _isr_list {
+        /** IRQ line number */
+        s32_t irq;
+        /** Flags for this IRQ, see ISR_FLAG_* definitions */
+        s32_t flags;
+        /** ISR to call */
+        void *func;
+        /** Parameter for non-direct IRQs */
+        void *param;
+    };
+
+Zephyr is built in two phases; the first phase of the build produces
+zephyr_prebuilt.elf which contains all the entries in the .intList section
+preceded by a header:
+
+.. code-block:: c
+
+    struct {
+        void *spurious_irq_handler;
+        void *sw_irq_handler;
+        u32_t num_isrs;
+        u32_t num_vectors;
+        struct _isr_list isrs[];  <- of size num_isrs
+    };
+
+This data consisting of the header and instances of struct _isr_list inside
+zephyr_prebuilt.elf is then used by the gen_isr_tables.py script to generate a
+C file defining a vector table and software ISR table that are then compiled
+and linked into the final application.
+
+The priority level of any interrupt is not encoded in these tables, instead
+:c:macro:`IRQ_CONNECT` also has a runtime component which programs the desired
+priority level of the interrupt to the interrupt controller. Some architectures
+do not support the notion of interrupt priority, in which case the priority
+argument is ignored.
+
+Vector Table
+------------
+A vector table is generated when CONFIG_GEN_IRQ_VECTOR_TABLE is enabled.  This
+data structure is used natively by the CPU and is simply an array of function
+pointers, where each element n corresponds to the IRQ handler for IRQ line n,
+and the function pointers are:
+
+#. For 'direct' interrupts declared with :c:macro:`IRQ_DIRECT_CONNECT`, the
+   handler function will be placed here.
+#. For regular interrupts declared with :c:macro:`IRQ_CONNECT`, the address
+   of the common software IRQ handler is placed here. This code does common
+   kernel interrupt bookkeeping and looks up the ISR and parameter from the
+   software ISR table.
+#. For interrupt lines that are not configured at all, the address of the
+   spurious IRQ handler will be placed here. The spurious IRQ handler
+   causes a system fatal error if encountered.
+
+Some architectures (such as the Nios II internal interrupt controller) have a
+common entry point for all interrupts and do not support a vector table, in
+which case the CONFIG_GEN_IRQ_VECTOR_TABLE option should be disabled.
+
+Some architectures may reserve some initial vectors for system exceptions
+and declare this in a table elsewhere, in which case
+CONFIG_GEN_IRQ_START_VECTOR needs to be set to properly offset the indices
+in the table.
+
+SW ISR Table
+------------
+This is an array of struct _isr_table_entry:
+
+.. code-block:: c
+
+    struct _isr_table_entry {
+        void *arg;
+        void (*isr)(void *);
+    };
+
+This is used by the common software IRQ handler to look up the ISR and its
+argument and execute it. The active IRQ line is looked up in an interrupt
+controller register and used to index this table.
+
+x86 Details
+-----------
+
+The x86 architecture has a special type of vector table called the Interrupt
+Descriptor Table (IDT) which must be laid out in a certain way per the x86
+processor documentation.  It is still fundamentally a vector table, and the
+gen_idt tool uses the .intList section to create it. However, on APIC-based
+systems the indexes in the vector table do not correspond to the IRQ line. The
+first 32 vectors are reserved for CPU exceptions, and all remaining vectors (up
+to index 255) correspond to the priority level, in groups of 16. In this
+scheme, interrupts of priority level 0 will be placed in vectors 32-47, level 1
+48-63, and so forth. When the gen_idt tool is constructing the IDT, when it
+configures an interrupt it will look for a free vector in the appropriate range
+for the requested priority level and set the handler there.
+
+There are some APIC variants (such as MVIC) where priorities cannot be set
+by the user and the position in the vector table does correspond to the
+IRQ line. Systems like this will enable CONFIG_X86_FIXED_IRQ_MAPPING.
+
+On x86 when an interrupt or exception vector is executed by the CPU, there is
+no foolproof way to determine which vector was fired, so a software ISR table
+indexed by IRQ line is not used. Instead, the :c:macro:`IRQ_CONNECT` call
+creates a small assembly language function which calls the common interrupt
+code in :cpp:func:`_interrupt_enter` with the ISR and parameter as arguments.
+It is the address of this assembly interrupt stub which gets placed in the IDT.
+For interrupts declared with :c:macro:`IRQ_DIRECT_CONNECT` the parameterless
+ISR is placed directly in the IDT.
+
+On systems where the position in the vector table corresponds to the
+interrupt's priority level, the interrupt controller needs to know at
+runtime what vector is associated with an IRQ line. gen_idt additionally
+creates an _irq_to_interrupt_vector array which maps an IRQ line to its
+configured vector in the IDT. This is used at runtime by :c:macro:`IRQ_CONNECT`
+to program the IRQ-to-vector association in the interrupt controller.
+
 Suggested Uses
 **************
 

doc/porting/arch.rst

@@ -21,7 +21,7 @@ some are optional:
   take when the CPU comes out of reset (required).
 
 * **Interrupt and exception handling**: each architecture handles asynchronous
-  and un-requested events in a specific manner (required).
+  and unrequested events in a specific manner (required).
 
 * **Thread context switching**: the Zephyr context switch is dependent on the
   ABI and each ISA has a different set of registers to save (required).

doc/release-notes-1.8.rst

@@ -0,0 +1,324 @@
+.. _zephyr_1.8:
+
+Zephyr Kernel 1.8.0
+####################
+
+We are pleased to announce the release of Zephyr kernel version 1.8.0.
+
+Major enhancements with this release include:
+
+* Tickless kernel
+* IP Stack improvements
+* Bluetooth 5.0 features
+* Ecosystem: Tracing, debugging support through third-party tools (openocd,
+  Segger Systemview)
+* Improved build support on Mac and Windows development environments
+* Xtensa GCC support
+* Initial implementation of MMU/MPU support
+* Expanded device support
+
+The following sections provide detailed lists of changes by component.
+
+Kernel
+******
+
+* Use k_cycle_get_32 instead of sys_cycle_get_32 for Kernel
+* Added k_panic() and k_oops() APIs for Kernel
+* Added k_thread_create() API for Kernel
+* Added k_queue API for Kernel
+* Add tickless kernel support
+
+Architectures
+*************
+
+* arm: Update core to use struct k_thread
+* arm: Added ARM MPU support
+* dts: Added ARM CMSDK support
+* arm: Added Initial support for NXP MPU
+* arm: Added Device Tree Support for nRF52832 SoC based boards
+* arm: Fixed nRF52840-QIAA SoC support for device tree
+* arm: Added Device Tree Support for nRF52840 SoC & boards
+* arm: Added Device Tree Support for nRF51822 SoC & boards
+* dts: Introduced st/mem.h for FLASH & SRAM sizes
+* dts: Put IRQ priority into the interrupt property
+* arm: Support for MKL25Z soc
+* arm: Added FPU support
+* x86: defined MMU data structures
+* Support for ARC EM Starter Kit version 2.3 added
+
+
+
+Boards
+******
+
+* Added qemu_xtensa board definition
+* Added a more informative page fault handler x86 board
+* xtensa: build similar to other Zephyr arches
+* Define MMU data structures for x86 board
+* Added support for board disco_l475_iot1
+* Added STM32F413 Nucleo board
+* Added support for the CC3220SF_LAUNCHXL board
+* Support for new ARM board FRDM-KL25Z
+* arduino_101 board enable GPIO by default
+* boards: convert to using newly introduced integer sized types
+* arm: Added support for Nucleo L432KC board
+* arm: Added support for STM32L496G Discovery board
+* arm: Added support for STM32F469I-DISCO board
+* BBC micro:bit: Added driver & API for the 5x5 LED display
+
+Drivers and Sensors
+*******************
+
+* UART interrupt-driver API is better defined
+* Support for pull-style console API
+* nRF5 IEEE 802.15.4 radio driver added
+* KW41Z IEEE 802.15.4 radio driver added
+* Added MCUX TRNG driver
+* Added support for the SiFive Freedom E310 pinmux driver
+* drivers/sensor: Convert formatter strings to use PRI defines
+* Added lps22hb sensor driver
+* Added lsm6dsl sensor driver
+* Added heart rate sensor driver
+* Added support for max30101 heart rate sensor
+* Added support for lis2dh accelerometer
+
+Networking
+**********
+
+* HTTPS server support added
+* HTTP Basic-Auth support added
+* IPv6 fragmentation support added
+* Add block wise support to CoAP for well-known response
+* Big refactoring of network buffer handling
+* Start to collect TCP statistics if enabled in config
+* IEEE 802.15.4 security support added
+* DNS resolver sample application added
+* IPv6 multicast listener (MLDv2) support added
+* NATS protocol sample application added
+* HTTP client and server connectivity fixes
+* Network samples Coverity fixes
+* Network samples llvm compiler warning fixes
+* MQTT publisher connectivity fixes
+* 6lo IPv6 header compression fixes
+* CoAP connectivity fixes
+* DHCPv4 connectivity fixes
+* TCP connectivity fixes
+* DNS documentation and connectivity fixes
+* IPv6 connectivity fixes
+* IPv4 ARP fixes
+* IEEE 802.15.4 configuration tweaking fixes
+* Remove ORFD (Overly Reduced Function Device) 802.15.4 support
+* Network offloading driver fixes
+* Fix various memory leaks
+* Properly check TCP and UDP checksum before accepting packet
+* Start RX and TX network threads in proper order
+* Network samples documentation fixes and clarifications
+* RPL mesh routing fixes
+* Network link (MAC) address fixes
+
+Bluetooth
+*********
+
+* Host: Added ATT and SMP packet tracking for flow control enforcement
+* Host: GATT database changed to a linked list in preparation for dynamic allocation
+* Bluetooth 5.0: The Controller reports itself as 5.0-capable
+* Bluetooth 5.0: Introduced Channel Selection Algorithm #2 support
+* Bluetooth 5.0: Added Multiple PHY support, both 2Mbit/s and long-range coded
+* Bluetooth 5.0: Integrated Scan Request notifications
+* Controller: Added Low Duty Cycle Directed Advertising support
+* Controller: Added Scan duplicate filtering support
+* Controller: Enforced complete role separation in the controller for smaller builds
+* Controller: Introduced Advanced Controller configuration with several new Kconfig options
+* Controller: Changed the radio interrupts to direct ISRs to reduce interrupt latency
+* Added HCI Controller to Host flow control support in both Host and Controller
+* BR/EDR: Added HFP (e)SCO audio channel establishment support
+* BR/EDR: Added support for a functional SDP server
+
+Build and Infrastructure
+************************
+
+* Support building host tools
+* Added separate DTS target
+* Added support for MSYS2
+* Use -O2 instead of -Os for ARC with SDK 0.9
+
+Libraries
+*********
+
+* Added library for software driven I2C
+* Created a HTTP library
+* Added HTTP server library support
+* Added minimal JSON library
+* Update TinyCrypt to version 0.2.6
+* Added minimal JSON library
+
+HALs
+****
+
+* Added Atmel SAM family I2C (TWIHS) driver
+* Added Atmel SAM serial (UART) driver
+* Added WDT driver for Atmel SAM SoCs
+* Added Atmel SAM4S SoC support
+* Imported Nordic 802.15.4 radio driver
+* Added Initial support for NXP MPU
+* Updated QMSI to 1.4 RC4
+* Added FPU support
+* Added basic support for STM32F413
+* Introduced STM32F4x DMA driver
+* pinmux: stm32: Added support for Nucleo L432KC
+* Added support for STM32L496G Discovery board
+* Added dts for STM32F407
+* Added support for STM32F4DISCOVERY Board
+* Added support for STM32F469XI
+* Added support for STM32F469I-DISCO
+
+Documentation
+*************
+
+* Board documentation added for new board ports
+* Added a board porting guide
+* Added security sections to porting and user guides
+* Continued migration of wiki.zephyrproject.org material to website and github wiki
+* Improved CSS formatting and appearance of generated documents
+* Added breadcrumb navigation header with kernel version number
+* Updated getting started setup guides for Linux, Windows, and macOS
+* Updates and additions to follow new and updated kernel features
+* Broken link and spelling check scans
+* Removed deprecated kernel documentation (pre 1.6 release) from website (still available in git repo if needed)
+
+Tests and Samples
+*****************
+
+* Added test to verify same tick timeout expiry order
+* Added clock_test for kernel
+* Added tickless tests
+* Added a simple CC2520 crypto dev test
+* Added combined observer & broadcaster app for Bluetooth samples
+* Added support to wait both IPv4 and IPv6
+* Enabled tickless kernel option in some apps
+
+JIRA Related Items
+******************
+
+.. comment  List derived from Jira query: ...
+
+* :jira:`ZEP-248` - Add a BOARD/SOC porting guide
+* :jira:`ZEP-339` - Tickless Kernel
+* :jira:`ZEP-540` - add APIs for asynchronous transfer callbacks
+* :jira:`ZEP-628` - Validate RPL Routing node support
+* :jira:`ZEP-638` - feature to consider: flag missing functionality at build time when possible
+* :jira:`ZEP-720` - Add MAX30101 heart rate sensor driver
+* :jira:`ZEP-828` - IPv6 - Multicast Join/Leave Support
+* :jira:`ZEP-843` - Unified assert/unrecoverable error infrastructure
+* :jira:`ZEP-888` - 802.15.4 - Security support
+* :jira:`ZEP-932` - Adapt kernel sample & test projects
+* :jira:`ZEP-948` - Revisit the timeslicing algorithm
+* :jira:`ZEP-973` - Remove deprecated API related to device PM functions and DEVICE\_ and SYS\_* macros
+* :jira:`ZEP-1028` - shrink k_block struct size
+* :jira:`ZEP-1032` - IPSP router role support
+* :jira:`ZEP-1169` - Sample mbedDTLS DTLS client stability on ethernet driver
+* :jira:`ZEP-1171` - Event group kernel APIs
+* :jira:`ZEP-1280` - Provide Event Queues Object
+* :jira:`ZEP-1313` - porting and user guides must include a security section
+* :jira:`ZEP-1326` - Clean up _THREAD_xxx APIs
+* :jira:`ZEP-1388` - Add support for KW40 SoC
+* :jira:`ZEP-1391` - Add support for Hexiwear KW40
+* :jira:`ZEP-1392` - Add FXAS21002 gyroscope sensor driver
+* :jira:`ZEP-1435` - Improve Quark SE C1000 ARC Floating Point Performance
+* :jira:`ZEP-1438` - AIO: AIO Comparator is not stable on D2000 and Arduino101
+* :jira:`ZEP-1463` - Add Zephyr Support in segger SystemView
+* :jira:`ZEP-1500` - net/mqtt: Test case for the MQTT high-level API
+* :jira:`ZEP-1528` - Provide template for multi-core applications
+* :jira:`ZEP-1529` - Unable to exit menuconfig
+* :jira:`ZEP-1530` - Hotkeys for the menu at the bottom of menuconfig sometimes doesn't work
+* :jira:`ZEP-1568` - Replace arm cortex_m scs and scb functionality with direct CMSIS-core calls
+* :jira:`ZEP-1586` - menuconfig: Backspace is broken
+* :jira:`ZEP-1599` - printk() support for the '-' indicator  in format string (left justifier)
+* :jira:`ZEP-1607` - Json encoding/decoding library
+* :jira:`ZEP-1621` - Stack Monitoring
+* :jira:`ZEP-1631` - Ability to use k_mem_pool_alloc (or similar API) from ISR
+* :jira:`ZEP-1684` - Add Atmel SAM family watchdog (WDT) driver
+* :jira:`ZEP-1695` - Support ADXL362 sensor
+* :jira:`ZEP-1698` - BME280 support for SPI communication
+* :jira:`ZEP-1711` - xtensa build defines Kconfigs with lowercase names
+* :jira:`ZEP-1718` - support for IPv6 fragmentation
+* :jira:`ZEP-1719` - TCP does not work with 6lo
+* :jira:`ZEP-1721` - many tinycrypt test cases only run on ARM and x86
+* :jira:`ZEP-1722` - xtensa: tinycrypt does not build
+* :jira:`ZEP-1735` - Controller to Host flow control
+* :jira:`ZEP-1759` - All python scripts needed for build should be moved to python 3 to minimize dependencies
+* :jira:`ZEP-1761` - K_MEM_POOL_DEFINE build error "invalid register name" when built with llvm/icx from ISSM toolchain
+* :jira:`ZEP-1769` - Implement  Set Event Mask and LE Set Event Mask commands
+* :jira:`ZEP-1772` - re-introduce controller to host flow control
+* :jira:`ZEP-1776` - sending LE COC data from RX thread can lead to deadlock
+* :jira:`ZEP-1785` - Tinytile: Flashing not supported with this board
+* :jira:`ZEP-1788` - [REG] bt_enable: No HCI driver registered
+* :jira:`ZEP-1800` - Update external mbed TLS library to latest version (2.4.2)
+* :jira:`ZEP-1812` - Add tickless kernel support in HPET timer
+* :jira:`ZEP-1816` - Add tickless kernel support in LOAPIC timer
+* :jira:`ZEP-1817` - Add tickless kernel support in ARCV2 timer
+* :jira:`ZEP-1818` - Add tickless kernel support in cortex_m_systick timer
+* :jira:`ZEP-1821` - Update PM apps to use mili/micro seconds instead of ticks
+* :jira:`ZEP-1823` - Improved Benchmarks
+* :jira:`ZEP-1825` - Context Switching KPI
+* :jira:`ZEP-1836` - Expose current ecb_encrypt() as bt_encrypt() so host can directly access it
+* :jira:`ZEP-1856` - remove legacy micro/nano kernel APIs
+* :jira:`ZEP-1857` - Build warnings [-Wpointer-sign] with LLVM/icx (bluetooth_handsfree)
+* :jira:`ZEP-1866` - Add Atmel SAM family I2C (TWIHS) driver
+* :jira:`ZEP-1880` - "samples/grove/temperature": warning raised when generating configure file
+* :jira:`ZEP-1886` - Build warnings [-Wpointer-sign] with LLVM/icx (tests/net/nbuf)
+* :jira:`ZEP-1887` - Build warnings [-Wpointer-sign] with LLVM/icx (tests/drivers/spi/spi_basic_api)
+* :jira:`ZEP-1893` - openocd: 'make flash' works with Zephyr SDK only and fails for all other toolchains
+* :jira:`ZEP-1896` - [PTS] L2CAP/LE/CFC/BV-06-C
+* :jira:`ZEP-1899` - Missing board documentation for xtensa/xt-sim
+* :jira:`ZEP-1908` - Missing board documentation for arm/nucleo_96b_nitrogen
+* :jira:`ZEP-1910` - Missing board documentation for arm/96b_carbon
+* :jira:`ZEP-1927` - AIO: AIO_CMP_POL_FALL is triggered immediately after aio_cmp_configure
+* :jira:`ZEP-1935` - Packet loss make RPL mesh more vulnerable
+* :jira:`ZEP-1936` - tests/drivers/spi/spi_basic_api/testcase.ini#test_spi - Assertion Fail
+* :jira:`ZEP-1946` - Time to Next Event
+* :jira:`ZEP-1955` - Nested interrupts crash on Xtensa architecture
+* :jira:`ZEP-1959` - Add Atmel SAM family serial (UART) driver
+* :jira:`ZEP-1965` - net-tools HEAD is broken for QEMU/TAP
+* :jira:`ZEP-1966` - Doesn't seem to be able to both send and receive locally via local address
+* :jira:`ZEP-1968` - "make mrproper" removes top-level dts/ dir, makes ARM builds fail afterwards
+* :jira:`ZEP-1980` - Move app_kernel benchmark to unified kernel
+* :jira:`ZEP-1984` - net_nbuf_append(), net_nbuf_append_bytes() have data integrity problems
+* :jira:`ZEP-1990` - Basic support for the BBC micro:bit LED display
+* :jira:`ZEP-1993` - Flowcontrol Required for CDC_ACM
+* :jira:`ZEP-1995` - samples/subsys/console breaks xtensa build
+* :jira:`ZEP-1997` - Crash during startup if co-processors are present
+* :jira:`ZEP-2008` - Port tickless idle test to unified kernel and cleanup
+* :jira:`ZEP-2009` - Port test_sleep test to unified kernel and cleanup
+* :jira:`ZEP-2011` - Retrieve RPL node information through CoAP requests
+* :jira:`ZEP-2012` - Fault in networking stack for cores that can't access unaligned memory
+* :jira:`ZEP-2013` - dead object monitor code
+* :jira:`ZEP-2014` - Default samples/subsys/shell/shell fails to build on QEMU RISCv32 / NIOS2
+* :jira:`ZEP-2019` - Xtensa port does not compile if CONFIG_TICKLESS_IDLE is enabled
+* :jira:`ZEP-2027` - Bluetooth Peripheral Sample won't pair with certain Android devices
+* :jira:`ZEP-2029` - xtensa: irq_offload() doesn't work on XRC_D2PM
+* :jira:`ZEP-2033` - Channel Selection Algorithm #2
+* :jira:`ZEP-2034` - High Duty Cycle Non-Connectable Advertising
+* :jira:`ZEP-2037` - Malformed echo response
+* :jira:`ZEP-2048` - Change UART "baud-rate" property to "current-speed"
+* :jira:`ZEP-2051` - Move away from C99 types to zephyr defined types
+* :jira:`ZEP-2052` - arm: unhandled exceptions in thread take down entire system
+* :jira:`ZEP-2055` - Add README.rst in the root of the project for github
+* :jira:`ZEP-2057` - crash in tests/net/rpl on qemu_x86 causing intermittent sanitycheck failure
+* :jira:`ZEP-2061` - samples/net/dns_resolve networking setup/README is confusing
+* :jira:`ZEP-2064` - RFC: Making net_shell command handlers reusable
+* :jira:`ZEP-2065` - struct dns_addrinfo has unused fields
+* :jira:`ZEP-2066` - nitpick: SOCK_STREAM/SOCK_DGRAM values swapped compared to most OSes
+* :jira:`ZEP-2069` - samples: net: dhcpv4_client: runs failed on frdm k64f board
+* :jira:`ZEP-2070` - net pkt doesn't full unref after send a data form bluetooth's ipsp
+* :jira:`ZEP-2076` - samples: net: coaps_server: build failed
+* :jira:`ZEP-2077` - Fix IID when using CONFIG_NET_L2_BLUETOOTH_ZEP1656
+* :jira:`ZEP-2080` - No reply from RPL node after 20-30 minutes.
+* :jira:`ZEP-2092` - [NRF][BT] Makefile:946: recipe for target 'include/generated/generated_dts_board.h' failed
+* :jira:`ZEP-2114` - tests/kernel/fatal : Fail for QC1000/arc
+* :jira:`ZEP-2125` - Compilation error when UART1 port is enabled via menuconfig
+* :jira:`ZEP-2132` - Build samples/bluetooth/hci_uart fail
+* :jira:`ZEP-2138` - Static code scan (coverity) issues seen
+* :jira:`ZEP-2143` - Compilation Error on Windows 10 with MSYS2
+* :jira:`ZEP-2152` - Xtensa crashes on startup for cores with coprocessors
+* :jira:`ZEP-2178` - Static code scan (coverity) issues seen

doc/release-notes.rst

@@ -6,6 +6,7 @@ Release Notes
 .. toctree::
    :maxdepth: 1
 
+   release-notes-1.8
    release-notes-1.7
    release-notes-1.6
    release-notes-1.5

doc/subsystems/networking/l2-and-drivers.rst

@@ -90,14 +90,14 @@ parameter here. The Ethernet L2 layer will update such information
 once the packet's Ethernet header has been successfully parsed.
 
 In case :c:func:`net_recv_data()` call fails, it will be up to the
-device driver to un-reference the buffer via
+device driver to unreference the buffer via
 :c:func:`net_pkt_unref()`.
 
 On sending, it is up to the device driver to send the buffer all at
 once, with all the fragments.
 
 In case of a fully successful packet transmission only, the device
-driver must un-reference the buffer via `net_pkt_unref()`.
+driver must unreference the buffer via `net_pkt_unref()`.
 
 Each Ethernet device driver will need, in the end, to call
 `NET_DEVICE_INIT_INSTANCE()` like this:
@@ -139,7 +139,7 @@ here as well.  There are two specific differences however:
   :c:type:`struct net_if` send function. It turn, the implementation
   of :c:func:`ieee802154_radio_send()` will ensure the same behavior:
   sending one fragment at a time through :c:type:`struct
-  ieee802154_radio_api` tx function, and un-referencing the buffer
+  ieee802154_radio_api` tx function, and unreferencing the buffer
   only when all the transmission were successful.
 
 Each IEEE 802.15.4 device driver, in the end, will need to call

doc/subsystems/networking/network-management-api.rst

@@ -44,7 +44,7 @@ more events that are relevant.
 
 Two functions are available, `net_mgmt_add_event_callback()` for
 registering the callback function, and `net_mgmt_del_event_callback()`
-for un-registering. A helper function, `net_mgmt_init_event_cb()`, can
+for unregistering. A helper function, `net_mgmt_init_event_cb()`, can
 be used to ease the initialization of the callback structure.
 
 When an event is raised that matches a registered event mask, the

doc/subsystems/networking/networking-api-usage.rst

@@ -23,6 +23,7 @@ example; you may need to do things differently in your own application.)
     :linenos:
     :language: c
     :lines: 2-54
+    :lineno-start: 2
 
 After initialization, first thing application needs to create a context.
 Context is similar to a socket.
@@ -31,6 +32,7 @@ Context is similar to a socket.
     :linenos:
     :language: c
     :lines: 57-66
+    :lineno-start: 57
 
 Then you need to define the local end point for a connection.
 
@@ -38,6 +40,7 @@ Then you need to define the local end point for a connection.
     :linenos:
     :language: c
     :lines: 69-83
+    :lineno-start: 69
 
 Wait until the connection data is received.
 
@@ -45,13 +48,15 @@ Wait until the connection data is received.
     :linenos:
     :language: c
     :lines: 86-202
+    :lineno-start: 86
 
 Close the context when finished.
 
 .. literalinclude:: connectivity-example-app.c
     :linenos:
     :language: c
-    :lines: 204-215
+    :lines: 204-214
+    :lineno-start: 204
 
 .. toctree::
    :maxdepth: 1

drivers/ethernet/Kconfig.mcux

@@ -17,8 +17,8 @@ menuconfig ETH_MCUX
 if ETH_MCUX
 config ETH_MCUX_PROMISCUOUS_MODE
 	bool "Enable promiscuous mode"
-	default false if !NET_IPV6
-	default true if NET_IPV6
+	default n if !NET_IPV6
+	default y if NET_IPV6
 	help
 	  Place the ethernet receiver in promiscuous mode.
 

drivers/ethernet/eth_mcux.c

@@ -142,7 +142,7 @@ static void eth_mcux_phy_enter_reset(struct eth_context *context)
 
 static void eth_mcux_phy_start(struct eth_context *context)
 {
-#ifdef CONFIG_ETH_MCUX_PHY_DETAILED_DEBUG
+#ifdef CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG
 	SYS_LOG_DBG("phy_state=%s", phy_state_name(context->phy_state));
 #endif
 
@@ -166,7 +166,7 @@ static void eth_mcux_phy_start(struct eth_context *context)
 
 void eth_mcux_phy_stop(struct eth_context *context)
 {
-#ifdef CONFIG_ETH_MCUX_PHY_DETAILED_DEBUG
+#ifdef CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG
 	SYS_LOG_DBG("phy_state=%s", phy_state_name(context->phy_state));
 #endif
 
@@ -203,7 +203,7 @@ static void eth_mcux_phy_event(struct eth_context *context)
 	phy_speed_t phy_speed = kPHY_Speed100M;
 	const u32_t phy_addr = 0;
 
-#ifdef CONFIG_ETH_MCUX_PHY_DETAILED_DEBUG
+#ifdef CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG
 	SYS_LOG_DBG("phy_state=%s", phy_state_name(context->phy_state));
 #endif
 	switch (context->phy_state) {

drivers/sensor/lps22hb/lps22hb.c

@@ -56,7 +56,8 @@ static inline void lps22hb_press_convert(struct sensor_value *val,
 	/* Pressure sensitivity is 4096 LSB/hPa */
 	/* Convert raw_val to val in kPa */
 	val->val1 = (raw_val >> 12) / 10;
-	val->val2 = ((s32_t)((raw_val) & 0x0FFF) * 1000L) >> 12;
+	val->val2 = (raw_val >> 12) % 10 * 100000 +
+		(((s32_t)((raw_val) & 0x0FFF) * 100000L) >> 12);
 }
 
 static inline void lps22hb_temp_convert(struct sensor_value *val,

drivers/spi/spi_context.h

@@ -29,13 +29,15 @@ struct spi_context {
 	struct k_poll_signal *signal;
 	bool asynchronous;
 #endif
-	const struct spi_buf **current_tx;
-	struct spi_buf **current_rx;
+	const struct spi_buf *current_tx;
+	size_t tx_count;
+	struct spi_buf *current_rx;
+	size_t rx_count;
 
 	void *tx_buf;
-	u32_t tx_len;
+	size_t tx_len;
 	void *rx_buf;
-	u32_t rx_len;
+	size_t rx_len;
 };
 
 #define SPI_CONTEXT_INIT_LOCK(_data, _ctx_name)				\
@@ -144,36 +146,40 @@ static inline void spi_context_cs_control(struct spi_context *ctx, bool on)
 }
 
 static inline void spi_context_buffers_setup(struct spi_context *ctx,
-					     const struct spi_buf **tx_bufs,
-					     struct spi_buf **rx_bufs,
+					     const struct spi_buf *tx_bufs,
+					     size_t tx_count,
+					     struct spi_buf *rx_bufs,
+					     size_t rx_count,
 					     uint8_t dfs)
 {
-	SYS_LOG_DBG("tx_bufs %p (%p) - rx_bufs %p (%p) - %u",
-		    tx_bufs, tx_bufs ? *tx_bufs : NULL,
-		    rx_bufs, rx_bufs ? *rx_bufs : NULL, dfs);
+	SYS_LOG_DBG("tx_bufs %p (%zu) - rx_bufs %p (%zu) - %u",
+		    tx_bufs, tx_count, rx_bufs, rx_count, dfs);
 
 	ctx->current_tx = tx_bufs;
+	ctx->tx_count = tx_count;
 	ctx->current_rx = rx_bufs;
+	ctx->rx_count = rx_count;
 
-	if (*tx_bufs) {
-		ctx->tx_buf = (*tx_bufs)->buf;
-		ctx->tx_len = (*tx_bufs)->len/dfs;
+	if (tx_bufs) {
+		ctx->tx_buf = tx_bufs->buf;
+		ctx->tx_len = tx_bufs->len / dfs;
 	} else {
 		ctx->tx_buf = NULL;
 		ctx->tx_len = 0;
 	}
 
-	if (*rx_bufs) {
-		ctx->rx_buf = (*rx_bufs)->buf;
-		ctx->rx_len = (*rx_bufs)->len/dfs;
+	if (rx_bufs) {
+		ctx->rx_buf = rx_bufs->buf;
+		ctx->rx_len = rx_bufs->len / dfs;
 	} else {
 		ctx->rx_buf = NULL;
 		ctx->rx_len = 0;
 	}
 
-	SYS_LOG_DBG("current_tx %p, current_rx %p,"
-		    " tx buf/len %p/%u, rx buf/len %p/%u",
-		    ctx->current_tx, ctx->current_rx,
+	SYS_LOG_DBG("current_tx %p (%zu), current_rx %p (%zu),"
+		    " tx buf/len %p/%zu, rx buf/len %p/%zu",
+		    ctx->current_tx, ctx->tx_count,
+		    ctx->current_rx, ctx->rx_count,
 		    ctx->tx_buf, ctx->tx_len, ctx->rx_buf, ctx->rx_len);
 }
 
@@ -187,9 +193,11 @@ void spi_context_update_tx(struct spi_context *ctx, uint8_t dfs)
 	ctx->tx_len--;
 	if (!ctx->tx_len) {
 		ctx->current_tx++;
-		if (*ctx->current_tx) {
-			ctx->tx_buf = (*ctx->current_tx)->buf;
-			ctx->tx_len = (*ctx->current_tx)->len/dfs;
+		ctx->tx_count--;
+
+		if (ctx->tx_count) {
+			ctx->tx_buf = ctx->current_tx->buf;
+			ctx->tx_len = ctx->current_tx->len / dfs;
 		} else {
 			ctx->tx_buf = NULL;
 		}
@@ -197,7 +205,7 @@ void spi_context_update_tx(struct spi_context *ctx, uint8_t dfs)
 		ctx->tx_buf += dfs;
 	}
 
-	SYS_LOG_DBG("tx buf/len %p/%u", ctx->tx_buf, ctx->tx_len);
+	SYS_LOG_DBG("tx buf/len %p/%zu", ctx->tx_buf, ctx->tx_len);
 }
 
 static ALWAYS_INLINE
@@ -216,9 +224,11 @@ void spi_context_update_rx(struct spi_context *ctx, uint8_t dfs)
 	ctx->rx_len--;
 	if (!ctx->rx_len) {
 		ctx->current_rx++;
-		if (*ctx->current_rx) {
-			ctx->rx_buf = (*ctx->current_rx)->buf;
-			ctx->rx_len = (*ctx->current_rx)->len/dfs;
+		ctx->rx_count--;
+
+		if (ctx->rx_count) {
+			ctx->rx_buf = ctx->current_rx->buf;
+			ctx->rx_len = ctx->current_rx->len / dfs;
 		} else {
 			ctx->rx_buf = NULL;
 		}
@@ -226,7 +236,7 @@ void spi_context_update_rx(struct spi_context *ctx, uint8_t dfs)
 		ctx->rx_buf += dfs;
 	}
 
-	SYS_LOG_DBG("rx buf/len %p/%u", ctx->rx_buf, ctx->rx_len);
+	SYS_LOG_DBG("rx buf/len %p/%zu", ctx->rx_buf, ctx->rx_len);
 }
 
 static ALWAYS_INLINE

drivers/spi/spi_dw.c

@@ -251,8 +251,10 @@ static int spi_dw_configure(const struct spi_dw_config *info,
 }
 
 static int transceive(struct spi_config *config,
-		      const struct spi_buf **tx_bufs,
-		      struct spi_buf **rx_bufs,
+		      const struct spi_buf *tx_bufs,
+		      size_t tx_count,
+		      struct spi_buf *rx_bufs,
+		      size_t rx_count,
 		      bool asynchronous,
 		      struct k_poll_signal *signal)
 {
@@ -277,7 +279,8 @@ static int transceive(struct spi_config *config,
 	}
 
 	/* Set buffers info */
-	spi_context_buffers_setup(&spi->ctx, tx_bufs, rx_bufs, spi->dfs);
+	spi_context_buffers_setup(&spi->ctx, tx_bufs, tx_count,
+				  rx_bufs, rx_count, spi->dfs);
 
 	spi->fifo_diff = 0;
 
@@ -317,23 +320,31 @@ out:
 }
 
 static int spi_dw_transceive(struct spi_config *config,
-			     const struct spi_buf **tx_bufs,
-			     struct spi_buf **rx_bufs)
+			     const struct spi_buf *tx_bufs,
+			     size_t tx_count,
+			     struct spi_buf *rx_bufs,
+			     size_t rx_count)
 {
-	SYS_LOG_DBG("%p, %p, %p", config->dev, tx_bufs, rx_bufs);
+	SYS_LOG_DBG("%p, %p (%zu), %p (%zu)",
+		    config->dev, tx_bufs, tx_count, rx_bufs, rx_count);
 
-	return transceive(config, tx_bufs, rx_bufs, false, NULL);
+	return transceive(config, tx_bufs, tx_count,
+			  rx_bufs, rx_count, false, NULL);
 }
 
 #ifdef CONFIG_POLL
 static int spi_dw_transceive_async(struct spi_config *config,
-				   const struct spi_buf **tx_bufs,
-				   struct spi_buf **rx_bufs,
+				   const struct spi_buf *tx_bufs,
+				   size_t tx_count,
+				   struct spi_buf *rx_bufs,
+				   size_t rx_count,
 				   struct k_poll_signal *async)
 {
-	SYS_LOG_DBG("%p, %p, %p, %p", config->dev, tx_bufs, rx_bufs, async);
+	SYS_LOG_DBG("%p, %p (%zu), %p (%zu), %p",
+		    config->dev, tx_bufs, tx_count, rx_bufs, rx_count, async);
 
-	return transceive(config, tx_bufs, rx_bufs, true, async);
+	return transceive(config, tx_bufs, tx_count,
+			  rx_bufs, rx_count, true, async);
 }
 #endif /* CONFIG_POLL */
 

drivers/spi/spi_mcux_dspi.c

@@ -77,6 +77,10 @@ static int spi_mcux_configure(struct device *dev, struct spi_config *spi_config)
 		    word_size, spi_config->max_sys_freq);
 
 	clock_freq = CLOCK_GetFreq(config->clock_source);
+	if (!clock_freq) {
+		SYS_LOG_ERR("Got frequency of 0");
+		return -EINVAL;
+	}
 	DSPI_MasterInit(base, &master_config, clock_freq);
 
 	DSPI_MasterTransferCreateHandle(base, &data->handle,

drivers/timer/nrf_rtc_timer.c

@@ -308,12 +308,21 @@ int _sys_clock_driver_init(struct device *device)
 u32_t _timer_cycle_get_32(void)
 {
 	u32_t elapsed_cycles;
+	u32_t sys_clock_tick_count;
+	u32_t rtc_prev;
+	u32_t rtc_now;
 
-	elapsed_cycles = (RTC_COUNTER -
-			  (_sys_clock_tick_count * RTC_TICKS_PER_SYS_TICK))
-			  & RTC_MASK;
+	rtc_now = RTC_COUNTER;
+	do {
+		sys_clock_tick_count = _sys_clock_tick_count;
+		elapsed_cycles = (rtc_now - (sys_clock_tick_count *
+					     RTC_TICKS_PER_SYS_TICK)) &
+				 RTC_MASK;
+		rtc_prev = rtc_now;
+		rtc_now = RTC_COUNTER;
+	} while (rtc_now != rtc_prev);
 
-	return (_sys_clock_tick_count * sys_clock_hw_cycles_per_tick) +
+	return (sys_clock_tick_count * sys_clock_hw_cycles_per_tick) +
 	       elapsed_cycles;
 }
 

drivers/watchdog/Kconfig.sam

@@ -7,7 +7,7 @@
 
 menuconfig WDT_SAM
 	bool "Atmel SAM MCU Family Watchdog (WDT) Driver"
-	depends on SOC_SERIES_SAME70
+	depends on SOC_FAMILY_SAM
 	default y
 	help
 	  Enable WDT driver for Atmel SAM MCUs.

dts/arm/96b_carbon.dts

@@ -8,8 +8,8 @@
 #include <st/stm32f401.dtsi>
 
 / {
-	model = "STMicroelectronics STM32F401RE-NUCLEO board";
-	compatible = "st,stm32f401re-nucleo", "st,stm32f401";
+	model = "Seeed Studio Carbon 96boards";
+	compatible = "seeed,carbon", "st,stm32f401";
 
 	chosen {
 		zephyr,console = &usart1;

dts/arm/atmel/sam3x.dtsi

@@ -35,5 +35,5 @@
 };
 
 &nvic {
-	arm,num-irq-priority-bits = <3>;
+	arm,num-irq-priority-bits = <4>;
 };

dts/arm/atmel/same70_mem.h

@@ -1,3 +1,10 @@
+/*
+ * Copyright (c) 2017 Piotr Mienkowski
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
 #ifndef __DT_BINDING_SAME70_MEM_H
 #define __DT_BINDING_SAME70_MEM_H
 

dts/arm/nordic/mem.h

@@ -1,3 +1,8 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef __DT_BINDING_ST_MEM_H
 #define __DT_BINDING_ST_MEM_H
 

dts/arm/st/mem.h

@@ -1,3 +1,8 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef __DT_BINDING_ST_MEM_H
 #define __DT_BINDING_ST_MEM_H
 

dts/arm/ti/mem.h

@@ -1,3 +1,9 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 #ifndef __DT_BINDING_TI_MEM_H
 #define __DT_BINDING_TI_MEM_H
 

dts/common/yaml/device_node.yaml.template

@@ -0,0 +1,51 @@
+---
+title: <Title should describe what node you are describing>
+version: 0.1
+
+description: >
+    Describe in free form text w/ spanning lines what you
+    are describing
+
+# properties will be the contents of the device tree node
+# property names must match the property names in the DT
+
+properties:
+
+# A typical property entry will look like the following
+# - <name of property as it is in device tree>
+#     category: <required | optional>
+#     type: <string | int | array>
+#     description: <description of property>
+#     generation: <define | structure>
+
+# At a minimum, the compatible is required for matching nodes
+  - compatible: <list of string compatible matches>
+      category: required
+      type: string
+      description: compatible of node
+
+# reg is used to denote mmio registers
+  - reg:
+      type: array
+      description: mmio register space
+      generation: define
+      category: required
+
+# interrupts specifies the interrupts that the driver may utilize
+  - interrupts:
+      type: array
+      category: required
+      description: required interrupts
+      generation: define
+
+# If a node is a interrupt controller, gpio controller, pinmux device
+# or any device which is referenced via phandle plus some number of cells
+# then the cell fiels below must be present.
+cell_string: <cell string prefix>
+
+"#cells":
+  - cell0    # name of first cell
+  - cell1    # name of second cell
+  - cell2    # name of third cell
+  - and so on and so forth
+...

include/arch/arm/cortex_m/error.h

@@ -35,8 +35,18 @@ extern void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF *esf);
 #define _SVC_CALL_IRQ_OFFLOAD		1
 #define _SVC_CALL_RUNTIME_EXCEPT	2
 
+#if defined(CONFIG_ARMV6_M)
+/* ARMv6 will hard-fault if SVC is called with interrupts locked. Just
+ * force them unlocked, the thread is in an undefined state anyway
+ *
+ * On ARMv7m we won't get a hardfault, but if interrupts were locked the
+ * thread will continue executing after the exception and forbid PendSV to
+ * schedule a new thread until they are unlocked which is not what we want.
+ * Force them unlocked as well.
+ */
 #define _ARCH_EXCEPT(reason_p) do { \
 	__asm__ volatile ( \
+		"cpsie i\n\t" \
 		"mov r0, %[reason]\n\t" \
 		"svc %[id]\n\t" \
 		: \
@@ -44,6 +54,21 @@ extern void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF *esf);
 		: "memory"); \
 	CODE_UNREACHABLE; \
 } while (0)
+#elif defined(CONFIG_ARMV7_M)
+#define _ARCH_EXCEPT(reason_p) do { \
+	__asm__ volatile ( \
+		"eors.n r0, r0\n\t" \
+		"msr BASEPRI, r0\n\t" \
+		"mov r0, %[reason]\n\t" \
+		"svc %[id]\n\t" \
+		: \
+		: [reason] "i" (reason_p), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \
+		: "memory"); \
+	CODE_UNREACHABLE; \
+} while (0)
+#else
+#error Unknown ARM architecture
+#endif /* CONFIG_ARMV6_M */
 
 #ifdef __cplusplus
 }

include/arch/arm/cortex_m/mpu/arm_mpu.h

@@ -44,6 +44,9 @@ struct arm_mpu {
 #define ARM_MPU_PRIVDEFENA	(1 << 2)
 
 #define REGION_VALID	(1 << 4)
+/* ARM MPU RBAR Register */
+/* Region base address mask */
+#define REGION_BASE_ADDR_MASK	0xFFFFFFE0
 
 /* eXecute Never */
 #define NOT_EXEC        (0x1 << 28)

include/arch/arm/cortex_m/mpu/nxp_mpu.h

@@ -13,23 +13,70 @@
 
 #define NXP_MPU_REGION_NUMBER 12
 
+/* Bus Master User Mode Access */
+#define UM_READ		4
+#define UM_WRITE	2
+#define UM_EXEC		1
+
+#define BM0_UM_SHIFT	0
+#define BM1_UM_SHIFT	6
+#define BM2_UM_SHIFT	12
+#define BM3_UM_SHIFT	18
+
+/* Bus Master Supervisor Mode Access */
+#define SM_RWX_ALLOW	0
+#define SM_RX_ALLOW	1
+#define SM_RW_ALLOW	2
+#define SM_SAME_AS_UM	3
+
+#define BM0_SM_SHIFT	3
+#define BM1_SM_SHIFT	9
+#define BM2_SM_SHIFT	15
+#define BM3_SM_SHIFT	21
+
 /* Read Attribute */
-#define MPU_REGION_READ  ((1 << 2) | (1 << 8) | (1 << 14))
+#define MPU_REGION_READ  ((UM_READ << BM0_UM_SHIFT) | \
+			  (UM_READ << BM1_UM_SHIFT) | \
+			  (UM_READ << BM2_UM_SHIFT) | \
+			  (UM_READ << BM3_UM_SHIFT))
 
 /* Write Attribute */
-#define MPU_REGION_WRITE ((1 << 1) | (1 << 7) | (1 << 13))
+#define MPU_REGION_WRITE ((UM_WRITE << BM0_UM_SHIFT) | \
+			  (UM_WRITE << BM1_UM_SHIFT) | \
+			  (UM_WRITE << BM2_UM_SHIFT) | \
+			  (UM_WRITE << BM3_UM_SHIFT))
 
 /* Execute Attribute */
-#define MPU_REGION_EXEC  ((1 << 0) | (1 << 6) | (1 << 12))
+#define MPU_REGION_EXEC  ((UM_EXEC << BM0_UM_SHIFT) | \
+			  (UM_EXEC << BM1_UM_SHIFT) | \
+			  (UM_EXEC << BM2_UM_SHIFT) | \
+			  (UM_EXEC << BM3_UM_SHIFT))
 
 /* Super User Attributes */
-#define MPU_REGION_SU    ((3 << 3) | (3 << 9) | (3 << 15) | (3 << 21))
+#define MPU_REGION_SU	 ((SM_SAME_AS_UM << BM0_SM_SHIFT) | \
+			  (SM_SAME_AS_UM << BM1_SM_SHIFT) | \
+			  (SM_SAME_AS_UM << BM2_SM_SHIFT) | \
+			  (SM_SAME_AS_UM << BM3_SM_SHIFT))
+
+/* The ENDADDR field has the last 5 bit reserved and set to 1 */
+#define ENDADDR_ROUND(x) (x - 0x1F)
 
 /* Some helper defines for common regions */
-#define REGION_RAM_ATTR	(MPU_REGION_READ | MPU_REGION_WRITE | MPU_REGION_SU)
-#define REGION_FLASH_ATTR (MPU_REGION_READ | MPU_REGION_EXEC | MPU_REGION_SU)
-#define REGION_IO_ATTR (MPU_REGION_READ | MPU_REGION_WRITE | \
-			MPU_REGION_EXEC |  MPU_REGION_SU)
+#define REGION_RAM_ATTR	  (MPU_REGION_READ | \
+			   MPU_REGION_WRITE | \
+			   MPU_REGION_SU)
+
+#define REGION_FLASH_ATTR (MPU_REGION_READ | \
+			   MPU_REGION_EXEC | \
+			   MPU_REGION_SU)
+
+#define REGION_IO_ATTR	  (MPU_REGION_READ | \
+			   MPU_REGION_WRITE | \
+			   MPU_REGION_EXEC | \
+			   MPU_REGION_SU)
+
+#define REGION_RO_ATTR	  (MPU_REGION_READ | \
+			   MPU_REGION_SU)
 
 /* Region definition data structure */
 struct nxp_mpu_region {
@@ -57,6 +104,8 @@ struct nxp_mpu_config {
 	u32_t num_regions;
 	/* Regions */
 	struct nxp_mpu_region *mpu_regions;
+	/* SRAM Region */
+	u32_t sram_region;
 };
 
 /* Reference to the MPU configuration */

include/bluetooth/gatt.h

@@ -1026,7 +1026,8 @@ int bt_gatt_subscribe(struct bt_conn *conn,
  *
  * This procedure unsubscribe to value notification using the Client
  * Characteristic Configuration handle. Notification callback with NULL data
- * will not be called if subscription was removed by this call.
+ * will be called if subscription was removed by this call, until then the
+ * parameters cannot be reused.
  *
  * @param conn Connection object.
  * @param params Subscribe parameters.

include/misc/stack.h

@@ -9,6 +9,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#ifndef _MISC_STACK_H_
+#define _MISC_STACK_H_
+
 #include <misc/printk.h>
 
 #if defined(CONFIG_INIT_STACKS)
@@ -69,3 +72,5 @@ static inline void stack_analyze(const char *name, const char *stack,
 {
 }
 #endif
+
+#endif /* _MISC_STACK_H_ */

include/net/http.h

@@ -567,6 +567,13 @@ struct http_server_ctx {
 		/** From which net_context the request came from */
 		struct net_context *net_ctx;
 
+		/** HTTP request timer. After sending a response to the
+		 * client, it is possible to wait for any request back via
+		 * the same socket. If no response is received, then this
+		 * timeout is activated and connection is tore down.
+		 */
+		struct k_delayed_work timer;
+
 		/** HTTP parser */
 		struct http_parser parser;
 
@@ -596,6 +603,9 @@ struct http_server_ctx {
 
 		/** URL's length */
 		u16_t url_len;
+
+		/** Has the request timer been cancelled. */
+		u8_t timer_cancelled;
 	} req;
 
 #if defined(CONFIG_HTTPS)
@@ -833,6 +843,25 @@ int http_server_del_default(struct http_server_urls *urls);
 /**
  * @brief Send HTTP response to client.
  *
+ * @detail After sending a response, an optional timeout is started
+ * which will wait for any new requests from the peer.
+ *
+ * @param ctx HTTP context.
+ * @param http_header HTTP headers to send.
+ * @param html_payload HTML payload to send.
+ * @param timeout Timeout to wait until the connection is shutdown.
+ *
+ * @return 0 if ok, <0 if error.
+ */
+int http_response_wait(struct http_server_ctx *ctx, const char *http_header,
+		       const char *html_payload, s32_t timeout);
+
+/**
+ * @brief Send HTTP response to client.
+ *
+ * @detail The connection to peer is torn down right after the response
+ * is sent.
+ *
  * @param ctx HTTP context.
  * @param http_header HTTP headers to send.
  * @param html_payload HTML payload to send.

include/net/net_core.h

@@ -134,7 +134,7 @@ struct net_stack_info {
 #if defined(CONFIG_INIT_STACKS)
 #include <misc/stack.h>
 
-static inline void net_analyze_stack_get_values(unsigned char *stack,
+static inline void net_analyze_stack_get_values(const char *stack,
 						size_t size,
 						unsigned *pcnt,
 						unsigned *unused)
@@ -146,7 +146,7 @@ static inline void net_analyze_stack_get_values(unsigned char *stack,
 }
 
 static inline void net_analyze_stack(const char *name,
-				     unsigned char *stack,
+				     const char *stack,
 				     size_t size)
 {
 	unsigned int pcnt, unused;

include/net/zoap.h

@@ -16,6 +16,7 @@
 #include <zephyr/types.h>
 #include <stddef.h>
 #include <stdbool.h>
+#include <net/net_ip.h>
 
 #include <misc/slist.h>
 

include/spi.h

@@ -190,8 +190,10 @@ struct spi_buf {
  * See spi_transceive() for argument descriptions
  */
 typedef int (*spi_api_io)(struct spi_config *config,
-			  const struct spi_buf **tx_bufs,
-			  struct spi_buf **rx_bufs);
+			  const struct spi_buf *tx_bufs,
+			  size_t tx_count,
+			  struct spi_buf *rx_bufs,
+			  size_t rx_count);
 
 /**
  * @typedef spi_api_io
@@ -199,8 +201,10 @@ typedef int (*spi_api_io)(struct spi_config *config,
  * See spi_transceive_async() for argument descriptions
  */
 typedef int (*spi_api_io_async)(struct spi_config *config,
-				const struct spi_buf **tx_bufs,
-				struct spi_buf **rx_bufs,
+				const struct spi_buf *tx_bufs,
+				size_t tx_count,
+				struct spi_buf *rx_bufs,
+				size_t rx_count,
 				struct k_poll_signal *async);
 
 /**
@@ -229,20 +233,24 @@ struct spi_driver_api {
  * Note: This function is synchronous.
  *
  * @param config Pointer to a valid spi_config structure instance.
- * @param tx_bufs NULL terminated buffer array where data to be sent
- *        originates from, or NULL if none.
- * @param rx_bufs NULL terminated buffer array where data to be read
- *        will be written to, or NULL if none.
+ * @param tx_bufs Buffer array where data to be sent originates from,
+ *        or NULL if none.
+ * @param tx_count Number of element in the tx_bufs array.
+ * @param rx_bufs Buffer array where data to be read will be written to,
+ *        or NULL if none.
+ * @param rx_count Number of element in the rx_bufs array.
  *
  * @retval 0 If successful, negative errno code otherwise.
  */
 static inline int spi_transceive(struct spi_config *config,
-				 const struct spi_buf **tx_bufs,
-				 struct spi_buf **rx_bufs)
+				 const struct spi_buf *tx_bufs,
+				 size_t tx_count,
+				 struct spi_buf *rx_bufs,
+				 size_t rx_count)
 {
 	const struct spi_driver_api *api = config->dev->driver_api;
 
-	return api->transceive(config, tx_bufs, rx_bufs);
+	return api->transceive(config, tx_bufs, tx_count, rx_bufs, rx_count);
 }
 
 /**
@@ -251,17 +259,18 @@ static inline int spi_transceive(struct spi_config *config,
  * Note: This function is synchronous.
  *
  * @param config Pointer to a valid spi_config structure instance.
- * @param rx_bufs NULL terminated buffer array where data to be read
- *        will be written to.
+ * @param rx_bufs Buffer array where data to be read will be written to.
+ * @param rx_count Number of element in the rx_bufs array.
  *
  * @retval 0 If successful, negative errno code otherwise.
  */
 static inline int spi_read(struct spi_config *config,
-			   struct spi_buf **rx_bufs)
+			   struct spi_buf *rx_bufs,
+			   size_t rx_count)
 {
 	const struct spi_driver_api *api = config->dev->driver_api;
 
-	return api->transceive(config, NULL, rx_bufs);
+	return api->transceive(config, NULL, 0, rx_bufs, rx_count);
 }
 
 /**
@@ -270,17 +279,18 @@ static inline int spi_read(struct spi_config *config,
  * Note: This function is synchronous.
  *
  * @param config Pointer to a valid spi_config structure instance.
- * @param tx_bufs NULL terminated buffer array where data to be sent
- *        originates from.
+ * @param tx_bufs Buffer array where data to be sent originates from.
+ * @param tx_count Number of element in the tx_bufs array.
  *
  * @retval 0 If successful, negative errno code otherwise.
  */
 static inline int spi_write(struct spi_config *config,
-			    const struct spi_buf **tx_bufs)
+			    const struct spi_buf *tx_bufs,
+			    size_t tx_count)
 {
 	const struct spi_driver_api *api = config->dev->driver_api;
 
-	return api->transceive(config, tx_bufs, NULL);
+	return api->transceive(config, tx_bufs, tx_count, NULL, 0);
 }
 
 #ifdef CONFIG_POLL
@@ -290,10 +300,12 @@ static inline int spi_write(struct spi_config *config,
  * Note: This function is asynchronous.
  *
  * @param config Pointer to a valid spi_config structure instance.
- * @param tx_bufs NULL terminated buffer array where data to be sent
- *        originates from, or NULL if none.
- * @param rx_bufs NULL terminated buffer array where data to be read
- *        will be written to, or NULL if none.
+ * @param tx_bufs Buffer array where data to be sent originates from,
+ *        or NULL if none.
+ * @param tx_count Number of element in the tx_bufs array.
+ * @param rx_bufs Buffer array where data to be read will be written to,
+ *        or NULL if none.
+ * @param rx_count Number of element in the rx_bufs array.
  * @param async A pointer to a valid and ready to be signaled
  *        struct k_poll_signal. (Note: if NULL this function will not
  *        notify the end of the transaction, and whether it went
@@ -302,13 +314,16 @@ static inline int spi_write(struct spi_config *config,
  * @retval 0 If successful, negative errno code otherwise.
  */
 static inline int spi_transceive_async(struct spi_config *config,
-				       const struct spi_buf **tx_bufs,
-				       struct spi_buf **rx_bufs,
+				       const struct spi_buf *tx_bufs,
+				       size_t tx_count,
+				       struct spi_buf *rx_bufs,
+				       size_t rx_count,
 				       struct k_poll_signal *async)
 {
 	const struct spi_driver_api *api = config->dev->driver_api;
 
-	return api->transceive_async(config, tx_bufs, rx_bufs, async);
+	return api->transceive_async(config, tx_bufs, tx_count,
+				     rx_bufs, rx_count, async);
 }
 
 /**
@@ -317,8 +332,8 @@ static inline int spi_transceive_async(struct spi_config *config,
  * Note: This function is asynchronous.
  *
  * @param config Pointer to a valid spi_config structure instance.
- * @param rx_bufs NULL terminated buffer array where data to be read
- *        will be written to.
+ * @param rx_bufs Buffer array where data to be read will be written to.
+ * @param rx_count Number of element in the rx_bufs array.
  * @param async A pointer to a valid and ready to be signaled
  *        struct k_poll_signal. (Note: if NULL this function will not
  *        notify the end of the transaction, and whether it went
@@ -327,12 +342,14 @@ static inline int spi_transceive_async(struct spi_config *config,
  * @retval 0 If successful, negative errno code otherwise.
  */
 static inline int spi_read_async(struct spi_config *config,
-				 struct spi_buf **rx_bufs,
+				 struct spi_buf *rx_bufs,
+				 size_t rx_count,
 				 struct k_poll_signal *async)
 {
 	const struct spi_driver_api *api = config->dev->driver_api;
 
-	return api->transceive_async(config, NULL, rx_bufs, async);
+	return api->transceive_async(config, NULL, 0,
+				     rx_bufs, rx_count, async);
 }
 
 /**
@@ -341,8 +358,8 @@ static inline int spi_read_async(struct spi_config *config,
  * Note: This function is asynchronous.
  *
  * @param config Pointer to a valid spi_config structure instance.
- * @param tx_bufs NULL terminated buffer array where data to be sent
- *        originates from.
+ * @param tx_bufs Buffer array where data to be sent originates from.
+ * @param tx_count Number of element in the tx_bufs array.
  * @param async A pointer to a valid and ready to be signaled
  *        struct k_poll_signal. (Note: if NULL this function will not
  *        notify the end of the transaction, and whether it went
@@ -351,12 +368,14 @@ static inline int spi_read_async(struct spi_config *config,
  * @retval 0 If successful, negative errno code otherwise.
  */
 static inline int spi_write_async(struct spi_config *config,
-				  const struct spi_buf **tx_bufs,
+				  const struct spi_buf *tx_bufs,
+				  size_t tx_count,
 				  struct k_poll_signal *async)
 {
 	const struct spi_driver_api *api = config->dev->driver_api;
 
-	return api->transceive_async(config, tx_bufs, NULL, async);
+	return api->transceive_async(config, tx_bufs, tx_count,
+				     NULL, 0, async);
 }
 #endif /* CONFIG_POLL */
 

include/uart.h

@@ -241,6 +241,15 @@ static inline unsigned char uart_poll_out(struct device *dev,
 /**
  * @brief Fill FIFO with data.
  *
+ * @details This function is expected to be called from UART
+ * interrupt handler (ISR), if uart_irq_tx_ready() returns true.
+ * Result of calling this function not from an ISR is undefined
+ * (hardware-dependent). Likewise, *not* calling this function
+ * from an ISR if uart_irq_tx_ready() returns true may lead to
+ * undefined behavior, e.g. infinite interrupt loops. It's
+ * mandatory to test return value of this function, as different
+ * hardware has different FIFO depth (oftentimes just 1).
+ *
  * @param dev UART device structure.
  * @param tx_data Data to transmit.
  * @param size Number of bytes to send.
@@ -262,6 +271,16 @@ static inline int uart_fifo_fill(struct device *dev, const u8_t *tx_data,
 /**
  * @brief Read data from FIFO.
  *
+ * @details This function is expected to be called from UART
+ * interrupt handler (ISR), if uart_irq_rx_ready() returns true.
+ * Result of calling this function not from an ISR is undefined
+ * (hardware-dependent). It's unspecified whether "RX ready"
+ * condition as returned by uart_irq_rx_ready() is level- or
+ * edge- triggered. That means that once uart_irq_rx_ready() is
+ * detected, uart_fifo_read() must be called until it reads all
+ * available data in the FIFO (i.e. until it returns less data
+ * than was requested).
+ *
  * @param dev UART device structure.
  * @param rx_data Data container.
  * @param size Container size.
@@ -406,16 +425,21 @@ static inline int __deprecated uart_irq_tx_empty(struct device *dev)
 }
 
 /**
- * @brief Check if UART RX buffer has a new char
+ * @brief Check if UART RX buffer has a received char
  *
+ * @details Check if UART RX buffer has at least one pending character
  * (i.e. uart_fifo_read() will succeed and return non-zero). This function
  * must be called in a UART interrupt handler, or its result is undefined.
  * Before calling this function in the interrupt handler, uart_irq_update()
- * must be called once per the handler invocation.
+ * must be called once per the handler invocation. It's unspecified whether
+ * condition as returned by this function is level- or edge- triggered (i.e.
+ * if this function returns true when RX FIFO is non-empty, or when a new
+ * char was received since last call to it). See description of
+ * uart_fifo_read() for implication of this.
  *
  * @param dev UART device structure.
  *
- * @retval 1 If a new received char is ready.
+ * @retval 1 If a received char is ready.
  * @retval 0 Otherwise.
  */
 static inline int uart_irq_rx_ready(struct device *dev)

kernel/include/ksched.h

@@ -31,9 +31,6 @@ extern void _update_time_slice_before_swap(void);
 extern s32_t _ms_to_ticks(s32_t ms);
 #endif
 extern void idle(void *, void *, void *);
-#ifdef CONFIG_STACK_SENTINEL
-extern void _check_stack_sentinel(void);
-#endif
 
 /* find which one is the next thread to run */
 /* must be called with interrupts locked */

kernel/include/nano_internal.h

@@ -52,19 +52,27 @@ extern void _new_thread(struct k_thread *thread, char *pStack, size_t stackSize,
 
 extern unsigned int __swap(unsigned int key);
 
-#if defined(CONFIG_TICKLESS_KERNEL) && defined(CONFIG_TIMESLICING)
+#ifdef CONFIG_TIMESLICING
 extern void _update_time_slice_before_swap(void);
+#endif
 
-static inline unsigned int _time_slice_swap(unsigned int key)
+#ifdef CONFIG_STACK_SENTINEL
+extern void _check_stack_sentinel(void);
+#endif
+
+static inline unsigned int _Swap(unsigned int key)
 {
+
+#ifdef CONFIG_STACK_SENTINEL
+	_check_stack_sentinel();
+#endif
+#ifdef CONFIG_TIMESLICING
 	_update_time_slice_before_swap();
+#endif
+
 	return __swap(key);
 }
 
-#define _Swap(x)  _time_slice_swap(x)
-#else
-#define _Swap(x)  __swap(x)
-#endif
 /* set and clear essential fiber/task flag */
 
 extern void _thread_essential_set(void);

kernel/sched.c

@@ -397,7 +397,6 @@ void k_sched_time_slice_set(s32_t duration_in_ms, int prio)
 	_time_slice_prio_ceiling = prio;
 }
 
-#ifdef CONFIG_TICKLESS_KERNEL
 int _is_thread_time_slicing(struct k_thread *thread)
 {
 	/*
@@ -424,21 +423,20 @@ int _is_thread_time_slicing(struct k_thread *thread)
 /* Should be called only immediately before a thread switch */
 void _update_time_slice_before_swap(void)
 {
+#ifdef CONFIG_TICKLESS_KERNEL
 	if (!_is_thread_time_slicing(_get_next_ready_thread())) {
 		return;
 	}
 
-	/* Restart time slice count at new thread switch */
-	_time_slice_elapsed = 0;
-
 	u32_t remaining = _get_remaining_program_time();
 
 	if (!remaining || (_time_slice_duration < remaining)) {
 		_set_time(_time_slice_duration);
 	}
-}
 #endif
-
+	/* Restart time slice count at new thread switch */
+	_time_slice_elapsed = 0;
+}
 #endif /* CONFIG_TIMESLICING */
 
 int k_is_preempt_thread(void)

kernel/sys_clock.c

@@ -307,18 +307,10 @@ static void handle_time_slicing(s32_t ticks)
 {
 #ifdef CONFIG_TICKLESS_KERNEL
 	next_ts = 0;
+#endif
 	if (!_is_thread_time_slicing(_current)) {
 		return;
 	}
-#else
-	if (_time_slice_duration == 0) {
-		return;
-	}
-
-	if (_is_prio_higher(_current->base.prio, _time_slice_prio_ceiling)) {
-		return;
-	}
-#endif
 
 	_time_slice_elapsed += __ticks_to_ms(ticks);
 	if (_time_slice_elapsed >= _time_slice_duration) {

kernel/thread.c

@@ -141,12 +141,11 @@ void _thread_monitor_exit(struct k_thread *thread)
  * in a few places:
  *
  * 1) In k_yield() if the current thread is not swapped out
- * 2) In the interrupt code, after the interrupt has been serviced, and
- *    a decision *not* to call _Swap() has been made.
+ * 2) After servicing a non-nested interrupt
  * 3) In _Swap(), check the sentinel in the outgoing thread
  * 4) When a thread returns from its entry function to cooperatively terminate
  *
- * Items 2 and 3 require support in arch/ code.
+ * Item 2 requires support in arch/ code.
  *
  * If the check fails, the thread will be terminated appropriately through
  * the system fatal error handler.

lib/json/json.h

@@ -154,7 +154,8 @@ typedef int (*json_append_bytes_t)(const u8_t *bytes, size_t len,
  *      };
  *
  *      struct json_obj_descr array[] = {
- *           JSON_OBJ_DESCR_ARRAY(struct example, foo, JSON_TOK_NUMBER)
+ *           JSON_OBJ_DESCR_ARRAY(struct example, foo, 10, foo_len,
+ *                                JSON_TOK_NUMBER)
  *      };
  */
 #define JSON_OBJ_DESCR_ARRAY(struct_, field_name_, max_len_, \
@@ -171,6 +172,95 @@ typedef int (*json_append_bytes_t)(const u8_t *bytes, size_t len,
 		.n_elements = (max_len_), \
 	}
 
+/**
+ * @brief Variant of JSON_OBJ_DESCR_PRIM that can be used when the
+ *        structure and JSON field names differ.
+ *
+ * This is useful when the JSON field is not a valid C identifier.
+ *
+ * @param struct_ Struct packing the values.
+ *
+ * @param json_field_name_ String, field name in JSON strings
+ *
+ * @param struct_field_name_ Field name in the struct
+ *
+ * @param type_ Token type for JSON value corresponding to a primitive
+ * type.
+ *
+ * @see JSON_OBJ_DESCR_PRIM
+ */
+#define JSON_OBJ_DESCR_PRIM_NAMED(struct_, json_field_name_, \
+				  struct_field_name_, type_) \
+	{ \
+		.field_name = (json_field_name_), \
+		.field_name_len = sizeof(json_field_name_) - 1, \
+		.offset = offsetof(struct_, struct_field_name_), \
+		.type = type_, \
+	}
+
+/**
+ * @brief Variant of JSON_OBJ_DESCR_OBJECT that can be used when the
+ *        structure and JSON field names differ.
+ *
+ * This is useful when the JSON field is not a valid C identifier.
+ *
+ * @param struct_ Struct packing the values
+ *
+ * @param json_field_name_ String, field name in JSON strings
+ *
+ * @param struct_field_name_ Field name in the struct
+ *
+ * @param sub_descr_ Array of json_obj_descr describing the subobject
+ *
+ * @see JSON_OBJ_DESCR_OBJECT
+ */
+#define JSON_OBJ_DESCR_OBJECT_NAMED(struct_, json_field_name_, \
+				    struct_field_name_, sub_descr_) \
+	{ \
+		.field_name = (json_field_name_), \
+		.field_name_len = (sizeof(json_field_name_) - 1), \
+		.offset = offsetof(struct_, struct_field_name_), \
+		.type = JSON_TOK_OBJECT_START, \
+		.sub_descr = sub_descr_, \
+		.sub_descr_len = ARRAY_SIZE(sub_descr_) \
+	}
+
+/**
+ * @brief Variant of JSON_OBJ_DESCR_ARRAY that can be used when the
+ *        structure and JSON field names differ.
+ *
+ * This is useful when the JSON field is not a valid C identifier.
+ *
+ * @param struct_ Struct packing the values
+ *
+ * @param json_field_name_ String, field name in JSON strings
+ *
+ * @param struct_field_name_ Field name in the struct
+ *
+ * @param max_len_ Maximum number of elements in array
+ *
+ * @param len_field_ Field name in the struct for the number of elements
+ * in the array
+ *
+ * @param elem_type_ Element type
+ *
+ * @see JSON_OBJ_DESCR_ARRAY
+ */
+#define JSON_OBJ_DESCR_ARRAY_NAMED(struct_, json_field_name_,\
+				   struct_field_name_, max_len_, len_field_, \
+				   elem_type_) \
+	{ \
+		.field_name = (json_field_name_), \
+		.field_name_len = sizeof(json_field_name_) - 1, \
+		.offset = offsetof(struct_, struct_field_name_), \
+		.type = JSON_TOK_LIST_START, \
+		.element_descr = &(struct json_obj_descr) { \
+			.type = elem_type_, \
+			.offset = offsetof(struct_, len_field_), \
+		}, \
+		.n_elements = (max_len_), \
+	}
+
 /**
  * @brief Parses the JSON-encoded object pointer to by @param json, with
  * size @param len, according to the descriptor pointed to by @param descr.

misc/printk.c

@@ -90,6 +90,7 @@ void _vprintk(out_func_t out, void *ctx, const char *fmt, va_list ap)
 	int might_format = 0; /* 1 if encountered a '%' */
 	enum pad_type padding = PAD_NONE;
 	int min_width = -1;
+	int long_ctr = 0;
 
 	/* fmt has already been adjusted if needed */
 
@@ -101,6 +102,7 @@ void _vprintk(out_func_t out, void *ctx, const char *fmt, va_list ap)
 				might_format = 1;
 				min_width = -1;
 				padding = PAD_NONE;
+				long_ctr = 0;
 			}
 		} else {
 			switch (*fmt) {
@@ -124,14 +126,21 @@ void _vprintk(out_func_t out, void *ctx, const char *fmt, va_list ap)
 					padding = PAD_SPACE_BEFORE;
 				}
 				goto still_might_format;
-			case 'z':
 			case 'l':
+				long_ctr++;
+				/* Fall through */
+			case 'z':
 			case 'h':
 				/* FIXME: do nothing for these modifiers */
 				goto still_might_format;
 			case 'd':
 			case 'i': {
-				long d = va_arg(ap, long);
+				long d;
+				if (long_ctr < 2) {
+					d = va_arg(ap, long);
+				} else {
+					d = (long)va_arg(ap, long long);
+				}
 
 				if (d < 0) {
 					out((int)'-', ctx);
@@ -143,8 +152,14 @@ void _vprintk(out_func_t out, void *ctx, const char *fmt, va_list ap)
 				break;
 			}
 			case 'u': {
-				unsigned long u = va_arg(
-					ap, unsigned long);
+				unsigned long u;
+
+				if (long_ctr < 2) {
+					u = va_arg(ap, unsigned long);
+				} else {
+					u = (unsigned long)va_arg(ap,
+							unsigned long long);
+				}
 				_printk_dec_ulong(out, ctx, u, padding,
 						  min_width);
 				break;
@@ -158,8 +173,15 @@ void _vprintk(out_func_t out, void *ctx, const char *fmt, va_list ap)
 				  /* Fall through */
 			case 'x':
 			case 'X': {
-				unsigned long x = va_arg(
-					ap, unsigned long);
+				unsigned long x;
+
+				if (long_ctr < 2) {
+					x = va_arg(ap, unsigned long);
+				} else {
+					x = (unsigned long)va_arg(ap,
+							unsigned long long);
+				}
+
 				_printk_hex_ulong(out, ctx, x, padding,
 						  min_width);
 				break;

samples/bluetooth/eddystone/README.rst

@@ -5,7 +5,7 @@ Bluetooth: Eddystone
 
 Overview
 ********
-Application demostrating `Eddystone Configuration Service`_
+Application demonstrating `Eddystone Configuration Service`_
 
 The Eddystone Configuration Service runs as a GATT service on the beacon while
 it is connectable and allows configuration of the advertised data, the

samples/cpp_synchronization/Makefile

@@ -0,0 +1,5 @@
+BOARD ?= qemu_x86
+CONF_FILE = prj.conf
+
+
+include ${ZEPHYR_BASE}/Makefile.inc

samples/cpp_synchronization/README.txt

@@ -0,0 +1,62 @@
+Title: C++ Synchronization
+
+Description:
+The sample project illustrates usage of pure virtual class, member
+functions with different types of arguments, global objects constructor
+invocation.
+
+A simple application demonstrates basic sanity of the kernel.  The main thread
+and a cooperative thread take turns printing a greeting message to the console,
+and use timers and semaphores to control the rate at which messages are
+generated. This demonstrates that kernel scheduling, communication, and
+timing are operating correctly.
+
+--------------------------------------------------------------------------------
+
+Building and Running Project:
+
+This kernel project outputs to the console.  It can be built and executed
+on QEMU as follows:
+
+    make run
+
+--------------------------------------------------------------------------------
+
+Troubleshooting:
+
+Problems caused by out-dated project information can be addressed by
+issuing one of the following commands then rebuilding the project:
+
+    make clean          # discard results of previous builds
+                        # but keep existing configuration info
+or
+    make pristine       # discard results of previous builds
+                        # and restore pre-defined configuration info
+
+--------------------------------------------------------------------------------
+
+Sample Output:
+
+Create semaphore 0x001042b0
+Create semaphore 0x001042c4
+main: Hello World!
+coop_thread_entry: Hello World!
+main: Hello World!
+coop_thread_entry: Hello World!
+main: Hello World!
+coop_thread_entry: Hello World!
+main: Hello World!
+coop_thread_entry: Hello World!
+main: Hello World!
+coop_thread_entry: Hello World!
+main: Hello World!
+coop_thread_entry: Hello World!
+main: Hello World!
+coop_thread_entry: Hello World!
+main: Hello World!
+coop_thread_entry: Hello World!
+main: Hello World!
+coop_thread_entry: Hello World!
+main: Hello World!
+
+<repeats endlessly>