95 lines
2.4 KiB
C
95 lines
2.4 KiB
C
/*
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* Copyright (c) 2025 Core Devices LLC
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sifli_sf32lb_hxt48
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#include <stdint.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/clock_control.h>
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#include <register.h>
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#define HPSYS_AON_ACR offsetof(HPSYS_AON_TypeDef, ACR)
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struct clock_control_sf32lb_hxt48_config {
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uintptr_t aon;
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uint32_t freq_hz;
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};
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static int clock_control_sf32lb_hxt48_on(const struct device *dev, clock_control_subsys_t sys)
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{
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const struct clock_control_sf32lb_hxt48_config *config = dev->config;
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uint32_t val;
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ARG_UNUSED(sys);
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val = sys_read32(config->aon + HPSYS_AON_ACR);
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val |= HPSYS_AON_ACR_HXT48_REQ;
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sys_write32(val, config->aon + HPSYS_AON_ACR);
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while (sys_test_bit(config->aon + HPSYS_AON_ACR, HPSYS_AON_ACR_HXT48_RDY_Pos) == 0U) {
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}
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return 0;
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}
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static int clock_control_sf32lb_hxt48_off(const struct device *dev, clock_control_subsys_t sys)
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{
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const struct clock_control_sf32lb_hxt48_config *config = dev->config;
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uint32_t val;
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ARG_UNUSED(sys);
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val = sys_read32(config->aon + HPSYS_AON_ACR);
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val &= ~HPSYS_AON_ACR_HXT48_REQ;
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sys_write32(val, config->aon + HPSYS_AON_ACR);
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return 0;
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}
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static enum clock_control_status clock_control_sf32lb_hxt48_get_status(const struct device *dev,
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clock_control_subsys_t sys)
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{
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const struct clock_control_sf32lb_hxt48_config *config = dev->config;
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ARG_UNUSED(sys);
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if (sys_test_bit(config->aon + HPSYS_AON_ACR, HPSYS_AON_ACR_HXT48_RDY_Pos) != 0U) {
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return CLOCK_CONTROL_STATUS_ON;
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}
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return CLOCK_CONTROL_STATUS_OFF;
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}
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static int clock_control_sf32lb_hxt48_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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const struct clock_control_sf32lb_hxt48_config *config = dev->config;
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ARG_UNUSED(sys);
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*rate = config->freq_hz;
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return 0;
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}
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static DEVICE_API(clock_control, clock_control_sf32lb_hxt48_api) = {
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.on = clock_control_sf32lb_hxt48_on,
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.off = clock_control_sf32lb_hxt48_off,
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.get_status = clock_control_sf32lb_hxt48_get_status,
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.get_rate = clock_control_sf32lb_hxt48_get_rate,
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};
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static const struct clock_control_sf32lb_hxt48_config config = {
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.aon = DT_REG_ADDR(DT_INST_PHANDLE(0, sifli_aon)),
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.freq_hz = DT_INST_PROP(0, clock_frequency),
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};
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DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, &config, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_sf32lb_hxt48_api);
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