2bd84a1bc5
Port the only RISC-V SoC from GigaDevice to HWMv2. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
37 lines
818 B
ArmAsm
37 lines
818 B
ArmAsm
/*
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* Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "nuclei_csr.h"
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#include <zephyr/toolchain.h>
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#include <zephyr/arch/riscv/csr.h>
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GTEXT(__nuclei_start)
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SECTION_FUNC(init, __nuclei_start)
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/* Disable Global Interrupt */
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csrc mstatus, MSTATUS_MIE
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/* Jump to logical address first to ensure correct operation of RAM region */
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la a0, __nuclei_start
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li a1, 1
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slli a1, a1, 29 # 0x2000 0000
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bleu a1, a0, _start0800
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srli a1, a1, 2 # 0x0800 0000
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bleu a1, a0, _start0800
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la a0, _start0800
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add a0, a0, a1
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jr a0
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_start0800:
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/* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */
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li t0, 0x200
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csrs CSR_MMISC_CTL, t0
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/* Disable performance counter */
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csrsi mcountinhibit, 0x5
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/* Jump to common start */
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tail __start
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