2bd84a1bc5
Port the only RISC-V SoC from GigaDevice to HWMv2. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
26 lines
770 B
C
26 lines
770 B
C
/*
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* Copyright (c) 2022, Teslabs Engineering S.L.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SOC_ARM_GIGADEVICE_GD32VF103_GD32_REGS_H_
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#define SOC_ARM_GIGADEVICE_GD32VF103_GD32_REGS_H_
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#include <zephyr/sys/util_macro.h>
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/* RCU */
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#define RCU_CFG0_OFFSET 0x04U
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#define RCU_AHBEN_OFFSET 0x14U
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#define RCU_APB2EN_OFFSET 0x18U
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#define RCU_APB1EN_OFFSET 0x1CU
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#define RCU_ADDAPB1EN_OFFSET 0xE4U
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#define RCU_CFG0_AHBPSC_POS 4U
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#define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
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#define RCU_CFG0_APB1PSC_POS 8U
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#define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
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#define RCU_CFG0_APB2PSC_POS 11U
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#define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
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#endif /* SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_ */
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