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Merge tag 'u-boot-imx-next-20250905a' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27573

- Several improvements for kontron-sl-mx6ul.
- Add Phytec imx8mp-libra-fpsc board
- Add redundant environment support for imx8m evk boards.
- Several improvements for phycore-imx93.
This commit is contained in:
Tom Rini
2025-09-05 10:48:05 -06:00
parent e31947724f 28d6f787b0
commit 1116d91596
37 changed files with 2636 additions and 931 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/Makefile
View File

@@ -833,9 +833,7 @@ dtb-$(CONFIG_MX6UL) += \
imx6ul-liteboard.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
imx6ul-kontron-bl.dtb \
imx6ull-kontron-bl.dtb
imx6ul-pico-pi.dtb
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \

103
arch/arm/dts/imx6ul-kontron-bl-43.dts
View File

@@ -1,103 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include "imx6ul-kontron-bl.dts"
/ {
model = "Kontron BL i.MX6UL 43 (N631X S 43)";
compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul",
"kontron,sl-imx6ul", "fsl,imx6ul";
backlight {
compatible = "pwm-backlight";
pwms = <&pwm7 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
};
};
&i2c4 {
touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cap_touch>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
/* Leave status disabled because of missing display panel node */
};
&pwm7 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
status = "okay";
};
&iomuxc {
pinctrl_cap_touch: captouchgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
>;
};
pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
>;
};
};

12
arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi
View File

@@ -30,9 +30,6 @@
* in Linux we can't assign the shared reset GPIO to the PHYs, as this
* would cause Linux to reset both PHYs every time one of them gets
* reinitialized.
*
* Also we disable the second ethernet as it currently doesn't work with
* the devicetree setup in U-Boot.
*/
&fec1 {
@@ -53,11 +50,16 @@
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
};
};
};
&fec2 {
status = "disabled";
/delete-property/ phy-handle;
/delete-node/ mdio;
};

406
arch/arm/dts/imx6ul-kontron-bl-common.dtsi
View File

@@ -1,406 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include <dt-bindings/gpio/gpio.h>
/ {
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led1 {
label = "debug-led1";
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
led2 {
label = "debug-led2";
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3 {
label = "debug-led3";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm8 0 5000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_adc: regulator-vref-adc {
compatible = "regulator-fixed";
regulator-name = "vref-adc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
num-channels = <3>;
vref-supply = <&reg_vref_adc>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
eeprom@0 {
compatible = "anvo,anv32e61w", "atmel,at25";
reg = <0>;
spi-max-frequency = <20000000>;
spi-cpha;
spi-cpol;
pagesize = <1>;
size = <8192>;
address-width = <16>;
};
};
&fec1 {
pinctrl-0 = <&pinctrl_enet1>;
/delete-node/ mdio;
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy2>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
};
&pwm8 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
rs485-rts-active-low;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_5v>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
non-removable;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
pinctrl_adc1: adc1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
>;
};
pinctrl_enet2_mdio: enet2mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp{
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
>;
};
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
/*
* mux unused RTS to make sure it doesn't cause
* any interrupts when it is undefined
*/
MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1 {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>;
};
};

16
arch/arm/dts/imx6ul-kontron-bl.dts
View File

@@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
/dts-v1/;
#include "imx6ul-kontron-sl.dtsi"
#include "imx6ul-kontron-bl-common.dtsi"
/ {
model = "Kontron BL i.MX6UL (N631X S)";
compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul";
};

137
arch/arm/dts/imx6ul-kontron-sl-common.dtsi
View File

@@ -1,137 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include <dt-bindings/gpio/gpio.h>
/ {
chosen {
stdout-path = &uart4;
};
memory@80000000 {
reg = <0x80000000 0x10000000>;
device_type = "memory";
};
};
&ecspi2 {
cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
flash@0 {
compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};
&fec2 {
phy-mode = "rmii";
status = "disabled";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <104000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
};
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_out>;
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
>;
};
pinctrl_enet1_mdio: enet1mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
};
pinctrl_reset_out: rstoutgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0
>;
};
};

14
arch/arm/dts/imx6ul-kontron-sl.dtsi
View File

@@ -1,14 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include "imx6ul.dtsi"
#include "imx6ul-kontron-sl-common.dtsi"
/ {
model = "Kontron SL i.MX6UL (N631X SOM)";
compatible = "kontron,sl-imx6ul", "fsl,imx6ul";
};

15
arch/arm/dts/imx6ull-kontron-bl.dts
View File

@@ -1,15 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2019 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx6ull-kontron-sl.dtsi"
#include "imx6ul-kontron-bl-common.dtsi"
/ {
model = "Kontron BL i.MX6ULL (N641X S)";
compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull";
};

13
arch/arm/dts/imx6ull-kontron-sl.dtsi
View File

@@ -1,13 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#include "imx6ull.dtsi"
#include "imx6ul-kontron-sl-common.dtsi"
/ {
model = "Kontron SL i.MX6ULL (N641X SOM)";
compatible = "kontron,sl-imx6ull", "fsl,imx6ull";
};

131
arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi Normal file
View File

@@ -0,0 +1,131 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include "imx8mp-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
bootstd {
bootph-verify;
compatible = "u-boot,boot-std";
filename-prefixes = "/", "/boot/";
bootdev-order = "mmc2", "mmc1", "ethernet";
efi {
compatible = "u-boot,distro-efi";
};
rauc {
compatible = "u-boot,distro-rauc";
};
script {
compatible = "u-boot,script";
};
};
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
&pinctrl_uart4 {
bootph-pre-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc3 {
bootph-pre-ram;
};
&pinctrl_wdog {
bootph-pre-ram;
};
&gpio1 {
bootph-pre-ram;
};
&gpio2 {
bootph-pre-ram;
};
&gpio3 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&gpio5 {
bootph-pre-ram;
};
&uart4 {
bootph-pre-ram;
};
&i2c1 {
bootph-pre-ram;
};
&pmic {
bootph-pre-ram;
};
/* USB1 Type-C */
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
fsl,over-current-active-low;
fsl,power-active-low;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "peripheral";
status = "okay";
};
/* USB2 4-port USB3.0 HUB */
&usb3_phy1 {
vbus-supply = <&reg_vdd_5v0>;
status = "okay";
};
&usb3_1 {
fsl,permanently-attached;
fsl,disable-port-power-control;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
bootph-pre-ram;
};
&usdhc3 {
bootph-pre-ram;
};
&wdog1 {
bootph-pre-ram;
};

219
arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
View File

@@ -69,6 +69,16 @@
bootph-some-ram;
};
&pinctrl_lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_pmic {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
};
@@ -83,6 +93,16 @@
bootph-some-ram;
};
&pinctrl_usdhc1_100mhz {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc1_200mhz {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2_cd {
bootph-pre-ram;
bootph-some-ram;
@@ -128,31 +148,9 @@
bootph-some-ram;
};
/*
* Remove once USB support is added to imx93-phyboard-segin.dts upstream.
*/
&usbotg1 {
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usdhc1 {
bootph-pre-ram;
bootph-some-ram;
/*
* Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
*/
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
};
&usdhc2 {
@@ -174,6 +172,21 @@
&lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
pmic@25 {
bootph-pre-ram;
bootph-some-ram;
regulators {
bootph-pre-ram;
bootph-some-ram;
};
};
eeprom@50 {
bootph-pre-ram;
bootph-some-ram;
};
};
&s4muap {
@@ -209,165 +222,3 @@
bootph-all;
bootph-pre-ram;
};
/*
* The two nodes below won't be needed once nxp,pca9451a
* support is added to the Linux kernel.
*/
&iomuxc {
pinctrl_lpi2c3: lpi2c3grp {
bootph-pre-ram;
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_pmic: pmicgrp {
bootph-pre-ram;
fsl,pins = <
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
>;
};
/*
* Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
* are added to imx93-phycore-som.dtsi
*/
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
bootph-pre-ram;
bootph-some-ram;
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
bootph-pre-ram;
bootph-some-ram;
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
};
&lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3>;
status = "okay";
pmic@25 {
bootph-pre-ram;
bootph-some-ram;
compatible = "nxp,pca9451a";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
regulators {
bootph-pre-ram;
bootph-some-ram;
buck1: BUCK1 {
regulator-name = "VDD_SOC";
regulator-min-microvolt = <610000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "VDDQ_0V6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <600000>;
regulator-boot-on;
regulator-always-on;
};
buck4: BUCK4 {
regulator-name = "VDD_3V3_BUCK";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "VDD_1V1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "PMIC_SNVS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "VDD_0V8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "NVCC_SD2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
eeprom@50 {
bootph-pre-ram;
bootph-some-ram;
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&buck4>;
};
};

10
arch/arm/mach-imx/imx8m/Kconfig
View File

@@ -345,6 +345,15 @@ config TARGET_PHYCORE_IMX8MP
select IMX8M_LPDDR4
imply OF_UPSTREAM
config TARGET_IMX8MP_LIBRA_FPSC
bool "PHYTEC Libra i.MX 8M Plus FPSC"
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
imply OF_UPSTREAM
help
Libra i.MX8M Plus FPSC is an SBC based on the NXP i.MX 8M Plus SoC.
config TARGET_IMX8MM_CL_IOT_GATE
bool "CompuLab iot-gate-imx8"
select IMX8MM
@@ -409,6 +418,7 @@ source "board/kontron/sl-mx8mm/Kconfig"
source "board/menlo/mx8menlo/Kconfig"
source "board/msc/sm2s_imx8mp/Kconfig"
source "board/mntre/imx8mq_reform2/Kconfig"
source "board/phytec/imx8mp-libra-fpsc/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/polyhex/imx8mp_debix_model_a/Kconfig"

2
board/kontron/sl-mx6ul/sl-mx6ul-common.c
View File

@@ -6,7 +6,7 @@
#include <asm/types.h>
#include <asm/arch/sys_proto.h>
#include <sl-mx6ul-common.h>
#include "sl-mx6ul-common.h"
bool sl_mx6ul_is_spi_nor_boot(void)
{

23
board/kontron/sl-mx6ul/sl-mx6ul.c
View File

@@ -5,11 +5,14 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-mx6/imx-regs.h>
#include <asm/global_data.h>
#include <env.h>
#include <env_internal.h>
#include <fdt_support.h>
#include <phy.h>
#include <sl-mx6ul-common.h>
#include "sl-mx6ul-common.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -86,15 +89,31 @@ int board_init(void)
return 0;
}
int board_late_init(void)
{
if (is_boot_from_usb()) {
env_set("bootdelay", "0");
env_set("bootcmd", "fastboot 0");
}
return 0;
}
enum env_location env_get_location(enum env_operation op, int prio)
{
if (prio)
return ENVL_UNKNOWN;
if (CONFIG_IS_ENABLED(ENV_IS_NOWHERE) && is_boot_from_usb())
return ENVL_NOWHERE;
if (sl_mx6ul_is_spi_nor_boot() && CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
return ENVL_SPI_FLASH;
else if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
return ENVL_MMC;
return ENVL_NOWHERE;
if (CONFIG_IS_ENABLED(ENV_IS_NOWHERE))
return ENVL_NOWHERE;
return ENVL_UNKNOWN;
}

3
board/kontron/sl-mx6ul/spl.c
View File

@@ -18,7 +18,8 @@
#include <linux/sizes.h>
#include <linux/errno.h>
#include <mmc.h>
#include <sl-mx6ul-common.h>
#include "sl-mx6ul-common.h"
DECLARE_GLOBAL_DATA_PTR;

16
board/phytec/imx8mp-libra-fpsc/Kconfig Normal file
View File

@@ -0,0 +1,16 @@
if TARGET_IMX8MP_LIBRA_FPSC
config SYS_BOARD
default "imx8mp-libra-fpsc"
config SYS_VENDOR
default "phytec"
config IMX_CONFIG
default "board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg"
config SYS_CONFIG_NAME
default "imx8mp-libra-fpsc"
source "board/phytec/common/Kconfig"
endif

9
board/phytec/imx8mp-libra-fpsc/MAINTAINERS Normal file
View File

@@ -0,0 +1,9 @@
Libra-i.MX 8M Plus
M: Teresa Remmet <t.remmet@phytec.de>
W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/
S: Maintained
F: arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
F: board/phytec/imx8mp-libra-fpsc/
F: configs/imx8mp-libra-fpsc_defconfig
F: include/configs/imx8mp-libra-fpsc.h
F: doc/board/phytec/imx8mp-libra-fpsc.rst

10
board/phytec/imx8mp-libra-fpsc/Makefile Normal file
View File

@@ -0,0 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) 2025 PHYTEC Messtechnik GmbH
obj-y += imx8mp-libra-fpsc.o
ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif

89
board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c Normal file
View File

@@ -0,0 +1,89 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <linux/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <dwc3-uboot.h>
#include <env.h>
#include <init.h>
#include <fdt_support.h>
#include <jffs2/load_kernel.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <usb.h>
#include <i2c.h>
#define EEPROM_ADDR 0x51
#define TUSB_PORT_POL_CRTL_REG 0xB
#define TUSB_CUSTOM_POL BIT(7)
#define TUSB_P0_POL BIT(0)
/*
* WORKAROUND for PCM-937-L 1618.0, 1618.1.
* USB HUB TUSB8042A has swapped upstream pin polarity.
* Set i2c registers to inform the hub that the lines
* are swapped.
*/
void tusb8042a_swap_lines(void)
{
const u8 pol_swap_val = (TUSB_CUSTOM_POL | TUSB_P0_POL);
const int addr = 0x44;
struct udevice *dev = 0;
int ret = i2c_get_chip_for_busnum(2, addr, 1, &dev);
if (!ret)
dm_i2c_write(dev, TUSB_PORT_POL_CRTL_REG, &pol_swap_val, 1);
else
printf("TUSB8042A: Failed to fixup USB HUB.\n");
}
int board_init(void)
{
tusb8042a_swap_lines();
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
switch (get_boot_device()) {
case SD2_BOOT:
env_set_ulong("mmcdev", 1);
if (!strcmp(env_get("boot_targets"), env_get_default("boot_targets")))
env_set("boot_targets", "mmc1 mmc2 ethernet");
break;
case MMC3_BOOT:
env_set_ulong("mmcdev", 2);
break;
case USB_BOOT:
printf("Detect USB boot. Will enter fastboot mode!\n");
if (!strcmp(env_get("bootcmd"), env_get_default("bootcmd")))
env_set("bootcmd", "fastboot 0; bootflow scan -lb;");
break;
default:
break;
}
return 0;
}
int board_phys_sdram_size(phys_size_t *size)
{
if (!size)
return -EINVAL;
*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
return 0;
}

19
board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env Normal file
View File

@@ -0,0 +1,19 @@
boot_script_dhcp=boot.scr.uimg
console=ttymxc3,CONFIG_BAUDRATE
emmc_dev=2 /* This is needed by built-in uuu flash scripts */
fdtfile=CONFIG_DEFAULT_FDT_FILE
fdt_addr_r=0x40480000
fdt_overlay_addr_r=0x404a0000
fit_fdtconf=conf-imx8mp-libra-rdk-fpsc.dtb
kernel_addr_r=0x40a00000
kernel_comp_addr_r=0x43a00000
kernel_comp_size=0x1e00000
mmcroot=2
pxefile_addr_r=0x45800000
ramdisk_addr_r=0x45802000
scriptaddr=0x47600000
script_offset_f=0x0
script_size_f=0x2000
sd_dev=1 /* This is needed by built-in uuu flash scripts */
ip_dyn=yes
nfsroot=/srv/nfs

9
board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg Normal file
View File

@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 NXP
*/
ROM_VERSION v2
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x920000

1813
board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c Normal file
View File

File diff suppressed because it is too large Load Diff

132
board/phytec/imx8mp-libra-fpsc/spl.c Normal file
View File

@@ -0,0 +1,132 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include <config.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/iomux-v3.h>
#include <hang.h>
#include <init.h>
#include <log.h>
#include <power/pmic.h>
#include <power/pca9450.h>
#include <spl.h>
#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION)
#include "../common/imx8m_som_detection.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
#define EEPROM_ADDR 0x51
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_dram_init(void)
{
#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION)
int ret;
ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
if (!ret) {
ret = phytec_imx8m_detect(NULL);
if (!ret)
phytec_print_som_info(NULL);
}
#endif
ddr_init(&dram_timing);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
int power_init_board(void)
{
struct pmic *p;
int ret;
ret = power_pca9450_init(0, 0x25);
if (ret)
printf("power init failed");
p = pmic_get("PCA9450");
pmic_probe(p);
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
/* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
/* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
/* Set WDOG_B_CFG to cold reset */
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
void spl_board_init(void)
{
arch_misc_init();
/* Set GIC clock to 500Mhz for OD VDD_SOC. */
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
clock_enable(CCGR_GIC, 1);
}
int board_fit_config_name_match(const char *name)
{
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
arch_cpu_init();
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
enable_tzc380();
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
power_init_board();
/* DDR initialization */
spl_dram_init();
}

2
board/phytec/phycore_imx93/phycore-imx93.c
View File

@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
int ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR);
if (ret)
printf("%s: EEPROM data init failed\n", __func__);

2
board/phytec/phycore_imx93/spl.c
View File

@@ -52,7 +52,7 @@ void spl_dram_init(void)
int ret;
enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID;
ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR);
if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
goto out;

6
configs/imx8mn_ddr4_evk_defconfig
View File

@@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-ddr4-evk"
CONFIG_TARGET_IMX8MN_DDR4_EVK=y
@@ -22,6 +22,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x204000
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
@@ -64,6 +65,7 @@ CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_REDUNDANT=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_MMC_DEVICE_INDEX=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y

6
configs/imx8mn_evk_defconfig
View File

@@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-evk"
CONFIG_TARGET_IMX8MN_EVK=y
@@ -22,6 +22,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x204000
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_EFI_SET_TIME=y
CONFIG_EFI_MM_COMM_TEE=y
@@ -82,6 +83,7 @@ CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_REDUNDANT=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y

175
configs/imx8mp-libra-fpsc_defconfig Normal file
View File

@@ -0,0 +1,175 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SF_DEFAULT_SPEED=80000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-libra-rdk-fpsc"
CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000
CONFIG_TARGET_IMX8MP_LIBRA_FPSC=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x960000
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x98fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SYS_LOAD_ADDR=0x47602000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3e0000
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTD_FULL=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-libra-rdk-fpsc.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_EEPROM_SIZE=4096
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_REG=y
CONFIG_CMD_MTD=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_REDUNDANT=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_MMC_DEVICE_INDEX=2
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_FSL_CAAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
CONFIG_FASTBOOT_BUF_SIZE=0x13000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0"
CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1"
CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
CONFIG_FASTBOOT_MMC_USER_NAME="mmc2"
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x51
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
CONFIG_POWER_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
CONFIG_DM_RNG=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_IMX_WATCHDOG=y

6
configs/imx8mp_evk_defconfig
View File

@@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-evk"
CONFIG_TARGET_IMX8MP_EVK=y
@@ -22,6 +22,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x20400
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_EFI_MM_COMM_TEE=y
CONFIG_EFI_VAR_BUF_SIZE=139264
@@ -77,6 +78,7 @@ CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_REDUNDANT=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_MMC_DEVICE_INDEX=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y

6
configs/imx8mq_evk_defconfig
View File

@@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x200000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
@@ -25,6 +25,7 @@ CONFIG_SPL_BSS_START_ADDR=0x180000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x204000
CONFIG_IMX_BOOTAUX=y
CONFIG_REMAKE_ELF=y
CONFIG_EFI_MM_COMM_TEE=y
@@ -75,6 +76,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_REDUNDANT=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_MMC_DEVICE_INDEX=1
CONFIG_USE_ETHPRIME=y

2
configs/imx93-phycore_defconfig
View File

@@ -7,13 +7,13 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_PHYTEC_EEPROM_BUS=2
CONFIG_ENV_SOURCE_FILE="phycore_imx93"
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-phyboard-segin"
CONFIG_AHAB_BOOT=y
CONFIG_TARGET_PHYCORE_IMX93=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288

32
configs/kontron-sl-mx6ul_defconfig
View File

@@ -7,25 +7,27 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0xF0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x4000
CONFIG_MX6UL=y
CONFIG_TARGET_KONTRON_MX6UL=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-kontron-bl"
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6ul-kontron-bl"
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xF8000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTD_FULL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_SYS_PBSIZE=532
@@ -49,25 +51,37 @@ CONFIG_CMD_SF_TEST=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FS_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi1.0,spi-nand0=spi4.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:128k(spl),832k(u-boot),64k(env);spi4.0:-(UBI)"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:960k(u-boot),32k(env),32k(env_redundant);spi4.0:-(UBI)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6ul-kontron-bl imx6ull-kontron-bl"
CONFIG_OF_UPSTREAM=y
CONFIG_OF_LIST="nxp/imx/imx6ul-kontron-bl nxp/imx/imx6ull-kontron-bl"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_REDUNDANT=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth0"
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="kontron-mx6ul"
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
CONFIG_FASTBOOT_MMC_USER_NAME="mmc1"
CONFIG_DM_I2C=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
@@ -96,6 +110,9 @@ CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
# CONFIG_FSL_QSPI_AHB_FULL_MAP is not set
CONFIG_MXC_SPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_SYSRESET_WATCHDOG_AUTO=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
@@ -106,5 +123,6 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SDP_LOADADDR=0x8f7fffc0
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y

83
doc/board/phytec/imx8mp-libra-fpsc.rst Normal file
View File

@@ -0,0 +1,83 @@
.. SPDX-License-Identifier: GPL-2.0+
Libra i.MX 8M Plus FPSC
=======================
The Libra i.MX 8M Plus FPSC is a SBC based with the phyCORE-i.MX 8M Plus FPSC
SoM.
The phyCORE-i.MX 8M Plus FPSC with 2GB of main memory is supported.
Quick Start
-----------
- Build the ARM Trusted firmware binary
- Build the OP-TEE binary
- Get ddr firmware
- Build U-Boot
- Boot
Build the ARM Trusted firmware binary
-------------------------------------
.. code-block:: bash
$ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
$ cd trusted-firmware-a
$ make -j $(nproc) \
CROSS_COMPILE=aarch64-linux-gnu- \
PLAT=imx8mp \
IMX_BOOT_UART_BASE=0x30a60000 \
BL32_BASE=0x7e000000 \
SPD=opteed \
bl31
Build the OP-TEE binary
-----------------------
.. code-block:: bash
$ git clone https://github.com/OP-TEE/optee_os.git
$ cd optee_os
$ make -j $(nproc) \
CROSS_COMPILE=aarch64-linux-gnu- \
CFG_TEE_BENCHMARK=n \
O=out/arm \
PLATFORM=imx-mx8mp_libra_fpsc
Get the ddr firmware
--------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin
$ chmod +x firmware-imx-8.28-994fa14.bin
$ ./firmware-imx-8.28-994fa14.bin
Build U-Boot for SD card
------------------------
Copy binaries
^^^^^^^^^^^^^
.. code-block:: bash
$ cp <TF-A dir>/build/imx8mp/release/bl31.bin .
$ cp <OP-TEE dir>/out/arm/core/tee-raw.bin tee.bin
$ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4*.bin .
Build U-Boot
^^^^^^^^^^^^
.. code-block:: bash
$ make -j $(nproc) \
CROSS_COMPILE=aarch64-linux-gnu- \
imx8mp-libra-fpsc_defconfig \
flash.bin
Flash SD card
^^^^^^^^^^^^^
.. code-block:: bash
$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=fsync

1
doc/board/phytec/index.rst
View File

@@ -6,6 +6,7 @@ PHYTEC
.. toctree::
:maxdepth: 2
imx8mp-libra-fpsc
imx8mm-phygate-tauri-l
imx93-phycore
phycore-am62x

27
include/configs/imx8mp-libra-fpsc.h Normal file
View File

@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-or-later
*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#ifndef __IMX8MP_LIBRA_FPSC_H
#define __IMX8MP_LIBRA_FPSC_H
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* Link Definitions */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */
#endif /* __IMX8MP_LIBRA_FPSC_H */

12
include/configs/kontron-sl-mx6ul.h
View File

@@ -24,22 +24,10 @@
/* Board and environment settings */
#define CFG_MXC_UART_BASE UART4_BASE
/* Boot order for distro boot */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(UBIFS, ubifs, 0, UBI, boot) \
func(USB, usb, 0) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#define CFG_EXTRA_ENV_SETTINGS BOOTENV
#endif /* __KONTRON_MX6UL_CONFIG_H */

2
tools/imx8image.c
View File

@@ -23,7 +23,7 @@ static uint8_t cntr_version;
static uint32_t custom_partition;
static uint32_t scfw_flags;
int imx8image_check_params(struct image_tool_params *params)
static int imx8image_check_params(struct image_tool_params *params)
{
return 0;
}