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drivers: spi_dw: Add clock control

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This adds optional clock control support to the spi_dw driver. The
support currently assumes that the clock control binding uses clkid for
the clock cell name.

Signed-off-by: Łukasz Kędziora <lkedziora@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Andreas Weissel <andreas.weissel@synaptics.com>
This commit is contained in:
Łukasz Kędziora
2025-10-29 11:00:28 +01:00
committed by Alberto Escolar
parent e73e2f148c
commit 261dfbc765
2 changed files with 28 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/spi/spi_dw.c
View File

@@ -558,6 +558,16 @@ int spi_dw_init(const struct device *dev)
pinctrl_apply_state(info->pcfg, PINCTRL_STATE_DEFAULT);
#endif
#if defined(CONFIG_CLOCK_CONTROL)
if (info->clk_dev) {
err = clock_control_on(info->clk_dev, info->clk_id);
if (err < 0) {
LOG_ERR("Failed to enable the clock");
return err;
}
}
#endif
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
info->config_func();
@@ -649,6 +659,15 @@ COND_CODE_1(IS_EQ(DT_NUM_IRQS(DT_DRV_INST(inst)), 1), \
(SPI_CFG_IRQS_MULTIPLE_ERR_LINES(inst))))) \
}
#if defined(CONFIG_CLOCK_CONTROL)
#define CLOCK_DW_CONFIG(n) \
IF_ENABLED(DT_INST_NODE_HAS_PROP(0, clocks), \
(.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clk_id = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, clkid),))
#else
#define CLOCK_DW_CONFIG(n)
#endif
#define SPI_DW_INIT(inst) \
IF_ENABLED(CONFIG_PINCTRL, (PINCTRL_DT_INST_DEFINE(inst);)) \
SPI_DW_IRQ_HANDLER(inst); \
@@ -679,6 +698,7 @@ COND_CODE_1(IS_EQ(DT_NUM_IRQS(DT_DRV_INST(inst)), 1), \
.set_bit_func = reg_set_bit, \
.clear_bit_func = reg_clear_bit, \
.test_bit_func = reg_test_bit,)) \
CLOCK_DW_CONFIG(inst) \
}; \
SPI_DEVICE_DT_INST_DEFINE(inst, \
spi_dw_init, \

8
drivers/spi/spi_dw.h
View File

@@ -14,6 +14,10 @@
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#if defined(CONFIG_CLOCK_CONTROL)
#include <zephyr/drivers/clock_control.h>
#endif
#include "spi_context.h"
#ifdef __cplusplus
@@ -46,6 +50,10 @@ struct spi_dw_config {
uint8_t max_xfer_size;
#ifdef CONFIG_PINCTRL
const struct pinctrl_dev_config *pcfg;
#endif
#if defined(CONFIG_CLOCK_CONTROL)
const struct device *clk_dev;
const clock_control_subsys_t clk_id;
#endif
spi_dw_read_t read_func;
spi_dw_write_t write_func;