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drivers: gpio: mcux: Fix updating ICR registers without IRQ lock

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During configuration the base->ICR1 or base->ICR2 register is written
without an IRQ lock. This can result in unwanted side-effects if the status
bit isn't cleared, or the edge select still needs to be updated.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This commit is contained in:
Pieter De Gendt
2026-01-21 11:17:47 +01:00
committed by Alberto Escolar
parent 7af0a2fcdf
commit 8402a4f8e5
1 changed files with 7 additions and 5 deletions
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12
drivers/gpio/gpio_mcux_igpio.c
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@@ -292,6 +292,10 @@ static int mcux_igpio_pin_interrupt_configure(const struct device *dev,
return -ENOTSUP;
}
if (pin >= 32) {
return -EINVAL;
}
if (mode == GPIO_INT_MODE_DISABLED) {
key = irq_lock();
@@ -314,18 +318,16 @@ static int mcux_igpio_pin_interrupt_configure(const struct device *dev,
icr = 0;
}
key = irq_lock();
if (pin < 16) {
shift = 2 * pin;
base->ICR1 = (base->ICR1 & ~(3 << shift)) | (icr << shift);
} else if (pin < 32) {
} else {
shift = 2 * (pin - 16);
base->ICR2 = (base->ICR2 & ~(3 << shift)) | (icr << shift);
} else {
return -EINVAL;
}
key = irq_lock();
WRITE_BIT(base->EDGE_SEL, pin, trig == GPIO_INT_TRIG_BOTH);
WRITE_BIT(base->ISR, pin, 1);
WRITE_BIT(base->IMR, pin, 1);