soc: opentitan: Port to HWMv2

Ports the SoC configuration to hardware model version 2 Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2024-02-14 08:25:39 +00:00
parent a8659e170b
commit 92eadf06b8
8 changed files with 10 additions and 4 deletions
--- a/soc/soc_legacy/riscv/opentitan/CMakeLists.txt
+++ b/soc/soc_legacy/riscv/opentitan/CMakeLists.txt
--- a/soc/soc_legacy/riscv/opentitan/Kconfig.soc
+++ b/soc/soc_legacy/riscv/opentitan/Kconfig.soc
@@ -2,7 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 config SOC_OPENTITAN
 	bool "OpenTitan implementation"
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_RV32I
--- a/soc/soc_legacy/riscv/opentitan/Kconfig.defconfig
+++ b/soc/soc_legacy/riscv/opentitan/Kconfig.defconfig
@@ -3,9 +3,6 @@
 if SOC_OPENTITAN
 config SOC
 	default "opentitan"
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 1000000
--- a/soc/lowrisc/opentitan/Kconfig.soc
+++ b/soc/lowrisc/opentitan/Kconfig.soc
@@ -0,0 +1,8 @@
 # Copyright (c) 2023 Rivos Inc.
 # SPDX-License-Identifier: Apache-2.0
 config SOC_OPENTITAN
 	bool
 config SOC
 	default "opentitan" if SOC_OPENTITAN
--- a/soc/soc_legacy/riscv/opentitan/rom_header.S
+++ b/soc/soc_legacy/riscv/opentitan/rom_header.S
--- a/soc/soc_legacy/riscv/opentitan/rom_header.ld
+++ b/soc/soc_legacy/riscv/opentitan/rom_header.ld
--- a/soc/soc_legacy/riscv/opentitan/soc.c
+++ b/soc/soc_legacy/riscv/opentitan/soc.c
--- a/soc/lowrisc/opentitan/soc.yml
+++ b/soc/lowrisc/opentitan/soc.yml
@@ -0,0 +1,2 @@
 socs:
 - name: opentitan