soc/sifive/sifive_freedom: add SiFive Freedom E310 SoC

This commit adds support for the SiFive Freedom E310 SoC for the Zephyr
Hardware Model v2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Filip Kokosinski
2024-02-09 13:09:26 +01:00
committed by Carles Cufi
parent 4b90b30b9d
commit b9e06f4c38
16 changed files with 64 additions and 35 deletions

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@@ -0,0 +1,9 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_SIFIVE_FREEDOM
rsource "*/Kconfig"
endif # SOC_FAMILY_SIFIVE_FREEDOM

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@@ -0,0 +1,9 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_SIFIVE_FREEDOM
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_SIFIVE_FREEDOM

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@@ -0,0 +1,11 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_SIFIVE_FREEDOM
bool
config SOC_FAMILY
default "sifive_freedom" if SOC_FAMILY_SIFIVE_FREEDOM
rsource "*/Kconfig.soc"

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@@ -1,5 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(clock.c)
zephyr_include_directories(.)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

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@@ -1,20 +1,19 @@
# RISCV_SIFIVE_FREEDOM SOC configuration options
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
choice
prompt "SiFive Freedom SOC implementation"
depends on SOC_SERIES_SIFIVE_FREEDOM_E300
config SOC_SERIES_SIFIVE_FREEDOM_FE300
bool
config SOC_SIFIVE_FREEDOM_E340
bool "SiFive Freedom SOC implementation"
select ATOMIC_OPERATIONS_C
select INCLUDE_RESET_VECTOR
# RISC-V options
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
endchoice
select ATOMIC_OPERATIONS_C
select INCLUDE_RESET_VECTOR

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@@ -1,10 +1,8 @@
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SIFIVE_FREEDOM_E300
config SOC_SERIES
default "e300"
if SOC_SERIES_SIFIVE_FREEDOM_FE300
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
@@ -27,6 +25,4 @@ config MAX_IRQ_PER_AGGREGATOR
config NUM_IRQS
default 64
source "soc/soc_legacy/riscv/sifive_freedom/e300/Kconfig.defconfig.e*"
endif # SOC_SERIES_SIFIVE_FREEDOM_E300
endif # SOC_SERIES_SIFIVE_FREEDOM_FE300

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@@ -0,0 +1,16 @@
# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SIFIVE_FREEDOM_FE300
bool
select SOC_FAMILY_SIFIVE_FREEDOM
config SOC_SERIES
default "fe300" if SOC_SERIES_SIFIVE_FREEDOM_FE300
config SOC_SIFIVE_FREEDOM_FE310
bool
select SOC_SERIES_SIFIVE_FREEDOM_FE300
config SOC
default "fe310" if SOC_SIFIVE_FREEDOM_FE310

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@@ -0,0 +1,6 @@
family:
- name: sifive_freedom
series:
- name: fe300
socs:
- name: fe310

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@@ -1,5 +0,0 @@
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC
default "e340" if SOC_SIFIVE_FREEDOM_E340

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@@ -1,13 +0,0 @@
# RISCV_SIFIVE_FREEDOM SOC implementation
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SIFIVE_FREEDOM_E300
bool "SiFive Freedom E300 SOC implementation"
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
select SOC_FAMILY_SIFIVE_FREEDOM
help
Enable support for SiFive Freedom FE300 SOC