tests/benchmarks: add dynamic memory allocation measurement

add a test into latency_measure test case to measure
the average time for dynamic memory allocation and release.

Signed-off-by: Chen Peng1 <peng1.chen@intel.com>

VERSION

@@ -1,4 +1,5 @@
 VERSION_MAJOR = 2
 VERSION_MINOR = 6
-PATCHLEVEL = 0
+PATCHLEVEL = 1
 VERSION_TWEAK = 0
+EXTRAVERSION = rc1

arch/arc/Kconfig

@@ -252,6 +252,7 @@ config CODE_DENSITY
 
 config ARC_HAS_ACCL_REGS
 	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
+	default y if CPU_HS3X
 	default y if FPU
 	help
 	  Depending on the configuration, CPU can contain accumulator reg-pair

arch/x86/core/acpi.c

@@ -50,8 +50,11 @@ static void find_rsdp(void)
 	bda_seg = 0x040e + zero_page_base;
 	uint64_t *search = (void *)(long)(((int)*(uint16_t *)bda_seg) << 4);
 
-	/* Might be nothing there, check before we inspect */
-	if (search != NULL) {
+	/* Might be nothing there, check before we inspect.
+	 * Note that EBDA usually is in 0x80000 to 0x100000.
+	 */
+	if ((POINTER_TO_UINT(search) >= 0x80000UL) &&
+	    (POINTER_TO_UINT(search) < 0x100000UL)) {
 		for (int i = 0; i < 1024/8; i++) {
 			if (search[i] == ACPI_RSDP_SIGNATURE) {
 				rsdp = (void *)&search[i];

arch/x86/zefi/zefi.c

@@ -92,6 +92,20 @@ uintptr_t __abi efi_entry(void *img_handle, struct efi_system_table *sys_tab)
 		for (int j = 0; j < bytes; j++) {
 			dst[j] = src[j];
 		}
+
+		/* Page-aligned blocks below 1M are the .locore
+		 * section, which has a jump in its first bytes for
+		 * the benefit of 32 bit entry.  Those have to be
+		 * written over with NOP instructions. (See comment
+		 * about OUTRAGEOUS HACK in locore.S) before Zephyr
+		 * starts, because the very first thing it does is
+		 * install its own page table that disallows writes.
+		 */
+		if (((long)dst & 0xfff) == 0 && dst < (uint8_t *)0x100000L) {
+			for (int i = 0; i < 8; i++) {
+				dst[i] = 0x90; /* 0x90 == 1-byte NOP */
+			}
+		}
 	}
 
 	unsigned char *code = (void *)zefi_entry;

cmake/compiler/gcc/target.cmake

@@ -61,23 +61,21 @@ elseif("${ARCH}" STREQUAL "sparc")
   include(${CMAKE_CURRENT_LIST_DIR}/target_sparc.cmake)
 endif()
 
-if(NOT no_libgcc)
-  # This libgcc code is partially duplicated in compiler/*/target.cmake
-  execute_process(
-    COMMAND ${CMAKE_C_COMPILER} ${TOOLCHAIN_C_FLAGS} --print-libgcc-file-name
-    OUTPUT_VARIABLE LIBGCC_FILE_NAME
-    OUTPUT_STRIP_TRAILING_WHITESPACE
-    )
+# This libgcc code is partially duplicated in compiler/*/target.cmake
+execute_process(
+  COMMAND ${CMAKE_C_COMPILER} ${TOOLCHAIN_C_FLAGS} --print-libgcc-file-name
+  OUTPUT_VARIABLE LIBGCC_FILE_NAME
+  OUTPUT_STRIP_TRAILING_WHITESPACE
+  )
 
-  assert_exists(LIBGCC_FILE_NAME)
+assert_exists(LIBGCC_FILE_NAME)
 
-  get_filename_component(LIBGCC_DIR ${LIBGCC_FILE_NAME} DIRECTORY)
+get_filename_component(LIBGCC_DIR ${LIBGCC_FILE_NAME} DIRECTORY)
 
-  assert_exists(LIBGCC_DIR)
+assert_exists(LIBGCC_DIR)
 
-  LIST(APPEND LIB_INCLUDE_DIR "-L\"${LIBGCC_DIR}\"")
-  LIST(APPEND TOOLCHAIN_LIBS gcc)
-endif()
+LIST(APPEND LIB_INCLUDE_DIR "-L\"${LIBGCC_DIR}\"")
+LIST(APPEND TOOLCHAIN_LIBS gcc)
 
 if(SYSROOT_DIR)
   # The toolchain has specified a sysroot dir that we can use to set

cmake/compiler/host-gcc/target.cmake

@@ -18,21 +18,6 @@ else()
 endif()
 find_program(CMAKE_CXX_COMPILER ${cplusplus_compiler}     CACHE INTERNAL " " FORCE)
 
-# The x32 version of libgcc is usually not available (can't trust gcc
-# -mx32 --print-libgcc-file-name) so don't fail to build for something
-# that is currently not needed. See comments in compiler/gcc/target.cmake
-if (CONFIG_X86)
-  # Convert to list as cmake Modules/*.cmake do it
-  STRING(REGEX REPLACE " +" ";" PRINT_LIBGCC_ARGS "${CMAKE_C_FLAGS}")
-  # This libgcc code is partially duplicated in compiler/*/target.cmake
-  execute_process(
-    COMMAND ${CMAKE_C_COMPILER} "${PRINT_LIBGCC_ARGS}" --print-libgcc-file-name
-    OUTPUT_VARIABLE LIBGCC_FILE_NAME
-    OUTPUT_STRIP_TRAILING_WHITESPACE
-    )
-  assert_exists(LIBGCC_FILE_NAME)
-endif()
-
 set(NOSTDINC "")
 
 # Note that NOSYSDEF_CFLAG may be an empty string, and

cmake/linker/ld/target.cmake

@@ -13,14 +13,16 @@ endif()
 
 set_ifndef(LINKERFLAGPREFIX -Wl)
 
-if(CONFIG_EXCEPTIONS)
-  # When building with C++ Exceptions, it is important that crtbegin and crtend
-  # are linked at specific locations.
-  # The location is so important that we cannot let this be controlled by normal
-  # link libraries, instead we must control the link command specifically as
-  # part of toolchain.
-  set(CMAKE_CXX_LINK_EXECUTABLE
-      "<CMAKE_CXX_COMPILER> <FLAGS> <CMAKE_CXX_LINK_FLAGS> <LINK_FLAGS> ${LIBGCC_DIR}/crtbegin.o <OBJECTS> -o <TARGET> <LINK_LIBRARIES> ${LIBGCC_DIR}/crtend.o")
+if(NOT "${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "host")
+  if(CONFIG_EXCEPTIONS)
+    # When building with C++ Exceptions, it is important that crtbegin and crtend
+    # are linked at specific locations.
+    # The location is so important that we cannot let this be controlled by normal
+    # link libraries, instead we must control the link command specifically as
+    # part of toolchain.
+    set(CMAKE_CXX_LINK_EXECUTABLE
+        "<CMAKE_CXX_COMPILER> <FLAGS> <CMAKE_CXX_LINK_FLAGS> <LINK_FLAGS> ${LIBGCC_DIR}/crtbegin.o <OBJECTS> -o <TARGET> <LINK_LIBRARIES> ${LIBGCC_DIR}/crtend.o")
+  endif()
 endif()
 
 # Run $LINKER_SCRIPT file through the C preprocessor, producing ${linker_script_gen}

doc/guides/dts/bindings.rst

@@ -1013,6 +1013,8 @@ gpio_dt_spec``, then use it like this:
 
    #include <drivers/gpio.h>
 
+   #define ZEPHYR_USER_NODE DT_PATH(zephyr_user)
+
    const struct gpio_dt_spec signal =
            GPIO_DT_SPEC_GET(ZEPHYR_USER_NODE, signal_gpios);
 

doc/reference/api/overview.rst

@@ -80,7 +80,7 @@ current :ref:`stability level <api_lifecycle>`.
    * - :ref:`devicetree_api`
      - Experimental
      - 2.2
-     - 2.4
+     - 2.6
 
    * - :ref:`disk_access_api`
      - Stable

doc/releases/release-notes-2.6.rst

@@ -2,6 +2,29 @@
 
 .. _zephyr_2.6:
 
+
+.. _zephyr_2.6.1:
+
+Zephyr 2.6.1
+#############
+
+This is a maintenance release with the following fixes.
+
+Security Vulnerability Related
+******************************
+
+The following security vulnerabilities (CVEs) were addressed in this
+release:
+
+More detailed information can be found in:
+https://docs.zephyrproject.org/latest/security/vulnerabilities.html
+
+Issues Fixed
+************
+
+
+.. _zephyr_2.6.0:
+
 Zephyr 2.6.0
 ############
 

drivers/bluetooth/hci/ipm_stm32wb.c

@@ -12,6 +12,7 @@
 #include <bluetooth/hci.h>
 #include <drivers/bluetooth/hci_driver.h>
 #include "bluetooth/addr.h"
+#include <drivers/clock_control/stm32_clock_control.h>
 
 #include "app_conf.h"
 #include "stm32_wpan_common.h"

drivers/clock_control/clock_stm32_ll_common.c

@@ -55,7 +55,7 @@
 #define RCC_CALC_FLASH_FREQ __LL_RCC_CALC_HCLK3_FREQ
 #define GET_CURRENT_FLASH_PRESCALER LL_RCC_GetAHB3Prescaler
 #else
-#define RCC_CALC_FLASH_FREQ __LL_RCC_CALC_HCLK1_FREQ
+#define RCC_CALC_FLASH_FREQ __LL_RCC_CALC_HCLK_FREQ
 #define GET_CURRENT_FLASH_PRESCALER LL_RCC_GetAHBPrescaler
 #endif
 

drivers/flash/flash_stm32_v1.c

@@ -210,11 +210,13 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
 			    const void *data, unsigned int len)
 {
 	int i, rc = 0;
-	const flash_prg_t *values = (const flash_prg_t *)data;
+	flash_prg_t value;
 
 	for (i = 0; i < len / sizeof(flash_prg_t); i++) {
-		rc = write_value(dev, offset + i * sizeof(flash_prg_t),
-				 values[i]);
+		memcpy(&value,
+		       (const uint8_t *)data + i * sizeof(flash_prg_t),
+		       sizeof(flash_prg_t));
+		rc = write_value(dev, offset + i * sizeof(flash_prg_t), value);
 		if (rc < 0) {
 			return rc;
 		}

drivers/timer/Kconfig

@@ -82,7 +82,7 @@ config HPET_TIMER
 	depends on X86
 	select IOAPIC if X86
 	select LOAPIC if X86
-	select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
+	imply TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
 	select TICKLESS_CAPABLE
 	help
 	  This option selects High Precision Event Timer (HPET) as a

drivers/timer/hpet.c

@@ -13,40 +13,233 @@
 
 #include <dt-bindings/interrupt-controller/intel-ioapic.h>
 
+#include <soc.h>
+
+/**
+ * @file
+ * @brief HPET (High Precision Event Timers) driver
+ *
+ * HPET hardware contains a number of timers which can be used by
+ * the operating system, where the number of timers is implementation
+ * specific. The timers are implemented as a single up-counter with
+ * a set of comparators where the counter increases monotonically.
+ * Each timer has a match register and a comparator, and can generate
+ * an interrupt when the value in the match register equals the value of
+ * the free running counter. Some of these timers can be enabled to
+ * generate periodic interrupt.
+ *
+ * The HPET registers are usually mapped to memory space on x86
+ * hardware. If this is not the case, custom register access functions
+ * can be used by defining macro HPET_USE_CUSTOM_REG_ACCESS_FUNCS in
+ * soc.h, and implementing necessary initialization and access
+ * functions as described below.
+ *
+ * HPET_COUNTER_CLK_PERIOD can be overridden in soc.h if
+ * COUNTER_CLK_PERIOD is not in femtoseconds (1e-15 sec).
+ *
+ * HPET_CMP_MIN_DELAY can be overridden in soc.h to better match
+ * the frequency of the timers. Default is 1000 where the value
+ * written to the comparator must be 1000 larger than the current
+ * main counter value.
+ */
+
+/* General Configuration register */
+#define GCONF_ENABLE			BIT(0)
+#define GCONF_LR			BIT(1) /* legacy interrupt routing, */
+					       /* disables PIT              */
+
+/* General Interrupt Status register */
+#define TIMER0_INT_STS			BIT(0)
+
+/* Timer Configuration and Capabilities register */
+#define TIMER_CONF_INT_LEVEL		BIT(1)
+#define TIMER_CONF_INT_ENABLE		BIT(2)
+#define TIMER_CONF_PERIODIC		BIT(3)
+#define TIMER_CONF_VAL_SET		BIT(6)
+#define TIMER_CONF_MODE32		BIT(8)
+#define TIMER_CONF_FSB_EN		BIT(14) /* FSB interrupt delivery   */
+						/* enable                   */
+
+/*
+ * The following MMIO initialization and register access functions
+ * should work on generic x86 hardware. If the targeted SoC requires
+ * special handling of HPET registers, these functions will need to be
+ * implemented in the SoC layer by first defining the macro
+ * HPET_USE_CUSTOM_REG_ACCESS_FUNCS in soc.h to signal such intent.
+ *
+ * This is a list of functions which must be implemented in the SoC
+ * layer:
+ *   void hpet_mmio_init(void)
+ *   uint32_t hpet_counter_get(void)
+ *   uint32_t hpet_counter_clk_period_get(void)
+ *   uint32_t hpet_gconf_get(void)
+ *   void hpet_gconf_set(uint32_t val)
+ *   void hpet_int_sts_set(uint32_t val)
+ *   uint32_t hpet_timer_conf_get(void)
+ *   void hpet_timer_conf_set(uint32_t val)
+ *   void hpet_timer_comparator_set(uint32_t val)
+ */
+#ifndef HPET_USE_CUSTOM_REG_ACCESS_FUNCS
 DEVICE_MMIO_TOPLEVEL_STATIC(hpet_regs, DT_DRV_INST(0));
 
-#define HPET_REG32(off) (*(volatile uint32_t *)(long)			\
-			 (DEVICE_MMIO_TOPLEVEL_GET(hpet_regs) + (off)))
+#define HPET_REG_ADDR(off)			\
+	((mm_reg_t)(DEVICE_MMIO_TOPLEVEL_GET(hpet_regs) + (off)))
 
-#define CLK_PERIOD_REG        HPET_REG32(0x04) /* High dword of caps reg */
-#define GENERAL_CONF_REG      HPET_REG32(0x10)
-#define INTR_STATUS_REG       HPET_REG32(0x20)
-#define MAIN_COUNTER_REG      HPET_REG32(0xf0)
-#define TIMER0_CONF_REG       HPET_REG32(0x100)
-#define TIMER0_COMPARATOR_REG HPET_REG32(0x108)
+/* High dword of General Capabilities and ID register */
+#define CLK_PERIOD_REG			HPET_REG_ADDR(0x04)
 
-/* GENERAL_CONF_REG bits */
-#define GCONF_ENABLE BIT(0)
-#define GCONF_LR     BIT(1) /* legacy interrupt routing, disables PIT */
+/* General Configuration register */
+#define GCONF_REG			HPET_REG_ADDR(0x10)
 
-/* INTR_STATUS_REG bits */
-#define TIMER0_INT_STS   BIT(0)
+/* General Interrupt Status register */
+#define INTR_STATUS_REG			HPET_REG_ADDR(0x20)
 
-/* TIMERn_CONF_REG bits */
-#define TCONF_INT_LEVEL  BIT(1)
-#define TCONF_INT_ENABLE BIT(2)
-#define TCONF_PERIODIC   BIT(3)
-#define TCONF_VAL_SET    BIT(6)
-#define TCONF_MODE32     BIT(8)
-#define TCONF_FSB_EN     BIT(14) /* FSB interrupt delivery enable */
+/* Main Counter Register */
+#define MAIN_COUNTER_REG		HPET_REG_ADDR(0xf0)
 
-#define MIN_DELAY 1000
+/* Timer 0 Configuration and Capabilities register */
+#define TIMER0_CONF_REG			HPET_REG_ADDR(0x100)
+
+/* Timer 0 Comparator Register */
+#define TIMER0_COMPARATOR_REG		HPET_REG_ADDR(0x108)
+
+/**
+ * @brief Setup memory mappings needed to access HPET registers.
+ *
+ * This is called in sys_clock_driver_init() to setup any memory
+ * mappings needed to access HPET registers.
+ */
+static inline void hpet_mmio_init(void)
+{
+	DEVICE_MMIO_TOPLEVEL_MAP(hpet_regs, K_MEM_CACHE_NONE);
+}
+
+/**
+ * @brief Return the value of the main counter.
+ *
+ * @return Value of Main Counter
+ */
+static inline uint32_t hpet_counter_get(void)
+{
+	return sys_read32(MAIN_COUNTER_REG);
+}
+
+/**
+ * @brief Get COUNTER_CLK_PERIOD
+ *
+ * Read and return the COUNTER_CLK_PERIOD, which is the high
+ * 32-bit of the General Capabilities and ID Register. This can
+ * be used to calculate the frequency of the main counter.
+ *
+ * Usually the period is in femtoseconds. If this is not
+ * the case, define HPET_COUNTER_CLK_PERIOD in soc.h so
+ * it can be used to calculate frequency.
+ *
+ * @return COUNTER_CLK_PERIOD
+ */
+static inline uint32_t hpet_counter_clk_period_get(void)
+{
+	return sys_read32(CLK_PERIOD_REG);
+}
+
+/**
+ * @brief Return the value of the General Configuration Register
+ *
+ * @return Value of the General Configuration Register
+ */
+static inline uint32_t hpet_gconf_get(void)
+{
+	return sys_read32(GCONF_REG);
+}
+
+/**
+ * @brief Write to General Configuration Register
+ *
+ * @param val Value to be written to the register
+ */
+static inline void hpet_gconf_set(uint32_t val)
+{
+	sys_write32(val, GCONF_REG);
+}
+
+/**
+ * @brief Write to General Interrupt Status Register
+ *
+ * This is used to acknowledge and clear interrupt bits.
+ *
+ * @param val Value to be written to the register
+ */
+static inline void hpet_int_sts_set(uint32_t val)
+{
+	sys_write32(val, INTR_STATUS_REG);
+}
+
+/**
+ * @brief Return the value of the Timer Configuration Register
+ *
+ * This reads and returns the value of the Timer Configuration
+ * Register of Timer #0.
+ *
+ * @return Value of the Timer Configuration Register
+ */
+static inline uint32_t hpet_timer_conf_get(void)
+{
+	return sys_read32(TIMER0_CONF_REG);
+}
+
+/**
+ * @brief Write to the Timer Configuration Register
+ *
+ * This writes the specified value to the Timer Configuration
+ * Register of Timer #0.
+ *
+ * @param val Value to be written to the register
+ */
+static inline void hpet_timer_conf_set(uint32_t val)
+{
+	sys_write32(val, TIMER0_CONF_REG);
+}
+
+/**
+ * @brief Write to the Timer Comparator Value Register
+ *
+ * This writes the specified value to the Timer Comparator
+ * Value Register of Timer #0.
+ *
+ * @param val Value to be written to the register
+ */
+static inline void hpet_timer_comparator_set(uint32_t val)
+{
+	sys_write32(val, TIMER0_COMPARATOR_REG);
+}
+#endif /* HPET_USE_CUSTOM_REG_ACCESS_FUNCS */
+
+#ifndef HPET_COUNTER_CLK_PERIOD
+/* COUNTER_CLK_PERIOD (CLK_PERIOD_REG) is in femtoseconds (1e-15 sec) */
+#define HPET_COUNTER_CLK_PERIOD		(1000000000000000ULL)
+#endif
+
+#ifndef HPET_CMP_MIN_DELAY
+/* Minimal delay for comparator before the next timer event */
+#define HPET_CMP_MIN_DELAY		(1000)
+#endif
+
+#define MAX_TICKS			0x7FFFFFFFUL
 
 static __pinned_bss struct k_spinlock lock;
-static __pinned_bss unsigned int max_ticks;
-static __pinned_bss unsigned int cyc_per_tick;
 static __pinned_bss unsigned int last_count;
 
+#ifdef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
+static __pinned_bss unsigned int cyc_per_tick;
+static __pinned_bss unsigned int max_ticks;
+#else
+#define cyc_per_tick			\
+	(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
+
+#define max_ticks			\
+	((MAX_TICKS - cyc_per_tick) / cyc_per_tick)
+#endif /* CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME */
+
 __isr
 static void hpet_isr(const void *arg)
 {
@@ -54,7 +247,7 @@ static void hpet_isr(const void *arg)
 
 	k_spinlock_key_t key = k_spin_lock(&lock);
 
-	uint32_t now = MAIN_COUNTER_REG;
+	uint32_t now = hpet_counter_get();
 
 #if ((DT_INST_IRQ(0, sense) & IRQ_TYPE_LEVEL) == IRQ_TYPE_LEVEL)
 	/*
@@ -62,7 +255,7 @@ static void hpet_isr(const void *arg)
 	 * When edge trigger is selected, spec says only 0 can
 	 * be written.
 	 */
-	INTR_STATUS_REG = TIMER0_INT_STS;
+	hpet_int_sts_set(TIMER0_INT_STS);
 #endif
 
 	if (IS_ENABLED(CONFIG_SMP) &&
@@ -85,10 +278,10 @@ static void hpet_isr(const void *arg)
 	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
 		uint32_t next = last_count + cyc_per_tick;
 
-		if ((int32_t)(next - now) < MIN_DELAY) {
+		if ((int32_t)(next - now) < HPET_CMP_MIN_DELAY) {
 			next += cyc_per_tick;
 		}
-		TIMER0_COMPARATOR_REG = next;
+		hpet_timer_comparator_set(next);
 	}
 
 	k_spin_unlock(&lock, key);
@@ -98,26 +291,30 @@ static void hpet_isr(const void *arg)
 __pinned_func
 static void set_timer0_irq(unsigned int irq)
 {
+	uint32_t val = hpet_timer_conf_get();
+
 	/* 5-bit IRQ field starting at bit 9 */
-	uint32_t val = (TIMER0_CONF_REG & ~(0x1f << 9)) | ((irq & 0x1f) << 9);
+	val = (val & ~(0x1f << 9)) | ((irq & 0x1f) << 9);
 
 #if ((DT_INST_IRQ(0, sense) & IRQ_TYPE_LEVEL) == IRQ_TYPE_LEVEL)
 	/* Level trigger */
-	val |= TCONF_INT_LEVEL;
+	val |= TIMER_CONF_INT_LEVEL;
 #endif
 
-	TIMER0_CONF_REG = val;
+	hpet_timer_conf_set(val);
 }
 
 __boot_func
 int sys_clock_driver_init(const struct device *dev)
 {
 	extern int z_clock_hw_cycles_per_sec;
-	uint32_t hz;
+	uint32_t hz, reg;
 
 	ARG_UNUSED(dev);
+	ARG_UNUSED(hz);
+	ARG_UNUSED(z_clock_hw_cycles_per_sec);
 
-	DEVICE_MMIO_TOPLEVEL_MAP(hpet_regs, K_MEM_CACHE_NONE);
+	hpet_mmio_init();
 
 	IRQ_CONNECT(DT_INST_IRQN(0),
 		    DT_INST_IRQ(0, priority),
@@ -125,27 +322,34 @@ int sys_clock_driver_init(const struct device *dev)
 	set_timer0_irq(DT_INST_IRQN(0));
 	irq_enable(DT_INST_IRQN(0));
 
-	/* CLK_PERIOD_REG is in femtoseconds (1e-15 sec) */
-	hz = (uint32_t)(1000000000000000ULL / CLK_PERIOD_REG);
+#ifdef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
+	hz = (uint32_t)(HPET_COUNTER_CLK_PERIOD / hpet_counter_clk_period_get());
 	z_clock_hw_cycles_per_sec = hz;
 	cyc_per_tick = hz / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
 
+	max_ticks = (MAX_TICKS - cyc_per_tick) / cyc_per_tick;
+#endif
+
+	last_count = hpet_counter_get();
+
 	/* Note: we set the legacy routing bit, because otherwise
 	 * nothing in Zephyr disables the PIT which then fires
 	 * interrupts into the same IRQ.  But that means we're then
 	 * forced to use IRQ2 contra the way the kconfig IRQ selection
 	 * is supposed to work.  Should fix this.
 	 */
-	GENERAL_CONF_REG |= GCONF_LR | GCONF_ENABLE;
-	TIMER0_CONF_REG &= ~TCONF_PERIODIC;
-	TIMER0_CONF_REG &= ~TCONF_FSB_EN;
-	TIMER0_CONF_REG |= TCONF_MODE32;
+	reg = hpet_gconf_get();
+	reg |= GCONF_LR | GCONF_ENABLE;
+	hpet_gconf_set(reg);
 
-	max_ticks = (0x7fffffff - cyc_per_tick) / cyc_per_tick;
-	last_count = MAIN_COUNTER_REG;
+	reg = hpet_timer_conf_get();
+	reg &= ~TIMER_CONF_PERIODIC;
+	reg &= ~TIMER_CONF_FSB_EN;
+	reg |= TIMER_CONF_MODE32;
+	reg |= TIMER_CONF_INT_ENABLE;
+	hpet_timer_conf_set(reg);
 
-	TIMER0_CONF_REG |= TCONF_INT_ENABLE;
-	TIMER0_COMPARATOR_REG = MAIN_COUNTER_REG + cyc_per_tick;
+	hpet_timer_comparator_set(last_count + cyc_per_tick);
 
 	return 0;
 }
@@ -165,8 +369,12 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
 	ARG_UNUSED(idle);
 
 #if defined(CONFIG_TICKLESS_KERNEL)
+	uint32_t reg;
+
 	if (ticks == K_TICKS_FOREVER && idle) {
-		GENERAL_CONF_REG &= ~GCONF_ENABLE;
+		reg = hpet_gconf_get();
+		reg &= ~GCONF_ENABLE;
+		hpet_gconf_set(reg);
 		return;
 	}
 
@@ -174,7 +382,7 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
 	ticks = CLAMP(ticks - 1, 0, (int32_t)max_ticks);
 
 	k_spinlock_key_t key = k_spin_lock(&lock);
-	uint32_t now = MAIN_COUNTER_REG, cyc, adj;
+	uint32_t now = hpet_counter_get(), cyc, adj;
 	uint32_t max_cyc = max_ticks * cyc_per_tick;
 
 	/* Round up to next tick boundary. */
@@ -188,11 +396,11 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
 	cyc = (cyc / cyc_per_tick) * cyc_per_tick;
 	cyc += last_count;
 
-	if ((cyc - now) < MIN_DELAY) {
+	if ((cyc - now) < HPET_CMP_MIN_DELAY) {
 		cyc += cyc_per_tick;
 	}
 
-	TIMER0_COMPARATOR_REG = cyc;
+	hpet_timer_comparator_set(cyc);
 	k_spin_unlock(&lock, key);
 #endif
 }
@@ -205,7 +413,7 @@ uint32_t sys_clock_elapsed(void)
 	}
 
 	k_spinlock_key_t key = k_spin_lock(&lock);
-	uint32_t ret = (MAIN_COUNTER_REG - last_count) / cyc_per_tick;
+	uint32_t ret = (hpet_counter_get() - last_count) / cyc_per_tick;
 
 	k_spin_unlock(&lock, key);
 	return ret;
@@ -214,11 +422,15 @@ uint32_t sys_clock_elapsed(void)
 __pinned_func
 uint32_t sys_clock_cycle_get_32(void)
 {
-	return MAIN_COUNTER_REG;
+	return hpet_counter_get();
 }
 
 __pinned_func
 void sys_clock_idle_exit(void)
 {
-	GENERAL_CONF_REG |= GCONF_ENABLE;
+	uint32_t reg;
+
+	reg = hpet_gconf_get();
+	reg |= GCONF_ENABLE;
+	hpet_gconf_set(reg);
 }

dts/arm/st/g0/stm32g050.dtsi

@@ -36,4 +36,5 @@
 		dmamux1: dmamux@40020800 {
 			dma-channels = <7>;
 		};
+	};
 };

include/linker/cplusplus-ram.ld

@@ -11,17 +11,6 @@
 	} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
 
 #if defined (CONFIG_EXCEPTIONS)
-    SECTION_PROLOGUE(.eh_frame_hdr,,)
-	{
-	*(.eh_frame_hdr)
-	}
-
-    SECTION_PROLOGUE(.eh_frame,,)
-	{
-	KEEP (*(SORT_NONE(EXCLUDE_FILE (*crtend.o) .eh_frame)))
-	KEEP (*(SORT_NONE(.eh_frame)))
-	} GROUP_LINK_IN(ROMABLE_REGION)
-
     SECTION_PROLOGUE(.tm_clone_table,,)
 	{
 	KEEP (*(SORT_NONE(EXCLUDE_FILE (*crtend.o) .tm_clone_table)))

include/linker/cplusplus-rom.ld

@@ -9,4 +9,18 @@
 	{
 	*(.gcc_except_table .gcc_except_table.*)
 	} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
-#endif
+
+#if defined (CONFIG_EXCEPTIONS)
+	SECTION_PROLOGUE(.eh_frame_hdr,,)
+	{
+	*(.eh_frame_hdr)
+	} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+
+	SECTION_PROLOGUE(.eh_frame,,)
+	{
+	KEEP (*(SORT_NONE(EXCLUDE_FILE (*crtend.o) .eh_frame)))
+	KEEP (*(SORT_NONE(.eh_frame)))
+	} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+#endif /* CONFIG_EXCEPTIONS */
+
+#endif /* CONFIG_CPLUSPLUS */

modules/TraceRecorder/CMakeLists.txt

@@ -10,17 +10,28 @@ if(CONFIG_PERCEPIO_TRACERECORDER)
   zephyr_library_sources_ifdef(
     CONFIG_PERCEPIO_TRACERECORDER
     ${TRACERECORDER_DIR}/kernelports/Zephyr/trcKernelPort.c
+    ${TRACERECORDER_DIR}/trcInternalBuffer.c
     ${TRACERECORDER_DIR}/trcStreamingRecorder.c
     ${TRACERECORDER_DIR}/extras/SDK/trcSDK.c
     )
 
   if(CONFIG_PERCEPIO_RECORDER_TRC_RECORDER_STREAM_PORT_RTT)
     zephyr_library_sources(
-      ${TRACERECORDER_DIR}/streamports/Jlink_RTT/trcStreamingPort.c
+      ${TRACERECORDER_DIR}/kernelports/Zephyr/streamports/Jlink_RTT/trcStreamingPort.c
     )
 
     zephyr_include_directories(
-      ${TRACERECORDER_DIR}/streamports/Jlink_RTT/include/
+      ${TRACERECORDER_DIR}/kernelports/Zephyr/streamports/Jlink_RTT/include/
+    )
+  endif()
+
+  if(CONFIG_PERCEPIO_RECORDER_TRC_RECORDER_STREAM_PORT_ITM)
+    zephyr_library_sources(
+      ${TRACERECORDER_DIR}/kernelports/Zephyr/streamports/ARM_ITM/trcStreamingPort.c
+    )
+
+    zephyr_include_directories(
+      ${TRACERECORDER_DIR}/kernelports/Zephyr/streamports/ARM_ITM/include/
     )
   endif()
 

scripts/dts/python-devicetree/tox.ini

@@ -5,6 +5,7 @@ envlist=py3
 deps =
     setuptools-scm
     pytest
+    types-PyYAML
     mypy
 setenv =
     TOXTEMPDIR={envtmpdir}

soc/riscv/openisa_rv32m1/Kconfig.soc

@@ -17,6 +17,7 @@ config SOC_OPENISA_RV32M1_RISCV32
 	select CLOCK_CONTROL
 	select HAS_RV32M1_FTFX
 	select HAS_FLASH_LOAD_OFFSET
+	select BUILD_OUTPUT_HEX
 	help
 	  Enable support for OpenISA RV32M1 RISC-V processors. Choose
 	  this option to target the RI5CY or ZERO-RISCY core. This

soc/riscv/openisa_rv32m1/soc.c

@@ -146,9 +146,7 @@ void soc_interrupt_init(void)
 	(void)(EVENT_UNIT->EVTPENDCLEAR); /* Ensures write has finished. */
 
 	if (IS_ENABLED(CONFIG_MULTI_LEVEL_INTERRUPTS)) {
-		dev_intmux = device_get_binding(
-				DT_LABEL(DT_INST(0, openisa_rv32m1_intmux)));
-		__ASSERT(dev_intmux, "no INTMUX device found");
+		dev_intmux = DEVICE_DT_GET(DT_INST(0, openisa_rv32m1_intmux));
 	}
 }
 

subsys/bluetooth/controller/ll_sw/ull.c

@@ -312,11 +312,20 @@ static struct {
  * Increasing this by times the max. simultaneous connection count will permit
  * simultaneous parallel PHY update or Connection Update procedures amongst
  * active connections.
+ * Minimum node rx of 2 that can be reserved happens when local central
+ * initiated PHY Update reserves 2 node rx, one for PHY update complete and
+ * another for Data Length Update complete notification. Otherwise, a
+ * peripheral only needs 1 additional node rx to generate Data Length Update
+ * complete when PHY Update completes; node rx for PHY update complete is
+ * reserved as the received PHY Update Ind PDU.
  */
-#if defined(CONFIG_BT_CTLR_PHY) && defined(CONFIG_BT_CTLR_DATA_LENGTH)
-#define LL_PDU_RX_CNT 3
+#if defined(CONFIG_BT_CENTRAL) && defined(CONFIG_BT_CTLR_PHY) && \
+	defined(CONFIG_BT_CTLR_DATA_LENGTH)
+#define LL_PDU_RX_CNT (2 * (CONFIG_BT_CTLR_LLCP_CONN))
+#elif defined(CONFIG_BT_CONN)
+#define LL_PDU_RX_CNT (CONFIG_BT_CTLR_LLCP_CONN)
 #else
-#define LL_PDU_RX_CNT 2
+#define LL_PDU_RX_CNT 0
 #endif
 
 /* No. of node rx for LLL to ULL.
@@ -1997,7 +2006,7 @@ static inline void rx_alloc(uint8_t max)
 		max = mem_link_rx.quota_pdu;
 	}
 
-	while ((max--) && MFIFO_ENQUEUE_IDX_GET(pdu_rx_free, &idx)) {
+	while (max && MFIFO_ENQUEUE_IDX_GET(pdu_rx_free, &idx)) {
 		memq_link_t *link;
 		struct node_rx_hdr *rx;
 
@@ -2017,6 +2026,8 @@ static inline void rx_alloc(uint8_t max)
 		MFIFO_BY_IDX_ENQUEUE(pdu_rx_free, idx, rx);
 
 		ll_rx_link_inc_quota(-1);
+
+		max--;
 	}
 
 #if defined(CONFIG_BT_CONN)

subsys/bluetooth/controller/ll_sw/ull_conn.c

@@ -4017,12 +4017,12 @@ static inline void event_phy_upd_ind_prep(struct ll_conn *conn,
 			rx->hdr.link->mem = conn->llcp_rx;
 			conn->llcp_rx = rx;
 
-#if defined(CONFIG_BT_CTLR_DATA_LENGTH)
 			/* reserve rx node for DLE event generation */
-			rx = ll_pdu_rx_alloc();
-			rx->hdr.link->mem = conn->llcp_rx;
-			conn->llcp_rx = rx;
-#endif /* CONFIG_BT_CTLR_DATA_LENGTH */
+			if (IS_ENABLED(CONFIG_BT_CTLR_DATA_LENGTH)) {
+				rx = ll_pdu_rx_alloc();
+				rx->hdr.link->mem = conn->llcp_rx;
+				conn->llcp_rx = rx;
+			}
 		}
 
 		/* place the phy update ind packet as next in
@@ -4047,6 +4047,21 @@ static inline void event_phy_upd_ind_prep(struct ll_conn *conn,
 		struct node_rx_pdu *rx;
 		uint8_t old_tx, old_rx;
 
+		/* Acquire additional rx node for Data length notification as
+		 * a peripheral.
+		 */
+		if (IS_ENABLED(CONFIG_BT_PERIPHERAL) &&
+		    IS_ENABLED(CONFIG_BT_CTLR_DATA_LENGTH) &&
+		    conn->lll.role) {
+			rx = ll_pdu_rx_alloc();
+			if (!rx) {
+				return;
+			}
+
+			rx->hdr.link->mem = conn->llcp_rx;
+			conn->llcp_rx = rx;
+		}
+
 #if defined(CONFIG_BT_PERIPHERAL) && defined(CONFIG_BT_CTLR_LE_ENC)
 		if (conn->lll.role && (conn->slave.llcp_type != LLCP_NONE)) {
 			/* Local peripheral initiated PHY update completed while
@@ -4107,8 +4122,11 @@ static inline void event_phy_upd_ind_prep(struct ll_conn *conn,
 			/* enqueue rx node towards Thread */
 			ll_rx_put(rx->hdr.link, rx);
 
+			/* Release rx node that was reserved for Data Length
+			 * notification.
+			 */
 			if (IS_ENABLED(CONFIG_BT_CTLR_DATA_LENGTH)) {
-				/* get the DLE rx node reserved for ULL->LL */
+				/* Get the DLE rx node reserved for ULL->LL */
 				rx = conn->llcp_rx;
 				LL_ASSERT(rx && rx->hdr.link);
 				conn->llcp_rx = rx->hdr.link->mem;
@@ -5454,23 +5472,27 @@ static inline uint8_t phy_upd_ind_recv(struct ll_conn *conn, memq_link_t *link,
 	conn->llcp.phy_upd_ind.instant = instant;
 	conn->llcp.phy_upd_ind.initiate = 0U;
 
+	/* Reserve the Rx-ed PHY Update Indication PDU in the connection
+	 * context, by appending to the LLCP node rx list. We do not mark it
+	 * for release in ULL, i.e., by returning *rx as NULL.
+	 * PHY Update notification to HCI layer will use node rx from this
+	 * list when at the instant.
+	 * If data length update is supported in the Controller, then, at the
+	 * instant we attempt to acquire an additional free node rx for Data
+	 * Length Update notification.
+	 */
 	link->mem = conn->llcp_rx;
 	(*rx)->hdr.link = link;
 	conn->llcp_rx = *rx;
 	*rx = NULL;
 
-#if defined(CONFIG_BT_CTLR_DATA_LENGTH)
-	/* reserve rx node for DLE event generation */
-	struct node_rx_pdu *rx_dle = ll_pdu_rx_alloc();
-
-	LL_ASSERT(rx_dle);
-	rx_dle->hdr.link->mem = conn->llcp_rx;
-	conn->llcp_rx = rx_dle;
-#endif /* CONFIG_BT_CTLR_DATA_LENGTH */
-
+	/* Transition to PHY Update Ind received state and  wait for the
+	 * instant.
+	 */
 	conn->llcp_type = LLCP_PHY_UPD;
 	conn->llcp_ack -= 2U;
 
+	/* Enforce packet timing restrictions until the instant */
 	if (conn->llcp.phy_upd_ind.tx) {
 		conn->lll.phy_tx_time = conn->llcp.phy_upd_ind.tx;
 	}

subsys/bluetooth/host/l2cap.c

@@ -872,6 +872,8 @@ static void l2cap_chan_tx_process(struct k_work *work)
 		if (sent < 0) {
 			if (sent == -EAGAIN) {
 				ch->tx_buf = buf;
+			} else {
+				net_buf_unref(buf);
 			}
 			break;
 		}

subsys/cpp/Kconfig

@@ -54,6 +54,7 @@ if LIB_CPLUSPLUS
 
 config EXCEPTIONS
 	bool "Enable C++ exceptions support"
+	depends on !NEWLIB_LIBC_NANO
 	help
 	  This option enables support of C++ exceptions.
 

subsys/logging/log_backend_fs.c

@@ -119,8 +119,8 @@ static int check_log_file_exist(int num)
 	while (true) {
 		rc = fs_readdir(&dir, &ent);
 		if (rc < 0) {
-			(void) fs_closedir(&dir);
-			return -EIO;
+			rc = -EIO;
+			goto close_dir;
 		}
 		if (ent.name[0] == 0) {
 			break;
@@ -129,13 +129,17 @@ static int check_log_file_exist(int num)
 		rc = get_log_file_id(&ent);
 
 		if (rc == num) {
-			return 1;
+			rc = 1;
+			goto close_dir;
 		}
 	}
 
+	rc = 0;
+
+close_dir:
 	(void) fs_closedir(&dir);
 
-	return 0;
+	return rc;
 }
 
 int write_log_to_file(uint8_t *data, size_t length, void *ctx)

tests/benchmarks/latency_measure/README.rst

@@ -15,27 +15,30 @@ This benchmark measures the latency of selected kernel capabilities, including:
 * Time it takes to resume a suspended thread
 * Time it takes to create a new thread (without starting it)
 * Time it takes to start a newly created thread
+* Measure average time to alloc memory from heap then free that memory
 
 
 Sample output of the benchmark::
 
-        *** Booting Zephyr OS build zephyr-v2.3.0-2257-g0f420483db07  ***
+        *** Booting Zephyr OS build zephyr-v2.6.0-1119-g378a1e082ac5  ***
         START - Time Measurement
-        Timing results: Clock frequency: 120 MHz
-        Average thread context switch using yield                   :     420 cycles ,     3502 ns
-        Average context switch time between threads (coop)          :     429 cycles ,     3583 ns
-        Switch from ISR back to interrupted thread                  :     670 cycles ,     5583 ns
-        Time from ISR to executing a different thread               :     570 cycles ,     4750 ns
-        Time to create a thread (without start)                     :     360 cycles ,     3000 ns
-        Time to start a thread                                      :     545 cycles ,     4541 ns
-        Time to suspend a thread                                    :     605 cycles ,     5041 ns
-        Time to resume a thread                                     :     660 cycles ,     5500 ns
-        Time to abort a thread (not running)                        :     495 cycles ,     4125 ns
-        Average semaphore signal time                               :     195 cycles ,     1626 ns
-        Average semaphore test time                                 :      62 cycles ,      518 ns
-        Semaphore take time (context switch)                        :     695 cycles ,     5791 ns
-        Semaphore give time (context switch)                        :     845 cycles ,     7041 ns
-        Average time to lock a mutex                                :      79 cycles ,      659 ns
-        Average time to unlock a mutex                              :     370 cycles ,     3085 ns
+        Timing results: Clock frequency: 1000 MHz
+        Average thread context switch using yield                   :    9060 cycles ,     9060 ns
+        Average context switch time between threads (coop)          :    9503 cycles ,     9503 ns
+        Switch from ISR back to interrupted thread                  :   14208 cycles ,    14208 ns
+        Time from ISR to executing a different thread               :    9664 cycles ,     9664 ns
+        Time to create a thread (without start)                     :    3968 cycles ,     3968 ns
+        Time to start a thread                                      :   12064 cycles ,    12064 ns
+        Time to suspend a thread                                    :   12640 cycles ,    12640 ns
+        Time to resume a thread                                     :   12096 cycles ,    12096 ns
+        Time to abort a thread (not running)                        :    2208 cycles ,     2208 ns
+        Average semaphore signal time                               :    8928 cycles ,     8928 ns
+        Average semaphore test time                                 :    2048 cycles ,     2048 ns
+        Semaphore take time (context switch)                        :   13472 cycles ,    13472 ns
+        Semaphore give time (context switch)                        :   18400 cycles ,    18400 ns
+        Average time to lock a mutex                                :    3072 cycles ,     3072 ns
+        Average time to unlock a mutex                              :    9251 cycles ,     9251 ns
+        Average time for heap malloc                                :   13056 cycles ,    13056 ns
+        Average time for heap free                                  :    7776 cycles ,     7776 ns
         ===================================================================
         PROJECT EXECUTION SUCCESSFUL

tests/benchmarks/latency_measure/prj.conf

@@ -22,3 +22,5 @@ CONFIG_PM=n
 # Can only run under 1 CPU
 CONFIG_MP_NUM_CPUS=1
 CONFIG_TIMING_FUNCTIONS=y
+
+CONFIG_HEAP_MEM_POOL_SIZE=2048

tests/benchmarks/latency_measure/src/heap_malloc_free.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+#include <timing/timing.h>
+#include "utils.h"
+
+#define TEST_COUNT 100
+#define TEST_SIZE 10
+
+void heap_malloc_free(void)
+{
+	timing_t heap_malloc_start_time = 0U;
+	timing_t heap_malloc_end_time = 0U;
+
+	timing_t heap_free_start_time = 0U;
+	timing_t heap_free_end_time = 0U;
+
+	uint32_t count = 0U;
+	uint32_t sum_malloc = 0U;
+	uint32_t sum_free = 0U;
+
+	timing_start();
+
+	while (count != TEST_COUNT) {
+		heap_malloc_start_time = timing_counter_get();
+		void *allocated_mem = k_malloc(TEST_SIZE);
+
+		heap_malloc_end_time = timing_counter_get();
+		if (allocated_mem == NULL) {
+			printk("Failed to alloc memory from heap "
+					"at count %d\n", count);
+			break;
+		}
+
+		heap_free_start_time = timing_counter_get();
+		k_free(allocated_mem);
+		heap_free_end_time = timing_counter_get();
+
+		sum_malloc += timing_cycles_get(&heap_malloc_start_time,
+				&heap_malloc_end_time);
+		sum_free += timing_cycles_get(&heap_free_start_time,
+				&heap_free_end_time);
+		count++;
+	}
+
+	PRINT_STATS_AVG("Average time for heap malloc", sum_malloc, count);
+	PRINT_STATS_AVG("Average time for heap free", sum_free, count);
+
+	timing_stop();
+}

tests/benchmarks/latency_measure/src/main.c

@@ -27,6 +27,7 @@ extern int coop_ctx_switch(void);
 extern int sema_test(void);
 extern int sema_context_switch(void);
 extern int suspend_resume(void);
+extern void heap_malloc_free(void);
 
 void test_thread(void *arg1, void *arg2, void *arg3)
 {
@@ -57,6 +58,8 @@ void test_thread(void *arg1, void *arg2, void *arg3)
 
 	mutex_lock_unlock();
 
+	heap_malloc_free();
+
 	TC_END_REPORT(error_count);
 }
 

tests/subsys/cpp/libcxx/testcase.yaml

@@ -3,14 +3,17 @@ common:
   integration_platforms:
     - mps2_an385
 tests:
-  cpp.libcxx:
+  cpp.libcxx.newlib:
     toolchain_exclude: xcc
     min_flash: 54
     tags: cpp
-  cpp.libcxx.exceptions:
+    extra_configs:
+        - CONFIG_NEWLIB_LIBC_NANO=n
+        - CONFIG_EXCEPTIONS=y
+  cpp.libcxx.newlib_nano:
     toolchain_exclude: xcc
     min_flash: 54
     tags: cpp
     timeout: 30
     extra_configs:
-        - CONFIG_EXCEPTIONS=y
+        - CONFIG_NEWLIB_LIBC_NANO=y

west.yml

@@ -134,7 +134,7 @@ manifest:
       revision: a47e326ca772ddd14cc3b9d4ca30a9ab44ecca16
     - name: TraceRecorderSource
       path: modules/debug/TraceRecorder
-      revision: d9889883abb4657d71e15ff055517a9b032f8212
+      revision: 5b5f8d7adbf0e93a09087e8f5708f0eebb8b25bf
     - name: hal_xtensa
       revision: 2f04b615cd5ad3a1b8abef33f9bdd10cc1990ed6
       path: modules/hal/xtensa