Zephyr 1.3.0

Change-Id: I44ebde6cab75fbf64666c1a574ec57463a7167b0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.gitignore

@@ -5,7 +5,7 @@
 *.pyc
 *.swp
 *.swo
-!arch/*/*/*/*.cmd
+!arch/*/*/**/*.cmd
 *~
 cscope.*
 .dir
@@ -19,9 +19,9 @@ scripts/kconfig/zconf.hash.c
 scripts/kconfig/zconf.lex.c
 scripts/kconfig/zconf.tab.c
 doc/_build
-xml
-html/
-doc/latex/
+doc/xml
+doc/html
+doc/latex
 sanity-out/
 scripts/grub
 doc/reference/kconfig/CONFIG_*

.gitreview

@@ -0,0 +1,4 @@
+[gerrit]
+host=gerrit.zephyrproject.org
+port=29418
+project=zephyr.git

Kconfig

@@ -15,6 +15,6 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 #
-mainmenu "Zephyr Kernel/$ARCH Configuration"
+mainmenu "Zephyr Kernel Configuration"
 
 source "Kconfig.zephyr"

Kconfig.zephyr

@@ -2,6 +2,7 @@
 
 #
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
+# Copyright (c) 2016 Intel Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -29,3 +30,12 @@ source "net/Kconfig"
 
 source "misc/Kconfig"
 
+#
+# The following are for Kconfig files for default values only.
+# These should be parsed at the end.
+#
+# Board defaults should be parsed before SoC defaults
+# because board usually overrides them.
+#
+source "boards/*/Kconfig.defconfig"
+source "arch/*/soc/*/Kconfig.defconfig"

Makefile

@@ -1,5 +1,5 @@
 VERSION_MAJOR 	   = 1
-VERSION_MINOR 	   = 0
+VERSION_MINOR 	   = 3
 PATCHLEVEL 	   = 0
 VERSION_RESERVED   = 0
 EXTRAVERSION       =
@@ -7,11 +7,9 @@ NAME 		   = Zephyr Kernel
 
 export SOURCE_DIR PROJECT MDEF_FILE
 
-ifneq ($(MAKECMDGOALS),help)
-ifeq ($(PROJECT),)
+ifeq ($(MAKECMDGOALS),)
 $(error Invoking make from top-level kernel directory is not supported)
 endif
-endif
 
 # *DOCUMENTATION*
 # To see a list of typical targets execute "make help"
@@ -283,15 +281,6 @@ KBUILD_BUILTIN := 1
 export KBUILD_BUILTIN
 export KBUILD_CHECKSRC KBUILD_SRC
 
-ifneq ($(CC),)
-ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
-COMPILER := clang
-else
-COMPILER := gcc
-endif
-export COMPILER
-endif
-
 # Look for make include files relative to root of kernel src
 MAKEFLAGS += --include-dir=$(srctree)
 
@@ -347,18 +336,22 @@ endif
 USERINCLUDE    := -include $(CURDIR)/include/generated/autoconf.h
 
 SOC_NAME = $(subst $(DQUOTE),,$(CONFIG_SOC))
+SOC_SERIES = $(subst $(DQUOTE),,$(CONFIG_SOC_SERIES))
+SOC_FAMILY = $(subst $(DQUOTE),,$(CONFIG_SOC_FAMILY))
+
 override ARCH = $(subst $(DQUOTE),,$(CONFIG_ARCH))
 BOARD_NAME = $(subst $(DQUOTE),,$(CONFIG_BOARD))
 KERNEL_NAME = $(subst $(DQUOTE),,$(CONFIG_KERNEL_BIN_NAME))
 KERNEL_ELF_NAME = $(KERNEL_NAME).elf
 KERNEL_BIN_NAME = $(KERNEL_NAME).bin
 
-export SOC_NAME BOARD_NAME ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME
+export SOC_FAMILY SOC_SERIES SOC_PATH SOC_NAME BOARD_NAME
+export ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME
 # Use ZEPHYRINCLUDE when you must reference the include/ directory.
 # Needed to be compatible with the O= option
 ZEPHYRINCLUDE    = \
 		-I$(srctree)/arch/$(ARCH)/include \
-		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_NAME) \
+		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH) \
 		-I$(srctree)/boards/$(BOARD_NAME) \
 		$(if $(KBUILD_SRC), -I$(srctree)/include) \
 		-I$(srctree)/include \
@@ -450,7 +443,7 @@ endif
 
 version_h := include/generated/version.h
 
-no-dot-config-targets := pristine distclean clean mrproper help \
+no-dot-config-targets := pristine distclean clean mrproper help kconfig-help \
 			 cscope gtags TAGS tags help% %docs check% \
 			 $(version_h) headers_% kernelversion %src-pkg
 
@@ -521,8 +514,16 @@ scripts: scripts_basic include/config/auto.conf include/config/tristate.conf
 core-y := lib/ kernel/ misc/ net/ boards/ arch/
 drivers-y := drivers/
 
+ifneq ($(strip $(MAKEFILE_APP_DIR)),)
+MAKEFILE_APP := $(realpath $(MAKEFILE_APP_DIR)/Makefile.app)
+endif
+
 ifneq ($(strip $(PROJECT)),)
+ifneq ($(strip $(MAKEFILE_APP)), )
+include $(MAKEFILE_APP)
+else
 -include $(PROJECT)/Makefile.app
+endif
 ifneq ($(strip $(KBUILD_ZEPHYR_APP)),)
 export KBUILD_ZEPHYR_APP
 endif
@@ -569,7 +570,16 @@ $(if $(CROSS_COMPILE),, \
      $(error ZEPHYR_GCC_VARIANT is not set. ))
 endif
 
-ifdef CONFIG_QMSI_DRIVERS
+ifneq ($(CC),)
+ifeq ($(shell $(CC) -v 2>&1 | grep -Ec "clang version|icx version"), 1)
+COMPILER := clang
+else
+COMPILER := gcc
+endif
+export COMPILER
+endif
+
+ifdef CONFIG_QMSI_LIBRARY
 LIB_INCLUDE_DIR += -L$(CONFIG_QMSI_INSTALL_PATH:"%"=%)/lib
 ALL_LIBS += qmsi
 endif
@@ -580,7 +590,7 @@ endif
 
 ifdef CONFIG_NEWLIB_LIBC
 ZEPHYRINCLUDE += $(TOOLCHAIN_CFLAGS)
-ALL_LIBS += c m
+ALL_LIBS += m c
 endif
 
 QEMU_BIN_PATH	?= /usr/bin
@@ -618,6 +628,11 @@ KBUILD_CFLAGS += $(subst $(DQUOTE),,$(CONFIG_COMPILER_OPT))
 
 export LDFLAG_LINKERCMD
 
+ifeq ($(SOC_SERIES),)
+SOC_PATH = $(SOC_NAME)
+else
+SOC_PATH = $(SOC_FAMILY)/$(SOC_SERIES)
+endif
 include arch/$(ARCH)/Makefile
 
 KBUILD_CFLAGS += $(CFLAGS)
@@ -626,7 +641,6 @@ KBUILD_AFLAGS += $(CFLAGS)
 
 
 ifeq ($(COMPILER),clang)
-KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
 KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,)
 KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
 KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
@@ -649,6 +663,7 @@ endif
 
 # arch Makefile may override CC so keep this after arch Makefile is included
 NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
+NOSTDINC_FLAGS += -isystem $(shell $(CC) -print-file-name=include-fixed)
 CHECKFLAGS     += $(NOSTDINC_FLAGS)
 
 # disable pointer signed / unsigned warnings in gcc 4.0
@@ -698,7 +713,7 @@ KBUILD_LDS := $(srctree)/boards/$(BOARD_NAME)/linker.cmd
 
 # If not available, try an SoC specific linker file
 ifeq ($(wildcard $(KBUILD_LDS)),)
-KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/linker.cmd
+KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/linker.cmd
 endif
 endif
 
@@ -998,6 +1013,12 @@ distclean: mrproper
 boards := $(wildcard $(srctree)/boards/*/*_defconfig)
 boards := $(sort $(notdir $(boards)))
 
+kconfig-help:
+	@echo  'Configuration targets:'
+	@echo  ''
+	@$(MAKE) -f $(srctree)/scripts/kconfig/Makefile help
+	@echo  ''
+
 help:
 	@echo  'Cleaning targets:'
 	@echo  '  clean		  - Remove most generated files but keep configuration and backup files'
@@ -1006,13 +1027,15 @@ help:
 	@echo  '  pristine	  - Remove the output directory with all generated files'
 	@echo  ''
 	@echo  'Configuration targets:'
-	@$(MAKE) -f $(srctree)/scripts/kconfig/Makefile help
+	@echo  ''
+	@echo  '  run <make kconfig-help>'
 	@echo  ''
 	@echo  'Other generic targets:'
 	@echo  '  all		  - Build all targets marked with [*]'
 	@echo  '* zephyr	  - Build a zephyr application'
 	@echo  '  qemu		  - Build a zephyr application and run it in qemu'
 	@echo  '  flash		  - Build and flash an application'
+	@echo  '  debug		  - Build and debug an application using GDB'
 	@echo  ''
 	@echo  'Supported Boards:'
 	@echo  ''
@@ -1020,15 +1043,19 @@ help:
 	@echo  ''
 	@echo  '  make BOARD=<BOARD NAME>'
 	@echo  '  in the application directory.'
+	@echo  ''
 	@echo  '  To flash the image (if supported), run:'
 	@echo  ''
 	@echo  '  make BOARD=<BOARD NAME> flash'
 	@echo  ''
 	@$(if $(boards), \
 		$(foreach b, $(boards), \
-		printf "  %-24s - Build for %s\\n" $(b) $(subst _defconfig,,$(b));) \
+		printf "  make BOARD=%-24s - Build for %s\\n" $(subst _defconfig,,$(b)) $(subst _defconfig,,$(b));) \
 		echo '')
 
+	@echo  ''
+	@echo  'Build flags:'
+	@echo  ''
 	@echo  '  make V=0|1 [targets] 0 => quiet build (default), 1 => verbose build'
 	@echo  '  make V=2   [targets] 2 => give reason for rebuild of target'
 	@echo  '  make O=dir [targets] Locate all output files in "dir", including .config'
@@ -1118,6 +1145,7 @@ endif
 qemu: zephyr
 	$(if $(QEMU_PIPE),,@echo "To exit from QEMU enter: 'CTRL+a, x'")
 	@echo '[QEMU] CPU: $(QEMU_CPU_TYPE_$(ARCH))'
+	$(if $(CONFIG_X86_IAMCU),python $(ZEPHYR_BASE)/scripts/qemu-machine-hack.py $(KERNEL_ELF_NAME))
 	$(Q)$(QEMU) $(QEMU_FLAGS) $(QEMU_EXTRA_FLAGS) -kernel $(KERNEL_ELF_NAME)
 
 -include $(srctree)/boards/$(BOARD_NAME)/Makefile.board

Makefile.inc

@@ -24,8 +24,10 @@ KERNEL_TYPE ?= micro
 override CONF_FILE := $(strip $(subst $(DQUOTE),,$(CONF_FILE)))
 
 ifdef BOARD
-KBUILD_DEFCONFIG_PATH=$(ZEPHYR_BASE)/boards/$(BOARD)/$(BOARD)_defconfig
-export KBUILD_DEFCONFIG_PATH
+KBUILD_DEFCONFIG_PATH=$(wildcard $(ZEPHYR_BASE)/boards/*/$(BOARD)_defconfig)
+ifeq ($(KBUILD_DEFCONFIG_PATH),)
+$(error Board $(BOARD) not found!)
+endif
 else
 $(error BOARD is not defined!)
 endif

arch/Kconfig

@@ -30,25 +30,68 @@ config ARM
 
 config X86
 	bool "x86 architecture"
+	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
 
 endchoice
 
+#
+# Hidden PM feature configs which are to be selected by
+# individual SoC.
+#
+config SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	# Hidden
+        bool
+        default n
+        help
+        This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
+        configuration option.
+
+config SYS_POWER_DEEP_SLEEP_SUPPORTED
+	# Hidden
+        bool
+        default n
+        help
+        This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
+        configuration option.
+#
+# End hidden PM feature configs
+#
+
 config ARCH
 	string
 	help
 	System architecture string.
 
 config SOC
-        string
-        help
-        This option holds the directory name used by the build system to locate
-        the correct linker file.
+	string
+	help
+	SoC name which can be found under arch/<arch>/soc/<soc name>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files for the SoC. This option will go away
+	once all SoCs are using family/series structure.
+
+config SOC_SERIES
+	string
+	help
+	SoC series name which can be found under arch/<arch>/soc/<family>/<series>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
+
+config SOC_FAMILY
+	string
+	help
+	SoC family name which can be found under arch/<arch>/soc/<family>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
 
 config BOARD
 	string
 	help
 	This option holds the name of the board and is used to located the files
-	related to the board in the source tree.
+	related to the board in the source tree (under boards/).
+	The Board is the first location where we search for a linker.cmd file,
+	if not found we look for the linker file in
+	arch/<arch>/soc/<family>/<series>
 
 source "arch/*/Kconfig"
 

arch/Makefile

@@ -1,9 +1 @@
-ifeq (${ARCH},arm)
-obj-y += arm/
-endif
-ifeq (${ARCH},x86)
-obj-y += x86/
-endif
-ifeq (${ARCH},arc)
-obj-y += arc/
-endif
+obj-y += $(ARCH)/

arch/arc/Kbuild

@@ -2,5 +2,5 @@ subdir-ccflags-y +=-I$(srctree)/include/drivers
 subdir-ccflags-y +=-I$(srctree)/drivers
 subdir-asflags-y += $(subdir-ccflags-y)
 
-obj-y += soc/$(SOC_NAME)/
+obj-y += soc/$(SOC_PATH)/
 obj-y += core/

arch/arc/Kconfig

@@ -15,7 +15,16 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 #
-menu "ARC architecture"
+
+choice
+	prompt "ARC SoC Selection"
+	depends on ARC
+
+	source "arch/arc/soc/*/Kconfig.soc"
+endchoice
+
+
+menu "ARC Options"
 	depends on ARC
 
 config ARCH
@@ -25,17 +34,13 @@ config ARCH_DEFCONFIG
 	string
 	default "arch/arc/defconfig"
 
-choice
-prompt "SoC Selection"
-source "arch/arc/soc/*/Kconfig.soc"
-endchoice
-
 menu "ARC EM4 processor options"
 
 config	CPU_ARCEM4
 	bool
 	default y
 	select CPU_ARCV2
+	select ATOMIC_OPERATIONS_C
 	help
 	This option signifies the use of an ARC EM4 CPU
 
@@ -50,14 +55,6 @@ config	CPU_ARCV2
 	help
 	  This option signifies the use of a CPU of the ARCv2 family.
 
-config RAM_START
-	prompt "RAM start address"
-	hex
-
-config RAM_SIZE
-	prompt "RAM size (in kB)"
-	int
-
 config NSIM
 	prompt "Running on the MetaWare nSIM simulator"
 	bool
@@ -82,7 +79,6 @@ config	DATA_ENDIANNESS_LITTLE
 config	NUM_IRQ_PRIO_LEVELS
 	int
 	prompt "Number of supported interrupt priority levels"
-	default 1
 	range 1 16
 	help
 	  Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
@@ -93,12 +89,12 @@ config	NUM_IRQ_PRIO_LEVELS
 config	NUM_REGULAR_IRQ_PRIO_LEVELS
 	int
 	prompt "Number of supported regular interrupt priority levels"
-	default 1
 	range 1 16
 	help
 	 This represents the number of Regular Interrupt priorities, which
 	 does NOT include the Fast (FIRQ) priority.
 	 The Regular Interrupt priorities available will be
+
 	  (NUM_IRQ_PRIO_LEVELS - NUM_REGULAR_IRQ_PRIO_LEVELS) to
 	  (NUM_REGULAR_IRQ_PRIO_LEVELS - 1).
 
@@ -127,6 +123,14 @@ config	FIRQ_STACK_SIZE
 	  FIRQs and regular IRQs have different stacks so that a FIRQ can start
 	  running without doing stack switching in software.
 
+config	ARC_STACK_CHECKING
+	bool "Enable Stack Checking"
+	depends on CPU_ARCV2
+	default n
+	help
+	  ARCV2 has a special feature allowing to check stack overflows. This
+	  enables code that allows using this debug feature
+
 config	FAULT_DUMP
 	int
 	prompt "Fault dump level"
@@ -153,12 +157,54 @@ config	XIP
 	default n if NSIM
 	default y
 
+config DCCM_SIZE
+	int "DCCM Size in kB"
+	help
+	This option specifies the size of the DCCM in kB.  It is normally set by
+	the platform's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config DCCM_BASE_ADDRESS
+	hex "DCCM Base Address"
+	help
+	This option specifies the base address of the DCCM on the platform.  It is
+	normally set by the platform's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config SRAM_SIZE
+	int "SRAM Size in kB"
+	help
+	This option specifies the size of the SRAM in kB.  It is normally set by
+	the platform's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config SRAM_BASE_ADDRESS
+	hex "SRAM Base Address"
+	help
+	This option specifies the base address of the SRAM on the platform.  It is
+	normally set by the platform's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config FLASH_SIZE
+	int "Flash Size in kB"
+	help
+	This option specifies the size of the flash in kB.  It is normally set by
+	the platform's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config FLASH_BASE_ADDRESS
+	hex "Flash Base Address"
+	help
+	This option specifies the base address of the flash on the platform.  It is
+	normally set by the platform's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
 config NSIM
 	prompt "Running on the MetaWare nSIM simulator"
 	bool
 	default n
 	help
 	For running on nSIM simulator.
+
 	a) Uses non-XIP to run in RAM.
 	b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
 	   a pc_size of 16 (default).
@@ -188,24 +234,6 @@ config  SW_ISR_TABLE_DYNAMIC
 	  SRAM so that it is writable. This has the side-effect of removing
 	  write-protection on the ISR table.
 
-config  SW_ISR_TABLE_STATIC_CUSTOM
-	bool
-	prompt "Projects provide a custom static software ISR table"
-	depends on SW_ISR_TABLE && !SW_ISR_TABLE_DYNAMIC
-	default n
-	help
-	  Projects, not the BSP, provide a software table of ISR and their
-	  parameters. The table is static, and thus ISRs cannot be connected
-	  at runtime.
-
-config	SW_ISR_TABLE_BSP
-	bool
-	# omit prompt to signify a "hidden" option
-	depends on SW_ISR_TABLE_DYNAMIC || (SW_ISR_TABLE && !SW_ISR_TABLE_STATIC_CUSTOM)
-	default y
-	help
-	  Not user-selectable, helps build system logic.
-
 config  IRQ_VECTOR_TABLE_CUSTOM
 	bool
 	prompt "Projects provide a custom static IRQ part of vector table"
@@ -222,10 +250,11 @@ config  IRQ_VECTOR_TABLE_CUSTOM
 	  the least overhead when handling an interrupt.
 
 	  Downsides:
+
 	  - ISRs cannot have a parameter
 	  - ISRs cannot be connected at runtime
 	  - ISRs must notify the kernel manually by invoking _ExcExit() when
-		then are about to return.
+	    then are about to return.
 
 config	IRQ_VECTOR_TABLE_BSP
 	bool
@@ -245,19 +274,6 @@ config  ARCH_HAS_NANO_FIBER_ABORT
 	# omit prompt to signify a "hidden" option
 	default n
 
-config  ARC_ATOMIC_ASM
-	bool
-	default n
-	depends on !CPU_ARCEM4
-	help
-	  Say y if the processor supports atomic assembly instructions:
-	  LLOCK and SCOND.
-
-	  Say n if not sure.
-
-	  Note that these instructions are not supported on ARC EM family
-	  processors.
-
 endmenu
 
 

arch/arc/Makefile

@@ -1,7 +1,8 @@
 cflags-y += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
+cflags-$(CONFIG_ARC_STACK_CHECKING) = $(call cc-option,-fomit-frame-pointer)
 cflags-$(CONFIG_LTO) = $(call cc-option,-flto,)
 
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/Makefile
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 
 KBUILD_CFLAGS += $(cflags-y)
 KBUILD_CXXFLAGS += $(cflags-y)

arch/arc/core/Makefile

@@ -15,8 +15,9 @@ obj-y += prep_c.o \
 obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
 obj-$(CONFIG_ERRNO) += errno.o
 
-ifeq ($(CONFIG_ARC_ATOMIC_ASM),y)
+ifneq ($(CONFIG_ATOMIC_OPERATIONS_C),y)
 obj-y += atomic.o
-else
-obj-y += atomic_native.o
 endif
+
+obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
+obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o

arch/arc/core/fast_irq.S

@@ -48,8 +48,8 @@ SECTION_VAR(NOINIT, _firq_stack)
  * LP_COUNT/LP_END registers, which are not banked.
  *
  * If all FIRQ ISRs are programmed such that there are no use of the LP
- * registers (ie. no LPcc instruction), then the kernel can be configured to
- * remove the use of _firq_enter().
+ * registers (ie. no LPcc instruction), and CONFIG_ARC_STACK_CHECKING is
+ * not set, then the kernel can be configured to remove the use of _firq_enter().
  *
  * When entering a FIRQ, interrupts might as well be locked: the processor is
  * running at its highest priority, and cannot be preempted by anything.
@@ -61,6 +61,13 @@ SECTION_VAR(NOINIT, _firq_stack)
 
 SECTION_FUNC(TEXT, _firq_enter)
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+#endif
+
 #ifndef CONFIG_FIRQ_NO_LPCC
 	/*
 	 * Unlike the rest of context switching code, r2 is loaded with something
@@ -71,8 +78,6 @@ SECTION_FUNC(TEXT, _firq_enter)
 	/* save LP_START/LP_COUNT/LP_END variables */
 	mov_s r1, _nanokernel
 
-	/* cannot store lp_count directly to memory */
-	mov r2, lp_count
 	st lp_count, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_count_OFFSET]
 
 	lr r2, [_ARC_V2_LP_START]
@@ -184,6 +189,13 @@ _firq_reschedule:
 	ld r3, [r2, __tTCS_link_OFFSET]
 	st r3, [r1, __tNANO_fiber_OFFSET]
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* Use stack top and down registers from restored context */
+	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	sr r3, [_ARC_V2_KSTACK_TOP]
+	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	sr r3, [_ARC_V2_KSTACK_BASE]
+#endif
 	/*
 	 * _load_callee_saved_regs expects incoming thread in r2.
 	 * _load_callee_saved_regs restores the stack pointer.

arch/arc/core/irq_manage.c

@@ -36,7 +36,7 @@
 #include <toolchain.h>
 #include <sections.h>
 #include <sw_isr_table.h>
-
+#include <irq.h>
 
 /*
  * @brief Enable an interrupt line
@@ -48,7 +48,7 @@
  * @return N/A
  */
 
-void irq_enable(unsigned int irq)
+void _arch_irq_enable(unsigned int irq)
 {
 	int key = irq_lock();
 
@@ -65,7 +65,7 @@ void irq_enable(unsigned int irq)
  * @return N/A
  */
 
-void irq_disable(unsigned int irq)
+void _arch_irq_disable(unsigned int irq)
 {
 	int key = irq_lock();
 
@@ -158,7 +158,7 @@ void _irq_handler_set(
  * @return the interrupt line number
  */
 
-int irq_connect_dynamic(
+int _arch_irq_connect_dynamic(
 	unsigned int irq,
 	unsigned int prio,
 	void (*isr)(void *arg),

arch/arc/core/isr_wrapper.S

@@ -211,6 +211,22 @@ SECTION_FUNC(TEXT, _isr_enter)
 
 	j_s.nd [r2]
 
+#if defined(CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT)
+GTEXT(_sys_k_event_logger_interrupt)
+
+.macro log_interrupt_k_event
+	clri r0 /* do not interrupt event logger operations */
+	push_s r0
+	push_s blink
+	jl _sys_k_event_logger_interrupt
+	pop_s blink
+	pop_s r0
+	seti r0
+.endm
+#else
+	#define log_interrupt_k_event
+#endif
+
 #if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
 .macro exit_tickless_idle
 	clri r0 /* do not interrupt exiting tickless idle operations */
@@ -232,6 +248,7 @@ SECTION_FUNC(TEXT, _isr_demux)
 	/* cannot be done before this point because we must be able to run C */
 	/* r0 is available to be stomped here, and exit_tickless_idle uses it */
 	exit_tickless_idle
+	log_interrupt_k_event
 
 	lr r0, [_ARC_V2_ICAUSE]
 	sub r0, r0, 16

arch/arc/core/offsets/offsets.c

@@ -40,14 +40,17 @@
 /* ARCv2-specific tNANO structure member offsets */
 GEN_OFFSET_SYM(tNANO, rirq_sp);
 GEN_OFFSET_SYM(tNANO, firq_regs);
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 GEN_OFFSET_SYM(tNANO, idle);
-#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
+#endif
 
 /* ARCv2-specific struct tcs structure member offsets */
 GEN_OFFSET_SYM(tTCS, intlock_key);
 GEN_OFFSET_SYM(tTCS, relinquish_cause);
 GEN_OFFSET_SYM(tTCS, return_value);
+#ifdef CONFIG_ARC_STACK_CHECKING
+GEN_OFFSET_SYM(tTCS, stack_top);
+#endif
 #ifdef CONFIG_THREAD_CUSTOM_DATA
 GEN_OFFSET_SYM(tTCS, custom_data);
 #endif

arch/arc/core/regular_irq.S

@@ -51,6 +51,12 @@ GTEXT(_rirq_exit)
 SECTION_FUNC(TEXT, _rirq_enter)
 
 	mov r1, _nanokernel
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+#endif
 	ld r2, [r1, __tNANO_current_OFFSET]
 #if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS == 1
 	st sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
@@ -126,6 +132,13 @@ _rirq_reschedule:
 	ld r3, [r2, __tTCS_link_OFFSET]
 	st r3, [r1, __tNANO_fiber_OFFSET]
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* Use stack top and down registers from restored context */
+	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	sr r3, [_ARC_V2_KSTACK_TOP]
+	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	sr r3, [_ARC_V2_KSTACK_BASE]
+#endif
 	/*
 	 * _load_callee_saved_regs expects incoming thread in r2.
 	 * _load_callee_saved_regs restores the stack pointer.

arch/arc/core/reset.S

@@ -28,7 +28,7 @@
 #include <sections.h>
 #include <arch/cpu.h>
 
-#define _RAM_END (CONFIG_RAM_START + CONFIG_RAM_SIZE * 1024)
+#define _RAM_END (CONFIG_SRAM_BASE_ADDRESS + CONFIG_SRAM_SIZE * 1024)
 
 GTEXT(__reset)
 

arch/arc/core/swap.S

@@ -86,6 +86,11 @@ SECTION_FUNC(TEXT, _Swap)
 	 */
 	lr r3, [_ARC_V2_STATUS32]
 	push_s r3
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* disable stack checking during swap */
+	bclr r3, r3, _ARC_V2_STATUS32_SC_BIT
+	kflag r3
+#endif
 	push_s blink
 
 	_save_callee_saved_regs
@@ -118,7 +123,13 @@ _finish_swapping_to_thread:
 	ld r3, [r2, __tTCS_flags_OFFSET]
 	st r3, [r1, __tNANO_flags_OFFSET]
 #endif
-
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* Use stack top and down registers from restored context */
+	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	sr r3, [_ARC_V2_KSTACK_TOP]
+	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	sr r3, [_ARC_V2_KSTACK_BASE]
+#endif
 	/* XXX - can be moved to delay slot of _CAUSE_RIRQ ? */
 	st r2, [r1, __tNANO_current_OFFSET]
 
@@ -168,11 +179,23 @@ _swap_return_from_firq:
 	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
 
 	ld ilink, [sp, -4] /* status32 into ilink */
+#ifdef CONFIG_ARC_STACK_CHECKING
+	and ilink, ilink, 0x7fffbffe // keep SC off till we stop using under SP
+#else
 	and ilink, ilink, 0x7ffffffe // keep interrupts disabled until seti
+#endif
 	kflag ilink
 
 	ld ilink, [sp, -8] /* pc into ilink */
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* Enable stack checking now it is safe */
+	push_s r3
+	lr r3, [_ARC_V2_STATUS32]
+	bset r3, r3, _ARC_V2_STATUS32_SC_BIT
+	flag r3
+	pop_s r3
+#endif
 	j.d [ilink]
 	seti (_ARC_V2_DEF_IRQ_LEVEL | (1 << 4))
 

arch/arc/core/thread.c

@@ -131,8 +131,12 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 	 * enable the interrupts based on intlock_key
 	 * value.
 	 */
+#ifdef CONFIG_ARC_STACK_CHECKING
+	pInitCtx->status32 = _ARC_V2_STATUS32_SC | _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
+	tcs->stack_top = (uint32_t) stackEnd;
+#else
 	pInitCtx->status32 = _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
-
+#endif
 	tcs->link = NULL;
 	tcs->flags = priority == -1 ? TASK | PREEMPTIBLE : FIBER;
 	tcs->prio = priority;
@@ -143,6 +147,13 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 	tcs->custom_data = NULL;
 #endif
 
+#ifdef CONFIG_THREAD_MONITOR
+	/*
+	 * In debug mode tcs->entry give direct access to the thread entry
+	 * and the corresponding parameters.
+	 */
+	tcs->entry = (struct __thread_entry *)(pInitCtx);
+#endif
 	/*
 	 * intlock_key is constructed based on ARCv2 ISA Programmer's
 	 * Reference Manual CLRI instruction description:

arch/arc/include/kernel_event_logger_arch.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Kernel event logger support for ARM
+ */
+
+#ifndef __KERNEL_EVENT_LOGGER_ARCH_H__
+#define __KERNEL_EVENT_LOGGER_ARCH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get the identification of the current interrupt.
+ *
+ * This routine obtain the key of the interrupt that is currently processed
+ * if it is called from a ISR context.
+ *
+ * @return The key of the interrupt that is currently being processed.
+ */
+int _sys_current_irq_key_get(void)
+{
+	return _INTERRUPT_CAUSE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __KERNEL_EVENT_LOGGER_ARCH_H__ */

arch/arc/include/nano_private.h

@@ -48,6 +48,16 @@ extern "C" {
 #endif
 
 #ifndef _ASMLANGUAGE
+
+#ifdef CONFIG_THREAD_MONITOR
+struct __thread_entry {
+	_thread_entry_t pEntry;
+	void *parameter1;
+	void *parameter2;
+	void *parameter3;
+};
+#endif /*CONFIG_THREAD_MONITOR*/
+
 struct coop {
 	/*
 	 * Saved on the stack as part of handling a regular IRQ or by the kernel
@@ -175,6 +185,7 @@ struct tcs {
 	struct coop coopReg;
 	struct preempt preempReg;
 #ifdef CONFIG_THREAD_MONITOR
+	struct __thread_entry *entry; /* thread entry and parameters description */
 	struct tcs *next_thread;  /* next item in list of ALL fiber+tasks */
 #endif
 #ifdef CONFIG_NANO_TIMEOUTS
@@ -183,6 +194,9 @@ struct tcs {
 #ifdef CONFIG_ERRNO
 	int errno_var;
 #endif
+#ifdef CONFIG_ARC_STACK_CHECKING
+	uint32_t stack_top;
+#endif
 };
 
 struct s_NANO {
@@ -198,7 +212,7 @@ struct s_NANO {
 	struct tcs *current_fp; /* thread (fiber or task) that owns the FP regs */
 #endif
 
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 	int32_t idle; /* Number of ticks for kernel idling */
 #endif
 
@@ -210,7 +224,7 @@ struct s_NANO {
 	 */
 
 	struct firq_regs firq_regs;
-#ifdef CONFIG_NANO_TIMEOUTS
+#if defined(CONFIG_NANO_TIMEOUTS) || defined(CONFIG_NANO_TIMERS)
 	sys_dlist_t timeout_q;
 	int32_t task_timeout;
 #endif
@@ -264,6 +278,21 @@ static ALWAYS_INLINE int _IS_IN_ISR(void)
 	return ((act & 0xffff) != 0);
 }
 
+/**
+ *
+ * @bried Indicates the interrupt number of the highest priority
+ * active interrupt
+ *
+ * @return IRQ number
+ */
+static ALWAYS_INLINE int _INTERRUPT_CAUSE(void)
+{
+	uint32_t irq_num = _arc_v2_aux_reg_read(_ARC_V2_ICAUSE);
+
+	return irq_num;
+}
+
+
 extern void nanoCpuAtomicIdle(unsigned int);
 extern void _thread_entry_wrapper(void);
 

arch/arc/soc/quark_se_ss/Kbuild

@@ -7,5 +7,3 @@ ccflags-$(CONFIG_ADC) +=-I$(srctree)/drivers/adc
 asflags-y := ${ccflags-y}
 
 obj-y = soc.o soc_config.o
-obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
-obj-$(CONFIG_SW_ISR_TABLE_BSP) += sw_isr_table.o

arch/arc/soc/quark_se_ss/Kconfig.defconfig

@@ -1,5 +1,6 @@
 #
 # Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2015-2016 Intel Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -36,72 +37,91 @@ config  NUM_IRQS
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 32000000
 
-config RAM_START
+config FLASH_BASE_ADDRESS
+	default 0x40000000
+
+config FLASH_SIZE
+	default 152
+
+config SRAM_BASE_ADDRESS
 	default 0x4000 if NSIM
 	default 0xa8000400
 
-config RAM_SIZE
+config SRAM_SIZE
 	default 16 if NSIM
 	default 24
 
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 8
+
 if GPIO
+
 config GPIO_DW
 	def_bool y
+
+if GPIO_DW
+
 config GPIO_DW_BOTHEDGES_SUPPORT
 	default n
 
 config GPIO_DW_0
 	def_bool y
-config GPIO_DW_0_BASE_ADDR
-	default 0x80017800
-config GPIO_DW_0_IRQ
-	default 20
-config GPIO_DW_0_BITS
-	default 8
+
+if GPIO_DW_0
+
+config GPIO_DW_0_PRI
+	default 2
+
+endif # GPIO_DW_0
 
 config GPIO_DW_1
 	def_bool y
-config GPIO_DW_1_BASE_ADDR
-	default 0x80017900
-config GPIO_DW_1_IRQ
-	default 21
-config GPIO_DW_1_BITS
-	default 8
-endif
+
+if GPIO_DW_1
+
+config GPIO_DW_1_PRI
+	default 2
+
+endif # GPIO_DW_1
+
+endif # GPIO_DW
+
+endif # GPIO
 
 if I2C
 
 config I2C_QUARK_SE_SS
 	def_bool y
 
+if I2C_QUARK_SE_SS
+
 config I2C_QUARK_SE_SS_0
 	def_bool y
 
 if I2C_QUARK_SE_SS_0
 
-config I2C_QUARK_SE_SS_0_BASE
-	default 0x80012000
-
 config I2C_QUARK_SE_SS_0_NAME
-	default "I2C0"
+	default "I2C_0"
 
 config I2C_QUARK_SE_SS_0_DEFAULT_CFG
 	default 0x12
 
-endif
+endif # I2C_QUARK_SE_SS_0
 
 if I2C_QUARK_SE_SS_1
 
-config I2C_QUARK_SE_SS_1_BASE
-	default 0x80012100
-
 config I2C_QUARK_SE_SS_1_NAME
-	default "I2C1"
+	default "I2C_1"
 
 config I2C_QUARK_SE_SS_1_DEFAULT_CFG
 	default 0x12
 
-endif
+endif # I2C_QUARK_SE_SS_1
+
+endif # I2C_QUARK_SE_SS
 
 endif # I2C
 
@@ -114,16 +134,10 @@ if UART_NS16550_PORT_0
 
 config UART_NS16550_PORT_0_NAME
         default "UART_0"
-config UART_NS16550_PORT_0_BASE_ADDR
-        default 0xB0002000
-config UART_NS16550_PORT_0_IRQ
-        default 41
 config UART_NS16550_PORT_0_IRQ_PRI
         default 1
 config UART_NS16550_PORT_0_BAUD_RATE
         default 115200
-config UART_NS16550_PORT_0_CLK_FREQ
-        default 32000000
 config UART_NS16550_PORT_0_OPTIONS
         default 0
 
@@ -136,16 +150,10 @@ if UART_NS16550_PORT_1
 
 config UART_NS16550_PORT_1_NAME
         default "UART_1"
-config UART_NS16550_PORT_1_BASE_ADDR
-        default 0xB0002400
-config UART_NS16550_PORT_1_IRQ
-        default 42
 config UART_NS16550_PORT_1_IRQ_PRI
         default 1
 config UART_NS16550_PORT_1_BAUD_RATE
         default 115200
-config UART_NS16550_PORT_1_CLK_FREQ
-        default 32000000
 config UART_NS16550_PORT_1_OPTIONS
         default 0
 
@@ -157,29 +165,57 @@ if UART_CONSOLE
 
 config UART_CONSOLE_ON_DEV_NAME
         default "UART_1"
-config UART_CONSOLE_IRQ
-        default 42
-config UART_CONSOLE_IRQ_PRI
-        default 1
 
 endif
 
-config KERNEL_INIT_PRIORITY_DEFAULT
-	default 40
+if SPI
 
-config KERNEL_INIT_PRIORITY_DEVICE
-	default 50
+config SPI_DW
+	def_bool y
 
-config IPM_CONSOLE_PRIORITY
-	default 60
+if SPI_DW
 
-config UART_CONSOLE_PRIORITY
-	default 60
+config SPI_DW_CLOCK_GATE
+	def_bool n
 
-config GPIO_DW_INIT_PRIORITY
-	default 60
+config SPI_DW_PORT_0
+	def_bool y
 
-config I2C_INIT_PRIORITY
-	default 60
+if SPI_DW_PORT_0
+
+config SPI_DW_PORT_0_PRI
+	default 1
+config SPI_DW_PORT_0_REGS
+	default 0x80010000
+config SPI_DW_PORT_0_ERROR_IRQ
+	default 30
+config SPI_DW_PORT_0_RX_IRQ
+	default 31
+config SPI_DW_PORT_0_TX_IRQ
+	default 32
+
+endif # SPI_DW_PORT_0
+
+config SPI_DW_PORT_1
+	def_bool y
+
+if SPI_DW_PORT_1
+
+config SPI_DW_PORT_1_PRI
+	default 1
+config SPI_DW_PORT_1_REGS
+	default 0x80010100
+config SPI_DW_PORT_1_ERROR_IRQ
+	default 33
+config SPI_DW_PORT_1_RX_IRQ
+	default 34
+config SPI_DW_PORT_1_TX_IRQ
+	default 35
+
+endif # SPI_DW_PORT_1
+
+endif # SPI_DW
+
+endif # SPI
 
 endif #SOC_QUARK_SE_ARC

arch/arc/soc/quark_se_ss/Kconfig.soc

@@ -1,3 +1,4 @@
 
 config SOC_QUARK_SE_SS
         bool "Intel Quark SE - Sensor Sub System"
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED

arch/arc/soc/quark_se_ss/linker.cmd

@@ -20,8 +20,8 @@
  */
 
 /* Flash base address and size */
-#define FLASH_START     0x40000000  /* Flash bank 1 */
-#define FLASH_SIZE      152K
+#define FLASH_START     CONFIG_FLASH_BASE_ADDRESS  /* Flash bank 1 */
+#define FLASH_SIZE      CONFIG_FLASH_SIZE
 
 /*
  * SRAM base address and size
@@ -29,11 +29,11 @@
  * Internal SRAM includes the exception vector table at reset, which is at
  * the beginning of the region.
  */
-#define SRAM_START		CONFIG_RAM_START
-#define SRAM_SIZE		CONFIG_RAM_SIZE
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
 
 /* Data Closely Coupled Memory (DCCM) base address and size */
-#define DCCM_START		0x80000000
-#define DCCM_SIZE		8K
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
 
 #include <arch/arc/v2/linker.cmd>

arch/arc/soc/quark_se_ss/soc.h

@@ -122,9 +122,10 @@
 #define INT_ENABLE_ARC					~(0x00000001 << 8)
 #define INT_ENABLE_ARC_BIT_POS				(8)
 
-#if defined(CONFIG_I2C)
-
-#if defined(CONFIG_I2C_QUARK_SE_SS_0)
+/*
+ * I2C
+ */
+#define I2C_QUARK_SE_SS_0_BASE_ADDR			0x80012000
 #define I2C_SS_0_ERR_VECTOR				22
 #define I2C_SS_0_ERR_MASK				0x410
 #define I2C_SS_0_RX_VECTOR				23
@@ -133,9 +134,8 @@
 #define I2C_SS_0_TX_MASK				0x418
 #define I2C_SS_0_STOP_VECTOR				25
 #define I2C_SS_0_STOP_MASK				0x41C
-#endif
 
-#if defined(CONFIG_I2C_QUARK_SE_SS_1)
+#define I2C_QUARK_SE_SS_1_BASE_ADDR			0x80012100
 #define I2C_SS_1_ERR_VECTOR				26
 #define I2C_SS_1_ERR_MASK				0x420
 #define I2C_SS_1_RX_VECTOR				27
@@ -144,19 +144,50 @@
 #define I2C_SS_1_TX_MASK				0x428
 #define I2C_SS_1_STOP_VECTOR				29
 #define I2C_SS_1_STOP_MASK				0x42C
+
+/*
+ * GPIO
+ */
+#define GPIO_DW_IO_ACCESS
+
+#define GPIO_DW_0_BASE_ADDR			0x80017800
+#define GPIO_DW_0_IRQ				20
+#define GPIO_DW_0_BITS				8
+#define GPIO_DW_PORT_0_INT_MASK			(SCSS_REGISTER_BASE + 0x408)
+
+#define GPIO_DW_1_BASE_ADDR			0x80017900
+#define GPIO_DW_1_IRQ				21
+#define GPIO_DW_1_BITS				8
+#define GPIO_DW_PORT_1_INT_MASK			(SCSS_REGISTER_BASE + 0x40C)
+
+#if defined(CONFIG_IOAPIC)
+#define GPIO_DW_0_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
+#define GPIO_DW_1_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
 #endif
 
-#endif /* CONFIG_I2C */
+/*
+ * UART
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xB0002000
+#define UART_NS16550_PORT_0_IRQ				41
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_0_INT_MASK			0x460
 
-#if defined(CONFIG_GPIO_DW)
-#define GPIO_DW_PORT_0_INT_MASK				(SCSS_REGISTER_BASE + 0x408)
-#define GPIO_DW_PORT_1_INT_MASK				(SCSS_REGISTER_BASE + 0x40C)
-#endif /* CONFIG_GPIO_DW */
+#define UART_NS16550_PORT_1_BASE_ADDR			0xB0002400
+#define UART_NS16550_PORT_1_IRQ				42
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_1_INT_MASK			0x464
 
-#if defined(CONFIG_UART_NS16550)
-#define UART_NS16550_0_INT_MASK				0x460
-#define UART_NS16550_1_INT_MASK				0x464
-#endif /* CONFIG_UART_NS16550 */
+/*
+ * SPI
+ */
+#define SPI_DW_PORT_0_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x430)
+#define SPI_DW_PORT_0_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x434)
+#define SPI_DW_PORT_0_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x438)
+
+#define SPI_DW_PORT_1_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x43C)
+#define SPI_DW_PORT_1_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x440)
+#define SPI_DW_PORT_1_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x444)
 
 #endif /* !_ASMLANGUAGE */
 

arch/arc/soc/quark_se_ss/soc_config.c

@@ -27,15 +27,16 @@ static int arc_quark_se_ipm_init(void)
 	IRQ_CONNECT(QUARK_SE_IPM_INTERRUPT, QUARK_SE_IPM_INTERRUPT_PRI,
 		    quark_se_ipm_isr, NULL, 0);
 	irq_enable(QUARK_SE_IPM_INTERRUPT);
-	return DEV_OK;
+	return 0;
 }
 
 static struct quark_se_ipm_controller_config_info ipm_controller_config = {
 	.controller_init = arc_quark_se_ipm_init
 };
-DEVICE_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
+DEVICE_AND_API_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
 				NULL, &ipm_controller_config,
-				SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+				SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+				&ipm_quark_se_api_funcs);
 
 #if CONFIG_IPM_CONSOLE_SENDER
 #include <console/ipm_console.h>
@@ -47,7 +48,7 @@ struct ipm_console_sender_config_info quark_se_ipm_sender_config = {
 };
 DEVICE_INIT(ipm_console, "ipm_console", ipm_console_sender_init,
 				NULL, &quark_se_ipm_sender_config,
-				SECONDARY, CONFIG_IPM_CONSOLE_PRIORITY);
+				SECONDARY, CONFIG_IPM_CONSOLE_INIT_PRIORITY);
 
 #endif /* CONFIG_IPM_CONSOLE_SENDER */
 #endif /* CONFIG_IPM_QUARK_SE */
@@ -59,16 +60,16 @@ static int uart_ns16550_init(struct device *dev)
 	ARG_UNUSED(dev);
 
 #ifdef CONFIG_UART_NS16550_PORT_0
-	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_0_INT_MASK),
+	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_0_INT_MASK),
 		      INT_ENABLE_ARC_BIT_POS);
 #endif /* CONFIG_UART_NS16550_PORT_0 */
 
 #ifdef CONFIG_UART_NS16550_PORT_1
-	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_1_INT_MASK),
+	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_1_INT_MASK),
 		      INT_ENABLE_ARC_BIT_POS);
 #endif /* CONFIG_UART_NS16550_PORT_1 */
 
-	return DEV_OK;
+	return 0;
 }
 
 SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arm/Kbuild

@@ -2,5 +2,10 @@ subdir-ccflags-y +=-I$(srctree)/include/drivers
 subdir-ccflags-y +=-I$(srctree)/drivers
 subdir-asflags-y := ${subdir-ccflags-y}
 
-obj-y += soc/$(SOC_NAME)/
+ifneq ($(SOC_FAMILY),)
+obj-y += soc/$(SOC_FAMILY)/
+else
+obj-y += soc/$(SOC_PATH)/
+endif
+
 obj-y += core/

arch/arm/Kconfig

@@ -16,8 +16,15 @@
 # limitations under the License.
 #
 
+choice
+	prompt "ARM SoC Selection"
+	default SOC_SERIES_KINETIS_K6X
+	depends on ARM
 
-menu "ARM architecture"
+	source "arch/arm/soc/*/Kconfig.soc"
+endchoice
+
+menu "ARM Options"
 	depends on ARM
 
 config ARCH
@@ -27,63 +34,12 @@ config ARCH_DEFCONFIG
 	string
 	default "arch/arm/defconfig"
 
-menu "General Platform Configuration"
-
-choice
-prompt "SoC Selection"
-default SOC_FSL_FRDM_K64F
-source "arch/arm/soc/*/Kconfig.soc"
-endchoice
-
-config IS_BOOTLOADER
-	bool "Act as a bootloader"
-	default n
-	depends on XIP
-	help
-	This option indicates that Zephyr will act as a bootloader to execute
-	a separate Zephyr image payload.
-
-config BOOTLOADER_SRAM_SIZE
-	int "SRAM reserved for when Zephyr acts as a bootloader"
-	default 16
-	depends on !XIP || IS_BOOTLOADER
-	help
-	This option specifies the amount of SRAM (measure in kB) reserved for
-	when Zephyr is to act as a bootloader.
-
-config ISA_THUMB2
-	bool
-	# Omit prompt to signify "hidden" option
-	default n
-	help
-	From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
-
-	Thumb-2 technology is the instruction set underlying the ARM Cortex
-	architecture which provides enhanced levels of performance, energy
-	efficiency, and code density for a wide range of embedded
-	applications.
-
-	Thumb-2 technology builds on the success of Thumb, the innovative
-	high code density instruction set for ARM microprocessor cores, to
-	increase the power of the ARM microprocessor core available to
-	developers of low cost, high performance systems.
-
-	The technology is backwards compatible with existing ARM and Thumb
-	solutions, while significantly extending the features available to
-	the Thumb instructions set. This allows more of the application to
-	benefit from the best in class code density of Thumb.
-
-	For performance optimised code Thumb-2 technology uses 31 percent
-	less memory to reduce system cost, while providing up to 38 percent
-	higher performance than existing high density code, which can be used
-	to prolong battery-life or to enrich the product feature set. Thumb-2
-	technology is featured in the  processor, and in all ARMv7
-	architecture-based processors.
 
 source "arch/arm/core/Kconfig"
 
-endmenu
+menu "Platform Configuration"
 
 source "arch/arm/soc/*/Kconfig"
 
 endmenu
+endmenu

arch/arm/Makefile

@@ -1,6 +1,6 @@
 KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
 
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/Makefile
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 
 cflags-$(CONFIG_LTO) += $(call cc-option,-flto,)
 

arch/arm/core/cortex_m/Kconfig

@@ -16,6 +16,35 @@
 # limitations under the License.
 #
 
+config ISA_THUMB2
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	help
+	From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
+
+	Thumb-2 technology is the instruction set underlying the ARM Cortex
+	architecture which provides enhanced levels of performance, energy
+	efficiency, and code density for a wide range of embedded
+	applications.
+
+	Thumb-2 technology builds on the success of Thumb, the innovative
+	high code density instruction set for ARM microprocessor cores, to
+	increase the power of the ARM microprocessor core available to
+	developers of low cost, high performance systems.
+
+	The technology is backwards compatible with existing ARM and Thumb
+	solutions, while significantly extending the features available to
+	the Thumb instructions set. This allows more of the application to
+	benefit from the best in class code density of Thumb.
+
+	For performance optimised code Thumb-2 technology uses 31 percent
+	less memory to reduce system cost, while providing up to 38 percent
+	higher performance than existing high density code, which can be used
+	to prolong battery-life or to enrich the product feature set. Thumb-2
+	technology is featured in the  processor, and in all ARMv7
+	architecture-based processors.
+
 config CPU_CORTEX_M3_M4
 	bool
 	# Omit prompt to signify "hidden" option
@@ -160,16 +189,6 @@ config SW_ISR_TABLE_DYNAMIC
 	SRAM so that it is writable. This has the side-effect of removing
 	write-protection on the ISR table.
 
-config SW_ISR_TABLE_STATIC_CUSTOM
-	bool
-	prompt "Projects provide a custom static software ISR table"
-	depends on SW_ISR_TABLE && !SW_ISR_TABLE_DYNAMIC
-	default n
-	help
-	Projects, not the platform, provide a software table of ISR and their
-	parameters. The table is static, and thus ISRs cannot be connected
-	at runtime.
-
 config IRQ_VECTOR_TABLE_CUSTOM
 	bool
 	prompt "Projects provide a custom static IRQ part of vector table"
@@ -186,10 +205,11 @@ config IRQ_VECTOR_TABLE_CUSTOM
 	the least overhead when handling an interrupt.
 
 	Downsides:
+
 	- ISRs cannot have a parameter
 	- ISRs cannot be connected at runtime
 	- ISRs must notify the kernel manually by invoking _IntExit() when
-		then are about to return.
+	  then are about to return.
 
 config IRQ_VECTOR_TABLE_SOC
 	bool

arch/arm/core/cortex_m/Makefile

@@ -1,10 +1,12 @@
 ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/arch/$(ARCH)/platforms/$(SOC_NAME)
+ccflags-y +=-I$(srctree)/arch/arm/soc/$(SOC_PATH)
 
 asflags-y = $(ccflags-y)
 
 obj-y = vector_table.o reset.o \
-	prep_c.o scs.o scb.o nmi.o \
-	sw_isr_table.o exc_manage.o exc_wrapper.o
+	nmi_on_reset.o prep_c.o scs.o scb.o nmi.o \
+	exc_manage.o exc_wrapper.o
 
 obj-$(CONFIG_ERRNO) += errno.o
+obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o
+obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o

arch/arm/core/cortex_m/irq_vector_table.c

@@ -32,11 +32,6 @@
 #include <toolchain.h>
 #include <sections.h>
 
-#if defined(CONFIG_CONSOLE_HANDLER)
-#include <soc.h>
-#include <console/uart_console.h>
-#endif /* CONFIG_CONSOLE_HANDLER */
-
 extern void _isr_wrapper(void);
 typedef void (*vth)(void); /* Vector Table Handler */
 
@@ -50,20 +45,9 @@ vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
 
 extern void _irq_spurious(void);
 
-#if defined(CONFIG_CONSOLE_HANDLER)
-static void _uart_console_isr(void)
-{
-	uart_console_isr(NULL);
-	_IntExit();
-}
-#endif /* CONFIG_CONSOLE_HANDLER */
-
 /* placeholders: fill with real ISRs */
 vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
 	[0 ...(CONFIG_NUM_IRQS - 1)] = _irq_spurious,
-#if defined(CONFIG_CONSOLE_HANDLER)
-	[CONFIG_UART_CONSOLE_IRQ] = _uart_console_isr,
-#endif
 };
 
 #endif /* CONFIG_SW_ISR_TABLE */

arch/arm/core/cpu_idle.S

@@ -33,7 +33,7 @@
 _ASM_FILE_PROLOGUE
 
 GTEXT(_CpuIdleInit)
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 GTEXT(_NanoIdleValGet)
 GTEXT(_NanoIdleValClear)
 #endif
@@ -62,7 +62,7 @@ SECTION_FUNC(TEXT, _CpuIdleInit)
     str r2, [r1]
     bx lr
 
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 
 /**
  *
@@ -101,7 +101,7 @@ SECTION_FUNC(TEXT, _NanoIdleValClear)
     str r1, [r0, #__tNANO_idle_OFFSET]
     bx lr
 
-#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
+#endif /* CONFIG_SYS_POWER_MANAGEMENT */
 
 /**
  *

arch/arm/core/fault.c

@@ -357,5 +357,4 @@ void _Fault(const NANO_ESF *esf)
 void _FaultInit(void)
 {
 	_ScbDivByZeroFaultEnable();
-	_ScbUnalignedFaultEnable();
 }

arch/arm/core/irq_manage.c

@@ -30,6 +30,7 @@
 #include <toolchain.h>
 #include <sections.h>
 #include <sw_isr_table.h>
+#include <irq.h>
 
 extern void __reserved(void);
 
@@ -44,7 +45,7 @@ extern void __reserved(void);
  *
  * @return N/A
  */
-void irq_enable(unsigned int irq)
+void _arch_irq_enable(unsigned int irq)
 {
 	/* before enabling interrupts, ensure that interrupt is cleared */
 	_NvicIrqUnpend(irq);
@@ -60,7 +61,7 @@ void irq_enable(unsigned int irq)
  *
  * @return N/A
  */
-void irq_disable(unsigned int irq)
+void _arch_irq_disable(unsigned int irq)
 {
 	_NvicIrqDisable(irq);
 }
@@ -70,20 +71,42 @@ void irq_disable(unsigned int irq)
  *
  * @brief Set an interrupt's priority
  *
- * Valid values are from 1 to 255. Interrupts of priority 1 are not masked when
- * interrupts are locked system-wide, so care must be taken when using them. ISR
- * installed with priority 1 interrupts cannot make kernel calls.
- *
- * Priority 0 is reserved for kernel usage and cannot be used.
- *
- * The priority is verified if ASSERT_ON is enabled.
+ * The priority is verified if ASSERT_ON is enabled. The maximum number
+ * of priority levels is a little complex, as there are some hardware
+ * priority levels which are reserved: three for various types of exceptions,
+ * and possibly one additional to support zero latency interrupts.
  *
  * @return N/A
  */
-void _irq_priority_set(unsigned int irq,
-					     unsigned int prio)
+void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
-	__ASSERT(prio > 0 && prio < 256, "invalid priority!");
+	/* Hardware priority levels 0 and 1 reserved for Kernel use.
+	 * So we add 2 to the requested priority level. If we support
+	 * ZLI, 2 is also reserved so we add 3.
+	 */
+
+#if CONFIG_ZERO_LATENCY_IRQS
+#define IRQ_PRIORITY_OFFSET 3
+	/* If we have zero latency interrupts, that makes priority level 2
+	 * a case with special semantics; it is not masked by irq_lock().
+	 * Our policy is to express priority levels with special properties
+	 * via flags
+	 */
+	if (flags | IRQ_ZERO_LATENCY) {
+		prio = 2;
+	} else {
+		prio += IRQ_PRIORITY_OFFSET;
+	}
+#else
+#define IRQ_PRIORITY_OFFSET 2
+	ARG_UNUSED(flags);
+	prio += IRQ_PRIORITY_OFFSET;
+#endif
+	/* Last priority level reserved for PendSV exception */
+	__ASSERT(prio < ((1 << CONFIG_NUM_IRQ_PRIO_BITS) - 1),
+		 "invalid priority %d! values must be less than %d\n",
+		 prio - IRQ_PRIORITY_OFFSET,
+		 (1 << CONFIG_NUM_IRQ_PRIO_BITS) - (IRQ_PRIORITY_OFFSET + 1));
 	_NvicIrqPrioSet(irq, _EXC_PRIO(prio));
 }
 
@@ -138,7 +161,7 @@ void _irq_handler_set(unsigned int irq,
  *
  * @return the interrupt line number
  */
-int irq_connect_dynamic(unsigned int irq,
+int _arch_irq_connect_dynamic(unsigned int irq,
 					    unsigned int prio,
 					    void (*isr)(void *arg),
 					    void *arg,
@@ -146,7 +169,7 @@ int irq_connect_dynamic(unsigned int irq,
 {
 	ARG_UNUSED(flags);
 	_irq_handler_set(irq, isr, arg);
-	_irq_priority_set(irq, prio);
+	_irq_priority_set(irq, prio, flags);
 	return irq;
 }
 

arch/arm/core/isr_wrapper.S

@@ -69,7 +69,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
 	pop {lr}
 #endif
 
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 	/*
 	 * All interrupts are disabled when handling idle wakeup.  For tickless
 	 * idle, this ensures that the calculation and programming of the device
@@ -90,7 +90,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
 		blxne	_sys_power_save_idle_exit
 
 	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
-#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
+#endif
 
 	mrs r0, IPSR	/* get exception number */
 	sub r0, r0, #16	/* get IRQ number */

arch/arm/core/offsets/offsets.c

@@ -40,9 +40,9 @@
 /* ARM-specific tNANO structure member offsets */
 
 GEN_OFFSET_SYM(tNANO, flags);
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 GEN_OFFSET_SYM(tNANO, idle);
-#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
+#endif
 
 /* ARM-specific struct tcs structure member offsets */
 

arch/arm/core/swap.S

@@ -160,7 +160,7 @@ SECTION_FUNC(TEXT, __svc)
 
     ldr r0, [r0, #24]   /* grab address of PC from stack frame */
     /* SVC is a two-byte instruction, point to it and read  encoding */
-    ldr r0, [r0, #-2]
+    ldrh r0, [r0, #-2]
 
    /*
     * grab service call number: if zero, it's a context switch;  if not,

arch/arm/core/thread.c

@@ -135,6 +135,14 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 	tcs->custom_data = NULL;
 #endif
 
+#ifdef CONFIG_THREAD_MONITOR
+	/*
+	 * In debug mode tcs->entry give direct access to the thread entry
+	 * and the corresponding parameters.
+	 */
+	tcs->entry = (struct __thread_entry *)(pInitCtx);
+#endif
+
 	tcs->preempReg.psp = (uint32_t)pInitCtx;
 	tcs->basepri = 0;
 

arch/arm/defconfig

@@ -3,7 +3,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000
 CONFIG_SOC_TI_LM3S6965=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
-CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_0"
 CONFIG_SERIAL=y
 CONFIG_CORTEX_M_SYSTICK=y
 CONFIG_FLASH_SIZE=256

arch/arm/include/nano_private.h

@@ -45,6 +45,16 @@ extern "C" {
 #endif
 
 #ifndef _ASMLANGUAGE
+
+#ifdef CONFIG_THREAD_MONITOR
+struct __thread_entry {
+	_thread_entry_t pEntry;
+	void *parameter1;
+	void *parameter2;
+	void *parameter3;
+};
+#endif /*CONFIG_THREAD_MONITOR*/
+
 struct coop {
 	/*
 	 * Unused for Cortex-M, which automatically saves the neccesary
@@ -120,6 +130,7 @@ struct tcs {
 	struct coop coopReg;
 	struct preempt preempReg;
 #if defined(CONFIG_THREAD_MONITOR)
+	struct __thread_entry *entry; /* thread entry and parameters description */
 	struct tcs *next_thread; /* next item in list of ALL fiber+tasks */
 #endif
 #ifdef CONFIG_NANO_TIMEOUTS
@@ -144,11 +155,11 @@ struct s_NANO {
 	struct tcs *current_fp; /* thread (fiber or task) that owns the FP regs */
 #endif			  /* CONFIG_FP_SHARING */
 
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 	int32_t idle; /* Number of ticks for kernel idling */
-#endif		      /* CONFIG_ADVANCED_POWER_MANAGEMENT */
+#endif
 
-#ifdef CONFIG_NANO_TIMEOUTS
+#if defined(CONFIG_NANO_TIMEOUTS) || defined(CONFIG_NANO_TIMERS)
 	sys_dlist_t timeout_q;
 	int32_t task_timeout;
 #endif

arch/arm/soc/atmel_sam3/Kbuild

@@ -1,3 +1 @@
-obj-y += soc.o nmi_on_reset.o
-
-obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o
+obj-y += soc.o

arch/arm/soc/atmel_sam3/Kconfig

@@ -19,55 +19,10 @@
 
 config SOC_ATMEL_SAM3
 	bool
+	depends on ARM
 	default n
 
-if SOC_ATMEL_SAM3
-
-config SOC
-	default atmel_sam3
-
-config NUM_IRQ_PRIO_BITS
-	int
-	default 3
-
-#
-# SAM3X8E has total 45 peripherals capable of
-# generating interrupts.
-#
-config NUM_IRQS
-	int
-	default 45
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	int
-	default 84000000
-
-#
-# SRAM address depends on the processor.
-#
-# SAM3X8E has two SRAM banks:
-#   64K @ 0x20000000
-#   32K @ 0x20080000
-# The first 64K is mirrored at 0x20070000
-# to provide one continuous 96K block.
-#
-config SRAM_SIZE
-	default 96 if SOC_ATMEL_SAM3X8E
-
-config SRAM_BASE_ADDRESS
-	default 0x20000000 if !SOC_ATMEL_SAM3X8E
-	default 0x20070000 if SOC_ATMEL_SAM3X8E
-
-#
-# Atmel SAM3 family has flash starting @ 0x00080000.
-#
-# SAM3X8E has 512K of flash.
-#
-config FLASH_SIZE
-	default 512 if SOC_ATMEL_SAM3X8E
-
-config FLASH_BASE_ADDRESS
-	default 0x00080000
+if ARM && SOC_ATMEL_SAM3
 
 config SOC_ATMEL_SAM3_EXT_SLCK
 	bool "Atmel SAM3 to use external crystal oscillator for slow clock"
@@ -125,50 +80,4 @@ config SOC_ATMEL_SAM3_PLLA_DIVA
 	With default of MULA == 6, and DIVA == 1,
 	PLL is running at 7 times of main clock.
 
-config KERNEL_INIT_PRIORITY_DEFAULT
-	default 40
-
-config KERNEL_INIT_PRIORITY_DEVICE
-	default 50
-
-config UART_CONSOLE_PRIORITY
-	default 60
-
-if UART_ATMEL_SAM3
-
-config UART_ATMEL_SAM3_BAUD_RATE
-	default 115200
-
-config UART_ATMEL_SAM3_CLK_FREQ
-	default 84000000
-
-endif # UART_ATMEL_SAM3
-
-if UART_CONSOLE
-
-config UART_CONSOLE_ON_DEV_NAME
-	default "UART_0"
-config UART_CONSOLE_IRQ
-	default 8
-config UART_CONSOLE_IRQ_PRI
-	default 3
-
-endif # UART_CONSOLE
-
-if GPIO_ATMEL_SAM3
-
-config GPIO_ATMEL_SAM3_PORTA
-	default y
-
-config GPIO_ATMEL_SAM3_PORTB
-	default y
-
-config GPIO_ATMEL_SAM3_PORTC
-	default y
-
-config GPIO_ATMEL_SAM3_PORTD
-	default y
-
-endif # GPIO_ATMEL_SAM3
-
 endif # SOC_ATMEL_SAM3

arch/arm/soc/atmel_sam3/Kconfig.defconfig

@@ -0,0 +1,110 @@
+# Kconfig - Atmel SAM3 family processor configuration options
+
+#
+# Copyright (c) 2016 Intel Corporation.
+# Copyright (c) 2014-2015 Wind River Systems, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_ATMEL_SAM3
+
+config SOC
+	default atmel_sam3
+
+config NUM_IRQ_PRIO_BITS
+	int
+	default 3
+
+#
+# SAM3X8E has total 45 peripherals capable of
+# generating interrupts.
+#
+config NUM_IRQS
+	int
+	default 45
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 84000000
+
+#
+# SRAM address depends on the processor.
+#
+# SAM3X8E has two SRAM banks:
+#   64K @ 0x20000000
+#   32K @ 0x20080000
+# The first 64K is mirrored at 0x20070000
+# to provide one continuous 96K block.
+#
+config SRAM_SIZE
+	default 96 if SOC_ATMEL_SAM3X8E
+
+config SRAM_BASE_ADDRESS
+	default 0x20000000 if !SOC_ATMEL_SAM3X8E
+	default 0x20070000 if SOC_ATMEL_SAM3X8E
+
+#
+# Atmel SAM3 family has flash starting @ 0x00080000.
+#
+# SAM3X8E has 512K of flash.
+#
+config FLASH_SIZE
+	default 512 if SOC_ATMEL_SAM3X8E
+
+config FLASH_BASE_ADDRESS
+	default 0x00080000
+
+if UART_ATMEL_SAM3
+
+config UART_ATMEL_SAM3_BAUD_RATE
+	default 115200
+
+config UART_ATMEL_SAM3_CLK_FREQ
+	default 84000000
+
+endif # UART_ATMEL_SAM3
+
+if GPIO
+
+config GPIO_ATMEL_SAM3
+	def_bool y
+
+config GPIO_ATMEL_SAM3_PORTA
+	default y
+
+config GPIO_ATMEL_SAM3_PORTB
+	default y
+
+config GPIO_ATMEL_SAM3_PORTC
+	default y
+
+config GPIO_ATMEL_SAM3_PORTD
+	default y
+
+endif # GPIO
+
+if I2C
+
+config I2C_ATMEL_SAM3
+	def_bool y
+
+config I2C_ATMEL_SAM3_0
+	default y
+
+config I2C_ATMEL_SAM3_1
+	default y
+
+endif # I2C
+
+endif # SOC_ATMEL_SAM3

arch/arm/soc/atmel_sam3/Kconfig.soc

@@ -4,3 +4,4 @@ config SOC_ATMEL_SAM3X8E
 	select CPU_CORTEX_M
 	select CPU_CORTEX_M3
 	select SOC_ATMEL_SAM3
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED

arch/arm/soc/atmel_sam3/soc.c

@@ -28,12 +28,7 @@
 #include <init.h>
 #include <soc.h>
 
-#ifdef CONFIG_RUNTIME_NMI
-extern void _NmiInit(void);
-#define NMI_INIT() _NmiInit()
-#else
-#define NMI_INIT()
-#endif
+#include <arch/cpu.h>
 
 /**
  * @brief Setup various clock on SoC.

arch/arm/soc/atmel_sam3/soc.h

@@ -183,6 +183,12 @@
 #define EEFC_BANK0_ADDR	0x400E0A00
 #define EEFC_BANK1_ADDR	0x400E0C00
 
+/* Peripheral DMA Controller (PDC) */
+#define PDC_PTCR_RXTEN	(1 << 0)
+#define PDC_PTCR_RXTDIS	(1 << 1)
+#define PDC_PTCR_TXTEN	(1 << 8)
+#define PDC_PTCR_TXTDIS	(1 << 9)
+
 /* PIO Controllers */
 #define PIOA_ADDR	0x400E0E00
 #define PIOB_ADDR	0x400E1000
@@ -199,6 +205,10 @@
 
 #define SUPC_SR_OSCSEL	(1 << 7)
 
+/* Two-wire Interface (TWI) */
+#define TWI0_ADDR	0x4008C000
+#define TWI1_ADDR	0x40090000
+
 #ifndef _ASMLANGUAGE
 
 #include <device.h>
@@ -228,6 +238,10 @@
 /* Supply Controller Register struct */
 #define __SUPC		((volatile struct __supc *)SUPC_ADDR)
 
+/* Two-wire Interface (TWI) */
+#define __TWI0		((volatile struct __twi *)TWI0_ADDR)
+#define __TWI1		((volatile struct __twi *)TWI1_ADDR)
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _ATMEL_SAM3_SOC_H_ */

arch/arm/soc/atmel_sam3/soc_registers.h

@@ -23,6 +23,26 @@
 #ifndef _ATMEL_SAM3_SOC_REGS_H_
 #define _ATMEL_SAM3_SOC_REGS_H_
 
+/* Peripheral DMA Controller
+ *
+ * DO NOT USE DIRECTLY! This is to be used within individual
+ * peripheral's register struct.
+ *
+ * Starts at offset 0x100.
+ */
+struct __pdc {
+	uint32_t	rpr;	/* 0x100 Receive Pointer       */
+	uint32_t	rcr;	/* 0x104 Receive Counter       */
+	uint32_t	tpr;	/* 0x108 Transmit Pointer      */
+	uint32_t	tcr;	/* 0x10C Transmit Counter      */
+	uint32_t	rnpr;	/* 0x110 Receive Next Pointer  */
+	uint32_t	rncr;	/* 0x114 Receive Next Counter  */
+	uint32_t	tnpr;	/* 0x118 Transmit Next Pointer */
+	uint32_t	tncr;	/* 0x11C Transmit Next Counter */
+	uint32_t	ptcr;	/* 0x120 Transfer Control      */
+	uint32_t	ptsr;	/* 0x124 Transfer Status       */
+};
+
 /* Enhanced Embedded Flash Controller */
 struct __eefc {
 	uint32_t	fmr;	/* 0x00 Flash Mode Register    */
@@ -191,5 +211,28 @@ struct __supc {
 	uint32_t	sr;	/* 0x14 Status                      */
 };
 
+/* Two-wire Interface (TWI), aka I2C */
+struct __twi {
+	uint32_t	cr;	/* 0x00 Control                     */
+	uint32_t	mmr;	/* 0x04 Master Mode                 */
+	uint32_t	smr;	/* 0x08 Slave Mode                  */
+	uint32_t	iadr;	/* 0x0C Internal Address            */
+	uint32_t	cwgr;	/* 0x10 Clock Waveform Generator    */
+
+	uint32_t	rev0[3];	/* 0x14-0x1C reserved       */
+
+	uint32_t	sr;	/* 0x20 Status                      */
+
+	uint32_t	ier;	/* 0x24 Interrupt Enable            */
+	uint32_t	idr;	/* 0x28 Interrupt Disable           */
+	uint32_t	imr;	/* 0x2C Interrupt Mask              */
+
+	uint32_t	rhr;	/* 0x30 Receive Holding             */
+	uint32_t	thr;	/* 0x34 Transmit Holding            */
+
+	uint32_t	rev1[50];	/* 0x38-0xFC Reserved       */
+
+	struct __pdc	pdc;	/* 0x100 - 0x124 PDC                */
+};
 
 #endif /* _ATMEL_SAM3_SOC_REGS_H_ */

arch/arm/soc/fsl_frdm_k64f/Kbuild

@@ -1,6 +0,0 @@
-obj-y += soc_config.o
-obj-y += soc.o
-obj-y += nmi_on_reset.o
-obj-y += wdog.o
-
-obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o

arch/arm/soc/fsl_frdm_k64f/Kconfig

@@ -1,162 +0,0 @@
-# Kconfig - FSL FRDM K64F platform configuration options
-
-#
-# Copyright (c) 2014-2015 Wind River Systems, Inc.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-
-if SOC_FSL_FRDM_K64F
-config SOC
-	default fsl_frdm_k64f
-
-config SRAM_BASE_ADDRESS
-	default 0x20000000
-
-config FLASH_BASE_ADDRESS
-	default 0x00000000
-
-config NUM_IRQ_PRIO_BITS
-	int
-	default 4
-
-config NUM_IRQS
-	int
-	# must be >= the highest interrupt number used
-	default 86
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	int
-	default 120000000
-
-config WDOG_INIT
-	def_bool y
-	# omit prompt to signify a "hidden" option
-	help
-	This processor enables the watchdog timer with a short timeout
-	upon reset. Therefore, this requires that the watchdog be configured
-	during reset handling.
-
-config KERNEL_INIT_PRIORITY_DEFAULT
-	default 40
-
-config KERNEL_INIT_PRIORITY_DEVICE
-	default 50
-
-config UART_CONSOLE_PRIORITY
-	default 60
-
-if UART_K20
-
-config UART_K20_PORT_0
-	def_bool y
-
-if UART_K20_PORT_0
-config UART_K20_PORT_0_BASE_ADDR
-	default 0x4006A000
-config UART_K20_PORT_0_IRQ
-	default 31
-config UART_K20_PORT_0_IRQ_PRI
-	default 3
-config UART_K20_PORT_0_BAUD_RATE
-	default 115200
-config UART_K20_PORT_0_CLK_FREQ
-	default 120000000
-endif
-
-config UART_K20_PORT_1
-	def_bool y
-
-if UART_K20_PORT_1
-config UART_K20_PORT_1_BASE_ADDR
-	default 0x4006B000
-config UART_K20_PORT_1_IRQ
-	default 33
-config UART_K20_PORT_1_IRQ_PRI
-	default 3
-config UART_K20_PORT_1_BAUD_RATE
-	default 115200
-config UART_K20_PORT_1_CLK_FREQ
-	default 120000000
-endif
-
-config UART_K20_PORT_2
-	def_bool y
-if UART_K20_PORT_2
-config UART_K20_PORT_2_BASE_ADDR
-	default 0x4006C000
-config UART_K20_PORT_2_IRQ
-	default 35
-config UART_K20_PORT_2_IRQ_PRI
-	default 3
-config UART_K20_PORT_2_BAUD_RATE
-	default 115200
-config UART_K20_PORT_2_CLK_FREQ
-	default 120000000
-endif
-
-config UART_K20_PORT_3
-	def_bool y
-if UART_K20_PORT_3
-config UART_K20_PORT_3_BASE_ADDR
-	default 0x4006D000
-config UART_K20_PORT_3_IRQ
-	default 37
-config UART_K20_PORT_3_IRQ_PRI
-	default 3
-config UART_K20_PORT_3_BAUD_RATE
-	default 115200
-config UART_K20_PORT_3_CLK_FREQ
-	default 120000000
-endif
-
-config UART_K20_PORT_4
-	def_bool y
-if UART_K20_PORT_4
-config UART_K20_PORT_4_BASE_ADDR
-	default 0x400EA000
-config UART_K20_PORT_4_IRQ
-	default 66
-config UART_K20_PORT_4_IRQ_PRI
-	default 3
-config UART_K20_PORT_4_BAUD_RATE
-	default 115200
-config UART_K20_PORT_4_CLK_FREQ
-	default 120000000
-endif
-
-endif # UART_K20
-
-if UART_CONSOLE
-
-config UART_CONSOLE_ON_DEV_NAME
-	default "UART_0"
-config UART_CONSOLE_IRQ
-	default 31
-config UART_CONSOLE_IRQ_PRI
-	default 3
-
-endif
-
-if BLUETOOTH_UART
-
-config BLUETOOTH_UART_ON_DEV_NAME
-	default "UART_1"
-config BLUETOOTH_UART_IRQ
-	default 33
-config BLUETOOTH_UART_IRQ_PRI
-	default 3
-
-endif
-
-endif

arch/arm/soc/fsl_frdm_k64f/Kconfig.soc

@@ -1,5 +0,0 @@
-
-config  SOC_FSL_FRDM_K64F
-	bool "Freescale FRDM-K64F"
-	select CPU_CORTEX_M
-	select CPU_CORTEX_M4

arch/arm/soc/fsl_frdm_k64f/irq_vector_table.c

@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file
- * @brief IRQ part of vector table
- *
- * This file contains the IRQ part of the vector table. It is meant to be used
- * for one of two cases:
- *
- * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
- *    binds _isr_wrapper() to all the IRQ entries in the vector table.
- *
- * b) When the platform is written so that device ISRs are installed directly in
- *    the vector table, they are enumerated here.
- */
-
-#include <toolchain.h>
-#include <sections.h>
-
-#if defined(CONFIG_CONSOLE_HANDLER)
-#include <soc.h>
-#include <console/uart_console.h>
-#endif /* CONFIG_CONSOLE_HANDLER */
-
-#if defined(CONFIG_BLUETOOTH_UART)
-#include <soc.h>
-#include <bluetooth/uart.h>
-#endif /* CONFIG_BLUETOOTH_UART */
-
-extern void _isr_wrapper(void);
-typedef void (*vth)(void); /* Vector Table Handler */
-
-#if defined(CONFIG_SW_ISR_TABLE)
-
-vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
-	[0 ...(CONFIG_NUM_IRQS - 1)] = _isr_wrapper,
-};
-
-#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
-
-extern void _irq_spurious(void);
-
-#if defined(CONFIG_CONSOLE_HANDLER)
-static void _uart_console_isr(void)
-{
-	uart_console_isr(NULL);
-	_IntExit();
-}
-#endif /* CONFIG_CONSOLE_HANDLER */
-
-#if defined(CONFIG_BLUETOOTH_UART)
-static void _bt_uart_isr(void)
-{
-	bt_uart_isr(NULL);
-	_IntExit();
-}
-#endif /* CONFIG_BLUETOOTH_UART */
-
-/* placeholders: fill with real ISRs */
-vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
-	[0 ...(CONFIG_NUM_IRQS - 1)] = _irq_spurious,
-#if defined(CONFIG_CONSOLE_HANDLER)
-	[CONFIG_UART_CONSOLE_IRQ] = _uart_console_isr,
-#endif
-#if defined(CONFIG_BLUETOOTH_UART)
-	[CONFIG_BLUETOOTH_UART_IRQ] = _bt_uart_isr,
-#endif
-};
-
-#endif /* CONFIG_SW_ISR_TABLE */

arch/arm/soc/nxp_kinetis/Kbuild

@@ -0,0 +1,2 @@
+
+obj-y += $(SOC_SERIES)/

arch/arm/soc/nxp_kinetis/Kconfig

@@ -1,7 +1,5 @@
-# Makefile - Simple network listener Makefile for nanokernel
-
 #
-# Copyright (c) 2015 Intel Corporation
+# Copyright (c) 2016 Intel Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -16,10 +14,15 @@
 # limitations under the License.
 #
 
-MDEF_FILE = prj.mdef
-KERNEL_TYPE = nano
-BOARD ?= qemu_x86
-CONF_FILE = prj_$(ARCH).conf
-SOURCE_DIR = $(ZEPHYR_BASE)/samples/net/listener/src/
+config SOC_FAMILY_KINETIS
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
 
-include $(ZEPHYR_BASE)/Makefile.inc
+if SOC_FAMILY_KINETIS
+config SOC_FAMILY
+	string
+	default "nxp_kinetis"
+endif
+
+source "arch/arm/soc/nxp_kinetis/*/Kconfig.soc"

arch/arm/soc/nxp_kinetis/Kconfig.defconfig

@@ -0,0 +1 @@
+source "arch/arm/soc/nxp_kinetis/*/Kconfig.defconfig.series"

arch/arm/soc/nxp_kinetis/Kconfig.soc

@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+source "arch/arm/soc/nxp_kinetis/*/Kconfig.series"

arch/arm/soc/nxp_kinetis/k6x/Kbuild

@@ -0,0 +1,3 @@
+obj-y += soc_config.o
+obj-y += soc.o
+obj-y += wdog.o

arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.mk64f12

@@ -0,0 +1,170 @@
+# Kconfig - FSL FRDM K64F platform configuration options
+
+#
+# Copyright (c) 2014-2016 Wind River Systems, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_MK64F12
+
+config SOC
+	string
+	default mk64f12
+
+if UART_K20
+
+config UART_K20_PORT_0
+	def_bool y
+
+if UART_K20_PORT_0
+config UART_K20_PORT_0_IRQ_PRI
+	default 3
+config UART_K20_PORT_0_BAUD_RATE
+	default 115200
+endif
+
+config UART_K20_PORT_1
+	def_bool y
+
+if UART_K20_PORT_1
+config UART_K20_PORT_1_IRQ_PRI
+	default 3
+config UART_K20_PORT_1_BAUD_RATE
+	default 115200
+endif
+
+config UART_K20_PORT_2
+	def_bool y
+if UART_K20_PORT_2
+config UART_K20_PORT_2_IRQ_PRI
+	default 3
+config UART_K20_PORT_2_BAUD_RATE
+	default 115200
+endif
+
+config UART_K20_PORT_3
+	def_bool y
+if UART_K20_PORT_3
+config UART_K20_PORT_3_IRQ_PRI
+	default 3
+config UART_K20_PORT_3_BAUD_RATE
+	default 115200
+endif
+
+config UART_K20_PORT_4
+	def_bool y
+if UART_K20_PORT_4
+config UART_K20_PORT_4_IRQ_PRI
+	default 3
+config UART_K20_PORT_4_BAUD_RATE
+	default 115200
+endif
+
+endif # UART_K20
+
+config BLUETOOTH_UART_ON_DEV_NAME
+	default "UART_1" if BLUETOOTH_UART
+
+config GPIO
+	def_bool y
+
+config PINMUX
+	def_bool y
+
+if GPIO
+
+config GPIO_K64
+	def_bool y
+
+if GPIO_K64
+
+config GPIO_K64_A
+	def_bool y
+
+config GPIO_K64_B
+	def_bool y
+
+config GPIO_K64_C
+	def_bool y
+
+config GPIO_K64_D
+	def_bool y
+
+config GPIO_K64_E
+	def_bool y
+
+endif # GPIO_K64
+
+endif # GPIO
+
+if PINMUX
+
+config PINMUX_K64
+	def_bool y
+
+if PINMUX_K64
+
+config PINMUX_K64_GPIO_A_NAME
+	default GPIO_K64_A_DEV_NAME
+config PINMUX_K64_GPIO_B_NAME
+	default GPIO_K64_B_DEV_NAME
+config PINMUX_K64_GPIO_C_NAME
+	default GPIO_K64_C_DEV_NAME
+config PINMUX_K64_GPIO_D_NAME
+	default GPIO_K64_D_DEV_NAME
+config PINMUX_K64_GPIO_E_NAME
+	default GPIO_K64_E_DEV_NAME
+
+endif # PINMUX_K64
+
+endif # PINMUX
+
+if PWM
+
+config PWM_K64_FTM
+	def_bool y
+
+if PWM_K64_FTM
+
+config PWM_K64_FTM_0
+	def_bool y
+
+endif # PWM_K64_FTM
+
+endif
+
+config SPI
+	def_bool n
+
+if SPI
+
+config SPI_K64
+	def_bool y
+
+if SPI_K64
+
+config SPI_K64_0
+	def_bool y
+
+config SPI_K64_1
+	def_bool n
+
+config SPI_K64_2
+	def_bool n
+
+endif # SPI_K64
+
+endif # SPI
+
+endif # SOC_MK64F12

arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.series

@@ -1,7 +1,7 @@
-# Makefile - dtls client that is used in testing
+# Kconfig - Kinetis K6x series configuration options
 
 #
-# Copyright (c) 2015 Intel Corporation
+# Copyright (c) 2014-2016 Wind River Systems, Inc.
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -16,12 +16,26 @@
 # limitations under the License.
 #
 
-MDEF_FILE = prj.mdef
-KERNEL_TYPE = micro
-BOARD ?= basic_minuteia
-CONF_FILE = prj_$(ARCH).conf
-SOURCE_DIR = $(ZEPHYR_BASE)/samples/net/dtls_client/src/
+if SOC_SERIES_KINETIS_K6X
 
-QEMU_EXTRA_FLAGS = -serial none -serial unix:/tmp/slip.sock
+config SOC_SERIES
+	default k6x
 
-include $(ZEPHYR_BASE)/Makefile.inc
+config SRAM_BASE_ADDRESS
+	default 0x20000000
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config NUM_IRQ_PRIO_BITS
+	int
+	default 4
+
+config NUM_IRQS
+	int
+	# must be >= the highest interrupt number used
+	default 86
+
+source "arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.mk*"
+
+endif # SOC_SERIES_KINETIS_K6X

arch/arm/soc/nxp_kinetis/k6x/Kconfig.series

@@ -0,0 +1,25 @@
+# Kconfig - Kinetis K6X MCU line
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config SOC_SERIES_KINETIS_K6X
+	bool "Kinetis K6x Series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_KINETIS
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	help
+	 Enable support for Kinetis K6x MCU series

arch/arm/soc/nxp_kinetis/k6x/Kconfig.soc

@@ -0,0 +1,79 @@
+# Kconfig - Kinetis K6X MCU line
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+choice
+prompt "Kinetis K6x MCU Selection"
+depends on SOC_SERIES_KINETIS_K6X
+
+config SOC_MK64F12
+       bool "SOC_MK64F12"
+
+endchoice
+
+if SOC_SERIES_KINETIS_K6X
+
+config K64_CORE_CLOCK_DIVIDER
+	int
+	prompt "Freescale K64 core clock divider"
+	default 1
+	help
+	This option specifies the divide value for the K64 processor core clock
+	from the system clock.
+
+config K64_BUS_CLOCK_DIVIDER
+	int
+	prompt "Freescale K64 bus clock divider"
+	default 2
+	help
+	This option specifies the divide value for the K64 bus clock from the
+	system clock.
+
+config K64_FLEXBUS_CLOCK_DIVIDER
+	int
+	prompt "Freescale K64 FlexBus clock divider"
+	default 3
+	help
+	This option specifies the divide value for the K64 FlexBus clock from the
+	system clock.
+
+config K64_FLASH_CLOCK_DIVIDER
+	int
+	prompt "Freescale K64 flash clock divider"
+	default 5
+	help
+	This option specifies the divide value for the K64 flash clock from the
+	system clock.
+
+config WDOG_INIT
+	def_bool y
+	# omit prompt to signify a "hidden" option
+	help
+	This processor enables the watchdog timer with a short timeout
+	upon reset. Therefore, this requires that the watchdog be configured
+	during reset handling.
+
+config PRESERVE_JTAG_IO_PINS
+	bool "Kinetis K6x JTAG pin usage"
+	depends on PINMUX
+	default y
+	help
+	The FRDM-K64F board routes the PTA0/1/2 pins as JTAG/SWD signals that
+	are used for the OpenSDAv2 debug interface.  These pins are also routed to
+	the Arduino header as D8, D3 and D5, respectively.
+	Enable this option to preserve these pins for the debug interface.
+
+endif # SOC_SERIES_KINETIS_K6X

arch/arm/soc/nxp_kinetis/k6x/soc.c

@@ -34,6 +34,8 @@
 #include <drivers/k6x_pmc.h>
 #include <sections.h>
 
+#include <arch/cpu.h>
+
 
 /* board's setting for PLL multipler (PRDIV0) */
 #define FRDM_K64F_PLL_DIV_20 (20 - 1)
@@ -41,13 +43,6 @@
 /* board's setting for PLL multipler (VDIV0) */
 #define FRDM_K64F_PLL_MULT_48 (48 - 24)
 
-#ifdef CONFIG_RUNTIME_NMI
-extern void _NmiInit(void);
-#define NMI_INIT() _NmiInit()
-#else
-#define NMI_INIT()
-#endif
-
 /*
  * K64F Flash configuration fields
  * These 16 bytes, which must be loaded to address 0x400, include default
@@ -301,10 +296,15 @@ static int fsl_frdm_k64f_init(struct device *arg)
 	 * FlexBus clock = 40 MHz (PLL/OUTDIV3)
 	 * Flash clock = 24 MHz (PLL/OUTDIV4)
 	 */
-	sim_p->clkdiv1.value = ((SIM_CLKDIV(1) << SIM_CLKDIV1_OUTDIV1_SHIFT) |
-				(SIM_CLKDIV(2) << SIM_CLKDIV1_OUTDIV2_SHIFT) |
-				(SIM_CLKDIV(3) << SIM_CLKDIV1_OUTDIV3_SHIFT) |
-				(SIM_CLKDIV(5) << SIM_CLKDIV1_OUTDIV4_SHIFT));
+	sim_p->clkdiv1.value = (
+		(SIM_CLKDIV(CONFIG_K64_CORE_CLOCK_DIVIDER) <<
+			SIM_CLKDIV1_OUTDIV1_SHIFT) |
+		(SIM_CLKDIV(CONFIG_K64_BUS_CLOCK_DIVIDER) <<
+			SIM_CLKDIV1_OUTDIV2_SHIFT) |
+		(SIM_CLKDIV(CONFIG_K64_FLEXBUS_CLOCK_DIVIDER) <<
+			SIM_CLKDIV1_OUTDIV3_SHIFT) |
+		(SIM_CLKDIV(CONFIG_K64_FLASH_CLOCK_DIVIDER) <<
+			SIM_CLKDIV1_OUTDIV4_SHIFT));
 
 	/* Initialize PLL/system clock to 120 MHz */
 	clkInit();

arch/arm/soc/nxp_kinetis/k6x/soc.h

@@ -149,11 +149,31 @@ extern "C" {
 /*
  * UART configuration settings
  */
+#if defined(CONFIG_UART_K20)
 
 #include <drivers/k20_pcr.h>
 
+#define UART_K20_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
+
 #define UART_IRQ_FLAGS 0
 
+#define UART_K20_PORT_0_BASE_ADDR	0x4006A000
+#define UART_K20_PORT_0_IRQ		IRQ_UART0_STATUS
+
+#define UART_K20_PORT_1_BASE_ADDR	0x4006B000
+#define UART_K20_PORT_1_IRQ		IRQ_UART1_STATUS
+
+#define UART_K20_PORT_2_BASE_ADDR	0x4006C000
+#define UART_K20_PORT_2_IRQ		IRQ_UART2_STATUS
+
+#define UART_K20_PORT_3_BASE_ADDR	0x4006D000
+#define UART_K20_PORT_3_IRQ		IRQ_UART3_STATUS
+
+#define UART_K20_PORT_4_BASE_ADDR	0x400EA000
+#define UART_K20_PORT_4_IRQ		IRQ_UART4_STATUS
+
+#endif /* CONFIG_UART_K20 */
+
 /* Uart console settings */
 #if defined(CONFIG_UART_CONSOLE)
 
@@ -165,6 +185,76 @@ extern "C" {
 
 #endif /* CONFIG_UART_CONSOLE */
 
+/*
+ * GPIO configuration settings
+ */
+#if defined(CONFIG_GPIO_K64)
+
+#define GPIO_K64_A_BASE_ADDR	0x400FF000
+#define GPIO_K64_A_IRQ		IRQ_GPIO_PORTA
+
+#define GPIO_K64_B_BASE_ADDR	0x400FF040
+#define GPIO_K64_B_IRQ		IRQ_GPIO_PORTB
+
+#define GPIO_K64_C_BASE_ADDR	0x400FF080
+#define GPIO_K64_C_IRQ		IRQ_GPIO_PORTC
+
+#define GPIO_K64_D_BASE_ADDR	0x400FF0C0
+#define GPIO_K64_D_IRQ		IRQ_GPIO_PORTD
+
+#define GPIO_K64_E_BASE_ADDR	0x400FF100
+#define GPIO_K64_E_IRQ		IRQ_GPIO_PORTE
+
+#endif /* CONFIG_GPIO_K64 */
+
+#define PORT_K64_A_BASE_ADDR	0x40049000
+#define PORT_K64_B_BASE_ADDR	0x4004A000
+#define PORT_K64_C_BASE_ADDR	0x4004B000
+#define PORT_K64_D_BASE_ADDR	0x4004C000
+#define PORT_K64_E_BASE_ADDR	0x4004D000
+
+/*
+ * PWM/FTM configuration settings
+ */
+#define PWM_K64_FTM_0_REG_BASE	0x40038000
+#define PWM_K64_FTM_1_REG_BASE	0x40039000
+#define PWM_K64_FTM_2_REG_BASE	0x4003A000
+#define PWM_K64_FTM_3_REG_BASE	0x400B9000
+
+/*
+ * SPI configuration settings
+ */
+#if defined(CONFIG_SPI_K64)
+
+#define SPI_K64_0_BASE_ADDR		0x4002C000
+#define SPI_K64_0_IRQ			IRQ_SPI0
+#define SPI_K64_0_PCS_NUM		6
+#define SPI_K64_0_CLK_GATE_REG_ADDR	0x4004803C
+#define SPI_K64_0_CLK_GATE_REG_BIT	12
+
+#define SPI_K64_1_BASE_ADDR		0x4002D000
+#define SPI_K64_1_IRQ			IRQ_SPI1
+#define SPI_K64_1_PCS_NUM		4
+#define SPI_K64_1_CLK_GATE_REG_ADDR	0x4004803C
+#define SPI_K64_1_CLK_GATE_REG_BIT	13
+
+#define SPI_K64_2_BASE_ADDR		0x400AC000
+#define SPI_K64_2_IRQ			IRQ_SPI2
+#define SPI_K64_2_PCS_NUM		2
+#define SPI_K64_2_CLK_GATE_REG_ADDR	0x40048030
+#define SPI_K64_2_CLK_GATE_REG_BIT	12
+
+#endif /* CONFIG_SPI_K64 */
+
+/*
+ * PINMUX configuration settings
+ */
+#if defined(CONFIG_PINMUX)
+
+#define PINMUX_NUM_PINS			160
+
+#endif /* CONFIG_PINMUX */
+
 #endif /* !_ASMLANGUAGE */
 
 #ifdef __cplusplus

arch/arm/soc/nxp_kinetis/k6x/soc_config.c

@@ -30,9 +30,14 @@
 #include <drivers/k20_pcr.h>
 #include <drivers/k20_sim.h>
 #include <console/uart_console.h>
-
 #include <serial/uart_k20_priv.h>
+#endif /* CONFIG_UART_K20 */
 
+/*
+ * UART configuration
+ */
+
+#ifdef CONFIG_UART_K20
 
 #if defined(CONFIG_UART_CONSOLE)
 #if defined(CONFIG_PRINTK) || defined(CONFIG_STDOUT_CONSOLE)
@@ -44,7 +49,7 @@
  *
  * @param dev The UART device struct
  *
- * @return DEV_OK if successful, otherwise failed.
+ * @return 0 if successful, otherwise failed.
  */
 static int uart_k20_console_init(struct device *dev)
 {
@@ -68,7 +73,7 @@ static int uart_k20_console_init(struct device *dev)
 	port_pcr_p->port[port].pcr[rxPin] = pcr;
 	port_pcr_p->port[port].pcr[txPin] = pcr;
 
-	return DEV_OK;
+	return 0;
 }
 
 SYS_INIT(uart_k20_console_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
@@ -112,7 +117,7 @@ static int uart_k20_init(struct device *dev)
 	sim->scgc1.field.uart4_clk_en = 1;
 #endif
 
-	return DEV_OK;
+	return 0;
 }
 
 DEVICE_INIT(_uart_k20_init, "", uart_k20_init,

arch/arm/soc/st_stm32/Kbuild

@@ -0,0 +1,2 @@
+
+obj-y += $(SOC_SERIES)/

arch/arm/soc/st_stm32/Kconfig

@@ -1,7 +1,6 @@
-# Makefile - Network echo server microkernel
-
+# Kconfig - ST Microelectronics STM32 MCU line
 #
-# Copyright (c) 2015 Intel Corporation
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -16,11 +15,15 @@
 # limitations under the License.
 #
 
-MDEF_FILE = prj.mdef
-KERNEL_TYPE = nano
-BOARD ?= qemu_x86
-CONF_FILE = prj_$(ARCH).conf
-SOURCE_DIR = $(ZEPHYR_BASE)/samples/net/echo_server/src/
-QEMU_EXTRA_FLAGS = -serial unix:/tmp/slip.sock
+config SOC_FAMILY_STM32
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
 
-include $(ZEPHYR_BASE)/Makefile.inc
+if SOC_FAMILY_STM32
+config SOC_FAMILY
+	string
+	default st_stm32
+endif
+
+source "arch/arm/soc/st_stm32/*/Kconfig.soc"

arch/arm/soc/st_stm32/Kconfig.defconfig

@@ -0,0 +1 @@
+source "arch/arm/soc/st_stm32/*/Kconfig.defconfig.series"

arch/arm/soc/st_stm32/Kconfig.soc

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics STM32 MCU line
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+source "arch/arm/soc/st_stm32/*/Kconfig.series"

arch/arm/soc/st_stm32/stm32f1/Kbuild

@@ -0,0 +1,4 @@
+obj-y += soc.o
+
+obj-$(CONFIG_GPIO) += soc_gpio.o
+obj-$(CONFIG_PINMUX) += soc_config.o

arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.series

@@ -1,7 +1,6 @@
-# Makefile - coap observe client test application
-
+# Kconfig - ST Microelectronics STM32F1 MCU line
 #
-# Copyright (c) 2015 Intel Corporation
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -16,12 +15,21 @@
 # limitations under the License.
 #
 
-MDEF_FILE = prj.mdef
-KERNEL_TYPE = micro
-BOARD ?= basic_minuteia
-CONF_FILE = prj_$(ARCH).conf
-SOURCE_DIR = $(ZEPHYR_BASE)/samples/net/coap_observe_client/src/
+if SOC_SERIES_STM32F1X
 
-QEMU_EXTRA_FLAGS = -serial none -serial unix:/tmp/slip.sock
+source "arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f1*"
 
-include $(ZEPHYR_BASE)/Makefile.inc
+config SOC_SERIES
+       default stm32f1
+
+config SRAM_BASE_ADDRESS
+        default 0x20000000
+
+config FLASH_BASE_ADDRESS
+        default 0x08000000
+
+config NUM_IRQ_PRIO_BITS
+        int
+        default 4
+
+endif # SOC_SERIES_STM32F1X

arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103rb

@@ -0,0 +1,34 @@
+# Kconfig - ST Microelectronics STM32F103RB MCU
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_STM32F103RB
+
+config SOC
+	string
+	default stm32f103rb
+config SRAM_SIZE
+       default 20
+
+config FLASH_SIZE
+       default 128
+
+config NUM_IRQS
+        int
+        default 59
+
+endif # SOC_STM32F103RB
+

arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103ve

@@ -0,0 +1,35 @@
+# Kconfig - ST Microelectronics STM32F103VE MCU
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_STM32F103VE
+
+config SOC
+	string
+	default stm32f103ve
+
+config SRAM_SIZE
+       default 64
+
+config FLASH_SIZE
+       default 512
+
+config NUM_IRQS
+        int
+        default 68
+
+endif # SOC_STM32F103VE
+

arch/arm/soc/st_stm32/stm32f1/Kconfig.series

@@ -0,0 +1,25 @@
+# Kconfig - ST Microelectronics STM32F1 MCU series
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config SOC_SERIES_STM32F1X
+	bool "STM32F1x Series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M3
+	select SOC_FAMILY_STM32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	help
+	 Enable support for STM32F1 MCU series

arch/arm/soc/st_stm32/stm32f1/Kconfig.soc

@@ -1,7 +1,6 @@
-# Makefile - Simple network listener Makefile for nanokernel
-
+# Kconfig - ST Microelectronics STM32F1 MCU line
 #
-# Copyright (c) 2015 Intel Corporation
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -16,11 +15,14 @@
 # limitations under the License.
 #
 
-MDEF_FILE = prj.mdef
-KERNEL_TYPE = nano
-BOARD ?= qemu_x86
-CONF_FILE = prj_$(ARCH).conf
+choice
+prompt "STM32F1x MCU Selection"
+depends on SOC_SERIES_STM32F1X
 
-QEMU_EXTRA_FLAGS = -serial none -serial unix:/tmp/slip.sock
+config SOC_STM32F103VE
+       bool "STM32F103VE"
 
-include $(ZEPHYR_BASE)/Makefile.inc
+config SOC_STM32F103RB
+       bool "STM32F103RB"
+
+endchoice

arch/arm/soc/st_stm32/stm32f1/Makefile

@@ -0,0 +1,7 @@
+
+arch-cflags += $(call cc-option,-mthumb -mcpu=cortex-m3) \
+		$(call cc-option,-mthumb -march=armv7-m)
+
+KBUILD_AFLAGS += $(arch-cflags)
+KBUILD_CXXFLAGS += $(arch-cflags)
+KBUILD_CFLAGS += $(arch-cflags)

arch/arm/soc/st_stm32/stm32f1/flash_registers.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _STM32F10X_FLASH_REGISTERS_H_
+#define _STM32F10X_FLASH_REGISTERS_H_
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
+ *   advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 3.3.3: Embedded Flash Memory
+ */
+
+enum {
+	STM32F10X_FLASH_LATENCY_0 = 0x0,
+	STM32F10X_FLASH_LATENCY_1 = 0x1,
+	STM32F10X_FLASH_LATENCY_2 = 0x2,
+};
+
+/* 3.3.3 FLASH_ACR */
+union __ef_acr {
+	uint32_t val;
+	struct {
+		uint32_t latency :3 __packed;
+		uint32_t hlfcya :1 __packed;
+		uint32_t prftbe :1 __packed;
+		uint32_t prftbs :1 __packed;
+		uint32_t rsvd__6_31 :26 __packed;
+	} bit;
+};
+
+/* 3.3.3 Embedded flash registers */
+struct stm32f10x_flash {
+	union __ef_acr acr;
+	uint32_t keyr;
+	uint32_t optkeyr;
+	uint32_t sr;
+	uint32_t cr;
+	uint32_t ar;
+	uint32_t rsvd;
+	uint32_t obr;
+	uint32_t wrpr;
+};
+
+#endif	/* _STM32F10X_FLASHREGISTERS_H_ */

arch/arm/soc/st_stm32/stm32f1/gpio_registers.h

@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _STM32F10X_GPIO_REGISTERS_H_
+#define _STM32F10X_GPIO_REGISTERS_H_
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
+ *   advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 9: General-purpose and alternate-function I/Os
+ *            (GPIOs and AFIOs)
+ */
+
+/* 9.2 GPIO registers - each GPIO port controls 16 pins */
+struct stm32f10x_gpio {
+	uint32_t crl;
+	uint32_t crh;
+	uint32_t idr;
+	uint32_t odr;
+	uint32_t bsrr;
+	uint32_t brr;
+	uint32_t lckr;
+};
+
+/* 9.4.1 AFIO_EVCR */
+union __afio_evcr {
+	uint32_t val;
+	struct {
+		uint32_t pin :4 __packed;
+		uint32_t port :3 __packed;
+		uint32_t evoe :1 __packed;
+		uint32_t rsvd__8_31 :24 __packed;
+	} bit;
+};
+
+/* 9.4.2 AFIO_MAPR */
+/* TODO: support connectivity line devices */
+union __afio_mapr {
+	uint32_t val;
+	struct {
+		uint32_t spi1_remap :1 __packed;
+		uint32_t i2c1_remap :1 __packed;
+		uint32_t usart1_remap :1 __packed;
+		uint32_t usart2_remap :1 __packed;
+		uint32_t usart3_remap :2 __packed;
+		uint32_t tim1_remap :2 __packed;
+		uint32_t tim2_remap :2 __packed;
+		uint32_t tim3_remap :2 __packed;
+		uint32_t tim4_remap :1 __packed;
+		uint32_t can_remap :2 __packed;
+		uint32_t pd01_remap :1 __packed;
+		uint32_t tim5ch4_iremap :1 __packed;
+		uint32_t adc1_etrginj_remap :1 __packed;
+		uint32_t adc1_etrgreg_remap :1 __packed;
+		uint32_t adc2_etrginj_remap :1 __packed;
+		uint32_t adc2_etrgreg_remap :1 __packed;
+		uint32_t rsvd__21_23 :3 __packed;
+		uint32_t swj_cfg :3 __packed;
+		uint32_t rsvd__27_31 :5 __packed;
+	} bit;
+};
+
+/* 9.4.{3,4,5,6} AFIO_EXTICRx */
+union __afio_exticr {
+	uint32_t val;
+	struct {
+		uint16_t rsvd__16_31;
+		uint16_t exti;
+	} bit;
+};
+
+/* 9.4.7 AFIO_MAPR2 */
+union __afio_mapr2 {
+	uint32_t val;
+	struct {
+		uint32_t rsvd__0_4 :5 __packed;
+		uint32_t tim9_remap :1 __packed;
+		uint32_t tim10_remap :1 __packed;
+		uint32_t tim11_remap :1 __packed;
+		uint32_t tim13_remap :1 __packed;
+		uint32_t tim14_remap :1 __packed;
+		uint32_t fsmc_nadv :1 __packed;
+		uint32_t rsvd__11_31 :21 __packed;
+	} bit;
+};
+
+/* 9.4 AFIO registers */
+struct stm32f10x_afio {
+	union __afio_evcr evcr;
+	union __afio_mapr mapr;
+	union __afio_exticr exticr1;
+	union __afio_exticr exticr2;
+	union __afio_exticr exticr3;
+	union __afio_exticr exticr4;
+	union __afio_mapr2 mapr2;
+};
+
+#endif /* _STM32F10X_GPIO_REGISTERS_H_ */

arch/arm/soc/st_stm32/stm32f1/linker.cmd

@@ -0,0 +1,19 @@
+/* linker.cmd - Linker command/script file */
+
+/*
+ * Copyright (c) 2014-2016 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.cmd>

arch/arm/soc/st_stm32/stm32f1/rcc_registers.h

@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _STM32F10X_CLOCK_H_
+#define _STM32F10X_CLOCK_H_
+
+/**
+ * @brief Driver for Reset & Clock Control of STM32F10x family processor.
+ *
+ * Based on reference manual:
+ *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
+ *   advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 7: Low-, medium-, high- and XL-density reset and
+ *            clock control
+ */
+
+/* 8.3.1 Clock control register (RCC_CR) */
+enum {
+	STM32F10X_RCC_CFG_PLL_SRC_HSI	  = 0x0,
+	STM32F10X_RCC_CFG_PLL_SRC_HSE     = 0x1,
+};
+
+enum {
+	STM32F10X_RCC_CFG_PLL_XTPRE_DIV_0  = 0x0,
+	STM32F10X_RCC_CFG_PLL_XTPRE_DIV_2  = 0x1,
+};
+
+enum {
+	STM32F10X_RCC_CFG_SYSCLK_SRC_HSI = 0x0,
+	STM32F10X_RCC_CFG_SYSCLK_SRC_HSE = 0x1,
+	STM32F10X_RCC_CFG_SYSCLK_SRC_PLL = 0x2,
+};
+
+enum {
+	STM32F10X_RCC_CFG_HCLK_DIV_0  = 0x0,
+	STM32F10X_RCC_CFG_HCLK_DIV_2  = 0x4,
+	STM32F10X_RCC_CFG_HCLK_DIV_4  = 0x5,
+	STM32F10X_RCC_CFG_HCLK_DIV_8  = 0x6,
+	STM32F10X_RCC_CFG_HCLK_DIV_16 = 0x7,
+};
+
+enum {
+	STM32F10X_RCC_CFG_SYSCLK_DIV_0	 = 0x0,
+	STM32F10X_RCC_CFG_SYSCLK_DIV_2	 = 0x8,
+	STM32F10X_RCC_CFG_SYSCLK_DIV_4	 = 0x9,
+	STM32F10X_RCC_CFG_SYSCLK_DIV_8	 = 0xa,
+	STM32F10X_RCC_CFG_SYSCLK_DIV_16	 = 0xb,
+	STM32F10X_RCC_CFG_SYSCLK_DIV_64	 = 0xc,
+	STM32F10X_RCC_CFG_SYSCLK_DIV_128 = 0xd,
+	STM32F10X_RCC_CFG_SYSCLK_DIV_256 = 0xe,
+	STM32F10X_RCC_CFG_SYSCLK_DIV_512 = 0xf,
+};
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+union __rcc_cr {
+	uint32_t val;
+	struct {
+		uint32_t hsion :1 __packed;
+		uint32_t hsirdy :1 __packed;
+		uint32_t rsvd__2 :1 __packed;
+		uint32_t hsitrim :5 __packed;
+		uint32_t hsical :8 __packed;
+		uint32_t hseon :1 __packed;
+		uint32_t hserdy :1 __packed;
+		uint32_t hsebyp :1 __packed;
+		uint32_t csson :1 __packed;
+		uint32_t rsvd__20_23 :4 __packed;
+		uint32_t pllon :1 __packed;
+		uint32_t pllrdy :1 __packed;
+		uint32_t rsvd__26_31 :6 __packed;
+	} bit;
+};
+
+union __rcc_cfgr {
+	uint32_t val;
+	struct {
+		uint32_t sw :2 __packed;
+		uint32_t sws :2 __packed;
+		uint32_t hpre :4 __packed;
+		uint32_t ppre1 :3 __packed;
+		uint32_t ppre2 :3 __packed;
+		uint32_t adcpre :2 __packed;
+		uint32_t pllsrc :1 __packed;
+		uint32_t pllxtpre :1 __packed;
+		uint32_t pllmul :4 __packed;
+		uint32_t usbpre :1 __packed;
+		uint32_t rsvd__23 :1 __packed;
+		uint32_t mco :3 __packed;
+		uint32_t rsvd__27_31 :5 __packed;
+	} bit;
+};
+
+struct stm32f10x_rcc {
+	union __rcc_cr cr;
+	union __rcc_cfgr cfgr;
+	uint32_t cir;
+	uint32_t apb2rstr;
+	uint32_t apb1rstr;
+	uint32_t ahbenr;
+	uint32_t apb2enr;
+	uint32_t apb1enr;
+	uint32_t bdcr;
+	uint32_t csr;
+};
+
+#endif /* _STM32F10X_CLOCK_H_ */

arch/arm/soc/st_stm32/stm32f1/soc.c

@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32F1 processor
+ */
+
+#include <nanokernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+#include <arch/cpu.h>
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int stm32f1_init(struct device *arg)
+{
+	uint32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	/* Setup the vector table offset register (VTOR),
+	 * which is located at the beginning of flash area.
+	 */
+	_scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS);
+
+	/* Clear all faults */
+	_ScbMemFaultAllFaultsReset();
+	_ScbBusFaultAllFaultsReset();
+	_ScbUsageFaultAllFaultsReset();
+
+	_ScbHardFaultAllFaultsReset();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+SYS_INIT(stm32f1_init, PRIMARY, 0);

arch/arm/soc/st_stm32/stm32f1/soc.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file SoC configuration macros for the STM32F103 family processors.
+ *
+ * Based on reference manual:
+ *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
+ *   advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 3.3: Memory Map
+ */
+
+
+#ifndef _STM32F1_SOC_H_
+#define _STM32F1_SOC_H_
+
+/* peripherals start address */
+#define PERIPH_BASE           0x40000000
+
+/* use naming consistent with STMF10x Peripherals Library */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+
+/* UART */
+#define USART1_ADDR           (APB2PERIPH_BASE + 0x3800)
+#define USART2_ADDR           (APB1PERIPH_BASE + 0x4400)
+#define USART3_ADDR           (APB1PERIPH_BASE + 0x4800)
+
+/* Reset and Clock Control */
+#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
+
+#define GPIO_REG_SIZE         0x400
+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
+/* base address for where GPIO registers start */
+#define GPIO_PORTS_BASE       (GPIOA_BASE)
+
+/* EXTI */
+#define EXTI_BASE            (APB2PERIPH_BASE + 0x0400)
+
+/* AFIO */
+#define AFIO_BASE            (APB2PERIPH_BASE + 0x0000)
+
+/* IWDG */
+#define IWDG_BASE            (APB1PERIPH_BASE + 0x3000)
+
+/* FLASH */
+#define FLASH_BASE           (AHBPERIPH_BASE + 0x2000)
+
+#ifndef _ASMLANGUAGE
+
+#include <device.h>
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+/* IO pin functions */
+enum stm32f10x_pin_config_mode {
+	STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
+	STM32F10X_PIN_CONFIG_BIAS_PULL_UP,
+	STM32F10X_PIN_CONFIG_BIAS_PULL_DOWN,
+	STM32F10X_PIN_CONFIG_ANALOG,
+	STM32F10X_PIN_CONFIG_DRIVE_OPEN_DRAIN,
+	STM32F10X_PIN_CONFIG_DRIVE_PUSH_PULL,
+	STM32F10X_PIN_CONFIG_AF_PUSH_PULL,
+	STM32F10X_PIN_CONFIG_AF_OPEN_DRAIN,
+};
+
+#include "soc_irq.h"
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32F1_SOC_H_ */

arch/arm/soc/st_stm32/stm32f1/soc_config.c

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <errno.h>
+
+#include "soc.h"
+#include <device.h>
+#include <misc/util.h>
+#include <pinmux/stm32/pinmux_stm32.h>
+#include <drivers/clock_control/stm32_clock_control.h>
+
+static const stm32_pin_func_t pin_pa9_funcs[] = {
+	[STM32F1_PINMUX_FUNC_PA9_USART1_TX - 1] = STM32F10X_PIN_CONFIG_AF_PUSH_PULL,
+};
+
+static const stm32_pin_func_t pin_pa10_funcs[] = {
+	[STM32F1_PINMUX_FUNC_PA9_USART1_TX - 1] = STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
+};
+
+static const stm32_pin_func_t pin_pa2_funcs[] = {
+	[STM32F1_PINMUX_FUNC_PA2_USART2_TX - 1] = STM32F10X_PIN_CONFIG_AF_PUSH_PULL,
+};
+
+static const stm32_pin_func_t pin_pa3_funcs[] = {
+	[STM32F1_PINMUX_FUNC_PA3_USART2_RX - 1] = STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
+};
+
+static const stm32_pin_func_t pin_pb10_funcs[] = {
+	[STM32F1_PINMUX_FUNC_PB10_USART3_TX - 1] = STM32F10X_PIN_CONFIG_AF_PUSH_PULL,
+};
+
+static const stm32_pin_func_t pin_pb11_funcs[] = {
+	[STM32F1_PINMUX_FUNC_PB11_USART3_RX - 1] = STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
+};
+
+/**
+ * @brief pin configuration
+ */
+static struct stm32_pinmux_conf pins[] = {
+	STM32_PIN_CONF(STM32_PIN_PA2, pin_pa2_funcs),
+	STM32_PIN_CONF(STM32_PIN_PA3, pin_pa3_funcs),
+	STM32_PIN_CONF(STM32_PIN_PA9, pin_pa9_funcs),
+	STM32_PIN_CONF(STM32_PIN_PA10, pin_pa10_funcs),
+	STM32_PIN_CONF(STM32_PIN_PB10, pin_pb10_funcs),
+	STM32_PIN_CONF(STM32_PIN_PB11, pin_pb11_funcs),
+};
+
+int stm32_get_pin_config(int pin, int func)
+{
+	/* GPIO function is always available, to save space it is not
+	 * listed in alternate functions array
+	 */
+	if (func == STM32_PINMUX_FUNC_GPIO) {
+		return STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE;
+	}
+
+	/* analog function is another 'known' setting */
+	if (func == STM32_PINMUX_FUNC_ANALOG) {
+		return STM32F10X_PIN_CONFIG_ANALOG;
+	}
+
+	func -= 1;
+
+	for (int i = 0; i < ARRAY_SIZE(pins); i++) {
+		if (pins[i].pin == pin) {
+			if (func > pins[i].nfuncs) {
+				return -EINVAL;
+			}
+
+			return pins[i].funcs[func];
+		}
+	}
+	return -EINVAL;
+}
+
+clock_control_subsys_t stm32_get_port_clock(int port)
+{
+	const clock_control_subsys_t ports_to_clock[STM32_PORTS_MAX] = {
+		UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_IOPA),
+		UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_IOPB),
+		UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_IOPC),
+		UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_IOPD),
+		UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_IOPE),
+	};
+
+	if (port > STM32_PORTE) {
+		return NULL;
+	}
+
+	return ports_to_clock[port];
+}

arch/arm/soc/st_stm32/stm32f1/soc_gpio.c

@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
+ *   advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 9: General-purpose and alternate-function I/Os
+ *            (GPIOs and AFIOs)
+ */
+
+#include <errno.h>
+
+#include <device.h>
+#include "soc.h"
+#include "soc_registers.h"
+#include <gpio.h>
+#include <gpio/gpio_stm32.h>
+
+/**
+ * @brief map pin function to MODE register value
+ */
+static uint32_t __func_to_mode(int func)
+{
+	switch (func) {
+	case STM32F10X_PIN_CONFIG_ANALOG:
+	case STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+	case STM32F10X_PIN_CONFIG_BIAS_PULL_UP:
+	case STM32F10X_PIN_CONFIG_BIAS_PULL_DOWN:
+		return 0;
+	case STM32F10X_PIN_CONFIG_DRIVE_OPEN_DRAIN:
+	case STM32F10X_PIN_CONFIG_DRIVE_PUSH_PULL:
+	case STM32F10X_PIN_CONFIG_AF_PUSH_PULL:
+	case STM32F10X_PIN_CONFIG_AF_OPEN_DRAIN:
+		return 0x1;
+	}
+	return 0;
+}
+
+/**
+ * @brief map pin function to CNF register value
+ */
+static uint32_t __func_to_cnf(int func)
+{
+	switch (func) {
+	case STM32F10X_PIN_CONFIG_ANALOG:
+		return 0x0;
+	case STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+		return 0x1;
+	case STM32F10X_PIN_CONFIG_BIAS_PULL_UP:
+	case STM32F10X_PIN_CONFIG_BIAS_PULL_DOWN:
+		return 0x2;
+	case STM32F10X_PIN_CONFIG_DRIVE_PUSH_PULL:
+		return 0x0;
+	case STM32F10X_PIN_CONFIG_DRIVE_OPEN_DRAIN:
+		return 0x1;
+	case STM32F10X_PIN_CONFIG_AF_PUSH_PULL:
+		return 0x2;
+	case STM32F10X_PIN_CONFIG_AF_OPEN_DRAIN:
+		return 0x3;
+	}
+	return 0;
+}
+
+int stm32_gpio_flags_to_conf(int flags, int *pincfg)
+{
+	int direction = flags & GPIO_DIR_MASK;
+
+	if (!pincfg) {
+		return -EINVAL;
+	}
+
+	if (direction == GPIO_DIR_OUT) {
+		*pincfg = STM32F10X_PIN_CONFIG_DRIVE_PUSH_PULL;
+	} else if (direction == GPIO_DIR_IN) {
+		int pud = flags & GPIO_PUD_MASK;
+
+		/* pull-{up,down} maybe? */
+		if (pud == GPIO_PUD_PULL_UP) {
+			*pincfg = STM32F10X_PIN_CONFIG_BIAS_PULL_UP;
+		} else if (pud == GPIO_PUD_PULL_DOWN) {
+			*pincfg = STM32F10X_PIN_CONFIG_BIAS_PULL_DOWN;
+		} else {
+			/* floating */
+			*pincfg = STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE;
+		}
+	} else {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+int stm32_gpio_configure(uint32_t *base_addr, int pin, int conf)
+{
+	volatile struct stm32f10x_gpio *gpio =
+		(struct stm32f10x_gpio *)(base_addr);
+	int cnf, mode;
+	int crpin = pin;
+
+	/* pins are configured in CRL (0-7) and CRH (8-15)
+	 * registers
+	 */
+	volatile uint32_t *reg = &gpio->crl;
+
+	if (crpin > 7) {
+		reg = &gpio->crh;
+		crpin -= 8;
+	}
+
+	/* each port is configured by 2 registers:
+	 * CNFy[1:0]: Port x configuration bits
+	 * MODEy[1:0]: Port x mode bits
+	 *
+	 * memory layout is repeated for every port:
+	 *   |  CNF  |  MODE |
+	 *   | [0:1] | [0:1] |
+	 */
+	cnf = __func_to_cnf(conf);
+	mode = __func_to_mode(conf);
+
+	/* clear bits */
+	*reg &= ~(0xf << (crpin * 4));
+	/* set bits */
+	*reg |= (cnf << (crpin * 4 + 2) | mode << (crpin * 4));
+
+	/* input mode - 0x1 */
+	if (conf == STM32F10X_PIN_CONFIG_BIAS_PULL_UP) {
+		/* enable pull up */
+		gpio->odr |= 1 << pin;
+	} else if (conf == STM32F10X_PIN_CONFIG_BIAS_PULL_DOWN) {
+		/* or pull down */
+		gpio->odr &= ~(1 << pin);
+	}
+
+	return 0;
+}
+
+int stm32_gpio_set(uint32_t *base, int pin, int value)
+{
+	struct stm32f10x_gpio *gpio = (struct stm32f10x_gpio *)base;
+
+	int pval = 1 << (pin & 0xf);
+
+	if (value) {
+		gpio->odr |= pval;
+	} else {
+		gpio->odr &= ~pval;
+	}
+
+	return 0;
+}
+
+int stm32_gpio_get(uint32_t *base, int pin)
+{
+	struct stm32f10x_gpio *gpio = (struct stm32f10x_gpio *)base;
+
+	return (gpio->idr >> pin) & 0x1;
+}
+
+int stm32_gpio_enable_int(int port, int pin)
+{
+	volatile struct stm32f10x_afio *afio =
+		(struct stm32f10x_afio *)AFIO_BASE;
+	volatile union __afio_exticr *exticr;
+	int shift = 0;
+
+	if (pin <= 3) {
+		exticr = &afio->exticr1;
+	} else if (pin <= 7) {
+		exticr = &afio->exticr2;
+	} else if (pin <= 11) {
+		exticr = &afio->exticr3;
+	} else if (pin <= 15) {
+		exticr = &afio->exticr4;
+	} else {
+		return -EINVAL;
+	}
+
+	shift = 4 * (pin % 4);
+
+	exticr->val &= ~(0xf << shift);
+	exticr->val |= port << shift;
+
+	return 0;
+}

arch/arm/soc/st_stm32/stm32f1/soc_irq.h

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Interrupt numbers for STM32F1 family processors.
+ *
+ * Based on reference manual:
+ *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
+ *   advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 10.1.2: Interrupt and exception vectors
+ */
+
+
+#ifndef _STM32F1_SOC_IRQ_H_
+#define _STM32F1_SOC_IRQ_H_
+
+#define STM32F1_IRQ_WWDG		0
+#define STM32F1_IRQ_PVD		1
+#define STM32F1_IRQ_TAMPER		2
+#define STM32F1_IRQ_RTC		3
+#define STM32F1_IRQ_FLAGS		4
+#define STM32F1_IRQ_RCC		5
+#define STM32F1_IRQ_EXTI0		6
+#define STM32F1_IRQ_EXTI1		7
+#define STM32F1_IRQ_EXTI2		8
+#define STM32F1_IRQ_EXTI3		9
+#define STM32F1_IRQ_EXTI4		10
+#define STM32F1_IRQ_DMA1_CH1		11
+#define STM32F1_IRQ_DMA1_CH2		12
+#define STM32F1_IRQ_DMA1_CH3		13
+#define STM32F1_IRQ_DMA1_CH4		14
+#define STM32F1_IRQ_DMA1_CH5		15
+#define STM32F1_IRQ_DMA1_CH6		16
+#define STM32F1_IRQ_DMA1_CH7		17
+#define STM32F1_IRQ_ADC1_2		18
+#define STM32F1_IRQ_USB_HP_CAN_TX	19
+#define STM32F1_IRQ_USB_LP_CAN_RX0	20
+#define STM32F1_IRQ_CAN_RX1		21
+#define STM32F1_IRQ_CAN_SCE		22
+#define STM32F1_IRQ_EXTI9_5		23
+#define STM32F1_IRQ_TIM1_BRK		24
+#define STM32F1_IRQ_TIM1_UP		25
+#define STM32F1_IRQ_TIM1_TRG_COM	26
+#define STM32F1_IRQ_TIM1_CC		27
+#define STM32F1_IRQ_TIM2		28
+#define STM32F1_IRQ_TIM3		29
+#define STM32F1_IRQ_TIM4		30
+#define STM32F1_IRQ_I2C1_EV		31
+#define STM32F1_IRQ_I2C1_ER		32
+#define STM32F1_IRQ_I2C2_EV		33
+#define STM32F1_IRQ_I2C2_ER		34
+#define STM32F1_IRQ_SPI1		35
+#define STM32F1_IRQ_SPI2		36
+#define STM32F1_IRQ_USART1		37
+#define STM32F1_IRQ_USART2		38
+#define STM32F1_IRQ_USART3		39
+#define STM32F1_IRQ_EXTI15_10		40
+#define STM32F1_IRQ_RTC_ALARM		41
+#define STM32F1_IRQ_USB_WAKEUP		42
+#define STM32F1_IRQ_OTG_FS_WKUP	STM32F1_IRQ_USB_WAKEUP
+#define STM32F1_IRQ_TIM8_BRK		43
+#define STM32F1_IRQ_TIM8_UP		44
+#define STM32F1_IRQ_TIM8_TRG_COM	45
+#define STM32F1_IRQ_TIM8_CC		46
+#define STM32F1_IRQ_ADC3		47
+#define STM32F1_IRQ_FSMC		48
+#define STM32F1_IRQ_SDIO		49
+#define STM32F1_IRQ_TIM5		50
+#define STM32F1_IRQ_SPI3		51
+#define STM32F1_IRQ_UART4		52
+#define STM32F1_IRQ_UART5		53
+#define STM32F1_IRQ_TIM6		54
+#define STM32F1_IRQ_TIM7		55
+#define STM32F1_IRQ_DMA2_CH1		56
+#define STM32F1_IRQ_DMA2_CH2		57
+#define STM32F1_IRQ_DMA2_CH3		58
+#define STM32F1_IRQ_DMA2_CH4_5		59
+/* IRQs below this point are available on connectivity line
+ * devices only
+ */
+#define STM32F1_IRQ_DMA2_CH4		STM32F1_IRQ_DMA2_CH4_5
+#define STM32F1_IRQ_DMA2_CH5		60
+#define STM32F1_IRQ_ETH		61
+#define STM32F1_IRQ_ETH_WKUP		62
+#define STM32F1_IRQ_CAN2_TX		63
+#define STM32F1_IRQ_CAN2_RX0		64
+#define STM32F1_IRQ_CAN2_RX1		65
+#define STM32F1_IRQ_CAN2_SCE		66
+#define STM32F1_IRQ_OTG_FS		67
+
+#endif	/* _STM32F1_SOC_IRQ_H_ */

arch/arm/soc/st_stm32/stm32f1/soc_registers.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _STM32F10X_SOC_REGISTERS_H_
+#define _STM32F10X_SOC_REGISTERS_H_
+
+/* include register mapping headers */
+#include "rcc_registers.h"
+#include "gpio_registers.h"
+#include "flash_registers.h"
+
+#endif /* _STM32F10X_SOC_REGISTERS_H_ */

arch/arm/soc/ti_lm3s6965/Kbuild

@@ -1,6 +1,3 @@
 obj-y += soc_config.o
 obj-y += soc.o
-obj-y += nmi_on_reset.o
 obj-y += scp.o
-
-obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o

arch/arm/soc/ti_lm3s6965/Kconfig

@@ -17,122 +17,10 @@
 #
 
 if SOC_TI_LM3S6965
-config SOC
-	default ti_lm3s6965
-
-config SRAM_BASE_ADDRESS
-	default 0x20000000
-
-config FLASH_BASE_ADDRESS
-	default 0x00000000
-
-config NUM_IRQ_PRIO_BITS
-	int
-	default 3
-
-config NUM_IRQS
-	int
-	# must be >= the highest interrupt number used
-	# - include the UART interrupts
-	default 34
 
 config SOC_TI_LM3S6965_QEMU
 	def_bool y
 	# Platform has only been tested on QEMU, not on real hardware, so always
 	# assume it is used for a QEMU target.
 
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	int
-	default 12000000
-
-config KERNEL_INIT_PRIORITY_DEFAULT
-	default 40
-
-config KERNEL_INIT_PRIORITY_DEVICE
-	default 50
-
-config UART_CONSOLE_PRIORITY
-	default 60
-
-config IPM_CONSOLE_PRIORITY
-	default 60
-
-if UART_STELLARIS
-
-config UART_STELLARIS_PORT_0
-	def_bool y
-
-if UART_STELLARIS_PORT_0
-config UART_STELLARIS_PORT_0_BASE_ADDR
-	default 0x4000C000
-config UART_STELLARIS_PORT_0_IRQ
-	default 6
-config UART_STELLARIS_PORT_0_BAUD_RATE
-	default 115200
-config UART_STELLARIS_PORT_0_CLK_FREQ
-	default 12000000
-endif
-
-config UART_STELLARIS_PORT_1
-	def_bool y
-
-if UART_STELLARIS_PORT_1
-config UART_STELLARIS_PORT_1_BASE_ADDR
-	default 0x4000D000
-config UART_STELLARIS_PORT_1_IRQ
-	default 6
-config UART_STELLARIS_PORT_1_BAUD_RATE
-	default 115200
-config UART_STELLARIS_PORT_1_CLK_FREQ
-	default 12000000
-endif
-
-config UART_STELLARIS_PORT_2
-	def_bool y
-if UART_STELLARIS_PORT_2
-config UART_STELLARIS_PORT_2_BASE_ADDR
-	default 0x4000E000
-config UART_STELLARIS_PORT_2_IRQ
-	default 33
-config UART_STELLARIS_PORT_2_BAUD_RATE
-	default 115200
-config UART_STELLARIS_PORT_2_CLK_FREQ
-	default 12000000
-endif
-
-endif # UART_STELLARIS
-
-if UART_CONSOLE
-
-config UART_CONSOLE_ON_DEV_NAME
-	default "UART_0"
-config UART_CONSOLE_IRQ
-	default 5
-config UART_CONSOLE_IRQ_PRI
-	default 3
-
-endif
-
-if BLUETOOTH_UART
-
-config BLUETOOTH_UART_ON_DEV_NAME
-	default "UART_1"
-config BLUETOOTH_UART_IRQ
-	default 6
-config BLUETOOTH_UART_IRQ_PRI
-	default 3
-
-endif
-
-if UART_PIPE
-
-config UART_PIPE_ON_DEV_NAME
-	default "UART_2"
-config UART_PIPE_IRQ
-	default 33
-config UART_PIPE_IRQ_PRI
-	default 3
-
-endif
-
-endif
+endif # SOC_TI_LM3S6965

arch/arm/soc/ti_lm3s6965/Kconfig.defconfig

@@ -0,0 +1,86 @@
+# Kconfig - TI LM3S6965 platform configuration options
+
+#
+# Copyright (c) 2014-2015 Wind River Systems, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_TI_LM3S6965
+
+config SOC
+	default ti_lm3s6965
+
+config SRAM_BASE_ADDRESS
+	default 0x20000000
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config NUM_IRQ_PRIO_BITS
+	int
+	default 3
+
+config NUM_IRQS
+	int
+	# must be >= the highest interrupt number used
+	# - include the UART interrupts
+	default 34
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 12000000
+
+if UART_STELLARIS
+
+config UART_STELLARIS_PORT_0
+	def_bool y
+
+if UART_STELLARIS_PORT_0
+config UART_STELLARIS_PORT_0_IRQ_PRI
+	default 3
+config UART_STELLARIS_PORT_0_BAUD_RATE
+	default 115200
+endif
+
+config UART_STELLARIS_PORT_1
+	def_bool y
+
+if UART_STELLARIS_PORT_1
+config UART_STELLARIS_PORT_1_IRQ_PRI
+	default 3
+config UART_STELLARIS_PORT_1_BAUD_RATE
+	default 115200
+endif
+
+config UART_STELLARIS_PORT_2
+	def_bool y
+if UART_STELLARIS_PORT_2
+config UART_STELLARIS_PORT_2_IRQ_PRI
+	default 3
+config UART_STELLARIS_PORT_2_BAUD_RATE
+	default 115200
+endif
+
+endif # UART_STELLARIS
+
+config BLUETOOTH_UART_ON_DEV_NAME
+	default "UART_1" if BLUETOOTH_UART
+
+config UART_PIPE_ON_DEV_NAME
+	default "UART_2" if UART_PIPE
+
+config BLUETOOTH_MONITOR_ON_DEV_NAME
+	default "UART_2" if  BLUETOOTH_DEBUG_MONITOR
+
+endif

arch/arm/soc/ti_lm3s6965/irq_vector_table.c

@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file
- * @brief IRQ part of vector table
- *
- * This file contains the IRQ part of the vector table. It is meant to be used
- * for one of two cases:
- *
- * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
- *    binds _isr_wrapper() to all the IRQ entries in the vector table.
- *
- * b) When the platform is written so that device ISRs are installed directly in
- *    the vector table, they are enumerated here.
- */
-
-#include <toolchain.h>
-#include <sections.h>
-
-#if defined(CONFIG_CONSOLE_HANDLER)
-#include <soc.h>
-#include <console/uart_console.h>
-#endif /* CONFIG_CONSOLE_HANDLER */
-
-#if defined(CONFIG_BLUETOOTH_UART)
-#include <soc.h>
-#include <bluetooth/uart.h>
-#endif /* CONFIG_BLUETOOTH_UART */
-
-extern void _isr_wrapper(void);
-typedef void (*vth)(void); /* Vector Table Handler */
-
-#if defined(CONFIG_SW_ISR_TABLE)
-
-vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
-	[0 ...(CONFIG_NUM_IRQS - 1)] = _isr_wrapper,
-};
-
-#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
-
-extern void _irq_spurious(void);
-
-#if defined(CONFIG_CONSOLE_HANDLER)
-static void _uart_console_isr(void)
-{
-	uart_console_isr(NULL);
-	_IntExit();
-}
-#endif /* CONFIG_CONSOLE_HANDLER */
-
-#if defined(CONFIG_BLUETOOTH_UART)
-static void _bt_uart_isr(void)
-{
-	bt_uart_isr(NULL);
-	_IntExit();
-}
-#endif /* CONFIG_BLUETOOTH_UART */
-
-/* placeholders: fill with real ISRs */
-vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
-	[0 ...(CONFIG_NUM_IRQS - 1)] = _irq_spurious,
-#if defined(CONFIG_CONSOLE_HANDLER)
-	[CONFIG_UART_CONSOLE_IRQ] = _uart_console_isr,
-#endif
-#if defined(CONFIG_BLUETOOTH_UART)
-	[CONFIG_BLUETOOTH_UART_IRQ] = _bt_uart_isr,
-#endif
-};
-
-#endif /* CONFIG_SW_ISR_TABLE */

arch/arm/soc/ti_lm3s6965/soc.c

@@ -27,12 +27,7 @@
 #include <init.h>
 #include <soc.h>
 
-#ifdef CONFIG_RUNTIME_NMI
-extern void _NmiInit(void);
-#define NMI_INIT() _NmiInit()
-#else
-#define NMI_INIT()
-#endif
+#include <arch/cpu.h>
 
 /**
  *

arch/arm/soc/ti_lm3s6965/soc.h

@@ -89,9 +89,23 @@ extern "C" {
 #include <drivers/rand32.h>
 
 /* uart configuration settings */
+#if defined(CONFIG_UART_STELLARIS)
 
 #define UART_IRQ_FLAGS 0
 
+#define UART_STELLARIS_PORT_0_BASE_ADDR	0x4000C000
+#define UART_STELLARIS_PORT_0_IRQ	IRQ_UART0
+
+#define UART_STELLARIS_PORT_1_BASE_ADDR	0x4000D000
+#define UART_STELLARIS_PORT_1_IRQ	IRQ_UART1
+
+#define UART_STELLARIS_PORT_2_BASE_ADDR	0x4000E000
+#define UART_STELLARIS_PORT_2_IRQ	IRQ_UART2
+
+#define UART_STELLARIS_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
+
+#endif /* CONFIG_UART_STELLARIS */
+
 #endif /* !_ASMLANGUAGE */
 
 #ifdef __cplusplus