Zephyr 1.3.0

Change-Id: I44ebde6cab75fbf64666c1a574ec57463a7167b0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.gitignore

@@ -19,9 +19,9 @@ scripts/kconfig/zconf.hash.c
 scripts/kconfig/zconf.lex.c
 scripts/kconfig/zconf.tab.c
 doc/_build
-xml
-html/
-doc/latex/
+doc/xml
+doc/html
+doc/latex
 sanity-out/
 scripts/grub
 doc/reference/kconfig/CONFIG_*

Makefile

@@ -1,5 +1,5 @@
 VERSION_MAJOR 	   = 1
-VERSION_MINOR 	   = 2
+VERSION_MINOR 	   = 3
 PATCHLEVEL 	   = 0
 VERSION_RESERVED   = 0
 EXTRAVERSION       =
@@ -281,15 +281,6 @@ KBUILD_BUILTIN := 1
 export KBUILD_BUILTIN
 export KBUILD_CHECKSRC KBUILD_SRC
 
-ifneq ($(CC),)
-ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
-COMPILER := clang
-else
-COMPILER := gcc
-endif
-export COMPILER
-endif
-
 # Look for make include files relative to root of kernel src
 MAKEFLAGS += --include-dir=$(srctree)
 
@@ -345,18 +336,22 @@ endif
 USERINCLUDE    := -include $(CURDIR)/include/generated/autoconf.h
 
 SOC_NAME = $(subst $(DQUOTE),,$(CONFIG_SOC))
+SOC_SERIES = $(subst $(DQUOTE),,$(CONFIG_SOC_SERIES))
+SOC_FAMILY = $(subst $(DQUOTE),,$(CONFIG_SOC_FAMILY))
+
 override ARCH = $(subst $(DQUOTE),,$(CONFIG_ARCH))
 BOARD_NAME = $(subst $(DQUOTE),,$(CONFIG_BOARD))
 KERNEL_NAME = $(subst $(DQUOTE),,$(CONFIG_KERNEL_BIN_NAME))
 KERNEL_ELF_NAME = $(KERNEL_NAME).elf
 KERNEL_BIN_NAME = $(KERNEL_NAME).bin
 
-export SOC_NAME BOARD_NAME ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME
+export SOC_FAMILY SOC_SERIES SOC_PATH SOC_NAME BOARD_NAME
+export ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME
 # Use ZEPHYRINCLUDE when you must reference the include/ directory.
 # Needed to be compatible with the O= option
 ZEPHYRINCLUDE    = \
 		-I$(srctree)/arch/$(ARCH)/include \
-		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_NAME) \
+		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH) \
 		-I$(srctree)/boards/$(BOARD_NAME) \
 		$(if $(KBUILD_SRC), -I$(srctree)/include) \
 		-I$(srctree)/include \
@@ -575,7 +570,16 @@ $(if $(CROSS_COMPILE),, \
      $(error ZEPHYR_GCC_VARIANT is not set. ))
 endif
 
-ifdef CONFIG_QMSI_DRIVERS
+ifneq ($(CC),)
+ifeq ($(shell $(CC) -v 2>&1 | grep -Ec "clang version|icx version"), 1)
+COMPILER := clang
+else
+COMPILER := gcc
+endif
+export COMPILER
+endif
+
+ifdef CONFIG_QMSI_LIBRARY
 LIB_INCLUDE_DIR += -L$(CONFIG_QMSI_INSTALL_PATH:"%"=%)/lib
 ALL_LIBS += qmsi
 endif
@@ -586,7 +590,7 @@ endif
 
 ifdef CONFIG_NEWLIB_LIBC
 ZEPHYRINCLUDE += $(TOOLCHAIN_CFLAGS)
-ALL_LIBS += c m
+ALL_LIBS += m c
 endif
 
 QEMU_BIN_PATH	?= /usr/bin
@@ -624,6 +628,11 @@ KBUILD_CFLAGS += $(subst $(DQUOTE),,$(CONFIG_COMPILER_OPT))
 
 export LDFLAG_LINKERCMD
 
+ifeq ($(SOC_SERIES),)
+SOC_PATH = $(SOC_NAME)
+else
+SOC_PATH = $(SOC_FAMILY)/$(SOC_SERIES)
+endif
 include arch/$(ARCH)/Makefile
 
 KBUILD_CFLAGS += $(CFLAGS)
@@ -632,7 +641,6 @@ KBUILD_AFLAGS += $(CFLAGS)
 
 
 ifeq ($(COMPILER),clang)
-KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
 KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,)
 KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
 KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
@@ -655,6 +663,7 @@ endif
 
 # arch Makefile may override CC so keep this after arch Makefile is included
 NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
+NOSTDINC_FLAGS += -isystem $(shell $(CC) -print-file-name=include-fixed)
 CHECKFLAGS     += $(NOSTDINC_FLAGS)
 
 # disable pointer signed / unsigned warnings in gcc 4.0
@@ -704,7 +713,7 @@ KBUILD_LDS := $(srctree)/boards/$(BOARD_NAME)/linker.cmd
 
 # If not available, try an SoC specific linker file
 ifeq ($(wildcard $(KBUILD_LDS)),)
-KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/linker.cmd
+KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/linker.cmd
 endif
 endif
 

Makefile.inc

@@ -25,7 +25,9 @@ override CONF_FILE := $(strip $(subst $(DQUOTE),,$(CONF_FILE)))
 
 ifdef BOARD
 KBUILD_DEFCONFIG_PATH=$(wildcard $(ZEPHYR_BASE)/boards/*/$(BOARD)_defconfig)
-export KBUILD_DEFCONFIG_PATH
+ifeq ($(KBUILD_DEFCONFIG_PATH),)
+$(error Board $(BOARD) not found!)
+endif
 else
 $(error BOARD is not defined!)
 endif

arch/Kconfig

@@ -63,16 +63,35 @@ config ARCH
 	System architecture string.
 
 config SOC
-        string
-        help
-        This option holds the directory name used by the build system to locate
-        the correct linker file.
+	string
+	help
+	SoC name which can be found under arch/<arch>/soc/<soc name>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files for the SoC. This option will go away
+	once all SoCs are using family/series structure.
+
+config SOC_SERIES
+	string
+	help
+	SoC series name which can be found under arch/<arch>/soc/<family>/<series>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
+
+config SOC_FAMILY
+	string
+	help
+	SoC family name which can be found under arch/<arch>/soc/<family>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
 
 config BOARD
 	string
 	help
 	This option holds the name of the board and is used to located the files
-	related to the board in the source tree.
+	related to the board in the source tree (under boards/).
+	The Board is the first location where we search for a linker.cmd file,
+	if not found we look for the linker file in
+	arch/<arch>/soc/<family>/<series>
 
 source "arch/*/Kconfig"
 

arch/Makefile

@@ -1,9 +1 @@
-ifeq (${ARCH},arm)
-obj-y += arm/
-endif
-ifeq (${ARCH},x86)
-obj-y += x86/
-endif
-ifeq (${ARCH},arc)
-obj-y += arc/
-endif
+obj-y += $(ARCH)/

arch/arc/Kbuild

@@ -2,5 +2,5 @@ subdir-ccflags-y +=-I$(srctree)/include/drivers
 subdir-ccflags-y +=-I$(srctree)/drivers
 subdir-asflags-y += $(subdir-ccflags-y)
 
-obj-y += soc/$(SOC_NAME)/
+obj-y += soc/$(SOC_PATH)/
 obj-y += core/

arch/arc/Kconfig

@@ -40,6 +40,7 @@ config	CPU_ARCEM4
 	bool
 	default y
 	select CPU_ARCV2
+	select ATOMIC_OPERATIONS_C
 	help
 	This option signifies the use of an ARC EM4 CPU
 
@@ -54,14 +55,6 @@ config	CPU_ARCV2
 	help
 	  This option signifies the use of a CPU of the ARCv2 family.
 
-config RAM_START
-	prompt "RAM start address"
-	hex
-
-config RAM_SIZE
-	prompt "RAM size (in kB)"
-	int
-
 config NSIM
 	prompt "Running on the MetaWare nSIM simulator"
 	bool
@@ -164,6 +157,47 @@ config	XIP
 	default n if NSIM
 	default y
 
+config DCCM_SIZE
+	int "DCCM Size in kB"
+	help
+	This option specifies the size of the DCCM in kB.  It is normally set by
+	the platform's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config DCCM_BASE_ADDRESS
+	hex "DCCM Base Address"
+	help
+	This option specifies the base address of the DCCM on the platform.  It is
+	normally set by the platform's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config SRAM_SIZE
+	int "SRAM Size in kB"
+	help
+	This option specifies the size of the SRAM in kB.  It is normally set by
+	the platform's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config SRAM_BASE_ADDRESS
+	hex "SRAM Base Address"
+	help
+	This option specifies the base address of the SRAM on the platform.  It is
+	normally set by the platform's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config FLASH_SIZE
+	int "Flash Size in kB"
+	help
+	This option specifies the size of the flash in kB.  It is normally set by
+	the platform's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config FLASH_BASE_ADDRESS
+	hex "Flash Base Address"
+	help
+	This option specifies the base address of the flash on the platform.  It is
+	normally set by the platform's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
 config NSIM
 	prompt "Running on the MetaWare nSIM simulator"
 	bool
@@ -240,19 +274,6 @@ config  ARCH_HAS_NANO_FIBER_ABORT
 	# omit prompt to signify a "hidden" option
 	default n
 
-config  ARC_ATOMIC_ASM
-	bool
-	default n
-	depends on !CPU_ARCEM4
-	help
-	  Say y if the processor supports atomic assembly instructions:
-	  LLOCK and SCOND.
-
-	  Say n if not sure.
-
-	  Note that these instructions are not supported on ARC EM family
-	  processors.
-
 endmenu
 
 

arch/arc/Makefile

@@ -2,7 +2,7 @@ cflags-y += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-secti
 cflags-$(CONFIG_ARC_STACK_CHECKING) = $(call cc-option,-fomit-frame-pointer)
 cflags-$(CONFIG_LTO) = $(call cc-option,-flto,)
 
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/Makefile
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 
 KBUILD_CFLAGS += $(cflags-y)
 KBUILD_CXXFLAGS += $(cflags-y)

arch/arc/core/Makefile

@@ -15,10 +15,8 @@ obj-y += prep_c.o \
 obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
 obj-$(CONFIG_ERRNO) += errno.o
 
-ifeq ($(CONFIG_ARC_ATOMIC_ASM),y)
+ifneq ($(CONFIG_ATOMIC_OPERATIONS_C),y)
 obj-y += atomic.o
-else
-obj-y += atomic_native.o
 endif
 
 obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o

arch/arc/core/isr_wrapper.S

@@ -211,6 +211,22 @@ SECTION_FUNC(TEXT, _isr_enter)
 
 	j_s.nd [r2]
 
+#if defined(CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT)
+GTEXT(_sys_k_event_logger_interrupt)
+
+.macro log_interrupt_k_event
+	clri r0 /* do not interrupt event logger operations */
+	push_s r0
+	push_s blink
+	jl _sys_k_event_logger_interrupt
+	pop_s blink
+	pop_s r0
+	seti r0
+.endm
+#else
+	#define log_interrupt_k_event
+#endif
+
 #if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
 .macro exit_tickless_idle
 	clri r0 /* do not interrupt exiting tickless idle operations */
@@ -232,6 +248,7 @@ SECTION_FUNC(TEXT, _isr_demux)
 	/* cannot be done before this point because we must be able to run C */
 	/* r0 is available to be stomped here, and exit_tickless_idle uses it */
 	exit_tickless_idle
+	log_interrupt_k_event
 
 	lr r0, [_ARC_V2_ICAUSE]
 	sub r0, r0, 16

arch/arc/core/reset.S

@@ -28,7 +28,7 @@
 #include <sections.h>
 #include <arch/cpu.h>
 
-#define _RAM_END (CONFIG_RAM_START + CONFIG_RAM_SIZE * 1024)
+#define _RAM_END (CONFIG_SRAM_BASE_ADDRESS + CONFIG_SRAM_SIZE * 1024)
 
 GTEXT(__reset)
 

arch/arc/include/kernel_event_logger_arch.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Kernel event logger support for ARM
+ */
+
+#ifndef __KERNEL_EVENT_LOGGER_ARCH_H__
+#define __KERNEL_EVENT_LOGGER_ARCH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get the identification of the current interrupt.
+ *
+ * This routine obtain the key of the interrupt that is currently processed
+ * if it is called from a ISR context.
+ *
+ * @return The key of the interrupt that is currently being processed.
+ */
+int _sys_current_irq_key_get(void)
+{
+	return _INTERRUPT_CAUSE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __KERNEL_EVENT_LOGGER_ARCH_H__ */

arch/arc/include/nano_private.h

@@ -278,6 +278,21 @@ static ALWAYS_INLINE int _IS_IN_ISR(void)
 	return ((act & 0xffff) != 0);
 }
 
+/**
+ *
+ * @bried Indicates the interrupt number of the highest priority
+ * active interrupt
+ *
+ * @return IRQ number
+ */
+static ALWAYS_INLINE int _INTERRUPT_CAUSE(void)
+{
+	uint32_t irq_num = _arc_v2_aux_reg_read(_ARC_V2_ICAUSE);
+
+	return irq_num;
+}
+
+
 extern void nanoCpuAtomicIdle(unsigned int);
 extern void _thread_entry_wrapper(void);
 

arch/arc/soc/quark_se_ss/Kconfig.defconfig

@@ -37,14 +37,26 @@ config  NUM_IRQS
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 32000000
 
-config RAM_START
+config FLASH_BASE_ADDRESS
+	default 0x40000000
+
+config FLASH_SIZE
+	default 152
+
+config SRAM_BASE_ADDRESS
 	default 0x4000 if NSIM
 	default 0xa8000400
 
-config RAM_SIZE
+config SRAM_SIZE
 	default 16 if NSIM
 	default 24
 
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 8
+
 if GPIO
 
 config GPIO_DW
@@ -60,14 +72,8 @@ config GPIO_DW_0
 
 if GPIO_DW_0
 
-config GPIO_DW_0_BASE_ADDR
-	default 0x80017800
-config GPIO_DW_0_IRQ
-	default 20
 config GPIO_DW_0_PRI
 	default 2
-config GPIO_DW_0_BITS
-	default 8
 
 endif # GPIO_DW_0
 
@@ -76,14 +82,8 @@ config GPIO_DW_1
 
 if GPIO_DW_1
 
-config GPIO_DW_1_BASE_ADDR
-	default 0x80017900
-config GPIO_DW_1_IRQ
-	default 21
 config GPIO_DW_1_PRI
 	default 2
-config GPIO_DW_1_BITS
-	default 8
 
 endif # GPIO_DW_1
 
@@ -104,7 +104,7 @@ config I2C_QUARK_SE_SS_0
 if I2C_QUARK_SE_SS_0
 
 config I2C_QUARK_SE_SS_0_NAME
-	default "I2C0"
+	default "I2C_0"
 
 config I2C_QUARK_SE_SS_0_DEFAULT_CFG
 	default 0x12
@@ -114,7 +114,7 @@ endif # I2C_QUARK_SE_SS_0
 if I2C_QUARK_SE_SS_1
 
 config I2C_QUARK_SE_SS_1_NAME
-	default "I2C1"
+	default "I2C_1"
 
 config I2C_QUARK_SE_SS_1_DEFAULT_CFG
 	default 0x12

arch/arc/soc/quark_se_ss/linker.cmd

@@ -20,8 +20,8 @@
  */
 
 /* Flash base address and size */
-#define FLASH_START     0x40000000  /* Flash bank 1 */
-#define FLASH_SIZE      152K
+#define FLASH_START     CONFIG_FLASH_BASE_ADDRESS  /* Flash bank 1 */
+#define FLASH_SIZE      CONFIG_FLASH_SIZE
 
 /*
  * SRAM base address and size
@@ -29,11 +29,11 @@
  * Internal SRAM includes the exception vector table at reset, which is at
  * the beginning of the region.
  */
-#define SRAM_START		CONFIG_RAM_START
-#define SRAM_SIZE		CONFIG_RAM_SIZE
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
 
 /* Data Closely Coupled Memory (DCCM) base address and size */
-#define DCCM_START		0x80000000
-#define DCCM_SIZE		8K
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
 
 #include <arch/arc/v2/linker.cmd>

arch/arc/soc/quark_se_ss/soc.h

@@ -148,8 +148,22 @@
 /*
  * GPIO
  */
-#define GPIO_DW_PORT_0_INT_MASK				(SCSS_REGISTER_BASE + 0x408)
-#define GPIO_DW_PORT_1_INT_MASK				(SCSS_REGISTER_BASE + 0x40C)
+#define GPIO_DW_IO_ACCESS
+
+#define GPIO_DW_0_BASE_ADDR			0x80017800
+#define GPIO_DW_0_IRQ				20
+#define GPIO_DW_0_BITS				8
+#define GPIO_DW_PORT_0_INT_MASK			(SCSS_REGISTER_BASE + 0x408)
+
+#define GPIO_DW_1_BASE_ADDR			0x80017900
+#define GPIO_DW_1_IRQ				21
+#define GPIO_DW_1_BITS				8
+#define GPIO_DW_PORT_1_INT_MASK			(SCSS_REGISTER_BASE + 0x40C)
+
+#if defined(CONFIG_IOAPIC)
+#define GPIO_DW_0_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
+#define GPIO_DW_1_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
+#endif
 
 /*
  * UART

arch/arc/soc/quark_se_ss/soc_config.c

@@ -33,9 +33,10 @@ static int arc_quark_se_ipm_init(void)
 static struct quark_se_ipm_controller_config_info ipm_controller_config = {
 	.controller_init = arc_quark_se_ipm_init
 };
-DEVICE_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
+DEVICE_AND_API_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
 				NULL, &ipm_controller_config,
-				SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+				SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+				&ipm_quark_se_api_funcs);
 
 #if CONFIG_IPM_CONSOLE_SENDER
 #include <console/ipm_console.h>

arch/arm/Kbuild

@@ -2,5 +2,10 @@ subdir-ccflags-y +=-I$(srctree)/include/drivers
 subdir-ccflags-y +=-I$(srctree)/drivers
 subdir-asflags-y := ${subdir-ccflags-y}
 
-obj-y += soc/$(SOC_NAME)/
+ifneq ($(SOC_FAMILY),)
+obj-y += soc/$(SOC_FAMILY)/
+else
+obj-y += soc/$(SOC_PATH)/
+endif
+
 obj-y += core/

arch/arm/Kconfig

@@ -18,7 +18,7 @@
 
 choice
 	prompt "ARM SoC Selection"
-	default SOC_FSL_FRDM_K64F
+	default SOC_SERIES_KINETIS_K6X
 	depends on ARM
 
 	source "arch/arm/soc/*/Kconfig.soc"

arch/arm/Makefile

@@ -1,6 +1,6 @@
 KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
 
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/Makefile
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 
 cflags-$(CONFIG_LTO) += $(call cc-option,-flto,)
 

arch/arm/core/cortex_m/Makefile

@@ -1,5 +1,5 @@
 ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/arch/$(ARCH)/platforms/$(SOC_NAME)
+ccflags-y +=-I$(srctree)/arch/arm/soc/$(SOC_PATH)
 
 asflags-y = $(ccflags-y)
 

arch/arm/soc/atmel_sam3/Kconfig.defconfig

@@ -75,7 +75,10 @@ config UART_ATMEL_SAM3_CLK_FREQ
 
 endif # UART_ATMEL_SAM3
 
-if GPIO_ATMEL_SAM3
+if GPIO
+
+config GPIO_ATMEL_SAM3
+	def_bool y
 
 config GPIO_ATMEL_SAM3_PORTA
 	default y
@@ -89,9 +92,12 @@ config GPIO_ATMEL_SAM3_PORTC
 config GPIO_ATMEL_SAM3_PORTD
 	default y
 
-endif # GPIO_ATMEL_SAM3
+endif # GPIO
 
-if I2C_ATMEL_SAM3
+if I2C
+
+config I2C_ATMEL_SAM3
+	def_bool y
 
 config I2C_ATMEL_SAM3_0
 	default y
@@ -99,6 +105,6 @@ config I2C_ATMEL_SAM3_0
 config I2C_ATMEL_SAM3_1
 	default y
 
-endif # I2C_ATMEL_SAM3
+endif # I2C
 
 endif # SOC_ATMEL_SAM3

arch/arm/soc/fsl_frdm_k64f/Kconfig.soc

@@ -1,6 +0,0 @@
-
-config  SOC_FSL_FRDM_K64F
-	bool "Freescale FRDM-K64F"
-	select CPU_CORTEX_M
-	select CPU_CORTEX_M4
-	select SYS_POWER_LOW_POWER_STATE_SUPPORTED

arch/arm/soc/nxp_kinetis/Kbuild

@@ -0,0 +1,2 @@
+
+obj-y += $(SOC_SERIES)/

arch/arm/soc/nxp_kinetis/Kconfig

@@ -0,0 +1,28 @@
+#
+# Copyright (c) 2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config SOC_FAMILY_KINETIS
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
+
+if SOC_FAMILY_KINETIS
+config SOC_FAMILY
+	string
+	default "nxp_kinetis"
+endif
+
+source "arch/arm/soc/nxp_kinetis/*/Kconfig.soc"

arch/arm/soc/nxp_kinetis/Kconfig.defconfig

@@ -0,0 +1 @@
+source "arch/arm/soc/nxp_kinetis/*/Kconfig.defconfig.series"

arch/arm/soc/nxp_kinetis/Kconfig.soc

@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+source "arch/arm/soc/nxp_kinetis/*/Kconfig.series"

arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.mk64f12

@@ -16,29 +16,11 @@
 # limitations under the License.
 #
 
-if SOC_FSL_FRDM_K64F
+if SOC_MK64F12
 
 config SOC
-	default fsl_frdm_k64f
-
-config SRAM_BASE_ADDRESS
-	default 0x20000000
-
-config FLASH_BASE_ADDRESS
-	default 0x00000000
-
-config NUM_IRQ_PRIO_BITS
-	int
-	default 4
-
-config NUM_IRQS
-	int
-	# must be >= the highest interrupt number used
-	default 86
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	int
-	default 120000000
+	string
+	default mk64f12
 
 if UART_K20
 
@@ -185,4 +167,4 @@ endif # SPI_K64
 
 endif # SPI
 
-endif # SOC_FSL_FRDM_K64F
+endif # SOC_MK64F12

arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.series

@@ -0,0 +1,41 @@
+# Kconfig - Kinetis K6x series configuration options
+
+#
+# Copyright (c) 2014-2016 Wind River Systems, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_SERIES_KINETIS_K6X
+
+config SOC_SERIES
+	default k6x
+
+config SRAM_BASE_ADDRESS
+	default 0x20000000
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config NUM_IRQ_PRIO_BITS
+	int
+	default 4
+
+config NUM_IRQS
+	int
+	# must be >= the highest interrupt number used
+	default 86
+
+source "arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.mk*"
+
+endif # SOC_SERIES_KINETIS_K6X

arch/arm/soc/nxp_kinetis/k6x/Kconfig.series

@@ -0,0 +1,25 @@
+# Kconfig - Kinetis K6X MCU line
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config SOC_SERIES_KINETIS_K6X
+	bool "Kinetis K6x Series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_KINETIS
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	help
+	 Enable support for Kinetis K6x MCU series

arch/arm/soc/nxp_kinetis/k6x/Kconfig.soc

@@ -1,7 +1,6 @@
-# Kconfig - FSL FRDM K64F platform configuration options
-
+# Kconfig - Kinetis K6X MCU line
 #
-# Copyright (c) 2014-2016 Wind River Systems, Inc.
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -16,7 +15,16 @@
 # limitations under the License.
 #
 
-if SOC_FSL_FRDM_K64F
+choice
+prompt "Kinetis K6x MCU Selection"
+depends on SOC_SERIES_KINETIS_K6X
+
+config SOC_MK64F12
+       bool "SOC_MK64F12"
+
+endchoice
+
+if SOC_SERIES_KINETIS_K6X
 
 config K64_CORE_CLOCK_DIVIDER
 	int
@@ -59,7 +67,7 @@ config WDOG_INIT
 	during reset handling.
 
 config PRESERVE_JTAG_IO_PINS
-	bool "Freescale FRDM-K64F JTAG pin usage"
+	bool "Kinetis K6x JTAG pin usage"
 	depends on PINMUX
 	default y
 	help
@@ -68,4 +76,4 @@ config PRESERVE_JTAG_IO_PINS
 	the Arduino header as D8, D3 and D5, respectively.
 	Enable this option to preserve these pins for the debug interface.
 
-endif # SOC_FSL_FRDM_K64F
+endif # SOC_SERIES_KINETIS_K6X

arch/arm/soc/st_stm32/Kbuild

@@ -0,0 +1,2 @@
+
+obj-y += $(SOC_SERIES)/

arch/arm/soc/st_stm32/Kconfig

@@ -15,9 +15,15 @@
 # limitations under the License.
 #
 
-config SOC_STM32
+config SOC_FAMILY_STM32
 	bool
 	# omit prompt to signify a "hidden" option
 	default n
 
-source "arch/arm/soc/st_stm32/*/Kconfig.soc.family"
+if SOC_FAMILY_STM32
+config SOC_FAMILY
+	string
+	default st_stm32
+endif
+
+source "arch/arm/soc/st_stm32/*/Kconfig.soc"

arch/arm/soc/st_stm32/Kconfig.defconfig

@@ -1 +1 @@
-source "arch/arm/soc/st_stm32/*/Kconfig.defconfig.family"
+source "arch/arm/soc/st_stm32/*/Kconfig.defconfig.series"

arch/arm/soc/st_stm32/Kconfig.soc

@@ -15,11 +15,4 @@
 # limitations under the License.
 #
 
-config SOC_STM32F1X
-	bool "STM32F1x Series MCU"
-	select CPU_CORTEX_M
-	select CPU_CORTEX_M3
-	select SOC_STM32
-	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
-	help
-	 Enable support for STM32F1 MCU series
+source "arch/arm/soc/st_stm32/*/Kconfig.series"

arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.series

@@ -15,12 +15,12 @@
 # limitations under the License.
 #
 
-if SOC_STM32F1X
+if SOC_SERIES_STM32F1X
 
 source "arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f1*"
 
-config SOC
-       default st_stm32/stm32f1
+config SOC_SERIES
+       default stm32f1
 
 config SRAM_BASE_ADDRESS
         default 0x20000000
@@ -32,4 +32,4 @@ config NUM_IRQ_PRIO_BITS
         int
         default 4
 
-endif # SOC_STM32F1X
+endif # SOC_SERIES_STM32F1X

arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103rb

@@ -17,6 +17,9 @@
 
 if SOC_STM32F103RB
 
+config SOC
+	string
+	default stm32f103rb
 config SRAM_SIZE
        default 20
 

arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103ve

@@ -17,6 +17,10 @@
 
 if SOC_STM32F103VE
 
+config SOC
+	string
+	default stm32f103ve
+
 config SRAM_SIZE
        default 64
 

arch/arm/soc/st_stm32/stm32f1/Kconfig.series

@@ -0,0 +1,25 @@
+# Kconfig - ST Microelectronics STM32F1 MCU series
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config SOC_SERIES_STM32F1X
+	bool "STM32F1x Series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M3
+	select SOC_FAMILY_STM32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	help
+	 Enable support for STM32F1 MCU series

arch/arm/soc/st_stm32/stm32f1/Kconfig.soc

@@ -17,7 +17,7 @@
 
 choice
 prompt "STM32F1x MCU Selection"
-depends on SOC_STM32F1X
+depends on SOC_SERIES_STM32F1X
 
 config SOC_STM32F103VE
        bool "STM32F103VE"

arch/arm/soc/st_stm32/stm32f1/soc_config.c

@@ -14,6 +14,8 @@
  * limitations under the License.
  */
 
+#include <errno.h>
+
 #include "soc.h"
 #include <device.h>
 #include <misc/util.h>

arch/arm/soc/st_stm32/stm32f1/soc_gpio.c

@@ -25,6 +25,8 @@
  *            (GPIOs and AFIOs)
  */
 
+#include <errno.h>
+
 #include <device.h>
 #include "soc.h"
 #include "soc_registers.h"

arch/arm/soc/ti_lm3s6965/Kconfig.defconfig

@@ -80,4 +80,7 @@ config BLUETOOTH_UART_ON_DEV_NAME
 config UART_PIPE_ON_DEV_NAME
 	default "UART_2" if UART_PIPE
 
+config BLUETOOTH_MONITOR_ON_DEV_NAME
+	default "UART_2" if  BLUETOOTH_DEBUG_MONITOR
+
 endif

arch/x86/Kbuild

@@ -1,2 +1,3 @@
 obj-y += core/
-obj-y += soc/$(SOC_NAME)/
+obj-$(CONFIG_GDB_SERVER) += debug/
+obj-y += soc/$(SOC_PATH)/

arch/x86/Makefile

@@ -8,9 +8,18 @@ PREFERRED_STACK_BOUNDARY = y
 endif
 
 ifeq ($(COMPILER),clang)
+ifeq ($(CONFIG_X86_IAMCU),)
+KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
+else
+CC_M32 = -m32 -mmcu
+KBUILD_CFLAGS   += -mmcu
+KBUILD_CPPFLAGS += -mmcu
+endif
 biarch := $(call cc-option,-m32)
+dwarf2 := $(call cc-option,-gdwarf-2)
 KBUILD_AFLAGS += $(biarch)
 KBUILD_CFLAGS += $(biarch)
+KBUILD_CFLAGS += $(dwarf2)
 else
 cflags-$(PREFERRED_STACK_BOUNDARY) += $(call cc-option,-mpreferred-stack-boundary=2)
 endif
@@ -20,7 +29,7 @@ ifneq ($(CONFIG_SSE_FP_MATH),y)
 cflags-y += -mno-sse
 endif
 
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/Makefile
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 
 KBUILD_CXXFLAGS += $(cflags-y)
 KBUILD_CFLAGS += $(cflags-y)

arch/x86/core/Makefile

@@ -1,7 +1,7 @@
 ccflags-y += -I$(srctree)/kernel/nanokernel/include
 ccflags-y += -I$(srctree)/kernel/microkernel/include
 
-ifeq ($(COMPILER),clang)
+ifeq ($(COMPILER)$(CONFIG_X86_IAMCU),clang)
 # We rely on GAS for assembling, so don't use the integrated assembler
 KBUILD_AFLAGS += -no-integrated-as
 endif
@@ -28,3 +28,6 @@ obj-$(CONFIG_MICROKERNEL) += strtask.o
 obj-$(CONFIG_ERRNO) += errno.o
 obj-$(CONFIG_GDT_DYNAMIC) += gdt.o
 obj-$(CONFIG_REBOOT_RST_CNT) += reboot_rst_cnt.o
+
+obj-$(CONFIG_DEBUG_INFO) += debug/
+obj-$(CONFIG_REBOOT_RST_CNT) += reboot_rst_cnt.o

arch/x86/core/debug/Makefile

@@ -0,0 +1,4 @@
+ccflags-y += -I$(srctree)/kernel/nanokernel/include
+ccflags-y += -I$(srctree)/kernel/microkernel/include
+
+obj-y = debug_frames.o

arch/x86/core/debug/debug_frames.c

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2015 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Stack frames for debugging purposes
+ *
+ * This file contains a routine useful for debugging that gets a pointer to
+ * the current interrupt stack frame.
+ */
+
+#include <nanokernel.h>
+#include <nano_private.h>
+
+NANO_ISF *sys_debug_current_isf_get(void)
+{
+	return _nanokernel.isf;
+}

arch/x86/core/excstub.S

@@ -308,7 +308,11 @@ SYS_NANO_CPU_EXC_CONNECT(_FpNotAvailableExcHandler,IV_DEVICE_NOT_AVAILABLE)
 #define EXC_HANDLER(vec) NANO_CPU_EXC_CONNECT_NO_ERR(handle_exc_##vec, vec, 0)
 #define EXC_HANDLER_CODE(vec) NANO_CPU_EXC_CONNECT(handle_exc_##vec, vec, 0)
 
+#if !defined(CONFIG_DEBUGGER_OWNS_FATAL_PROG_EXC_HANDLERS)
 EXC_HANDLER(IV_DIVIDE_ERROR)
+EXC_HANDLER_CODE(IV_PAGE_FAULT)
+#endif
+
 EXC_HANDLER(IV_NON_MASKABLE_INTERRUPT)
 EXC_HANDLER(IV_OVERFLOW)
 EXC_HANDLER(IV_BOUND_RANGE)
@@ -321,7 +325,6 @@ EXC_HANDLER_CODE(IV_INVALID_TSS)
 EXC_HANDLER_CODE(IV_SEGMENT_NOT_PRESENT)
 EXC_HANDLER_CODE(IV_STACK_FAULT)
 EXC_HANDLER_CODE(IV_GENERAL_PROTECTION)
-EXC_HANDLER_CODE(IV_PAGE_FAULT)
 EXC_HANDLER(IV_X87_FPU_FP_ERROR)
 EXC_HANDLER_CODE(IV_ALIGNMENT_CHECK)
 EXC_HANDLER(IV_MACHINE_CHECK)

arch/x86/core/fatal.c

@@ -30,6 +30,8 @@
 #include <asmPrv.h>
 #include <drivers/loapic.h>
 
+__weak void _debug_fatal_hook(const NANO_ESF *esf) { ARG_UNUSED(esf); }
+
 /*
  * Define a default ESF for use with _NanoFatalErrorHandler() in the event
  * the caller does not have a NANO_ESF to pass
@@ -68,6 +70,7 @@ const NANO_ESF _default_esf = {
 FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 					  const NANO_ESF *pEsf)
 {
+	_debug_fatal_hook(pEsf);
 
 #ifdef CONFIG_PRINTK
 

arch/x86/core/i386_sysV_abi/Makefile

@@ -2,7 +2,7 @@ ccflags-y += -I$(srctree)/kernel/nanokernel/include
 ccflags-y += -I$(srctree)/kernel/microkernel/include
 
 # see explanation for flags in arch/x86/core/Makefile
-ifeq ($(COMPILER),clang)
+ifeq ($(COMPILER)$(CONFIG_X86_IAMCU),clang)
 KBUILD_AFLAGS += -no-integrated-as
 endif
 KBUILD_AFLAGS += -Wa,--divide

arch/x86/core/i386_sysV_abi/intstub.S

@@ -132,6 +132,21 @@ SECTION_FUNC(TEXT, _IntEnt)
 	pushl	%ecx
 	pushl	%edx
 
+#ifdef CONFIG_DEBUG_INFO
+	/*
+	 * Push the cooperative registers on the existing stack as they are
+	 * required by debug tools.
+	 */
+
+	pushl	%edi
+	pushl	%esi
+	pushl	%ebx
+	pushl	%ebp
+
+	leal	44(%esp), %ecx   /* Calculate ESP before interrupt occurred */
+	pushl	%ecx             /* Save calculated ESP */
+#endif
+
 #ifdef CONFIG_INT_LATENCY_BENCHMARK
 	/*
 	 * Volatile registers are now saved it is safe to start measuring
@@ -173,7 +188,11 @@ SECTION_FUNC(TEXT, _IntEnt)
 
 	incl	__tNANO_nested_OFFSET(%ecx)	/* inc interrupt nest count */
 	cmpl	$1, __tNANO_nested_OFFSET(%ecx)	/* use int stack if !nested */
+#ifdef CONFIG_DEBUG_INFO
+	jne	nested_save_isf
+#else
 	jne	alreadyOnIntStack
+#endif
 
 	/* switch to base of the interrupt stack */
 
@@ -185,12 +204,30 @@ SECTION_FUNC(TEXT, _IntEnt)
 
 	pushl	%edx			/* Save stack pointer */
 
+#ifdef CONFIG_DEBUG_INFO
+	/*
+	 * The saved stack pointer happens to match the address of the
+	 * interrupt stack frame.  To simplify the exit case, push a dummy ISF
+	 * for the "old" ISF and save it to the _nanokernel.isf.
+	 */
+	pushl	%edx
+	movl	%edx, __tNANO_isf_OFFSET(%ecx)
+#endif
+
 #ifdef CONFIG_SYS_POWER_MANAGEMENT
 	cmpl	$0, __tNANO_idle_OFFSET(%ecx)
 	jne	_HandleIdle
 	/* fast path is !idle, in the pipeline */
 #endif
 
+#ifdef CONFIG_DEBUG_INFO
+	jmp alreadyOnIntStack
+
+BRANCH_LABEL(nested_save_isf)
+	movl	__tNANO_isf_OFFSET(%ecx), %edx	/* Get old ISF */
+	movl	%esp, __tNANO_isf_OFFSET(%ecx)	/* Save new ISF */
+	pushl	%edx                            /* Save old ISF */
+#endif
 
 	/* fall through to nested case */
 
@@ -290,6 +327,9 @@ BRANCH_LABEL(_IntExit)
 	/* determine whether exiting from a nested interrupt */
 
 	movl	$_nanokernel, %ecx
+#ifdef CONFIG_DEBUG_INFO
+	popl	__tNANO_isf_OFFSET(%ecx)    /* Restore old ISF */
+#endif
 	decl	__tNANO_nested_OFFSET(%ecx)	/* dec interrupt nest count */
 	jne	nestedInterrupt                 /* 'iret' if nested case */
 
@@ -331,6 +371,14 @@ BRANCH_LABEL(_IntExit)
 
 	popl	%esp		/* switch back to kernel stack */
 
+#ifdef CONFIG_DEBUG_INFO
+	popl	%ebp        /* Discard saved ESP */
+	popl	%ebp
+	popl	%ebx
+	popl	%esi
+	popl	%edi
+#endif
+
 	pushfl			/* push KERNEL_LOCK_KEY argument */
 	call	_Swap
 
@@ -397,6 +445,15 @@ BRANCH_LABEL(nestedInterrupt)
 #ifdef CONFIG_INT_LATENCY_BENCHMARK
 	call	_int_latency_stop
 #endif
+
+#ifdef CONFIG_DEBUG_INFO
+	popl	%ebp        /* Discard saved ESP */
+	popl	%ebp
+	popl	%ebx
+	popl	%esi
+	popl	%edi
+#endif
+
 	popl	%edx		/* pop volatile registers in reverse order */
 	popl	%ecx
 	popl	%eax

arch/x86/core/i386_sysV_abi/thread.c

@@ -41,10 +41,10 @@ tNANO _nanokernel = {0};
 
 /* forward declaration */
 
-#ifdef CONFIG_GDB_INFO
+#if defined(CONFIG_GDB_INFO) || defined(CONFIG_DEBUG_INFO)
 void _thread_entry_wrapper(_thread_entry_t, _thread_arg_t,
 			   _thread_arg_t, _thread_arg_t);
-#endif /* CONFIG_GDB_INFO */
+#endif
 
 /**
  *
@@ -199,7 +199,7 @@ static void _new_thread_internal(char *pStackMem, unsigned stackSize,
 	_nano_timeout_tcs_init(tcs);
 }
 
-#ifdef CONFIG_GDB_INFO
+#if defined(CONFIG_GDB_INFO) || defined(CONFIG_DEBUG_INFO)
 /**
  *
  * @brief Adjust stack before invoking _thread_entry
@@ -263,7 +263,7 @@ __asm__("\t.globl _thread_entry\n"
 				    */
 	"\tmovl $0, (%esp)\n" /* zero initialEFLAGS location */
 	"\tjmp _thread_entry\n");
-#endif /* CONFIG_GDB_INFO */
+#endif /* defined(CONFIG_GDB_INFO) || defined(CONFIG_DEBUG_INFO) */
 
 /**
  *
@@ -320,7 +320,7 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 
 	*--pInitialThread = (EflagsGet() & ~EFLAGS_MASK) | EFLAGS_INITIAL;
 
-#ifdef CONFIG_GDB_INFO
+#if defined(CONFIG_GDB_INFO) || defined(CONFIG_DEBUG_INFO)
 
 	/*
 	 * Arrange for the _thread_entry_wrapper() function to be called
@@ -329,11 +329,11 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 
 	*--pInitialThread = (unsigned long)_thread_entry_wrapper;
 
-#else /* CONFIG_GDB_INFO */
+#else /* defined(CONFIG_GDB_INFO) || defined(CONFIG_DEBUG_INFO) */
 
 	*--pInitialThread = (unsigned long)_thread_entry;
 
-#endif /* CONFIG_GDB_INFO */
+#endif /* defined(CONFIG_GDB_INFO) || defined(CONFIG_DEBUG_INFO) */
 
 	/*
 	 * note: stack area for edi, esi, ebx, ebp, and eax registers can be

arch/x86/core/offsets/offsets.c

@@ -46,6 +46,9 @@
 
 GEN_OFFSET_SYM(tNANO, nested);
 GEN_OFFSET_SYM(tNANO, common_isp);
+#ifdef CONFIG_DEBUG_INFO
+GEN_OFFSET_SYM(tNANO, isf);
+#endif
 #ifdef CONFIG_SYS_POWER_MANAGEMENT
 GEN_OFFSET_SYM(tNANO, idle);
 #endif

arch/x86/debug/Makefile

@@ -0,0 +1,3 @@
+ccflags-y += -I$(srctree)/kernel/nanokernel/include
+
+obj-$(CONFIG_GDB_SERVER) = gdb_arch.o gdb_dbg_regs.o gdb_arch_exc.o

arch/x86/debug/gdb_arch.c

@@ -0,0 +1,696 @@
+/*
+ * Copyright (c) 2015-2016 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * x86 part of the GDB server
+ */
+
+#include <nanokernel.h>
+#include <nano_private.h>
+#include <string.h>
+#include <debug/gdb_arch.h>
+#include <misc/debug/gdb_server.h>
+#include <asmPrv.h>
+
+#define TRACE_FLAG	0x0100 /* EFLAGS:TF */
+#define INT_FLAG	0x0200 /* EFLAGS:IF */
+
+#define INSTRUCTION_HLT 0xf4
+#define INSTRUCTION_STI 0xfb
+#define INSTRUCTION_CLI 0xfa
+
+#ifdef GDB_ARCH_HAS_RUNCONTROL
+#ifdef GDB_ARCH_HAS_HW_BP
+static int gdb_hw_bp_find(struct gdb_debug_regs *regs,
+			  enum gdb_bp_type *bp_type,
+			  long *address);
+#endif
+#endif
+
+/**
+ * @brief Initialize GDB server architecture part
+ *
+ * This routine initializes the architecture part of the GDB server.
+ *
+ * Does nothing currently.
+ *
+ * @return N/A
+ */
+
+void gdb_arch_init(void)
+{
+	/* currently empty */
+}
+
+/**
+ * @brief Fill a GDB register set from a given ESF register set
+ *
+ * This routine fills the provided GDB register set with values from given
+ * NANO_ESF register set.
+ *
+ * @param regs Destination GDB register set to fill
+ * @param esf Source exception stack frame
+ *
+ * @return N/A
+ */
+
+void gdb_arch_regs_from_esf(struct gdb_reg_set *regs, NANO_ESF *esf)
+{
+	regs->regs.eax = esf->eax;
+	regs->regs.ecx = esf->ecx;
+	regs->regs.edx = esf->edx;
+	regs->regs.ebx = esf->ebx;
+	regs->regs.esp = esf->esp;
+	regs->regs.ebp = esf->ebp;
+	regs->regs.esi = esf->esi;
+	regs->regs.edi = esf->edi;
+	regs->regs.eip = esf->eip;
+	regs->regs.eflags = esf->eflags;
+	regs->regs.cs = esf->cs;
+}
+
+/**
+ * @brief Fill a GDB register set from a given ISF register set
+ *
+ * This routine fills the provided GDB register set with values from given
+ * NANO_ISF register set.
+ *
+ * @param regs Destination GDB register set to fill
+ * @param isf Source interrupt stack frame
+ *
+ * @return N/A
+ */
+
+void gdb_arch_regs_from_isf(struct gdb_reg_set *regs, NANO_ISF *isf)
+{
+	memcpy(&regs->regs, isf, sizeof(regs->regs));
+}
+
+/**
+ * @brief Fill an ESF register set from a given GDB register set
+ *
+ * This routine fills the provided NANO_ESF register set with values
+ * from given GDB register set.
+ *
+ * @param regs Source GDB register set
+ * @param esf Destination exception stack frame to fill
+ *
+ * @return N/A
+ */
+
+void gdb_arch_regs_to_esf(struct gdb_reg_set *regs, NANO_ESF *esf)
+{
+	esf->eax = regs->regs.eax;
+	esf->ecx = regs->regs.ecx;
+	esf->edx = regs->regs.edx;
+	esf->ebx = regs->regs.ebx;
+	esf->esp = regs->regs.esp;
+	esf->ebp = regs->regs.ebp;
+	esf->esi = regs->regs.esi;
+	esf->edi = regs->regs.edi;
+	esf->eip = regs->regs.eip;
+	esf->eflags = regs->regs.eflags;
+	esf->cs = regs->regs.cs;
+}
+
+/**
+ * @brief Fill an ISF register set from a given GDB register set
+ *
+ * This routine fills the provided NANO_ISF register set with values
+ * from given GDB register set.
+ *
+ * @param regs Source GDB register set
+ * @param isf Destination interrupt stack frame to fill
+ *
+ * @return N/A
+ */
+
+void gdb_arch_regs_to_isf(struct gdb_reg_set *regs, NANO_ISF *isf)
+{
+	memcpy(isf, &regs->regs, sizeof(NANO_ISF));
+}
+
+/**
+ * @brief Fill given buffer from given register set
+ *
+ * This routine fills the provided buffer with values from given register set.
+ *
+ * The provided buffer must be large enough to store all register values.
+ * It is up to the caller to do this check.
+ *
+ * @param regs Source GDB register set
+ * @param esf Destination buffer to fill
+ *
+ * @return N/A
+ */
+
+void gdb_arch_regs_get(struct gdb_reg_set *regs, char *buffer)
+{
+	*((uint32_t *) buffer) = regs->regs.eax;
+	buffer += 4;
+	*((uint32_t *) buffer) = regs->regs.ecx;
+	buffer += 4;
+	*((uint32_t *) buffer) = regs->regs.edx;
+	buffer += 4;
+	*((uint32_t *) buffer) = regs->regs.ebx;
+	buffer += 4;
+	*((uint32_t *) buffer) = regs->regs.esp;
+	buffer += 4;
+	*((uint32_t *) buffer) = regs->regs.ebp;
+	buffer += 4;
+	*((uint32_t *) buffer) = regs->regs.esi;
+	buffer += 4;
+	*((uint32_t *) buffer) = regs->regs.edi;
+	buffer += 4;
+	*((uint32_t *) buffer) = (uint32_t) regs->regs.eip;
+	buffer += 4;
+	*((uint32_t *) buffer) = regs->regs.eflags;
+	buffer += 4;
+	*((uint32_t *) buffer) = regs->regs.cs;
+}
+
+/**
+ * @brief Write given registers buffer to GDB register set
+ *
+ * This routine fills given register set with value from provided buffer.
+ * The provided buffer must be large enough to contain all register values.
+ * It is up to the caller to do this check.
+ *
+ * @param regs Destination GDB register set to fill
+ * @param esf Source buffer
+ *
+ * @return N/A
+ */
+
+void gdb_arch_regs_set(struct gdb_reg_set *regs, char *buffer)
+{
+	regs->regs.eax = *((uint32_t *)buffer);
+	buffer += 4;
+	regs->regs.ecx = *((uint32_t *)buffer);
+	buffer += 4;
+	regs->regs.edx = *((uint32_t *)buffer);
+	buffer += 4;
+	regs->regs.ebx = *((uint32_t *)buffer);
+	buffer += 4;
+	regs->regs.esp = *((uint32_t *)buffer);
+	buffer += 4;
+	regs->regs.ebp = *((uint32_t *)buffer);
+	buffer += 4;
+	regs->regs.esi = *((uint32_t *)buffer);
+	buffer += 4;
+	regs->regs.edi = *((uint32_t *)buffer);
+	buffer += 4;
+	regs->regs.eip = *((uint32_t *)buffer);
+	buffer += 4;
+	regs->regs.eflags = *((uint32_t *)buffer);
+	buffer += 4;
+	regs->regs.cs = *((uint32_t *)buffer);
+}
+
+/**
+ * @brief Get size and offset of given register
+ *
+ * This routine returns size and offset of given register.
+ *
+ * @param reg_id Register identifier
+ * @param size Container to return size of register, in bytes
+ * @param offset Container to return offset of register, in bytes
+ *
+ * @return N/A
+ */
+
+void gdb_arch_reg_info_get(int reg_id, int *size, int *offset)
+{
+	/* Determine register size and offset */
+	if (reg_id >= 0 && reg_id < GDB_NUM_REGS) {
+		*size = 4;
+		*offset = 4 * reg_id;
+	}
+}
+
+#ifdef GDB_ARCH_HAS_RUNCONTROL
+#ifdef GDB_ARCH_HAS_HW_BP
+/**
+ * @brief Get the HW breakpoint architecture type for a common GDB type
+ *
+ * This routine gets the specific architecture value that corresponds to a
+ * common hardware breakpoint type.
+ *
+ * The values accepted for the @a type are GDB_HW_INST_BP,
+ * GDB_HW_DATA_WRITE_BP, GDB_HW_DATA_ACCESS_BP and GDB_HW_DATA_READ_BP.
+ *
+ * @param type Common GDB breakpoint type
+ * @param len Data length
+ * @param err Error code on failure (return value of -1)
+ *
+ * @return The architecture type, -1 on failure
+ */
+
+static char gdb_hw_bp_type_get(enum gdb_bp_type type, int len,
+				enum gdb_error_code *err)
+{
+	char hw_type = -1;
+
+	switch (type) {
+		/* Following combinations are supported on IA */
+	case GDB_HW_INST_BP:
+		hw_type = 0;
+		break;
+	case GDB_HW_DATA_WRITE_BP:
+		if (len == 1) {
+			hw_type = 0x1;
+		} else if (len == 2) {
+			hw_type = 0x5;
+		} else if (len == 4) {
+			hw_type = 0xd;
+		} else if (len == 8) {
+			hw_type = 0x9;
+		}
+		break;
+	case GDB_HW_DATA_ACCESS_BP:
+		if (len == 1) {
+			hw_type = 0x3;
+		} else if (len == 2) {
+			hw_type = 0x7;
+		} else if (len == 4) {
+			hw_type = 0xf;
+		} else if (len == 8) {
+			hw_type = 0xb;
+		}
+		break;
+	case GDB_HW_DATA_READ_BP:
+		/* Data read not supported on IA */
+		/*
+		 * NOTE: Read only watchpoints are not supported by IA debug
+		 * registers, but it could be possible to use RW watchpoints
+		 * and ignore the RW watchpoint if it has been hit by a write
+		 * operation.
+		 */
+		*err = GDB_ERROR_HW_BP_NOT_SUP;
+		return -1;
+	default:
+		/* Unknown type */
+		*err = GDB_ERROR_HW_BP_INVALID_TYPE;
+		return -1;
+	}
+	return hw_type;
+}
+
+/**
+ * @brief Set the debug registers for a specific HW BP.
+ *
+ * This routine sets the @a regs debug registers according to the HW breakpoint
+ * description.
+ *
+ * @param regs Debug registers to set
+ * @param addr Address of the breakpoint
+ * @param type Common GDB breakpoint type
+ * @param len Data length
+ * @param err Error code on failure (return value of -1)
+ *
+ * @return 0 if debug registers have been modified, -1 on error
+ */
+
+int gdb_hw_bp_set(struct gdb_debug_regs *regs, long addr,
+		  enum gdb_bp_type type,
+		  int len, enum gdb_error_code *err)
+{
+	char hw_type;
+
+	hw_type = gdb_hw_bp_type_get(type, len, err);
+	if (hw_type < 0) {
+		return -1;
+	}
+
+	if (regs->db0 == 0) {
+		regs->db0 = addr;
+		regs->db7 |= (hw_type << 16) | 0x02;
+	} else if (regs->db1 == 0) {
+		regs->db1 = addr;
+		regs->db7 |= (hw_type << 20) | 0x08;
+	} else if (regs->db2 == 0) {
+		regs->db2 = addr;
+		regs->db7 |= (hw_type << 24) | 0x20;
+	} else if (regs->db3 == 0) {
+		regs->db3 = addr;
+		regs->db7 |= (hw_type << 28) | 0x80;
+	} else {
+		*err = GDB_ERROR_HW_BP_DBG_REGS_FULL;
+		return -1;
+	}
+
+	/* set GE bit if it is data breakpoint */
+	if (hw_type != 0) {
+		regs->db7 |= 0x200;
+	}
+	return 0;
+}
+
+/**
+ * @brief Clear the debug registers for a specific HW BP.
+ *
+ * This routine updates the @a regs debug registers to remove a HW breakpoint.
+ *
+ * @param regs Debug registers to clear
+ * @param addr Address of the breakpoint
+ * @param type Common GDB breakpoint type
+ * @param len Data length
+ * @param err Error code on failure (return value of -1)
+ *
+ * @return 0 if debug registers have been modified, -1 on error
+ */
+
+int gdb_hw_bp_clear(struct gdb_debug_regs *regs, long addr,
+		    enum gdb_bp_type type, int len,
+		    enum gdb_error_code *err)
+{
+	char hw_type;
+
+	hw_type = gdb_hw_bp_type_get(type, len, err);
+	if (hw_type < 0) {
+		return -1;
+	}
+
+	if ((regs->db0 == addr) && (((regs->db7 >> 16) & 0xf) == hw_type)) {
+		regs->db0 = 0;
+		regs->db7 &= ~((hw_type << 16) | 0x02);
+	} else if ((regs->db1 == addr)
+		   && (((regs->db7 >> 20) & 0xf) == hw_type)) {
+		regs->db1 = 0;
+		regs->db7 &= ~((hw_type << 20) | 0x08);
+	} else if ((regs->db2 == addr)
+		   && (((regs->db7 >> 24) & 0xf) == hw_type)) {
+		regs->db2 = 0;
+		regs->db7 &= ~((hw_type << 24) | 0x20);
+	} else if ((regs->db3 == addr)
+		   && (((regs->db7 >> 28) & 0xf) == hw_type)) {
+		regs->db3 = 0;
+		regs->db7 &= ~((hw_type << 28) | 0x80);
+	} else {
+		/* Unknown breakpoint */
+		*err = GDB_ERROR_INVALID_BP;
+		return -1;
+	}
+	return 0;
+}
+
+/**
+ * @brief Look for a Hardware breakpoint
+ *
+ * This routine checks from the @a regs debug register set if a hardware
+ * breakpoint has been hit.
+ *
+ * @param regs Debug registers to check
+ * @param bp_type Common GDB breakpoint type
+ * @param address Address of the breakpoint
+ *
+ * @return 0 if a HW BP has been found, -1 otherwise
+ */
+
+static int gdb_hw_bp_find(struct gdb_debug_regs *regs,
+			  enum gdb_bp_type *bp_type,
+			  long *address)
+{
+	int ix;
+	unsigned char type = 0;
+	long addr = 0;
+	int status_bit;
+	int enable_bit;
+
+	/* get address and type of breakpoint from DR6 and DR7 */
+	for (ix = 0; ix < 4; ix++) {
+		status_bit = 1 << ix;
+		enable_bit = 2 << (ix << 1);
+
+		if ((regs->db6 & status_bit) && (regs->db7 & enable_bit)) {
+			switch (ix) {
+			case 0:
+				addr = regs->db0;
+				type = (regs->db7 & 0x000f0000) >> 16;
+				break;
+
+			case 1:
+				addr = regs->db1;
+				type = (regs->db7 & 0x00f00000) >> 20;
+				break;
+
+			case 2:
+				addr = regs->db2;
+				type = (regs->db7 & 0x0f000000) >> 24;
+				break;
+
+			case 3:
+				addr = regs->db3;
+				type = (regs->db7 & 0xf0000000) >> 28;
+				break;
+			}
+		}
+	}
+
+	if ((addr == 0) && (type == 0))
+		return -1;
+
+	*address = addr;
+	switch (type) {
+	case 0x1:
+	case 0x5:
+	case 0xd:
+	case 0x9:
+		*bp_type = GDB_HW_DATA_WRITE_BP;
+		break;
+	case 0x3:
+	case 0x7:
+	case 0xf:
+	case 0xb:
+		*bp_type = GDB_HW_DATA_ACCESS_BP;
+		break;
+	default:
+		*bp_type = GDB_HW_INST_BP;
+		break;
+	}
+	return 0;
+}
+
+/**
+ * @brief Clear all debug registers.
+ *
+ * This routine clears all debug registers
+ *
+ * @return N/A
+ */
+
+void gdb_dbg_regs_clear(void)
+{
+	struct gdb_debug_regs regs;
+
+	regs.db0 = 0;
+	regs.db1 = 0;
+	regs.db2 = 0;
+	regs.db3 = 0;
+	regs.db6 = 0;
+	regs.db7 = 0;
+	gdb_dbg_regs_set(&regs);
+}
+#endif /* GDB_ARCH_HAS_HW_BP */
+
+/**
+ * @brief Clear trace mode
+ *
+ * This routine makes CPU trace-disabled.
+ *
+ * @param regs GDB register set to modify.
+ * @param arg Interrupt locking key
+ *
+ * @return N/A
+ */
+
+void gdb_trace_mode_clear(struct gdb_reg_set *regs, int arg)
+{
+	regs->regs.eflags &= ~INT_FLAG;
+	regs->regs.eflags |= (arg & INT_FLAG);
+	regs->regs.eflags &= ~TRACE_FLAG;
+}
+
+/**
+ * @brief Test if single stepping is possible for current program counter
+ *
+ * @param regs GDB register set to fetch PC from.
+ *
+ * @return 1 if it is possible to step the instruction, 0 otherwise
+ */
+
+int gdb_arch_can_step(struct gdb_reg_set *regs)
+{
+	unsigned char *pc = (unsigned char *)regs->regs.eip;
+
+	if (*pc == INSTRUCTION_HLT) {
+		return 0;
+	}
+
+	return 1;
+}
+
+/**
+ * @brief Set trace mode
+ *
+ * This routine makes CPU trace-enabled.
+ *
+ * In the event that the program counter currently points to a sti or a cli
+ * instruction, the returned eflags will contain an IF bit as if that
+ * instruction had executed (set for sti, cleared for cli).
+ *
+ * @param regs GDB register set to modify.
+ *
+ * @return eflags with IF bit possibly modified by current sti/cli instruction.
+ */
+
+int gdb_trace_mode_set(struct gdb_reg_set *regs)
+{
+	unsigned char *pc = (unsigned char *)regs->regs.eip;
+	int simulated_eflags = regs->regs.eflags;
+
+	if (*pc == INSTRUCTION_STI) {
+		simulated_eflags |= INT_FLAG;
+	}
+
+	if (*pc == INSTRUCTION_CLI) {
+		simulated_eflags &= ~INT_FLAG;
+	}
+
+	regs->regs.eflags &= ~INT_FLAG;
+	regs->regs.eflags |= TRACE_FLAG;
+
+	return simulated_eflags;
+}
+
+#ifdef GDB_ARCH_HAS_HW_BP
+/**
+ * @brief Implementation of GDB trace handler for HW breakpoint support
+ *
+ * @param esf Exception stack frame when taking the exception
+ *
+ * @return N/A
+ */
+
+static void _do_gdb_trace_handler(NANO_ESF *esf)
+{
+	struct gdb_debug_regs regs;
+
+	gdb_dbg_regs_get(&regs);
+	if ((regs.db6 & 0x00004000) == 0x00004000) {
+		gdb_handler(GDB_EXC_TRACE, esf, GDB_SIG_TRAP);
+	} else {
+		int type;
+		long addr;
+
+		gdb_dbg_regs_clear();
+		(void)gdb_hw_bp_find(&regs, &type, &addr);
+		gdb_cpu_stop_hw_bp_addr = addr;
+		gdb_cpu_stop_bp_type = type;
+		gdb_debug_status = DEBUGGING;
+		gdb_handler(GDB_EXC_BP, esf, GDB_SIG_TRAP);
+	}
+}
+#else
+/**
+ * @brief Implementation of GDB trace handler for SW breakpoint support
+ *
+ * @param esf Exception stack frame when taking the exception
+ *
+ * @return N/A
+ */
+
+static void _do_gdb_trace_handler(NANO_ESF *esf)
+{
+	gdb_handler(GDB_EXC_TRACE, esf, GDB_SIG_TRAP);
+}
+#endif
+
+/**
+ * @brief GDB trace handler
+ *
+ * The GDB trace handler is used to catch and handle the trace mode exceptions
+ * (single step).
+ *
+ * @param esf Exception stack frame when taking the exception
+ *
+ * @return N/A
+ */
+
+void gdb_trace_handler(NANO_ESF *esf)
+{
+	(void)irq_lock();
+	_do_gdb_trace_handler(esf);
+}
+
+/**
+ * @brief GDB breakpoint handler
+ *
+ * The GDB breakpoint handler is used to catch and handle the breakpoint
+ * exceptions.
+ *
+ * @param esf Exception stack frame when taking the exception
+ *
+ * @return N/A
+ */
+
+void gdb_bp_handler(NANO_ESF *esf)
+{
+	(void)irq_lock();
+
+	gdb_debug_status = DEBUGGING;
+	GDB_SET_STOP_BP_TYPE_SOFT(GDB_SOFT_BP);
+	esf->eip -= sizeof(gdb_instr_t);
+
+	gdb_handler(GDB_EXC_BP, esf, GDB_SIG_TRAP);
+}
+
+/**
+ * @brief GDB division-by-zero handler
+ *
+ * This GDB handler is used to catch and handle the division-by-zero exception.
+ *
+ * @param esf Exception stack frame when taking the exception
+ *
+ * @return N/A
+ */
+
+void gdb_div_by_zero_handler(NANO_ESF *esf)
+{
+	(void)irq_lock();
+	gdb_debug_status = DEBUGGING;
+	gdb_handler(GDB_EXC_OTHER, esf, GDB_SIG_FPE);
+}
+
+/**
+ * @brief GDB page fault handler
+ *
+ * This GDB handler is used to catch and handle the page fault exceptions.
+ *
+ * @param esf Exception stack frame when taking the exception
+ *
+ * @return N/A
+ */
+
+void gdb_pfault_handler(NANO_ESF *esf)
+{
+	(void)irq_lock();
+	gdb_debug_status = DEBUGGING;
+	gdb_handler(GDB_EXC_OTHER, esf, GDB_SIG_SIGSEGV);
+}
+
+#endif /* GDB_ARCH_HAS_RUNCONTROL */

arch/x86/debug/gdb_arch_exc.S

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2015-2016 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * Hooking of exception handlers.
+ */
+
+#define _ASMLANGUAGE
+
+#include <arch/x86/asm.h>
+#include <arch/x86/arch.h>
+#include <asmPrv.h>
+#include <debug/gdb_arch.h>
+
+#ifdef GDB_ARCH_HAS_RUNCONTROL
+
+	GTEXT(gdb_bp_handler)
+	GTEXT(gdb_trace_handler)
+	GTEXT(gdb_div_by_zero_handler)
+	GTEXT(gdb_pfault_handler)
+
+NANO_CPU_EXC_CONNECT_NO_ERR(gdb_div_by_zero_handler, IV_DIVIDE_ERROR, 0);
+NANO_CPU_EXC_CONNECT_NO_ERR(gdb_trace_handler, IV_DEBUG, 0);
+NANO_CPU_EXC_CONNECT_NO_ERR(gdb_bp_handler, IV_BREAKPOINT, 0);
+NANO_CPU_EXC_CONNECT(gdb_pfault_handler, IV_PAGE_FAULT, 0);
+
+#endif

arch/x86/debug/gdb_dbg_regs.S

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2015 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ *
+ * This module provides the implementation of the gdb_dbg_regs_set/get()
+ * utilities.
+ */
+
+#define _ASMLANGUAGE
+
+#include <arch/x86/asm.h>
+
+	/* exports (internal APIs) */
+
+	GTEXT(gdb_dbg_regs_set)
+	GTEXT(gdb_dbg_regs_get)
+
+/**
+ * @brief Write debug registers
+ *
+ * This function is used to write to debug registers
+ *
+ * C function prototype:
+ *
+ *   void gdb_dbg_regs_set (struct gdb_debug_regs * regs);
+ *
+ * @return N/A
+ */
+
+SECTION_FUNC(TEXT, gdb_dbg_regs_set)
+    movl    SP_ARG1(%esp),%edx
+    movl    0(%edx),%eax
+    movl    %eax,%db0
+    movl    4(%edx),%eax
+    movl    %eax,%db1
+    movl    8(%edx),%eax
+    movl    %eax,%db2
+    movl    12(%edx),%eax
+    movl    %eax,%db3
+    movl    16(%edx),%eax
+    movl    %eax,%db6
+    movl    20(%edx),%eax
+    movl    %eax,%db7
+    ret
+
+/**
+ * @brief Read debug registers
+ *
+ * This function is used to read debug registers
+ *
+ * C function prototype:
+ *
+ *   void gdb_dbg_regs_get (struct gdb_debug_regs * regs);
+ *
+ * @return N/A
+ */
+
+SECTION_FUNC(TEXT, gdb_dbg_regs_get)
+    movl    SP_ARG1(%esp),%edx
+    movl    %db0,%eax
+    movl    %eax,0(%edx)
+    movl    %db1,%eax
+    movl    %eax,4(%edx)
+    movl    %db2,%eax
+    movl    %eax,8(%edx)
+    movl    %db3,%eax
+    movl    %eax,12(%edx)
+    movl    %db6,%eax
+    movl    %eax,16(%edx)
+    movl    %db7,%eax
+    movl    %eax,20(%edx)
+    ret

arch/x86/include/debug/gdb_arch.h

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2015 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _GDB_ARCH__H_
+#define _GDB_ARCH__H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <nano_private.h>
+#include <misc/debug/gdb_server.h>
+
+#define GDB_ARCH_HAS_ALL_REGS
+
+#ifndef CONFIG_GDB_SERVER_BOOTLOADER
+	#undef  GDB_ARCH_HAS_HW_BP
+	#define GDB_ARCH_HAS_REMOTE_SERIAL_EXT_USING_NOTIF_PACKETS
+	#define GDB_ARCH_HAS_RUNCONTROL
+	#define GDB_ARCH_CAN_STEP gdb_arch_can_step
+#endif
+
+#ifndef CONFIG_GDB_RAM_SIZE
+	#define CONFIG_GDB_RAM_SIZE (CONFIG_RAM_SIZE * 1024)
+#endif
+#ifndef CONFIG_GDB_RAM_ADDRESS
+	#define CONFIG_GDB_RAM_ADDRESS 0x100000
+#endif
+
+/* Default GDB buffer size */
+#ifdef CONFIG_GDB_SERVER_BOOTLOADER
+	#define GDB_BUF_SIZE 8192
+#else
+	#define GDB_BUF_SIZE  600
+#endif
+
+#define GDB_TGT_ARCH "i386"
+
+#define GDB_NUM_REGS 16
+#define GDB_NUM_REG_BYTES (GDB_NUM_REGS * 4)
+
+#define GDB_PC_REG 8
+
+#define GDB_BREAK_INSTRUCTION 0xcc /* 'int3' opcode */
+
+#ifndef _ASMLANGUAGE
+
+typedef unsigned char gdb_instr_t;
+
+struct gdb_reg_set {
+	NANO_ISF regs;
+	unsigned int pad1; /* padding for ss register */
+	unsigned int pad2; /* padding for ds register */
+	unsigned int pad3; /* padding for es register */
+	unsigned int pad4; /* padding for fs register */
+	unsigned int pad5; /* padding for gs register */
+};
+
+struct gdb_debug_regs {
+	unsigned int db0; /* debug register 0 */
+	unsigned int db1; /* debug register 1 */
+	unsigned int db2; /* debug register 2 */
+	unsigned int db3; /* debug register 3 */
+	unsigned int db6; /* debug register 6 */
+	unsigned int db7; /* debug register 7 */
+};
+
+#if defined(GDB_ARCH_HAS_RUNCONTROL) && defined(GDB_ARCH_HAS_HW_BP)
+extern volatile int gdb_cpu_stop_bp_type;
+extern long gdb_cpu_stop_hw_bp_addr;
+#define GDB_SET_STOP_BP_TYPE_SOFT(x) \
+	do { gdb_cpu_stop_bp_type = (x); } while ((0))
+#else
+#define GDB_SET_STOP_BP_TYPE_SOFT(x)
+#endif
+
+extern void gdb_arch_init(void);
+extern void gdb_arch_regs_from_esf(struct gdb_reg_set *regs,
+				   NANO_ESF *esf);
+extern void gdb_arch_regs_to_esf(struct gdb_reg_set *regs,
+				 NANO_ESF *esf);
+extern void gdb_arch_regs_from_isf(struct gdb_reg_set *regs,
+				   NANO_ISF *esf);
+extern void gdb_arch_regs_to_isf(struct gdb_reg_set *regs,
+				 NANO_ISF *esf);
+extern void gdb_arch_regs_get(struct gdb_reg_set *regs, char *buffer);
+extern void gdb_arch_regs_set(struct gdb_reg_set *regs, char *buffer);
+extern void gdb_arch_reg_info_get(int reg_id, int *size, int *offset);
+extern void gdb_trace_mode_clear(struct gdb_reg_set *regs, int arg);
+extern int gdb_trace_mode_set(struct gdb_reg_set *regs);
+extern int gdb_arch_can_step(struct gdb_reg_set *regs);
+#ifdef GDB_ARCH_HAS_HW_BP
+extern int gdb_hw_bp_set(struct gdb_debug_regs *regs, long addr,
+			 enum gdb_bp_type type, int length,
+			 enum gdb_error_code *err);
+extern int gdb_hw_bp_clear(struct gdb_debug_regs *regs, long addr,
+			   enum gdb_bp_type type, int length,
+			   enum gdb_error_code *err);
+extern void gdb_dbg_regs_set(struct gdb_debug_regs *regs);
+extern void gdb_dbg_regs_get(struct gdb_debug_regs *regs);
+extern void gdb_dbg_regs_clear(void);
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _GDB_ARCH__H_ */

arch/x86/include/nano_private.h

@@ -710,6 +710,10 @@ typedef struct s_NANO {
 	unsigned nested;  /* nested interrupt count */
 	char *common_isp; /* interrupt stack pointer base */
 
+#if defined(CONFIG_DEBUG_INFO)
+	NANO_ISF *isf;    /* ptr to interrupt stack frame */
+#endif
+
 #ifdef CONFIG_SYS_POWER_MANAGEMENT
 	int32_t idle; /* Number of ticks for kernel idling */
 #endif

arch/x86/soc/atom/Kconfig.defconfig

@@ -94,4 +94,7 @@ config UART_PIPE_ON_DEV_NAME
 
 endif
 
+config BLUETOOTH_MONITOR_ON_DEV_NAME
+	default "UART_1" if BLUETOOTH_DEBUG_MONITOR
+
 endif

arch/x86/soc/ia32/Kconfig.defconfig

@@ -87,6 +87,13 @@ config BLUETOOTH_UART_ON_DEV_NAME
 
 endif
 
+if NBLE
+
+config NBLE_UART_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
 if UART_PIPE
 
 config UART_PIPE_ON_DEV_NAME
@@ -94,4 +101,7 @@ config UART_PIPE_ON_DEV_NAME
 
 endif
 
+config BLUETOOTH_MONITOR_ON_DEV_NAME
+	default "UART_1" if BLUETOOTH_DEBUG_MONITOR
+
 endif

arch/x86/soc/ia32/Makefile

@@ -1,6 +1,10 @@
 ifeq ($(CONFIG_X86_IAMCU),y)
+LD_TOOLCHAIN ?= -D__GCC_LINKER_CMD__ -D__IAMCU
+OUTPUT_FORMAT = elf32-iamcu
+OUTPUT_ARCH = iamcu:intel
 KBUILD_CFLAGS += $(call cc-option,-msoft-float)
 endif
+
 KBUILD_CFLAGS += $(call cc-option,-march=pentium)
 KBUILD_CXXFLAGS += $(call cc-option,-march=pentium)
 KBUILD_AFLAGS += $(KBUILD_CFLAGS)

arch/x86/soc/quark_d2000/Kconfig.defconfig

@@ -52,60 +52,19 @@ config PHYS_RAM_ADDR
 config TOOLCHAIN_VARIANT
         default "iamcu"
 
-if UART_NS16550
-
-config UART_NS16550_DLF
+config QMSI
 	def_bool y
 
-config UART_NS16550_PORT_0
+config QMSI_BUILTIN
 	def_bool y
 
-if UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_0_NAME
-	default "UART_0"
-config UART_NS16550_PORT_0_IRQ_PRI
-	default 3
-config UART_NS16550_PORT_0_BAUD_RATE
-	default 115200
-config UART_NS16550_PORT_0_OPTIONS
-	default 0
-config UART_NS16550_PORT_0_DLF
-	default 0x06
-
-endif # UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_1
-	def_bool y
-
-if UART_NS16550_PORT_1
-
-config UART_NS16550_PORT_1_NAME
-	default "UART_1"
-config UART_NS16550_PORT_1_IRQ_PRI
-	default 3
-config UART_NS16550_PORT_1_BAUD_RATE
-	default 115200
-config UART_NS16550_PORT_1_OPTIONS
-	default 0
-config UART_NS16550_PORT_1_DLF
-	default 0x06
-
-endif # UART_NS16550_PORT_1
-
-endif # UART_NS16550
-
 if UART_QMSI
 config UART_QMSI_0
 	def_bool y
-config UART_QMSI_0_IRQ
-	default 8
 config UART_QMSI_0_IRQ_PRI
 	default 0
 config UART_QMSI_1
 	def_bool y
-config UART_QMSI_1_IRQ
-	default 6
 config UART_QMSI_1_IRQ_PRI
 	default 0
 endif # UART_QMSI
@@ -124,72 +83,49 @@ config UART_PIPE_ON_DEV_NAME
 
 endif
 
+config BLUETOOTH_MONITOR_ON_DEV_NAME
+	default "UART_1" if BLUETOOTH_DEBUG_MONITOR
+
 if WATCHDOG
-config WDT_DW
+config WDT_QMSI
 	def_bool y
 
-if WDT_DW
-config WDT_DW_IRQ_PRI
-	default 0
-endif # WDT_DW
-
-if WDT_QMSI
-config WDT_QMSI_IRQ
-	default 16
 config WDT_QMSI_IRQ_PRI
 	default 0
-endif # WDT_QMSI
 endif # WATCHDOG
 
 if RTC
+config RTC_QMSI
+	def_bool y
 
-if RTC_QMSI
-config RTC_QMSI_IRQ
-	default 2
 config RTC_QMSI_IRQ_PRI
 	default 0
-endif # RTC_QMSI
-
-config RTC_DW
-	def_bool y
-config RTC_DW_IRQ_PRI
-	default 0 if RTC_DW
 
 endif # RTC
 
-if I2C
 
-config I2C_DW
+if GPIO
+
+config GPIO_QMSI
 	def_bool y
+config GPIO_QMSI_0
+	def_bool y
+config GPIO_QMSI_0_PRI
+	default 0
+endif # GPIO
 
-if I2C_DW
-
-config I2C_DW_0
+if PWM
+config PWM_QMSI
         def_bool y
+endif
 
-if I2C_DW_0
-
-config I2C_DW_0_NAME
-        default "I2C0"
-
-config I2C_DW_0_IRQ_PRI
-        default 0
-
-config I2C_DW_0_DEFAULT_CFG
-        default 0x12
-
-config I2C_CLOCK_SPEED
-        default 32
-
-endif # I2C_DW_0
-
-endif # I2C_DW
+if I2C
+config I2C_QMSI
+	def_bool y
 
 if I2C_QMSI
 config I2C_QMSI_0
 	def_bool y
-config I2C_QMSI_0_IRQ
-	default 4
 config I2C_QMSI_0_IRQ_PRI
 	default 0
 config I2C_QMSI_0_DEFAULT_CFG
@@ -197,29 +133,38 @@ config I2C_QMSI_0_DEFAULT_CFG
 endif # I2C_QMSI
 endif # I2C
 
-if GPIO_QMSI
-config GPIO_QMSI_0
-	def_bool y
-config GPIO_QMSI_0_IRQ
-	default 15
-config GPIO_QMSI_0_PRI
-	default 0
-endif # GPIO_QMSI
 
-if SPI_QMSI
-config SPI_QMSI_PORT_0
+if AIO_COMPARATOR
+config AIO_QMSI_COMPARATOR
 	def_bool y
-config SPI_QMSI_PORT_0_IRQ
-	default 7
-config SPI_QMSI_PORT_0_PRI
-	default 0
-endif # SPI_QMSI
+endif
 
-if AON_TIMER_QMSI
-config AON_TIMER_IRQ
-	default 3
+if COUNTER
+config AON_COUNTER_QMSI
+	def_bool y
+config AON_TIMER_QMSI
+	def_bool y
 config AON_TIMER_IRQ_PRI
 	default 0
-endif # AON_TIMER_QMSI
+endif
+
+if ADC
+config ADC_QMSI
+	def_bool y
+endif
+
+if SPI
+config SPI_QMSI
+	def_bool y
+config SPI_QMSI_PORT_0
+	def_bool y
+config SPI_QMSI_PORT_0_PRI
+	default 0
+endif # SPI
+
+if SOC_FLASH_QMSI
+config SOC_FLASH_QMSI_SYS_SIZE
+	default 0x8000
+endif # SOC_FLASH_QMSI
 
 endif # SOC_QUARK_D2000

arch/x86/soc/quark_d2000/Makefile

@@ -1,7 +1,14 @@
+ifeq ($(COMPILER),clang)
+arch-cflags = $(call cc-option,-msoft-float, -march=pentium)
+else
 arch-cflags = $(call cc-option,-march=lakemont -mtune=lakemont -msoft-float, -march=pentium)
+endif
 
 ifeq ($(CONFIG_X86_IAMCU),y)
 arch-cflags += $(call cc-option,-miamcu)
+LD_TOOLCHAIN ?= -D__GCC_LINKER_CMD__ -D__IAMCU
+OUTPUT_FORMAT = elf32-iamcu
+OUTPUT_ARCH = iamcu:intel
 else
 arch-cflags += $(call cc-option,-mno-iamcu)
 endif

arch/x86/soc/quark_d2000/soc.c

@@ -23,47 +23,10 @@
  */
 
 #include <nanokernel.h>
-#include <arch/cpu.h>
-#include <misc/printk.h>
-#include <misc/__assert.h>
 #include "soc.h"
 #include <drivers/mvic.h>
 #include <init.h>
 
-/**
- *
- * _InitHardware - perform basic hardware initialization
- *
- * Initialize the Quark D2000 Interrupt Controller (MVIC) device driver and the
- * Intel 8250 UART device driver.
- * Also initialize the timer device driver, if required.
- *
- * RETURNS: N/A
- */
-static int quark_d2000_init(struct device *arg)
-{
-	ARG_UNUSED(arg);
-
-#ifdef CONFIG_UART_NS16550
-	/* enable clock gating */
-#ifdef CONFIG_UART_NS16550_PORT_0
-	sys_set_bit(CLOCK_PERIPHERAL_BASE_ADDR, 17);
-#endif
-#ifdef CONFIG_UART_NS16550_PORT_1
-	sys_set_bit(CLOCK_PERIPHERAL_BASE_ADDR, 18);
-#endif
-	sys_set_bit(CLOCK_PERIPHERAL_BASE_ADDR, 1);
-#endif /* CONFIG_UART_NS16550 */
-
-#ifdef CONFIG_I2C_DW_0
-	/* Unmask interrupt */
-	sys_clear_bit(I2C_MST_0_INT_MASK, 0);
-#endif
-
-	return 0;
-}
-SYS_INIT(quark_d2000_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
 #ifdef CONFIG_MVIC
 SYS_INIT(_mvic_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
 #endif /* CONFIG_IOAPIC */

arch/x86/soc/quark_d2000/soc.h

@@ -41,139 +41,20 @@
 #define CLOCK_SENSOR_BASE_ADDR		(SCSS_REGISTER_BASE + 0x28)
 #define CLOCK_SYSTEM_CLOCK_CONTROL      (SCSS_REGISTER_BASE + 0x38)
 
-struct scss_peripheral {
-	volatile uint32_t usb_phy_cfg0; /**< USB Configuration */
-	volatile uint32_t periph_cfg0;  /**< Peripheral Configuration */
-	volatile uint32_t reserved[2];
-	volatile uint32_t cfg_lock; /**< Configuration Lock */
-};
-
-struct int_ss_i2c {
-	volatile uint32_t err_mask;
-	volatile uint32_t rx_avail_mask;
-	volatile uint32_t tx_req_mask;
-	volatile uint32_t stop_det_mask;
-};
-
-struct int_ss_spi {
-	volatile uint32_t err_int_mask;
-	volatile uint32_t rx_avail_mask;
-	volatile uint32_t tx_req_mask;
-};
-
-
-struct scss_interrupt {
-	volatile uint32_t int_ss_adc_err_mask;
-	volatile uint32_t int_ss_adc_irq_mask;
-	volatile uint32_t int_ss_gpio_intr_mask[2];
-	struct int_ss_i2c int_ss_i2c[2];
-	struct int_ss_spi int_ss_spi[2];
-	volatile uint32_t int_i2c_mst_mask[2];
-	volatile uint32_t reserved;
-	volatile uint32_t int_spi_mst_mask[2];
-	volatile uint32_t int_spi_slv_mask[1];
-	volatile uint32_t int_uart_mask[2];
-	volatile uint32_t int_i2s_mask;
-	volatile uint32_t int_gpio_mask;
-	volatile uint32_t int_pwm_timer_mask;
-	volatile uint32_t int_usb_mask;
-	volatile uint32_t int_rtc_mask;
-	volatile uint32_t int_watchdog_mask;
-	volatile uint32_t int_dma_channel_mask[8];
-	volatile uint32_t int_mailbox_mask;
-	volatile uint32_t int_comparators_ss_halt_mask;
-	volatile uint32_t int_comparators_host_halt_mask;
-	volatile uint32_t int_comparators_ss_mask;
-	volatile uint32_t int_comparators_host_mask;
-	volatile uint32_t int_host_bus_err_mask;
-	volatile uint32_t int_dma_error_mask;
-	volatile uint32_t int_sram_controller_mask;
-	volatile uint32_t int_flash_controller_mask[2];
-	volatile uint32_t int_aon_timer_mask;
-	volatile uint32_t int_adc_pwr_mask;
-	volatile uint32_t int_adc_calib_mask;
-	volatile uint32_t int_aon_gpio_mask;
-	volatile uint32_t lock_int_mask_reg;
-};
-
-#define SCSS_PERIPHERAL_BASE (0xB0800800)
-#define SCSS_PERIPHERAL ((struct scss_peripheral *)SCSS_PERIPHERAL_BASE)
-
-#define SCSS_INT_BASE (0xB0800400)
-#define SCSS_INTERRUPT ((struct scss_interrupt *)SCSS_INT_BASE)
-
-/* Peripheral Clock Gate Control */
-#define SCSS_CCU_PERIPH_CLK_GATE_CTL	0x18
-#define CCU_PERIPH_CLK_EN		(1 << 1)
-#define CCU_PERIPH_CLK_DIV_CTL0		0x1C
 #define INT_UNMASK_IA			(~0x00000001)
+
+
 /*
  * Local APIC (LOAPIC) device information (Intel loapic)
  */
-
 #define LOAPIC_IRQ_BASE			CONFIG_LOAPIC_TIMER_IRQ
 #define LOAPIC_IRQ_COUNT		1
-#define LOAPIC_LVT_REG_SPACING  0x10
-
-/* Watchdog */
-#define WDT_DW_INT_MASK			(SCSS_INT_BASE + 0x7C)
-#define SCSS_PERIPH_CFG0		0x4
-
-/* RTC */
-#define RTC_DW_INT_MASK			(SCSS_INT_BASE + 0x78)
-#define CCU_RTC_CLK_DIV_OFFSET          0x3
-
-/*
- * I2C
- */
-#define I2C_MST_0_INT_MASK		(SCSS_INT_BASE + 0x48)
-
-#define I2C_DW_0_BASE_ADDR		0xB0002800
-#define I2C_DW_0_IRQ			4
-
-#if defined(CONFIG_MVIC)
-#define I2C_DW_IRQ_FLAGS		(IOAPIC_EDGE | IOAPIC_HIGH)
-#endif
-
-/* Comparator */
-#define INT_AIO_CMP_IRQ			(0x0E)
+#define LOAPIC_LVT_REG_SPACING  	0x10
 
 /*
  * PINMUX configuration settings
  */
-#if defined(CONFIG_PINMUX)
-
 #define PINMUX_BASE_ADDR		0xb0800900
 #define PINMUX_NUM_PINS			25
 
-#endif /* CONFIG_PINMUX */
-
-/*
- * RTC (Real Time Clock)
- */
-#define RTC_DW_BASE_ADDR		0xB0000400
-#define RTC_DW_IRQ			2
-
-/*
- * UART
- */
-#define UART_NS16550_PORT_0_BASE_ADDR	0xB0002000
-#define UART_NS16550_PORT_0_IRQ		8
-#define UART_NS16550_PORT_0_CLK_FREQ	MHZ(32)
-
-#define UART_NS16550_PORT_1_BASE_ADDR	0xB0002400
-#define UART_NS16550_PORT_1_IRQ		6
-#define UART_NS16550_PORT_1_CLK_FREQ	MHZ(32)
-
-#ifdef CONFIG_MVIC
-#include <drivers/ioapic.h>
-#define UART_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
-#endif /* CONFIG_MVIC */
-
-/*
- * WDT/Watchdog
- */
-#define WDT_DW_BASE_ADDR		0xB0000000
-#define WDT_DW_IRQ			16
-
 #endif /* __SOC_H_ */

arch/x86/soc/quark_se/Kconfig

@@ -25,6 +25,13 @@ config EOI_FORWARDING_BUG
 	Quark SE LOAPIC has issues with forwarding EOI to the IOAPIC for level
 	triggered interrupts, this is a SW workaround.
 
+config SS_RESET_VECTOR
+	hex "Sensor Subsystem Reset Vector"
+	default 0x40000000
+	help
+	Sensor subsystem reset vector. This value is needed to init the ARC
+	system on the SoC.
+
 config ARC_INIT
 	bool "Quark SE ARC Kickoff"
 	default n

arch/x86/soc/quark_se/Kconfig.defconfig

@@ -45,139 +45,42 @@ config LOAPIC_TIMER_IRQ
 config TOOLCHAIN_VARIANT
 	default "iamcu"
 
+config QMSI
+	def_bool y
+
+config QMSI_BUILTIN
+	def_bool y
+
+if PWM
+config PWM_QMSI
+	def_bool y
+endif
+
 if GPIO
-
-config GPIO_DW
-	def_bool y
-
-if GPIO_DW
-
-config GPIO_DW_BOTHEDGES_SUPPORT
-	def_bool y
-
-config GPIO_DW_CLOCK_GATE
-	def_bool n
-
-if GPIO_DW_CLOCK_GATE
-
-config GPIO_DW_CLOCK_GATE_DRV_NAME
-	default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
-
-endif # GPIO_DW_CLOCK_GATE
-
-config GPIO_DW_0
-	def_bool y
-
-if GPIO_DW_0
-
-config GPIO_DW_0_BASE_ADDR
-	default 0xb0000C00
-config GPIO_DW_0_IRQ
-	default 8
-config GPIO_DW_0_PRI
-	default 2
-config GPIO_DW_0_BITS
-	default 32
-config GPIO_DW_0_CLOCK_GATE_SUBSYS
-	default 13
-	depends on GPIO_DW_CLOCK_GATE
-
-endif # GPIO_DW_0
-
-config GPIO_DW_1
-	def_bool y
-
-if GPIO_DW_1
-
-config GPIO_DW_1_BASE_ADDR
-	default 0xb0800b00
-config GPIO_DW_1_IRQ
-	default 31
-config GPIO_DW_1_PRI
-	default 2
-config GPIO_DW_1_BITS
-	default 6
-
-endif # GPIO_DW_1
-
-endif # GPIO_DW
-
-if QMSI_DRIVERS
-
 config GPIO_QMSI
-	def_bool n
-
-if GPIO_QMSI
+	def_bool y
 
 config GPIO_QMSI_0
-	def_bool n
+	def_bool y
 
-if GPIO_QMSI_0
-
-config GPIO_QMSI_0_IRQ
-	default 8
 config GPIO_QMSI_0_PRI
 	default 2
 
-endif # GPIO_QMSI_0
-
 config GPIO_QMSI_AON
-	def_bool n
-config GPIO_QMSI_AON_NAME
-	default "gpio_aon"
-config GPIO_QMSI_AON_IRQ
-	default 31
+	def_bool y
 config GPIO_QMSI_AON_PRI
 	default 2
-
-endif # GPIO_QMSI
-
-endif # QMSI_DRIVERS
-
 endif # GPIO
 
 if I2C
-
-config I2C_DW
+config I2C_QMSI
 	def_bool y
 
-if I2C_DW
-
-config I2C_DW_0
-        def_bool y
-
-if I2C_DW_0
-
-config I2C_DW_0_NAME
-        default "I2C0"
-config I2C_DW_0_IRQ_PRI
-	default 2
-
-endif # I2C_DW_0
-
-config I2C_DW_1
-        def_bool y
-
-if I2C_DW_1
-
-config I2C_DW_1_NAME
-        default "I2C1"
-config I2C_DW_1_IRQ_PRI
-	default 2
-
-endif # I2C_DW_1
-
-endif # I2C_DW
-
-if I2C_QMSI
-
 config I2C_QMSI_0
 	def_bool y
 
 if I2C_QMSI_0
 
-config I2C_QMSI_0_IRQ
-	default 0
 config I2C_QMSI_0_IRQ_PRI
 	default 2
 config I2C_QMSI_0_DEFAULT_CFG
@@ -189,9 +92,6 @@ config I2C_QMSI_1
 	def_bool y
 
 if I2C_QMSI_1
-
-config I2C_QMSI_1_IRQ
-	default 1
 config I2C_QMSI_1_IRQ_PRI
 	default 2
 config I2C_QMSI_1_DEFAULT_CFG
@@ -199,10 +99,9 @@ config I2C_QMSI_1_DEFAULT_CFG
 
 endif # I2C_QMSI_1
 
-endif # I2C_QMSI
-
 endif # I2C
 
+
 if CLOCK_CONTROL
 
 config CLOCK_CONTROL_QUARK_SE
@@ -229,184 +128,69 @@ endif # CLOCK_CONTROL_QUARK_SE
 
 endif # CLOCK_CONTROL
 
+
+if COUNTER
+config AON_COUNTER_QMSI
+        def_bool y
+config AON_TIMER_QMSI
+        def_bool y
+config AON_TIMER_IRQ_PRI
+	default 2
+
+endif
+
+
 if SPI
-
-config SPI_DW
-	def_bool y
-
-if SPI_DW
-
-config SPI_DW_CLOCK_GATE
-	def_bool n
-
-if SPI_DW_CLOCK_GATE
-
-config SPI_DW_CLOCK_GATE_DRV_NAME
-	default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
-
-endif # SPI_DW_CLOCK_GATE
-
-config SPI_DW_PORT_0
-	def_bool y
-
-if SPI_DW_PORT_0
-
-config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
-	default 14
-	depends on SPI_DW_CLOCK_GATE
-config SPI_DW_PORT_0_REGS
-	default 0xb0001000
-config SPI_DW_PORT_0_IRQ
-	default 2
-config SPI_DW_PORT_0_PRI
-	default 2
-
-endif # SPI_DW_PORT_0
-
-config SPI_DW_PORT_1
-	def_bool y
-
-if SPI_DW_PORT_1
-
-config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
-	default 15
-	depends on SPI_DW_CLOCK_GATE
-config SPI_DW_PORT_1_REGS
-	default 0xb0001400
-config SPI_DW_PORT_1_IRQ
-	default 3
-config SPI_DW_PORT_1_PRI
-	default 2
-
-endif # SPI_DW_PORT_1
-
-endif # SPI_DW
-
 config SPI_QMSI
-       def_bool n
-
-if SPI_QMSI
+       def_bool y
 
 config SPI_QMSI_PORT_0
 	def_bool y
 
-if SPI_QMSI_PORT_0
-
-config SPI_QMSI_PORT_0_IRQ
-	default 2
 config SPI_QMSI_PORT_0_PRI
 	default 2
 
-endif # SPI_QMSI_PORT_0
-
 config SPI_QMSI_PORT_1
 	def_bool y
 
-if SPI_QMSI_PORT_1
-
-config SPI_QMSI_PORT_1_IRQ
-	default 3
 config SPI_QMSI_PORT_1_PRI
 	default 2
 
-endif # SPI_QMSI_PORT_1
-
-endif # SPI_QMSI
-
 endif # SPI
 
+if ADC
+config ADC_QMSI
+        def_bool y
+endif
+
+
+if AIO_COMPARATOR
+config AIO_QMSI_COMPARATOR
+        def_bool y
+endif
+
+
 if WATCHDOG
-config WDT_DW
+config WDT_QMSI
 	def_bool y
 
-if WDT_DW
-config WDT_DW_CLOCK_GATE
-	def_bool n
-config WDT_DW_CLOCK_GATE_DRV_NAME
-	default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
-config WDT_DW_CLOCK_GATE_SUBSYS
-	default 10
-config WDT_DW_IRQ_PRI
-	default 2
-endif # WDT_DW
-
-if WDT_QMSI
-config WDT_QMSI_IRQ
-	default 12
 config WDT_QMSI_IRQ_PRI
 	default 2
-endif # WDT_QMSI
 endif # WATCHDOG
 
 if RTC
-
-if RTC_QMSI
-config RTC_QMSI_IRQ
-	default 11
+config RTC_QMSI
+	def_bool y
 config RTC_QMSI_IRQ_PRI
 	default 2
-endif # RTC_QMSI
-
-config RTC_DW
-	def_bool y
-
-if RTC_DW
-config RTC_DW_CLOCK_GATE
-	def_bool y
-config RTC_DW_CLOCK_GATE_DRV_NAME
-	default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
-config RTC_DW_CLOCK_GATE_SUBSYS
-	default 11
-config RTC_DW_IRQ_PRI
-	default 2
-endif # RTC_DW
 endif # RTC
 
-if UART_NS16550
-
-config UART_NS16550_PORT_0
-	def_bool y
-
-if UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_0_NAME
-	default "UART_0"
-config UART_NS16550_PORT_0_IRQ_PRI
-	default 3
-config UART_NS16550_PORT_0_BAUD_RATE
-	default 115200
-config UART_NS16550_PORT_0_OPTIONS
-	default 0
-
-endif # UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_1
-	def_bool y
-
-if UART_NS16550_PORT_1
-
-config UART_NS16550_PORT_1_NAME
-	default "UART_1"
-config UART_NS16550_PORT_1_IRQ_PRI
-	default 3
-config UART_NS16550_PORT_1_BAUD_RATE
-	default 115200
-config UART_NS16550_PORT_1_OPTIONS
-	default 0
-
-endif # UART_NS16550_PORT_1
-
-endif # UART_NS16550
-
 if UART_QMSI
-
 config UART_QMSI_0
 	def_bool y
 
 if UART_QMSI_0
 
-config UART_QMSI_0_IRQ
-	default 5
 config UART_QMSI_0_IRQ_PRI
 	default 3
 
@@ -417,8 +201,6 @@ config UART_QMSI_1
 
 if UART_QMSI_1
 
-config UART_QMSI_1_IRQ
-	default 6
 config UART_QMSI_1_IRQ_PRI
 	default 3
 
@@ -433,20 +215,9 @@ config UART_CONSOLE_ON_DEV_NAME
 
 endif
 
-if BLUETOOTH_UART
-
-config BLUETOOTH_UART_ON_DEV_NAME
-	default "UART_1"
-
-endif
-
-if AON_TIMER_QMSI
-
-config AON_TIMER_IRQ
-	default 28
-config AON_TIMER_IRQ_PRI
-	default 2
-
-endif # AON_TIMER_QMSI
+if SOC_FLASH_QMSI
+config SOC_FLASH_QMSI_SYS_SIZE
+       default 0x60000
+endif # SOC_FLASH_QMSI
 
 endif # SOC_QUARK_SE

arch/x86/soc/quark_se/Makefile

@@ -1,7 +1,14 @@
+ifeq ($(COMPILER),clang)
+arch-cflags = $(call cc-option,-msoft-float, -march=pentium)
+else
 arch-cflags = $(call cc-option,-march=lakemont -mtune=lakemont -msoft-float, -march=pentium)
+endif
 
 ifeq ($(CONFIG_X86_IAMCU),y)
 arch-cflags += $(call cc-option,-miamcu)
+LD_TOOLCHAIN ?= -D__GCC_LINKER_CMD__ -D__IAMCU
+OUTPUT_FORMAT = elf32-iamcu
+OUTPUT_ARCH = iamcu:intel
 else
 arch-cflags += $(call cc-option,-mno-iamcu)
 endif

arch/x86/soc/quark_se/soc.c

@@ -100,25 +100,3 @@ SYS_INIT(arc_init, SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
 
 #endif /*CONFIG_ARC_INIT*/
 
-#ifdef CONFIG_UART_NS16550
-#ifdef CONFIG_UART_INTERRUPT_DRIVEN
-
-static int platform_uart_init(struct device *arg)
-{
-	ARG_UNUSED(arg);
-
-#ifdef CONFIG_UART_NS16550_PORT_0
-	SCSS_INTERRUPT->int_uart_mask[0] &= INT_UNMASK_IA;
-#endif
-
-#ifdef CONFIG_UART_NS16550_PORT_1
-	SCSS_INTERRUPT->int_uart_mask[1] &= INT_UNMASK_IA;
-#endif
-
-	return 0;
-}
-
-SYS_INIT(platform_uart_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
-#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
-#endif /* CONFIG_UART_NS16550 */

arch/x86/soc/quark_se/soc.h

@@ -32,138 +32,22 @@
 #endif
 
 #define INT_VEC_IRQ0  0x20	/* Vector number for IRQ0 */
-#define HPET_TIMER0_IRQ INT_VEC_IRQ0
 
 #ifndef _ASMLANGUAGE
 
-/* Core system registers */
-
-struct scss_ccu {
-	volatile uint32_t osc0_cfg0;    /**< Hybrid Oscillator Configuration 0 */
-	volatile uint32_t osc0_stat1;   /**< Hybrid Oscillator status 1 */
-	volatile uint32_t osc0_cfg1;    /**< Hybrid Oscillator configuration 1 */
-	volatile uint32_t osc1_stat0;   /**< RTC Oscillator status 0 */
-	volatile uint32_t osc1_cfg0;    /**< RTC Oscillator Configuration 0 */
-	volatile uint32_t usb_pll_cfg0; /**< USB Phase lock look configuration */
-	volatile uint32_t
-		ccu_periph_clk_gate_ctl; /**< Peripheral Clock Gate Control */
-	volatile uint32_t
-		ccu_periph_clk_div_ctl0; /**< Peripheral Clock Divider Control 0 */
-	volatile uint32_t
-		ccu_gpio_db_clk_ctl; /**< Peripheral Clock Divider Control 1 */
-	volatile uint32_t ccu_ext_clock_ctl; /**< External Clock Control Register */
-	volatile uint32_t ccu_ss_periph_clk_gate_ctl; /**< Sensor subsustem
-							peripheral clock gate
-							control */
-	volatile uint32_t ccu_lp_clk_ctl; /**< System Low Power Clock Control */
-	volatile uint32_t reserved;
-	volatile uint32_t ccu_mlayer_ahb_ctl; /**< AHB Control Register */
-	volatile uint32_t ccu_sys_clk_ctl;    /**< System Clock Control Register */
-	volatile uint32_t osc_lock_0;        /**< Clocks Lock Register */
-};
-
-struct scss_peripheral {
-	volatile uint32_t usb_phy_cfg0; /**< USB Configuration */
-	volatile uint32_t periph_cfg0;  /**< Peripheral Configuration */
-	volatile uint32_t reserved[2];
-	volatile uint32_t cfg_lock; /**< Configuration Lock */
-};
-
-struct int_ss_i2c {
-	volatile uint32_t err_mask;
-	volatile uint32_t rx_avail_mask;
-	volatile uint32_t tx_req_mask;
-	volatile uint32_t stop_det_mask;
-};
-
-struct int_ss_spi {
-	volatile uint32_t err_int_mask;
-	volatile uint32_t rx_avail_mask;
-	volatile uint32_t tx_req_mask;
-};
-
-struct scss_interrupt {
-	volatile uint32_t int_ss_adc_err_mask;
-	volatile uint32_t int_ss_adc_irq_mask;
-	volatile uint32_t int_ss_gpio_intr_mask[2];
-	struct int_ss_i2c int_ss_i2c[2];
-	struct int_ss_spi int_ss_spi[2];
-	volatile uint32_t int_i2c_mst_mask[2];
-	volatile uint32_t reserved;
-	volatile uint32_t int_spi_mst_mask[2];
-	volatile uint32_t int_spi_slv_mask[1];
-	volatile uint32_t int_uart_mask[2];
-	volatile uint32_t int_i2s_mask;
-	volatile uint32_t int_gpio_mask;
-	volatile uint32_t int_pwm_timer_mask;
-	volatile uint32_t int_usb_mask;
-	volatile uint32_t int_rtc_mask;
-	volatile uint32_t int_watchdog_mask;
-	volatile uint32_t int_dma_channel_mask[8];
-	volatile uint32_t int_mailbox_mask;
-	volatile uint32_t int_comparators_ss_halt_mask;
-	volatile uint32_t int_comparators_host_halt_mask;
-	volatile uint32_t int_comparators_ss_mask;
-	volatile uint32_t int_comparators_host_mask;
-	volatile uint32_t int_host_bus_err_mask;
-	volatile uint32_t int_dma_error_mask;
-	volatile uint32_t int_sram_controller_mask;
-	volatile uint32_t int_flash_controller_mask[2];
-	volatile uint32_t int_aon_timer_mask;
-	volatile uint32_t int_adc_pwr_mask;
-	volatile uint32_t int_adc_calib_mask;
-	volatile uint32_t int_aon_gpio_mask;
-	volatile uint32_t lock_int_mask_reg;
-};
-
-#define SCSS_PERIPHERAL_BASE (0xB0800800)
-#define SCSS_PERIPHERAL ((struct scss_peripheral *)SCSS_PERIPHERAL_BASE)
-
-#define SCSS_INT_BASE (0xB0800400)
-#define SCSS_INTERRUPT ((struct scss_interrupt *)SCSS_INT_BASE)
-
 /* Base Register */
 #define SCSS_REGISTER_BASE		0xB0800000
-#define SCSS_CCU ((struct scss_ccu *)SCSS_REGISTER_BASE)
 
-#define SCSS_CCU_SYS_CLK_CTL		0x38
-
-/* Peripheral Clock Gate Control */
-#define SCSS_CCU_PERIPH_CLK_GATE_CTL	0x18
-#define CCU_PERIPH_CLK_EN 		(1 << 1)
-#define CCU_PERIPH_CLK_DIV_CTL0		0x1C
 #define INT_UNMASK_IA  		        (~0x00000001)
 
-/* PWM */
-#define CCU_PWM_PCLK_EN_SW     		(1 << 12)
-
-/* Watchdog */
-#define WDT_DW_INT_MASK			(SCSS_INT_BASE + 0x7C)
-#define SCSS_PERIPH_CFG0		(0x4)
-
-/* RTC */
-#define RTC_DW_INT_MASK			(SCSS_INT_BASE + 0x78)
-#define CCU_RTC_CLK_DIV_OFFSET		(3)
-
 /* Clock */
 #define CLOCK_PERIPHERAL_BASE_ADDR	(SCSS_REGISTER_BASE + 0x18)
 #define CLOCK_EXTERNAL_BASE_ADDR	(SCSS_REGISTER_BASE + 0x24)
 #define CLOCK_SENSOR_BASE_ADDR		(SCSS_REGISTER_BASE + 0x28)
 #define CLOCK_SYSTEM_CLOCK_CONTROL	(SCSS_REGISTER_BASE + SCSS_CCU_SYS_CLK_CTL)
 
-/* SPI */
-#define SPI_DW_PORT_0_INT_MASK		(SCSS_INT_BASE + 0x54)
-#define SPI_DW_PORT_1_INT_MASK		(SCSS_INT_BASE + 0x58)
-
-/* GPIO */
-#define GPIO_DW_PORT_0_INT_MASK		(SCSS_INT_BASE + 0x6C)
-#define GPIO_DW_PORT_1_INT_MASK		(SCSS_INT_BASE + 0xD4)
-
-/* Comparator */
-#define INT_AIO_CMP_IRQ			(0x16)
-
-/*ARC INIT*/
-#define RESET_VECTOR                   	0x40000000
+/* ARC INIT */
+#define RESET_VECTOR                   	CONFIG_SS_RESET_VECTOR
 #define SCSS_SS_CFG                    	0x0600
 #define SCSS_SS_STS                    	0x0604
 #define ARC_HALT_INT_REDIR             	(1 << 26)
@@ -175,64 +59,8 @@ struct scss_interrupt {
 /*
  * PINMUX configuration settings
  */
-#if defined(CONFIG_PINMUX)
-
 #define PINMUX_BASE_ADDR		0xb0800900
 
-#endif
-
-/*
- * UART
- */
-#define UART_NS16550_PORT_0_BASE_ADDR	0xB0002000
-#define UART_NS16550_PORT_0_IRQ		5
-#define UART_NS16550_PORT_0_CLK_FREQ	MHZ(32)
-
-#define UART_NS16550_PORT_1_BASE_ADDR	0xB0002400
-#define UART_NS16550_PORT_1_IRQ		6
-#define UART_NS16550_PORT_1_CLK_FREQ	MHZ(32)
-
-#ifdef CONFIG_IOAPIC
-#include <drivers/ioapic.h>
-#define UART_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
-#endif /* CONFIG_IOAPIC */
-
-/*
- * AIO/Comparator
- */
-#define AIO_DW_COMPARATOR_BASE_ADDR	0xb0800300
-
-/*
- * I2C
- */
-#define I2C_DW_0_BASE_ADDR		0xb0002800
-#define I2C_DW_0_IRQ			0
-
-#define I2C_DW_1_BASE_ADDR		0xb0002c00
-#define I2C_DW_1_IRQ			1
-
-#if defined(CONFIG_IOAPIC)
-#define I2C_DW_IRQ_FLAGS		(IOAPIC_EDGE | IOAPIC_HIGH)
-#endif
-
-/*
- * PWM
- */
-#define PWM_DW_BASE_ADDR		0xB0000800
-#define PWM_DW_NUM_PORTS		4
-
-/*
- * RTC (Real Time Clock)
- */
-#define RTC_DW_BASE_ADDR		0xB0000400
-#define RTC_DW_IRQ			11
-
-/*
- * WDT/Watchdog
- */
-#define WDT_DW_BASE_ADDR		0xB0000000
-#define WDT_DW_IRQ			12
-
 #endif /*  _ASMLANGUAGE */
 
 #endif /* __SOC_H_ */

arch/x86/soc/quark_se/soc_config.c

@@ -38,9 +38,10 @@ static int x86_quark_se_ipm_init(void)
 static struct quark_se_ipm_controller_config_info ipm_controller_config = {
 	.controller_init = x86_quark_se_ipm_init
 };
-DEVICE_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
+DEVICE_AND_API_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
 				NULL, &ipm_controller_config,
-				PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
+				PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
+				&ipm_quark_se_api_funcs);
 
 #if defined(CONFIG_IPM_CONSOLE_RECEIVER) && defined(CONFIG_PRINTK)
 #include <console/ipm_console.h>

arch/x86/soc/quark_x1000/Kconfig.defconfig

@@ -87,7 +87,7 @@ config I2C_DW_0
 if I2C_DW_0
 
 config I2C_DW_0_NAME
-        default "I2C0"
+        default "I2C_0"
 config I2C_DW_0_DEFAULT_CFG
         default 0x12
 config I2C_DW_0_IRQ_PRI
@@ -144,20 +144,6 @@ if GPIO_DW_0
 
 config GPIO_DW_0_NAME
 	default "GPIO_0"
-config GPIO_DW_0_BUS
-	default 0
-config GPIO_DW_0_DEV
-	default 21
-config GPIO_DW_0_FUNCTION
-	default 2
-config GPIO_DW_0_BAR
-	default 1
-config GPIO_DW_0_BITS
-	default 8
-config GPIO_DW_0_BASE_ADDR
-	default 0x90006000
-config GPIO_DW_0_IRQ
-	default 18
 config GPIO_DW_0_PRI
 	default 2
 config GPIO_DW_0_IRQ_SHARED_NAME
@@ -287,10 +273,6 @@ config ETH_DW_0
 
 if ETH_DW_0
 
-config ETH_DW_0_BASE_ADDR
-	default 0x90002000
-config ETH_DW_0_IRQ
-	default 18
 config ETH_DW_0_IRQ_SHARED_NAME
 	default SHARED_IRQ_0_NAME if SHARED_IRQ
 

arch/x86/soc/quark_x1000/soc.h

@@ -36,6 +36,21 @@
 #include <drivers/ioapic.h>
 #endif
 
+/*
+ * Ethernet (DesignWare)
+ */
+#define ETH_DW_PCI_VENDOR_ID			0x8086
+#define ETH_DW_PCI_DEVICE_ID			0x0937
+#define ETH_DW_PCI_CLASS			0x02
+
+#define ETH_DW_0_BASE_ADDR			0x90002000
+#define ETH_DW_0_IRQ				18
+
+#define ETH_DW_0_PCI_BUS			0
+#define ETH_DW_0_PCI_DEV			20
+#define ETH_DW_0_PCI_FUNCTION			6
+#define ETH_DW_0_PCI_BAR			0
+
 /*
  * GPIO
  */
@@ -47,6 +62,23 @@
 #define GPIO_SCH_1_BASE_ADDR			0x10A0
 #define GPIO_SCH_1_BITS				6
 
+#define GPIO_DW_PCI_VENDOR_ID			0x8086
+#define GPIO_DW_PCI_DEVICE_ID			0x0934
+#define GPIO_DW_PCI_CLASS			0x0C
+
+#define GPIO_DW_0_BASE_ADDR			0x90006000
+#define GPIO_DW_0_IRQ				18
+#define GPIO_DW_0_BITS				8
+
+#define GPIO_DW_0_PCI_BUS			0
+#define GPIO_DW_0_PCI_DEV			21
+#define GPIO_DW_0_PCI_FUNCTION			2
+#define GPIO_DW_0_PCI_BAR			1
+
+#if defined(CONFIG_IOAPIC)
+#define GPIO_DW_0_IRQ_FLAGS			(IOAPIC_LEVEL | IOAPIC_LOW)
+#endif
+
 /*
  * I2C
  */

boards/arduino_101/Kconfig.defconfig

@@ -9,18 +9,40 @@ if NBLE
 config GPIO
 	def_bool y
 
+config BLUETOOTH_NRF51_PM
+	def_bool y
+
 config NBLE_UART_ON_DEV_NAME
-        default UART_NS16550_PORT_0_NAME
+        default UART_QMSI_0_NAME
+
+endif
+
+if BLUETOOTH_H4
+
+config GPIO
+	def_bool y
+
+config BLUETOOTH_NRF51_PM
+	def_bool y
+
+config BLUETOOTH_WAIT_NOP
+	def_bool y
+
+config BLUETOOTH_UART_ON_DEV_NAME
+        default UART_QMSI_0_NAME
 
 endif
 
 if UART_PIPE
 
 config UART_PIPE_ON_DEV_NAME
-	default UART_NS16550_PORT_1_NAME
+	default UART_QMSI_1_NAME
 
 endif
 
+config BLUETOOTH_MONITOR_ON_DEV_NAME
+	default UART_QMSI_1_NAME if BLUETOOTH_DEBUG_MONITOR
+
 if FLASH && SPI
 
 config SPI_FLASH_W25QXXDV
@@ -29,7 +51,7 @@ config SPI_FLASH_W25QXXDV
 if SPI_FLASH_W25QXXDV
 
 config SPI_FLASH_W25QXXDV_SPI_NAME
-	default SPI_DW_PORT_0_DRV_NAME
+	default SPI_QMSI_PORT_0_DRV_NAME
 config SPI_FLASH_W25QXXDV_SPI_SLAVE
 	default 1
 

boards/arduino_101/arduino_101_defconfig

@@ -5,9 +5,9 @@ CONFIG_CPU_MINUTEIA=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
-CONFIG_UART_NS16550=y
-CONFIG_UART_NS16550_PORT_0_BAUD_RATE=1000000
-CONFIG_UART_NS16550_PORT_0_OPTIONS=1
+CONFIG_UART_QMSI=y
+CONFIG_UART_QMSI_0_BAUDRATE=1000000
+CONFIG_UART_QMSI_0_HW_FC=y
 CONFIG_PRINTK=y
 CONFIG_IPM=y
 CONFIG_IPM_QUARK_SE=y
@@ -15,4 +15,3 @@ CONFIG_IPM_QUARK_SE_MASTER=y
 CONFIG_IPM_CONSOLE_RECEIVER=y
 CONFIG_ARC_INIT=y
 CONFIG_PINMUX=y
-CONFIG_SPI_DW_LEVEL_HIGH=y

boards/arduino_101/arduino_101_factory_defconfig

@@ -0,0 +1,20 @@
+CONFIG_X86=y
+CONFIG_SOC_QUARK_SE=y
+CONFIG_BOARD_ARDUINO_101=y
+CONFIG_CPU_MINUTEIA=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_QMSI=y
+CONFIG_UART_QMSI_0_BAUDRATE=1000000
+CONFIG_UART_QMSI_0_HW_FC=y
+CONFIG_PRINTK=y
+CONFIG_IPM=y
+CONFIG_IPM_QUARK_SE=y
+CONFIG_IPM_QUARK_SE_MASTER=y
+CONFIG_IPM_CONSOLE_RECEIVER=y
+CONFIG_ARC_INIT=y
+CONFIG_PINMUX=y
+CONFIG_SS_RESET_VECTOR=0x40034000
+CONFIG_PHYS_LOAD_ADDR=0x40010000
+CONFIG_VERSION_HEADER=y

boards/arduino_101/board.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2011-2015, Wind River Systems, Inc.
+ * Copyright (c) 2016, Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -19,3 +20,15 @@
 #include <uart.h>
 #include <device.h>
 #include <init.h>
+
+#ifdef CONFIG_VERSION_HEADER
+#include "version_header.h"
+/* The content of this struct is overwritten in a post-build script */
+struct version_header version_header __attribute__((section(".version_header")))
+__attribute__((used)) = {
+	.magic = {'$', 'B', '!', 'N'},
+	.version = 0x01,
+	.reserved_1 = {0, 0, 0, 0},
+	.reserved_2 = {0, 0, 0, 0},
+};
+#endif

boards/arduino_101/support/arduino_101_backup.sh

@@ -2,7 +2,7 @@
 
 if [ -z ${ZEPHYR_SDK_INSTALL_DIR} ];
 then
-    echo "ZEPHYR_SDK_INSTLL_DIR is not set.  Unable to continue"
+    echo "ZEPHYR_SDK_INSTALL_DIR is not set.  Unable to continue"
     exit 1
 fi
 

boards/arduino_101/support/arduino_101_load.sh

@@ -2,7 +2,7 @@
 
 if [ -z ${ZEPHYR_SDK_INSTALL_DIR} ];
 then
-    echo "ZEPHYR_SDK_INSTLL_DIR is not set.  Unable to continue"
+    echo "ZEPHYR_SDK_INSTALL_DIR is not set.  Unable to continue"
     exit 1
 fi
 
@@ -22,7 +22,7 @@ echo "About to flash Zephyr comptaible ROM"
 $OPENOCD -s ${OPENOCD_SCRIPT} \
          -f ${ZEPHYR_BASE}/boards/arduino_101/support/restore.cfg \
          -c 'init' \
-         -c 'targets' \
+         -c 'targets 1' \
          -c 'reset halt' \
          -c 'load_image quark_se_rom.bin 0xffffe000 bin' \
          -c 'verify_image quark_se_rom.bin 0xffffe000 bin' \
@@ -48,7 +48,7 @@ echo "About to flash the OS and BOOT binaries"
 $OPENOCD -s ${OPENOCD_SCRIPT} \
          -f ${ZEPHYR_BASE}/boards/arduino_101/support/restore.cfg \
          -c 'init' \
-         -c 'targets' \
+         -c 'targets 1' \
          -c 'reset halt' \
          -c "load_image   A101_OS.bin 0x40000000 bin" \
          -c "verify_image A101_OS.bin 0x40000000 bin" \

boards/arduino_101/version_header.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016 Intel Corporation
+ * Copyright (c) 2016, Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -14,6 +14,9 @@
  * limitations under the License.
  */
 
+#ifndef __VERSION_HEADER_H__
+#define __VERSION_HEADER_H__
+
 #include <stdint.h>
 
 /**
@@ -24,13 +27,9 @@
  *    version header.
  *  - the position of this struct is usually defined in the linker script and
  *    its content is overwritten after the build (in a special post-build script).
- * It therefore doesn't need to be initialized at compile-time (excepted magic
+ * It therefore doesn't need to be initialized at compile-time (expected magic
  * and version), yet can be used in the code at runtime.
  *
- * The binary version header is usually localized at the beginning of
- * the payload, but in the case of e.g. a bootloader, it can also be stored
- * at the end of the payload, or even anywhere within the payload.
- *
  * Major, Minor, Patch are the following the usual definition, e.g. 1.0.0
  */
 struct version_header {
@@ -46,30 +45,30 @@ struct version_header {
 	/**
 	 * Human-friendly version string, free format (not NULL terminated)
 	 * Advised format is: PPPPXXXXXX-YYWWTBBBB
-	 *  - PPPP  : product code, e.g ATP1
+	 *  - PPPP  : product code
 	 *  - XXXXXX: binary info. Usually contains information such as the
 	 *    binary type (bootloader, application), build variant (unit tests,
 	 *    debug, release), release/branch name
 	 *  - YY    : year last 2 digits
 	 *  - WW    : work week number
-	 *  - T     : build type, e.g. [W]eekly, [L]atest, [R]elease, [P]rod,
+	 *  - T     : build type, e.g. [W]eekly, [L]atest, [R]elease, [P]roduction,
 	 *    [F]actory, [C]ustom
 	 *  - BBBB  : build number, left padded with zeros
 	 * Examples:
-	 *  - ATP1BOOT01-1503W0234
-	 *  - CLRKAPP123-1502R0013
+	 *  - A101BOOT01-1503W0234
+	 *  - CCCKAPP123-1502R0013
 	 */
 	char version_string[20];
 
 	/**
-	 * Micro-SHA1 (first 4 bytes of the SHA1) of the binary payload excl
+	 * Micro-SHA1 (first 4 bytes of the SHA1) of the binary payload excluding
 	 * this header. It allows to uniquely identify the exact binary used.
 	 * In the case the header is located in the middle of the payload, the
 	 * SHA1 has to be computed from two disjoint buffers.
 	 */
 	uint8_t hash[4];
 
-	/** Position of the payload start relative to the address of struct */
+	/** Position of the payload start relative to the address of this structure */
 	int32_t offset;
 
 	/** Filled with zeros, can be eventually used for 64 bits support */
@@ -81,3 +80,9 @@ struct version_header {
 	/** Filled with zeros, can be eventually used for 64 bits support */
 	uint8_t reserved_2[4];
 } __packed;
+
+/** The global version header struct */
+extern struct version_header version_header;
+
+#endif /* __VERSION_HEADER_H__ */
+

boards/arduino_101_sss/Makefile.board

@@ -1,7 +1,7 @@
 FLASH_SCRIPT = openocd.sh
 OPENOCD_PRE_CMD = "-c targets 1"
-OPENOCD_LOAD_CMD = "load_image ${O}/${KERNEL_BIN_NAME} 0x40000000"
-OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} 0x40000000"
+OPENOCD_LOAD_CMD = "load_image ${O}/${KERNEL_BIN_NAME} $(CONFIG_FLASH_BASE_ADDRESS)"
+OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} $(CONFIG_FLASH_BASE_ADDRESS)"
 
 GDB_PORT = 3334
 

boards/arduino_101_sss/arduino_101_sss_factory_defconfig

@@ -0,0 +1,19 @@
+CONFIG_ARC=y
+CONFIG_SOC_QUARK_SE_SS=y
+CONFIG_BOARD_ARDUINO_101_SSS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
+CONFIG_XIP=y
+CONFIG_NANO_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_CPU_ARCEM4=y
+CONFIG_CPU_ARCV2=y
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y
+CONFIG_IPM=y
+CONFIG_IPM_QUARK_SE=y
+CONFIG_IPM_CONSOLE_SENDER=y
+CONFIG_CONSOLE=y
+CONFIG_SPI_DW_INTERRUPT_SEPARATED_LINES=y
+CONFIG_VERSION_HEADER=y
+CONFIG_FLASH_BASE_ADDRESS=0x40034000

boards/arduino_101_sss/board.c

@@ -19,3 +19,15 @@
 #include <uart.h>
 #include <device.h>
 #include <init.h>
+
+#ifdef CONFIG_VERSION_HEADER
+#include "version_header.h"
+/* The content of this struct is overwritten in a post-build script */
+struct version_header version_header __attribute__((section(".version_header")))
+__attribute__((used)) = {
+	.magic = {'$', 'B', '!', 'N'},
+	.version = 0x01,
+	.reserved_1 = {0, 0, 0, 0},
+	.reserved_2 = {0, 0, 0, 0},
+};
+#endif

boards/arduino_101_sss/version_header.h

@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2016, Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __VERSION_HEADER_H__
+#define __VERSION_HEADER_H__
+
+#include <stdint.h>
+
+/**
+ * Define the content of a 48-bytes binary version header.
+ *
+ * The binary version header allows to uniquely identify the binary used. Note:
+ *  - a device may include more than one binary, each having its own binary
+ *    version header.
+ *  - the position of this struct is usually defined in the linker script and
+ *    its content is overwritten after the build (in a special post-build script).
+ * It therefore doesn't need to be initialized at compile-time (expected magic
+ * and version), yet can be used in the code at runtime.
+ *
+ * Major, Minor, Patch are the following the usual definition, e.g. 1.0.0
+ */
+struct version_header {
+	/** Always equal to $B!N */
+	uint8_t magic[4];
+
+	/** Header format version */
+	uint8_t version;
+	uint8_t major;
+	uint8_t minor;
+	uint8_t patch;
+
+	/**
+	 * Human-friendly version string, free format (not NULL terminated)
+	 * Advised format is: PPPPXXXXXX-YYWWTBBBB
+	 *  - PPPP  : product code
+	 *  - XXXXXX: binary info. Usually contains information such as the
+	 *    binary type (bootloader, application), build variant (unit tests,
+	 *    debug, release), release/branch name
+	 *  - YY    : year last 2 digits
+	 *  - WW    : work week number
+	 *  - T     : build type, e.g. [W]eekly, [L]atest, [R]elease, [P]roduction,
+	 *    [F]actory, [C]ustom
+	 *  - BBBB  : build number, left padded with zeros
+	 * Examples:
+	 *  - A101BOOT01-1503W0234
+	 *  - CCCKAPP123-1502R0013
+	 */
+	char version_string[20];
+
+	/**
+	 * Micro-SHA1 (first 4 bytes of the SHA1) of the binary payload excluding
+	 * this header. It allows to uniquely identify the exact binary used.
+	 * In the case the header is located in the middle of the payload, the
+	 * SHA1 has to be computed from two disjoint buffers.
+	 */
+	uint8_t hash[4];
+
+	/** Position of the payload start relative to the address of this structure */
+	int32_t offset;
+
+	/** Filled with zeros, can be eventually used for 64 bits support */
+	uint8_t reserved_1[4];
+
+	/** Size of the payload in bytes, including this header */
+	uint32_t size;
+
+	/** Filled with zeros, can be eventually used for 64 bits support */
+	uint8_t reserved_2[4];
+} __packed;
+
+/** The global version header struct */
+extern struct version_header version_header;
+
+#endif /* __VERSION_HEADER_H__ */
+

boards/arduino_due/Kconfig.defconfig

@@ -9,16 +9,6 @@ if I2C
 config I2C_ATMEL_SAM3
 	default y
 
-if I2C_ATMEL_SAM3
-
-config I2C_ATMEL_SAM3_0
-	default y
-
-config I2C_ATMEL_SAM3_1
-	default y
-
-endif # I2C_ATMEL_SAM3
-
 endif # I2C
 
 endif # BOARD_ARDUINO_DUE

boards/frdm_k64f/Kconfig.board

@@ -1,4 +1,4 @@
 
 config  BOARD_FRDM_K64F
         bool "Freescale FRDM-K64F"
-        depends on SOC_FSL_FRDM_K64F
+        depends on SOC_SERIES_KINETIS_K6X

boards/frdm_k64f/Kconfig.defconfig

@@ -10,4 +10,4 @@ config FLASH_SIZE
 config SRAM_SIZE
 	default 192
 
-endif # BOARD_FSL_FRDM_K64F
+endif # BOARD_FRDM_K64F

boards/frdm_k64f/frdm_k64f_defconfig

@@ -1,5 +1,6 @@
 CONFIG_ARM=y
-CONFIG_SOC_FSL_FRDM_K64F=y
+CONFIG_SOC_MK64F12=y
+CONFIG_SOC_SERIES_KINETIS_K6X=y
 CONFIG_BOARD_FRDM_K64F=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
@@ -7,3 +8,4 @@ CONFIG_SERIAL=y
 CONFIG_CORTEX_M_SYSTICK=y
 CONFIG_UART_K20=y
 CONFIG_GPIO=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000

boards/galileo/Kconfig.defconfig

@@ -25,6 +25,9 @@ config ADC
 config SHARED_IRQ
 	def_bool y
 
+config PCI_ENUMERATION
+	def_bool y
+
 if PINMUX
 
 config PINMUX_GALILEO_EXP0_NAME
@@ -139,9 +142,9 @@ endif # PWM_PCA9685
 endif # PWM && I2C
 
 # SPI uses GPIO pin for CS, so it needs to be initialized after
-# the gpio_dw driver
-config SPI_INTEL_INIT_PRIORITY
-	default 70 if SPI_INTEL
+# the gpio_dw driver ( and the pinmux driver for port 1)
+config SPI_INIT_PRIORITY
+       default 90 if SPI_INTEL
 
 # Pin multiplexer uses PCAL9535A, needs to be initialized after it
 config PINMUX_INIT_PRIORITY

boards/nucleo_f103rb/Makefile.board

@@ -0,0 +1,6 @@
+FLASH_SCRIPT = openocd.sh
+
+OPENOCD_LOAD_CMD = "flash write_image erase ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
+OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
+
+export FLASH_SCRIPT OPENOCD_LOAD_CMD OPENOCD_VERIFY_CMD