Zephyr v1.4.0

Change-Id: Iedb103de08349c3a046247cbdcf6498126765d72
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.checkpatch.conf

@@ -3,14 +3,15 @@
 --emacs
 --summary-file
 --show-types
---max-line-length=100
+--max-line-length=80
+--min-conf-desc-length=1
 
 --ignore BRACES
 --ignore PRINTK_WITHOUT_KERN_LEVEL
 --ignore SPLIT_STRING
---ignore FILE_PATH_CHANGES
 --ignore VOLATILE
 --ignore CONFIG_EXPERIMENTAL
 --ignore PREFER_KERNEL_TYPES
 --ignore AVOID_EXTERNS
 --ignore NETWORKING_BLOCK_COMMENT_STYLE
+--exclude ext

.gitignore

@@ -5,7 +5,6 @@
 *.pyc
 *.swp
 *.swo
-!arch/*/*/**/*.cmd
 *~
 cscope.*
 .dir
@@ -19,9 +18,9 @@ scripts/kconfig/zconf.hash.c
 scripts/kconfig/zconf.lex.c
 scripts/kconfig/zconf.tab.c
 doc/_build
-xml
-html/
-doc/latex/
+doc/xml
+doc/html
+doc/latex
 sanity-out/
 scripts/grub
 doc/reference/kconfig/CONFIG_*

.mailmap

@@ -5,3 +5,9 @@ Leona Cook <leonax.cook@intel.com> <lsc@hackeress.com>
 Leona Cook <leonax.cook@intel.com> <leonax.cook@intel.com>
 Thomas Heeley <thomas.heeley@intel.com> <thomas.heeley@intel.com>
 Shuang He <shuang.he@intel.com> <shuang.he@intel.com>
+Chuck Jordan <cjordan@synopsys.com> <cjordan@synopsys.com>
+Jeremie Garcia <jeremie.garcia@intel.com> <jeremie.garcia@intel.com>
+Bit Pathe <bitpathe@gmail.com> <bitpathe@gmail.com>
+Carles Cufi <carles.cufi@nordicsemi.no> <carles.cufi@nordicsemi.no>
+Kuo-Lang Tseng <kuo-lang.tseng@intel.com> <kuo-lang.tseng@intel.com>
+Gerardo Aceves <gerardo.aceves@intel.com> <gerardo.aceves@intel.com>

Kbuild

@@ -94,7 +94,7 @@ OFFSETS_INCLUDE = $(strip \
 
 cmd_cc_o_c_1 = $(CC) $(KBUILD_CFLAGS) $(OFFSETS_INCLUDE) -c -o $@ $<
 
-arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c
+arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c $(KCONFIG_CONFIG)
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed,cc_o_c_1)
 

Kconfig

@@ -15,6 +15,6 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 #
-mainmenu "Zephyr Kernel/$ARCH Configuration"
+mainmenu "Zephyr Kernel Configuration"
 
 source "Kconfig.zephyr"

Kconfig.zephyr

@@ -2,6 +2,7 @@
 
 #
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
+# Copyright (c) 2016 Intel Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -16,8 +17,8 @@
 # limitations under the License.
 #
 config KERNELVERSION
-        string
-        option env="KERNELVERSION"
+	string
+	option env="KERNELVERSION"
 
 source "arch/Kconfig"
 
@@ -29,3 +30,16 @@ source "net/Kconfig"
 
 source "misc/Kconfig"
 
+source "lib/Kconfig"
+
+source "ext/Kconfig"
+
+#
+# The following are for Kconfig files for default values only.
+# These should be parsed at the end.
+#
+# Board defaults should be parsed before SoC defaults
+# because board usually overrides them.
+#
+source "boards/*/Kconfig.defconfig"
+source "arch/*/soc/*/Kconfig.defconfig"

MAINTAINERS

@@ -0,0 +1,132 @@
+Originally from the Linux Kernel.
+# Licensed under the terms of the GNU GPL License version 2
+
+Descriptions of section entries:
+
+	P: Person (obsolete)
+	M: Mail patches to: FullName <address@domain>
+	R: Designated reviewer: FullName <address@domain>
+	   These reviewers should be CCed on patches.
+	L: Mailing list that is relevant to this area
+	W: Web-page with status/info
+	Q: Patchwork web based patch tracking system site
+	T: SCM tree type and location.
+	   Type is one of: git, hg, quilt, stgit, topgit
+	S: Status, one of the following:
+	   Supported:	Someone is actually paid to look after this.
+	   Maintained:	Someone actually looks after it.
+	   Odd Fixes:	It has a maintainer but they don't have time to do
+			much other than throw the odd patch in. See below..
+	   Orphan:	No current maintainer [but maybe you could take the
+			role as you write your new code].
+	   Obsolete:	Old code. Something tagged obsolete generally means
+			it has been replaced by a better system and you
+			should be using that.
+	F: Files and directories with wildcard patterns.
+	   A trailing slash includes all files and subdirectory files.
+	   F:	drivers/net/	all files in and below drivers/net
+	   F:	drivers/net/*	all files in drivers/net, but not below
+	   F:	*/net/*		all files in "any top level directory"/net
+	   One pattern per line.  Multiple F: lines acceptable.
+	N: Files and directories with regex patterns.
+	   N:	[^a-z]tegra	all files whose path contains the word tegra
+	   One pattern per line.  Multiple N: lines acceptable.
+	   scripts/get_maintainer.pl has different behavior for files that
+	   match F: pattern and matches of N: patterns.  By default,
+	   get_maintainer will not look at git log history when an F: pattern
+	   match occurs.  When an N: match occurs, git log history is used
+	   to also notify the people that have git commit signatures.
+	X: Files and directories that are NOT maintained, same rules as F:
+	   Files exclusions are tested before file matches.
+	   Can be useful for excluding a specific subdirectory, for instance:
+	   F:	net/
+	   X:	net/ipv6/
+	   matches all files in and below net excluding net/ipv6/
+	K: Keyword perl extended regex pattern to match content in a
+	   patch or file.  For instance:
+	   K: of_get_profile
+	      matches patches or files that contain "of_get_profile"
+	   K: \b(printk|pr_(info|err))\b
+	      matches patches or files that contain one or more of the words
+	      printk, pr_info or pr_err
+	   One regex pattern per line.  Multiple K: lines acceptable.
+
+Note: For the hard of thinking, this list is meant to remain in alphabetical
+order. If you could add yourselves to it in alphabetical order that would be
+so much easier [Ed]
+
+Maintainers List (try to look for most precise areas first)
+
+		-----------------------------------
+
+BLUETOOTH
+M:	Johan Hedberg <johan.hedberg@intel.com>
+M:	Luiz Augusto von Dentz <luiz.dentz@gmail.com>
+M:	Szymon Janc <szymon.janc@gmail.com>
+S:	Supported
+F:	net/bluetooth/
+F:	include/bluetooth/
+F:	drivers/bluetooth/
+F:	samples/bluetooth/
+F:	tests/bluetooth/
+
+DOCUMENTATION
+M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
+S:	Supported
+F:	doc/
+
+FLASH DRIVER
+M:	Baohong Liu <baohong.liu@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	drivers/flash/
+
+NORDIC MDK
+M:	Carles Cufi <carles.cufi@nordicsemi.no>
+S:	Supported
+F:	ext/hal/nordic/mdk
+
+POWER MANAGEMENT
+M:	Ramesh Thomas <ramesh.thomas@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	arch/x86/core/crt0.S
+F:	include/device.h
+F:	include/init.h
+F:	include/power.h
+F:	kernel/microkernel/k_idle.c
+F:	kernel/nanokernel/device.c
+F:	samples/power/
+
+QMSI
+M:	Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	ext/hal/qmsi/
+
+QMSI DRIVERS
+M:	Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
+M:	Baohong Liu <baohong.liu@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	drivers/*/*qmsi*
+F:	drivers/*/*/*qmsi*
+
+SANITYCHECK
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	scripts/sanitycheck
+F:	scripts/expr_parser.py
+F:	scripts/sanity_chk/
+
+TINYCRYPT
+M:	Constanza Heath <constanza.m.heath@intel.com>
+S:	Supported
+F:	ext/lib/crypto/tinycrypt
+
+THE REST
+M:	Anas Nashif <anas.nashif@intel.com>
+L:	devel@lists.zephyrproject.com
+T:	git https://gerrit.zephyrproject.org/r/a/zephyr
+S:	Buried alive in reporters
+F:	*
+F:	*/

Makefile

@@ -1,5 +1,5 @@
 VERSION_MAJOR 	   = 1
-VERSION_MINOR 	   = 1
+VERSION_MINOR 	   = 4
 PATCHLEVEL 	   = 0
 VERSION_RESERVED   = 0
 EXTRAVERSION       =
@@ -28,6 +28,9 @@ ifeq (MINGW, $(findstring MINGW, $(UNAME)))
 HOST_OS=MINGW
 PWD_OPT=-W
 DISABLE_TRYRUN=y
+CPATH ?= $(MIGW_DIR)/include
+LIBRARY_PATH ?= $(MINGW_DIR)/lib
+export CPATH LIBRARY_PATH
 else ifeq (Linux, $(findstring Linux, $(UNAME)))
 HOST_OS=Linux
 else ifeq (Darwin, $(findstring Darwin, $(UNAME)))
@@ -281,15 +284,6 @@ KBUILD_BUILTIN := 1
 export KBUILD_BUILTIN
 export KBUILD_CHECKSRC KBUILD_SRC
 
-ifneq ($(CC),)
-ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
-COMPILER := clang
-else
-COMPILER := gcc
-endif
-export COMPILER
-endif
-
 # Look for make include files relative to root of kernel src
 MAKEFLAGS += --include-dir=$(srctree)
 
@@ -307,8 +301,8 @@ ifeq ($(USE_CCACHE),1)
 CC		= $(CCACHE) $(CROSS_COMPILE)gcc
 CXX		= $(CCACHE) $(CROSS_COMPILE)g++
 else
-CC		= $(CROSS_COMPILE)gcc
-CXX		= $(CROSS_COMPILE)g++
+CC		?= $(CROSS_COMPILE)gcc
+CXX		?= $(CROSS_COMPILE)g++
 endif
 CPP		= $(CC) -E
 AR		= $(CROSS_COMPILE)ar
@@ -317,6 +311,7 @@ STRIP		= $(CROSS_COMPILE)strip
 OBJCOPY		= $(CROSS_COMPILE)objcopy
 OBJDUMP		= $(CROSS_COMPILE)objdump
 GDB		= $(CROSS_COMPILE)gdb
+READELF		= $(CROSS_COMPILE)readelf
 AWK		= awk
 GENIDT		= scripts/gen_idt/gen_idt
 GENOFFSET_H	= scripts/gen_offset_header/gen_offset_header
@@ -345,18 +340,23 @@ endif
 USERINCLUDE    := -include $(CURDIR)/include/generated/autoconf.h
 
 SOC_NAME = $(subst $(DQUOTE),,$(CONFIG_SOC))
+SOC_SERIES = $(subst $(DQUOTE),,$(CONFIG_SOC_SERIES))
+SOC_FAMILY = $(subst $(DQUOTE),,$(CONFIG_SOC_FAMILY))
+
 override ARCH = $(subst $(DQUOTE),,$(CONFIG_ARCH))
 BOARD_NAME = $(subst $(DQUOTE),,$(CONFIG_BOARD))
 KERNEL_NAME = $(subst $(DQUOTE),,$(CONFIG_KERNEL_BIN_NAME))
 KERNEL_ELF_NAME = $(KERNEL_NAME).elf
 KERNEL_BIN_NAME = $(KERNEL_NAME).bin
+KERNEL_STAT_NAME = $(KERNEL_NAME).stat
 
-export SOC_NAME BOARD_NAME ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME
+export SOC_FAMILY SOC_SERIES SOC_PATH SOC_NAME BOARD_NAME
+export ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME
 # Use ZEPHYRINCLUDE when you must reference the include/ directory.
 # Needed to be compatible with the O= option
 ZEPHYRINCLUDE    = \
 		-I$(srctree)/arch/$(ARCH)/include \
-		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_NAME) \
+		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH) \
 		-I$(srctree)/boards/$(BOARD_NAME) \
 		$(if $(KBUILD_SRC), -I$(srctree)/include) \
 		-I$(srctree)/include \
@@ -516,7 +516,7 @@ scripts: scripts_basic include/config/auto.conf include/config/tristate.conf
 	$(Q)$(MAKE) $(build)=$(@)
 
 
-core-y := lib/ kernel/ misc/ net/ boards/ arch/
+core-y := lib/ kernel/ misc/ net/ boards/ arch/ ext/
 drivers-y := drivers/
 
 ifneq ($(strip $(MAKEFILE_APP_DIR)),)
@@ -559,13 +559,6 @@ else
 include/config/auto.conf: ;
 endif # $(dot-config)
 
-ifdef CONFIG_TINYCRYPT
-# Objects we will link into the kernel / subdirs we need to visit
-KCRYPTO_DIR := lib/crypto/tinycrypt
-libs-y += $(KCRYPTO_DIR)/
- ZEPHYRINCLUDE += -I$(srctree)/lib/crypto/tinycrypt/include
-endif
-
 ARCH = $(subst $(DQUOTE),,$(CONFIG_ARCH))
 export ARCH
 ifdef ZEPHYR_GCC_VARIANT
@@ -575,18 +568,17 @@ $(if $(CROSS_COMPILE),, \
      $(error ZEPHYR_GCC_VARIANT is not set. ))
 endif
 
-ifdef CONFIG_QMSI_DRIVERS
-LIB_INCLUDE_DIR += -L$(CONFIG_QMSI_INSTALL_PATH:"%"=%)/lib
-ALL_LIBS += qmsi
-endif
 
-ifdef CONFIG_MINIMAL_LIBC
-ZEPHYRINCLUDE += -I$(srctree)/lib/libc/minimal/include
-endif
+-include $(srctree)/lib/Makefile
+-include $(srctree)/ext/Makefile
 
-ifdef CONFIG_NEWLIB_LIBC
-ZEPHYRINCLUDE += $(TOOLCHAIN_CFLAGS)
-ALL_LIBS += c m
+ifneq ($(CC),)
+ifeq ($(shell $(CC) -v 2>&1 | grep -Ec "clang version|icx version"), 1)
+COMPILER := clang
+else
+COMPILER := gcc
+endif
+export COMPILER
 endif
 
 QEMU_BIN_PATH	?= /usr/bin
@@ -624,6 +616,11 @@ KBUILD_CFLAGS += $(subst $(DQUOTE),,$(CONFIG_COMPILER_OPT))
 
 export LDFLAG_LINKERCMD
 
+ifeq ($(SOC_SERIES),)
+SOC_PATH = $(SOC_NAME)
+else
+SOC_PATH = $(SOC_FAMILY)/$(SOC_SERIES)
+endif
 include arch/$(ARCH)/Makefile
 
 KBUILD_CFLAGS += $(CFLAGS)
@@ -632,7 +629,6 @@ KBUILD_AFLAGS += $(CFLAGS)
 
 
 ifeq ($(COMPILER),clang)
-KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
 KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,)
 KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
 KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
@@ -655,6 +651,7 @@ endif
 
 # arch Makefile may override CC so keep this after arch Makefile is included
 NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
+NOSTDINC_FLAGS += -isystem $(shell $(CC) -print-file-name=include-fixed)
 CHECKFLAGS     += $(NOSTDINC_FLAGS)
 
 # disable pointer signed / unsigned warnings in gcc 4.0
@@ -688,11 +685,12 @@ KBUILD_CFLAGS += $(KCFLAGS)
 
 # Use --build-id when available.
 
+LINKFLAGPREFIX ?= -Wl,
 LDFLAGS_zephyr += $(LDFLAGS)
-LDFLAGS_zephyr += $(call ld-option,-X)
-LDFLAGS_zephyr += $(call ld-option,-N)
-LDFLAGS_zephyr += $(call ld-option,--gc-sections)
-LDFLAGS_zephyr += $(call ld-option,--build-id=none)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)-X)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)-N)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)--gc-sections)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)--build-id=none)
 
 LD_TOOLCHAIN ?= -D__GCC_LINKER_CMD__
 
@@ -700,11 +698,11 @@ ifdef CONFIG_HAVE_CUSTOM_LINKER_SCRIPT
 KBUILD_LDS         := $(subst $(DQUOTE),,$(CONFIG_CUSTOM_LINKER_SCRIPT))
 else
 # Try a board specific linker file
-KBUILD_LDS := $(srctree)/boards/$(BOARD_NAME)/linker.cmd
+KBUILD_LDS := $(srctree)/boards/$(BOARD_NAME)/linker.ld
 
 # If not available, try an SoC specific linker file
 ifeq ($(wildcard $(KBUILD_LDS)),)
-KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/linker.cmd
+KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/linker.ld
 endif
 endif
 
@@ -714,7 +712,7 @@ export LD_TOOLCHAIN KBUILD_LDS
 # command line.
 # This allow a user to issue only 'make' to build a kernel including modules
 # Defaults to zephyr, but the arch makefile usually adds further targets
-all: $(KERNEL_BIN_NAME)
+all: $(KERNEL_BIN_NAME) $(KERNEL_STAT_NAME)
 
 # Default kernel image to build when no specific target is given.
 # KBUILD_IMAGE may be overruled on the command line or
@@ -753,19 +751,21 @@ quiet_cmd_create-lnk = LINK    $@
       cmd_create-lnk =								\
 (										\
 	echo $(LDFLAGS_zephyr); 						\
-	echo "-Map ./$(KERNEL_NAME).map"; 					\
+	echo "$(LINKFLAGPREFIX)-Map=$(O)/$(KERNEL_NAME).map"; 			\
 	echo "-L $(objtree)/include/generated";					\
 	echo "-u _OffsetAbsSyms -u _ConfigAbsSyms"; 				\
 	echo "-e __start"; 						 	\
-	echo "--start-group";							\
-	echo "--whole-archive $(KBUILD_ZEPHYR_APP) --no-whole-archive";         \
+	echo "$(LINKFLAGPREFIX)--start-group";					\
+	echo "$(LINKFLAGPREFIX)--whole-archive";				\
+	echo "$(KBUILD_ZEPHYR_APP)";						\
+	echo "$(LINKFLAGPREFIX)--no-whole-archive";         			\
 	echo "$(KBUILD_ZEPHYR_MAIN)";						\
 	echo "$(objtree)/arch/$(ARCH)/core/offsets/offsets.o"; 			\
-	echo "--end-group"; 							\
+	echo "$(LINKFLAGPREFIX)--end-group"; 					\
 	echo "$(LIB_INCLUDE_DIR) $(LINK_LIBS)";					\
 ) > $@
 
-$(KERNEL_NAME).lnk:
+$(KERNEL_NAME).lnk: $(zephyr-deps)
 	$(call cmd,create-lnk)
 
 linker.cmd: $(zephyr-deps)
@@ -781,7 +781,7 @@ final-linker.cmd: $(zephyr-deps)
 TMP_ELF = .tmp_$(KERNEL_NAME).prebuilt
 
 $(TMP_ELF): $(zephyr-deps) $(KBUILD_ZEPHYR_APP) linker.cmd $(KERNEL_NAME).lnk
-	$(Q)$(LD) -T linker.cmd @$(KERNEL_NAME).lnk -o $@
+	$(Q)$(CC) -T linker.cmd @$(KERNEL_NAME).lnk -o $@
 
 quiet_cmd_gen_idt = SIDT    $@
       cmd_gen_idt =								\
@@ -807,19 +807,29 @@ staticIdt.o: $(TMP_ELF)
 quiet_cmd_lnk_elf = LINK    $@
       cmd_lnk_elf =									\
 (											\
-	$(LD) -T final-linker.cmd @$(KERNEL_NAME).lnk staticIdt.o int_vector_alloc.o 	\
+	$(CC) -T final-linker.cmd @$(KERNEL_NAME).lnk staticIdt.o int_vector_alloc.o 	\
 	irq_int_vector_map.o -o $@;							\
 	${OBJCOPY} --change-section-address intList=${CONFIG_PHYS_LOAD_ADDR} $@ elf.tmp;\
 	$(OBJCOPY) -R intList elf.tmp $@;						\
 	rm elf.tmp									\
 )
 
+ASSERT_WARNING_STR := \
+    "\n      ------------------------------------------------------------" \
+    "\n      --- WARNING:  __ASSERT() statements are globally ENABLED ---" \
+    "\n      --- The kernel will run more slowly and uses more memory ---" \
+    "\n      ------------------------------------------------------------\n\n" \
+
+WARN_ABOUT_ASSERT := $(if $(CONFIG_ASSERT),echo -e -n $(ASSERT_WARNING_STR),true)
+
 ifeq ($(ARCH),x86)
 $(KERNEL_ELF_NAME): staticIdt.o final-linker.cmd
 	$(call cmd,lnk_elf)
+	@$(WARN_ABOUT_ASSERT)
 else
 $(KERNEL_ELF_NAME): $(TMP_ELF)
 	@cp $(TMP_ELF) $(KERNEL_ELF_NAME)
+	@$(WARN_ABOUT_ASSERT)
 endif
 
 
@@ -834,6 +844,14 @@ quiet_cmd_gen_bin = BIN     $@
 $(KERNEL_BIN_NAME): $(KERNEL_ELF_NAME)
 	$(call cmd,gen_bin)
 
+$(KERNEL_STAT_NAME): $(KERNEL_BIN_NAME) $(KERNEL_ELF_NAME)
+	@$(READELF) -e $(KERNEL_ELF_NAME) > $@
+
+ram_report: $(KERNEL_STAT_NAME)
+	@$(srctree)/scripts/size_report -r -o $(O)
+rom_report: $(KERNEL_STAT_NAME)
+	@$(srctree)/scripts/size_report -F -o $(O)
+
 zephyr: $(zephyr-deps) $(KERNEL_BIN_NAME)
 
 # The actual objects are generated when descending,
@@ -1126,16 +1144,21 @@ tools/%: FORCE
 
 QEMU_FLAGS = $(QEMU_FLAGS_$(ARCH)) -pidfile qemu.pid
 
+ifneq ($(QEMU_PTY),)
+    QEMU_FLAGS += -serial pty
+else
 ifneq ($(QEMU_PIPE),)
     # Send console output to a pipe, used for running automated sanity tests
     QEMU_FLAGS += -serial pipe:$(QEMU_PIPE)
 else
     QEMU_FLAGS += -serial mon:stdio
 endif
+endif
 
 qemu: zephyr
 	$(if $(QEMU_PIPE),,@echo "To exit from QEMU enter: 'CTRL+a, x'")
 	@echo '[QEMU] CPU: $(QEMU_CPU_TYPE_$(ARCH))'
+	$(if $(CONFIG_X86_IAMCU),python $(ZEPHYR_BASE)/scripts/qemu-machine-hack.py $(KERNEL_ELF_NAME))
 	$(Q)$(QEMU) $(QEMU_FLAGS) $(QEMU_EXTRA_FLAGS) -kernel $(KERNEL_ELF_NAME)
 
 -include $(srctree)/boards/$(BOARD_NAME)/Makefile.board

Makefile.inc

@@ -6,7 +6,13 @@ DQUOTE = "
 
 ARCH ?= x86
 
+UNAME := $(shell uname)
+ifeq (MINGW, $(findstring MINGW, $(UNAME)))
+PROJECT_BASE ?= $(shell sh -c "pwd -W")
+else
 PROJECT_BASE ?= $(CURDIR)
+endif
+
 O ?= $(PROJECT_BASE)/outdir
 
 # Turn O into an absolute path; we call the main Kbuild with $(MAKE) -C
@@ -24,16 +30,18 @@ KERNEL_TYPE ?= micro
 override CONF_FILE := $(strip $(subst $(DQUOTE),,$(CONF_FILE)))
 
 ifdef BOARD
-KBUILD_DEFCONFIG_PATH=$(ZEPHYR_BASE)/boards/$(BOARD)/$(BOARD)_defconfig
-export KBUILD_DEFCONFIG_PATH
+KBUILD_DEFCONFIG_PATH=$(wildcard $(ZEPHYR_BASE)/boards/*/$(BOARD)_defconfig)
+ifeq ($(KBUILD_DEFCONFIG_PATH),)
+$(error Board $(BOARD) not found!)
+endif
 else
 $(error BOARD is not defined!)
 endif
 
 SOURCE_DIR ?= $(PROJECT_BASE)/src/
-# Kbuild doesn't work correctly if this is an absolute path
-# FIXME Do not depend on python
-override SOURCE_DIR := $(shell python -c "import os.path; print(\"%s\" % os.path.relpath(os.path.realpath('$(SOURCE_DIR)'), os.path.realpath('$(ZEPHYR_BASE)')))")/
+override SOURCE_DIR := $(abspath $(SOURCE_DIR))
+# Kbuild doesn't work correctly if SOURCE_DIR is an absolute path
+override SOURCE_DIR := $(subst $(ZEPHYR_BASE),.,$(SOURCE_DIR))/
 override SOURCE_DIR := $(subst \,/,$(SOURCE_DIR))
 export SOURCE_DIR
 
@@ -52,9 +60,13 @@ else
   S = -s
 endif
 
-zephyrmake	= @+$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) CFLAGS=$(CFLAGS) \
+export CFLAGS
+
+zephyrmake	= @+$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) \
 			PROJECT=$(PROJECT_BASE) SOURCE_DIR=$(SOURCE_DIR) $(2)
 
+BOARDCONFIG = $(O)/.board_$(BOARD)
+
 DOTCONFIG = $(O)/.config
 
 all: $(DOTCONFIG)
@@ -86,6 +98,17 @@ debugserver: FORCE
 
 initconfig: $(DOTCONFIG)
 
+$(BOARDCONFIG):
+	@rm -f $(O)/.board_*
+	@touch $@
+
+
+ram_report: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
+rom_report: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
 menuconfig: initconfig
 	$(Q)$(call zephyrmake,$(O),$@)
 
@@ -98,7 +121,7 @@ help:
 
 KERNEL_CONFIG = $(ZEPHYR_BASE)/kernel/configs/$(KERNEL_TYPE).config
 
-$(DOTCONFIG): $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
+$(DOTCONFIG): $(BOARDCONFIG) $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
 	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/kconfig/merge_config.sh \
 		-q -m -O $(O) $(KBUILD_DEFCONFIG_PATH) $(KERNEL_CONFIG) $(CONF_FILE)
 	$(Q)$(MAKE) $(S) -C $(ZEPHYR_BASE) O=$(O) PROJECT=$(PROJECT_BASE) oldnoconfig

arch/Kconfig

@@ -31,26 +31,70 @@ config ARM
 config X86
 	bool "x86 architecture"
 	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
-	select ADVANCED_IDLE_SUPPORTED
+
+config NIOS2
+	bool "Nios II Gen 2 architecture"
 
 endchoice
 
+#
+# Hidden PM feature configs which are to be selected by
+# individual SoC.
+#
+config SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	# Hidden
+	bool
+	default n
+	help
+	This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
+	configuration option.
+
+config SYS_POWER_DEEP_SLEEP_SUPPORTED
+	# Hidden
+	bool
+	default n
+	help
+	This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
+	configuration option.
+#
+# End hidden PM feature configs
+#
+
 config ARCH
 	string
 	help
 	System architecture string.
 
 config SOC
-        string
-        help
-        This option holds the directory name used by the build system to locate
-        the correct linker file.
+	string
+	help
+	SoC name which can be found under arch/<arch>/soc/<soc name>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files for the SoC. This option will go away
+	once all SoCs are using family/series structure.
+
+config SOC_SERIES
+	string
+	help
+	SoC series name which can be found under arch/<arch>/soc/<family>/<series>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
+
+config SOC_FAMILY
+	string
+	help
+	SoC family name which can be found under arch/<arch>/soc/<family>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
 
 config BOARD
 	string
 	help
 	This option holds the name of the board and is used to located the files
-	related to the board in the source tree.
+	related to the board in the source tree (under boards/).
+	The Board is the first location where we search for a linker.ld file,
+	if not found we look for the linker file in
+	arch/<arch>/soc/<family>/<series>
 
 source "arch/*/Kconfig"
 

arch/Makefile

@@ -1,9 +1 @@
-ifeq (${ARCH},arm)
-obj-y += arm/
-endif
-ifeq (${ARCH},x86)
-obj-y += x86/
-endif
-ifeq (${ARCH},arc)
-obj-y += arc/
-endif
+obj-y += $(ARCH)/

arch/arc/Kbuild

@@ -2,5 +2,5 @@ subdir-ccflags-y +=-I$(srctree)/include/drivers
 subdir-ccflags-y +=-I$(srctree)/drivers
 subdir-asflags-y += $(subdir-ccflags-y)
 
-obj-y += soc/$(SOC_NAME)/
+obj-y += soc/$(SOC_PATH)/
 obj-y += core/

arch/arc/Kconfig

@@ -15,7 +15,16 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 #
-menu "ARC architecture"
+
+choice
+	prompt "ARC SoC Selection"
+	depends on ARC
+
+	source "arch/arc/soc/*/Kconfig.soc"
+endchoice
+
+
+menu "ARC Options"
 	depends on ARC
 
 config ARCH
@@ -25,17 +34,13 @@ config ARCH_DEFCONFIG
 	string
 	default "arch/arc/defconfig"
 
-choice
-prompt "SoC Selection"
-source "arch/arc/soc/*/Kconfig.soc"
-endchoice
-
 menu "ARC EM4 processor options"
 
 config	CPU_ARCEM4
 	bool
 	default y
 	select CPU_ARCV2
+	select ATOMIC_OPERATIONS_C
 	help
 	This option signifies the use of an ARC EM4 CPU
 
@@ -50,14 +55,6 @@ config	CPU_ARCV2
 	help
 	  This option signifies the use of a CPU of the ARCv2 family.
 
-config RAM_START
-	prompt "RAM start address"
-	hex
-
-config RAM_SIZE
-	prompt "RAM size (in kB)"
-	int
-
 config NSIM
 	prompt "Running on the MetaWare nSIM simulator"
 	bool
@@ -68,8 +65,6 @@ config NSIM
 	  a) Uses non-XIP to run in RAM.
 	  b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
 	     a pc_size of 16 (default).
-	  c) Sets the entry point to __reset, since it seems nSIM ignores the
-	     reset vector when starting (??).
 
 config	DATA_ENDIANNESS_LITTLE
 	bool
@@ -126,6 +121,14 @@ config	FIRQ_STACK_SIZE
 	  FIRQs and regular IRQs have different stacks so that a FIRQ can start
 	  running without doing stack switching in software.
 
+config	ARC_STACK_CHECKING
+	bool "Enable Stack Checking"
+	depends on CPU_ARCV2
+	default n
+	help
+	  ARCV2 has a special feature allowing to check stack overflows. This
+	  enables code that allows using this debug feature
+
 config	FAULT_DUMP
 	int
 	prompt "Fault dump level"
@@ -152,20 +155,71 @@ config	XIP
 	default n if NSIM
 	default y
 
-config NSIM
-	prompt "Running on the MetaWare nSIM simulator"
+config HARVARD
+	prompt "Harvard Architecture"
 	bool
 	default n
 	help
-	For running on nSIM simulator.
+	  The ARC CPU can be configured to have two busses;
+	  one for instruction fetching and another that serves as a data bus.
 
-	a) Uses non-XIP to run in RAM.
-	b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
-	   a pc_size of 16 (default).
-	c) Sets the entry point to __reset, since it seems nSIM ignores the
-	   reset vector when starting.
+config ICCM_SIZE
+	int "ICCM Size in kB"
+	help
+	This option specifies the size of the ICCM in kB.  It is normally set by
+	the platform's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
 
-config  SW_ISR_TABLE
+config ICCM_BASE_ADDRESS
+	hex "ICCM Base Address"
+	help
+	This option specifies the base address of the ICCM on the platform.  It is
+	normally set by the platform's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config DCCM_SIZE
+	int "DCCM Size in kB"
+	help
+	This option specifies the size of the DCCM in kB.  It is normally set by
+	the platform's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config DCCM_BASE_ADDRESS
+	hex "DCCM Base Address"
+	help
+	This option specifies the base address of the DCCM on the platform.  It is
+	normally set by the platform's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config SRAM_SIZE
+	int "SRAM Size in kB"
+	help
+	This option specifies the size of the SRAM in kB.  It is normally set by
+	the platform's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config SRAM_BASE_ADDRESS
+	hex "SRAM Base Address"
+	help
+	This option specifies the base address of the SRAM on the platform.  It is
+	normally set by the platform's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config FLASH_SIZE
+	int "Flash Size in kB"
+	help
+	This option specifies the size of the flash in kB.  It is normally set by
+	the platform's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config FLASH_BASE_ADDRESS
+	hex "Flash Base Address"
+	help
+	This option specifies the base address of the flash on the platform.  It is
+	normally set by the platform's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config SW_ISR_TABLE
 	bool
 	prompt "Enable software interrupt handler table"
 	default y
@@ -178,7 +232,7 @@ config  SW_ISR_TABLE
 	  This has to be enabled for dynamically connecting interrupt handlers
 	  at runtime (SW_ISR_TABLE_DYNAMIC).
 
-config  SW_ISR_TABLE_DYNAMIC
+config SW_ISR_TABLE_DYNAMIC
 	bool
 	prompt "Allow installing interrupt handlers at runtime"
 	depends on SW_ISR_TABLE
@@ -188,25 +242,7 @@ config  SW_ISR_TABLE_DYNAMIC
 	  SRAM so that it is writable. This has the side-effect of removing
 	  write-protection on the ISR table.
 
-config  SW_ISR_TABLE_STATIC_CUSTOM
-	bool
-	prompt "Projects provide a custom static software ISR table"
-	depends on SW_ISR_TABLE && !SW_ISR_TABLE_DYNAMIC
-	default n
-	help
-	  Projects, not the BSP, provide a software table of ISR and their
-	  parameters. The table is static, and thus ISRs cannot be connected
-	  at runtime.
-
-config	SW_ISR_TABLE_BSP
-	bool
-	# omit prompt to signify a "hidden" option
-	depends on SW_ISR_TABLE_DYNAMIC || (SW_ISR_TABLE && !SW_ISR_TABLE_STATIC_CUSTOM)
-	default y
-	help
-	  Not user-selectable, helps build system logic.
-
-config  IRQ_VECTOR_TABLE_CUSTOM
+config IRQ_VECTOR_TABLE_CUSTOM
 	bool
 	prompt "Projects provide a custom static IRQ part of vector table"
 	depends on !SW_ISR_TABLE
@@ -236,29 +272,16 @@ config	IRQ_VECTOR_TABLE_BSP
 	help
 	  Not user-selectable, helps build system logic.
 
-config  ARCH_HAS_TASK_ABORT
+config ARCH_HAS_TASK_ABORT
 	bool
 	# omit prompt to signify a "hidden" option
 	default n
 
-config  ARCH_HAS_NANO_FIBER_ABORT
+config ARCH_HAS_NANO_FIBER_ABORT
 	bool
 	# omit prompt to signify a "hidden" option
 	default n
 
-config  ARC_ATOMIC_ASM
-	bool
-	default n
-	depends on !CPU_ARCEM4
-	help
-	  Say y if the processor supports atomic assembly instructions:
-	  LLOCK and SCOND.
-
-	  Say n if not sure.
-
-	  Note that these instructions are not supported on ARC EM family
-	  processors.
-
 endmenu
 
 

arch/arc/Makefile

@@ -1,8 +1,15 @@
 cflags-y += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
+cflags-$(CONFIG_ARC_STACK_CHECKING) = $(call cc-option,-fomit-frame-pointer)
 cflags-$(CONFIG_LTO) = $(call cc-option,-flto,)
 
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/Makefile
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 
 KBUILD_CFLAGS += $(cflags-y)
 KBUILD_CXXFLAGS += $(cflags-y)
 
+soc-cxxflags ?= $(soc-cflags)
+soc-aflags ?= $(soc-cflags)
+KBUILD_CFLAGS += $(soc-cflags)
+KBUILD_CXXFLAGS += $(soc-cxxflags)
+KBUILD_AFLAGS += $(soc-aflags)
+

arch/arc/core/Makefile

@@ -13,10 +13,10 @@ obj-y += prep_c.o \
          vector_table.o
 
 obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
-obj-$(CONFIG_ERRNO) += errno.o
 
-ifeq ($(CONFIG_ARC_ATOMIC_ASM),y)
+ifneq ($(CONFIG_ATOMIC_OPERATIONS_C),y)
 obj-y += atomic.o
-else
-obj-y += atomic_native.o
 endif
+
+obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
+obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o

arch/arc/core/cpu_idle.S

@@ -61,12 +61,17 @@ SECTION_VAR(BSS, nano_cpu_sleep_mode)
 
 SECTION_FUNC(TEXT, nano_cpu_idle)
 
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+	push_s blink
+	jl    _sys_k_event_logger_enter_sleep
+	pop_s blink
+#endif
 	enter_tickless_idle
 
 	ld r1, [nano_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
-	j_s.nd [blink]
+	j_s [blink]
 	nop
 
 /*
@@ -78,6 +83,12 @@ SECTION_FUNC(TEXT, nano_cpu_idle)
  */
 SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
 
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+	push_s blink
+	jl    _sys_k_event_logger_enter_sleep
+	pop_s blink
+#endif
+
 	enter_tickless_idle
 
 	ld r1, [nano_cpu_sleep_mode]

arch/arc/core/fast_irq.S

@@ -45,14 +45,16 @@ SECTION_VAR(NOINIT, _firq_stack)
  *
  * The processor switches to a second register bank so registers from the
  * current bank do not have to be preserved yet. The only issue is the LP_START/
- * LP_COUNT/LP_END registers, which are not banked.
+ * LP_COUNT/LP_END registers, which are not banked. These can be saved
+ * in available callee saved registers.
  *
  * If all FIRQ ISRs are programmed such that there are no use of the LP
- * registers (ie. no LPcc instruction), then the kernel can be configured to
- * remove the use of _firq_enter().
+ * registers (ie. no LPcc instruction), and CONFIG_ARC_STACK_CHECKING is
+ * not set, then the kernel can be configured to not save and restore them.
  *
  * When entering a FIRQ, interrupts might as well be locked: the processor is
- * running at its highest priority, and cannot be preempted by anything.
+ * running at its highest priority, and cannot be interrupted by any other
+ * interrupt. An exception, however, can be taken.
  *
  * Assumption by _isr_demux: r3 is untouched by _firq_enter.
  *
@@ -61,24 +63,27 @@ SECTION_VAR(NOINIT, _firq_stack)
 
 SECTION_FUNC(TEXT, _firq_enter)
 
-#ifndef CONFIG_FIRQ_NO_LPCC
 	/*
-	 * Unlike the rest of context switching code, r2 is loaded with something
-	 * else than 'current' in this routine: this is to preserve r3 so that it
-	 * does not have to be fetched again in _isr_demux.
+	 * ATTENTION:
+	 * firq uses a 2nd register bank so GPRs do not need to be saved.
 	 */
 
-	/* save LP_START/LP_COUNT/LP_END variables */
-	mov_s r1, _nanokernel
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+#endif
 
-	/* cannot store lp_count directly to memory */
-	mov r2, lp_count
-	st lp_count, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_count_OFFSET]
-
-	lr r2, [_ARC_V2_LP_START]
-	st r2, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_start_OFFSET]
-	lr r2, [_ARC_V2_LP_END]
-	st r2, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_end_OFFSET]
+#ifndef CONFIG_FIRQ_NO_LPCC
+	/*
+	 * Save LP_START/LP_COUNT/LP_END because called handler might use.
+	 * Save these in callee saved registers to avoid using memory.
+	 * These will be saved by the compiler if it needs to spill them.
+	 */
+	mov r23,lp_count
+	lr r24, [_ARC_V2_LP_START]
+	lr r25, [_ARC_V2_LP_END]
 #endif
 
 	j @_isr_demux
@@ -92,30 +97,19 @@ SECTION_FUNC(TEXT, _firq_enter)
 
 SECTION_FUNC(TEXT, _firq_exit)
 
+#ifndef CONFIG_FIRQ_NO_LPCC
+	/* restore lp_count, lp_start, lp_end from r23-r25 */
+	mov lp_count,r23
+	sr r24, [_ARC_V2_LP_START]
+	sr r25, [_ARC_V2_LP_END]
+#endif
+
 	mov_s r1, _nanokernel
 	ld_s r2, [r1, __tNANO_current_OFFSET]
 
-#ifndef CONFIG_FIRQ_NO_LPCC
-
-	/* assumption: r1 contains _nanokernel, r2 contains the current thread */
-
-	/* restore LP_START/LP_COUNT/LP_END variables */
-
-	/* cannot load lp_count from memory */
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_count_OFFSET]
-	mov lp_count, r3
-
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_start_OFFSET]
-	sr r3, [_ARC_V2_LP_START]
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_end_OFFSET]
-	sr r3, [_ARC_V2_LP_END]
-
-	/* exiting here: r1/r2 unchanged, r0/r3 destroyed */
-#endif
-
 #if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
-	/* check if we're a nested interrupt: if so, let the interrupted interrupt
-	 * handle the reschedule */
+	/* check if we're a nested interrupt: if so, let the interrupted
+	 * interrupt handle the reschedule */
 
 	lr r3, [_ARC_V2_AUX_IRQ_ACT]
 
@@ -124,7 +118,7 @@ SECTION_FUNC(TEXT, _firq_exit)
 	 * means that another bit is set so an interrupt was interrupted.
 	 */
 
-	breq.nd r3, 1, _check_if_current_is_the_task
+	breq r3, 1, _check_if_current_is_the_task
 
 	rtie
 
@@ -133,15 +127,15 @@ SECTION_FUNC(TEXT, _firq_exit)
 .balign 4
 _check_if_current_is_the_task:
 
-	ld r0, [r2, __tTCS_flags_OFFSET]
+	ld_s r0, [r2, __tTCS_flags_OFFSET]
 	and.f r0, r0, PREEMPTIBLE
-	bnz.nd _check_if_a_fiber_is_ready
+	bnz _check_if_a_fiber_is_ready
 	rtie
 
 .balign 4
 _check_if_a_fiber_is_ready:
-	ld r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
-	brne.nd r0, 0, _firq_reschedule
+	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
+	brne r0, 0, _firq_reschedule
 	rtie
 
 .balign 4
@@ -172,29 +166,36 @@ _firq_reschedule:
 	st ilink, [sp, __tISF_pc_OFFSET] /* ilink into pc */
 
 	mov_s r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 
 	_save_callee_saved_regs
 
 	st _CAUSE_FIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	ld r2, [r1, __tNANO_fiber_OFFSET]
+	ld_s r2, [r1, __tNANO_fiber_OFFSET]
 
-	st r2, [r1, __tNANO_current_OFFSET]
-	ld r3, [r2, __tTCS_link_OFFSET]
-	st r3, [r1, __tNANO_fiber_OFFSET]
+	st_s r2, [r1, __tNANO_current_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
+	st_s r3, [r1, __tNANO_fiber_OFFSET]
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* Use stack top and down registers from restored context */
+	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	sr r3, [_ARC_V2_KSTACK_TOP]
+	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
+	sr r3, [_ARC_V2_KSTACK_BASE]
+#endif
 	/*
 	 * _load_callee_saved_regs expects incoming thread in r2.
 	 * _load_callee_saved_regs restores the stack pointer.
 	 */
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	breq.nd r3, _CAUSE_RIRQ, _firq_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _firq_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _firq_return_from_firq
+	breq r3, _CAUSE_FIRQ, _firq_return_from_firq
 	nop
 
 	/* fall through */
@@ -202,7 +203,7 @@ _firq_reschedule:
 .balign 4
 _firq_return_from_coop:
 
-	ld r3, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r3, [r2, __tTCS_intlock_key_OFFSET]
 	st  0, [r2, __tTCS_intlock_key_OFFSET]
 
 	/* pc into ilink */
@@ -213,15 +214,15 @@ _firq_return_from_coop:
 	/*
 	 * There are only two interrupt lock states: locked and unlocked. When
 	 * entering _Swap(), they are always locked, so the IE bit is unset in
-	 * status32. If the incoming thread had them locked recursively, it means
-	 * that the IE bit should stay unset. The only time the bit has to change
-	 * is if they were not locked recursively.
+	 * status32. If the incoming thread had them locked recursively, it
+	 * means that the IE bit should stay unset. The only time the bit
+	 * has to change is if they were not locked recursively.
 	 */
 	and.f r3, r3, (1 << 4)
 	or.nz r0, r0, _ARC_V2_STATUS32_IE
 	sr r0, [_ARC_V2_STATUS32_P0]
 
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, __tTCS_return_value_OFFSET]
 	rtie
 
 .balign 4
@@ -267,4 +268,4 @@ SECTION_FUNC(TEXT, _firq_stack_setup)
 	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
 	kflag r0
 
-	j_s.nd [blink]
+	j_s [blink]

arch/arc/core/fault_s.S

@@ -49,6 +49,15 @@ GDATA(_firq_stack)
 SECTION_VAR(BSS, saved_stack_pointer)
 	.word 0
 
+#if CONFIG_NUM_IRQ_PRIO_LEVELS == 1
+#error "NUM_IRQ_PRIO_LEVELS==1 is not supported."
+/* The code below sets bit 1 in AUX_IRQ_ACT and thus requires
+ * priority 0 and 1 at a minimum. Supporting only 1 priority
+ * requires a change to this file but also changes to make
+ * FIRQ optional.
+ */
+#endif
+
 /*
  * @brief Fault handler installed in the fault and reserved vectors
  */
@@ -78,6 +87,15 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 	 * a diagnostic message and halt.
 	 */
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	push_s r2
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+	pop_s r2
+#endif
+
 	st sp, [saved_stack_pointer]
 	mov_s sp, _firq_stack
 	add sp, sp, CONFIG_FIRQ_STACK_SIZE
@@ -85,6 +103,11 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, __tISF_status32_OFFSET]
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, __tISF_pc_OFFSET] /* eret into pc */
+
 	jl _Fault
 
 	/* if _Fault returns, restore the registers */
@@ -102,24 +125,102 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	 * Before invoking exception handler, the kernel switches to an exception
 	 * stack, which is really the FIRQ stack, to save the faulting thread's
 	 * registers. It can use the FIRQ stack because it knows it is unused
-	 * since it is save to assume that if an exception has happened in FIRQ
+	 * since it is safe to assume that if an exception has happened in FIRQ
 	 * handler, the problem is fatal and all the kernel can do is just print
 	 * a diagnostic message and halt.
 	 */
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	push_s r2
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+	pop_s r2
+#endif
+
+#ifndef CONFIG_MICROKERNEL
 	st sp, [saved_stack_pointer]
 	mov_s sp, _firq_stack
 	add sp, sp, CONFIG_FIRQ_STACK_SIZE
+#endif
 
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, __tISF_status32_OFFSET]
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, __tISF_pc_OFFSET] /* eret into pc */
+
 	jl _irq_do_offload
 
+#ifdef CONFIG_MICROKERNEL
+	mov_s r1, _nanokernel
+	ld_s r2, [r1, __tNANO_current_OFFSET]
+#if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
+	/* check if we're a nested interrupt: if so, let the
+	 * interrupted interrupt handle the reschedule
+	 */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
+	 * AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is 0, it
+	 * means trap was taken from outside an interrupt handler.
+	 * But if it was inside, let that handler do the swap.
+	 */
+	breq r3, 0, _trap_check_for_swap
+_trap_return:
+	_pop_irq_stack_frame
+	rtie
+#endif
+
+.balign 4
+_trap_check_for_swap:
+	ld_s r0, [r2, __tTCS_flags_OFFSET]
+	and.f r0, r0, PREEMPTIBLE
+	bnz _e_check_if_a_fiber_is_ready
+	b _trap_return
+
+.balign 4
+_e_check_if_a_fiber_is_ready:
+	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
+	brne r0, 0, _trap_reschedule
+	b _trap_return
+
+.balign 4
+_trap_reschedule:
+
+	_save_callee_saved_regs
+
+	st _CAUSE_RIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
+	/* note: Ok to use _CAUSE_RIRQ since everything is saved */
+
+	ld_s r2, [r1, __tNANO_fiber_OFFSET]
+
+	st_s r2, [r1, __tNANO_current_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
+	st_s r3, [r1, __tNANO_fiber_OFFSET]
+
+	/* clear AE bit to forget this was an exception */
+	lr r3, [_ARC_V2_STATUS32]
+	and r3,r3,(~_ARC_V2_STATUS32_AE)
+	kflag r3
+ 	/* pretend priority 1 int happened to use common handler */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	or r3,r3,2
+	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+
+	/* Assumption: r2 has current thread */
+	b _rirq_common_interrupt_swap
+#else
+	/* Nanokernel-only just returns from exception */
+
 	/* if _Fault returns, restore the registers */
 	_pop_irq_stack_frame
 
 	/* now restore the stack */
 	ld sp,[saved_stack_pointer]
 	rtie
+#endif
+
 #endif /* CONFIG_IRQ_OFFLOAD */

arch/arc/core/isr_wrapper.S

@@ -209,7 +209,38 @@ SECTION_FUNC(TEXT, _isr_enter)
 	mov.nz r3, _rirq_exit
 	mov.nz r2, _rirq_enter
 
-	j_s.nd [r2]
+	j_s [r2]
+
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+GTEXT(_sys_k_event_logger_exit_sleep)
+
+.macro log_sleep_k_event
+	clri r0 /* do not interrupt event logger operations */
+	push_s r0
+	push_s blink
+	jl _sys_k_event_logger_exit_sleep
+	pop_s blink
+	pop_s r0
+	seti r0
+.endm
+#else
+	#define log_sleep_k_event
+#endif
+#if defined(CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT)
+GTEXT(_sys_k_event_logger_interrupt)
+
+.macro log_interrupt_k_event
+	clri r0 /* do not interrupt event logger operations */
+	push_s r0
+	push_s blink
+	jl _sys_k_event_logger_interrupt
+	pop_s blink
+	pop_s r0
+	seti r0
+.endm
+#else
+	#define log_interrupt_k_event
+#endif
 
 #if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
 .macro exit_tickless_idle
@@ -232,6 +263,8 @@ SECTION_FUNC(TEXT, _isr_demux)
 	/* cannot be done before this point because we must be able to run C */
 	/* r0 is available to be stomped here, and exit_tickless_idle uses it */
 	exit_tickless_idle
+	log_interrupt_k_event
+	log_sleep_k_event
 
 	lr r0, [_ARC_V2_ICAUSE]
 	sub r0, r0, 16
@@ -239,11 +272,11 @@ SECTION_FUNC(TEXT, _isr_demux)
 	mov r1, _sw_isr_table
 	add3 r0, r1, r0   /* table entries are 8-bytes wide */
 
-	ld r1, [r0, 4] /* ISR into r1 */
+	ld_s r1, [r0, 4] /* ISR into r1 */
 	jl_s.d [r1]
 	ld_s r0, [r0] /* delay slot: ISR parameter into r0  */
 
 	/* back from ISR, jump to exit stub */
 	pop_s r3
-	j_s.nd [r3]
+	j_s [r3]
 	nop

arch/arc/core/offsets/offsets.c

@@ -39,15 +39,17 @@
 
 /* ARCv2-specific tNANO structure member offsets */
 GEN_OFFSET_SYM(tNANO, rirq_sp);
-GEN_OFFSET_SYM(tNANO, firq_regs);
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 GEN_OFFSET_SYM(tNANO, idle);
-#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
+#endif
 
 /* ARCv2-specific struct tcs structure member offsets */
 GEN_OFFSET_SYM(tTCS, intlock_key);
 GEN_OFFSET_SYM(tTCS, relinquish_cause);
 GEN_OFFSET_SYM(tTCS, return_value);
+#ifdef CONFIG_ARC_STACK_CHECKING
+GEN_OFFSET_SYM(tTCS, stack_top);
+#endif
 #ifdef CONFIG_THREAD_CUSTOM_DATA
 GEN_OFFSET_SYM(tTCS, custom_data);
 #endif
@@ -99,12 +101,6 @@ GEN_OFFSET_SYM(tCalleeSaved, fp);
 GEN_OFFSET_SYM(tCalleeSaved, r30);
 GEN_ABSOLUTE_SYM(__tCalleeSaved_SIZEOF, sizeof(tCalleeSaved));
 
-/* ARCv2-specific registers-saved-in-FIRQ structure member offsets */
-GEN_OFFSET_SYM(tFirqRegs, lp_count);
-GEN_OFFSET_SYM(tFirqRegs, lp_start);
-GEN_OFFSET_SYM(tFirqRegs, lp_end);
-GEN_ABSOLUTE_SYM(__tFirqRegs_SIZEOF, sizeof(tFirqRegs));
-
 /* size of the struct tcs structure sans save area for floating point regs */
 GEN_ABSOLUTE_SYM(__tTCS_NOFLOAT_SIZEOF, sizeof(tTCS));
 

arch/arc/core/prep_c.c

@@ -29,6 +29,7 @@
 #include <stdint.h>
 #include <toolchain.h>
 #include <linker-defs.h>
+#include <arch/arc/v2/aux_regs.h>
 
 /**
  *
@@ -75,6 +76,82 @@ static void dataCopy(void)
 }
 #endif
 
+
+/**
+ *
+ * @brief Disable the i-cache if present
+ *
+ * For those ARC CPUs that have a i-cache present,
+ * invalidate the i-cache and then disable it.
+ *
+ * @return N/A
+ */
+
+static void disable_icache(void)
+{
+	unsigned int val;
+
+	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
+	val &= 0xff; /* version field */
+	if (val == 0) {
+		return; /* skip if i-cache is not present */
+	}
+	_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0);
+	__asm__ __volatile__ ("nop");
+	_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1);
+}
+
+/**
+ *
+ * @brief Invalidate the data cache if present
+ *
+ * For those ARC CPUs that have a data cache present,
+ * invalidate the data cache.
+ *
+ * @return N/A
+ */
+
+static void invalidate_dcache(void)
+{
+	unsigned int val;
+
+	val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+	val &= 0xff; /* version field */
+	if (val == 0) {
+		return; /* skip if d-cache is not present */
+	}
+	_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
+}
+
+
+/**
+ *
+ * @brief Adjust the vector table base
+ *
+ * Set the vector table base if the value found in the
+ * _ARC_V2_IRQ_VECT_BASE auxiliary register is different from the
+ * _VectorTable known by software. It is important to do this very early
+ * so that exception vectors can be handled.
+ *
+ * @return N/A
+ */
+
+static void adjust_vector_table_base(void)
+{
+	extern struct vector_table _VectorTable;
+	unsigned int vbr;
+	/* if the compiled-in vector table is different
+	 * from the base address known by the ARC CPU,
+	 * set the vector base to the compiled-in address.
+	 */
+	vbr = _arc_v2_aux_reg_read(_ARC_V2_IRQ_VECT_BASE);
+	vbr &= 0xfffffc00;
+	if (vbr != (unsigned int)&_VectorTable) {
+		_arc_v2_aux_reg_write(_ARC_V2_IRQ_VECT_BASE,
+					(unsigned int)&_VectorTable);
+	}
+}
+
 extern FUNC_NORETURN void _Cstart(void);
 /**
  *
@@ -87,6 +164,9 @@ extern FUNC_NORETURN void _Cstart(void);
 
 void _PrepC(void)
 {
+	disable_icache();
+	invalidate_dcache();
+	adjust_vector_table_base();
 	bssZero();
 	dataCopy();
 	_Cstart();

arch/arc/core/regular_irq.S

@@ -34,6 +34,16 @@
 
 GTEXT(_rirq_enter)
 GTEXT(_rirq_exit)
+GTEXT(_rirq_common_interrupt_swap)
+
+#if CONFIG_NUM_IRQ_PRIO_LEVELS > 2
+#error "NUM_IRQ_PRIO_LEVELS>2 is not supported."
+/*
+ * Nesting of Regularing interrupts is not yet supported.
+ * If your SOC supports more than 2, set this value to 2.
+ */
+#endif
+
 
 /**
  *
@@ -51,7 +61,13 @@ GTEXT(_rirq_exit)
 SECTION_FUNC(TEXT, _rirq_enter)
 
 	mov r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+#endif
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 #if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS == 1
 	st sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 	ld sp, [r1, __tNANO_rirq_sp_OFFSET]
@@ -71,7 +87,7 @@ SECTION_FUNC(TEXT, _rirq_enter)
 SECTION_FUNC(TEXT, _rirq_exit)
 
 	mov r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 
 #if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS > 1
 	/* check if we're a nested interrupt: if so, let the interrupted interrupt
@@ -89,7 +105,7 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	 */
 
 	cmp r0, r3
-	brgt.nd _rirq_return_from_rirq
+	brgt _rirq_return_from_rirq
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 #endif
 
@@ -102,12 +118,12 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	 * b) needs to load it to restore the interrupted context.
 	 */
 
-	ld r0, [r2, __tTCS_flags_OFFSET]
+	ld_s r0, [r2, __tTCS_flags_OFFSET]
 	and.f r0, r0, PREEMPTIBLE
 	bz.d _rirq_no_reschedule
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 
-	ld r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
+	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
 	cmp r0, 0
 	bz.d _rirq_no_reschedule
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
@@ -122,21 +138,31 @@ _rirq_reschedule:
 
 	/* incoming fiber is in r0: it becomes the new 'current' */
 	mov r2, r0
-	st r2, [r1, __tNANO_current_OFFSET]
-	ld r3, [r2, __tTCS_link_OFFSET]
-	st r3, [r1, __tNANO_fiber_OFFSET]
+	st_s r2, [r1, __tNANO_current_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
+	st_s r3, [r1, __tNANO_fiber_OFFSET]
 
+_rirq_common_interrupt_swap:
+	/* r2 contains pointer to new thread */
+
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* Use stack top and down registers from restored context */
+	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	sr r3, [_ARC_V2_KSTACK_TOP]
+	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
+	sr r3, [_ARC_V2_KSTACK_BASE]
+#endif
 	/*
 	 * _load_callee_saved_regs expects incoming thread in r2.
 	 * _load_callee_saved_regs restores the stack pointer.
 	 */
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	breq.nd r3, _CAUSE_RIRQ, _rirq_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _rirq_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _rirq_return_from_firq
+	breq r3, _CAUSE_FIRQ, _rirq_return_from_firq
 	nop
 
 	/* fall through */
@@ -147,12 +173,12 @@ _rirq_return_from_coop:
 	/* status32 and pc (blink) are already on the stack in the right order */
 
 	/* update status32.ie (explanation in firq_exit:_firq_return_from_coop) */
-	ld r0, [sp, 4]
-	ld r3, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r0, [sp, 4]
+	ld_s r3, [r2, __tTCS_intlock_key_OFFSET]
 	st  0, [r2, __tTCS_intlock_key_OFFSET]
 	cmp r3, 0
 	or.ne r0, r0, _ARC_V2_STATUS32_IE
-	st r0, [sp, 4]
+	st_s r0, [sp, 4]
 
 	/* carve fake stack */
 
@@ -160,7 +186,7 @@ _rirq_return_from_coop:
 	                                  * b) a real value will be pushed in r0 */
 
 	/* push return value on stack */
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, __tTCS_return_value_OFFSET]
 	push_s r0
 
 	/*
@@ -169,7 +195,7 @@ _rirq_return_from_coop:
 	 * IRQ prologue. r13 thus has to be set to its correct value in the IRQ
 	 * stack frame.
 	 */
-	st r13, [sp, __tISF_r13_OFFSET]
+	st_s r13, [sp, __tISF_r13_OFFSET]
 
 	/* stack now has the IRQ stack frame layout, pointing to r0 */
 

arch/arc/core/reset.S

@@ -28,9 +28,15 @@
 #include <sections.h>
 #include <arch/cpu.h>
 
-#define _RAM_END (CONFIG_RAM_START + CONFIG_RAM_SIZE * 1024)
+#ifdef CONFIG_HARVARD
+#define _TOP_OF_MEMORY (CONFIG_DCCM_BASE_ADDRESS + CONFIG_DCCM_SIZE * 1024)
+/* harvard places the initial stack in the dccm memory */
+#else
+#define _TOP_OF_MEMORY (CONFIG_SRAM_BASE_ADDRESS + CONFIG_SRAM_SIZE * 1024)
+#endif
 
 GTEXT(__reset)
+GTEXT(__start)
 
 /**
  *
@@ -47,11 +53,12 @@ GTEXT(__reset)
  */
 
 SECTION_FUNC(TEXT,__reset)
+SECTION_FUNC(TEXT,__start)
 
 	/* lock interrupts: will get unlocked when switch to main task */
 	clri
 
-	/* setup a stack at the end of the RAM */
-	mov sp, _RAM_END
+	/* setup a stack at the end of MEMORY */
+	mov sp, _TOP_OF_MEMORY
 
 	j @_PrepC

arch/arc/core/swap.S

@@ -74,10 +74,10 @@ SECTION_FUNC(TEXT, _Swap)
 	/* interrupts are locked, interrupt key is in r0 */
 
 	mov r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 
 	/* save intlock key */
-	st r0, [r2, __tTCS_intlock_key_OFFSET]
+	st_s r0, [r2, __tTCS_intlock_key_OFFSET]
 	st _CAUSE_COOP, [r2, __tTCS_relinquish_cause_OFFSET]
 
 	/*
@@ -86,24 +86,29 @@ SECTION_FUNC(TEXT, _Swap)
 	 */
 	lr r3, [_ARC_V2_STATUS32]
 	push_s r3
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* disable stack checking during swap */
+	bclr r3, r3, _ARC_V2_STATUS32_SC_BIT
+	kflag r3
+#endif
 	push_s blink
 
 	_save_callee_saved_regs
 
-	ld r2, [r1, __tNANO_fiber_OFFSET]
-	breq.nd r2, 0, _swap_to_the_task
+	ld_s r2, [r1, __tNANO_fiber_OFFSET]
+	breq r2, 0, _swap_to_the_task
 
 .balign 4
 _swap_to_a_fiber:
 
-	ld r3, [r2, __tTCS_link_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
 	b.d _finish_swapping_to_thread    /* always execute delay slot */
-	st r3, [r1, __tNANO_fiber_OFFSET] /* delay slot */
+	st_s r3, [r1, __tNANO_fiber_OFFSET] /* delay slot */
 
 .balign 4
 _swap_to_the_task:
 
-	ld r2, [r1, __tNANO_task_OFFSET]
+	ld_s r2, [r1, __tNANO_task_OFFSET]
 
 	/* fall through */
 
@@ -115,20 +120,26 @@ _finish_swapping_to_thread:
 #if 0
 /* don't save flags in tNANO: slower, error-prone, and might not even give
  * a speed boost where it's supposed to */
-	ld r3, [r2, __tTCS_flags_OFFSET]
-	st r3, [r1, __tNANO_flags_OFFSET]
+	ld_s r3, [r2, __tTCS_flags_OFFSET]
+	st_s r3, [r1, __tNANO_flags_OFFSET]
+#endif
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* Use stack top and down registers from restored context */
+	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	sr r3, [_ARC_V2_KSTACK_TOP]
+	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
+	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
-
 	/* XXX - can be moved to delay slot of _CAUSE_RIRQ ? */
-	st r2, [r1, __tNANO_current_OFFSET]
+	st_s r2, [r1, __tNANO_current_OFFSET]
 
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	breq.nd r3, _CAUSE_RIRQ, _swap_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _swap_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _swap_return_from_firq
+	breq r3, _CAUSE_FIRQ, _swap_return_from_firq
 	nop
 
 	/* fall through to _swap_return_from_coop */
@@ -136,19 +147,12 @@ _finish_swapping_to_thread:
 .balign 4
 _swap_return_from_coop:
 
-	ld r1, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r1, [r2, __tTCS_intlock_key_OFFSET]
 	st  0, [r2, __tTCS_intlock_key_OFFSET]
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, __tTCS_return_value_OFFSET]
 
-	/*
-	 * Adjust the stack here in case we go to _return_from_exc: this allows
-	 * keeping handling both coop and irq cases in _return_from_exc without
-	 * adding extra logic.
-	 */
-	add_s sp, sp, 8
 	lr ilink, [_ARC_V2_STATUS32]
 	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
-	sub_s sp, sp, 8
 
 	pop_s blink /* pc into blink */
 	pop_s r3    /* status32 into r3 */
@@ -162,27 +166,32 @@ _swap_return_from_coop:
 _swap_return_from_rirq:
 _swap_return_from_firq:
 
-	_pop_irq_stack_frame
+	lr r3, [_ARC_V2_STATUS32]
+	bbit1 r3, _ARC_V2_STATUS32_AE_BIT, _return_from_exc_irq
 
-	lr ilink, [_ARC_V2_STATUS32]
-	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
+	/* pretend interrupt happened to use rtie instruction */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	brne r3,0,_swap_already_in_irq
 
-	ld ilink, [sp, -4] /* status32 into ilink */
-	and ilink, ilink, 0x7ffffffe // keep interrupts disabled until seti
-	kflag ilink
+	or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1)) /* use lowest */
+	sr r3, [_ARC_V2_AUX_IRQ_ACT]
 
-	ld ilink, [sp, -8] /* pc into ilink */
-
-	j.d [ilink]
-	seti (_ARC_V2_DEF_IRQ_LEVEL | (1 << 4))
+_swap_already_in_irq:
+	rtie
 
 .balign 4
+_return_from_exc_irq:
+	_pop_irq_stack_frame
+	sub_s sp, sp, 8
+
 _return_from_exc:
+
 	/* put the return address to eret */
-	ld ilink, [sp, -8] /* pc into ilink */
+	ld ilink, [sp] /* pc into ilink */
 	sr ilink, [_ARC_V2_ERET]
 
 	/* put status32 into estatus */
-	ld ilink, [sp, -4] /* status32 into ilink */
+	ld ilink, [sp, 4] /* status32 into ilink */
 	sr ilink, [_ARC_V2_ERSTATUS]
+	add_s sp, sp, 8
 	rtie

arch/arc/core/swap_macros.h

@@ -36,9 +36,9 @@ extern "C" {
 	sub_s sp, sp, __tCalleeSaved_SIZEOF
 
 	/* save regs on stack */
-	st r13, [sp, __tCalleeSaved_r13_OFFSET]
-	st r14, [sp, __tCalleeSaved_r14_OFFSET]
-	st r15, [sp, __tCalleeSaved_r15_OFFSET]
+	st_s r13, [sp, __tCalleeSaved_r13_OFFSET]
+	st_s r14, [sp, __tCalleeSaved_r14_OFFSET]
+	st_s r15, [sp, __tCalleeSaved_r15_OFFSET]
 	st r16, [sp, __tCalleeSaved_r16_OFFSET]
 	st r17, [sp, __tCalleeSaved_r17_OFFSET]
 	st r18, [sp, __tCalleeSaved_r18_OFFSET]
@@ -62,9 +62,9 @@ extern "C" {
 	/* restore stack pointer from struct tcs */
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 
-	ld r13, [sp, __tCalleeSaved_r13_OFFSET]
-	ld r14, [sp, __tCalleeSaved_r14_OFFSET]
-	ld r15, [sp, __tCalleeSaved_r15_OFFSET]
+	ld_s r13, [sp, __tCalleeSaved_r13_OFFSET]
+	ld_s r14, [sp, __tCalleeSaved_r14_OFFSET]
+	ld_s r15, [sp, __tCalleeSaved_r15_OFFSET]
 	ld r16, [sp, __tCalleeSaved_r16_OFFSET]
 	ld r17, [sp, __tCalleeSaved_r17_OFFSET]
 	ld r18, [sp, __tCalleeSaved_r18_OFFSET]
@@ -112,9 +112,9 @@ extern "C" {
 
 	mov r0, lp_count
 	st_s r0, [sp, __tISF_lp_count_OFFSET]
-	lr r0, [_ARC_V2_LP_START]
-	st_s r0, [sp, __tISF_lp_start_OFFSET]
+	lr r1, [_ARC_V2_LP_START]
 	lr r0, [_ARC_V2_LP_END]
+	st_s r1, [sp, __tISF_lp_start_OFFSET]
 	st_s r0, [sp, __tISF_lp_end_OFFSET]
 
 .endm
@@ -129,9 +129,9 @@ extern "C" {
 
 	ld_s r0, [sp, __tISF_lp_count_OFFSET]
 	mov lp_count, r0
-	ld_s r0, [sp, __tISF_lp_start_OFFSET]
-	sr r0, [_ARC_V2_LP_START]
+	ld_s r1, [sp, __tISF_lp_start_OFFSET]
 	ld_s r0, [sp, __tISF_lp_end_OFFSET]
+	sr r1, [_ARC_V2_LP_START]
 	sr r0, [_ARC_V2_LP_END]
 
 	ld_s r13, [sp, __tISF_r13_OFFSET]

arch/arc/core/sys_fatal_error_handler.c

@@ -73,7 +73,7 @@ void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF * pEsf)
 	ARG_UNUSED(reason);
 	ARG_UNUSED(pEsf);
 
-	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential(NULL)) {
+	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential()) {
 		PRINTK("Fatal fault in %s ! Spinning...\n",
 		       NANO_CTX_ISR == curCtx
 			       ? "ISR"

arch/arc/core/thread.c

@@ -101,7 +101,8 @@ static ALWAYS_INLINE void thread_monitor_init(struct tcs *tcs)
  *
  * @return N/A
  */
-void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
+void _new_thread(char *pStackMem, unsigned stackSize,
+		 void *uk_task_ptr, _thread_entry_t pEntry,
 		 void *parameter1, void *parameter2, void *parameter3,
 		 int priority, unsigned options)
 {
@@ -131,8 +132,12 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 	 * enable the interrupts based on intlock_key
 	 * value.
 	 */
+#ifdef CONFIG_ARC_STACK_CHECKING
+	pInitCtx->status32 = _ARC_V2_STATUS32_SC | _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
+	tcs->stack_top = (uint32_t) stackEnd;
+#else
 	pInitCtx->status32 = _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
-
+#endif
 	tcs->link = NULL;
 	tcs->flags = priority == -1 ? TASK | PREEMPTIBLE : FIBER;
 	tcs->prio = priority;
@@ -143,6 +148,20 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 	tcs->custom_data = NULL;
 #endif
 
+#ifdef CONFIG_THREAD_MONITOR
+	/*
+	 * In debug mode tcs->entry give direct access to the thread entry
+	 * and the corresponding parameters.
+	 */
+	tcs->entry = (struct __thread_entry *)(pInitCtx);
+#endif
+
+#ifdef CONFIG_MICROKERNEL
+	tcs->uk_task_ptr = uk_task_ptr;
+#else
+	ARG_UNUSED(uk_task_ptr);
+#endif
+
 	/*
 	 * intlock_key is constructed based on ARCv2 ISA Programmer's
 	 * Reference Manual CLRI instruction description:

arch/arc/core/vector_table.c

@@ -75,4 +75,3 @@ struct vector_table _VectorTable _GENERIC_SECTION(.exc_vector_table) = {
 	0
 };
 
-extern struct vector_table __start _ALIAS_OF(_VectorTable);

arch/arc/include/kernel_event_logger_arch.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Kernel event logger support for ARM
+ */
+
+#ifndef __KERNEL_EVENT_LOGGER_ARCH_H__
+#define __KERNEL_EVENT_LOGGER_ARCH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get the identification of the current interrupt.
+ *
+ * This routine obtain the key of the interrupt that is currently processed
+ * if it is called from a ISR context.
+ *
+ * @return The key of the interrupt that is currently being processed.
+ */
+int _sys_current_irq_key_get(void)
+{
+	return _INTERRUPT_CAUSE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __KERNEL_EVENT_LOGGER_ARCH_H__ */

arch/arc/include/nano_private.h

@@ -48,6 +48,16 @@ extern "C" {
 #endif
 
 #ifndef _ASMLANGUAGE
+
+#ifdef CONFIG_THREAD_MONITOR
+struct __thread_entry {
+	_thread_entry_t pEntry;
+	void *parameter1;
+	void *parameter2;
+	void *parameter3;
+};
+#endif /*CONFIG_THREAD_MONITOR*/
+
 struct coop {
 	/*
 	 * Saved on the stack as part of handling a regular IRQ or by the kernel
@@ -120,14 +130,6 @@ struct callee_saved {
 };
 typedef struct callee_saved tCalleeSaved;
 
-/* registers saved by software when taking a FIRQ */
-struct firq_regs {
-	uint32_t lp_count;
-	uint32_t lp_start;
-	uint32_t lp_end;
-};
-typedef struct firq_regs tFirqRegs;
-
 #endif /* _ASMLANGUAGE */
 
 /* Bitmask definitions for the struct tcs->flags bit field */
@@ -175,6 +177,7 @@ struct tcs {
 	struct coop coopReg;
 	struct preempt preempReg;
 #ifdef CONFIG_THREAD_MONITOR
+	struct __thread_entry *entry; /* thread entry and parameters description */
 	struct tcs *next_thread;  /* next item in list of ALL fiber+tasks */
 #endif
 #ifdef CONFIG_NANO_TIMEOUTS
@@ -183,6 +186,12 @@ struct tcs {
 #ifdef CONFIG_ERRNO
 	int errno_var;
 #endif
+#ifdef CONFIG_ARC_STACK_CHECKING
+	uint32_t stack_top;
+#endif
+#ifdef CONFIG_MICROKERNEL
+	void *uk_task_ptr;
+#endif
 };
 
 struct s_NANO {
@@ -198,7 +207,7 @@ struct s_NANO {
 	struct tcs *current_fp; /* thread (fiber or task) that owns the FP regs */
 #endif
 
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 	int32_t idle; /* Number of ticks for kernel idling */
 #endif
 
@@ -209,8 +218,7 @@ struct s_NANO {
 	 * there is no need to track it in _nanokernel.
 	 */
 
-	struct firq_regs firq_regs;
-#ifdef CONFIG_NANO_TIMEOUTS
+#if defined(CONFIG_NANO_TIMEOUTS) || defined(CONFIG_NANO_TIMERS)
 	sys_dlist_t timeout_q;
 	int32_t task_timeout;
 #endif
@@ -264,6 +272,21 @@ static ALWAYS_INLINE int _IS_IN_ISR(void)
 	return ((act & 0xffff) != 0);
 }
 
+/**
+ *
+ * @bried Indicates the interrupt number of the highest priority
+ * active interrupt
+ *
+ * @return IRQ number
+ */
+static ALWAYS_INLINE int _INTERRUPT_CAUSE(void)
+{
+	uint32_t irq_num = _arc_v2_aux_reg_read(_ARC_V2_ICAUSE);
+
+	return irq_num;
+}
+
+
 extern void nanoCpuAtomicIdle(unsigned int);
 extern void _thread_entry_wrapper(void);
 

arch/arc/include/start_task_arch.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 Wind River Systems, Inc.
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -16,24 +16,33 @@
 
 /**
  * @file
- * @brief Default basic NMI handler before the kernel is up
+ * @brief ARC nanokernel declarations to start a task
  *
- * Provide a default handler for NMI before the system is up. The default action
- * is to hard hang, sleeping.
+ * ARC-specific parts of start_task().
  *
- * This might be preferable than rebooting to help debugging, or because
- * rebooting might trigger the exact same problem over and over.
+ * Currently empty, only here for abstraction.
  */
 
-#define _ASMLANGUAGE
+#ifndef _START_TASK_ARCH__H_
+#define _START_TASK_ARCH__H_
 
 #include <toolchain.h>
 #include <sections.h>
 
-_ASM_FILE_PROLOGUE
+#include <micro_private.h>
+#include <nano_private.h>
+#include <microkernel/task.h>
 
-GTEXT(_SysNmiOnReset)
+#ifdef __cplusplus
+extern "C" {
+#endif
 
-SECTION_FUNC(TEXT, _SysNmiOnReset)
-    wfi
-    b _SysNmiOnReset
+#define _START_TASK_ARCH(task, opt_ptr) \
+	do {/* nothing */              \
+	} while ((0))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _START_TASK_ARCH__H_ */

arch/arc/include/v2/cache.h

@@ -49,7 +49,14 @@ static ALWAYS_INLINE void _icache_setup(void)
 		CACHE_DIRECT | /* direct mapping (one-way assoc.) */
 		CACHE_ENABLE   /* i-cache enabled */
 	);
-	_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
+	uint32_t val;
+
+	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
+	val &= 0xff;
+	if (val != 0) {
+		/* configure i-cache if present */
+		_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
+	}
 }
 
 #endif /* _ASMLANGUAGE */

arch/arc/soc/em11d/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/arc/soc/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o

arch/arc/soc/em11d/Kconfig.defconfig

@@ -0,0 +1,260 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_EM11D
+
+config SOC
+	default em11d
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	# TODO: But regular irq nesting is not implemented --
+	# so this must be 2 for now.
+	default 2
+
+config NUM_REGULAR_IRQ_PRIO_LEVELS
+	# This processor supports 3 Regular Interrupt priority level (1-3).
+	# TODO: But regular irq nesting is not implemented -- so use 1.
+	default 1
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 36
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	def_bool n
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config FLASH_SIZE
+	default 0
+	# em11d has no FLASH so size is 0.
+
+config SRAM_BASE_ADDRESS
+	default 0x10000000 if NSIM
+	default 0x10000000
+
+config SRAM_SIZE
+	default 131072 if NSIM
+	default 131072
+
+config ICCM_BASE_ADDRESS
+	default 0x00000000
+
+config ICCM_SIZE
+	default 64
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 64
+
+if GPIO
+
+config GPIO_DW
+	def_bool y
+
+if GPIO_DW
+
+config GPIO_DW_0
+	def_bool y
+
+if GPIO_DW_0
+
+config GPIO_DW_0_NAME
+	default "GPIO_PORTA"
+
+config GPIO_DW_0_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_0
+
+config GPIO_DW_1
+	def_bool y
+
+if GPIO_DW_1
+
+config GPIO_DW_1_NAME
+	default "GPIO_PORTB"
+
+config GPIO_DW_1_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_1
+
+config GPIO_DW_2
+	def_bool y
+
+if GPIO_DW_2
+
+config GPIO_DW_2_IRQ_PRI
+	default 1
+
+config GPIO_DW_2_NAME
+	default "GPIO_PORTC"
+
+endif # GPIO_DW_2
+
+config GPIO_DW_3
+	def_bool y
+
+if GPIO_DW_3
+
+config GPIO_DW_3_IRQ_PRI
+	default 1
+
+config GPIO_DW_3_NAME
+	default "GPIO_PORTD"
+
+endif # GPIO_DW_3
+
+endif # GPIO_DW
+
+endif # GPIO
+
+if I2C
+
+config I2C_CLOCK_SPEED
+	default 100
+
+config I2C_DW
+	def_bool y
+
+if I2C_DW
+
+config I2C_0
+	def_bool y
+
+if I2C_0
+
+config I2C_0_NAME
+	default "I2C_0"
+config I2C_0_DEFAULT_CFG
+	default 0x3
+config I2C_0_IRQ_PRI
+	default 1
+
+endif # I2C_0
+
+config I2C_1
+	def_bool y
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+config I2C_1_DEFAULT_CFG
+	default 0x3
+config I2C_1_IRQ_PRI
+	default 1
+
+endif # I2C_1
+
+endif # I2C_DW
+
+endif # I2C
+
+if UART_NS16550
+
+config UART_NS16550_PORT_0
+	def_bool n
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_NAME
+	default "UART_0"
+config UART_NS16550_PORT_0_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_0_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_NAME
+	default "UART_1"
+config UART_NS16550_PORT_1_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_1_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_1
+
+endif # UART_NS16550
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_DW
+	def_bool y
+
+if SPI_DW
+
+config SPI_DW_CLOCK_GATE
+	def_bool n
+
+config SPI_DW_FIFO_DEPTH
+	default 32
+
+config SPI_DW_ARC_AUX_REGS
+	def_bool n
+
+config SPI_0
+	def_bool y
+
+if SPI_0
+
+config SPI_0_IRQ_PRI
+	default 0
+
+endif # SPI_0
+
+config SPI_1
+	def_bool y
+
+if SPI_1
+
+config SPI_1_IRQ_PRI
+	default 0
+
+endif # SPI_1
+
+endif # SPI_DW
+
+endif # SPI
+
+endif #SOC_EM11D

arch/arc/soc/em11d/Kconfig.soc

@@ -0,0 +1,3 @@
+
+config SOC_EM11D
+	bool "Synopsys ARC EM11D"

arch/arc/soc/em11d/Makefile

@@ -0,0 +1,2 @@
+soc-cflags = $(call cc-option,-mARCv2EM) \
+                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)

arch/arc/soc/em11d/linker.ld

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit v2.2 EM11D platform.
+ */
+
+/*
+ * DRAM base address and size
+ *
+ * DRAM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
+/* TODO: Using SRAM config for now, even though this is really DRAM. */
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/em11d/soc.c

@@ -0,0 +1,46 @@
+/* soc.c - system/hardware module for em_starterkit BSP */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the ARC EM Starter kit board.
+ */
+
+#include <nanokernel.h>
+#include "soc.h"
+#include <init.h>
+
+
+/**
+ *
+ * @brief perform basic hardware initialization
+ *
+ * Hardware initialized:
+ * - interrupt unit
+ *
+ * RETURNS: N/A
+ */
+static int em11d_arc_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	_arc_v2_irq_unit_init();
+	return 0;
+}
+
+SYS_INIT(em11d_arc_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em11d/soc.h

@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+
+
+/* IRQs */
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+/* ARCv2 timer 0 configuration settings for the system clock */
+#ifdef CONFIG_NANOKERNEL
+#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 20000000 /* 20MHz reference clock */
+#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
+#endif /* CONFIG_NANOKERNEL */
+
+#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
+#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+
+#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/* I2C */
+
+/* I2C_0 is on Pmod2 connector */
+#define I2C_DW_0_BASE_ADDR                      0xF0004000
+#define I2C_DW_0_IRQ                            23
+
+
+/* I2C_1 is on Pmod4 connector */
+#define I2C_DW_1_BASE_ADDR                      0xF0005000
+#define I2C_DW_1_IRQ                            24
+
+#define I2C_DW_IRQ_FLAGS			0
+
+/* GPIO */
+#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ                           22
+#define GPIO_DW_0_BITS                          32
+#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_2_BITS                          32
+#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_3_BITS                          12
+#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+
+/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
+/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
+/* undef CONFIG_GPIO_DW_CLOCK_GATE */
+/* undef CONFIG_SOC_QUARK_SE_SS */
+
+/* SPI */
+
+#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+
+#define SPI_DW_PORT_0_REGS   0xF0006000
+#define SPI_DW_PORT_1_REGS   0xF0007000
+
+#define SPI_DW_PORT_0_IRQ    25
+#define SPI_DW_PORT_1_IRQ    26
+
+/*
+ * SPI Chip Select Assignments on EM Starter Kit
+ *
+ *  CS0   Pmod6 - pin 1 - J6
+ *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
+ *  CS2   Pmod6 - pin 8 - J6
+ *  CS3   SDCard (onboard)
+ *  CS4   Internal SPI Slave - loopback
+ *  CS5   SPI-Flash (onboard)
+ */
+
+/*
+ * UART
+     UART0 vector 27 0xF0008000
+     UART1 vector 28 0xF0009000
+     UART2 vector 29 0xF000A000
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
+#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
+#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/em11d/soc_config.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/em9d/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/arc/soc/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o

arch/arc/soc/em9d/Kconfig.defconfig

@@ -0,0 +1,261 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_EM9D
+
+config SOC
+	default em9d
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	# TODO: But regular irq nesting is not implemented --
+	# so this must be 2 for now.
+	default 2
+
+config NUM_REGULAR_IRQ_PRIO_LEVELS
+	# This processor supports 3 Regular Interrupt priority level (1-3).
+	# TODO: But regular irq nesting is not implemented -- so use 1.
+	default 1
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 36
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	def_bool y
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config FLASH_SIZE
+	default 0
+	# em9d has no FLASH so size is 0.
+
+config SRAM_BASE_ADDRESS
+	default 0x00000000 if NSIM
+	default 0x00000000
+
+config SRAM_SIZE
+	default 0 if NSIM
+	default 0
+	# em9d has no SRAM so size is 0.
+
+config ICCM_BASE_ADDRESS
+	default 0x00000000
+
+config ICCM_SIZE
+	default 256
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 128
+
+if GPIO
+
+config GPIO_DW
+	def_bool y
+
+if GPIO_DW
+
+config GPIO_DW_0
+	def_bool y
+
+if GPIO_DW_0
+
+config GPIO_DW_0_NAME
+	default "GPIO_PORTA"
+
+config GPIO_DW_0_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_0
+
+config GPIO_DW_1
+	def_bool y
+
+if GPIO_DW_1
+
+config GPIO_DW_1_NAME
+	default "GPIO_PORTB"
+
+config GPIO_DW_1_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_1
+
+config GPIO_DW_2
+	def_bool y
+
+if GPIO_DW_2
+
+config GPIO_DW_2_IRQ_PRI
+	default 1
+
+config GPIO_DW_2_NAME
+	default "GPIO_PORTC"
+
+endif # GPIO_DW_2
+
+config GPIO_DW_3
+	def_bool y
+
+if GPIO_DW_3
+
+config GPIO_DW_3_IRQ_PRI
+	default 1
+
+config GPIO_DW_3_NAME
+	default "GPIO_PORTD"
+
+endif # GPIO_DW_3
+
+endif # GPIO_DW
+
+endif # GPIO
+
+if I2C
+
+config I2C_CLOCK_SPEED
+	default 100
+
+config I2C_DW
+	def_bool y
+
+if I2C_DW
+
+config I2C_0
+	def_bool y
+
+if I2C_0
+
+config I2C_0_NAME
+	default "I2C_0"
+config I2C_0_DEFAULT_CFG
+	default 0x3
+config I2C_0_IRQ_PRI
+	default 1
+
+endif # I2C_0
+
+config I2C_1
+	def_bool y
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+config I2C_1_DEFAULT_CFG
+	default 0x3
+config I2C_1_IRQ_PRI
+	default 1
+
+endif # I2C_1
+
+endif # I2C_DW
+
+endif # I2C
+
+if UART_NS16550
+
+config UART_NS16550_PORT_0
+	def_bool n
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_NAME
+	default "UART_0"
+config UART_NS16550_PORT_0_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_0_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_NAME
+	default "UART_1"
+config UART_NS16550_PORT_1_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_1_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_1
+
+endif # UART_NS16550
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_DW
+	def_bool y
+
+if SPI_DW
+
+config SPI_DW_CLOCK_GATE
+	def_bool n
+
+config SPI_DW_FIFO_DEPTH
+	default 32
+
+config SPI_DW_ARC_AUX_REGS
+	def_bool n
+
+config SPI_0
+	def_bool y
+
+if SPI_0
+
+config SPI_0_IRQ_PRI
+	default 0
+
+endif # SPI_0
+
+config SPI_1
+	def_bool y
+
+if SPI_1
+
+config SPI_1_IRQ_PRI
+	default 0
+
+endif # SPI_1
+
+endif # SPI_DW
+
+endif # SPI
+
+endif #SOC_EM9D

arch/arc/soc/em9d/Kconfig.soc

@@ -0,0 +1,3 @@
+
+config SOC_EM9D
+	bool "Synopsys ARC EM9D"

arch/arc/soc/em9d/Makefile

@@ -0,0 +1,2 @@
+soc-cflags = $(call cc-option,-mARCv2EM) \
+                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)

arch/arc/soc/em9d/linker.ld

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit v2.2 EM9D platform.
+ */
+
+/*
+ * ICCM base address and size
+ *
+ * ICCM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+
+#include <arch/arc/v2/linker_harvard.ld>
+

arch/arc/soc/em9d/soc.c

@@ -0,0 +1,46 @@
+/* soc.c - system/hardware module for em_starterkit BSP */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the ARC EM Starter kit board.
+ */
+
+#include <nanokernel.h>
+#include "soc.h"
+#include <init.h>
+
+
+/**
+ *
+ * @brief perform basic hardware initialization
+ *
+ * Hardware initialized:
+ * - interrupt unit
+ *
+ * RETURNS: N/A
+ */
+static int em9d_arc_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	_arc_v2_irq_unit_init();
+	return 0;
+}
+
+SYS_INIT(em9d_arc_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em9d/soc.h

@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+
+
+/* IRQs */
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+/* ARCv2 timer 0 configuration settings for the system clock */
+#ifdef CONFIG_NANOKERNEL
+#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 20000000 /* 20MHz reference clock */
+#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
+#endif /* CONFIG_NANOKERNEL */
+
+#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
+#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+
+#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/* I2C */
+
+/* I2C_0 is on Pmod2 connector */
+#define I2C_DW_0_BASE_ADDR                      0xF0004000
+#define I2C_DW_0_IRQ                            23
+
+
+/* I2C_1 is on Pmod4 connector */
+#define I2C_DW_1_BASE_ADDR                      0xF0005000
+#define I2C_DW_1_IRQ                            24
+
+#define I2C_DW_IRQ_FLAGS			0
+
+/* GPIO */
+#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ                           22
+#define GPIO_DW_0_BITS                          32
+#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_2_BITS                          32
+#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_3_BITS                          12
+#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+
+/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
+/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
+/* undef CONFIG_GPIO_DW_CLOCK_GATE */
+/* undef CONFIG_SOC_QUARK_SE_SS */
+
+/* SPI */
+
+#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+
+#define SPI_DW_PORT_0_REGS   0xF0006000
+#define SPI_DW_PORT_1_REGS   0xF0007000
+
+#define SPI_DW_PORT_0_IRQ    25
+#define SPI_DW_PORT_1_IRQ    26
+
+/*
+ * SPI Chip Select Assignments on EM Starter Kit
+ *
+ *  CS0   Pmod6 - pin 1 - J6
+ *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
+ *  CS2   Pmod6 - pin 8 - J6
+ *  CS3   SDCard (onboard)
+ *  CS4   Internal SPI Slave - loopback
+ *  CS5   SPI-Flash (onboard)
+ */
+
+/*
+ * UART
+     UART0 vector 27 0xF0008000
+     UART1 vector 28 0xF0009000
+     UART2 vector 29 0xF000A000
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
+#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
+#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/em9d/soc_config.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/quark_se_ss/Kbuild

@@ -7,5 +7,3 @@ ccflags-$(CONFIG_ADC) +=-I$(srctree)/drivers/adc
 asflags-y := ${ccflags-y}
 
 obj-y = soc.o soc_config.o
-obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
-obj-$(CONFIG_SW_ISR_TABLE_BSP) += sw_isr_table.o

arch/arc/soc/quark_se_ss/Kconfig

@@ -1,225 +0,0 @@
-#
-# Copyright (c) 2014 Wind River Systems, Inc.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-
-if SOC_QUARK_SE_SS
-
-config SOC
-	default quark_se_ss
-
-config NUM_IRQ_PRIO_LEVELS
-	# This processor supports only 2 priority levels:
-	# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
-	default 2
-
-config NUM_REGULAR_IRQ_PRIO_LEVELS
-	# This processor supports only 1 Regular Interrupt priority level (1).
-	default 1
-
-config  NUM_IRQS
-	# must be > the highest interrupt number used
-	default 68
-
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 32000000
-
-config RAM_START
-	default 0x4000 if NSIM
-	default 0xa8000400
-
-config RAM_SIZE
-	default 16 if NSIM
-	default 24
-
-if GPIO
-config GPIO_DW
-	def_bool y
-config GPIO_DW_BOTHEDGES_SUPPORT
-	default n
-
-config GPIO_DW_0
-	def_bool y
-config GPIO_DW_0_BASE_ADDR
-	default 0x80017800
-config GPIO_DW_0_IRQ
-	default 20
-config GPIO_DW_0_PRI
-	default 2
-config GPIO_DW_0_BITS
-	default 8
-
-config GPIO_DW_1
-	def_bool y
-config GPIO_DW_1_BASE_ADDR
-	default 0x80017900
-config GPIO_DW_1_IRQ
-	default 21
-config GPIO_DW_1_PRI
-	default 2
-config GPIO_DW_1_BITS
-	default 8
-endif
-
-if I2C
-
-config I2C_QUARK_SE_SS
-	def_bool y
-
-config I2C_QUARK_SE_SS_0
-	def_bool y
-
-if I2C_QUARK_SE_SS_0
-
-config I2C_QUARK_SE_SS_0_BASE
-	default 0x80012000
-
-config I2C_QUARK_SE_SS_0_NAME
-	default "I2C0"
-
-config I2C_QUARK_SE_SS_0_DEFAULT_CFG
-	default 0x12
-
-endif
-
-if I2C_QUARK_SE_SS_1
-
-config I2C_QUARK_SE_SS_1_BASE
-	default 0x80012100
-
-config I2C_QUARK_SE_SS_1_NAME
-	default "I2C1"
-
-config I2C_QUARK_SE_SS_1_DEFAULT_CFG
-	default 0x12
-
-endif
-
-endif # I2C
-
-if UART_NS16550
-
-config UART_NS16550_PORT_0
-        def_bool y
-
-if UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_0_NAME
-        default "UART_0"
-config UART_NS16550_PORT_0_BASE_ADDR
-        default 0xB0002000
-config UART_NS16550_PORT_0_IRQ
-        default 41
-config UART_NS16550_PORT_0_IRQ_PRI
-        default 1
-config UART_NS16550_PORT_0_BAUD_RATE
-        default 115200
-config UART_NS16550_PORT_0_CLK_FREQ
-        default 32000000
-config UART_NS16550_PORT_0_OPTIONS
-        default 0
-
-endif # UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_1
-        def_bool y
-
-if UART_NS16550_PORT_1
-
-config UART_NS16550_PORT_1_NAME
-        default "UART_1"
-config UART_NS16550_PORT_1_BASE_ADDR
-        default 0xB0002400
-config UART_NS16550_PORT_1_IRQ
-        default 42
-config UART_NS16550_PORT_1_IRQ_PRI
-        default 1
-config UART_NS16550_PORT_1_BAUD_RATE
-        default 115200
-config UART_NS16550_PORT_1_CLK_FREQ
-        default 32000000
-config UART_NS16550_PORT_1_OPTIONS
-        default 0
-
-endif # UART_NS16550_PORT_1
-
-endif # UART_NS16550
-
-if UART_CONSOLE
-
-config UART_CONSOLE_ON_DEV_NAME
-        default "UART_1"
-config UART_CONSOLE_IRQ
-        default 42
-config UART_CONSOLE_IRQ_PRI
-        default 1
-
-endif
-
-if SPI
-config SPI_DW
-	def_bool y
-config SPI_DW_CLOCK_GATE
-	def_bool n
-
-config SPI_DW_PORT_0
-	def_bool y
-config SPI_DW_PORT_0_PRI
-	default 1
-config SPI_DW_PORT_0_REGS
-	default 0x80010000
-config SPI_DW_PORT_0_ERROR_IRQ
-	default 30
-config SPI_DW_PORT_0_RX_IRQ
-	default 31
-config SPI_DW_PORT_0_TX_IRQ
-	default 32
-
-config SPI_DW_PORT_1
-	def_bool y
-config SPI_DW_PORT_1_PRI
-	default 1
-config SPI_DW_PORT_1_REGS
-	default 0x80010100
-config SPI_DW_PORT_1_ERROR_IRQ
-	default 33
-config SPI_DW_PORT_1_RX_IRQ
-	default 34
-config SPI_DW_PORT_1_TX_IRQ
-	default 35
-endif
-
-config KERNEL_INIT_PRIORITY_DEFAULT
-	default 40
-
-config KERNEL_INIT_PRIORITY_DEVICE
-	default 50
-
-config IPM_CONSOLE_PRIORITY
-	default 60
-
-config UART_CONSOLE_PRIORITY
-	default 60
-
-config GPIO_DW_INIT_PRIORITY
-	default 60
-
-config I2C_INIT_PRIORITY
-	default 60
-
-config SPI_DW_INIT_PRIORITY
-	default 70 # It might require GPIO to be ready first
-
-endif #SOC_QUARK_SE_ARC

arch/arc/soc/quark_se_ss/Kconfig.defconfig

@@ -0,0 +1,188 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2015-2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_QUARK_SE_SS
+
+config SOC
+	default quark_se_ss
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports only 2 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
+	default 2
+
+config NUM_REGULAR_IRQ_PRIO_LEVELS
+	# This processor supports only 1 Regular Interrupt priority level (1).
+	default 1
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 68
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 32000000
+
+config HARVARD
+	def_bool n
+
+config FLASH_BASE_ADDRESS
+	default 0x40000000
+
+config FLASH_SIZE
+	default 152
+
+config SRAM_BASE_ADDRESS
+	default 0x4000 if NSIM
+	default 0xa8000400
+
+config SRAM_SIZE
+	default 16 if NSIM
+	default 24
+
+config ICCM_BASE_ADDRESS
+	default 0xFFFFFFFF
+
+config ICCM_SIZE
+	default 0
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 8
+
+config QMSI
+	def_bool y
+
+config QMSI_BUILTIN
+	def_bool y
+
+if GPIO
+
+config GPIO_QMSI_SS
+	def_bool y
+
+if GPIO_QMSI_SS
+
+config GPIO_QMSI_SS_0
+	def_bool y
+
+if GPIO_QMSI_SS_0
+
+config GPIO_QMSI_SS_0_PRI
+	default 1
+
+endif # GPIO_QMSI_SS_0
+
+config GPIO_QMSI_SS_1
+	def_bool y
+
+if GPIO_QMSI_SS_1
+
+config GPIO_QMSI_SS_1_PRI
+	default 1
+
+endif # GPIO_QMSI_SS_1
+
+endif # GPIO_QMSI_SS
+
+endif # GPIO
+
+
+if I2C
+
+config I2C_QMSI_SS
+	def_bool y
+
+config I2C_0
+	def_bool y
+
+config I2C_0_NAME
+	default "I2C_0"
+
+config I2C_0_DEFAULT_CFG
+	default 0x12
+
+config I2C_0_IRQ_PRI
+	default 2
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+
+config I2C_1_DEFAULT_CFG
+	default 0x12
+
+config I2C_1_IRQ_PRI
+	default 2
+
+endif # I2C_1
+
+
+endif # I2C
+
+
+if UART_QMSI
+config UART_QMSI_0
+	def_bool y
+
+if UART_QMSI_0
+
+config UART_QMSI_0_IRQ_PRI
+	default 3
+
+endif # UART_QMSI_0
+
+config UART_QMSI_1
+	def_bool y
+
+if UART_QMSI_1
+
+config UART_QMSI_1_IRQ_PRI
+	default 3
+
+endif # UART_QMSI_1
+
+endif # UART_QMSI
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_QMSI_SS
+	def_bool y
+
+config SPI_0
+	def_bool y
+
+config SPI_0_IRQ_PRI
+	default 1
+config SPI_1
+	def_bool y
+
+config SPI_1_IRQ_PRI
+	default 1
+endif # SPI
+
+
+endif #SOC_QUARK_SE_ARC

arch/arc/soc/quark_se_ss/Kconfig.soc

@@ -1,3 +1,5 @@
 
 config SOC_QUARK_SE_SS
-        bool "Intel Quark SE - Sensor Sub System"
+	bool "Intel Quark SE - Sensor Sub System"
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select HAS_QMSI

arch/arc/soc/quark_se_ss/Makefile

@@ -1,7 +1,5 @@
-
-arch-cflags = $(call cc-option,-mARCv2EM) \
+soc-cflags = $(call cc-option,-mARCv2EM) \
                    $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)
-
-KBUILD_AFLAGS += $(arch-cflags)
-KBUILD_CFLAGS += $(arch-cflags)
-KBUILD_CXXFLAGS += $(arch-cflags)
+soc-aflags = $(soc-cflags)
+soc-cxxflags = $(soc-cflags)
+soc-cflags += -DQM_SENSOR=1

arch/arc/soc/quark_se_ss/linker.ld

@@ -20,8 +20,8 @@
  */
 
 /* Flash base address and size */
-#define FLASH_START     0x40000000  /* Flash bank 1 */
-#define FLASH_SIZE      152K
+#define FLASH_START     CONFIG_FLASH_BASE_ADDRESS  /* Flash bank 1 */
+#define FLASH_SIZE      CONFIG_FLASH_SIZE
 
 /*
  * SRAM base address and size
@@ -29,11 +29,11 @@
  * Internal SRAM includes the exception vector table at reset, which is at
  * the beginning of the region.
  */
-#define SRAM_START		CONFIG_RAM_START
-#define SRAM_SIZE		CONFIG_RAM_SIZE
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
 
 /* Data Closely Coupled Memory (DCCM) base address and size */
-#define DCCM_START		0x80000000
-#define DCCM_SIZE		8K
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
 
-#include <arch/arc/v2/linker.cmd>
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/quark_se_ss/soc.c

@@ -26,10 +26,6 @@
 #include <init.h>
 #include <quark_se/shared_mem.h>
 
-/* Cannot use microkernel, since only nanokernel is supported */
-#if defined(CONFIG_MICROKERNEL)
-#error "Microkernel support is not available"
-#endif
 
 /**
  *

arch/arc/soc/quark_se_ss/soc.h

@@ -58,16 +58,18 @@
 #define IRQ_I2C1_TX_REQ 23
 #define IRQ_I2C1_STOP_DET 24
 #define IRQ_I2C1_ERR 25
-#define IRQ_SPI0_ERR_INT 26
-#define IRQ_SPI0_RX_AVAIL 27
-#define IRQ_SPI0_TX_REQ 28
-#define IRQ_SPI1_ERR_INT 29
-#define IRQ_SPI1_RX_AVAIL 30
-#define IRQ_SPI1_TX_REQ 31
-#define IRQ_ADC_IRQ 32
-#define IRQ_ADC_ERR 33
-#define IRQ_GPIO0_INTR 34
-#define IRQ_GPIO1_INTR 35
+#define IRQ_SPI0_ERR_INT 30
+#define IRQ_SPI0_RX_AVAIL 31
+#define IRQ_SPI0_TX_REQ 32
+
+#define IRQ_SPI1_ERR_INT 33
+#define IRQ_SPI1_RX_AVAIL 34
+#define IRQ_SPI1_TX_REQ 35
+
+#define IRQ_ADC_ERR 18
+#define IRQ_ADC_IRQ 19
+#define IRQ_GPIO0_INTR 20
+#define IRQ_GPIO1_INTR 21
 #define IRQ_I2C_MST0_INTR 36
 #define IRQ_I2C_MST1_INTR 37
 #define IRQ_SPI_MST0_INTR 38
@@ -122,9 +124,10 @@
 #define INT_ENABLE_ARC					~(0x00000001 << 8)
 #define INT_ENABLE_ARC_BIT_POS				(8)
 
-#if defined(CONFIG_I2C)
-
-#if defined(CONFIG_I2C_QUARK_SE_SS_0)
+/*
+ * I2C
+ */
+#define I2C_QUARK_SE_SS_0_BASE_ADDR			0x80012000
 #define I2C_SS_0_ERR_VECTOR				22
 #define I2C_SS_0_ERR_MASK				0x410
 #define I2C_SS_0_RX_VECTOR				23
@@ -133,9 +136,8 @@
 #define I2C_SS_0_TX_MASK				0x418
 #define I2C_SS_0_STOP_VECTOR				25
 #define I2C_SS_0_STOP_MASK				0x41C
-#endif
 
-#if defined(CONFIG_I2C_QUARK_SE_SS_1)
+#define I2C_QUARK_SE_SS_1_BASE_ADDR			0x80012100
 #define I2C_SS_1_ERR_VECTOR				26
 #define I2C_SS_1_ERR_MASK				0x420
 #define I2C_SS_1_RX_VECTOR				27
@@ -144,21 +146,47 @@
 #define I2C_SS_1_TX_MASK				0x428
 #define I2C_SS_1_STOP_VECTOR				29
 #define I2C_SS_1_STOP_MASK				0x42C
+
+/*
+ * GPIO
+ */
+#define GPIO_DW_IO_ACCESS
+
+#define GPIO_DW_0_BASE_ADDR			0x80017800
+#define GPIO_DW_0_IRQ				20
+#define GPIO_DW_0_BITS				8
+#define GPIO_DW_PORT_0_INT_MASK			(SCSS_REGISTER_BASE + 0x408)
+
+#define GPIO_DW_1_BASE_ADDR			0x80017900
+#define GPIO_DW_1_IRQ				21
+#define GPIO_DW_1_BITS				8
+#define GPIO_DW_PORT_1_INT_MASK			(SCSS_REGISTER_BASE + 0x40C)
+
+#if defined(CONFIG_IOAPIC)
+#define GPIO_DW_0_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
+#define GPIO_DW_1_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
 #endif
 
-#endif /* CONFIG_I2C */
+/*
+ * UART
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xB0002000
+#define UART_NS16550_PORT_0_IRQ				41
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_0_INT_MASK			0x460
 
-#if defined(CONFIG_GPIO_DW)
-#define GPIO_DW_PORT_0_INT_MASK				(SCSS_REGISTER_BASE + 0x408)
-#define GPIO_DW_PORT_1_INT_MASK				(SCSS_REGISTER_BASE + 0x40C)
-#endif /* CONFIG_GPIO_DW */
+#define UART_NS16550_PORT_1_BASE_ADDR			0xB0002400
+#define UART_NS16550_PORT_1_IRQ				42
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_1_INT_MASK			0x464
 
-#if defined(CONFIG_UART_NS16550)
-#define UART_NS16550_0_INT_MASK				0x460
-#define UART_NS16550_1_INT_MASK				0x464
-#endif /* CONFIG_UART_NS16550 */
+/*
+ * SPI
+ */
+
+#define SPI_DW_PORT_0_REGS				0x80010000
+#define SPI_DW_PORT_1_REGS				0x80010100
 
-#if defined(CONFIG_SPI_DW)
 #define SPI_DW_PORT_0_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x430)
 #define SPI_DW_PORT_0_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x434)
 #define SPI_DW_PORT_0_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x438)
@@ -166,7 +194,8 @@
 #define SPI_DW_PORT_1_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x43C)
 #define SPI_DW_PORT_1_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x440)
 #define SPI_DW_PORT_1_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x444)
-#endif
+
+#define SPI_DW_IRQ_FLAGS				0
 
 #endif /* !_ASMLANGUAGE */
 

arch/arc/soc/quark_se_ss/soc_config.c

@@ -27,15 +27,16 @@ static int arc_quark_se_ipm_init(void)
 	IRQ_CONNECT(QUARK_SE_IPM_INTERRUPT, QUARK_SE_IPM_INTERRUPT_PRI,
 		    quark_se_ipm_isr, NULL, 0);
 	irq_enable(QUARK_SE_IPM_INTERRUPT);
-	return DEV_OK;
+	return 0;
 }
 
 static struct quark_se_ipm_controller_config_info ipm_controller_config = {
 	.controller_init = arc_quark_se_ipm_init
 };
-DEVICE_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
+DEVICE_AND_API_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
 				NULL, &ipm_controller_config,
-				SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+				SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+				&ipm_quark_se_api_funcs);
 
 #if CONFIG_IPM_CONSOLE_SENDER
 #include <console/ipm_console.h>
@@ -47,7 +48,7 @@ struct ipm_console_sender_config_info quark_se_ipm_sender_config = {
 };
 DEVICE_INIT(ipm_console, "ipm_console", ipm_console_sender_init,
 				NULL, &quark_se_ipm_sender_config,
-				SECONDARY, CONFIG_IPM_CONSOLE_PRIORITY);
+				SECONDARY, CONFIG_IPM_CONSOLE_INIT_PRIORITY);
 
 #endif /* CONFIG_IPM_CONSOLE_SENDER */
 #endif /* CONFIG_IPM_QUARK_SE */
@@ -59,16 +60,16 @@ static int uart_ns16550_init(struct device *dev)
 	ARG_UNUSED(dev);
 
 #ifdef CONFIG_UART_NS16550_PORT_0
-	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_0_INT_MASK),
+	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_0_INT_MASK),
 		      INT_ENABLE_ARC_BIT_POS);
 #endif /* CONFIG_UART_NS16550_PORT_0 */
 
 #ifdef CONFIG_UART_NS16550_PORT_1
-	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_1_INT_MASK),
+	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_1_INT_MASK),
 		      INT_ENABLE_ARC_BIT_POS);
 #endif /* CONFIG_UART_NS16550_PORT_1 */
 
-	return DEV_OK;
+	return 0;
 }
 
 SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arm/Kbuild

@@ -2,5 +2,10 @@ subdir-ccflags-y +=-I$(srctree)/include/drivers
 subdir-ccflags-y +=-I$(srctree)/drivers
 subdir-asflags-y := ${subdir-ccflags-y}
 
-obj-y += soc/$(SOC_NAME)/
+ifneq ($(SOC_FAMILY),)
+obj-y += soc/$(SOC_FAMILY)/
+else
+obj-y += soc/$(SOC_PATH)/
+endif
+
 obj-y += core/

arch/arm/Kconfig

@@ -16,8 +16,15 @@
 # limitations under the License.
 #
 
+choice
+	prompt "ARM SoC Selection"
+	default SOC_SERIES_KINETIS_K6X
+	depends on ARM
 
-menu "ARM architecture"
+	source "arch/arm/soc/*/Kconfig.soc"
+endchoice
+
+menu "ARM Options"
 	depends on ARM
 
 config ARCH
@@ -27,63 +34,12 @@ config ARCH_DEFCONFIG
 	string
 	default "arch/arm/defconfig"
 
-menu "General Platform Configuration"
-
-choice
-prompt "SoC Selection"
-default SOC_FSL_FRDM_K64F
-source "arch/arm/soc/*/Kconfig.soc"
-endchoice
-
-config IS_BOOTLOADER
-	bool "Act as a bootloader"
-	default n
-	depends on XIP
-	help
-	This option indicates that Zephyr will act as a bootloader to execute
-	a separate Zephyr image payload.
-
-config BOOTLOADER_SRAM_SIZE
-	int "SRAM reserved for when Zephyr acts as a bootloader"
-	default 16
-	depends on !XIP || IS_BOOTLOADER
-	help
-	This option specifies the amount of SRAM (measure in kB) reserved for
-	when Zephyr is to act as a bootloader.
-
-config ISA_THUMB2
-	bool
-	# Omit prompt to signify "hidden" option
-	default n
-	help
-	From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
-
-	Thumb-2 technology is the instruction set underlying the ARM Cortex
-	architecture which provides enhanced levels of performance, energy
-	efficiency, and code density for a wide range of embedded
-	applications.
-
-	Thumb-2 technology builds on the success of Thumb, the innovative
-	high code density instruction set for ARM microprocessor cores, to
-	increase the power of the ARM microprocessor core available to
-	developers of low cost, high performance systems.
-
-	The technology is backwards compatible with existing ARM and Thumb
-	solutions, while significantly extending the features available to
-	the Thumb instructions set. This allows more of the application to
-	benefit from the best in class code density of Thumb.
-
-	For performance optimised code Thumb-2 technology uses 31 percent
-	less memory to reduce system cost, while providing up to 38 percent
-	higher performance than existing high density code, which can be used
-	to prolong battery-life or to enrich the product feature set. Thumb-2
-	technology is featured in the  processor, and in all ARMv7
-	architecture-based processors.
 
 source "arch/arm/core/Kconfig"
 
-endmenu
+menu "Platform Configuration"
 
 source "arch/arm/soc/*/Kconfig"
 
 endmenu
+endmenu

arch/arm/Makefile

@@ -1,21 +1,47 @@
 KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
 
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/Makefile
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 
 cflags-$(CONFIG_LTO) += $(call cc-option,-flto,)
 
+cflags-cortex-m0 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m0) \
+			$(call cc-option,-mthumb -march=armv6-m)
+cflags-cortex-m0+ = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m0plus) \
+			$(call cc-option,-mthumb -march=armv6-m)
+cflags-cortex-m1 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m1) \
+			$(call cc-option,-mthumb -march=armv6-m)
+cflags-cortex-m3 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m3) \
+			$(call cc-option,-mthumb -march=armv7-m)
+cflags-cortex-m4 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m4) \
+			$(call cc-option,-mthumb -march=armv7e-m)
+cflags-cortex-m7 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m7) \
+			$(call cc-option,-mthumb -march=armv7e-m)
+
+aflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
+cflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
+cxxflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
+_arm_isa-$(CONFIG_CPU_CORTEX_M3) = armv7-m
+
+aflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
+cflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
+cxxflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
+_arm_isa-$(CONFIG_CPU_CORTEX_M4) = armv7e-m
+
+_CROSS_COMPILE_arm_isa = $(_arm_isa-y)
+
+KBUILD_AFLAGS += $(aflags-y)
 KBUILD_CFLAGS += $(cflags-y)
 KBUILD_CXXFLAGS += $(cflags-y)
 
-ifeq ($(CONFIG_CPU_CORTEX_M3),y)
-arch-cflags += $(call cc-option, -mthumb -mcpu=cortex-m3)
-else ifeq ($(CONFIG_CPU_CORTEX_M4),y)
-arch-cflags += $(call cc-option, -mthumb -mcpu=cortex-m4)
-endif
+soc-cxxflags ?= $(soc-cflags)
+soc-aflags ?= $(soc-cflags)
+KBUILD_CFLAGS += $(soc-cflags)
+KBUILD_CXXFLAGS += $(soc-cxxflags)
+KBUILD_AFLAGS += $(soc-aflags)
 
 QEMU_CPU_TYPE_arm = cortex-m3
 QEMU_FLAGS_arm = -cpu  $(QEMU_CPU_TYPE_arm) \
-		-machine lm3s6965evb -nographic
+		-machine lm3s6965evb -nographic -vga none
 QEMU_arm = qemu-system-arm
 
 export QEMU_FLAGS_arm QEMU_arm

arch/arm/core/cortex_m/Kconfig

@@ -16,6 +16,35 @@
 # limitations under the License.
 #
 
+config ISA_THUMB2
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	help
+	From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
+
+	Thumb-2 technology is the instruction set underlying the ARM Cortex
+	architecture which provides enhanced levels of performance, energy
+	efficiency, and code density for a wide range of embedded
+	applications.
+
+	Thumb-2 technology builds on the success of Thumb, the innovative
+	high code density instruction set for ARM microprocessor cores, to
+	increase the power of the ARM microprocessor core available to
+	developers of low cost, high performance systems.
+
+	The technology is backwards compatible with existing ARM and Thumb
+	solutions, while significantly extending the features available to
+	the Thumb instructions set. This allows more of the application to
+	benefit from the best in class code density of Thumb.
+
+	For performance optimised code Thumb-2 technology uses 31 percent
+	less memory to reduce system cost, while providing up to 38 percent
+	higher performance than existing high density code, which can be used
+	to prolong battery-life or to enrich the product feature set. Thumb-2
+	technology is featured in the  processor, and in all ARMv7
+	architecture-based processors.
+
 config CPU_CORTEX_M3_M4
 	bool
 	# Omit prompt to signify "hidden" option
@@ -160,16 +189,6 @@ config SW_ISR_TABLE_DYNAMIC
 	SRAM so that it is writable. This has the side-effect of removing
 	write-protection on the ISR table.
 
-config SW_ISR_TABLE_STATIC_CUSTOM
-	bool
-	prompt "Projects provide a custom static software ISR table"
-	depends on SW_ISR_TABLE && !SW_ISR_TABLE_DYNAMIC
-	default n
-	help
-	Projects, not the platform, provide a software table of ISR and their
-	parameters. The table is static, and thus ISRs cannot be connected
-	at runtime.
-
 config IRQ_VECTOR_TABLE_CUSTOM
 	bool
 	prompt "Projects provide a custom static IRQ part of vector table"

arch/arm/core/cortex_m/Makefile

@@ -1,10 +1,11 @@
 ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/arch/$(ARCH)/platforms/$(SOC_NAME)
+ccflags-y +=-I$(srctree)/arch/arm/soc/$(SOC_PATH)
 
 asflags-y = $(ccflags-y)
 
 obj-y = vector_table.o reset.o \
-	prep_c.o scs.o scb.o nmi.o \
-	sw_isr_table.o exc_manage.o exc_wrapper.o
+	nmi_on_reset.o prep_c.o scs.o scb.o nmi.o \
+	exc_manage.o exc_wrapper.o
 
-obj-$(CONFIG_ERRNO) += errno.o
+obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o
+obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o

arch/arm/core/cortex_m/irq_vector_table.c

@@ -32,11 +32,6 @@
 #include <toolchain.h>
 #include <sections.h>
 
-#if defined(CONFIG_CONSOLE_HANDLER)
-#include <soc.h>
-#include <console/uart_console.h>
-#endif /* CONFIG_CONSOLE_HANDLER */
-
 extern void _isr_wrapper(void);
 typedef void (*vth)(void); /* Vector Table Handler */
 
@@ -50,20 +45,9 @@ vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
 
 extern void _irq_spurious(void);
 
-#if defined(CONFIG_CONSOLE_HANDLER)
-static void _uart_console_isr(void)
-{
-	uart_console_isr(NULL);
-	_IntExit();
-}
-#endif /* CONFIG_CONSOLE_HANDLER */
-
 /* placeholders: fill with real ISRs */
 vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
 	[0 ...(CONFIG_NUM_IRQS - 1)] = _irq_spurious,
-#if defined(CONFIG_CONSOLE_HANDLER)
-	[CONFIG_UART_CONSOLE_IRQ] = _uart_console_isr,
-#endif
 };
 
 #endif /* CONFIG_SW_ISR_TABLE */

arch/arm/core/cpu_idle.S

@@ -33,7 +33,7 @@
 _ASM_FILE_PROLOGUE
 
 GTEXT(_CpuIdleInit)
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 GTEXT(_NanoIdleValGet)
 GTEXT(_NanoIdleValClear)
 #endif
@@ -62,7 +62,7 @@ SECTION_FUNC(TEXT, _CpuIdleInit)
     str r2, [r1]
     bx lr
 
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 
 /**
  *
@@ -101,7 +101,7 @@ SECTION_FUNC(TEXT, _NanoIdleValClear)
     str r1, [r0, #__tNANO_idle_OFFSET]
     bx lr
 
-#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
+#endif /* CONFIG_SYS_POWER_MANAGEMENT */
 
 /**
  *

arch/arm/core/fault.c

@@ -357,5 +357,4 @@ void _Fault(const NANO_ESF *esf)
 void _FaultInit(void)
 {
 	_ScbDivByZeroFaultEnable();
-	_ScbUnalignedFaultEnable();
 }

arch/arm/core/isr_wrapper.S

@@ -69,7 +69,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
 	pop {lr}
 #endif
 
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 	/*
 	 * All interrupts are disabled when handling idle wakeup.  For tickless
 	 * idle, this ensures that the calculation and programming of the device
@@ -90,7 +90,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
 		blxne	_sys_power_save_idle_exit
 
 	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
-#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
+#endif
 
 	mrs r0, IPSR	/* get exception number */
 	sub r0, r0, #16	/* get IRQ number */

arch/arm/core/offsets/offsets.c

@@ -40,9 +40,9 @@
 /* ARM-specific tNANO structure member offsets */
 
 GEN_OFFSET_SYM(tNANO, flags);
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 GEN_OFFSET_SYM(tNANO, idle);
-#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
+#endif
 
 /* ARM-specific struct tcs structure member offsets */
 

arch/arm/core/swap.S

@@ -160,7 +160,7 @@ SECTION_FUNC(TEXT, __svc)
 
     ldr r0, [r0, #24]   /* grab address of PC from stack frame */
     /* SVC is a two-byte instruction, point to it and read  encoding */
-    ldr r0, [r0, #-2]
+    ldrh r0, [r0, #-2]
 
    /*
     * grab service call number: if zero, it's a context switch;  if not,

arch/arm/core/sys_fatal_error_handler.c

@@ -74,7 +74,7 @@ void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF * pEsf)
 	ARG_UNUSED(reason);
 	ARG_UNUSED(pEsf);
 
-	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential(NULL)) {
+	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential()) {
 		PRINTK("Fatal fault in %s ! Spinning...\n",
 		       NANO_CTX_ISR == curCtx
 			       ? "ISR"

arch/arm/core/thread.c

@@ -100,7 +100,8 @@ static ALWAYS_INLINE void _thread_monitor_init(struct tcs *tcs /* thread */
  * @return N/A
  */
 
-void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
+void _new_thread(char *pStackMem, unsigned stackSize,
+		 void *uk_task_ptr, _thread_entry_t pEntry,
 		 void *parameter1, void *parameter2, void *parameter3,
 		 int priority, unsigned options)
 {
@@ -135,6 +136,20 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 	tcs->custom_data = NULL;
 #endif
 
+#ifdef CONFIG_THREAD_MONITOR
+	/*
+	 * In debug mode tcs->entry give direct access to the thread entry
+	 * and the corresponding parameters.
+	 */
+	tcs->entry = (struct __thread_entry *)(pInitCtx);
+#endif
+
+#ifdef CONFIG_MICROKERNEL
+	tcs->uk_task_ptr = uk_task_ptr;
+#else
+	ARG_UNUSED(uk_task_ptr);
+#endif
+
 	tcs->preempReg.psp = (uint32_t)pInitCtx;
 	tcs->basepri = 0;
 

arch/arm/defconfig

@@ -3,7 +3,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000
 CONFIG_SOC_TI_LM3S6965=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
-CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_0"
 CONFIG_SERIAL=y
 CONFIG_CORTEX_M_SYSTICK=y
 CONFIG_FLASH_SIZE=256

arch/arm/include/nano_private.h

@@ -45,6 +45,16 @@ extern "C" {
 #endif
 
 #ifndef _ASMLANGUAGE
+
+#ifdef CONFIG_THREAD_MONITOR
+struct __thread_entry {
+	_thread_entry_t pEntry;
+	void *parameter1;
+	void *parameter2;
+	void *parameter3;
+};
+#endif /*CONFIG_THREAD_MONITOR*/
+
 struct coop {
 	/*
 	 * Unused for Cortex-M, which automatically saves the neccesary
@@ -120,6 +130,7 @@ struct tcs {
 	struct coop coopReg;
 	struct preempt preempReg;
 #if defined(CONFIG_THREAD_MONITOR)
+	struct __thread_entry *entry; /* thread entry and parameters description */
 	struct tcs *next_thread; /* next item in list of ALL fiber+tasks */
 #endif
 #ifdef CONFIG_NANO_TIMEOUTS
@@ -128,6 +139,9 @@ struct tcs {
 #ifdef CONFIG_ERRNO
 	int errno_var;
 #endif
+#ifdef CONFIG_MICROKERNEL
+	void *uk_task_ptr;
+#endif
 };
 
 struct s_NANO {
@@ -144,11 +158,11 @@ struct s_NANO {
 	struct tcs *current_fp; /* thread (fiber or task) that owns the FP regs */
 #endif			  /* CONFIG_FP_SHARING */
 
-#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
 	int32_t idle; /* Number of ticks for kernel idling */
-#endif		      /* CONFIG_ADVANCED_POWER_MANAGEMENT */
+#endif
 
-#ifdef CONFIG_NANO_TIMEOUTS
+#if defined(CONFIG_NANO_TIMEOUTS) || defined(CONFIG_NANO_TIMERS)
 	sys_dlist_t timeout_q;
 	int32_t task_timeout;
 #endif

arch/arm/soc/atmel_sam3/Kbuild

@@ -1,3 +0,0 @@
-obj-y += soc.o nmi_on_reset.o
-
-obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o

arch/arm/soc/atmel_sam3/Kconfig

@@ -19,55 +19,10 @@
 
 config SOC_ATMEL_SAM3
 	bool
+	depends on ARM
 	default n
 
-if SOC_ATMEL_SAM3
-
-config SOC
-	default atmel_sam3
-
-config NUM_IRQ_PRIO_BITS
-	int
-	default 3
-
-#
-# SAM3X8E has total 45 peripherals capable of
-# generating interrupts.
-#
-config NUM_IRQS
-	int
-	default 45
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	int
-	default 84000000
-
-#
-# SRAM address depends on the processor.
-#
-# SAM3X8E has two SRAM banks:
-#   64K @ 0x20000000
-#   32K @ 0x20080000
-# The first 64K is mirrored at 0x20070000
-# to provide one continuous 96K block.
-#
-config SRAM_SIZE
-	default 96 if SOC_ATMEL_SAM3X8E
-
-config SRAM_BASE_ADDRESS
-	default 0x20000000 if !SOC_ATMEL_SAM3X8E
-	default 0x20070000 if SOC_ATMEL_SAM3X8E
-
-#
-# Atmel SAM3 family has flash starting @ 0x00080000.
-#
-# SAM3X8E has 512K of flash.
-#
-config FLASH_SIZE
-	default 512 if SOC_ATMEL_SAM3X8E
-
-config FLASH_BASE_ADDRESS
-	default 0x00080000
+if ARM && SOC_ATMEL_SAM3
 
 config SOC_ATMEL_SAM3_EXT_SLCK
 	bool "Atmel SAM3 to use external crystal oscillator for slow clock"
@@ -125,60 +80,4 @@ config SOC_ATMEL_SAM3_PLLA_DIVA
 	With default of MULA == 6, and DIVA == 1,
 	PLL is running at 7 times of main clock.
 
-config KERNEL_INIT_PRIORITY_DEFAULT
-	default 40
-
-config KERNEL_INIT_PRIORITY_DEVICE
-	default 50
-
-config UART_CONSOLE_PRIORITY
-	default 60
-
-if UART_ATMEL_SAM3
-
-config UART_ATMEL_SAM3_BAUD_RATE
-	default 115200
-
-config UART_ATMEL_SAM3_CLK_FREQ
-	default 84000000
-
-endif # UART_ATMEL_SAM3
-
-if UART_CONSOLE
-
-config UART_CONSOLE_ON_DEV_NAME
-	default "UART_0"
-config UART_CONSOLE_IRQ
-	default 8
-config UART_CONSOLE_IRQ_PRI
-	default 3
-
-endif # UART_CONSOLE
-
-if GPIO_ATMEL_SAM3
-
-config GPIO_ATMEL_SAM3_PORTA
-	default y
-
-config GPIO_ATMEL_SAM3_PORTB
-	default y
-
-config GPIO_ATMEL_SAM3_PORTC
-	default y
-
-config GPIO_ATMEL_SAM3_PORTD
-	default y
-
-endif # GPIO_ATMEL_SAM3
-
-if I2C_ATMEL_SAM3
-
-config I2C_ATMEL_SAM3_0
-	default y
-
-config I2C_ATMEL_SAM3_1
-	default y
-
-endif # I2C_ATMEL_SAM3
-
 endif # SOC_ATMEL_SAM3

arch/arm/soc/atmel_sam3/Kconfig.defconfig

@@ -0,0 +1,115 @@
+# Kconfig - Atmel SAM3 family processor configuration options
+
+#
+# Copyright (c) 2016 Intel Corporation.
+# Copyright (c) 2014-2015 Wind River Systems, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_ATMEL_SAM3
+
+config SOC
+	default atmel_sam3
+
+config NUM_IRQ_PRIO_BITS
+	int
+	default 3
+
+#
+# SAM3X8E has total 45 peripherals capable of
+# generating interrupts.
+#
+config NUM_IRQS
+	int
+	default 45
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 84000000
+
+#
+# SRAM address depends on the processor.
+#
+# SAM3X8E has two SRAM banks:
+#   64K @ 0x20000000
+#   32K @ 0x20080000
+# The first 64K is mirrored at 0x20070000
+# to provide one continuous 96K block.
+#
+config SRAM_SIZE
+	default 96 if SOC_ATMEL_SAM3X8E
+
+config SRAM_BASE_ADDRESS
+	default 0x20000000 if !SOC_ATMEL_SAM3X8E
+	default 0x20070000 if SOC_ATMEL_SAM3X8E
+
+#
+# Atmel SAM3 family has flash starting @ 0x00080000.
+#
+# SAM3X8E has 512K of flash.
+#
+config FLASH_SIZE
+	default 512 if SOC_ATMEL_SAM3X8E
+
+config FLASH_BASE_ADDRESS
+	default 0x00080000
+
+if UART_ATMEL_SAM3
+
+config UART_ATMEL_SAM3_BAUD_RATE
+	default 115200
+
+config UART_ATMEL_SAM3_CLK_FREQ
+	default 84000000
+
+endif # UART_ATMEL_SAM3
+
+if GPIO
+
+config GPIO_ATMEL_SAM3
+	def_bool y
+
+config GPIO_ATMEL_SAM3_PORTA
+	default y
+
+config GPIO_ATMEL_SAM3_PORTB
+	default y
+
+config GPIO_ATMEL_SAM3_PORTC
+	default y
+
+config GPIO_ATMEL_SAM3_PORTD
+	default y
+
+endif # GPIO
+
+if I2C
+
+config I2C_ATMEL_SAM3
+	def_bool y
+
+config I2C_0
+	default y
+config I2C_0_IRQ_PRI
+	default 0
+
+config I2C_1
+	default y
+
+config I2C_1_IRQ_PRI
+	default 0
+
+endif # I2C
+
+endif # SOC_ATMEL_SAM3

arch/arm/soc/atmel_sam3/Kconfig.soc

@@ -4,3 +4,4 @@ config SOC_ATMEL_SAM3X8E
 	select CPU_CORTEX_M
 	select CPU_CORTEX_M3
 	select SOC_ATMEL_SAM3
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED

arch/arm/soc/atmel_sam3/Makefile

@@ -1,6 +1 @@
-
-arch-cflags += $(call cc-option,-mthumb -march=armv7-m)
-
-KBUILD_AFLAGS += $(arch-cflags)
-KBUILD_CXXFLAGS += $(arch-cflags)
-KBUILD_CFLAGS += $(arch-cflags)
+obj-y += soc.o

arch/arm/soc/atmel_sam3/linker.ld

@@ -1,4 +1,4 @@
-/* linker.cmd - Linker command/script file */
+/* linker.ld - Linker command/script file */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
@@ -16,4 +16,4 @@
  * limitations under the License.
  */
 
-#include <arch/arm/cortex_m/scripts/linker.cmd>
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/atmel_sam3/soc.c

@@ -28,12 +28,7 @@
 #include <init.h>
 #include <soc.h>
 
-#ifdef CONFIG_RUNTIME_NMI
-extern void _NmiInit(void);
-#define NMI_INIT() _NmiInit()
-#else
-#define NMI_INIT()
-#endif
+#include <arch/cpu.h>
 
 /**
  * @brief Setup various clock on SoC.
@@ -43,7 +38,7 @@ extern void _NmiInit(void);
  * Assumption:
  * SLCK = 32.768kHz
  */
-static void clock_init(void)
+static ALWAYS_INLINE void clock_init(void)
 {
 	uint32_t tmp;
 

arch/arm/soc/fsl_frdm_k64f/Kbuild

@@ -1,6 +0,0 @@
-obj-y += soc_config.o
-obj-y += soc.o
-obj-y += nmi_on_reset.o
-obj-y += wdog.o
-
-obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o

arch/arm/soc/fsl_frdm_k64f/Kconfig

@@ -1,162 +0,0 @@
-# Kconfig - FSL FRDM K64F platform configuration options
-
-#
-# Copyright (c) 2014-2015 Wind River Systems, Inc.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-
-if SOC_FSL_FRDM_K64F
-config SOC
-	default fsl_frdm_k64f
-
-config SRAM_BASE_ADDRESS
-	default 0x20000000
-
-config FLASH_BASE_ADDRESS
-	default 0x00000000
-
-config NUM_IRQ_PRIO_BITS
-	int
-	default 4
-
-config NUM_IRQS
-	int
-	# must be >= the highest interrupt number used
-	default 86
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	int
-	default 120000000
-
-config WDOG_INIT
-	def_bool y
-	# omit prompt to signify a "hidden" option
-	help
-	This processor enables the watchdog timer with a short timeout
-	upon reset. Therefore, this requires that the watchdog be configured
-	during reset handling.
-
-config KERNEL_INIT_PRIORITY_DEFAULT
-	default 40
-
-config KERNEL_INIT_PRIORITY_DEVICE
-	default 50
-
-config UART_CONSOLE_PRIORITY
-	default 60
-
-if UART_K20
-
-config UART_K20_PORT_0
-	def_bool y
-
-if UART_K20_PORT_0
-config UART_K20_PORT_0_BASE_ADDR
-	default 0x4006A000
-config UART_K20_PORT_0_IRQ
-	default 31
-config UART_K20_PORT_0_IRQ_PRI
-	default 3
-config UART_K20_PORT_0_BAUD_RATE
-	default 115200
-config UART_K20_PORT_0_CLK_FREQ
-	default 120000000
-endif
-
-config UART_K20_PORT_1
-	def_bool y
-
-if UART_K20_PORT_1
-config UART_K20_PORT_1_BASE_ADDR
-	default 0x4006B000
-config UART_K20_PORT_1_IRQ
-	default 33
-config UART_K20_PORT_1_IRQ_PRI
-	default 3
-config UART_K20_PORT_1_BAUD_RATE
-	default 115200
-config UART_K20_PORT_1_CLK_FREQ
-	default 120000000
-endif
-
-config UART_K20_PORT_2
-	def_bool y
-if UART_K20_PORT_2
-config UART_K20_PORT_2_BASE_ADDR
-	default 0x4006C000
-config UART_K20_PORT_2_IRQ
-	default 35
-config UART_K20_PORT_2_IRQ_PRI
-	default 3
-config UART_K20_PORT_2_BAUD_RATE
-	default 115200
-config UART_K20_PORT_2_CLK_FREQ
-	default 120000000
-endif
-
-config UART_K20_PORT_3
-	def_bool y
-if UART_K20_PORT_3
-config UART_K20_PORT_3_BASE_ADDR
-	default 0x4006D000
-config UART_K20_PORT_3_IRQ
-	default 37
-config UART_K20_PORT_3_IRQ_PRI
-	default 3
-config UART_K20_PORT_3_BAUD_RATE
-	default 115200
-config UART_K20_PORT_3_CLK_FREQ
-	default 120000000
-endif
-
-config UART_K20_PORT_4
-	def_bool y
-if UART_K20_PORT_4
-config UART_K20_PORT_4_BASE_ADDR
-	default 0x400EA000
-config UART_K20_PORT_4_IRQ
-	default 66
-config UART_K20_PORT_4_IRQ_PRI
-	default 3
-config UART_K20_PORT_4_BAUD_RATE
-	default 115200
-config UART_K20_PORT_4_CLK_FREQ
-	default 120000000
-endif
-
-endif # UART_K20
-
-if UART_CONSOLE
-
-config UART_CONSOLE_ON_DEV_NAME
-	default "UART_0"
-config UART_CONSOLE_IRQ
-	default 31
-config UART_CONSOLE_IRQ_PRI
-	default 3
-
-endif
-
-if BLUETOOTH_UART
-
-config BLUETOOTH_UART_ON_DEV_NAME
-	default "UART_1"
-config BLUETOOTH_UART_IRQ
-	default 33
-config BLUETOOTH_UART_IRQ_PRI
-	default 3
-
-endif
-
-endif

arch/arm/soc/fsl_frdm_k64f/Kconfig.soc

@@ -1,5 +0,0 @@
-
-config  SOC_FSL_FRDM_K64F
-	bool "Freescale FRDM-K64F"
-	select CPU_CORTEX_M
-	select CPU_CORTEX_M4

arch/arm/soc/fsl_frdm_k64f/Makefile

@@ -1,6 +0,0 @@
-
-arch-cflags = $(call cc-option,-mthumb -march=armv7e-m)
-
-KBUILD_CFLAGS += $(arch-cflags)
-KBUILD_CXXFLAGS += $(arch-cflags)
-KBUILD_AFLAGS += $(arch-cflags)

arch/arm/soc/fsl_frdm_k64f/irq_vector_table.c

@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file
- * @brief IRQ part of vector table
- *
- * This file contains the IRQ part of the vector table. It is meant to be used
- * for one of two cases:
- *
- * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
- *    binds _isr_wrapper() to all the IRQ entries in the vector table.
- *
- * b) When the platform is written so that device ISRs are installed directly in
- *    the vector table, they are enumerated here.
- */
-
-#include <toolchain.h>
-#include <sections.h>
-
-#if defined(CONFIG_CONSOLE_HANDLER)
-#include <soc.h>
-#include <console/uart_console.h>
-#endif /* CONFIG_CONSOLE_HANDLER */
-
-#if defined(CONFIG_BLUETOOTH_UART)
-#include <soc.h>
-#include <bluetooth/uart.h>
-#endif /* CONFIG_BLUETOOTH_UART */
-
-extern void _isr_wrapper(void);
-typedef void (*vth)(void); /* Vector Table Handler */
-
-#if defined(CONFIG_SW_ISR_TABLE)
-
-vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
-	[0 ...(CONFIG_NUM_IRQS - 1)] = _isr_wrapper,
-};
-
-#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
-
-extern void _irq_spurious(void);
-
-#if defined(CONFIG_CONSOLE_HANDLER)
-static void _uart_console_isr(void)
-{
-	uart_console_isr(NULL);
-	_IntExit();
-}
-#endif /* CONFIG_CONSOLE_HANDLER */
-
-#if defined(CONFIG_BLUETOOTH_UART)
-static void _bt_uart_isr(void)
-{
-	bt_uart_isr(NULL);
-	_IntExit();
-}
-#endif /* CONFIG_BLUETOOTH_UART */
-
-/* placeholders: fill with real ISRs */
-vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
-	[0 ...(CONFIG_NUM_IRQS - 1)] = _irq_spurious,
-#if defined(CONFIG_CONSOLE_HANDLER)
-	[CONFIG_UART_CONSOLE_IRQ] = _uart_console_isr,
-#endif
-#if defined(CONFIG_BLUETOOTH_UART)
-	[CONFIG_BLUETOOTH_UART_IRQ] = _bt_uart_isr,
-#endif
-};
-
-#endif /* CONFIG_SW_ISR_TABLE */

arch/arm/soc/nordic_nrf5/Kbuild

@@ -0,0 +1,2 @@
+
+obj-y += $(SOC_SERIES)/

arch/arm/soc/nordic_nrf5/Kconfig

@@ -0,0 +1,29 @@
+# Kconfig - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config SOC_NRF5
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
+
+if SOC_FAMILY_NRF5
+config SOC_FAMILY
+	string
+	default nordic_nrf5
+endif
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.soc"

arch/arm/soc/nordic_nrf5/Kconfig.defconfig

@@ -0,0 +1,18 @@
+# Kconfig.defconfig - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.defconfig.series"

arch/arm/soc/nordic_nrf5/Kconfig.soc

@@ -0,0 +1,19 @@
+# Kconfig.soc - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.series"
+

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52832

@@ -0,0 +1,40 @@
+# Kconfig.defconfig.nrf52832 - Nordic Semiconductor nRF52832 MCU
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+
+if SOC_NRF52832
+
+config SOC
+	string
+	default nRF52832
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 64000000
+
+config SRAM_SIZE
+	default 64
+
+config FLASH_SIZE
+	default 512
+
+config NUM_IRQS
+	int
+	default 38
+
+endif # SOC_NRF52832
+

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.series

@@ -0,0 +1,35 @@
+# Kconfig.defconfig.series - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_SERIES_NRF52X
+
+source "arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52*"
+
+config SOC_SERIES
+	default nordic_nrf5/nrf52
+
+config SRAM_BASE_ADDRESS
+	default 0x20000000
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config NUM_IRQ_PRIO_BITS
+	int
+	default 3
+
+endif # SOC_SERIES_NRF52X

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.series

@@ -0,0 +1,28 @@
+# Kconfig.series - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config  SOC_SERIES_NRF52X
+	bool "Nordic Semiconductor nRF52 series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_NRF5
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select XIP
+	select HAS_CMSIS
+	select HAS_NORDIC_MDK
+	help
+	 Enable support for NRF52 MCU series

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.soc

@@ -0,0 +1,25 @@
+# Kconfig.soc - Nordic Semiconductor nRF52 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+choice
+prompt "nRF52x MCU Selection"
+depends on SOC_SERIES_NRF52X
+
+config SOC_NRF52832
+	bool "NRF52832"
+
+endchoice

arch/arm/soc/nordic_nrf5/nrf52/Makefile

@@ -0,0 +1,19 @@
+ifdef CONFIG_SOC_SERIES_NRF52X
+soc-cflags += -DNRF52
+endif
+
+obj-y += soc.o
+
+KERNEL_HEX_NAME = $(KERNEL_NAME).hex
+
+quiet_cmd_gen_hex = HEX     $@
+      cmd_gen_hex =                                                         \
+(                                                                           \
+   $(OBJCOPY) -S -O ihex -R .note -R .comment -R COMMON -R .eh_frame $< $@; \
+)
+
+$(KERNEL_HEX_NAME): $(KERNEL_ELF_NAME)
+	$(call cmd,gen_hex)
+
+zephyr: $(KERNEL_HEX_NAME)
+all: $(KERNEL_HEX_NAME)

arch/arm/soc/nordic_nrf5/nrf52/linker.ld

@@ -1,4 +1,4 @@
-/* linker.cmd - Linker command/script file */
+/* linker.ld - Linker command/script file */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
@@ -16,4 +16,4 @@
  * limitations under the License.
  */
 
-#include <arch/arm/cortex_m/scripts/linker.cmd>
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/nordic_nrf5/nrf52/soc.c

@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Nordic Semiconductor nRF52 family processor
+ *
+ * This module provides routines to initialize and support board-level hardware
+ * for the Nordic Semiconductor nRF52 family processor.
+ */
+
+#include <nanokernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+
+#ifdef CONFIG_RUNTIME_NMI
+extern void _NmiInit(void);
+#define NMI_INIT() _NmiInit()
+#else
+#define NMI_INIT()
+#endif
+
+#include "nrf.h"
+
+#define __SYSTEM_CLOCK_64M (64000000UL)
+
+static bool ftpan_32(void);
+static bool ftpan_37(void);
+static bool ftpan_36(void);
+
+uint32_t SystemCoreClock __used = __SYSTEM_CLOCK_64M;
+
+static void clock_init(void)
+{
+	SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+static int nordicsemi_nrf52_init(struct device *arg)
+{
+	uint32_t key;
+
+	ARG_UNUSED(arg);
+
+	/* Note:
+	* Magic numbers below are obtained by reading the registers
+	* when the SoC was running the SAM-BA bootloader
+	* (with reserved bits set to 0).
+	*/
+
+	key = irq_lock();
+
+	/* Setup the vector table offset register (VTOR),
+	* which is located at the beginning of flash area.
+	*/
+	_scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS);
+
+	/* Workaround for FTPAN-32 "DIF: Debug session automatically
+	* enables TracePort pins" found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_32()) {
+		CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
+	}
+
+	/* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio,
+	* ECB, AAR and CCM." found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_37()) {
+		*(volatile uint32_t *)0x400005A0 = 0x3;
+	}
+
+	/* Workaround for FTPAN-36 "CLOCK: Some registers are not
+	* reset when expected." found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_36()) {
+		NRF_CLOCK->EVENTS_DONE = 0;
+		NRF_CLOCK->EVENTS_CTTO = 0;
+	}
+
+	/* Enable the FPU if the compiler used floating point unit
+	* instructions. __FPU_USED is a MACRO defined by the
+	* compiler. Since the FPU consumes energy, remember to
+	* disable FPU use in the compiler if floating point unit
+	* operations are not used in your code.
+	*/
+	#if (__FPU_USED == 1)
+
+	SCB->CPACR |= (3UL << 20) | (3UL << 22);
+	__DSB();
+	__ISB();
+
+	#endif
+
+	/* Configure NFCT pins as GPIOs if NFCT is not to be used in
+	* your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+	* two GPIOs (see Product Specification to see which ones)
+	* will be reserved for NFC and will not be available as
+	* normal GPIOs.
+	*/
+	#if defined(CONFIG_NFCT_PINS_AS_GPIOS)
+
+	if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) ==
+	    (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)) {
+
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NVIC_SystemReset();
+	}
+
+	#endif
+
+	/* Configure GPIO pads as pPin Reset pin if Pin Reset
+	* capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+	* defined, pin reset will not be available. One GPIO (see
+	* Product Specification to see which one) will then be
+	* reserved for PinReset and not available as normal GPIO.
+	*/
+	#if defined(CONFIG_GPIO_AS_PINRESET)
+	if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
+	     (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+	    ((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
+	     (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) {
+
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->PSELRESET[0] = 21;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->PSELRESET[1] = 21;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NVIC_SystemReset();
+	}
+	#endif
+
+	/* Enable SWO trace functionality. If ENABLE_SWO is not
+	* defined, SWO pin will be used as GPIO (see Product
+	* Specification to see which one).
+	*/
+	#if defined(ENABLE_SWO)
+
+	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+	NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial <<
+				  CLOCK_TRACECONFIG_TRACEMUX_Pos;
+	#endif
+
+	/* Enable Trace functionality. If ENABLE_TRACE is not
+	* defined, TRACE pins will be used as GPIOs (see Product
+	* Specification to see which ones).
+	*/
+	#if defined(ENABLE_TRACE)
+	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+	NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel <<
+				  CLOCK_TRACECONFIG_TRACEMUX_Pos;
+	#endif
+
+	/* Clear all faults */
+	_ScbMemFaultAllFaultsReset();
+	_ScbBusFaultAllFaultsReset();
+	_ScbUsageFaultAllFaultsReset();
+
+	_ScbHardFaultAllFaultsReset();
+
+	/* Setup master clock */
+	clock_init();
+
+	/* Install default handler that simply resets the CPU
+	* if configured in the kernel, NOP otherwise
+	*/
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+static bool ftpan_32(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static bool ftpan_37(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static bool ftpan_36(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+SYS_INIT(nordicsemi_nrf52_init, PRIMARY, 0);

arch/arm/soc/nordic_nrf5/nrf52/soc.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file SoC configuration macros for the Nordic Semiconductor nRF52 family processors.
+ */
+
+#ifndef _NORDICSEMI_NRF52_SOC_H_
+#define _NORDICSEMI_NRF52_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include "soc_irq.h"
+#include <nrf52.h>
+#include <nrf52_bitfields.h>
+#include <device.h>
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _NORDICSEMI_NRF52_SOC_H_ */

arch/arm/soc/nordic_nrf5/nrf52/soc_irq.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Interrupt numbers for NRF52 family processors.
+ *
+ * Based on Nordic MDK included header file: nrf52.h
+ */
+
+
+#ifndef _NRF52_SOC_IRQ_H_
+#define _NRF52_SOC_IRQ_H_
+
+#define NRF52_IRQ_POWER_CLOCK_IRQn			 0
+#define NRF52_IRQ_RADIO_IRQn				 1
+#define NRF52_IRQ_UARTE0_UART0_IRQn			 2
+#define NRF52_IRQ_SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn 3
+#define NRF52_IRQ_SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn 4
+#define NRF52_IRQ_NFCT_IRQn				 5
+#define NRF52_IRQ_GPIOTE_IRQn				 6
+#define NRF52_IRQ_SAADC_IRQn				 7
+#define NRF52_IRQ_TIMER0_IRQn				 8
+#define NRF52_IRQ_TIMER1_IRQn				 9
+#define NRF52_IRQ_TIMER2_IRQn				 10
+#define NRF52_IRQ_RTC0_IRQn				 11
+#define NRF52_IRQ_TEMP_IRQn				 12
+#define NRF52_IRQ_RNG_IRQn				 13
+#define NRF52_IRQ_ECB_IRQn				 14
+#define NRF52_IRQ_CCM_AAR_IRQn				 15
+#define NRF52_IRQ_WDT_IRQn				 16
+#define NRF52_IRQ_RTC1_IRQn				 17
+#define NRF52_IRQ_QDEC_IRQn				 18
+#define NRF52_IRQ_COMP_LPCOMP_IRQn			 19
+#define NRF52_IRQ_SWI0_EGU0_IRQn			 20
+#define NRF52_IRQ_SWI1_EGU1_IRQn			 21
+#define NRF52_IRQ_SWI2_EGU2_IRQn			 22
+#define NRF52_IRQ_SWI3_EGU3_IRQn			 23
+#define NRF52_IRQ_SWI4_EGU4_IRQn			 24
+#define NRF52_IRQ_SWI5_EGU5_IRQn			 25
+#define NRF52_IRQ_TIMER3_IRQn				 26
+#define NRF52_IRQ_TIMER4_IRQn				 27
+#define NRF52_IRQ_PWM0_IRQn				 28
+#define NRF52_IRQ_PDM_IRQn				 29
+#define NRF52_IRQ_MWU_IRQn				 32
+#define NRF52_IRQ_PWM1_IRQn				 33
+#define NRF52_IRQ_PWM2_IRQn				 34
+#define NRF52_IRQ_SPIM2_SPIS2_SPI2_IRQn			 35
+#define NRF52_IRQ_RTC2_IRQn				 36
+#define NRF52_IRQ_I2S_IRQn				 37
+#define NRF52_IRQ_FPU_IRQn				 38
+
+#endif /* _NRF52_SOC_IRQ_H_ */