Zephyr v1.4.0

Change-Id: Iedb103de08349c3a046247cbdcf6498126765d72
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.checkpatch.conf

@@ -3,14 +3,15 @@
 --emacs
 --summary-file
 --show-types
---max-line-length=100
+--max-line-length=80
+--min-conf-desc-length=1
 
 --ignore BRACES
 --ignore PRINTK_WITHOUT_KERN_LEVEL
 --ignore SPLIT_STRING
---ignore FILE_PATH_CHANGES
 --ignore VOLATILE
 --ignore CONFIG_EXPERIMENTAL
 --ignore PREFER_KERNEL_TYPES
 --ignore AVOID_EXTERNS
 --ignore NETWORKING_BLOCK_COMMENT_STYLE
+--exclude ext

.gitignore

@@ -5,7 +5,6 @@
 *.pyc
 *.swp
 *.swo
-!arch/*/*/**/*.cmd
 *~
 cscope.*
 .dir

.mailmap

@@ -5,3 +5,9 @@ Leona Cook <leonax.cook@intel.com> <lsc@hackeress.com>
 Leona Cook <leonax.cook@intel.com> <leonax.cook@intel.com>
 Thomas Heeley <thomas.heeley@intel.com> <thomas.heeley@intel.com>
 Shuang He <shuang.he@intel.com> <shuang.he@intel.com>
+Chuck Jordan <cjordan@synopsys.com> <cjordan@synopsys.com>
+Jeremie Garcia <jeremie.garcia@intel.com> <jeremie.garcia@intel.com>
+Bit Pathe <bitpathe@gmail.com> <bitpathe@gmail.com>
+Carles Cufi <carles.cufi@nordicsemi.no> <carles.cufi@nordicsemi.no>
+Kuo-Lang Tseng <kuo-lang.tseng@intel.com> <kuo-lang.tseng@intel.com>
+Gerardo Aceves <gerardo.aceves@intel.com> <gerardo.aceves@intel.com>

Kbuild

@@ -94,7 +94,7 @@ OFFSETS_INCLUDE = $(strip \
 
 cmd_cc_o_c_1 = $(CC) $(KBUILD_CFLAGS) $(OFFSETS_INCLUDE) -c -o $@ $<
 
-arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c
+arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c $(KCONFIG_CONFIG)
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed,cc_o_c_1)
 

Kconfig.zephyr

@@ -17,8 +17,8 @@
 # limitations under the License.
 #
 config KERNELVERSION
-        string
-        option env="KERNELVERSION"
+	string
+	option env="KERNELVERSION"
 
 source "arch/Kconfig"
 
@@ -30,6 +30,10 @@ source "net/Kconfig"
 
 source "misc/Kconfig"
 
+source "lib/Kconfig"
+
+source "ext/Kconfig"
+
 #
 # The following are for Kconfig files for default values only.
 # These should be parsed at the end.

MAINTAINERS

@@ -0,0 +1,132 @@
+Originally from the Linux Kernel.
+# Licensed under the terms of the GNU GPL License version 2
+
+Descriptions of section entries:
+
+	P: Person (obsolete)
+	M: Mail patches to: FullName <address@domain>
+	R: Designated reviewer: FullName <address@domain>
+	   These reviewers should be CCed on patches.
+	L: Mailing list that is relevant to this area
+	W: Web-page with status/info
+	Q: Patchwork web based patch tracking system site
+	T: SCM tree type and location.
+	   Type is one of: git, hg, quilt, stgit, topgit
+	S: Status, one of the following:
+	   Supported:	Someone is actually paid to look after this.
+	   Maintained:	Someone actually looks after it.
+	   Odd Fixes:	It has a maintainer but they don't have time to do
+			much other than throw the odd patch in. See below..
+	   Orphan:	No current maintainer [but maybe you could take the
+			role as you write your new code].
+	   Obsolete:	Old code. Something tagged obsolete generally means
+			it has been replaced by a better system and you
+			should be using that.
+	F: Files and directories with wildcard patterns.
+	   A trailing slash includes all files and subdirectory files.
+	   F:	drivers/net/	all files in and below drivers/net
+	   F:	drivers/net/*	all files in drivers/net, but not below
+	   F:	*/net/*		all files in "any top level directory"/net
+	   One pattern per line.  Multiple F: lines acceptable.
+	N: Files and directories with regex patterns.
+	   N:	[^a-z]tegra	all files whose path contains the word tegra
+	   One pattern per line.  Multiple N: lines acceptable.
+	   scripts/get_maintainer.pl has different behavior for files that
+	   match F: pattern and matches of N: patterns.  By default,
+	   get_maintainer will not look at git log history when an F: pattern
+	   match occurs.  When an N: match occurs, git log history is used
+	   to also notify the people that have git commit signatures.
+	X: Files and directories that are NOT maintained, same rules as F:
+	   Files exclusions are tested before file matches.
+	   Can be useful for excluding a specific subdirectory, for instance:
+	   F:	net/
+	   X:	net/ipv6/
+	   matches all files in and below net excluding net/ipv6/
+	K: Keyword perl extended regex pattern to match content in a
+	   patch or file.  For instance:
+	   K: of_get_profile
+	      matches patches or files that contain "of_get_profile"
+	   K: \b(printk|pr_(info|err))\b
+	      matches patches or files that contain one or more of the words
+	      printk, pr_info or pr_err
+	   One regex pattern per line.  Multiple K: lines acceptable.
+
+Note: For the hard of thinking, this list is meant to remain in alphabetical
+order. If you could add yourselves to it in alphabetical order that would be
+so much easier [Ed]
+
+Maintainers List (try to look for most precise areas first)
+
+		-----------------------------------
+
+BLUETOOTH
+M:	Johan Hedberg <johan.hedberg@intel.com>
+M:	Luiz Augusto von Dentz <luiz.dentz@gmail.com>
+M:	Szymon Janc <szymon.janc@gmail.com>
+S:	Supported
+F:	net/bluetooth/
+F:	include/bluetooth/
+F:	drivers/bluetooth/
+F:	samples/bluetooth/
+F:	tests/bluetooth/
+
+DOCUMENTATION
+M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
+S:	Supported
+F:	doc/
+
+FLASH DRIVER
+M:	Baohong Liu <baohong.liu@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	drivers/flash/
+
+NORDIC MDK
+M:	Carles Cufi <carles.cufi@nordicsemi.no>
+S:	Supported
+F:	ext/hal/nordic/mdk
+
+POWER MANAGEMENT
+M:	Ramesh Thomas <ramesh.thomas@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	arch/x86/core/crt0.S
+F:	include/device.h
+F:	include/init.h
+F:	include/power.h
+F:	kernel/microkernel/k_idle.c
+F:	kernel/nanokernel/device.c
+F:	samples/power/
+
+QMSI
+M:	Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	ext/hal/qmsi/
+
+QMSI DRIVERS
+M:	Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
+M:	Baohong Liu <baohong.liu@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	drivers/*/*qmsi*
+F:	drivers/*/*/*qmsi*
+
+SANITYCHECK
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	scripts/sanitycheck
+F:	scripts/expr_parser.py
+F:	scripts/sanity_chk/
+
+TINYCRYPT
+M:	Constanza Heath <constanza.m.heath@intel.com>
+S:	Supported
+F:	ext/lib/crypto/tinycrypt
+
+THE REST
+M:	Anas Nashif <anas.nashif@intel.com>
+L:	devel@lists.zephyrproject.com
+T:	git https://gerrit.zephyrproject.org/r/a/zephyr
+S:	Buried alive in reporters
+F:	*
+F:	*/

Makefile

@@ -1,5 +1,5 @@
 VERSION_MAJOR 	   = 1
-VERSION_MINOR 	   = 3
+VERSION_MINOR 	   = 4
 PATCHLEVEL 	   = 0
 VERSION_RESERVED   = 0
 EXTRAVERSION       =
@@ -28,6 +28,9 @@ ifeq (MINGW, $(findstring MINGW, $(UNAME)))
 HOST_OS=MINGW
 PWD_OPT=-W
 DISABLE_TRYRUN=y
+CPATH ?= $(MIGW_DIR)/include
+LIBRARY_PATH ?= $(MINGW_DIR)/lib
+export CPATH LIBRARY_PATH
 else ifeq (Linux, $(findstring Linux, $(UNAME)))
 HOST_OS=Linux
 else ifeq (Darwin, $(findstring Darwin, $(UNAME)))
@@ -298,8 +301,8 @@ ifeq ($(USE_CCACHE),1)
 CC		= $(CCACHE) $(CROSS_COMPILE)gcc
 CXX		= $(CCACHE) $(CROSS_COMPILE)g++
 else
-CC		= $(CROSS_COMPILE)gcc
-CXX		= $(CROSS_COMPILE)g++
+CC		?= $(CROSS_COMPILE)gcc
+CXX		?= $(CROSS_COMPILE)g++
 endif
 CPP		= $(CC) -E
 AR		= $(CROSS_COMPILE)ar
@@ -308,6 +311,7 @@ STRIP		= $(CROSS_COMPILE)strip
 OBJCOPY		= $(CROSS_COMPILE)objcopy
 OBJDUMP		= $(CROSS_COMPILE)objdump
 GDB		= $(CROSS_COMPILE)gdb
+READELF		= $(CROSS_COMPILE)readelf
 AWK		= awk
 GENIDT		= scripts/gen_idt/gen_idt
 GENOFFSET_H	= scripts/gen_offset_header/gen_offset_header
@@ -344,6 +348,7 @@ BOARD_NAME = $(subst $(DQUOTE),,$(CONFIG_BOARD))
 KERNEL_NAME = $(subst $(DQUOTE),,$(CONFIG_KERNEL_BIN_NAME))
 KERNEL_ELF_NAME = $(KERNEL_NAME).elf
 KERNEL_BIN_NAME = $(KERNEL_NAME).bin
+KERNEL_STAT_NAME = $(KERNEL_NAME).stat
 
 export SOC_FAMILY SOC_SERIES SOC_PATH SOC_NAME BOARD_NAME
 export ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME
@@ -511,7 +516,7 @@ scripts: scripts_basic include/config/auto.conf include/config/tristate.conf
 	$(Q)$(MAKE) $(build)=$(@)
 
 
-core-y := lib/ kernel/ misc/ net/ boards/ arch/
+core-y := lib/ kernel/ misc/ net/ boards/ arch/ ext/
 drivers-y := drivers/
 
 ifneq ($(strip $(MAKEFILE_APP_DIR)),)
@@ -554,13 +559,6 @@ else
 include/config/auto.conf: ;
 endif # $(dot-config)
 
-ifdef CONFIG_TINYCRYPT
-# Objects we will link into the kernel / subdirs we need to visit
-KCRYPTO_DIR := lib/crypto/tinycrypt
-libs-y += $(KCRYPTO_DIR)/
- ZEPHYRINCLUDE += -I$(srctree)/lib/crypto/tinycrypt/include
-endif
-
 ARCH = $(subst $(DQUOTE),,$(CONFIG_ARCH))
 export ARCH
 ifdef ZEPHYR_GCC_VARIANT
@@ -570,6 +568,10 @@ $(if $(CROSS_COMPILE),, \
      $(error ZEPHYR_GCC_VARIANT is not set. ))
 endif
 
+
+-include $(srctree)/lib/Makefile
+-include $(srctree)/ext/Makefile
+
 ifneq ($(CC),)
 ifeq ($(shell $(CC) -v 2>&1 | grep -Ec "clang version|icx version"), 1)
 COMPILER := clang
@@ -579,20 +581,6 @@ endif
 export COMPILER
 endif
 
-ifdef CONFIG_QMSI_LIBRARY
-LIB_INCLUDE_DIR += -L$(CONFIG_QMSI_INSTALL_PATH:"%"=%)/lib
-ALL_LIBS += qmsi
-endif
-
-ifdef CONFIG_MINIMAL_LIBC
-ZEPHYRINCLUDE += -I$(srctree)/lib/libc/minimal/include
-endif
-
-ifdef CONFIG_NEWLIB_LIBC
-ZEPHYRINCLUDE += $(TOOLCHAIN_CFLAGS)
-ALL_LIBS += m c
-endif
-
 QEMU_BIN_PATH	?= /usr/bin
 QEMU		= $(QEMU_BIN_PATH)/$(QEMU_$(ARCH))
 
@@ -697,11 +685,12 @@ KBUILD_CFLAGS += $(KCFLAGS)
 
 # Use --build-id when available.
 
+LINKFLAGPREFIX ?= -Wl,
 LDFLAGS_zephyr += $(LDFLAGS)
-LDFLAGS_zephyr += $(call ld-option,-X)
-LDFLAGS_zephyr += $(call ld-option,-N)
-LDFLAGS_zephyr += $(call ld-option,--gc-sections)
-LDFLAGS_zephyr += $(call ld-option,--build-id=none)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)-X)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)-N)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)--gc-sections)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)--build-id=none)
 
 LD_TOOLCHAIN ?= -D__GCC_LINKER_CMD__
 
@@ -709,11 +698,11 @@ ifdef CONFIG_HAVE_CUSTOM_LINKER_SCRIPT
 KBUILD_LDS         := $(subst $(DQUOTE),,$(CONFIG_CUSTOM_LINKER_SCRIPT))
 else
 # Try a board specific linker file
-KBUILD_LDS := $(srctree)/boards/$(BOARD_NAME)/linker.cmd
+KBUILD_LDS := $(srctree)/boards/$(BOARD_NAME)/linker.ld
 
 # If not available, try an SoC specific linker file
 ifeq ($(wildcard $(KBUILD_LDS)),)
-KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/linker.cmd
+KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/linker.ld
 endif
 endif
 
@@ -723,7 +712,7 @@ export LD_TOOLCHAIN KBUILD_LDS
 # command line.
 # This allow a user to issue only 'make' to build a kernel including modules
 # Defaults to zephyr, but the arch makefile usually adds further targets
-all: $(KERNEL_BIN_NAME)
+all: $(KERNEL_BIN_NAME) $(KERNEL_STAT_NAME)
 
 # Default kernel image to build when no specific target is given.
 # KBUILD_IMAGE may be overruled on the command line or
@@ -762,19 +751,21 @@ quiet_cmd_create-lnk = LINK    $@
       cmd_create-lnk =								\
 (										\
 	echo $(LDFLAGS_zephyr); 						\
-	echo "-Map ./$(KERNEL_NAME).map"; 					\
+	echo "$(LINKFLAGPREFIX)-Map=$(O)/$(KERNEL_NAME).map"; 			\
 	echo "-L $(objtree)/include/generated";					\
 	echo "-u _OffsetAbsSyms -u _ConfigAbsSyms"; 				\
 	echo "-e __start"; 						 	\
-	echo "--start-group";							\
-	echo "--whole-archive $(KBUILD_ZEPHYR_APP) --no-whole-archive";         \
+	echo "$(LINKFLAGPREFIX)--start-group";					\
+	echo "$(LINKFLAGPREFIX)--whole-archive";				\
+	echo "$(KBUILD_ZEPHYR_APP)";						\
+	echo "$(LINKFLAGPREFIX)--no-whole-archive";         			\
 	echo "$(KBUILD_ZEPHYR_MAIN)";						\
 	echo "$(objtree)/arch/$(ARCH)/core/offsets/offsets.o"; 			\
-	echo "--end-group"; 							\
+	echo "$(LINKFLAGPREFIX)--end-group"; 					\
 	echo "$(LIB_INCLUDE_DIR) $(LINK_LIBS)";					\
 ) > $@
 
-$(KERNEL_NAME).lnk:
+$(KERNEL_NAME).lnk: $(zephyr-deps)
 	$(call cmd,create-lnk)
 
 linker.cmd: $(zephyr-deps)
@@ -790,7 +781,7 @@ final-linker.cmd: $(zephyr-deps)
 TMP_ELF = .tmp_$(KERNEL_NAME).prebuilt
 
 $(TMP_ELF): $(zephyr-deps) $(KBUILD_ZEPHYR_APP) linker.cmd $(KERNEL_NAME).lnk
-	$(Q)$(LD) -T linker.cmd @$(KERNEL_NAME).lnk -o $@
+	$(Q)$(CC) -T linker.cmd @$(KERNEL_NAME).lnk -o $@
 
 quiet_cmd_gen_idt = SIDT    $@
       cmd_gen_idt =								\
@@ -816,19 +807,29 @@ staticIdt.o: $(TMP_ELF)
 quiet_cmd_lnk_elf = LINK    $@
       cmd_lnk_elf =									\
 (											\
-	$(LD) -T final-linker.cmd @$(KERNEL_NAME).lnk staticIdt.o int_vector_alloc.o 	\
+	$(CC) -T final-linker.cmd @$(KERNEL_NAME).lnk staticIdt.o int_vector_alloc.o 	\
 	irq_int_vector_map.o -o $@;							\
 	${OBJCOPY} --change-section-address intList=${CONFIG_PHYS_LOAD_ADDR} $@ elf.tmp;\
 	$(OBJCOPY) -R intList elf.tmp $@;						\
 	rm elf.tmp									\
 )
 
+ASSERT_WARNING_STR := \
+    "\n      ------------------------------------------------------------" \
+    "\n      --- WARNING:  __ASSERT() statements are globally ENABLED ---" \
+    "\n      --- The kernel will run more slowly and uses more memory ---" \
+    "\n      ------------------------------------------------------------\n\n" \
+
+WARN_ABOUT_ASSERT := $(if $(CONFIG_ASSERT),echo -e -n $(ASSERT_WARNING_STR),true)
+
 ifeq ($(ARCH),x86)
 $(KERNEL_ELF_NAME): staticIdt.o final-linker.cmd
 	$(call cmd,lnk_elf)
+	@$(WARN_ABOUT_ASSERT)
 else
 $(KERNEL_ELF_NAME): $(TMP_ELF)
 	@cp $(TMP_ELF) $(KERNEL_ELF_NAME)
+	@$(WARN_ABOUT_ASSERT)
 endif
 
 
@@ -843,6 +844,14 @@ quiet_cmd_gen_bin = BIN     $@
 $(KERNEL_BIN_NAME): $(KERNEL_ELF_NAME)
 	$(call cmd,gen_bin)
 
+$(KERNEL_STAT_NAME): $(KERNEL_BIN_NAME) $(KERNEL_ELF_NAME)
+	@$(READELF) -e $(KERNEL_ELF_NAME) > $@
+
+ram_report: $(KERNEL_STAT_NAME)
+	@$(srctree)/scripts/size_report -r -o $(O)
+rom_report: $(KERNEL_STAT_NAME)
+	@$(srctree)/scripts/size_report -F -o $(O)
+
 zephyr: $(zephyr-deps) $(KERNEL_BIN_NAME)
 
 # The actual objects are generated when descending,
@@ -1135,12 +1144,16 @@ tools/%: FORCE
 
 QEMU_FLAGS = $(QEMU_FLAGS_$(ARCH)) -pidfile qemu.pid
 
+ifneq ($(QEMU_PTY),)
+    QEMU_FLAGS += -serial pty
+else
 ifneq ($(QEMU_PIPE),)
     # Send console output to a pipe, used for running automated sanity tests
     QEMU_FLAGS += -serial pipe:$(QEMU_PIPE)
 else
     QEMU_FLAGS += -serial mon:stdio
 endif
+endif
 
 qemu: zephyr
 	$(if $(QEMU_PIPE),,@echo "To exit from QEMU enter: 'CTRL+a, x'")

Makefile.inc

@@ -6,7 +6,13 @@ DQUOTE = "
 
 ARCH ?= x86
 
+UNAME := $(shell uname)
+ifeq (MINGW, $(findstring MINGW, $(UNAME)))
+PROJECT_BASE ?= $(shell sh -c "pwd -W")
+else
 PROJECT_BASE ?= $(CURDIR)
+endif
+
 O ?= $(PROJECT_BASE)/outdir
 
 # Turn O into an absolute path; we call the main Kbuild with $(MAKE) -C
@@ -33,9 +39,9 @@ $(error BOARD is not defined!)
 endif
 
 SOURCE_DIR ?= $(PROJECT_BASE)/src/
-# Kbuild doesn't work correctly if this is an absolute path
-# FIXME Do not depend on python
-override SOURCE_DIR := $(shell python -c "import os.path; print(\"%s\" % os.path.relpath(os.path.realpath('$(SOURCE_DIR)'), os.path.realpath('$(ZEPHYR_BASE)')))")/
+override SOURCE_DIR := $(abspath $(SOURCE_DIR))
+# Kbuild doesn't work correctly if SOURCE_DIR is an absolute path
+override SOURCE_DIR := $(subst $(ZEPHYR_BASE),.,$(SOURCE_DIR))/
 override SOURCE_DIR := $(subst \,/,$(SOURCE_DIR))
 export SOURCE_DIR
 
@@ -54,9 +60,13 @@ else
   S = -s
 endif
 
-zephyrmake	= @+$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) CFLAGS=$(CFLAGS) \
+export CFLAGS
+
+zephyrmake	= @+$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) \
 			PROJECT=$(PROJECT_BASE) SOURCE_DIR=$(SOURCE_DIR) $(2)
 
+BOARDCONFIG = $(O)/.board_$(BOARD)
+
 DOTCONFIG = $(O)/.config
 
 all: $(DOTCONFIG)
@@ -88,6 +98,17 @@ debugserver: FORCE
 
 initconfig: $(DOTCONFIG)
 
+$(BOARDCONFIG):
+	@rm -f $(O)/.board_*
+	@touch $@
+
+
+ram_report: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
+rom_report: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
 menuconfig: initconfig
 	$(Q)$(call zephyrmake,$(O),$@)
 
@@ -100,7 +121,7 @@ help:
 
 KERNEL_CONFIG = $(ZEPHYR_BASE)/kernel/configs/$(KERNEL_TYPE).config
 
-$(DOTCONFIG): $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
+$(DOTCONFIG): $(BOARDCONFIG) $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
 	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/kconfig/merge_config.sh \
 		-q -m -O $(O) $(KBUILD_DEFCONFIG_PATH) $(KERNEL_CONFIG) $(CONF_FILE)
 	$(Q)$(MAKE) $(S) -C $(ZEPHYR_BASE) O=$(O) PROJECT=$(PROJECT_BASE) oldnoconfig

arch/Kconfig

@@ -32,6 +32,9 @@ config X86
 	bool "x86 architecture"
 	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
 
+config NIOS2
+	bool "Nios II Gen 2 architecture"
+
 endchoice
 
 #
@@ -40,19 +43,19 @@ endchoice
 #
 config SYS_POWER_LOW_POWER_STATE_SUPPORTED
 	# Hidden
-        bool
-        default n
-        help
-        This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
-        configuration option.
+	bool
+	default n
+	help
+	This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
+	configuration option.
 
 config SYS_POWER_DEEP_SLEEP_SUPPORTED
 	# Hidden
-        bool
-        default n
-        help
-        This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
-        configuration option.
+	bool
+	default n
+	help
+	This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
+	configuration option.
 #
 # End hidden PM feature configs
 #
@@ -89,7 +92,7 @@ config BOARD
 	help
 	This option holds the name of the board and is used to located the files
 	related to the board in the source tree (under boards/).
-	The Board is the first location where we search for a linker.cmd file,
+	The Board is the first location where we search for a linker.ld file,
 	if not found we look for the linker file in
 	arch/<arch>/soc/<family>/<series>
 

arch/arc/Kconfig

@@ -65,8 +65,6 @@ config NSIM
 	  a) Uses non-XIP to run in RAM.
 	  b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
 	     a pc_size of 16 (default).
-	  c) Sets the entry point to __reset, since it seems nSIM ignores the
-	     reset vector when starting (??).
 
 config	DATA_ENDIANNESS_LITTLE
 	bool
@@ -157,6 +155,28 @@ config	XIP
 	default n if NSIM
 	default y
 
+config HARVARD
+	prompt "Harvard Architecture"
+	bool
+	default n
+	help
+	  The ARC CPU can be configured to have two busses;
+	  one for instruction fetching and another that serves as a data bus.
+
+config ICCM_SIZE
+	int "ICCM Size in kB"
+	help
+	This option specifies the size of the ICCM in kB.  It is normally set by
+	the platform's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config ICCM_BASE_ADDRESS
+	hex "ICCM Base Address"
+	help
+	This option specifies the base address of the ICCM on the platform.  It is
+	normally set by the platform's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
 config DCCM_SIZE
 	int "DCCM Size in kB"
 	help
@@ -198,20 +218,8 @@ config FLASH_BASE_ADDRESS
 	This option specifies the base address of the flash on the platform.  It is
 	normally set by the platform's defconfig file and the user should generally
 	avoid modifying it via the menu configuration.
-config NSIM
-	prompt "Running on the MetaWare nSIM simulator"
-	bool
-	default n
-	help
-	For running on nSIM simulator.
 
-	a) Uses non-XIP to run in RAM.
-	b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
-	   a pc_size of 16 (default).
-	c) Sets the entry point to __reset, since it seems nSIM ignores the
-	   reset vector when starting.
-
-config  SW_ISR_TABLE
+config SW_ISR_TABLE
 	bool
 	prompt "Enable software interrupt handler table"
 	default y
@@ -224,7 +232,7 @@ config  SW_ISR_TABLE
 	  This has to be enabled for dynamically connecting interrupt handlers
 	  at runtime (SW_ISR_TABLE_DYNAMIC).
 
-config  SW_ISR_TABLE_DYNAMIC
+config SW_ISR_TABLE_DYNAMIC
 	bool
 	prompt "Allow installing interrupt handlers at runtime"
 	depends on SW_ISR_TABLE
@@ -234,7 +242,7 @@ config  SW_ISR_TABLE_DYNAMIC
 	  SRAM so that it is writable. This has the side-effect of removing
 	  write-protection on the ISR table.
 
-config  IRQ_VECTOR_TABLE_CUSTOM
+config IRQ_VECTOR_TABLE_CUSTOM
 	bool
 	prompt "Projects provide a custom static IRQ part of vector table"
 	depends on !SW_ISR_TABLE
@@ -264,12 +272,12 @@ config	IRQ_VECTOR_TABLE_BSP
 	help
 	  Not user-selectable, helps build system logic.
 
-config  ARCH_HAS_TASK_ABORT
+config ARCH_HAS_TASK_ABORT
 	bool
 	# omit prompt to signify a "hidden" option
 	default n
 
-config  ARCH_HAS_NANO_FIBER_ABORT
+config ARCH_HAS_NANO_FIBER_ABORT
 	bool
 	# omit prompt to signify a "hidden" option
 	default n

arch/arc/Makefile

@@ -7,3 +7,9 @@ include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 KBUILD_CFLAGS += $(cflags-y)
 KBUILD_CXXFLAGS += $(cflags-y)
 
+soc-cxxflags ?= $(soc-cflags)
+soc-aflags ?= $(soc-cflags)
+KBUILD_CFLAGS += $(soc-cflags)
+KBUILD_CXXFLAGS += $(soc-cxxflags)
+KBUILD_AFLAGS += $(soc-aflags)
+

arch/arc/core/Makefile

@@ -13,7 +13,6 @@ obj-y += prep_c.o \
          vector_table.o
 
 obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
-obj-$(CONFIG_ERRNO) += errno.o
 
 ifneq ($(CONFIG_ATOMIC_OPERATIONS_C),y)
 obj-y += atomic.o

arch/arc/core/cpu_idle.S

@@ -61,12 +61,17 @@ SECTION_VAR(BSS, nano_cpu_sleep_mode)
 
 SECTION_FUNC(TEXT, nano_cpu_idle)
 
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+	push_s blink
+	jl    _sys_k_event_logger_enter_sleep
+	pop_s blink
+#endif
 	enter_tickless_idle
 
 	ld r1, [nano_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
-	j_s.nd [blink]
+	j_s [blink]
 	nop
 
 /*
@@ -78,6 +83,12 @@ SECTION_FUNC(TEXT, nano_cpu_idle)
  */
 SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
 
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+	push_s blink
+	jl    _sys_k_event_logger_enter_sleep
+	pop_s blink
+#endif
+
 	enter_tickless_idle
 
 	ld r1, [nano_cpu_sleep_mode]

arch/arc/core/fast_irq.S

@@ -45,14 +45,16 @@ SECTION_VAR(NOINIT, _firq_stack)
  *
  * The processor switches to a second register bank so registers from the
  * current bank do not have to be preserved yet. The only issue is the LP_START/
- * LP_COUNT/LP_END registers, which are not banked.
+ * LP_COUNT/LP_END registers, which are not banked. These can be saved
+ * in available callee saved registers.
  *
  * If all FIRQ ISRs are programmed such that there are no use of the LP
  * registers (ie. no LPcc instruction), and CONFIG_ARC_STACK_CHECKING is
- * not set, then the kernel can be configured to remove the use of _firq_enter().
+ * not set, then the kernel can be configured to not save and restore them.
  *
  * When entering a FIRQ, interrupts might as well be locked: the processor is
- * running at its highest priority, and cannot be preempted by anything.
+ * running at its highest priority, and cannot be interrupted by any other
+ * interrupt. An exception, however, can be taken.
  *
  * Assumption by _isr_demux: r3 is untouched by _firq_enter.
  *
@@ -61,6 +63,11 @@ SECTION_VAR(NOINIT, _firq_stack)
 
 SECTION_FUNC(TEXT, _firq_enter)
 
+	/*
+	 * ATTENTION:
+	 * firq uses a 2nd register bank so GPRs do not need to be saved.
+	 */
+
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* disable stack checking */
 	lr r2, [_ARC_V2_STATUS32]
@@ -70,20 +77,13 @@ SECTION_FUNC(TEXT, _firq_enter)
 
 #ifndef CONFIG_FIRQ_NO_LPCC
 	/*
-	 * Unlike the rest of context switching code, r2 is loaded with something
-	 * else than 'current' in this routine: this is to preserve r3 so that it
-	 * does not have to be fetched again in _isr_demux.
+	 * Save LP_START/LP_COUNT/LP_END because called handler might use.
+	 * Save these in callee saved registers to avoid using memory.
+	 * These will be saved by the compiler if it needs to spill them.
 	 */
-
-	/* save LP_START/LP_COUNT/LP_END variables */
-	mov_s r1, _nanokernel
-
-	st lp_count, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_count_OFFSET]
-
-	lr r2, [_ARC_V2_LP_START]
-	st r2, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_start_OFFSET]
-	lr r2, [_ARC_V2_LP_END]
-	st r2, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_end_OFFSET]
+	mov r23,lp_count
+	lr r24, [_ARC_V2_LP_START]
+	lr r25, [_ARC_V2_LP_END]
 #endif
 
 	j @_isr_demux
@@ -97,30 +97,19 @@ SECTION_FUNC(TEXT, _firq_enter)
 
 SECTION_FUNC(TEXT, _firq_exit)
 
+#ifndef CONFIG_FIRQ_NO_LPCC
+	/* restore lp_count, lp_start, lp_end from r23-r25 */
+	mov lp_count,r23
+	sr r24, [_ARC_V2_LP_START]
+	sr r25, [_ARC_V2_LP_END]
+#endif
+
 	mov_s r1, _nanokernel
 	ld_s r2, [r1, __tNANO_current_OFFSET]
 
-#ifndef CONFIG_FIRQ_NO_LPCC
-
-	/* assumption: r1 contains _nanokernel, r2 contains the current thread */
-
-	/* restore LP_START/LP_COUNT/LP_END variables */
-
-	/* cannot load lp_count from memory */
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_count_OFFSET]
-	mov lp_count, r3
-
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_start_OFFSET]
-	sr r3, [_ARC_V2_LP_START]
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_end_OFFSET]
-	sr r3, [_ARC_V2_LP_END]
-
-	/* exiting here: r1/r2 unchanged, r0/r3 destroyed */
-#endif
-
 #if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
-	/* check if we're a nested interrupt: if so, let the interrupted interrupt
-	 * handle the reschedule */
+	/* check if we're a nested interrupt: if so, let the interrupted
+	 * interrupt handle the reschedule */
 
 	lr r3, [_ARC_V2_AUX_IRQ_ACT]
 
@@ -129,7 +118,7 @@ SECTION_FUNC(TEXT, _firq_exit)
 	 * means that another bit is set so an interrupt was interrupted.
 	 */
 
-	breq.nd r3, 1, _check_if_current_is_the_task
+	breq r3, 1, _check_if_current_is_the_task
 
 	rtie
 
@@ -138,15 +127,15 @@ SECTION_FUNC(TEXT, _firq_exit)
 .balign 4
 _check_if_current_is_the_task:
 
-	ld r0, [r2, __tTCS_flags_OFFSET]
+	ld_s r0, [r2, __tTCS_flags_OFFSET]
 	and.f r0, r0, PREEMPTIBLE
-	bnz.nd _check_if_a_fiber_is_ready
+	bnz _check_if_a_fiber_is_ready
 	rtie
 
 .balign 4
 _check_if_a_fiber_is_ready:
-	ld r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
-	brne.nd r0, 0, _firq_reschedule
+	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
+	brne r0, 0, _firq_reschedule
 	rtie
 
 .balign 4
@@ -177,23 +166,23 @@ _firq_reschedule:
 	st ilink, [sp, __tISF_pc_OFFSET] /* ilink into pc */
 
 	mov_s r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 
 	_save_callee_saved_regs
 
 	st _CAUSE_FIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	ld r2, [r1, __tNANO_fiber_OFFSET]
+	ld_s r2, [r1, __tNANO_fiber_OFFSET]
 
-	st r2, [r1, __tNANO_current_OFFSET]
-	ld r3, [r2, __tTCS_link_OFFSET]
-	st r3, [r1, __tNANO_fiber_OFFSET]
+	st_s r2, [r1, __tNANO_current_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
+	st_s r3, [r1, __tNANO_fiber_OFFSET]
 
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
 	add r3, r2, __tTCS_NOFLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/*
@@ -202,11 +191,11 @@ _firq_reschedule:
 	 */
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	breq.nd r3, _CAUSE_RIRQ, _firq_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _firq_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _firq_return_from_firq
+	breq r3, _CAUSE_FIRQ, _firq_return_from_firq
 	nop
 
 	/* fall through */
@@ -214,7 +203,7 @@ _firq_reschedule:
 .balign 4
 _firq_return_from_coop:
 
-	ld r3, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r3, [r2, __tTCS_intlock_key_OFFSET]
 	st  0, [r2, __tTCS_intlock_key_OFFSET]
 
 	/* pc into ilink */
@@ -225,15 +214,15 @@ _firq_return_from_coop:
 	/*
 	 * There are only two interrupt lock states: locked and unlocked. When
 	 * entering _Swap(), they are always locked, so the IE bit is unset in
-	 * status32. If the incoming thread had them locked recursively, it means
-	 * that the IE bit should stay unset. The only time the bit has to change
-	 * is if they were not locked recursively.
+	 * status32. If the incoming thread had them locked recursively, it
+	 * means that the IE bit should stay unset. The only time the bit
+	 * has to change is if they were not locked recursively.
 	 */
 	and.f r3, r3, (1 << 4)
 	or.nz r0, r0, _ARC_V2_STATUS32_IE
 	sr r0, [_ARC_V2_STATUS32_P0]
 
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, __tTCS_return_value_OFFSET]
 	rtie
 
 .balign 4
@@ -279,4 +268,4 @@ SECTION_FUNC(TEXT, _firq_stack_setup)
 	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
 	kflag r0
 
-	j_s.nd [blink]
+	j_s [blink]

arch/arc/core/fault_s.S

@@ -49,6 +49,15 @@ GDATA(_firq_stack)
 SECTION_VAR(BSS, saved_stack_pointer)
 	.word 0
 
+#if CONFIG_NUM_IRQ_PRIO_LEVELS == 1
+#error "NUM_IRQ_PRIO_LEVELS==1 is not supported."
+/* The code below sets bit 1 in AUX_IRQ_ACT and thus requires
+ * priority 0 and 1 at a minimum. Supporting only 1 priority
+ * requires a change to this file but also changes to make
+ * FIRQ optional.
+ */
+#endif
+
 /*
  * @brief Fault handler installed in the fault and reserved vectors
  */
@@ -78,6 +87,15 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 	 * a diagnostic message and halt.
 	 */
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	push_s r2
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+	pop_s r2
+#endif
+
 	st sp, [saved_stack_pointer]
 	mov_s sp, _firq_stack
 	add sp, sp, CONFIG_FIRQ_STACK_SIZE
@@ -85,6 +103,11 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, __tISF_status32_OFFSET]
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, __tISF_pc_OFFSET] /* eret into pc */
+
 	jl _Fault
 
 	/* if _Fault returns, restore the registers */
@@ -102,24 +125,102 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	 * Before invoking exception handler, the kernel switches to an exception
 	 * stack, which is really the FIRQ stack, to save the faulting thread's
 	 * registers. It can use the FIRQ stack because it knows it is unused
-	 * since it is save to assume that if an exception has happened in FIRQ
+	 * since it is safe to assume that if an exception has happened in FIRQ
 	 * handler, the problem is fatal and all the kernel can do is just print
 	 * a diagnostic message and halt.
 	 */
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	push_s r2
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+	pop_s r2
+#endif
+
+#ifndef CONFIG_MICROKERNEL
 	st sp, [saved_stack_pointer]
 	mov_s sp, _firq_stack
 	add sp, sp, CONFIG_FIRQ_STACK_SIZE
+#endif
 
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, __tISF_status32_OFFSET]
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, __tISF_pc_OFFSET] /* eret into pc */
+
 	jl _irq_do_offload
 
+#ifdef CONFIG_MICROKERNEL
+	mov_s r1, _nanokernel
+	ld_s r2, [r1, __tNANO_current_OFFSET]
+#if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
+	/* check if we're a nested interrupt: if so, let the
+	 * interrupted interrupt handle the reschedule
+	 */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
+	 * AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is 0, it
+	 * means trap was taken from outside an interrupt handler.
+	 * But if it was inside, let that handler do the swap.
+	 */
+	breq r3, 0, _trap_check_for_swap
+_trap_return:
+	_pop_irq_stack_frame
+	rtie
+#endif
+
+.balign 4
+_trap_check_for_swap:
+	ld_s r0, [r2, __tTCS_flags_OFFSET]
+	and.f r0, r0, PREEMPTIBLE
+	bnz _e_check_if_a_fiber_is_ready
+	b _trap_return
+
+.balign 4
+_e_check_if_a_fiber_is_ready:
+	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
+	brne r0, 0, _trap_reschedule
+	b _trap_return
+
+.balign 4
+_trap_reschedule:
+
+	_save_callee_saved_regs
+
+	st _CAUSE_RIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
+	/* note: Ok to use _CAUSE_RIRQ since everything is saved */
+
+	ld_s r2, [r1, __tNANO_fiber_OFFSET]
+
+	st_s r2, [r1, __tNANO_current_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
+	st_s r3, [r1, __tNANO_fiber_OFFSET]
+
+	/* clear AE bit to forget this was an exception */
+	lr r3, [_ARC_V2_STATUS32]
+	and r3,r3,(~_ARC_V2_STATUS32_AE)
+	kflag r3
+ 	/* pretend priority 1 int happened to use common handler */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	or r3,r3,2
+	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+
+	/* Assumption: r2 has current thread */
+	b _rirq_common_interrupt_swap
+#else
+	/* Nanokernel-only just returns from exception */
+
 	/* if _Fault returns, restore the registers */
 	_pop_irq_stack_frame
 
 	/* now restore the stack */
 	ld sp,[saved_stack_pointer]
 	rtie
+#endif
+
 #endif /* CONFIG_IRQ_OFFLOAD */

arch/arc/core/isr_wrapper.S

@@ -209,8 +209,23 @@ SECTION_FUNC(TEXT, _isr_enter)
 	mov.nz r3, _rirq_exit
 	mov.nz r2, _rirq_enter
 
-	j_s.nd [r2]
+	j_s [r2]
 
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+GTEXT(_sys_k_event_logger_exit_sleep)
+
+.macro log_sleep_k_event
+	clri r0 /* do not interrupt event logger operations */
+	push_s r0
+	push_s blink
+	jl _sys_k_event_logger_exit_sleep
+	pop_s blink
+	pop_s r0
+	seti r0
+.endm
+#else
+	#define log_sleep_k_event
+#endif
 #if defined(CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT)
 GTEXT(_sys_k_event_logger_interrupt)
 
@@ -249,6 +264,7 @@ SECTION_FUNC(TEXT, _isr_demux)
 	/* r0 is available to be stomped here, and exit_tickless_idle uses it */
 	exit_tickless_idle
 	log_interrupt_k_event
+	log_sleep_k_event
 
 	lr r0, [_ARC_V2_ICAUSE]
 	sub r0, r0, 16
@@ -256,11 +272,11 @@ SECTION_FUNC(TEXT, _isr_demux)
 	mov r1, _sw_isr_table
 	add3 r0, r1, r0   /* table entries are 8-bytes wide */
 
-	ld r1, [r0, 4] /* ISR into r1 */
+	ld_s r1, [r0, 4] /* ISR into r1 */
 	jl_s.d [r1]
 	ld_s r0, [r0] /* delay slot: ISR parameter into r0  */
 
 	/* back from ISR, jump to exit stub */
 	pop_s r3
-	j_s.nd [r3]
+	j_s [r3]
 	nop

arch/arc/core/offsets/offsets.c

@@ -39,7 +39,6 @@
 
 /* ARCv2-specific tNANO structure member offsets */
 GEN_OFFSET_SYM(tNANO, rirq_sp);
-GEN_OFFSET_SYM(tNANO, firq_regs);
 #ifdef CONFIG_SYS_POWER_MANAGEMENT
 GEN_OFFSET_SYM(tNANO, idle);
 #endif
@@ -102,12 +101,6 @@ GEN_OFFSET_SYM(tCalleeSaved, fp);
 GEN_OFFSET_SYM(tCalleeSaved, r30);
 GEN_ABSOLUTE_SYM(__tCalleeSaved_SIZEOF, sizeof(tCalleeSaved));
 
-/* ARCv2-specific registers-saved-in-FIRQ structure member offsets */
-GEN_OFFSET_SYM(tFirqRegs, lp_count);
-GEN_OFFSET_SYM(tFirqRegs, lp_start);
-GEN_OFFSET_SYM(tFirqRegs, lp_end);
-GEN_ABSOLUTE_SYM(__tFirqRegs_SIZEOF, sizeof(tFirqRegs));
-
 /* size of the struct tcs structure sans save area for floating point regs */
 GEN_ABSOLUTE_SYM(__tTCS_NOFLOAT_SIZEOF, sizeof(tTCS));
 

arch/arc/core/prep_c.c

@@ -29,6 +29,7 @@
 #include <stdint.h>
 #include <toolchain.h>
 #include <linker-defs.h>
+#include <arch/arc/v2/aux_regs.h>
 
 /**
  *
@@ -75,6 +76,82 @@ static void dataCopy(void)
 }
 #endif
 
+
+/**
+ *
+ * @brief Disable the i-cache if present
+ *
+ * For those ARC CPUs that have a i-cache present,
+ * invalidate the i-cache and then disable it.
+ *
+ * @return N/A
+ */
+
+static void disable_icache(void)
+{
+	unsigned int val;
+
+	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
+	val &= 0xff; /* version field */
+	if (val == 0) {
+		return; /* skip if i-cache is not present */
+	}
+	_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0);
+	__asm__ __volatile__ ("nop");
+	_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1);
+}
+
+/**
+ *
+ * @brief Invalidate the data cache if present
+ *
+ * For those ARC CPUs that have a data cache present,
+ * invalidate the data cache.
+ *
+ * @return N/A
+ */
+
+static void invalidate_dcache(void)
+{
+	unsigned int val;
+
+	val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+	val &= 0xff; /* version field */
+	if (val == 0) {
+		return; /* skip if d-cache is not present */
+	}
+	_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
+}
+
+
+/**
+ *
+ * @brief Adjust the vector table base
+ *
+ * Set the vector table base if the value found in the
+ * _ARC_V2_IRQ_VECT_BASE auxiliary register is different from the
+ * _VectorTable known by software. It is important to do this very early
+ * so that exception vectors can be handled.
+ *
+ * @return N/A
+ */
+
+static void adjust_vector_table_base(void)
+{
+	extern struct vector_table _VectorTable;
+	unsigned int vbr;
+	/* if the compiled-in vector table is different
+	 * from the base address known by the ARC CPU,
+	 * set the vector base to the compiled-in address.
+	 */
+	vbr = _arc_v2_aux_reg_read(_ARC_V2_IRQ_VECT_BASE);
+	vbr &= 0xfffffc00;
+	if (vbr != (unsigned int)&_VectorTable) {
+		_arc_v2_aux_reg_write(_ARC_V2_IRQ_VECT_BASE,
+					(unsigned int)&_VectorTable);
+	}
+}
+
 extern FUNC_NORETURN void _Cstart(void);
 /**
  *
@@ -87,6 +164,9 @@ extern FUNC_NORETURN void _Cstart(void);
 
 void _PrepC(void)
 {
+	disable_icache();
+	invalidate_dcache();
+	adjust_vector_table_base();
 	bssZero();
 	dataCopy();
 	_Cstart();

arch/arc/core/regular_irq.S

@@ -34,6 +34,16 @@
 
 GTEXT(_rirq_enter)
 GTEXT(_rirq_exit)
+GTEXT(_rirq_common_interrupt_swap)
+
+#if CONFIG_NUM_IRQ_PRIO_LEVELS > 2
+#error "NUM_IRQ_PRIO_LEVELS>2 is not supported."
+/*
+ * Nesting of Regularing interrupts is not yet supported.
+ * If your SOC supports more than 2, set this value to 2.
+ */
+#endif
+
 
 /**
  *
@@ -57,7 +67,7 @@ SECTION_FUNC(TEXT, _rirq_enter)
 	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
 	kflag r2
 #endif
-	ld r2, [r1, __tNANO_current_OFFSET]
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 #if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS == 1
 	st sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 	ld sp, [r1, __tNANO_rirq_sp_OFFSET]
@@ -77,7 +87,7 @@ SECTION_FUNC(TEXT, _rirq_enter)
 SECTION_FUNC(TEXT, _rirq_exit)
 
 	mov r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 
 #if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS > 1
 	/* check if we're a nested interrupt: if so, let the interrupted interrupt
@@ -95,7 +105,7 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	 */
 
 	cmp r0, r3
-	brgt.nd _rirq_return_from_rirq
+	brgt _rirq_return_from_rirq
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 #endif
 
@@ -108,12 +118,12 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	 * b) needs to load it to restore the interrupted context.
 	 */
 
-	ld r0, [r2, __tTCS_flags_OFFSET]
+	ld_s r0, [r2, __tTCS_flags_OFFSET]
 	and.f r0, r0, PREEMPTIBLE
 	bz.d _rirq_no_reschedule
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 
-	ld r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
+	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
 	cmp r0, 0
 	bz.d _rirq_no_reschedule
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
@@ -128,15 +138,18 @@ _rirq_reschedule:
 
 	/* incoming fiber is in r0: it becomes the new 'current' */
 	mov r2, r0
-	st r2, [r1, __tNANO_current_OFFSET]
-	ld r3, [r2, __tTCS_link_OFFSET]
-	st r3, [r1, __tNANO_fiber_OFFSET]
+	st_s r2, [r1, __tNANO_current_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
+	st_s r3, [r1, __tNANO_fiber_OFFSET]
+
+_rirq_common_interrupt_swap:
+	/* r2 contains pointer to new thread */
 
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
 	add r3, r2, __tTCS_NOFLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/*
@@ -145,11 +158,11 @@ _rirq_reschedule:
 	 */
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	breq.nd r3, _CAUSE_RIRQ, _rirq_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _rirq_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _rirq_return_from_firq
+	breq r3, _CAUSE_FIRQ, _rirq_return_from_firq
 	nop
 
 	/* fall through */
@@ -160,12 +173,12 @@ _rirq_return_from_coop:
 	/* status32 and pc (blink) are already on the stack in the right order */
 
 	/* update status32.ie (explanation in firq_exit:_firq_return_from_coop) */
-	ld r0, [sp, 4]
-	ld r3, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r0, [sp, 4]
+	ld_s r3, [r2, __tTCS_intlock_key_OFFSET]
 	st  0, [r2, __tTCS_intlock_key_OFFSET]
 	cmp r3, 0
 	or.ne r0, r0, _ARC_V2_STATUS32_IE
-	st r0, [sp, 4]
+	st_s r0, [sp, 4]
 
 	/* carve fake stack */
 
@@ -173,7 +186,7 @@ _rirq_return_from_coop:
 	                                  * b) a real value will be pushed in r0 */
 
 	/* push return value on stack */
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, __tTCS_return_value_OFFSET]
 	push_s r0
 
 	/*
@@ -182,7 +195,7 @@ _rirq_return_from_coop:
 	 * IRQ prologue. r13 thus has to be set to its correct value in the IRQ
 	 * stack frame.
 	 */
-	st r13, [sp, __tISF_r13_OFFSET]
+	st_s r13, [sp, __tISF_r13_OFFSET]
 
 	/* stack now has the IRQ stack frame layout, pointing to r0 */
 

arch/arc/core/reset.S

@@ -28,9 +28,15 @@
 #include <sections.h>
 #include <arch/cpu.h>
 
-#define _RAM_END (CONFIG_SRAM_BASE_ADDRESS + CONFIG_SRAM_SIZE * 1024)
+#ifdef CONFIG_HARVARD
+#define _TOP_OF_MEMORY (CONFIG_DCCM_BASE_ADDRESS + CONFIG_DCCM_SIZE * 1024)
+/* harvard places the initial stack in the dccm memory */
+#else
+#define _TOP_OF_MEMORY (CONFIG_SRAM_BASE_ADDRESS + CONFIG_SRAM_SIZE * 1024)
+#endif
 
 GTEXT(__reset)
+GTEXT(__start)
 
 /**
  *
@@ -47,11 +53,12 @@ GTEXT(__reset)
  */
 
 SECTION_FUNC(TEXT,__reset)
+SECTION_FUNC(TEXT,__start)
 
 	/* lock interrupts: will get unlocked when switch to main task */
 	clri
 
-	/* setup a stack at the end of the RAM */
-	mov sp, _RAM_END
+	/* setup a stack at the end of MEMORY */
+	mov sp, _TOP_OF_MEMORY
 
 	j @_PrepC

arch/arc/core/swap.S

@@ -74,10 +74,10 @@ SECTION_FUNC(TEXT, _Swap)
 	/* interrupts are locked, interrupt key is in r0 */
 
 	mov r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 
 	/* save intlock key */
-	st r0, [r2, __tTCS_intlock_key_OFFSET]
+	st_s r0, [r2, __tTCS_intlock_key_OFFSET]
 	st _CAUSE_COOP, [r2, __tTCS_relinquish_cause_OFFSET]
 
 	/*
@@ -95,20 +95,20 @@ SECTION_FUNC(TEXT, _Swap)
 
 	_save_callee_saved_regs
 
-	ld r2, [r1, __tNANO_fiber_OFFSET]
-	breq.nd r2, 0, _swap_to_the_task
+	ld_s r2, [r1, __tNANO_fiber_OFFSET]
+	breq r2, 0, _swap_to_the_task
 
 .balign 4
 _swap_to_a_fiber:
 
-	ld r3, [r2, __tTCS_link_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
 	b.d _finish_swapping_to_thread    /* always execute delay slot */
-	st r3, [r1, __tNANO_fiber_OFFSET] /* delay slot */
+	st_s r3, [r1, __tNANO_fiber_OFFSET] /* delay slot */
 
 .balign 4
 _swap_to_the_task:
 
-	ld r2, [r1, __tNANO_task_OFFSET]
+	ld_s r2, [r1, __tNANO_task_OFFSET]
 
 	/* fall through */
 
@@ -120,26 +120,26 @@ _finish_swapping_to_thread:
 #if 0
 /* don't save flags in tNANO: slower, error-prone, and might not even give
  * a speed boost where it's supposed to */
-	ld r3, [r2, __tTCS_flags_OFFSET]
-	st r3, [r1, __tNANO_flags_OFFSET]
+	ld_s r3, [r2, __tTCS_flags_OFFSET]
+	st_s r3, [r1, __tNANO_flags_OFFSET]
 #endif
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
 	add r3, r2, __tTCS_NOFLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/* XXX - can be moved to delay slot of _CAUSE_RIRQ ? */
-	st r2, [r1, __tNANO_current_OFFSET]
+	st_s r2, [r1, __tNANO_current_OFFSET]
 
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	breq.nd r3, _CAUSE_RIRQ, _swap_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _swap_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _swap_return_from_firq
+	breq r3, _CAUSE_FIRQ, _swap_return_from_firq
 	nop
 
 	/* fall through to _swap_return_from_coop */
@@ -147,19 +147,12 @@ _finish_swapping_to_thread:
 .balign 4
 _swap_return_from_coop:
 
-	ld r1, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r1, [r2, __tTCS_intlock_key_OFFSET]
 	st  0, [r2, __tTCS_intlock_key_OFFSET]
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, __tTCS_return_value_OFFSET]
 
-	/*
-	 * Adjust the stack here in case we go to _return_from_exc: this allows
-	 * keeping handling both coop and irq cases in _return_from_exc without
-	 * adding extra logic.
-	 */
-	add_s sp, sp, 8
 	lr ilink, [_ARC_V2_STATUS32]
 	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
-	sub_s sp, sp, 8
 
 	pop_s blink /* pc into blink */
 	pop_s r3    /* status32 into r3 */
@@ -173,39 +166,32 @@ _swap_return_from_coop:
 _swap_return_from_rirq:
 _swap_return_from_firq:
 
-	_pop_irq_stack_frame
-
-	lr ilink, [_ARC_V2_STATUS32]
-	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
-
-	ld ilink, [sp, -4] /* status32 into ilink */
-#ifdef CONFIG_ARC_STACK_CHECKING
-	and ilink, ilink, 0x7fffbffe // keep SC off till we stop using under SP
-#else
-	and ilink, ilink, 0x7ffffffe // keep interrupts disabled until seti
-#endif
-	kflag ilink
-
-	ld ilink, [sp, -8] /* pc into ilink */
-
-#ifdef CONFIG_ARC_STACK_CHECKING
-	/* Enable stack checking now it is safe */
-	push_s r3
 	lr r3, [_ARC_V2_STATUS32]
-	bset r3, r3, _ARC_V2_STATUS32_SC_BIT
-	flag r3
-	pop_s r3
-#endif
-	j.d [ilink]
-	seti (_ARC_V2_DEF_IRQ_LEVEL | (1 << 4))
+	bbit1 r3, _ARC_V2_STATUS32_AE_BIT, _return_from_exc_irq
+
+	/* pretend interrupt happened to use rtie instruction */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	brne r3,0,_swap_already_in_irq
+
+	or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1)) /* use lowest */
+	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+
+_swap_already_in_irq:
+	rtie
 
 .balign 4
+_return_from_exc_irq:
+	_pop_irq_stack_frame
+	sub_s sp, sp, 8
+
 _return_from_exc:
+
 	/* put the return address to eret */
-	ld ilink, [sp, -8] /* pc into ilink */
+	ld ilink, [sp] /* pc into ilink */
 	sr ilink, [_ARC_V2_ERET]
 
 	/* put status32 into estatus */
-	ld ilink, [sp, -4] /* status32 into ilink */
+	ld ilink, [sp, 4] /* status32 into ilink */
 	sr ilink, [_ARC_V2_ERSTATUS]
+	add_s sp, sp, 8
 	rtie

arch/arc/core/swap_macros.h

@@ -36,9 +36,9 @@ extern "C" {
 	sub_s sp, sp, __tCalleeSaved_SIZEOF
 
 	/* save regs on stack */
-	st r13, [sp, __tCalleeSaved_r13_OFFSET]
-	st r14, [sp, __tCalleeSaved_r14_OFFSET]
-	st r15, [sp, __tCalleeSaved_r15_OFFSET]
+	st_s r13, [sp, __tCalleeSaved_r13_OFFSET]
+	st_s r14, [sp, __tCalleeSaved_r14_OFFSET]
+	st_s r15, [sp, __tCalleeSaved_r15_OFFSET]
 	st r16, [sp, __tCalleeSaved_r16_OFFSET]
 	st r17, [sp, __tCalleeSaved_r17_OFFSET]
 	st r18, [sp, __tCalleeSaved_r18_OFFSET]
@@ -62,9 +62,9 @@ extern "C" {
 	/* restore stack pointer from struct tcs */
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 
-	ld r13, [sp, __tCalleeSaved_r13_OFFSET]
-	ld r14, [sp, __tCalleeSaved_r14_OFFSET]
-	ld r15, [sp, __tCalleeSaved_r15_OFFSET]
+	ld_s r13, [sp, __tCalleeSaved_r13_OFFSET]
+	ld_s r14, [sp, __tCalleeSaved_r14_OFFSET]
+	ld_s r15, [sp, __tCalleeSaved_r15_OFFSET]
 	ld r16, [sp, __tCalleeSaved_r16_OFFSET]
 	ld r17, [sp, __tCalleeSaved_r17_OFFSET]
 	ld r18, [sp, __tCalleeSaved_r18_OFFSET]
@@ -112,9 +112,9 @@ extern "C" {
 
 	mov r0, lp_count
 	st_s r0, [sp, __tISF_lp_count_OFFSET]
-	lr r0, [_ARC_V2_LP_START]
-	st_s r0, [sp, __tISF_lp_start_OFFSET]
+	lr r1, [_ARC_V2_LP_START]
 	lr r0, [_ARC_V2_LP_END]
+	st_s r1, [sp, __tISF_lp_start_OFFSET]
 	st_s r0, [sp, __tISF_lp_end_OFFSET]
 
 .endm
@@ -129,9 +129,9 @@ extern "C" {
 
 	ld_s r0, [sp, __tISF_lp_count_OFFSET]
 	mov lp_count, r0
-	ld_s r0, [sp, __tISF_lp_start_OFFSET]
-	sr r0, [_ARC_V2_LP_START]
+	ld_s r1, [sp, __tISF_lp_start_OFFSET]
 	ld_s r0, [sp, __tISF_lp_end_OFFSET]
+	sr r1, [_ARC_V2_LP_START]
 	sr r0, [_ARC_V2_LP_END]
 
 	ld_s r13, [sp, __tISF_r13_OFFSET]

arch/arc/core/sys_fatal_error_handler.c

@@ -73,7 +73,7 @@ void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF * pEsf)
 	ARG_UNUSED(reason);
 	ARG_UNUSED(pEsf);
 
-	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential(NULL)) {
+	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential()) {
 		PRINTK("Fatal fault in %s ! Spinning...\n",
 		       NANO_CTX_ISR == curCtx
 			       ? "ISR"

arch/arc/core/thread.c

@@ -101,7 +101,8 @@ static ALWAYS_INLINE void thread_monitor_init(struct tcs *tcs)
  *
  * @return N/A
  */
-void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
+void _new_thread(char *pStackMem, unsigned stackSize,
+		 void *uk_task_ptr, _thread_entry_t pEntry,
 		 void *parameter1, void *parameter2, void *parameter3,
 		 int priority, unsigned options)
 {
@@ -154,6 +155,13 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 	 */
 	tcs->entry = (struct __thread_entry *)(pInitCtx);
 #endif
+
+#ifdef CONFIG_MICROKERNEL
+	tcs->uk_task_ptr = uk_task_ptr;
+#else
+	ARG_UNUSED(uk_task_ptr);
+#endif
+
 	/*
 	 * intlock_key is constructed based on ARCv2 ISA Programmer's
 	 * Reference Manual CLRI instruction description:

arch/arc/core/vector_table.c

@@ -75,4 +75,3 @@ struct vector_table _VectorTable _GENERIC_SECTION(.exc_vector_table) = {
 	0
 };
 
-extern struct vector_table __start _ALIAS_OF(_VectorTable);

arch/arc/include/nano_private.h

@@ -130,14 +130,6 @@ struct callee_saved {
 };
 typedef struct callee_saved tCalleeSaved;
 
-/* registers saved by software when taking a FIRQ */
-struct firq_regs {
-	uint32_t lp_count;
-	uint32_t lp_start;
-	uint32_t lp_end;
-};
-typedef struct firq_regs tFirqRegs;
-
 #endif /* _ASMLANGUAGE */
 
 /* Bitmask definitions for the struct tcs->flags bit field */
@@ -197,6 +189,9 @@ struct tcs {
 #ifdef CONFIG_ARC_STACK_CHECKING
 	uint32_t stack_top;
 #endif
+#ifdef CONFIG_MICROKERNEL
+	void *uk_task_ptr;
+#endif
 };
 
 struct s_NANO {
@@ -223,7 +218,6 @@ struct s_NANO {
 	 * there is no need to track it in _nanokernel.
 	 */
 
-	struct firq_regs firq_regs;
 #if defined(CONFIG_NANO_TIMEOUTS) || defined(CONFIG_NANO_TIMERS)
 	sys_dlist_t timeout_q;
 	int32_t task_timeout;

arch/arc/include/start_task_arch.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 Wind River Systems, Inc.
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -14,27 +14,35 @@
  * limitations under the License.
  */
 
-/** @file
+/**
+ * @file
+ * @brief ARC nanokernel declarations to start a task
  *
- * @brief Per-thread errno accessor function
+ * ARC-specific parts of start_task().
  *
- * Allow accessing the errno for the current thread without involving the
- * context switching.
+ * Currently empty, only here for abstraction.
  */
 
-#define _ASMLANGUAGE
+#ifndef _START_TASK_ARCH__H_
+#define _START_TASK_ARCH__H_
 
+#include <toolchain.h>
+#include <sections.h>
+
+#include <micro_private.h>
 #include <nano_private.h>
-#include <offsets.h>	/* nanokernel structure offset definitions */
+#include <microkernel/task.h>
 
-_ASM_FILE_PROLOGUE
+#ifdef __cplusplus
+extern "C" {
+#endif
 
-GTEXT(_nanokernel)
-GTEXT(_get_errno)
+#define _START_TASK_ARCH(task, opt_ptr) \
+	do {/* nothing */              \
+	} while ((0))
 
-SECTION_FUNC(TEXT, _get_errno)
+#ifdef __cplusplus
+}
+#endif
 
-	ldr r0, =_nanokernel
-	ldr r0, [r0, #__tNANO_current_OFFSET]
-	adds.n r0, #__tTCS_errno_var_OFFSET
-	bx lr
+#endif /* _START_TASK_ARCH__H_ */

arch/arc/include/v2/cache.h

@@ -49,7 +49,14 @@ static ALWAYS_INLINE void _icache_setup(void)
 		CACHE_DIRECT | /* direct mapping (one-way assoc.) */
 		CACHE_ENABLE   /* i-cache enabled */
 	);
-	_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
+	uint32_t val;
+
+	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
+	val &= 0xff;
+	if (val != 0) {
+		/* configure i-cache if present */
+		_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
+	}
 }
 
 #endif /* _ASMLANGUAGE */

arch/arc/soc/em11d/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/arc/soc/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o

arch/arc/soc/em11d/Kconfig.defconfig

@@ -0,0 +1,260 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_EM11D
+
+config SOC
+	default em11d
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	# TODO: But regular irq nesting is not implemented --
+	# so this must be 2 for now.
+	default 2
+
+config NUM_REGULAR_IRQ_PRIO_LEVELS
+	# This processor supports 3 Regular Interrupt priority level (1-3).
+	# TODO: But regular irq nesting is not implemented -- so use 1.
+	default 1
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 36
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	def_bool n
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config FLASH_SIZE
+	default 0
+	# em11d has no FLASH so size is 0.
+
+config SRAM_BASE_ADDRESS
+	default 0x10000000 if NSIM
+	default 0x10000000
+
+config SRAM_SIZE
+	default 131072 if NSIM
+	default 131072
+
+config ICCM_BASE_ADDRESS
+	default 0x00000000
+
+config ICCM_SIZE
+	default 64
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 64
+
+if GPIO
+
+config GPIO_DW
+	def_bool y
+
+if GPIO_DW
+
+config GPIO_DW_0
+	def_bool y
+
+if GPIO_DW_0
+
+config GPIO_DW_0_NAME
+	default "GPIO_PORTA"
+
+config GPIO_DW_0_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_0
+
+config GPIO_DW_1
+	def_bool y
+
+if GPIO_DW_1
+
+config GPIO_DW_1_NAME
+	default "GPIO_PORTB"
+
+config GPIO_DW_1_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_1
+
+config GPIO_DW_2
+	def_bool y
+
+if GPIO_DW_2
+
+config GPIO_DW_2_IRQ_PRI
+	default 1
+
+config GPIO_DW_2_NAME
+	default "GPIO_PORTC"
+
+endif # GPIO_DW_2
+
+config GPIO_DW_3
+	def_bool y
+
+if GPIO_DW_3
+
+config GPIO_DW_3_IRQ_PRI
+	default 1
+
+config GPIO_DW_3_NAME
+	default "GPIO_PORTD"
+
+endif # GPIO_DW_3
+
+endif # GPIO_DW
+
+endif # GPIO
+
+if I2C
+
+config I2C_CLOCK_SPEED
+	default 100
+
+config I2C_DW
+	def_bool y
+
+if I2C_DW
+
+config I2C_0
+	def_bool y
+
+if I2C_0
+
+config I2C_0_NAME
+	default "I2C_0"
+config I2C_0_DEFAULT_CFG
+	default 0x3
+config I2C_0_IRQ_PRI
+	default 1
+
+endif # I2C_0
+
+config I2C_1
+	def_bool y
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+config I2C_1_DEFAULT_CFG
+	default 0x3
+config I2C_1_IRQ_PRI
+	default 1
+
+endif # I2C_1
+
+endif # I2C_DW
+
+endif # I2C
+
+if UART_NS16550
+
+config UART_NS16550_PORT_0
+	def_bool n
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_NAME
+	default "UART_0"
+config UART_NS16550_PORT_0_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_0_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_NAME
+	default "UART_1"
+config UART_NS16550_PORT_1_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_1_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_1
+
+endif # UART_NS16550
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_DW
+	def_bool y
+
+if SPI_DW
+
+config SPI_DW_CLOCK_GATE
+	def_bool n
+
+config SPI_DW_FIFO_DEPTH
+	default 32
+
+config SPI_DW_ARC_AUX_REGS
+	def_bool n
+
+config SPI_0
+	def_bool y
+
+if SPI_0
+
+config SPI_0_IRQ_PRI
+	default 0
+
+endif # SPI_0
+
+config SPI_1
+	def_bool y
+
+if SPI_1
+
+config SPI_1_IRQ_PRI
+	default 0
+
+endif # SPI_1
+
+endif # SPI_DW
+
+endif # SPI
+
+endif #SOC_EM11D

arch/arc/soc/em11d/Kconfig.soc

@@ -0,0 +1,3 @@
+
+config SOC_EM11D
+	bool "Synopsys ARC EM11D"

arch/arc/soc/em11d/Makefile

@@ -0,0 +1,2 @@
+soc-cflags = $(call cc-option,-mARCv2EM) \
+                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)

arch/arc/soc/em11d/linker.ld

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit v2.2 EM11D platform.
+ */
+
+/*
+ * DRAM base address and size
+ *
+ * DRAM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
+/* TODO: Using SRAM config for now, even though this is really DRAM. */
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/em11d/soc.c

@@ -0,0 +1,46 @@
+/* soc.c - system/hardware module for em_starterkit BSP */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the ARC EM Starter kit board.
+ */
+
+#include <nanokernel.h>
+#include "soc.h"
+#include <init.h>
+
+
+/**
+ *
+ * @brief perform basic hardware initialization
+ *
+ * Hardware initialized:
+ * - interrupt unit
+ *
+ * RETURNS: N/A
+ */
+static int em11d_arc_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	_arc_v2_irq_unit_init();
+	return 0;
+}
+
+SYS_INIT(em11d_arc_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em11d/soc.h

@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+
+
+/* IRQs */
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+/* ARCv2 timer 0 configuration settings for the system clock */
+#ifdef CONFIG_NANOKERNEL
+#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 20000000 /* 20MHz reference clock */
+#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
+#endif /* CONFIG_NANOKERNEL */
+
+#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
+#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+
+#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/* I2C */
+
+/* I2C_0 is on Pmod2 connector */
+#define I2C_DW_0_BASE_ADDR                      0xF0004000
+#define I2C_DW_0_IRQ                            23
+
+
+/* I2C_1 is on Pmod4 connector */
+#define I2C_DW_1_BASE_ADDR                      0xF0005000
+#define I2C_DW_1_IRQ                            24
+
+#define I2C_DW_IRQ_FLAGS			0
+
+/* GPIO */
+#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ                           22
+#define GPIO_DW_0_BITS                          32
+#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_2_BITS                          32
+#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_3_BITS                          12
+#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+
+/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
+/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
+/* undef CONFIG_GPIO_DW_CLOCK_GATE */
+/* undef CONFIG_SOC_QUARK_SE_SS */
+
+/* SPI */
+
+#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+
+#define SPI_DW_PORT_0_REGS   0xF0006000
+#define SPI_DW_PORT_1_REGS   0xF0007000
+
+#define SPI_DW_PORT_0_IRQ    25
+#define SPI_DW_PORT_1_IRQ    26
+
+/*
+ * SPI Chip Select Assignments on EM Starter Kit
+ *
+ *  CS0   Pmod6 - pin 1 - J6
+ *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
+ *  CS2   Pmod6 - pin 8 - J6
+ *  CS3   SDCard (onboard)
+ *  CS4   Internal SPI Slave - loopback
+ *  CS5   SPI-Flash (onboard)
+ */
+
+/*
+ * UART
+     UART0 vector 27 0xF0008000
+     UART1 vector 28 0xF0009000
+     UART2 vector 29 0xF000A000
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
+#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
+#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/em11d/soc_config.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/em9d/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/arc/soc/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o

arch/arc/soc/em9d/Kconfig.defconfig

@@ -0,0 +1,261 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_EM9D
+
+config SOC
+	default em9d
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	# TODO: But regular irq nesting is not implemented --
+	# so this must be 2 for now.
+	default 2
+
+config NUM_REGULAR_IRQ_PRIO_LEVELS
+	# This processor supports 3 Regular Interrupt priority level (1-3).
+	# TODO: But regular irq nesting is not implemented -- so use 1.
+	default 1
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 36
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	def_bool y
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config FLASH_SIZE
+	default 0
+	# em9d has no FLASH so size is 0.
+
+config SRAM_BASE_ADDRESS
+	default 0x00000000 if NSIM
+	default 0x00000000
+
+config SRAM_SIZE
+	default 0 if NSIM
+	default 0
+	# em9d has no SRAM so size is 0.
+
+config ICCM_BASE_ADDRESS
+	default 0x00000000
+
+config ICCM_SIZE
+	default 256
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 128
+
+if GPIO
+
+config GPIO_DW
+	def_bool y
+
+if GPIO_DW
+
+config GPIO_DW_0
+	def_bool y
+
+if GPIO_DW_0
+
+config GPIO_DW_0_NAME
+	default "GPIO_PORTA"
+
+config GPIO_DW_0_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_0
+
+config GPIO_DW_1
+	def_bool y
+
+if GPIO_DW_1
+
+config GPIO_DW_1_NAME
+	default "GPIO_PORTB"
+
+config GPIO_DW_1_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_1
+
+config GPIO_DW_2
+	def_bool y
+
+if GPIO_DW_2
+
+config GPIO_DW_2_IRQ_PRI
+	default 1
+
+config GPIO_DW_2_NAME
+	default "GPIO_PORTC"
+
+endif # GPIO_DW_2
+
+config GPIO_DW_3
+	def_bool y
+
+if GPIO_DW_3
+
+config GPIO_DW_3_IRQ_PRI
+	default 1
+
+config GPIO_DW_3_NAME
+	default "GPIO_PORTD"
+
+endif # GPIO_DW_3
+
+endif # GPIO_DW
+
+endif # GPIO
+
+if I2C
+
+config I2C_CLOCK_SPEED
+	default 100
+
+config I2C_DW
+	def_bool y
+
+if I2C_DW
+
+config I2C_0
+	def_bool y
+
+if I2C_0
+
+config I2C_0_NAME
+	default "I2C_0"
+config I2C_0_DEFAULT_CFG
+	default 0x3
+config I2C_0_IRQ_PRI
+	default 1
+
+endif # I2C_0
+
+config I2C_1
+	def_bool y
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+config I2C_1_DEFAULT_CFG
+	default 0x3
+config I2C_1_IRQ_PRI
+	default 1
+
+endif # I2C_1
+
+endif # I2C_DW
+
+endif # I2C
+
+if UART_NS16550
+
+config UART_NS16550_PORT_0
+	def_bool n
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_NAME
+	default "UART_0"
+config UART_NS16550_PORT_0_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_0_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_NAME
+	default "UART_1"
+config UART_NS16550_PORT_1_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_1_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_1
+
+endif # UART_NS16550
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_DW
+	def_bool y
+
+if SPI_DW
+
+config SPI_DW_CLOCK_GATE
+	def_bool n
+
+config SPI_DW_FIFO_DEPTH
+	default 32
+
+config SPI_DW_ARC_AUX_REGS
+	def_bool n
+
+config SPI_0
+	def_bool y
+
+if SPI_0
+
+config SPI_0_IRQ_PRI
+	default 0
+
+endif # SPI_0
+
+config SPI_1
+	def_bool y
+
+if SPI_1
+
+config SPI_1_IRQ_PRI
+	default 0
+
+endif # SPI_1
+
+endif # SPI_DW
+
+endif # SPI
+
+endif #SOC_EM9D

arch/arc/soc/em9d/Kconfig.soc

@@ -0,0 +1,3 @@
+
+config SOC_EM9D
+	bool "Synopsys ARC EM9D"

arch/arc/soc/em9d/Makefile

@@ -0,0 +1,2 @@
+soc-cflags = $(call cc-option,-mARCv2EM) \
+                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)

arch/arc/soc/em9d/linker.ld

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit v2.2 EM9D platform.
+ */
+
+/*
+ * ICCM base address and size
+ *
+ * ICCM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+
+#include <arch/arc/v2/linker_harvard.ld>
+

arch/arc/soc/em9d/soc.c

@@ -0,0 +1,46 @@
+/* soc.c - system/hardware module for em_starterkit BSP */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the ARC EM Starter kit board.
+ */
+
+#include <nanokernel.h>
+#include "soc.h"
+#include <init.h>
+
+
+/**
+ *
+ * @brief perform basic hardware initialization
+ *
+ * Hardware initialized:
+ * - interrupt unit
+ *
+ * RETURNS: N/A
+ */
+static int em9d_arc_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	_arc_v2_irq_unit_init();
+	return 0;
+}
+
+SYS_INIT(em9d_arc_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em9d/soc.h

@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+
+
+/* IRQs */
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+/* ARCv2 timer 0 configuration settings for the system clock */
+#ifdef CONFIG_NANOKERNEL
+#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 20000000 /* 20MHz reference clock */
+#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
+#endif /* CONFIG_NANOKERNEL */
+
+#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
+#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+
+#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/* I2C */
+
+/* I2C_0 is on Pmod2 connector */
+#define I2C_DW_0_BASE_ADDR                      0xF0004000
+#define I2C_DW_0_IRQ                            23
+
+
+/* I2C_1 is on Pmod4 connector */
+#define I2C_DW_1_BASE_ADDR                      0xF0005000
+#define I2C_DW_1_IRQ                            24
+
+#define I2C_DW_IRQ_FLAGS			0
+
+/* GPIO */
+#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ                           22
+#define GPIO_DW_0_BITS                          32
+#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_2_BITS                          32
+#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_3_BITS                          12
+#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+
+/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
+/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
+/* undef CONFIG_GPIO_DW_CLOCK_GATE */
+/* undef CONFIG_SOC_QUARK_SE_SS */
+
+/* SPI */
+
+#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+
+#define SPI_DW_PORT_0_REGS   0xF0006000
+#define SPI_DW_PORT_1_REGS   0xF0007000
+
+#define SPI_DW_PORT_0_IRQ    25
+#define SPI_DW_PORT_1_IRQ    26
+
+/*
+ * SPI Chip Select Assignments on EM Starter Kit
+ *
+ *  CS0   Pmod6 - pin 1 - J6
+ *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
+ *  CS2   Pmod6 - pin 8 - J6
+ *  CS3   SDCard (onboard)
+ *  CS4   Internal SPI Slave - loopback
+ *  CS5   SPI-Flash (onboard)
+ */
+
+/*
+ * UART
+     UART0 vector 27 0xF0008000
+     UART1 vector 28 0xF0009000
+     UART2 vector 29 0xF000A000
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
+#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
+#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/em9d/soc_config.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/quark_se_ss/Kconfig.defconfig

@@ -29,14 +29,16 @@ config NUM_REGULAR_IRQ_PRIO_LEVELS
 	# This processor supports only 1 Regular Interrupt priority level (1).
 	default 1
 
-config  NUM_IRQS
+config NUM_IRQS
 	# must be > the highest interrupt number used
 	default 68
 
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 32000000
 
+config HARVARD
+	def_bool n
+
 config FLASH_BASE_ADDRESS
 	default 0x40000000
 
@@ -51,171 +53,136 @@ config SRAM_SIZE
 	default 16 if NSIM
 	default 24
 
+config ICCM_BASE_ADDRESS
+	default 0xFFFFFFFF
+
+config ICCM_SIZE
+	default 0
+
 config DCCM_BASE_ADDRESS
 	default 0x80000000
 
 config DCCM_SIZE
 	default 8
 
+config QMSI
+	def_bool y
+
+config QMSI_BUILTIN
+	def_bool y
+
 if GPIO
 
-config GPIO_DW
+config GPIO_QMSI_SS
 	def_bool y
 
-if GPIO_DW
+if GPIO_QMSI_SS
 
-config GPIO_DW_BOTHEDGES_SUPPORT
-	default n
-
-config GPIO_DW_0
+config GPIO_QMSI_SS_0
 	def_bool y
 
-if GPIO_DW_0
+if GPIO_QMSI_SS_0
 
-config GPIO_DW_0_PRI
-	default 2
+config GPIO_QMSI_SS_0_PRI
+	default 1
 
-endif # GPIO_DW_0
+endif # GPIO_QMSI_SS_0
 
-config GPIO_DW_1
+config GPIO_QMSI_SS_1
 	def_bool y
 
-if GPIO_DW_1
+if GPIO_QMSI_SS_1
 
-config GPIO_DW_1_PRI
-	default 2
+config GPIO_QMSI_SS_1_PRI
+	default 1
 
-endif # GPIO_DW_1
+endif # GPIO_QMSI_SS_1
 
-endif # GPIO_DW
+endif # GPIO_QMSI_SS
 
 endif # GPIO
 
+
 if I2C
 
-config I2C_QUARK_SE_SS
+config I2C_QMSI_SS
 	def_bool y
 
-if I2C_QUARK_SE_SS
-
-config I2C_QUARK_SE_SS_0
+config I2C_0
 	def_bool y
 
-if I2C_QUARK_SE_SS_0
-
-config I2C_QUARK_SE_SS_0_NAME
+config I2C_0_NAME
 	default "I2C_0"
 
-config I2C_QUARK_SE_SS_0_DEFAULT_CFG
+config I2C_0_DEFAULT_CFG
 	default 0x12
 
-endif # I2C_QUARK_SE_SS_0
+config I2C_0_IRQ_PRI
+	default 2
 
-if I2C_QUARK_SE_SS_1
+if I2C_1
 
-config I2C_QUARK_SE_SS_1_NAME
+config I2C_1_NAME
 	default "I2C_1"
 
-config I2C_QUARK_SE_SS_1_DEFAULT_CFG
+config I2C_1_DEFAULT_CFG
 	default 0x12
 
-endif # I2C_QUARK_SE_SS_1
+config I2C_1_IRQ_PRI
+	default 2
+
+endif # I2C_1
 
-endif # I2C_QUARK_SE_SS
 
 endif # I2C
 
-if UART_NS16550
 
-config UART_NS16550_PORT_0
-        def_bool y
+if UART_QMSI
+config UART_QMSI_0
+	def_bool y
 
-if UART_NS16550_PORT_0
+if UART_QMSI_0
 
-config UART_NS16550_PORT_0_NAME
-        default "UART_0"
-config UART_NS16550_PORT_0_IRQ_PRI
-        default 1
-config UART_NS16550_PORT_0_BAUD_RATE
-        default 115200
-config UART_NS16550_PORT_0_OPTIONS
-        default 0
+config UART_QMSI_0_IRQ_PRI
+	default 3
 
-endif # UART_NS16550_PORT_0
+endif # UART_QMSI_0
 
-config UART_NS16550_PORT_1
-        def_bool y
+config UART_QMSI_1
+	def_bool y
 
-if UART_NS16550_PORT_1
+if UART_QMSI_1
 
-config UART_NS16550_PORT_1_NAME
-        default "UART_1"
-config UART_NS16550_PORT_1_IRQ_PRI
-        default 1
-config UART_NS16550_PORT_1_BAUD_RATE
-        default 115200
-config UART_NS16550_PORT_1_OPTIONS
-        default 0
+config UART_QMSI_1_IRQ_PRI
+	default 3
 
-endif # UART_NS16550_PORT_1
+endif # UART_QMSI_1
 
-endif # UART_NS16550
+endif # UART_QMSI
 
 if UART_CONSOLE
 
 config UART_CONSOLE_ON_DEV_NAME
-        default "UART_1"
+	default "UART_1"
 
 endif
 
 if SPI
 
-config SPI_DW
+config SPI_QMSI_SS
 	def_bool y
 
-if SPI_DW
-
-config SPI_DW_CLOCK_GATE
-	def_bool n
-
-config SPI_DW_PORT_0
+config SPI_0
 	def_bool y
 
-if SPI_DW_PORT_0
-
-config SPI_DW_PORT_0_PRI
+config SPI_0_IRQ_PRI
 	default 1
-config SPI_DW_PORT_0_REGS
-	default 0x80010000
-config SPI_DW_PORT_0_ERROR_IRQ
-	default 30
-config SPI_DW_PORT_0_RX_IRQ
-	default 31
-config SPI_DW_PORT_0_TX_IRQ
-	default 32
-
-endif # SPI_DW_PORT_0
-
-config SPI_DW_PORT_1
+config SPI_1
 	def_bool y
 
-if SPI_DW_PORT_1
-
-config SPI_DW_PORT_1_PRI
+config SPI_1_IRQ_PRI
 	default 1
-config SPI_DW_PORT_1_REGS
-	default 0x80010100
-config SPI_DW_PORT_1_ERROR_IRQ
-	default 33
-config SPI_DW_PORT_1_RX_IRQ
-	default 34
-config SPI_DW_PORT_1_TX_IRQ
-	default 35
-
-endif # SPI_DW_PORT_1
-
-endif # SPI_DW
-
 endif # SPI
 
+
 endif #SOC_QUARK_SE_ARC

arch/arc/soc/quark_se_ss/Kconfig.soc

@@ -1,4 +1,5 @@
 
 config SOC_QUARK_SE_SS
-        bool "Intel Quark SE - Sensor Sub System"
+	bool "Intel Quark SE - Sensor Sub System"
 	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select HAS_QMSI

arch/arc/soc/quark_se_ss/Makefile

@@ -1,7 +1,5 @@
-
-arch-cflags = $(call cc-option,-mARCv2EM) \
+soc-cflags = $(call cc-option,-mARCv2EM) \
                    $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)
-
-KBUILD_AFLAGS += $(arch-cflags)
-KBUILD_CFLAGS += $(arch-cflags)
-KBUILD_CXXFLAGS += $(arch-cflags)
+soc-aflags = $(soc-cflags)
+soc-cxxflags = $(soc-cflags)
+soc-cflags += -DQM_SENSOR=1

arch/arc/soc/quark_se_ss/linker.ld

@@ -36,4 +36,4 @@
 #define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
 #define DCCM_SIZE		CONFIG_DCCM_SIZE
 
-#include <arch/arc/v2/linker.cmd>
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/quark_se_ss/soc.c

@@ -26,10 +26,6 @@
 #include <init.h>
 #include <quark_se/shared_mem.h>
 
-/* Cannot use microkernel, since only nanokernel is supported */
-#if defined(CONFIG_MICROKERNEL)
-#error "Microkernel support is not available"
-#endif
 
 /**
  *

arch/arc/soc/quark_se_ss/soc.h

@@ -58,16 +58,18 @@
 #define IRQ_I2C1_TX_REQ 23
 #define IRQ_I2C1_STOP_DET 24
 #define IRQ_I2C1_ERR 25
-#define IRQ_SPI0_ERR_INT 26
-#define IRQ_SPI0_RX_AVAIL 27
-#define IRQ_SPI0_TX_REQ 28
-#define IRQ_SPI1_ERR_INT 29
-#define IRQ_SPI1_RX_AVAIL 30
-#define IRQ_SPI1_TX_REQ 31
-#define IRQ_ADC_IRQ 32
-#define IRQ_ADC_ERR 33
-#define IRQ_GPIO0_INTR 34
-#define IRQ_GPIO1_INTR 35
+#define IRQ_SPI0_ERR_INT 30
+#define IRQ_SPI0_RX_AVAIL 31
+#define IRQ_SPI0_TX_REQ 32
+
+#define IRQ_SPI1_ERR_INT 33
+#define IRQ_SPI1_RX_AVAIL 34
+#define IRQ_SPI1_TX_REQ 35
+
+#define IRQ_ADC_ERR 18
+#define IRQ_ADC_IRQ 19
+#define IRQ_GPIO0_INTR 20
+#define IRQ_GPIO1_INTR 21
 #define IRQ_I2C_MST0_INTR 36
 #define IRQ_I2C_MST1_INTR 37
 #define IRQ_SPI_MST0_INTR 38
@@ -181,6 +183,10 @@
 /*
  * SPI
  */
+
+#define SPI_DW_PORT_0_REGS				0x80010000
+#define SPI_DW_PORT_1_REGS				0x80010100
+
 #define SPI_DW_PORT_0_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x430)
 #define SPI_DW_PORT_0_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x434)
 #define SPI_DW_PORT_0_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x438)
@@ -189,6 +195,8 @@
 #define SPI_DW_PORT_1_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x440)
 #define SPI_DW_PORT_1_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x444)
 
+#define SPI_DW_IRQ_FLAGS				0
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _BOARD__H_ */

arch/arm/Makefile

@@ -4,12 +4,44 @@ include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 
 cflags-$(CONFIG_LTO) += $(call cc-option,-flto,)
 
+cflags-cortex-m0 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m0) \
+			$(call cc-option,-mthumb -march=armv6-m)
+cflags-cortex-m0+ = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m0plus) \
+			$(call cc-option,-mthumb -march=armv6-m)
+cflags-cortex-m1 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m1) \
+			$(call cc-option,-mthumb -march=armv6-m)
+cflags-cortex-m3 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m3) \
+			$(call cc-option,-mthumb -march=armv7-m)
+cflags-cortex-m4 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m4) \
+			$(call cc-option,-mthumb -march=armv7e-m)
+cflags-cortex-m7 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m7) \
+			$(call cc-option,-mthumb -march=armv7e-m)
+
+aflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
+cflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
+cxxflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
+_arm_isa-$(CONFIG_CPU_CORTEX_M3) = armv7-m
+
+aflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
+cflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
+cxxflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
+_arm_isa-$(CONFIG_CPU_CORTEX_M4) = armv7e-m
+
+_CROSS_COMPILE_arm_isa = $(_arm_isa-y)
+
+KBUILD_AFLAGS += $(aflags-y)
 KBUILD_CFLAGS += $(cflags-y)
 KBUILD_CXXFLAGS += $(cflags-y)
 
+soc-cxxflags ?= $(soc-cflags)
+soc-aflags ?= $(soc-cflags)
+KBUILD_CFLAGS += $(soc-cflags)
+KBUILD_CXXFLAGS += $(soc-cxxflags)
+KBUILD_AFLAGS += $(soc-aflags)
+
 QEMU_CPU_TYPE_arm = cortex-m3
 QEMU_FLAGS_arm = -cpu  $(QEMU_CPU_TYPE_arm) \
-		-machine lm3s6965evb -nographic
+		-machine lm3s6965evb -nographic -vga none
 QEMU_arm = qemu-system-arm
 
 export QEMU_FLAGS_arm QEMU_arm

arch/arm/core/cortex_m/Makefile

@@ -7,6 +7,5 @@ obj-y = vector_table.o reset.o \
 	nmi_on_reset.o prep_c.o scs.o scb.o nmi.o \
 	exc_manage.o exc_wrapper.o
 
-obj-$(CONFIG_ERRNO) += errno.o
 obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o
 obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o

arch/arm/core/sys_fatal_error_handler.c

@@ -74,7 +74,7 @@ void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF * pEsf)
 	ARG_UNUSED(reason);
 	ARG_UNUSED(pEsf);
 
-	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential(NULL)) {
+	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential()) {
 		PRINTK("Fatal fault in %s ! Spinning...\n",
 		       NANO_CTX_ISR == curCtx
 			       ? "ISR"

arch/arm/core/thread.c

@@ -100,7 +100,8 @@ static ALWAYS_INLINE void _thread_monitor_init(struct tcs *tcs /* thread */
  * @return N/A
  */
 
-void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
+void _new_thread(char *pStackMem, unsigned stackSize,
+		 void *uk_task_ptr, _thread_entry_t pEntry,
 		 void *parameter1, void *parameter2, void *parameter3,
 		 int priority, unsigned options)
 {
@@ -143,6 +144,12 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 	tcs->entry = (struct __thread_entry *)(pInitCtx);
 #endif
 
+#ifdef CONFIG_MICROKERNEL
+	tcs->uk_task_ptr = uk_task_ptr;
+#else
+	ARG_UNUSED(uk_task_ptr);
+#endif
+
 	tcs->preempReg.psp = (uint32_t)pInitCtx;
 	tcs->basepri = 0;
 

arch/arm/include/nano_private.h

@@ -139,6 +139,9 @@ struct tcs {
 #ifdef CONFIG_ERRNO
 	int errno_var;
 #endif
+#ifdef CONFIG_MICROKERNEL
+	void *uk_task_ptr;
+#endif
 };
 
 struct s_NANO {

arch/arm/soc/atmel_sam3/Kbuild

@@ -1 +0,0 @@
-obj-y += soc.o

arch/arm/soc/atmel_sam3/Kconfig.defconfig

@@ -99,11 +99,16 @@ if I2C
 config I2C_ATMEL_SAM3
 	def_bool y
 
-config I2C_ATMEL_SAM3_0
+config I2C_0
+	default y
+config I2C_0_IRQ_PRI
+	default 0
+
+config I2C_1
 	default y
 
-config I2C_ATMEL_SAM3_1
-	default y
+config I2C_1_IRQ_PRI
+	default 0
 
 endif # I2C
 

arch/arm/soc/atmel_sam3/Makefile

@@ -1,7 +1 @@
-
-arch-cflags += $(call cc-option,-mthumb -mcpu=cortex-m3) \
-		$(call cc-option,-mthumb -march=armv7-m)
-
-KBUILD_AFLAGS += $(arch-cflags)
-KBUILD_CXXFLAGS += $(arch-cflags)
-KBUILD_CFLAGS += $(arch-cflags)
+obj-y += soc.o

arch/arm/soc/atmel_sam3/linker.ld

@@ -1,4 +1,4 @@
-/* linker.cmd - Linker command/script file */
+/* linker.ld - Linker command/script file */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
@@ -16,4 +16,4 @@
  * limitations under the License.
  */
 
-#include <arch/arm/cortex_m/scripts/linker.cmd>
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/atmel_sam3/soc.c

@@ -38,7 +38,7 @@
  * Assumption:
  * SLCK = 32.768kHz
  */
-static void clock_init(void)
+static ALWAYS_INLINE void clock_init(void)
 {
 	uint32_t tmp;
 

arch/arm/soc/nordic_nrf5/Kbuild

@@ -0,0 +1,2 @@
+
+obj-y += $(SOC_SERIES)/

arch/arm/soc/nordic_nrf5/Kconfig

@@ -0,0 +1,29 @@
+# Kconfig - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config SOC_NRF5
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
+
+if SOC_FAMILY_NRF5
+config SOC_FAMILY
+	string
+	default nordic_nrf5
+endif
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.soc"

arch/arm/soc/nordic_nrf5/Kconfig.defconfig

@@ -0,0 +1,18 @@
+# Kconfig.defconfig - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.defconfig.series"

arch/arm/soc/nordic_nrf5/Kconfig.soc

@@ -0,0 +1,19 @@
+# Kconfig.soc - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.series"
+

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52832

@@ -0,0 +1,40 @@
+# Kconfig.defconfig.nrf52832 - Nordic Semiconductor nRF52832 MCU
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+
+if SOC_NRF52832
+
+config SOC
+	string
+	default nRF52832
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 64000000
+
+config SRAM_SIZE
+	default 64
+
+config FLASH_SIZE
+	default 512
+
+config NUM_IRQS
+	int
+	default 38
+
+endif # SOC_NRF52832
+

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.series

@@ -0,0 +1,35 @@
+# Kconfig.defconfig.series - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_SERIES_NRF52X
+
+source "arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52*"
+
+config SOC_SERIES
+	default nordic_nrf5/nrf52
+
+config SRAM_BASE_ADDRESS
+	default 0x20000000
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config NUM_IRQ_PRIO_BITS
+	int
+	default 3
+
+endif # SOC_SERIES_NRF52X

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.series

@@ -0,0 +1,28 @@
+# Kconfig.series - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config  SOC_SERIES_NRF52X
+	bool "Nordic Semiconductor nRF52 series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_NRF5
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select XIP
+	select HAS_CMSIS
+	select HAS_NORDIC_MDK
+	help
+	 Enable support for NRF52 MCU series

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.soc

@@ -0,0 +1,25 @@
+# Kconfig.soc - Nordic Semiconductor nRF52 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+choice
+prompt "nRF52x MCU Selection"
+depends on SOC_SERIES_NRF52X
+
+config SOC_NRF52832
+	bool "NRF52832"
+
+endchoice

arch/arm/soc/nordic_nrf5/nrf52/Makefile

@@ -0,0 +1,19 @@
+ifdef CONFIG_SOC_SERIES_NRF52X
+soc-cflags += -DNRF52
+endif
+
+obj-y += soc.o
+
+KERNEL_HEX_NAME = $(KERNEL_NAME).hex
+
+quiet_cmd_gen_hex = HEX     $@
+      cmd_gen_hex =                                                         \
+(                                                                           \
+   $(OBJCOPY) -S -O ihex -R .note -R .comment -R COMMON -R .eh_frame $< $@; \
+)
+
+$(KERNEL_HEX_NAME): $(KERNEL_ELF_NAME)
+	$(call cmd,gen_hex)
+
+zephyr: $(KERNEL_HEX_NAME)
+all: $(KERNEL_HEX_NAME)

arch/arm/soc/nordic_nrf5/nrf52/linker.ld

@@ -1,4 +1,4 @@
-/* linker.cmd - Linker command/script file */
+/* linker.ld - Linker command/script file */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
@@ -16,4 +16,4 @@
  * limitations under the License.
  */
 
-#include <arch/arm/cortex_m/scripts/linker.cmd>
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/nordic_nrf5/nrf52/soc.c

@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Nordic Semiconductor nRF52 family processor
+ *
+ * This module provides routines to initialize and support board-level hardware
+ * for the Nordic Semiconductor nRF52 family processor.
+ */
+
+#include <nanokernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+
+#ifdef CONFIG_RUNTIME_NMI
+extern void _NmiInit(void);
+#define NMI_INIT() _NmiInit()
+#else
+#define NMI_INIT()
+#endif
+
+#include "nrf.h"
+
+#define __SYSTEM_CLOCK_64M (64000000UL)
+
+static bool ftpan_32(void);
+static bool ftpan_37(void);
+static bool ftpan_36(void);
+
+uint32_t SystemCoreClock __used = __SYSTEM_CLOCK_64M;
+
+static void clock_init(void)
+{
+	SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+static int nordicsemi_nrf52_init(struct device *arg)
+{
+	uint32_t key;
+
+	ARG_UNUSED(arg);
+
+	/* Note:
+	* Magic numbers below are obtained by reading the registers
+	* when the SoC was running the SAM-BA bootloader
+	* (with reserved bits set to 0).
+	*/
+
+	key = irq_lock();
+
+	/* Setup the vector table offset register (VTOR),
+	* which is located at the beginning of flash area.
+	*/
+	_scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS);
+
+	/* Workaround for FTPAN-32 "DIF: Debug session automatically
+	* enables TracePort pins" found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_32()) {
+		CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
+	}
+
+	/* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio,
+	* ECB, AAR and CCM." found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_37()) {
+		*(volatile uint32_t *)0x400005A0 = 0x3;
+	}
+
+	/* Workaround for FTPAN-36 "CLOCK: Some registers are not
+	* reset when expected." found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_36()) {
+		NRF_CLOCK->EVENTS_DONE = 0;
+		NRF_CLOCK->EVENTS_CTTO = 0;
+	}
+
+	/* Enable the FPU if the compiler used floating point unit
+	* instructions. __FPU_USED is a MACRO defined by the
+	* compiler. Since the FPU consumes energy, remember to
+	* disable FPU use in the compiler if floating point unit
+	* operations are not used in your code.
+	*/
+	#if (__FPU_USED == 1)
+
+	SCB->CPACR |= (3UL << 20) | (3UL << 22);
+	__DSB();
+	__ISB();
+
+	#endif
+
+	/* Configure NFCT pins as GPIOs if NFCT is not to be used in
+	* your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+	* two GPIOs (see Product Specification to see which ones)
+	* will be reserved for NFC and will not be available as
+	* normal GPIOs.
+	*/
+	#if defined(CONFIG_NFCT_PINS_AS_GPIOS)
+
+	if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) ==
+	    (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)) {
+
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NVIC_SystemReset();
+	}
+
+	#endif
+
+	/* Configure GPIO pads as pPin Reset pin if Pin Reset
+	* capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+	* defined, pin reset will not be available. One GPIO (see
+	* Product Specification to see which one) will then be
+	* reserved for PinReset and not available as normal GPIO.
+	*/
+	#if defined(CONFIG_GPIO_AS_PINRESET)
+	if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
+	     (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+	    ((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
+	     (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) {
+
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->PSELRESET[0] = 21;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->PSELRESET[1] = 21;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NVIC_SystemReset();
+	}
+	#endif
+
+	/* Enable SWO trace functionality. If ENABLE_SWO is not
+	* defined, SWO pin will be used as GPIO (see Product
+	* Specification to see which one).
+	*/
+	#if defined(ENABLE_SWO)
+
+	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+	NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial <<
+				  CLOCK_TRACECONFIG_TRACEMUX_Pos;
+	#endif
+
+	/* Enable Trace functionality. If ENABLE_TRACE is not
+	* defined, TRACE pins will be used as GPIOs (see Product
+	* Specification to see which ones).
+	*/
+	#if defined(ENABLE_TRACE)
+	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+	NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel <<
+				  CLOCK_TRACECONFIG_TRACEMUX_Pos;
+	#endif
+
+	/* Clear all faults */
+	_ScbMemFaultAllFaultsReset();
+	_ScbBusFaultAllFaultsReset();
+	_ScbUsageFaultAllFaultsReset();
+
+	_ScbHardFaultAllFaultsReset();
+
+	/* Setup master clock */
+	clock_init();
+
+	/* Install default handler that simply resets the CPU
+	* if configured in the kernel, NOP otherwise
+	*/
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+static bool ftpan_32(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static bool ftpan_37(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static bool ftpan_36(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+SYS_INIT(nordicsemi_nrf52_init, PRIMARY, 0);

arch/arm/soc/nordic_nrf5/nrf52/soc.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file SoC configuration macros for the Nordic Semiconductor nRF52 family processors.
+ */
+
+#ifndef _NORDICSEMI_NRF52_SOC_H_
+#define _NORDICSEMI_NRF52_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include "soc_irq.h"
+#include <nrf52.h>
+#include <nrf52_bitfields.h>
+#include <device.h>
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _NORDICSEMI_NRF52_SOC_H_ */

arch/arm/soc/nordic_nrf5/nrf52/soc_irq.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Interrupt numbers for NRF52 family processors.
+ *
+ * Based on Nordic MDK included header file: nrf52.h
+ */
+
+
+#ifndef _NRF52_SOC_IRQ_H_
+#define _NRF52_SOC_IRQ_H_
+
+#define NRF52_IRQ_POWER_CLOCK_IRQn			 0
+#define NRF52_IRQ_RADIO_IRQn				 1
+#define NRF52_IRQ_UARTE0_UART0_IRQn			 2
+#define NRF52_IRQ_SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn 3
+#define NRF52_IRQ_SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn 4
+#define NRF52_IRQ_NFCT_IRQn				 5
+#define NRF52_IRQ_GPIOTE_IRQn				 6
+#define NRF52_IRQ_SAADC_IRQn				 7
+#define NRF52_IRQ_TIMER0_IRQn				 8
+#define NRF52_IRQ_TIMER1_IRQn				 9
+#define NRF52_IRQ_TIMER2_IRQn				 10
+#define NRF52_IRQ_RTC0_IRQn				 11
+#define NRF52_IRQ_TEMP_IRQn				 12
+#define NRF52_IRQ_RNG_IRQn				 13
+#define NRF52_IRQ_ECB_IRQn				 14
+#define NRF52_IRQ_CCM_AAR_IRQn				 15
+#define NRF52_IRQ_WDT_IRQn				 16
+#define NRF52_IRQ_RTC1_IRQn				 17
+#define NRF52_IRQ_QDEC_IRQn				 18
+#define NRF52_IRQ_COMP_LPCOMP_IRQn			 19
+#define NRF52_IRQ_SWI0_EGU0_IRQn			 20
+#define NRF52_IRQ_SWI1_EGU1_IRQn			 21
+#define NRF52_IRQ_SWI2_EGU2_IRQn			 22
+#define NRF52_IRQ_SWI3_EGU3_IRQn			 23
+#define NRF52_IRQ_SWI4_EGU4_IRQn			 24
+#define NRF52_IRQ_SWI5_EGU5_IRQn			 25
+#define NRF52_IRQ_TIMER3_IRQn				 26
+#define NRF52_IRQ_TIMER4_IRQn				 27
+#define NRF52_IRQ_PWM0_IRQn				 28
+#define NRF52_IRQ_PDM_IRQn				 29
+#define NRF52_IRQ_MWU_IRQn				 32
+#define NRF52_IRQ_PWM1_IRQn				 33
+#define NRF52_IRQ_PWM2_IRQn				 34
+#define NRF52_IRQ_SPIM2_SPIS2_SPI2_IRQn			 35
+#define NRF52_IRQ_RTC2_IRQn				 36
+#define NRF52_IRQ_I2S_IRQn				 37
+#define NRF52_IRQ_FPU_IRQn				 38
+
+#endif /* _NRF52_SOC_IRQ_H_ */

arch/arm/soc/nxp_kinetis/k6x/Kbuild

@@ -1,3 +0,0 @@
-obj-y += soc_config.o
-obj-y += soc.o
-obj-y += wdog.o

arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.mk64f12

@@ -154,13 +154,13 @@ config SPI_K64
 
 if SPI_K64
 
-config SPI_K64_0
+config SPI_0
 	def_bool y
 
-config SPI_K64_1
+config SPI_1
 	def_bool n
 
-config SPI_K64_2
+config SPI_2
 	def_bool n
 
 endif # SPI_K64

arch/arm/soc/nxp_kinetis/k6x/Kconfig.soc

@@ -20,7 +20,7 @@ prompt "Kinetis K6x MCU Selection"
 depends on SOC_SERIES_KINETIS_K6X
 
 config SOC_MK64F12
-       bool "SOC_MK64F12"
+	bool "SOC_MK64F12"
 
 endchoice
 

arch/arm/soc/nxp_kinetis/k6x/Makefile

@@ -1,8 +1,3 @@
-
-
-arch-cflags = $(call cc-option,-mthumb -mcpu=cortex-m4) \
-			$(call cc-option,-mthumb -march=armv7e-m)
-
-KBUILD_CFLAGS += $(arch-cflags)
-KBUILD_CXXFLAGS += $(arch-cflags)
-KBUILD_AFLAGS += $(arch-cflags)
+obj-y += soc_config.o
+obj-y += soc.o
+obj-y += wdog.o

arch/arm/soc/nxp_kinetis/k6x/linker.ld

@@ -38,4 +38,4 @@
 	#define SKIP_TO_SECURITY_FRDM_K64F . = 0x400;
 #endif
 
-#include <arch/arm/cortex_m/scripts/linker.cmd>
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/nxp_kinetis/k6x/soc.c

@@ -91,7 +91,7 @@ uint8_t __security_frdm_k64f_section __security_frdm_k64f[] = {
  *
  */
 
-static void clkInit(void)
+static ALWAYS_INLINE void clkInit(void)
 {
 	uint8_t temp_reg;
 	K20_MCG_t *mcg_p = (K20_MCG_t *)PERIPH_ADDR_BASE_MCG; /* clk gen. ctl */

arch/arm/soc/nxp_kinetis/k6x/soc_config.c

@@ -39,8 +39,8 @@
 
 #ifdef CONFIG_UART_K20
 
-#if defined(CONFIG_UART_CONSOLE)
-#if defined(CONFIG_PRINTK) || defined(CONFIG_STDOUT_CONSOLE)
+#if defined(CONFIG_UART_CONSOLE) && \
+	(defined(CONFIG_PRINTK) || defined(CONFIG_STDOUT_CONSOLE))
 
 /**
  * @brief Initialize K20 serial port as console
@@ -51,7 +51,7 @@
  *
  * @return 0 if successful, otherwise failed.
  */
-static int uart_k20_console_init(struct device *dev)
+static ALWAYS_INLINE int uart_k20_console_init(void)
 {
 	uint32_t port;
 	uint32_t rxPin;
@@ -76,10 +76,9 @@ static int uart_k20_console_init(struct device *dev)
 	return 0;
 }
 
-SYS_INIT(uart_k20_console_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
-#endif
-#endif /* CONFIG_UART_CONSOLE */
+#else
+#define uart_k20_console_init(...)
+#endif /* CONFIG_UART_CONSOLE && (CONFIG_PRINTK || CONFIG_STDOUT_CONSOLE) */
 
 static int uart_k20_init(struct device *dev)
 {
@@ -117,6 +116,9 @@ static int uart_k20_init(struct device *dev)
 	sim->scgc1.field.uart4_clk_en = 1;
 #endif
 
+	/* Initialize UART port for console if needed */
+	uart_k20_console_init();
+
 	return 0;
 }
 

arch/arm/soc/st_stm32/stm32f1/Kbuild

@@ -1,4 +0,0 @@
-obj-y += soc.o
-
-obj-$(CONFIG_GPIO) += soc_gpio.o
-obj-$(CONFIG_PINMUX) += soc_config.o

arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.series

@@ -20,16 +20,16 @@ if SOC_SERIES_STM32F1X
 source "arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f1*"
 
 config SOC_SERIES
-       default stm32f1
+	default stm32f1
 
 config SRAM_BASE_ADDRESS
-        default 0x20000000
+	default 0x20000000
 
 config FLASH_BASE_ADDRESS
-        default 0x08000000
+	default 0x08000000
 
 config NUM_IRQ_PRIO_BITS
-        int
-        default 4
+	int
+	default 4
 
 endif # SOC_SERIES_STM32F1X

arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103rb

@@ -21,14 +21,14 @@ config SOC
 	string
 	default stm32f103rb
 config SRAM_SIZE
-       default 20
+	default 20
 
 config FLASH_SIZE
-       default 128
+	default 128
 
 config NUM_IRQS
-        int
-        default 59
+	int
+	default 59
 
 endif # SOC_STM32F103RB
 

arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103ve

@@ -22,14 +22,14 @@ config SOC
 	default stm32f103ve
 
 config SRAM_SIZE
-       default 64
+	default 64
 
 config FLASH_SIZE
-       default 512
+	default 512
 
 config NUM_IRQS
-        int
-        default 68
+	int
+	default 68
 
 endif # SOC_STM32F103VE
 

arch/arm/soc/st_stm32/stm32f1/Kconfig.soc

@@ -20,9 +20,9 @@ prompt "STM32F1x MCU Selection"
 depends on SOC_SERIES_STM32F1X
 
 config SOC_STM32F103VE
-       bool "STM32F103VE"
+	bool "STM32F103VE"
 
 config SOC_STM32F103RB
-       bool "STM32F103RB"
+	bool "STM32F103RB"
 
 endchoice

arch/arm/soc/st_stm32/stm32f1/Makefile

@@ -1,7 +1,4 @@
+obj-y += soc.o
 
-arch-cflags += $(call cc-option,-mthumb -mcpu=cortex-m3) \
-		$(call cc-option,-mthumb -march=armv7-m)
-
-KBUILD_AFLAGS += $(arch-cflags)
-KBUILD_CXXFLAGS += $(arch-cflags)
-KBUILD_CFLAGS += $(arch-cflags)
+obj-$(CONFIG_GPIO) += soc_gpio.o
+obj-$(CONFIG_PINMUX) += soc_config.o

arch/arm/soc/st_stm32/stm32f1/linker.ld

@@ -1,4 +1,4 @@
-/* linker.cmd - Linker command/script file */
+/* linker.ld - Linker command/script file */
 
 /*
  * Copyright (c) 2014-2016 Wind River Systems, Inc.
@@ -16,4 +16,4 @@
  * limitations under the License.
  */
 
-#include <arch/arm/cortex_m/scripts/linker.cmd>
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/ti_lm3s6965/Kbuild

@@ -1,3 +0,0 @@
-obj-y += soc_config.o
-obj-y += soc.o
-obj-y += scp.o

arch/arm/soc/ti_lm3s6965/Makefile

@@ -1,7 +1,3 @@
-
-arch-cflags  = $(call cc-option,-mthumb -mcpu=cortex-m3) \
-		$(call cc-option,-mthumb -march=armv7-m)
-
-KBUILD_CFLAGS += $(arch-cflags)
-KBUILD_CXXFLAGS += $(arch-cflags)
-KBUILD_AFLAGS += $(arch-cflags)
+obj-y += soc_config.o
+obj-y += soc.o
+obj-y += scp.o

arch/arm/soc/ti_lm3s6965/linker.ld

@@ -0,0 +1,19 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/nios2/Kbuild

@@ -0,0 +1,6 @@
+subdir-ccflags-y +=-I$(srctree)/include/drivers
+subdir-ccflags-y +=-I$(srctree)/drivers
+subdir-asflags-y += $(subdir-ccflags-y)
+
+obj-y += soc/$(SOC_PATH)/
+obj-y += core/

arch/nios2/Kconfig

@@ -0,0 +1,102 @@
+#
+# Copyright (c) 2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+choice
+	prompt "Nios II configuration selection"
+	depends on NIOS2
+	source "arch/nios2/soc/*/Kconfig.soc"
+endchoice
+
+menu "Nios II Options"
+	depends on NIOS2
+
+config ARCH
+	string
+	default "nios2"
+
+config ARCH_DEFCONFIG
+	string
+	default "arch/nios2/defconfig"
+
+menu "Nios II Gen 2 Processor Options"
+
+config CPU_NIOS2_GEN2
+	bool
+	default y
+	select ATOMIC_OPERATIONS_C
+	help
+	This option signifies the use of a Nios II Gen 2 CPU
+
+endmenu
+
+menu "Nios II Family Options"
+
+# FIXME default is probably bogus
+config RESET_VECTOR
+	prompt "Nios II reset vector"
+	hex
+	default 0x00000000
+
+# FIXME default is probably bogus
+config EXCEPTION_VECTOR
+	prompt "Nios II exception vector"
+	hex
+	default 0x00000004
+
+config XIP
+	bool
+	default y
+
+config SRAM_SIZE
+	int "SRAM Size in kB"
+	help
+	This option specifies the size of the SRAM in kB.  It is normally set
+	by the platform's defconfig file and the user should generally avoid
+	modifying it via the menu configuration.
+
+config SRAM_BASE_ADDRESS
+	hex "SRAM Base Address"
+	help
+	This option specifies the base address of the SRAM on the platform.  It
+	is normally set by the platform's defconfig file and the user should
+	generally avoid modifying it via the menu configuration.
+
+config FLASH_SIZE
+	int "Flash Size in kB"
+	help
+	This option specifies the size of the flash in kB.  It is normally set
+	by the platform's defconfig file and the user should generally avoid
+	modifying it via the menu configuration.
+
+config FLASH_BASE_ADDRESS
+	hex "Flash Base Address"
+	help
+	This option specifies the base address of the flash on the platform.
+	It is normally set by the platform's defconfig file and the user should
+	generally avoid modifying it via the menu configuration.
+
+config IRQ_OFFLOAD
+	bool "Enable IRQ offload"
+	default n
+	help
+	Enable irq_offload() API which allows functions to be synchronously
+	run in interrupt context. Mainly useful for test cases.
+
+endmenu
+
+source "arch/nios2/soc/*/Kconfig"
+
+endmenu

arch/nios2/Makefile

@@ -0,0 +1,29 @@
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
+
+# FIXME: Disable use of global pointer for now, this isn't properly set up
+# in our linker script.
+arch_cflags := $(call cc-option,-G0)
+
+# FIXME I got tired of adding ARG_UNUSED to all the stubs, sanitycheck treats
+# warnings as errors. Remove this once the stubs are all implemented
+arch_cflags += $(call cc-option,-Wno-unused-parameter)
+
+# Put functions and data in their own binary sections so that ld can
+# garbage collect them
+arch_cflags += $(call cc-option,-ffunction-sections) \
+	       $(call cc-option,-fdata-sections)
+
+# Nios II CPUs are configurable and we need to pull in the generated
+# headers system.h and linker.h which specify what is enabled and where
+# everything is.
+arch_cflags += $(call cc-option,-I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/include)
+
+KBUILD_AFLAGS += $(arch_cflags)
+KBUILD_CFLAGS += $(arch_cflags)
+KBUILD_CXXFLAGS += $(arch_cflags)
+
+soc-cxxflags ?= $(soc-cflags)
+soc-aflags ?= $(soc-cflags)
+KBUILD_CFLAGS += $(soc-cflags)
+KBUILD_CXXFLAGS += $(soc-cxxflags)
+KBUILD_AFLAGS += $(soc-aflags)

arch/nios2/core/Makefile

@@ -0,0 +1,9 @@
+ccflags-y += -I$(srctree)/kernel/nanokernel/include
+ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
+ccflags-y += -I$(srctree)/kernel/microkernel/include
+
+obj-y += reset.o irq_manage.o fatal.o swap.o thread.o \
+	 cpu_idle.o irq_offload.o prep_c.o crt0.o
+
+obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
+

arch/nios2/core/cpu_idle.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <nano_private.h>
+
+/**
+ *
+ * @brief Power save idle routine
+ *
+ * This function will be called by the nanokernel idle loop or possibly within
+ * an implementation of _sys_power_save_idle in the microkernel when the
+ * '_sys_power_save_flag' variable is non-zero.
+ *
+ * @return N/A
+ */
+void nano_cpu_idle(void)
+{
+	/* STUB */
+}
+
+/**
+ *
+ * @brief Atomically re-enable interrupts and enter low power mode
+ *
+ * This function is utilized by the nanokernel object "wait" APIs for tasks,
+ * e.g. nano_task_lifo_get(), nano_task_sem_take(),
+ * nano_task_stack_pop(), and nano_task_fifo_get().
+ *
+ * INTERNAL
+ * The requirements for nano_cpu_atomic_idle() are as follows:
+ * 1) The enablement of interrupts and entering a low-power mode needs to be
+ *    atomic, i.e. there should be no period of time where interrupts are
+ *    enabled before the processor enters a low-power mode.  See the comments
+ *    in nano_task_lifo_get(), for example, of the race condition that
+ *    occurs if this requirement is not met.
+ *
+ * 2) After waking up from the low-power mode, the interrupt lockout state
+ *    must be restored as indicated in the 'imask' input parameter.
+ *
+ * @return N/A
+ */
+void nano_cpu_atomic_idle(unsigned int key)
+{
+	/* STUB */
+}
+

arch/nios2/core/crt0.S

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define _ASMLANGUAGE
+#include <arch/nios2/asm.h>
+
+/* exports */
+GTEXT(__start)
+
+/* imports */
+GTEXT(_PrepC)
+
+
+SECTION_FUNC(TEXT_START, __start)
+
+	/* TODO initialize instruction cache, if present */
+
+	/* TODO if shadow register sets enabled, ensure we are in set 0 */
+
+	/* TODO initialize data cache, if present */
+
+	/* TODO setup stack pointer */
+
+	/* TODO setup global pointer, if used */
+
+	/* TODO if shadow register sets enabled, interate through them to set
+	 * up. Need to clear r0, write gp, set the execption stack pointer */
+
+	/* Jump into C domain. _PrepC zeroes BSS, copies rw data into RAM,
+	 * and then enters nanokernel _Cstart */
+	call _PrepC
+

arch/nios2/core/fatal.c

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <arch/cpu.h>
+#include <nano_private.h>
+#include <misc/printk.h>
+
+/* TODO initialize with sentinel values */
+const NANO_ESF _default_esf;
+
+
+/**
+ *
+ * @brief Nanokernel fatal error handler
+ *
+ * This routine is called when a fatal error condition is detected by either
+ * hardware or software.
+ *
+ * The caller is expected to always provide a usable ESF.  In the event that the
+ * fatal error does not have a hardware generated ESF, the caller should either
+ * create its own or call _Fault instead.
+ *
+ * @param reason the reason that the handler was called
+ * @param pEsf pointer to the exception stack frame
+ *
+ * @return This function does not return.
+ */
+FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
+					  const NANO_ESF *esf)
+{
+	/* STUB TODO: dump out reason for the error and any interesting
+	 * info in esf
+	 */
+
+	_SysFatalErrorHandler(reason, esf);
+}
+
+
+
+FUNC_NORETURN void _Fault(void)
+{
+	/* STUB TODO dump out reason for this exception */
+
+	_NanoFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, &_default_esf);
+}
+
+/**
+ *
+ * @brief Fatal error handler
+ *
+ * This routine implements the corrective action to be taken when the system
+ * detects a fatal error.
+ *
+ * This sample implementation attempts to abort the current thread and allow
+ * the system to continue executing, which may permit the system to continue
+ * functioning with degraded capabilities.
+ *
+ * System designers may wish to enhance or substitute this sample
+ * implementation to take other actions, such as logging error (or debug)
+ * information to a persistent repository and/or rebooting the system.
+ *
+ * @param reason the fatal error reason
+ * @param pEsf the pointer to the exception stack frame
+ *
+ * @return This function does not return.
+ */
+FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
+					 const NANO_ESF *esf)
+{
+	/* STUB TODO try to abort task/fibers like in the x86 implementation */
+	printk("Fatal error!\n");
+
+	while (1) {
+		/* whee! */
+	}
+}
+
+
+

arch/nios2/core/irq_manage.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <arch/cpu.h>
+#include <irq.h>
+
+
+void _arch_irq_enable(unsigned int irq)
+{
+	/* STUB */
+	ARG_UNUSED(irq);
+};
+
+
+void _arch_irq_disable(unsigned int irq)
+{
+	/* STUB */
+	ARG_UNUSED(irq);
+};
+
+
+int _arch_irq_connect_dynamic(unsigned int irq,
+					 unsigned int priority,
+					 void (*routine)(void *parameter),
+					 void *parameter,
+					 uint32_t flags)
+{
+	ARG_UNUSED(irq);
+	ARG_UNUSED(priority);
+	ARG_UNUSED(routine);
+	ARG_UNUSED(parameter);
+	ARG_UNUSED(flags);
+
+	/* STUB. May never implement this, part of a deprecated API */
+	return -1;
+};
+

arch/nios2/core/irq_offload.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <nano_private.h>
+#include <irq_offload.h>
+
+void irq_offload(irq_offload_routine_t routine, void *parameter)
+{
+	/* STUB */
+}
+

arch/nios2/core/offsets/offsets.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Nios II nano kernel structure member offset definition file
+ *
+ * This module is responsible for the generation of the absolute symbols whose
+ * value represents the member offsets for various Nios II nanokernel
+ * structures.
+ *
+ * All of the absolute symbols defined by this module will be present in the
+ * final microkernel or nanokernel ELF image (due to the linker's reference to
+ * the _OffsetAbsSyms symbol).
+ *
+ * INTERNAL
+ * It is NOT necessary to define the offset for every member of a structure.
+ * Typically, only those members that are accessed by assembly language routines
+ * are defined; however, it doesn't hurt to define all fields for the sake of
+ * completeness.
+ */
+
+
+#include <gen_offset.h>
+#include <nano_private.h>
+#include <nano_offsets.h>
+
+/* size of the struct tcs structure sans save area for floating point regs */
+GEN_ABSOLUTE_SYM(__tTCS_NOFLOAT_SIZEOF, sizeof(tTCS));
+
+GEN_ABS_SYM_END