Zephyr 1.9.1

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.checkpatch.conf

@@ -11,7 +11,6 @@
 --ignore SPLIT_STRING
 --ignore VOLATILE
 --ignore CONFIG_EXPERIMENTAL
---ignore PREFER_KERNEL_TYPES
 --ignore AVOID_EXTERNS
 --ignore NETWORKING_BLOCK_COMMENT_STYLE
 --ignore DATE_TIME
@@ -19,4 +18,3 @@
 --ignore CONST_STRUCT
 --ignore FILE_PATH_CHANGES
 --exclude ext
---exclude net/ip/contiki

.gitignore

@@ -13,18 +13,25 @@ outdir
 outdir-*
 scripts/basic/fixdep
 scripts/gen_idt/gen_idt
-scripts/gen_offset_header/gen_offset_header
 scripts/kconfig/conf
 scripts/kconfig/mconf
 scripts/kconfig/zconf.hash.c
 scripts/kconfig/zconf.lex.c
 scripts/kconfig/zconf.tab.c
 doc/_build
+doc/doxygen
 doc/xml
 doc/html
+doc/boards
+doc/samples
 doc/latex
+doc/themes/zephyr-docs-theme
 sanity-out/
 scripts/grub
 doc/reference/kconfig/CONFIG_*
 doc/reference/kconfig/index.rst
 tags
+.project
+.cproject
+.xxproject
+.envrc

.gitlint

@@ -0,0 +1,54 @@
+# All these sections are optional, edit this file as you like.
+[general]
+ignore=title-trailing-punctuation, T3, title-max-length, T1
+# verbosity should be a value between 1 and 3, the commandline -v flags take precedence over this
+verbosity = 3
+# By default gitlint will ignore merge commits. Set to 'false' to disable.
+ignore-merge-commits=true
+# Enable debug mode (prints more output). Disabled by default
+debug = false
+
+# Set the extra-path where gitlint will search for user defined rules
+# See http://jorisroovers.github.io/gitlint/user_defined_rules for details
+extra-path=scripts/gitlint
+
+[title-max-length-no-revert]
+line-length=72
+
+[body-max-line-count]
+max-line-count=200
+
+[title-starts-with-subsystem]
+regex = ^(([^:]+):)(\s([^:]+):)*\s(.+)$
+
+[title-must-not-contain-word]
+# Comma-separated list of words that should not occur in the title. Matching is case
+# insensitive. It's fine if the keyword occurs as part of a larger word (so "WIPING"
+# will not cause a violation, but "WIP: my title" will.
+words=wip,title
+
+[title-match-regex]
+# python like regex (https://docs.python.org/2/library/re.html) that the
+# commit-msg title must be matched to.
+# Note that the regex can contradict with other rules if not used correctly
+# (e.g. title-must-not-contain-word).
+#regex=^US[0-9]*
+
+[max-line-length-with-exceptions]
+# B1 = body-max-line-length
+line-length=72
+
+[body-min-length]
+min-length=3
+
+[body-is-missing]
+# Whether to ignore this rule on merge commits (which typically only have a title)
+# default = True
+ignore-merge-commits=false
+
+[body-changed-file-mention]
+# List of files that need to be explicitly mentioned in the body when they are changed
+# This is useful for when developers often erroneously edit certain files or git submodules.
+# By specifying this rule, developers can only change the file when they explicitly reference
+# it in the commit message.
+#files=gitlint/rules.py,README.md

.gitreview

@@ -1,4 +0,0 @@
-[gerrit]
-host=gerrit.zephyrproject.org
-port=29418
-project=zephyr.git

.known-issues/doc/bluetooth.conf

@@ -36,3 +36,7 @@
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
 ^.*bt_gatt_read_params.__unnamed__.*
 ^[- \t]*\^
+#
+# Bluetooth packed
+#
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: cpp:typeOrConcept targets a member \(__packed\).$

.known-issues/doc/header_footer.conf

@@ -10,7 +10,7 @@
 ^srctree=.* SRCARCH=\w+ python scripts/genrest/genrest.py .*$
 # This cuts the sphinx build line; has to be separate because in the
 # middle, we have removed the KERNELVERSION one and a full regex won't match
-^sphinx-build -t \w+ -b html -d [-._/\w]+  -q \. .*
+^sphinx-build -t \w+ -b html .*
 #
 # Documentation generation, footer message
 #

.known-issues/doc/kernel.conf

@@ -0,0 +1,14 @@
+#
+# Kernel unnamed struct definition
+#
+# FIXME: all these should match the relative filename
+#
+^(?P<filename>[-._/\w]+/doc/api/kernel_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^[ \t]*$
+^[ \t]*\^$
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^[ \t]*$
+^[ \t]*\^$
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]$
+^.*k_msg.extra.*$
+^[- \t]*\^$

.known-issues/doc/networking.conf

@@ -0,0 +1,113 @@
+#
+# Networking
+#
+#
+# include/net/net_ip.h warnings
+#
+^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*in[_6]+addr.in[46]_u
+^[- \t]*\^
+#
+# include/net/net_if.h warnings
+#
+^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Error when parsing function declaration.
+^\If the function has no return type:
+^[ \t]*Error in declarator or parameters and qualifiers
+^[ \t]*Invalid definition: Expected identifier in nested name, got keyword: struct \[error at [0-9]+]
+^.*struct net_if __aligned\(32\)
+^[- \t]*\^
+^\If the function has a return type:
+^[ \t]*Error in declarator or parameters and qualifiers
+^[ \t]*If pointer to member declarator:
+^[ \t]*Invalid definition: Expected \'::\' in pointer to member \(function\). \[error at [0-9]+]
+^.*struct net_if __aligned\(32\)
+^[- \t]*\^
+^[ \t]*If declarator-id:
+^[ \t]*Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^.*struct net_if __aligned\(32\)
+^[- \t]*\^
+#
+# include/net/net_mgmt.h
+#
+^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*net_mgmt_event_callback.__unnamed__
+^[- \t]*\^
+#
+# include/net/buf.h
+#
+^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*net_buf.__unnamed__
+^[- \t]*\^
+#
+# include/net/ieee802154.h
+#
+^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*ieee802154_req_params.__unnamed__
+^[- \t]*\^
+#
+# Various warning about net_mgmt declarations
+#
+^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Error when parsing function declaration\.
+^If the function has no return type\:
+^[ \t]*Error in declarator or parameters and qualifiers
+^[ \t]*Invalid definition: Expected identifier in nested name\. \[error at [0-9]+\]
+^[ \t]*NET_MGMT_DEFINE_.*?$
+^[- \t]*\^
+#
+^If the function has a return type\:
+^[ \t]*Error in declarator
+^[ \t]*If pointer to member declarator:
+^[ \t]*Invalid definition: Expected identifier in nested name\. \[error at [0-9]+\]
+^[ \t]*NET_MGMT_DEFINE_.*?$
+^[- \t]*\^
+#
+^[ \t]*If declId, parameters, and qualifiers\:
+^[ \t]*Invalid definition: Expected identifier in nested name\. \[error at [0-9]+\]
+^[ \t]*NET_MGMT_DEFINE_.*?$
+^[- \t]*\^
+#
+^[ \t]*If parenthesis in noptr-declarator\:
+^[ \t]*Error in declarator
+^[ \t]*If pointer to member declarator:
+^[ \t]*Invalid definition: Expected identifier in nested name\. \[error at [0-9]+\]
+^[ \t]*NET_MGMT_DEFINE_.*?$
+^[- \t]*\^
+#
+^[ \t]*If parenthesis in noptr-declarator\:
+^[ \t]*Error in declarator or parameters and qualifiers
+^[ \t]*If pointer to member declarator:
+^[ \t]*Invalid definition: Expected \'\:\:\' in pointer to member \(function\)\. \[error at [0-9]+\]
+^[ \t]*NET_MGMT_DEFINE_.*?$
+^[- \t]*\^
+#
+^[ \t]*If declarator-id:
+^[ \t]*Invalid definition: Expecting \"\(\" in parameters_and_qualifiers\. \[error at [0-9]+\]
+^[ \t]*NET_MGMT_DEFINE_.*?$
+^[- \t]*\^

.mailmap

@@ -18,3 +18,4 @@ Keren Siman-Tov <keren.siman-tov@intel.com> <keren.siman-tov@intel.com>
 Naga Raja Rao Tulasi <tulasi.r@tcs.com> <tulasi.r@tcs.com>
 Felipe Neves <ryukokki.felipe@gmail.com> <ryukokki.felipe@gmail.com>
 Amir Kaplan <amir.kaplan@intel.com> <amir.kaplan@intel.com>
+Anas Nashif <anas.nashif@intel.com> <anas.nashif@intel.com>

.shippable.yml

@@ -0,0 +1,132 @@
+language: c
+
+compiler: gcc
+
+env:
+    global:
+        - SDK=0.9.1
+        - SANITYCHECK_OPTIONS=" --inline-logs -R"
+        - SANITYCHECK_OPTIONS_RETRY="${SANITYCHECK_OPTIONS} --only-failed --outdir=out-2nd-pass"
+        - ZEPHYR_SDK_INSTALL_DIR=/opt/sdk/zephyr-sdk-0.9.1
+        - ZEPHYR_GCC_VARIANT=zephyr
+        - USE_CCACHE=1
+        - MATRIX_BUILDS="2"
+        - MATRIX_BUILDS_EXTRA="3"
+    matrix:
+        - MATRIX_BUILD="1"
+        - MATRIX_BUILD="2"
+        - MATRIX_BUILD="3"
+
+build:
+    cache: true
+    cache_dir_list:
+        - ${SHIPPABLE_BUILD_DIR}/ccache
+    pre_ci_boot:
+        image_name: zephyrprojectrtos/ci
+        image_tag: v0.1
+        pull: true
+        options: "-e HOME=/home/buildslave --privileged=true --tty --net=bridge --user buildslave"
+
+    ci:
+      - export CCACHE_DIR=${SHIPPABLE_BUILD_DIR}/ccache/.ccache
+      - >
+        if [ "$IS_PULL_REQUEST" = "true" ]; then
+          git rebase origin/${PULL_REQUEST_BASE_BRANCH};
+        fi
+      - source zephyr-env.sh
+      - ccache -c -s --max-size=2000M
+      - make host-tools
+      - export PREBUILT_HOST_TOOLS=${ZEPHYR_BASE}/bin
+      - >
+          if [ "$MATRIX_BUILD" = "3" -a "$IS_PULL_REQUEST" = "true" ]; then
+            export COMMIT_RANGE=origin/${PULL_REQUEST_BASE_BRANCH}..HEAD
+            echo "Building a Pull Request";
+            echo "- Building Documentation";
+            echo "Commit range:" ${COMMIT_RANGE}
+            make htmldocs > doc.log 2>&1;
+            ./scripts/filter-known-issues.py --config-dir .known-issues/doc/ doc.log > doc.warnings;
+
+            if [ "$?" != 0 ]; then
+              echo " ==> Error running filter script"
+              exit 1
+            fi;
+            if [ -s doc.warnings ]; then
+              echo " => New documentation warnings/errors";
+            fi;
+            echo "- Verify commit message and coding style";
+            ./scripts/ci/check-compliance.py --commits ${COMMIT_RANGE} || true;
+          fi;
+      - >
+          if [ "$IS_PULL_REQUEST" = "true" ]; then
+            ./scripts/ci/get_modified_tests.py --commits origin/${PULL_REQUEST_BASE_BRANCH}..HEAD > modified_tests.args;
+            ./scripts/ci/get_modified_boards.py --commits origin/${PULL_REQUEST_BASE_BRANCH}..HEAD > modified_boards.args;
+
+            if [ -s modified_boards.args ]; then
+              ./scripts/sanitycheck --subset ${MATRIX_BUILD}/${MATRIX_BUILDS_EXTRA} +modified_boards.args || ./scripts/sanitycheck +modified_boards.args --only-failed;
+              cp ./scripts/sanity_chk/last_sanity.xml modified_boards.xml;
+            fi;
+            if [ -s modified_tests.args ]; then
+              ./scripts/sanitycheck --subset ${MATRIX_BUILD}/${MATRIX_BUILDS_EXTRA} +modified_tests.args || ./scripts/sanitycheck +modified_tests.args --only-failed;
+              cp ./scripts/sanity_chk/last_sanity.xml modified_tests.xml;
+            fi;
+            rm -f modified_tests.args modified_boards.args;
+          fi
+      - >
+          if [ "$MATRIX_BUILD" != "3" ]; then
+             ./scripts/sanitycheck ${PLATFORMS} --subset ${MATRIX_BUILD}/${MATRIX_BUILDS} ${COVERAGE} ${SANITYCHECK_OPTIONS} || ./scripts/sanitycheck ${PLATFORMS} ${COVERAGE} ${SANITYCHECK_OPTIONS_RETRY} || ./scripts/sanitycheck ${PLATFORMS} ${COVERAGE} ${SANITYCHECK_OPTIONS_RETRY}
+          fi;
+      - ccache -s
+    on_failure:
+      - rm -rf sanity-out out-2nd-pass
+      - mkdir -p shippable/testresults
+      - >
+          if [ -e compliance.xml ]; then
+            cp compliance.xml shippable/testresults/;
+          fi;
+      - >
+          if [ -e ./scripts/sanity_chk/last_sanity.xml ]; then
+            cp ./scripts/sanity_chk/last_sanity.xml shippable/testresults/;
+          fi;
+      - >
+          if [ -e ./modified_tests.xml ]; then
+            cp ./modified_tests.xml shippable/testresults/;
+          fi;
+    on_success:
+      - rm -rf sanity-out out-2nd-pass
+      - mkdir -p shippable/testresults
+      - >
+          if [ -e compliance.xml ]; then
+            cp compliance.xml shippable/testresults/;
+          fi;
+      - >
+          if [ -e ./scripts/sanity_chk/last_sanity.xml ]; then
+            cp ./scripts/sanity_chk/last_sanity.xml shippable/testresults/;
+          fi;
+      - >
+          if [ -e ./modified_tests.xml ]; then
+            cp ./modified_tests.xml shippable/testresults/;
+          fi;
+
+integrations:
+  notifications:
+    - integrationName: slack_integration
+      type: slack
+      recipients:
+        - "#ci"
+      branches:
+        only:
+          - master
+      on_success: never
+      on_failure: always
+    - integrationName: email
+      type: email
+      recipients:
+        - builds@zephyrproject.org
+      branches:
+        only:
+          - master
+          - net
+          - bluetooth
+          - arm
+      on_success: never
+      on_failure: never

CODEOWNERS

@@ -0,0 +1,177 @@
+# CODEOWNERS for autoreview assigning in github
+
+# Do not use wildcard on all source yet
+# *                                        @galak @nashif
+
+# Get all docs reviewed
+*.rst                                    @dbkinder
+.known-issues/*                          @inakypg @nashif
+MAINTAINERS                              @inakypg @nashif
+arch/arc/*                               @cjordan44 @ruuddw
+arch/arc/core/*                          @andrewboie
+arch/arm/*                               @MaureenHelm @galak
+arch/arm/core/*                          @andrewboie
+arch/arm/soc/arm/mps2/*                  @fvincenzo
+arch/arm/soc/st_stm32/*                  @erwango
+arch/arm/soc/st_stm32/stm32f4/*          @rsalveti @idlethread
+arch/arm/soc/ti_simplelink/cc32xx        @GAnthony
+arch/nios2/*                             @andrewboie
+arch/nios2/core/*                        @andrewboie
+arch/riscv32                             @fractalclone
+arch/x86/*                               @andrewboie @youvedeep
+arch/x86/core/*                          @andrewboie
+arch/x86/core/crt0.S                     @youvedeep @nashif
+arch/x86/soc/intel_quark/quark_d2000/*   @nashif
+arch/x86/soc/intel_quark/quark_se/*      @nashif
+arch/x86/soc/intel_quark/quark_x1000/*   @nashif
+arch/xtensa/*                            @andrewboie
+boards/arc/*                             @cjordan44 @ruuddw
+boards/arc/arduino_101_sss/*             @nashif
+boards/arc/em_starterkit/*               @cjordan44
+boards/arc/quark_se_c1000_ss_devboard/*  @nashif
+boards/arm/*                             @MaureenHelm @galak
+boards/arm/96b_carbon/*                  @rsalveti @idlethread
+boards/arm/96b_nitrogen/*                @idlethread
+boards/arm/arduino_101_ble/*             @jhedberg
+boards/arm/cc3220sf_launchxl/*           @GAnthony
+boards/arm/disco_l475_iot1/*             @erwango
+boards/arm/frdm_k64f/*                   @MaureenHelm
+boards/arm/frdm_kw41z/*                  @MaureenHelm
+boards/arm/hexiwear_k64/*                @MaureenHelm
+boards/arm/mps2_an385/*                  @fvincenzo
+boards/arm/nrf51_blenano/*               @rsalveti
+boards/arm/nrf52_pca10040/*              @carlescufi
+boards/arm/nucleo_f401re/*               @rsalveti @idlethread
+boards/arm/v2m_beetle/*                  @fvincenzo
+boards/arm/olimexino_stm32/*             @ydamigos
+boards/arm/stm32f3_disco/*               @ydamigos
+boards/nios2/*                           @andrewboie
+boards/nios2/altera_max10/*              @andrewboie
+boards/riscv32                           @fractalclone
+boards/x86/*                             @andrewboie @youvedeep
+boards/x86/arduino_101/*                 @nashif
+boards/x86/galileo/*                     @nashif
+boards/x86/quark_d2000_crb/*             @nashif
+boards/x86/quark_se_c1000_devboard/*     @nashif
+boards/xtensa/*                          @andrewboie
+doc/*                                    @dbkinder
+doc/subsystems/bluetooth/*               @sjanc @jhedberg @Vudentz
+drivers/*/*qmsi*                         @nashif
+drivers/*/*stm32*                        @erwango
+drivers/bluetooth/*                      @sjanc @jhedberg @Vudentz
+drivers/clock_control/*stm32f4*          @rsalveti @idlethread
+drivers/ethernet/*                       @jukkar @tbursztyka
+drivers/flash/*                          @nashif
+drivers/gpio/*stm32*                     @rsalveti @idlethread
+drivers/gpio/gpio_pulpino.c              @fractalclone
+drivers/ieee802154/*                     @jukkar @tbursztyka
+drivers/interrupt_controller/*           @andrewboie
+drivers/pinmux/stm32/*                   @rsalveti @idlethread
+drivers/sensor/*                         @bogdan-davidoaia
+drivers/serial/uart_altera_jtag.c        @andrewboie
+drivers/serial/uart_riscv_qemu.c         @fractalclone
+drivers/slip/*                           @jukkar @tbursztyka
+drivers/spi/*                            @tbursztyka
+drivers/spi/spi_ll_stm32.*               @superna9999 @mbolivar
+drivers/timer/altera_avalon_timer.c      @andrewboie
+drivers/timer/pulpino_timer.c            @fractalclone
+drivers/timer/riscv_machine_timer.c      @fractalclone
+drivers/usb                              @youvedeep @andyross
+drivers/i2c/i2c_ll_stm32*                @ldts @ydamigos
+dts/arm/st/*                             @erwango
+ext/fs/*                                 @nashif
+ext/hal/cmsis/*                          @MaureenHelm @galak
+ext/hal/nordic/mdk/*                     @carlescufi
+ext/hal/nxp/mcux/*                       @MaureenHelm
+ext/hal/qmsi/*                           @nashif
+ext/hal/st/stm32cube/*                   @erwango
+ext/lib/crypto/mbedtls/*                 @nashif
+ext/lib/crypto/tinycrypt/*               @lpereira
+include/arch/arc/*                       @cjordan44 @ruuddw
+include/arch/arc/arch.h                  @andrewboie
+include/arch/arc/v2/irq.h                @andrewboie
+include/arch/arm/*                       @MaureenHelm @galak
+include/arch/arm/cortex_m/irq.h          @andrewboie
+include/arch/nios2/*                     @andrewboie
+include/arch/nios2/arch.h                @andrewboie
+include/arch/riscv32                     @fractalclone
+include/arch/x86/*                       @andrewboie @youvedeep
+include/arch/x86/arch.h                  @andrewboie
+include/arch/xtensa/*                    @andrewboie
+include/atomic.h                         @andrewboie @andyross
+include/bluetooth/*                      @sjanc @jhedberg @Vudentz
+include/cache.h                          @andrewboie @andyross
+include/device.h                         @youvedeep @nashif
+include/drivers/bluetooth/*              @sjanc @jhedberg @Vudentz
+include/drivers/ioapic.h                 @andrewboie
+include/drivers/loapic.h                 @andrewboie
+include/drivers/mvic.h                   @andrewboie
+include/fs.h                             @nashif
+include/fs/*                             @nashif
+include/init.h                           @andrewboie @andyross
+include/init.h                           @youvedeep @nashif
+include/irq.h                            @andrewboie
+include/irq.h                            @andrewboie @andyross
+include/irq_offload.h                    @andrewboie @andyross
+include/kernel.h                         @andrewboie @andyross
+include/kernel_version.h                 @andrewboie @andyross
+include/linker/linker-defs.h             @andrewboie @andyross
+include/linker/linker-tool-gcc.h         @andrewboie @andyross
+include/linker/linker-tool.h             @andrewboie @andyross
+include/linker/section_tags.h            @andrewboie @andyross
+include/linker/sections.h                @andrewboie @andyross
+include/misc/*                           @andrewboie @andyross
+include/net/*                            @jukkar @tbursztyka
+include/net/buf.h                        @jukkar @jhedberg @tbursztyka
+include/power.h                          @youvedeep @nashif
+include/sensor.h                         @bogdan-davidoaia
+include/shared_irq.h                     @andrewboie @andyross
+include/spi.h                            @tbursztyka
+include/sw_isr_table.h                   @andrewboie @andyross
+include/sys_clock.h                      @andrewboie @andyross
+include/sys_io.h                         @andrewboie @andyross
+include/toolchain.h                      @andrewboie @andyross
+include/toolchain/*                      @andrewboie @andyross
+include/zephyr.h                         @andrewboie @andyross
+kernel/*                                 @andrewboie @andyross
+kernel/device.c                          @youvedeep @nashif
+kernel/idle.c                            @youvedeep @nashif
+samples/bluetooth/*                      @sjanc @jhedberg @Vudentz
+samples/boards/quark_se_c1000/power*/*   @youvedeep @nashif
+samples/net/*                            @jukkar @tbursztyka
+samples/net/dns_resolve/*                @jukkar @tbursztyka
+samples/net/http_server/*                @jukkar @tbursztyka
+samples/net/lwm2m_client/*               @mike-scott
+samples/net/mbedtls_sslclient/*          @nashif
+samples/net/mqtt_publisher/*             @jukkar @tbursztyka
+samples/net/zoap_client/*                @vcgomes
+samples/net/zoap_server/*                @vcgomes
+samples/sensor/*                         @bogdan-davidoaia
+samples/subsys/usb                       @youvedeep @andyross
+scripts/expr_parser.py                   @andrewboie
+scripts/sanity_chk/*                     @andrewboie
+scripts/sanitycheck                      @andrewboie
+subsys/bluetooth/*                       @sjanc @jhedberg @Vudentz
+subsys/bluetooth/controller/*            @carlescufi @cvinayak
+subsys/fs/*                              @nashif
+subsys/net/buf.c                         @jukkar @jhedberg @tbursztyka
+subsys/net/ip/*                          @jukkar @tbursztyka
+subsys/net/lib/*                         @jukkar @tbursztyka
+subsys/net/lib/dns/*                     @jukkar @tbursztyka
+subsys/net/lib/http/*                    @jukkar @tbursztyka
+subsys/net/lib/lwm2m/*                   @mike-scott
+subsys/net/lib/mqtt/*                    @jukkar @tbursztyka
+subsys/net/lib/zoap/*                    @vcgomes
+subsys/usb                               @youvedeep @andyross
+tests/bluetooth/*                        @sjanc @jhedberg @Vudentz
+tests/crypto/*                           @lpereira
+tests/crypto/mbedtls/*                   @nashif
+tests/drivers/spi/*                      @tbursztyka
+tests/kernel/*                           @andrewboie @andyross
+tests/net/*                              @jukkar @tbursztyka
+tests/net/buf/*                          @jukkar @jhedberg @tbursztyka
+tests/net/lib/*                          @jukkar @tbursztyka
+tests/net/lib/http_header_fields/*       @jukkar @tbursztyka
+tests/net/lib/mqtt_packet/*              @jukkar @tbursztyka
+tests/net/lib/zoap/*                     @vcgomes
+tests/subsys/fs/*                        @nashif

CONTRIBUTING.rst

@@ -0,0 +1,480 @@
+Contribution Guidelines
+#######################
+
+As an open-source project, we welcome and encourage the community to submit
+patches directly to the project.  In our collaborative open source environment,
+standards and methods for submitting changes help reduce the chaos that can result
+from an active development community.
+
+This document explains how to participate in project conversations, log bugs
+and enhancement requests, and submit patches to the project so your patch will
+be accepted quickly in the codebase.
+
+
+Licensing
+*********
+
+Licensing is very important to open source projects. It helps ensure the
+software continues to be available under the terms that the author desired.
+
+.. _Apache 2.0 license:
+   https://github.com/zephyrproject-rtos/zephyr/blob/master/LICENSE
+
+.. _GitHub repo: https://github.com/zephyrproject-rtos/zephyr
+
+Zephyr uses the `Apache 2.0 license`_ (as found in the LICENSE file in the
+project's `GitHub repo`_) to strike a balance between open contribution and
+allowing you to use the software however you would like to. There are some
+imported or reused components of the Zephyr project that use other licensing,
+as described in `Zephyr Licensing`_.
+
+.. _Zephyr Licensing:
+   https://www.zephyrproject.org/doc/LICENSING.html
+
+The license tells you what rights you have as a developer, provided by the
+copyright holder. It is important that the contributor fully understands the
+licensing rights and agrees to them. Sometimes the copyright holder isn't the
+contributor, such as when the contributor is doing work on behalf of a
+company.
+
+.. _DCO:
+
+Developer Certification of Origin (DCO)
+***************************************
+
+To make a good faith effort to ensure licensing criteria are met, the Zephyr
+project requires the Developer Certificate of Origin (DCO) process to be
+followed.
+
+The DCO is an attestation attached to every contribution made by every
+developer. In the commit message of the contribution, (described more fully
+later in this document), the developer simply adds a ``Signed-off-by``
+statement and thereby agrees to the DCO.
+
+When a developer submits a patch, it is a commitment that the contributor has
+the right to submit the patch per the license.  The DCO agreement is shown
+below and at http://developercertificate.org/.
+
+
+.. code-block:: none
+
+    Developer's Certificate of Origin 1.1
+
+    By making a contribution to this project, I certify that:
+
+    (a) The contribution was created in whole or in part by me and I
+        have the right to submit it under the open source license
+        indicated in the file; or
+
+    (b) The contribution is based upon previous work that, to the
+        best of my knowledge, is covered under an appropriate open
+        source license and I have the right under that license to
+        submit that work with modifications, whether created in whole
+        or in part by me, under the same open source license (unless
+        I am permitted to submit under a different license), as
+        Indicated in the file; or
+
+    (c) The contribution was provided directly to me by some other
+        person who certified (a), (b) or (c) and I have not modified
+        it.
+
+    (d) I understand and agree that this project and the contribution
+        are public and that a record of the contribution (including
+        all personal information I submit with it, including my
+        sign-off) is maintained indefinitely and may be redistributed
+        consistent with this project or the open source license(s)
+        involved.
+
+DCO Sign-Off Methods
+====================
+
+The DCO requires a sign-off message in the following format appear on each
+commit in the pull request::
+
+   Signed-off-by: Zephyrus Zephyr <zephyrus@zephyrproject.org>
+
+The DCO text can either be manually added to your commit body, or you can add
+either ``-s`` or ``--signoff`` to your usual Git commit commands. If you forget
+to add the sign-off you can also amend a previous commit with the sign-off by
+running ``git commit --amend -s``. If you've pushed your changes to GitHub
+already you'll need to force push your branch after this with ``git push -f``.
+
+
+Prerequisites
+*************
+
+.. _Zephyr Project website: https://zephyrproject.org
+
+As a contributor, you'll want to be familiar with the Zephyr project, how to
+configure, install, and use it as explained in the `Zephyr Project website`_
+and how to set up your development environment as introduced in the Zephyr
+`Getting Started Guide`_.
+
+.. _Getting Started Guide:
+   https://www.zephyrproject.org/doc/getting_started/getting_started.html
+
+The examples below use a Linux host environment for Zephyr development.
+You should be familiar with common developer tools such as Git and Make, and
+platforms such as GitHub.
+
+If you haven't already done so, you'll need to create a (free) GitHub account
+on http://github.com and have Git tools available on your development system.
+
+Repository layout
+*****************
+
+To clone the main Zephyr Project repository use::
+
+    $ git clone https://github.com/zephyrproject-rtos/zephyr
+
+The Zephyr project directory structure is described in `Source Tree Structure`_
+documentation. In addition to the Zephyr kernel itself, you'll also find the
+sources for technical documentation, sample code, supported board
+configurations, and a collection of subsystem tests.  All of these are
+available for developers to contribute to and enhance.
+
+.. _Source Tree Structure:
+   https://www.zephyrproject.org/doc/kernel/overview/source_tree.html
+
+Pull Requests and Issues
+************************
+
+.. _Zephyr Project Issues: https://jira.zephyrproject.org
+
+.. _open pull requests: https://github.com/zephyrproject-rtos/zephyr/pulls
+
+.. _Zephyr-devel mailing list:
+   https://lists.zephyrproject.org/mailman/listinfo/zephyr-devel
+
+Before starting on a patch, first check in our Jira `Zephyr Project Issues`_
+system to see what's been reported on the issue you'd like to address.  Have a
+conversation on the `Zephyr-devel mailing list`_ (or the #zephyrproject IRC
+channel on freenode.net) to see what others think of your issue (and proposed
+solution).  You may find others that have encountered the issue you're
+finding, or that have similar ideas for changes or additions.  Send a message
+to the `Zephyr-devel mailing list`_ to introduce and discuss your idea with
+the development community.
+
+It's always a good practice to search for existing or related issues before
+submitting your own. When you submit an issue (bug or feature request), the
+triage team will review and comment on the submission, typically within a few
+business days.
+
+You can find all `open pull requests`_ on GitHub and open `Zephyr Project
+Issues`_ in Jira.
+
+Development Tools and Git Setup
+*******************************
+
+Signed-off-by
+=============
+
+The name in the commit message ``Signed-off-by:`` line and your email must
+match the change authorship information. Make sure your *.git/config* is set
+up correctly::
+
+   $ git config --global user.name "David Developer"
+   $ git config --global user.email "david.developer@company.com"
+
+gitlint
+=========
+
+When you submit a pull request to the project, a series of checks are
+performed to verify your commit messages meet the requirements. The same step
+done during the CI process can be performed locally using the the *gitlint*
+command.
+
+Install gitlint and run it locally in your tree and branch where your patches
+have been committed::
+
+     $ sudo pip3 install gitlint
+     $ gitlint
+
+Note, gitlint only checks HEAD (the most recent commit), so you should run it
+after each commit, or use the ``--commits`` option to specify a commit range
+covering all the development patches to be submitted.
+
+sanitycheck
+===========
+
+To verify that your changes did not break any tests or samples, please run the
+``sanitycheck`` script locally before submitting your pull request to GitHub. To
+run the same tests the CI system runs, follow these steps from within your
+local Zephyr source working directory::
+
+    $ source zephyr-env.sh
+    $ make host-tools
+    $ export PREBUILT_HOST_TOOLS=${ZEPHYR_BASE}/bin
+    $ export USE_CCACHE=1
+    $ ./scripts/sanitycheck
+
+The above will execute the basic sanitycheck script, which will run various
+kernel tests using the QEMU emulator.  It will also do some build tests on
+various samples with advanced features that can't run in QEMU.
+
+We highly recommend you run these tests locally to avoid any CI failures.
+Using CCACHE and pre-built host tools is optional, however it speeds up the
+execution time considerably.
+
+
+Coding Style
+************
+
+Use these coding guidelines to ensure that your development complies with the
+project's style and naming conventions.
+
+.. _Linux kernel coding style:
+   https://kernel.org/doc/html/latest/process/coding-style.html
+
+
+In general, follow the `Linux kernel coding style`_, with the
+following exceptions:
+
+* Add braces to every ``if`` and ``else`` body, even for single-line code
+  blocks. Use the ``--ignore BRACES`` flag to make *checkpatch* stop
+  complaining.
+* Use spaces instead of tabs to align comments after declarations, as needed.
+* Use C89-style single line comments, ``/*  */``. The C99-style single line
+  comment, ``//``, is not allowed.
+* Use ``/**  */`` for doxygen comments that need to appear in the documentation.
+
+The Linux kernel GPL-licensed tool ``checkpatch`` is used to check coding
+style conformity. Checkpatch is available in the scripts directory. To invoke
+it when committing code, edit your *.git/hooks/pre-commit* file to contain:
+
+.. code-block:: bash
+
+    #!/bin/sh
+    set -e exec
+    exec git diff --cached | ${ZEPHYR_BASE}/scripts/checkpatch.pl - || true
+
+Contribution Workflow
+*********************
+
+One general practice we encourage, is to make small,
+controlled changes. This practice simplifies review, makes merging and
+rebasing easier, and keeps the change history clear and clean.
+
+When contributing to the Zephyr Project, it is also important you provide as much
+information as you can about your change, update appropriate documentation,
+and test your changes thoroughly before submitting.
+
+The general GitHub workflow used by Zephyr developers uses a combination of
+command line Git commands and browser interaction with GitHub.  As it is with
+Git, there are multiple ways of getting a task done.  We'll describe a typical
+workflow here:
+
+.. _Create a Fork of Zephyr:
+   https://github.com/zephyrproject-rtos/zephyr#fork-destination-box
+
+#. `Create a Fork of Zephyr`_
+   to your personal account on GitHub.  (Click on the fork button in the top
+   right corner of the Zephyr project repo page in GitHub.)
+
+#. On your development computer, clone the fork you just made::
+
+     $ git clone https://github.com/<your github id>/zephyr
+
+   This would be a good time to let Git know about the upstream repo too::
+
+     $ git remote add upstream https://github.com/zephyrproject-rtos/zephyr.git
+
+   and verify the remote repos::
+
+     $ git remote -v
+
+#. Create a topic branch (off of master) for your work (if you're addressing
+   Jira issue, we suggest including the Jira issue number in the branch name)::
+
+     $ git checkout master
+     $ git checkout -b fix_comment_typo
+
+   Some Zephyr subsystems do development work on a separate branch from
+   master so you may need to indicate this in your checkout::
+
+     $ git checkout -b fix_out_of_date_patch origin/net
+
+#. Make changes, test locally, change, test, test again, ...  (Check out the
+   prior chapter on `sanitycheck`_ as well).
+
+#. When things look good, start the pull request process by adding your changed
+   files::
+
+     $ git add [file(s) that changed, add -p if you want to be more specific]
+
+   You can see files that are not yet staged using::
+
+     $ git status
+
+#. Verify changes to be committed look as you expected::
+
+     $ git diff --cached
+
+#. Commit your changes to your local repo::
+
+     $ git commit -s
+
+   The ``-s`` option automatically adds your ``Signed-off-by:`` to your commit
+   message.  Your commit will be rejected without this line that indicates your
+   agreement with the `DCO`_.  See the `Commit Guidelines`_ section for
+   specific guidelines for writing your commit messages.
+
+#. Push your topic branch with your changes to your fork in your personal
+   GitHub account::
+
+     $ git push origin fix_comment_typo
+
+#. In your web browser, go to your forked repo and click on the
+   ``Compare & pull request`` button for the branch you just worked on and
+   you want to open a pull request with.
+
+#. Review the pull request changes, and verify that you are opening a
+   pull request for the appropriate branch. The title and message from your
+   commit message should appear as well.
+
+#. If you're working on a subsystem branch that's not ``master``,
+   you may need to change the intended branch for the pull request
+   here, for example, by changing the base branch from ``master`` to ``net``.
+
+#. GitHub will assign one or more suggested reviewers (based on the
+   CODEOWNERS file in the repo). If you are a project member, you can
+   select additional reviewers now too.
+
+#. Click on the submit button and your pull request is sent and awaits
+   review.  Email will be sent as review comments are made, or you can check
+   on your pull request at https://github.com/zephyrproject-rtos/zephyr/pulls.
+
+#. While you're waiting for your pull request to be accepted and merged, you
+   can create another branch to work on another issue. (Be sure to make your
+   new branch off of master and not the previous branch.)::
+
+     $ git checkout master
+     $ git checkout -b fix_another_issue
+
+   and use the same process described above to work on this new topic branch.
+
+#. If reviewers do request changes to your patch, you can interactively rebase
+   commit(s) to fix review issues.  In your development repo::
+
+     $ git fetch --all
+     $ git rebase --ignore-whitespace upstream/master
+
+   The ``--ignore-whitespace`` option stops ``git apply`` (called by rebase)
+   from changing any whitespace. Continuing::
+
+     $ git rebase -i <offending-commit-id>^
+
+   In the interactive rebase editor, replace ``pick`` with ``edit`` to select
+   a specific commit (if there's more than one in your pull request), or
+   remove the line to delete a commit entirely.  Then edit files to fix the
+   issues in the review.
+
+   As before, inspect and test your changes. When ready, continue the
+   patch submission::
+
+     $ git add [file(s)]
+     $ git rebase --continue
+
+   Update commit comment if needed, and continue::
+
+     $ git push --force origin fix_comment_typo
+
+   By force pushing your update, your original pull request will be updated
+   with your changes so you won't need to resubmit the pull request.
+
+
+Commit Guidelines
+*****************
+
+Changes are submitted as Git commits. Each commit message must contain:
+
+* A short and descriptive subject line that is less than 72 characters,
+  followed by a blank line. The subject line must include a prefix that
+  identifies the subsystem being changed, followed by a colon, and a short
+  title, for example:  ``doc: update wiki references to new site``.
+  (If you're updating an existing file, you can use
+  ``git log <filename>`` to see what developers used as the prefix for
+  previous patches of this file.)
+
+* A change description with your logic or reasoning for the changes, followed
+  by a blank line.
+
+* A Signed-off-by line, ``Signed-off-by: <name> <email>`` typically added
+  automatically by using ``git commit -s``
+
+* If the change address a Jira issue, include a line of the form::
+
+      Jira: ZEP-xxx
+
+
+All changes and topics sent to GitHub must be well-formed, as described above.
+
+Commit Message Body
+===================
+
+When editing the commit message, please briefly explain what your change
+does and why it's needed. A change summary of ``"Fixes stuff"`` will be rejected. An
+empty change summary is only acceptable for trivial changes fully described by
+the commit title (e.g., ``doc: fix misspellings in CONTRIBUTING doc``)
+
+The description body of the commit message must include:
+
+* **what** the change does,
+* **why** you chose that approach,
+* **what** assumptions were made, and
+* **how** you know it works -- for example, which tests you ran.
+
+For examples of accepted commit messages, you can refer to the Zephyr GitHub
+`changelog <https://github.com/zephyrproject-rtos/zephyr/commits/master>`__.
+
+Other Commit Expectations
+=========================
+
+* Commits must build cleanly when applied on top of each other, thus avoiding
+  breaking bisectability.
+
+* Commits must pass the *scripts/checkpatch.pl* requirements.
+
+* Each commit must address a single identifiable issue and must be
+  logically self-contained. Unrelated changes should be submitted as
+  separate commits.
+
+* You may submit pull request RFCs (requests for comments) to send work
+  proposals, progress snapshots of your work, or to get early feedback on
+  features or changes that will affect multiple areas in the code base.
+
+Identifying Contribution Origin
+===============================
+
+When adding a new file to the tree, it is important to detail the source of
+origin on the file, provide attributions, and detail the intended usage. In
+cases where the file is an original to Zephyr, the commit message should
+include the following ("Original" is the assumption if no Origin tag is
+present)::
+
+    Origin: Original
+
+In cases where the file is imported from an external project, the commit
+message shall contain details regarding the original project, the location of
+the project, the SHA-id of the origin commit for the file, the intended
+purpose, and if the file will be maintained by the Zephyr project,
+(whether or not the Zephyr project will contain a localized branch or if
+it is a downstream copy).
+
+For example, a copy of a locally maintained import::
+
+    Origin: Contiki OS
+    License: BSD 3-Clause
+    URL: http://www.contiki-os.org/
+    commit: 853207acfdc6549b10eb3e44504b1a75ae1ad63a
+    Purpose: Introduction of networking stack.
+    Maintained-by: Zephyr
+
+For example, a copy of an externally maintained import::
+
+    Origin: Tiny Crypt
+    License: BSD 3-Clause
+    URL: https://github.com/01org/tinycrypt
+    commit: 08ded7f21529c39e5133688ffb93a9d0c94e5c6e
+    Purpose: Introduction of TinyCrypt
+    Maintained-by: External

Kbuild

@@ -1,60 +1,5 @@
 # vim: filetype=make
 
-ifneq ("$(wildcard $(MDEF_FILE))","")
-MDEF_FILE_PATH=$(strip $(MDEF_FILE))
-else
-ifneq ($(MDEF_FILE),)
-MDEF_FILE_PATH=$(strip $(PROJECT_BASE)/$(MDEF_FILE))
-endif
-endif
-
-ifeq (${CONFIG_NUM_COMMAND_PACKETS},)
-CONFIG_NUM_COMMAND_PACKETS=0
-endif
-ifeq (${CONFIG_NUM_TIMER_PACKETS},)
-CONFIG_NUM_TIMER_PACKETS=0
-endif
-ifeq (${CONFIG_NUM_TASK_PRIORITIES},)
-CONFIG_NUM_TASK_PRIORITIES=$(CONFIG_NUM_PREEMPT_PRIORITIES)
-endif
-
-ifeq ($(ARCH),x86)
-TASKGROUP_SSE="  TASKGROUP SSE"
-endif
-
-define filechk_prj.mdef
-	(echo "% WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY!"; \
-	echo; \
-	echo "% CONFIG NUM_COMMAND_PACKETS NUM_TIMER_PACKETS NUM_TASK_PRIORITIES"; \
-	echo "% ============================================================="; \
-	echo "  CONFIG ${CONFIG_NUM_COMMAND_PACKETS}             ${CONFIG_NUM_TIMER_PACKETS}               ${CONFIG_NUM_TASK_PRIORITIES}"; \
-	echo; \
-	echo "% TASKGROUP NAME";\
-	echo "% ==============";\
-	echo "  TASKGROUP EXE";\
-	echo "  TASKGROUP SYS";\
-	echo "  TASKGROUP FPU_LEGACY";\
-	echo $(TASKGROUP_SSE);\
-	echo; \
-	if test -e "$(MDEF_FILE_PATH)"; then \
-		cat $(MDEF_FILE_PATH); \
-	fi;)
-endef
-
-misc/generated/sysgen/prj.mdef:	$(MDEF_FILE_PATH) \
-				include/config/auto.conf FORCE
-	$(call filechk,prj.mdef)
-
-sysgen_cmd=$(strip \
-	$(PYTHON) $(srctree)/scripts/sysgen \
-	-i $(CURDIR)/misc/generated/sysgen/prj.mdef \
-	-o $(CURDIR)/misc/generated/sysgen/ \
-)
-
-misc/generated/sysgen/kernel_main.c: misc/generated/sysgen/prj.mdef \
-				     $(srctree)/scripts/sysgen
-	$(Q)$(sysgen_cmd)
-
 define filechk_configs.c
 	(echo "/* file is auto-generated, do not modify ! */"; \
 	echo; \
@@ -79,45 +24,33 @@ targets += include/generated/offsets.h
 always := misc/generated/configs.c
 always += include/generated/offsets.h
 
-ifeq ($(CONFIG_MDEF),y)
-targets += misc/generated/sysgen/kernel_main.c
-always += misc/generated/sysgen/kernel_main.c
-endif
-
 define rule_cc_o_c_1
 	$(call echo-cmd,cc_o_c_1) $(cmd_cc_o_c_1);
 endef
 
-OFFSETS_INCLUDE = $(strip \
-		-include $(CURDIR)/include/generated/autoconf.h \
-		-I $(srctree)/include \
-		-I $(CURDIR)/include/generated \
-		-I $(srctree)/kernel/unified/include \
-		$(OFFSETS_INCLUDE_KERNEL_LOCATION) \
-		-I $(srctree)/lib/libc/minimal/include \
-		-I $(srctree)/arch/${ARCH}/include )
+cmd_cc_o_c_1 = $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(ZEPHYRINCLUDE) -c -o $@ $<
 
-cmd_cc_o_c_1 = $(CC) $(KBUILD_CFLAGS) $(OFFSETS_INCLUDE) -c -o $@ $<
-
-arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c $(KCONFIG_CONFIG)
+arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c $(KCONFIG_CONFIG) \
+				include/generated/generated_dts_board.h
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed,cc_o_c_1)
 
 
 define offsetchk
-	$(Q)set -e;                             \
-	$(kecho) '  CHK     $@';                \
-	mkdir -p $(dir $@);                     \
-	$(GENOFFSET_H) -i $(1) -o $@.tmp;       \
-	if [ -r $@ ] && cmp -s $@ $@.tmp; then  \
-	rm -f $@.tmp;                           \
-	else                                    \
-	$(kecho) '  UPD     $@';                \
-	mv -f $@.tmp $@;                        \
+	$(Q)set -e;                                                \
+	$(kecho) '  CHK     $@';                                   \
+	mkdir -p $(dir $@);                                        \
+	$(srctree)/scripts/gen_offset_header.py -i $(1) -o $@.tmp; \
+	if [ -r $@ ] && cmp -s $@ $@.tmp; then                     \
+	rm -f $@.tmp;                                              \
+	else                                                       \
+	$(kecho) '  UPD     $@';                                   \
+	mv -f $@.tmp $@;                                           \
 	fi
 endef
 
 include/generated/offsets.h: arch/$(ARCH)/core/offsets/offsets.o \
-					include/config/auto.conf FORCE
+			     include/config/auto.conf FORCE
 	$(call offsetchk,arch/$(ARCH)/core/offsets/offsets.o)
 
+

Kconfig

@@ -3,17 +3,7 @@
 #
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 mainmenu "Zephyr Kernel Configuration"
 

Kconfig.zephyr

@@ -4,17 +4,7 @@
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # Copyright (c) 2016 Intel Corporation
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 config KERNELVERSION
 	string
@@ -24,6 +14,8 @@ source "arch/Kconfig"
 
 source "kernel/Kconfig"
 
+source "dts/Kconfig"
+
 source "drivers/Kconfig"
 
 source "net/Kconfig"

LICENSING.rst

@@ -1,66 +0,0 @@
-.. _zephyr_licensing:
-
-Licensing of Zephyr Project components
-######################################
-
-The Zephyr kernel tree imports or reuses packages, scripts and other
-files that are not covered by the :download:`Apache License
-<../LICENSE>`. In some places there is no LICENSE file or way to put
-a LICENSE file there, so we describe the licensing in this document.
-
-
-- *kconfig* and *kbuild*
-
-  *Origin:* Linux Kernel
-  *Licensing:* *GPLv2*
-
-- *scripts/{checkpatch.pl,checkstack.pl,get_maintainers.pl,spelling.txt}*
-
-  *Origin:* Linux Kernel
-  *Licensing:* *GPLv2*
-
-- *ext/fs/fat/*
-
-  *Origin:* FatFs is a file system based on the FAT file system specification.  This is
-  provided by ELM Chan http://elm-chan.org/fsw/ff/00index_e.html
-
-  *Licensing*:
-
-    Copyright (C) 2016, ChaN, all right reserved.
-
-    FatFs module is an open source software. Redistribution and use of FatFs in
-    source and binary forms, with or without modification, are permitted provided
-    that the following condition is met:
-
-    1. Redistributions of source code must retain the above copyright notice,
-       this condition and the following disclaimer.
-
-    This software is provided by the copyright holder and contributors "AS IS"
-    and any warranties related to this software are DISCLAIMED.
-    The copyright owner or contributors be NOT LIABLE for any damages caused
-    by use of this software.
-
-- *ext/hal/cmsis/*
-
-  *Origin:* https://github.com/ARM-software/CMSIS.git
-
-  *Licensing*: :download:`CMSIS_END_USER_LICENCE_AGREEMENT <../ext/hal/cmsis/CMSIS_END_USER_LICENCE_AGREEMENT.pdf>`
-
-- *ext/hal/ksdk/*
-
-  *Origin:* http://kex.nxp.com
-
-  *Licensing*: 3-clause BSD (see :download:`source
-  <../ext/hal/ksdk/drivers/fsl_rtc.h>`)
-
-- *ext/hal/nordic/*
-
-  *Origin:*
-
-  *Licensing*: 3-clause BSD (see :download:`source <../ext/hal/nordic/mdk/nrf51.h>`)
-
-- *ext/hal/qmsi/*
-
-  *Origin:* https://github.com/quark-mcu/qmsi/releases
-
-  *Licensing*: 3-clause BSD (see :download:`source <../ext/hal/qmsi/include/qm_common.h>`)

MAINTAINERS

@@ -61,8 +61,7 @@ Maintainers List (try to look for most precise areas first)
 
 ARC ARCHITECTURE
 M:	Ruud Derwig <Ruud.Derwig@synopsys.com>
-M:	Chuck Jordan <Chuck.Jordan@synopsys.com>
-M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+M:	Chuck Jordan <cjordan@synopsys.com>
 S:	Supported
 F:	arch/arc/
 F:	include/arch/arc/
@@ -88,7 +87,7 @@ S:	Supported
 F:	boards/arc/arduino_101_sss/
 
 BOARDS/ARC - EM Starterkit
-M:	Chuck Jordan <Chuck.Jordan@synopsys.com>
+M:	Chuck Jordan <cjordan@synopsys.com>
 S:	Supported
 F:	boards/arc/em_starterkit/
 
@@ -113,16 +112,21 @@ M:	Johan Hedberg <johan.hedberg@intel.com>
 S:	Supported
 F:	boards/arm/arduino_101_ble/
 
-BOARDS/ARM - CC3200 LAUNCHXL
+BOARDS/ARM - CC32XX LAUNCHXL
 M:      Gil Pitney <gil.pitney@linaro.org>
 S:      Supported
-F:      boards/arm/cc3200_launchxl/
+F:      boards/arm/cc3220sf_launchxl/
 
 BOARDS/ARM - NXP FRDM-K64F
 M:	Maureen Helm <maureen.helm@nxp.com>
 S:	Supported
 F:	boards/arm/frdm_k64f/
 
+BOARDS/ARM - NXP FRDM-KW41Z
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	boards/arm/frdm_kw41z/
+
 BOARDS/ARM - NXP Hexiwear
 M:	Maureen Helm <maureen.helm@nxp.com>
 S:	Supported
@@ -167,12 +171,12 @@ F:	boards/x86/galileo/
 BOARDS/X86 - QUARK D2000 Devboard
 M:      Anas Nashif <anas.nashif@intel.com>
 S:	Supported
-F:	boards/x86/quark_d2000/
+F:	boards/x86/quark_d2000_crb/
 
 BOARDS/X86 - QUARK SE C1000 Devboard
 M:      Anas Nashif <anas.nashif@intel.com>
 S:	Supported
-F:	boards/x86/quark_se_c1000/
+F:	boards/x86/quark_se_c1000_devboard/
 
 BLUETOOTH
 M:	Johan Hedberg <johan.hedberg@intel.com>
@@ -182,6 +186,7 @@ S:	Supported
 W:	https://www.zephyrproject.org/doc/subsystems/bluetooth/bluetooth.html
 F:	subsys/bluetooth/
 F:	include/bluetooth/
+F:	include/drivers/bluetooth/
 F:	drivers/bluetooth/
 F:	samples/bluetooth/
 F:	tests/bluetooth/
@@ -193,35 +198,34 @@ M:	Carles Cufi <carles.cufi@nordicsemi.no>
 S:	Supported
 F:	subsys/bluetooth/controller/
 
-CC3200 SDK
+CC32XX SDK
 M:      Gil Pitney <gil.pitney@linaro.org>
 S:      Supported
-F:      ext/hal/cc3200sdk/
+F:      ext/hal/ti/simplelink
 
 CC32XX SOC - TI SIMPLELINK
 M:      Gil Pitney <gil.pitney@linaro.org>
 S:      Supported
-F:      arch/arm/soc/ti_simplelink/
+F:      arch/arm/soc/ti_simplelink/cc32xx
 
 DOCUMENTATION
-M:	Kinder, David <david.b.kinder@intel.com>
-M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
+M:	David Kinder <david.b.kinder@intel.com>
+M:	Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
 S:	Supported
 F:	doc/
+F:	*.rst
 
 FILE SYSTEM
-M:	Ramesh Thomas <ramesh.thomas@intel.com>
-M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+M:	Anas Nashif <anas.nashif@intel.com>
 S:	Supported
 F:	ext/fs/
 F:	subsys/fs/
 F:	include/fs/
 F:	include/fs.h
-F:	samples/fs/
+F:	tests/subsys/fs
 
 FLASH DRIVER
-M:	Baohong Liu <baohong.liu@intel.com>
-M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+M:	Anas Nashif <anas.nashif@intel.com>
 S:	Supported
 F:	drivers/flash/
 
@@ -244,13 +248,10 @@ F:	include/drivers/ioapic.h
 F:	include/drivers/mvic.h
 
 KERNEL CORE
-M:	Benjamin Walsh <benjamin.walsh@windriver.com>
-M:	Allan Stephens <allan.stephens@windriver.com>
+M:	Andrew Boie <andrew.p.boie@intel.com>
+M:	Andy Ross <andrew.j.ross@intel.com>
 S:	Supported
 F:	kernel/
-F:	include/nanokernel.h
-F:	include/microkernel.h
-F:	include/microkernel/
 F:	include/misc/
 F:	include/toolchain/
 F:	include/atomic.h
@@ -259,68 +260,90 @@ F:	include/init.h
 F:	include/irq.h
 F:	include/irq_offload.h
 F:	include/kernel_version.h
-F:	include/linker-defs.h
-F:	include/linker-tool-gcc.h
-F:	include/linker-tool.h
-F:	include/section_tags.h
-F:	include/sections.h
+F:	include/linker/linker-defs.h
+F:	include/linker/linker-tool-gcc.h
+F:	include/linker/linker-tool.h
+F:	include/linker/section_tags.h
+F:	include/linker/sections.h
 F:	include/shared_irq.h
 F:	include/sw_isr_table.h
 F:	include/sys_clock.h
 F:	include/sys_io.h
 F:	include/toolchain.h
 F:	include/zephyr.h
-
-KINETIS SOFTWARE DEVELOPMENT KIT (KSDK)
-M:	Maureen Helm <maureen.helm@nxp.com>
-S:	Supported
-F:	ext/hal/ksdk/
+F:	include/kernel.h
+F:	tests/kernel/
 
 KNOWN ISSUES
 M:	Anas Nashif <anas.nashif@intel.com>
 M:	Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
-M:	Javier B Perez <javier.b.perez.hernandez@intel.com>
 F:	.known-issues/
 
+LWM2M
+M:	Michael Scott <michael.scott@linaro.org>
+S:	Supported
+F:	subsys/net/lib/lwm2m/
+F:	samples/net/lwm2m_client/
 
 MAINTAINERS
-M:	Javier B Perez <javier.b.perez.hernandez@intel.com>
 M:	Anas Nashif <anas.nashif@intel.com>
-M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
+M:	Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
 S:	Supported
 F:	MAINTAINERS
 
 MBEDTLS
-M:	Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
-M:	Jithu Joseph <jithu.joseph@intel.com>
-M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+M:	Anas Nashif <anas.nashif@intel.com>
 S:	Supported
 F:	ext/lib/crypto/mbedtls/
 F:	samples/net/mbedtls_sslclient/
-F:	tests/crypto/test_mbedtls/
+F:	tests/crypto/mbedtls/
+
+MCUXPRESSO SOFTWARE DEVELOPMENT KIT (MCUX)
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	ext/hal/nxp/mcux/
+
+MPS2 - ARM LTD CORTEX-M PROTOTYPING SYSTEM
+M:	Vincenzo Frascino <vincenzo.frascino@linaro.org>
+S:	Supported
+F:	arch/arm/soc/arm/mps2/
+F:	boards/arm/mps2_an385/
 
 NETWORKING
 M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
+M:	Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
 S:	Supported
 W:	https://www.zephyrproject.org/doc/subsystems/networking/networking.html
-F:	net/ip/
+F:	subsys/net/ip/
+F:	subsys/net/lib/
 F:	include/net/
 F:	samples/net/
 F:	tests/net/
+F:	tests/net/lib/
+F:	drivers/ethernet/
+F:	drivers/ieee802154/
+F:	drivers/slip/
 
 NETWORK APPLICATIONS
-M:	Flavio Santes <flavio.santes@intel.com>
+M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
+M:	Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
 S:	Supported
-F:	samples/net/dns_client/
-F:	samples/net/nats_clients/
-F:	samples/net/paho_mqtt_clients/
+F:	subsys/net/lib/dns/
+F:	subsys/net/lib/http/
+F:	subsys/net/lib/mqtt/
+F:	samples/net/dns_resolve/
+F:	samples/net/http_server/
+F:	samples/net/mqtt_publisher/
+F:	tests/net/lib/http_header_fields/
+F:	tests/net/lib/mqtt_packet/
 
 NETWORK BUFFERS
 M:	Johan Hedberg <johan.hedberg@intel.com>
 M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
+M:	Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
 S:	Supported
 W:	https://www.zephyrproject.org/doc/subsystems/networking/buffers.html
-F:	net/buf.c
+F:	subsys/net/buf.c
 F:	include/net/buf.h
 F:	tests/net/buf/
 
@@ -331,7 +354,6 @@ F:	arch/nios2/
 F:	include/arch/nios2/
 F:	drivers/serial/uart_altera_jtag.c
 F:	drivers/timer/altera_avalon_timer.c
-F:	tests/kernel/test_intmath/
 F:	boards/nios2/
 
 NORDIC MDK
@@ -340,16 +362,16 @@ S:	Supported
 F:	ext/hal/nordic/mdk/
 
 POWER MANAGEMENT
-M:	Ramesh Thomas <ramesh.thomas@intel.com>
-M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+M:	Anas Nashif <anas.nashif@intel.com>
+M:	Youvedeep Singh <youvedeep.singh@intel.com>
 S:	Supported
 F:	arch/x86/core/crt0.S
 F:	include/device.h
 F:	include/init.h
 F:	include/power.h
-F:	kernel/microkernel/k_idle.c
-F:	kernel/nanokernel/device.c
-F:	samples/power/
+F:	kernel/idle.c
+F:	kernel/device.c
+F:	samples/boards/quark_se_c1000/power*/
 
 QMSI
 M:	Anas Nashif <anas.nashif@intel.com>
@@ -357,12 +379,9 @@ S:	Supported
 F:	ext/hal/qmsi/
 
 QMSI DRIVERS
-M:	Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
-M:	Baohong Liu <baohong.liu@intel.com>
-M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+M:      Anas Nashif <anas.nashif@intel.com>
 S:	Supported
 F:	drivers/*/*qmsi*
-F:	drivers/*/*/*qmsi*
 
 QUARK D2000 SOC
 M:      Anas Nashif <anas.nashif@intel.com>
@@ -372,20 +391,13 @@ F:	arch/x86/soc/intel_quark/quark_d2000/
 QUARK SE C1000 SOC
 M:      Anas Nashif <anas.nashif@intel.com>
 S:	Supported
-F:	arch/x86/soc/intel_quark/quark_se_c1000/
+F:	arch/x86/soc/intel_quark/quark_se/
 
 QUARK X1000 SOC
 M:      Anas Nashif <anas.nashif@intel.com>
 S:	Supported
 F:	arch/x86/soc/intel_quark/quark_x1000/
 
-RELEASE NOTES
-M:      Anas Nashif <anas.nashif@intel.com>
-M:	Javier B Perez <javier.b.perez.hernandez@intel.com>
-M:	Kinder, David <david.b.kinder@intel.com>
-S:	Supported
-F:	release-notes.rst
-
 SANITYCHECK
 M:	Andrew Boie <andrew.p.boie@intel.com>
 S:	Supported
@@ -394,11 +406,9 @@ F:	scripts/expr_parser.py
 F:	scripts/sanity_chk/
 
 SENSOR DRIVERS
-M:	Bogdan Davidoaia <bogdan.m.davidoaia@intel.com>
-M:	Laurentiu Palcu <laurentiu.palcu@intel.com>
-M:	Murtaza Alexandru <alexandru.murtaza@intel.com>
-M:	Vlad Dogaru <vlad.dogaru@intel.com>
-S:	Supported
+M:	Bogdan Davidoaia <bogdan.davidoaia@gmail.com>
+M:	Murtaza Alexandru <murtaza.alexandru1995@gmail.com>
+S:	Maintained
 W:	https://www.zephyrproject.org/doc/subsystems/sensor.html
 F:	include/sensor.h
 F:	drivers/sensor/
@@ -420,39 +430,64 @@ F:	drivers/clock_control/*stm32f4*
 
 TINYCRYPT
 M:	Constanza Heath <constanza.m.heath@intel.com>
-M:	Flavio Santes <flavio.santes@intel.com>
 S:	Supported
 F:	ext/lib/crypto/tinycrypt/
 F:	tests/crypto/
 
+SPI
+M:	Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
+S:	Supported
+F:	drivers/spi/
+F:	include/spi.h
+F:	tests/drivers/spi/
+
 USB
-M:	Jithu Joseph <jithu.joseph@intel.com>
+M:	Youvedeep Singh <youvedeep.singh@intel.com>
+M:	Andy Ross <andrew.j.ross@intel.com>
 S:	Supported
 F:	subsys/usb
 F:	drivers/usb
-F:	samples/usb
+F:	samples/subsys/usb
 
 X86 ARCH
-M:	Benjamin Walsh <benjamin.walsh@windriver.com>
-M:	Allan Stephens <allan.stephens@windriver.com>
+M:	Andrew Boie <andrew.p.boie@intel.com>
+M:	Youvedeep Singh <youvedeep.singh@intel.com>
 S:	Supported
 F:	arch/x86/
 F:	include/arch/x86/
 F:	boards/x86/
 
+XTENSA ARCH
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	arch/xtensa
+F:	include/arch/xtensa/
+F:	boards/xtensa/
+
+RISCV32 ARCH
+M:	Jean-Paul Etienne <fractalclone@gmail.com>
+S:	Supported
+F:	arch/riscv32
+F:	include/arch/riscv32
+F:	boards/riscv32
+F:	drivers/serial/uart_riscv_qemu.c
+F:	drivers/timer/pulpino_timer.c
+F:	drivers/timer/riscv_machine_timer.c
+F:	drivers/gpio/gpio_pulpino.c
+
 ZOAP
 M:	Vinicius Costa Gomes <vinicius.gomes@intel.com>
 S:	Supported
-F:	lib/iot/zoap/
+F:	subsys/net/lib/zoap/
 F:	samples/net/zoap_client/
 F:	samples/net/zoap_server/
-F:	tests/net/zoap/
+F:	tests/net/lib/zoap/
 
 THE REST
 M:	Anas Nashif <anas.nashif@intel.com>
 M:	Kumar Gala <kumar.gala@linaro.org>
 L:	devel@lists.zephyrproject.com
-T:	git https://gerrit.zephyrproject.org/r/a/zephyr
+T:	git https://github.com/zephyrproject-rtos/zephyr
 S:	Buried alive in reporters
 F:	*
 F:	*/

Makefile

@@ -1,11 +1,11 @@
 VERSION_MAJOR 	   = 1
-VERSION_MINOR 	   = 6
-PATCHLEVEL 	   = 0
+VERSION_MINOR 	   = 9
+PATCHLEVEL 	   = 1
 VERSION_RESERVED   = 0
 EXTRAVERSION       =
 NAME 		   = Zephyr Kernel
 
-export SOURCE_DIR PROJECT MDEF_FILE
+export SOURCE_DIR PROJECT
 
 ifeq ($(MAKECMDGOALS),)
 $(error Invoking make from top-level kernel directory is not supported)
@@ -24,9 +24,14 @@ endif
 MAKEFLAGS += -rR --include-dir=$(CURDIR)
 
 UNAME := $(shell uname)
-ifeq (MINGW, $(findstring MINGW, $(UNAME)))
+ifeq (MSYS, $(findstring MSYS, $(UNAME)))
+DISABLE_TRYRUN=y
+HOST_OS=MSYS
+NATIVE_PWD_OPT=-W
+else ifeq (MINGW, $(findstring MINGW, $(UNAME)))
 HOST_OS=MINGW
 PWD_OPT=-W
+NATIVE_PWD_OPT=-W
 DISABLE_TRYRUN=y
 CPATH ?= $(MIGW_DIR)/include
 LIBRARY_PATH ?= $(MINGW_DIR)/lib
@@ -36,7 +41,7 @@ HOST_OS=Linux
 else ifeq (Darwin, $(findstring Darwin, $(UNAME)))
 HOST_OS=Darwin
 endif
-export HOST_OS
+export HOST_OS NATIVE_PWD_OPT
 
 # Avoid funny character set dependencies
 unexport LC_ALL
@@ -103,11 +108,9 @@ endif
 ifeq ($(KBUILD_VERBOSE),1)
   quiet =
   Q =
-  GENIDT_EXTRA_ARGS = -d
 else
   quiet=quiet_
   Q = @
-  GENIDT_EXTRA_ARGS =
 endif
 
 # If the user is running make -s (silent mode), suppress echoing of
@@ -317,14 +320,14 @@ GDB		= $(CROSS_COMPILE)gdb
 READELF		= $(CROSS_COMPILE)readelf
 AWK		= awk
 ifeq ($(PREBUILT_HOST_TOOLS),)
-GENIDT		= scripts/gen_idt/gen_idt
-GENOFFSET_H	= scripts/gen_offset_header/gen_offset_header
 FIXDEP		= scripts/basic/fixdep
 else
-GENIDT		= $(PREBUILT_HOST_TOOLS)/gen_idt
-GENOFFSET_H	= $(PREBUILT_HOST_TOOLS)/gen_offset_header
+ifneq ($(filter host-tools, $(MAKECMDGOALS)),)
+FIXDEP		= scripts/basic/fixdep
+else
 FIXDEP		= $(PREBUILT_HOST_TOOLS)/fixdep
 endif
+endif
 PERL		= perl
 PYTHON		= python
 CHECK		= sparse
@@ -360,28 +363,30 @@ KERNEL_ELF_NAME = $(KERNEL_NAME).elf
 KERNEL_BIN_NAME = $(KERNEL_NAME).bin
 KERNEL_HEX_NAME = $(KERNEL_NAME).hex
 KERNEL_STAT_NAME = $(KERNEL_NAME).stat
+PREBUILT_KERNEL = $(KERNEL_NAME)_prebuilt.elf
 
 export SOC_FAMILY SOC_SERIES SOC_PATH SOC_NAME BOARD_NAME
 export ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME KERNEL_HEX_NAME
 # Use ZEPHYRINCLUDE when you must reference the include/ directory.
 # Needed to be compatible with the O= option
 ZEPHYRINCLUDE    = \
-		-I$(srctree)/kernel/unified/include \
+		-I$(srctree)/kernel/include \
 		-I$(srctree)/arch/$(ARCH)/include \
 		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH) \
 		-I$(srctree)/boards/$(ARCH)/$(BOARD_NAME) \
 		$(if $(KBUILD_SRC), -I$(srctree)/include) \
 		-I$(srctree)/include \
 		-I$(CURDIR)/include/generated \
-		-I$(CURDIR)/misc/generated/sysgen \
 		$(USERINCLUDE) \
 		$(STDINCLUDE)
 
-KBUILD_CPPFLAGS := -DKERNEL
+KBUILD_CPPFLAGS := -DKERNEL -D__ZEPHYR__=1
 
 KBUILD_CFLAGS   := -c -g -std=c99 \
-		-fno-asynchronous-unwind-tables \
 		-Wall \
+		-Wformat \
+		-Wformat-security \
+		-D_FORTIFY_SOURCE=2 \
 		-Wno-format-zero-length \
 		-Wno-main -ffreestanding
 
@@ -396,7 +401,7 @@ KBUILD_CXXFLAGS   := -c -g -std=c++11 \
 		-ffunction-sections -fdata-sections \
 		-fno-rtti -fno-exceptions
 
-KBUILD_AFLAGS   := -c -g -xassembler-with-cpp
+KBUILD_AFLAGS   := -c -g -xassembler-with-cpp -D_ASMLANGUAGE
 
 LDFLAGS += $(call ld-option,-nostartfiles)
 LDFLAGS += $(call ld-option,-nodefaultlibs)
@@ -409,7 +414,7 @@ exports += VERSION_MAJOR VERSION_MINOR PATCHLEVEL VERSION_RESERVED EXTRAVERSION
 exports += KERNELRELEASE KERNELVERSION
 exports += ARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC CXX
 exports += CPP AR NM STRIP OBJCOPY OBJDUMP GDB
-exports += MAKE AWK INSTALLKERNEL PERL PYTHON GENIDT GENOFFSET_H
+exports += MAKE AWK PERL PYTHON
 exports += HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS
 
 exports += KBUILD_CPPFLAGS NOSTDINC_FLAGS ZEPHYRINCLUDE OBJCOPYFLAGS LDFLAGS
@@ -430,7 +435,9 @@ define filechk_Makefile.export
 	echo "BOARD=$(BOARD)"; \
 	echo; \
 	$(foreach e,$(exports),echo $(e)=$($(e));) echo; \
-	echo "include $(O)/include/config/auto.conf";)
+	echo "include $(O)/include/config/auto.conf"; \
+	echo "include $(O)/include/generated/generated_dts_board.conf"; \
+	echo "-include $(srctree)/boards/$(ARCH)/$(BOARD_NAME)/Makefile.board";)
 endef
 
 # Files to ignore in find ... statements
@@ -449,8 +456,6 @@ PHONY += scripts_basic
 ifeq ($(PREBUILT_HOST_TOOLS),)
 scripts_basic:
 	$(Q)$(MAKE) $(build)=scripts/basic
-	$(Q)$(MAKE) $(build)=scripts/gen_idt
-	$(Q)$(MAKE) $(build)=scripts/gen_offset_header
 else
 scripts_basic:
 endif
@@ -478,7 +483,7 @@ endif
 
 version_h := include/generated/version.h
 
-no-dot-config-targets := pristine distclean clean mrproper help kconfig-help \
+no-dot-config-targets := pristine distclean clean mrproper help kconfig-help host-tools \
 			 cscope gtags TAGS tags help% %docs check% \
 			 $(version_h) headers_% kernelversion %src-pkg
 
@@ -573,6 +578,17 @@ ifeq ($(dot-config),1)
 # oldconfig if changes are detected.
 -include include/config/auto.conf.cmd
 
+# Read in DTS derived configuration, if it exists
+#
+# We check to see if the ARCH is correctly sourced before doing the -include
+# The reason for this is due to implicit rules kicking in to create this file.
+# If this occurs before the above auto.conf is sourced correctly, the build
+# will iterate over the dts conf file 2-3 times before settling down to the
+# correct output.
+ifneq ($(ARCH),)
+-include include/generated/generated_dts_board.conf
+endif
+
 # To avoid any implicit rule to kick in, define an empty command
 $(KCONFIG_CONFIG) include/config/auto.conf.cmd: ;
 
@@ -589,19 +605,29 @@ include/config/auto.conf: ;
 endif # $(dot-config)
 
 # kernel objects are built as a static library
-libs-y := kernel/unified/
-core-y := lib/ misc/ net/ boards/ ext/ subsys/ tests/ arch/
-drivers-y := drivers/
+libs-y := lib/
+core-y := kernel/ drivers/ misc/ boards/ ext/ subsys/ tests/ arch/
 
 ARCH = $(subst $(DQUOTE),,$(CONFIG_ARCH))
 export ARCH
 
+ifeq ($(CONFIG_DEBUG),y)
+KBUILD_CFLAGS_OPTIMIZE := -Og
+else
+KBUILD_CFLAGS_OPTIMIZE := -Os
+endif
+
 ifdef ZEPHYR_GCC_VARIANT
 include $(srctree)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
 else
+ifneq ($(MAKECMDGOALS),htmldocs)
 $(if $(CROSS_COMPILE),, \
      $(error ZEPHYR_GCC_VARIANT is not set. ))
 endif
+endif
+
+# Let Makefile.toolchain adjust optimization level
+KBUILD_CFLAGS += $(KBUILD_CFLAGS_OPTIMIZE)
 
 -include $(srctree)/ext/Makefile
 -include $(srctree)/lib/Makefile
@@ -631,11 +657,10 @@ KBUILD_CFLAGS += $(call cc-option,-fno-reorder-blocks,) \
                  $(call cc-option,-fno-partial-inlining)
 endif
 
-ifeq ($(CONFIG_DEBUG),y)
-KBUILD_CFLAGS  += -Og
-else
-KBUILD_CFLAGS  += -Os
-endif
+# Some GCC variants don't support these
+KBUILD_CFLAGS += $(call cc-option,-fno-asynchronous-unwind-tables,)
+KBUILD_CFLAGS += $(call cc-option,-fno-pie,)
+KBUILD_CFLAGS += $(call cc-option,-fno-pic,)
 
 ifeq ($(CONFIG_STACK_CANARIES),y)
 KBUILD_CFLAGS += $(call cc-option,-fstack-protector-all,)
@@ -643,11 +668,13 @@ else
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector,)
 endif
 
+ifeq ($(CONFIG_OVERRIDE_FRAME_POINTER_DEFAULT),y)
 ifeq ($(CONFIG_OMIT_FRAME_POINTER),y)
 fp_arg := $(call cc-option,-fomit-frame-pointer,)
 else
 fp_arg := $(call cc-option,-fno-omit-frame-pointer,)
 endif
+endif
 KBUILD_CFLAGS += $(fp_arg)
 KBUILD_CXXFLAGS += $(fp_arg)
 
@@ -680,8 +707,10 @@ else
 # Use make W=1 to enable this warning (see scripts/Makefile.build)
 KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable)
 KBUILD_CFLAGS += $(call cc-option,-fno-reorder-functions)
+ifneq (${ZEPHYR_GCC_VARIANT},xcc)
 KBUILD_CFLAGS += $(call cc-option,-fno-defer-pop)
 endif
+endif
 
 # We trigger additional mismatches with less inlining
 ifdef CONFIG_DEBUG_SECTION_MISMATCH
@@ -726,6 +755,7 @@ KBUILD_CFLAGS += $(KCFLAGS)
 
 LINKFLAGPREFIX ?= -Wl,
 LDFLAGS_zephyr += $(LDFLAGS)
+LDFLAGS_zephyr += $(call cc-ldoption,-no-pie)
 LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)-X)
 LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)-N)
 LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)--gc-sections)
@@ -771,8 +801,7 @@ all: $(KERNEL_BIN_NAME) $(KERNEL_STAT_NAME)
 # this default value
 export KBUILD_IMAGE ?= zephyr
 
-zephyr-dirs	:= $(patsubst %/,%,$(filter %/, $(core-y) $(drivers-y) \
-		     $(libs-y)))
+zephyr-dirs	:= $(patsubst %/,%,$(filter %/,$(libs-y) $(core-y)))
 
 # Workaround for some make notdir implementations that require
 # the paramenter not to end in "/".
@@ -783,35 +812,35 @@ zephyr-app-dir-root := $(abspath $(patsubst %, %/.., $(SOURCE_DIR)))
 zephyr-alldirs	:= $(sort $(zephyr-dirs) $(SOURCE_DIR) $(patsubst %/,%,$(filter %/, \
 		     $(core-) $(drivers-) $(libs-) $(app-))))
 
-core-y		:= $(patsubst %/, %/built-in.o, $(core-y))
+core-y		:= $(patsubst %/, %/built-in.o, $(core-y)) kernel/lib.a
 app-y		:= $(patsubst %, %/built-in.o, $(notdir $(zephyr-app-dir-root-name)))
-drivers-y	:= $(patsubst %/, %/built-in.o, $(drivers-y))
-libs-y1		:= $(patsubst %/, %/lib.a, $(libs-y))
-libs-y2		:= $(patsubst %/, %/built-in.o, $(libs-y))
-libs-y		:= $(libs-y1) $(libs-y2)
+libs-y		:= $(patsubst %/, %/built-in.o, $(libs-y))
 
 # core-y must be last here. several arches use .gnu.linkonce magic
 # to register interrupt or exception handlers, and defaults under
 # arch/ (part of core-y) must be linked after drivers or libs.
-export KBUILD_ZEPHYR_MAIN := $(drivers-y) $(libs-y) $(core-y)
 export LDFLAGS_zephyr
 
-zephyr-deps := $(KBUILD_LDS) $(KBUILD_ZEPHYR_MAIN) $(app-y)
+zephyr-deps := $(KBUILD_LDS) $(core-y) $(libs-y) $(app-y)
 
 ALL_LIBS += $(TOOLCHAIN_LIBS)
 export ALL_LIBS
 
 LINK_LIBS := $(foreach l,$(ALL_LIBS), -l$(l))
 
-OUTPUT_FORMAT ?= elf32-i386
-OUTPUT_ARCH ?= i386
-
 quiet_cmd_ar_target = AR      $@
-# Do not put lib.a into libzephyr.a. lib.a files are to be linked separately to
-# the final image
-cmd_ar_target = rm -f $@; $(AR) rcT$(KBUILD_ARFLAGS) $@ \
-	$(filter-out %/lib.a, $(KBUILD_ZEPHYR_MAIN))
-libzephyr.a: $(zephyr-deps)
+      cmd_ar_target = rm -f $@; $(AR) rcT$(KBUILD_ARFLAGS) $@ $^
+
+# Contains all the kernel-space objects except the kernel/lib.a which is
+# linked outside of the --whole-archive directive with different AR
+# parameters to save footprint space for unused kernel subsystems
+libzephyr.a: $(filter-out %/lib.a, $(core-y))
+	$(call cmd,ar_target)
+
+# All application objects and third party libraries which would be considered
+# to not directly be part of the kernel (and hence whose symbols would not
+# be globally marked as supervisor-only in memory protection scenarios)
+libapplication.a: $(app-y) $(libs-y) $(KBUILD_ZEPHYR_APP)
 	$(call cmd,ar_target)
 
 quiet_cmd_create-lnk = LINK    $@
@@ -824,11 +853,10 @@ quiet_cmd_create-lnk = LINK    $@
 	echo "-e __start"; 						 	\
 	echo "$(LINKFLAGPREFIX)--start-group";					\
 	echo "$(LINKFLAGPREFIX)--whole-archive";				\
-	echo "$(KBUILD_ZEPHYR_APP)";						\
-	echo "$(app-y)";							\
+	echo "libapplication.a";						\
 	echo "libzephyr.a";							\
 	echo "$(LINKFLAGPREFIX)--no-whole-archive";         			\
-	echo "$(filter %/lib.a, $(KBUILD_ZEPHYR_MAIN))";			\
+	echo "$(filter %/lib.a, $(core-y))";					\
 	echo "$(objtree)/arch/$(ARCH)/core/offsets/offsets.o"; 			\
 	echo "$(LINKFLAGPREFIX)--end-group"; 					\
 	echo "$(LIB_INCLUDE_DIR) $(LINK_LIBS)";					\
@@ -839,42 +867,16 @@ $(KERNEL_NAME).lnk: $(zephyr-deps)
 
 linker.cmd: $(zephyr-deps)
 	$(Q)$(CC) -x assembler-with-cpp -nostdinc -undef -E -P \
-	$(LDFLAG_LINKERCMD) $(LD_TOOLCHAIN) -I$(srctree)/include \
-	-I$(objtree)/include/generated $(EXTRA_LINKER_CMD_OPT) $(KBUILD_LDS) -o $@
+		$(LDFLAG_LINKERCMD) $(LD_TOOLCHAIN) \
+		-I$(srctree)/include -I$(SOURCE_DIR) \
+		-I$(objtree)/include/generated \
+		$(EXTRA_LINKER_CMD_OPT) $(KBUILD_LDS) -o $@
 
-PREBUILT_KERNEL = $(KERNEL_NAME)_prebuilt.elf
 
-$(PREBUILT_KERNEL): $(zephyr-deps) libzephyr.a $(KBUILD_ZEPHYR_APP) $(app-y) linker.cmd $(KERNEL_NAME).lnk
+$(PREBUILT_KERNEL): $(zephyr-deps) libzephyr.a libapplication.a \
+		linker.cmd $(KERNEL_NAME).lnk
 	$(Q)$(CC) -T linker.cmd @$(KERNEL_NAME).lnk -o $@
 
-quiet_cmd_gen_idt = SIDT    $@
-      cmd_gen_idt =								\
-(										\
-	$(OBJCOPY) -I $(OUTPUT_FORMAT)  -O binary -j intList $< isrList.bin &&	\
-	$(GENIDT) -i isrList.bin -n $(CONFIG_IDT_NUM_VECTORS) -o staticIdt.bin 	\
-		-m irq_int_vector_map.bin					\
-		-l $(CONFIG_MAX_IRQ_LINES) $(GENIDT_EXTRA_ARGS) &&		\
-	$(OBJCOPY) -I binary -B $(OUTPUT_ARCH) -O $(OUTPUT_FORMAT) 		\
-		--rename-section .data=staticIdt staticIdt.bin staticIdt.o &&	\
-	$(OBJCOPY) -I binary -B $(OUTPUT_ARCH) -O $(OUTPUT_FORMAT) 		\
-	--rename-section .data=irq_int_vector_map irq_int_vector_map.bin 	\
-		irq_int_vector_map.o &&						\
-	rm staticIdt.bin irq_int_vector_map.bin isrList.bin			\
-)
-
-staticIdt.o: $(PREBUILT_KERNEL)
-	$(call cmd,gen_idt)
-
-quiet_cmd_lnk_elf = LINK    $@
-      cmd_lnk_elf =									\
-(											\
-	$(CC) -T linker.cmd @$(KERNEL_NAME).lnk staticIdt.o				\
-		irq_int_vector_map.o -o $@;						\
-	${OBJCOPY} --change-section-address intList=${CONFIG_PHYS_LOAD_ADDR} $@ elf.tmp;\
-	$(OBJCOPY) -R intList elf.tmp $@;						\
-	rm elf.tmp									\
-)
-
 ASSERT_WARNING_STR := \
     "\n      ------------------------------------------------------------" \
     "\n      --- WARNING:  __ASSERT() statements are globally ENABLED ---" \
@@ -892,14 +894,45 @@ WARN_ABOUT_DEPRECATION := $(if $(CONFIG_BOARD_DEPRECATED),echo -e \
 				-n $(DEPRECATION_WARNING_STR),true)
 
 ifeq ($(ARCH),x86)
-$(KERNEL_ELF_NAME): staticIdt.o linker.cmd
-	$(call cmd,lnk_elf)
-	@$(srctree)/scripts/check_link_map.py $(KERNEL_NAME).map
+include $(srctree)/arch/x86/Makefile.idt
+ifeq ($(CONFIG_X86_MMU),y)
+include $(srctree)/arch/x86/Makefile.mmu
+endif
+ifeq ($(CONFIG_GDT_DYNAMIC),y)
+include $(srctree)/arch/x86/Makefile.gdt
+endif
+endif
+
+ifeq ($(CONFIG_GEN_ISR_TABLES),y)
+include $(srctree)/arch/common/Makefile.gen_isr_tables
+endif
+
+ifneq ($(GENERATED_KERNEL_OBJECT_FILES),)
+
+# Identical rule to linker.cmd, but we also define preprocessor LINKER_PASS2.
+# For arches that place special metadata in $(PREBUILT_KERNEL) not intended
+# for the final binary, it can be #ifndef'd around this.
+linker-pass2.cmd: $(zephyr-deps)
+	$(Q)$(CC) -x assembler-with-cpp -nostdinc -undef -E -P \
+		-DLINKER_PASS2 \
+		$(LDFLAG_LINKERCMD) $(LD_TOOLCHAIN) \
+		-I$(srctree)/include -I$(SOURCE_DIR) \
+		-I$(objtree)/include/generated \
+		$(EXTRA_LINKER_CMD_OPT) $(KBUILD_LDS) -o $@
+
+$(KERNEL_ELF_NAME): $(GENERATED_KERNEL_OBJECT_FILES) linker-pass2.cmd
+	$(Q)$(CC) -T linker-pass2.cmd $(GENERATED_KERNEL_OBJECT_FILES) \
+		@$(KERNEL_NAME).lnk -o $@
+	$(Q)$(srctree)/scripts/check_link_map.py $(KERNEL_NAME).map
 	@$(WARN_ABOUT_ASSERT)
 	@$(WARN_ABOUT_DEPRECATION)
-else
+
+else # GENERATED_KERNEL_OBJECT_FILES
+
+# Otherwise, nothing to do, prebuilt kernel is the real one
 $(KERNEL_ELF_NAME): $(PREBUILT_KERNEL)
-	@cp $(PREBUILT_KERNEL) $(KERNEL_ELF_NAME)
+	$(Q)cp $(PREBUILT_KERNEL) $(KERNEL_ELF_NAME)
+	$(Q)$(srctree)/scripts/check_link_map.py $(KERNEL_NAME).map
 	@$(WARN_ABOUT_ASSERT)
 	@$(WARN_ABOUT_DEPRECATION)
 endif
@@ -935,6 +968,62 @@ rom_report: $(KERNEL_STAT_NAME)
 
 zephyr: $(zephyr-deps) $(KERNEL_BIN_NAME)
 
+ifeq ($(CONFIG_HAS_DTS),y)
+define filechk_generated_dts_board.h
+	(echo "/* WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY! */"; \
+		if test -e $(ZEPHYR_BASE)/dts/$(ARCH)/$(BOARD_NAME).fixup; then \
+			$(ZEPHYR_BASE)/scripts/extract_dts_includes.py \
+				-d dts/$(ARCH)/$(BOARD_NAME).dts_compiled \
+				-y $(ZEPHYR_BASE)/dts/$(ARCH)/yaml \
+				-f $(ZEPHYR_BASE)/dts/$(ARCH)/$(BOARD_NAME).fixup; \
+		else \
+			$(ZEPHYR_BASE)/scripts/extract_dts_includes.py \
+				-d dts/$(ARCH)/$(BOARD_NAME).dts_compiled \
+				-y $(ZEPHYR_BASE)/dts/$(ARCH)/yaml; \
+		fi; \
+		)
+endef
+define filechk_generated_dts_board.conf
+	(echo "# WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY!"; \
+		$(ZEPHYR_BASE)/scripts/extract_dts_includes.py \
+		-d dts/$(ARCH)/$(BOARD_NAME).dts_compiled \
+		-y $(ZEPHYR_BASE)/dts/$(ARCH)/yaml -k; \
+		)
+endef
+else
+define filechk_generated_dts_board.h
+	(echo "/* WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY! */";)
+endef
+define filechk_generated_dts_board.conf
+	(echo "# WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY!";)
+endef
+endif
+
+include/generated/generated_dts_board.h: include/config/auto.conf FORCE
+ifeq ($(CONFIG_HAS_DTS),y)
+	$(Q)$(MAKE) $(build)=dts/$(ARCH)
+endif
+	$(call filechk,generated_dts_board.h)
+
+include/generated/generated_dts_board.conf: include/config/auto.conf FORCE
+ifeq ($(CONFIG_HAS_DTS),y)
+	$(Q)$(MAKE) $(build)=dts/$(ARCH)
+endif
+	$(call filechk,generated_dts_board.conf)
+
+dts: include/generated/generated_dts_board.h
+
+define filechk_.config-sanitycheck
+	(cat .config; \
+	 grep -e '^CONFIG' include/generated/generated_dts_board.conf | cat; \
+	)
+endef
+
+.config-sanitycheck: include/generated/generated_dts_board.conf FORCE
+	$(call filechk,.config-sanitycheck)
+
+config-sanitycheck: .config-sanitycheck
+
 # The actual objects are generated when descending,
 # make sure no implicit rule kicks in
 $(sort $(zephyr-deps)): $(zephyr-dirs) zephyr-app-dir ;
@@ -992,7 +1081,7 @@ archprepare = $(strip \
 		)
 
 # All the preparing..
-prepare: $(archprepare)  FORCE
+prepare: $(archprepare) dts FORCE
 	$(Q)$(MAKE) $(build)=.
 
 # Generate some files
@@ -1049,17 +1138,16 @@ depend dep:
 # Directories & files removed with 'make clean'
 CLEAN_DIRS  += $(MODVERDIR)
 
-CLEAN_FILES += 	misc/generated/sysgen/kernel_main.c \
-		misc/generated/sysgen/sysgen.h \
-		misc/generated/sysgen/prj.mdef \
-		misc/generated/sysgen/micro_private_types.h \
-		misc/generated/sysgen/kernel_main.h \
+CLEAN_FILES += 	include/generated/generated_dts_board.conf \
+		include/generated/generated_dts_board.h \
+		.config-sanitycheck \
 		.old_version .tmp_System.map .tmp_version \
 		.tmp_* System.map *.lnk *.map *.elf *.lst \
-		*.bin *.hex *.stat *.strip staticIdt.o linker.cmd
+		*.bin *.hex *.stat *.strip staticIdt.o linker.cmd \
+		linker-pass2.cmd
 
 # Directories & files removed with 'make mrproper'
-MRPROPER_DIRS  += include/config usr/include include/generated          \
+MRPROPER_DIRS  += bin include/config usr/include include/generated          \
 		  arch/*/include/generated .tmp_objdiff
 MRPROPER_FILES += .config .config.old .version $(version_h) \
 		  Module.symvers tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
@@ -1130,10 +1218,10 @@ help:
 	@echo  'Other generic targets:'
 	@echo  '  all		  - Build all targets marked with [*]'
 	@echo  '* zephyr	  - Build a zephyr application'
-	@echo  '  qemu		  - Build a zephyr application and run it in qemu'
-	@echo  '  qemugdb         - Same as 'qemu' but start a GDB server on port 1234'
+	@echo  '  run		  - Build a zephyr application and run it if board supports emulation'
 	@echo  '  flash		  - Build and flash an application'
 	@echo  '  debug		  - Build and debug an application using GDB'
+	@echo  '  debugserver	  - Build and start a GDB server (port 1234 for Qemu targets)'
 	@echo  '  ram_report	  - Build and create RAM usage report'
 	@echo  '  rom_report	  - Build and create ROM usage report'
 	@echo  ''
@@ -1185,6 +1273,14 @@ $(help-board-dirs): help-%:
 		echo '')
 
 
+
+host-tools:
+	$(Q)$(MAKE) $(build)=scripts/basic
+	$(Q)$(MAKE) $(build)=scripts/kconfig standalone
+	@mkdir -p ${ZEPHYR_BASE}/bin
+	@cp scripts/basic/fixdep scripts/kconfig/conf ${ZEPHYR_BASE}/bin
+
+
 # Documentation targets
 # ---------------------------------------------------------------------------
 %docs: FORCE
@@ -1233,41 +1329,32 @@ tools/%: FORCE
 	$(Q)mkdir -p $(objtree)/tools
 	$(Q)$(MAKE) LDFLAGS= MAKEFLAGS="$(filter --j% -j,$(MAKEFLAGS))" O=$(objtree) subdir=tools -C $(src)/tools/ $*
 
-QEMU_FLAGS = $(QEMU_FLAGS_$(ARCH)) -pidfile qemu.pid
-
-ifneq ($(QEMU_PTY),)
-    QEMU_FLAGS += -serial pty
-else
-ifneq ($(QEMU_PIPE),)
-    # Send console output to a pipe, used for running automated sanity tests
-    QEMU_FLAGS += -serial pipe:$(QEMU_PIPE)
-else
-    QEMU_FLAGS += -serial mon:stdio
-endif
-endif
-
-qemu: zephyr
-	$(if $(QEMU_PIPE),,@echo "To exit from QEMU enter: 'CTRL+a, x'")
-	@echo '[QEMU] CPU: $(QEMU_CPU_TYPE_$(ARCH))'
-	$(if $(CONFIG_X86_IAMCU),python $(ZEPHYR_BASE)/scripts/qemu-machine-hack.py $(KERNEL_ELF_NAME))
-	$(Q)$(QEMU) $(QEMU_FLAGS) $(QEMU_EXTRA_FLAGS) -kernel $(KERNEL_ELF_NAME)
-
-qemugdb: QEMU_EXTRA_FLAGS += -s -S
-qemugdb: qemu
-
 -include $(srctree)/boards/$(ARCH)/$(BOARD_NAME)/Makefile.board
+
+ifneq ($(EMU_PLATFORM),)
+-include $(srctree)/scripts/Makefile.$(EMU_PLATFORM)
+else
+run:
+	@echo ===================================================
+	@echo Emulation/Simulation not supported with this board.
+	@echo ===================================================
+endif
+
 ifneq ($(FLASH_SCRIPT),)
 flash: zephyr
 	@echo "Flashing $(BOARD_NAME)"
 	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/support/$(FLASH_SCRIPT) flash
-
-debug: zephyr
-	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/support/$(FLASH_SCRIPT) debug
 else
 flash: FORCE
 	@echo Flashing not supported with this board.
 	@echo Please check the documentation for alternate instructions.
+endif
 
+ifneq ($(DEBUG_SCRIPT),)
+debug: zephyr
+	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/support/$(DEBUG_SCRIPT) debug
+
+else
 debug: FORCE
 	@echo Debugging not supported with this board.
 	@echo Please check the documentation for alternate instructions.

Makefile.inc

@@ -42,7 +42,7 @@ $(shell mkdir -p $(O))
 override O := $(realpath $(O))
 endif
 
-export ARCH MDEF_FILE QEMU_EXTRA_FLAGS PROJECT_BASE
+export ARCH QEMU_EXTRA_FLAGS PROJECT_BASE
 
 override CONF_FILE := $(strip $(subst $(DQUOTE),,$(CONF_FILE)))
 
@@ -81,47 +81,48 @@ DOTCONFIG = $(O)/.config
 all: $(DOTCONFIG)
 	$(Q)$(call zephyrmake,$(O),$@)
 
-ifeq ($(findstring qemu_,$(BOARD)),)
-qemu:
-	@echo "Emulation not available for this platform"
-qemugdb: qemu
-else
-qemu: $(DOTCONFIG)
-	$(Q)$(call zephyrmake,$(O),$@)
-qemugdb: $(DOTCONFIG)
-	$(Q)$(call zephyrmake,$(O),$@)
-endif
-
 debug:	$(DOTCONFIG)
 	$(Q)$(call zephyrmake,$(O),$@)
 
 flash: $(DOTCONFIG)
 	$(Q)$(call zephyrmake,$(O),$@)
 
+run: $(DOTCONFIG)
+	$(Q)$(call zephyrmake,$(O),$@)
+
 ifeq ($(MAKECMDGOALS),debugserver)
 ARCH = $(notdir $(subst /$(BOARD),,$(wildcard $(ZEPHYR_BASE)/boards/*/$(BOARD))))
--include $(ZEPHYR_BASE)/boards/$(ARCH)/$(BOARD)/Makefile.board
+BOARD_DIR = $(dir $(wildcard $(ZEPHYR_BASE)/boards/*/*/$(BOARD)_defconfig))
+-include $(BOARD_DIR)/Makefile.board
 -include $(ZEPHYR_BASE)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
 BOARD_NAME = $(BOARD)
 export BOARD_NAME
 endif
+
 debugserver: FORCE
-	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/support/$(FLASH_SCRIPT) debugserver
+	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/support/$(DEBUG_SCRIPT) debugserver
 
-
-initconfig outputexports: $(DOTCONFIG)
+initconfig: $(DOTCONFIG)
 
 $(BOARDCONFIG):
 	@rm -f $(O)/.board_*
 	@touch $@
 
-
 ram_report: initconfig
 	$(Q)$(call zephyrmake,$(O),$@)
 
 rom_report: initconfig
 	$(Q)$(call zephyrmake,$(O),$@)
 
+outputexports: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
+dts: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
+config-sanitycheck: dts
+	$(Q)$(call zephyrmake,$(O),$@)
+
 menuconfig: initconfig
 	$(Q)$(call zephyrmake,$(O),$@)
 
@@ -132,11 +133,9 @@ help:
 %:
 	$(Q)$(call zephyrmake,$(O),$@)
 
-KERNEL_CONFIG = $(ZEPHYR_BASE)/kernel/configs/unified.config
-
 $(DOTCONFIG): $(BOARDCONFIG) $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
 	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/kconfig/merge_config.sh \
-		-q -m -O $(O) $(KBUILD_DEFCONFIG_PATH) $(KERNEL_CONFIG) $(CONF_FILE) \
+		-q -m -O $(O) $(KBUILD_DEFCONFIG_PATH) $(OVERLAY_CONFIG) $(CONF_FILE) \
 			      $(wildcard $(O)/*.conf)
 	$(Q)$(MAKE) $(S) -C $(ZEPHYR_BASE) O=$(O) PROJECT=$(PROJECT_BASE) oldnoconfig
 

Makefile.test

@@ -0,0 +1,4 @@
+
+OVERLAY_CONFIG += $(ZEPHYR_BASE)/tests/include/test.config
+
+include ${ZEPHYR_BASE}/Makefile.inc

README.rst

@@ -0,0 +1,101 @@
+Zephyr Project
+##############
+
+.. raw:: html
+
+   <a href="https://bestpractices.coreinfrastructure.org/projects/74"><img
+   src="https://bestpractices.coreinfrastructure.org/projects/74/badge"></a>
+
+The Zephyr Project is a scalable real-time operating system (RTOS) supporting
+multiple hardware architectures, optimized for resource constrained devices,
+and built with security in mind.
+
+The Zephyr OS is based on a small-footprint kernel designed for use on
+resource-constrained systems: from simple embedded environmental sensors and
+LED wearables to sophisticated smart watches and IoT wireless gateways.
+
+The Zephyr kernel supports multiple architectures, including ARM Cortex-M,
+Intel x86, ARC, NIOS II, Tensilica Xtensa, and RISC V, and a large number of
+`supported boards`_.
+
+.. below included in doc/introduction/introduction.rst
+
+.. start_include_here
+
+Community Support
+*****************
+
+The Zephyr Project Developer Community includes developers from member
+organizations and the general community all joining in the development of
+software within the Zephyr Project. Members contribute and discuss ideas,
+submit bugs and bug fixes, and provide training. They also help those in need
+through the community's forums such as mailing lists and IRC channels. Anyone
+can join the developer community and the community is always willing to help
+its members and the User Community to get the most out of the Zephyr Project.
+
+Welcome to the Zephyr community!
+
+Resources
+*********
+
+Here's a quick summary of resources to find your way around the Zephyr Project
+support systems:
+
+* **Zephyr Project Website**: The https://zephyrproject.org website is the
+  central source of information about the Zephyr Project. On this site, you'll
+  find background and current information about the project as well as all the
+  relevant links to project material.  For a quick start, refer to the
+  `Zephyr Introduction`_ and `Getting Started Guide`_.
+
+* **Releases**: Source code for Zephyr kernel releases are available at
+  https://zephyrproject.org/downloads. On this page,
+  you'll find release information, and links to download or clone source
+  code from our GitHub repository.  You'll also find links for the Zephyr
+  SDK, a moderated collection of tools and libraries used to develop your
+  applications.
+
+* **Source Code in GitHub**: Zephyr Project source code is maintained on a
+  public GitHub repository at https://github.com/zephyrproject-rtos/zephyr.
+  You'll find information about getting access to the repository and how to
+  contribute to the project in this `Contribution Guide`_ document.
+
+* **Samples Code**: In addition to the kernel source code, there are also
+  many documented `Sample and Demo Code Examples`_ that can help show you
+  how to use Zephyr services and subsystems.
+
+* **Documentation**: Extensive Project technical documentation is developed
+  along with the Zephyr kernel itself, and can be found at
+  https://zephyrproject.org/doc.  Additional documentation is maintained in
+  the `Zephyr GitHub wiki`_.
+
+* **Issue Reporting and Tracking**: Requirements and Issue tracking is done in
+  our JIRA system: https://jira.zephyrproject.org. You can browse through the
+  reported issues and submit issues of your own.
+
+* **Security-related Issue Reporting**: For security-related inquiries or
+  reporting suspected security-related bugs in the Zephyr OS, please
+  send email to vulnerabilities@zephyrproject.org.  We will assess and fix
+  flaws according to our security policy outlined in the Zephyr Project
+  `Security Overview`_.
+
+* **Mailing List**: The `Zephyr Mailing Lists`_ are perhaps the most convenient
+  way to track developer discussions and to ask your own support questions to
+  the Zephyr project community.
+  You can also read through message archives to follow
+  past posts and discussions, a good thing to do to discover more about the
+  Zephyr project.
+
+* **IRC Chatting**: You can chat online with the Zephyr project developer
+  community and other users in our IRC channel #zephyrproject on the
+  freenode.net IRC server. You can use the http://webchat.freenode.net web
+  client or use a client-side application such as pidgin.
+
+
+.. _supported boards: https://www.zephyrproject.org/doc/boards/boards.html
+.. _Zephyr Introduction: https://www.zephyrproject.org/doc/introduction/introducing_zephyr.html
+.. _Getting Started Guide: https://www.zephyrproject.org/doc/getting_started/getting_started.html
+.. _Contribution Guide: https://www.zephyrproject.org/doc/contribute/contribute_guidelines.html
+.. _Zephyr GitHub wiki: https://github.com/zephyrproject-rtos/zephyr/wiki
+.. _Zephyr Mailing Lists: https://lists.zephyrproject.org/
+.. _Sample and Demo Code Examples: https://www.zephyrproject.org/doc/samples/samples.html
+.. _Security Overview: https://www.zephyrproject.org/doc/security/security-overview.html

arch/Kconfig

@@ -3,18 +3,9 @@
 #
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # Copyright (c) 2015 Intel Corporation
+# Copyright (c) 2016 Cadence Design Systems, Inc.
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 
 
@@ -30,13 +21,18 @@ config ARM
 
 config X86
 	bool "x86 architecture"
-	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
 	select ATOMIC_OPERATIONS_BUILTIN
 
 config NIOS2
 	bool "Nios II Gen 2 architecture"
 	select ATOMIC_OPERATIONS_C
 
+config RISCV32
+	bool "RISCV32 architecture"
+
+config XTENSA
+	bool "Xtensa architecture"
+
 endchoice
 
 #
@@ -67,6 +63,17 @@ config BOOTLOADER_CONTEXT_RESTORE_SUPPORTED
 	This option signifies that the target has options of bootloaders
 	that support context restore upon resume from deep sleep
 
+config SIMPLE_FATAL_ERROR_HANDLER
+	prompt "Simple system fatal error handler"
+	bool
+	default n
+	default y if !MULTITHREADING
+	help
+	Provides an implementation of _SysFatalErrorHandler() that hard hangs
+	instead of aborting the faulting thread, and does not print anything,
+	for footprint-concerned systems. Only enable this option if you do not
+	want debug capabilities in case of system fatal error.
+
 #
 # End hidden PM feature configs
 #
@@ -101,12 +108,61 @@ config SOC_FAMILY
 config BOARD
 	string
 	help
-	This option holds the name of the board and is used to located the files
+	This option holds the name of the board and is used to locate the files
 	related to the board in the source tree (under boards/).
 	The Board is the first location where we search for a linker.ld file,
 	if not found we look for the linker file in
 	arch/<arch>/soc/<family>/<series>
 
+#
+# Interrupt related configs
+#
+
+config GEN_ISR_TABLES
+	bool
+	prompt "Use generated IRQ tables"
+	default n
+	help
+	This option controls whether a platform uses the gen_isr_tables
+	script to generate its interrupt tables. This mechanism will create
+	an appropriate hardware vector table and/or software IRQ table.
+
+config GEN_IRQ_VECTOR_TABLE
+	bool
+	prompt "Generate an interrupt vector table"
+	default y
+	depends on GEN_ISR_TABLES
+	help
+	This option controls whether a platform using gen_isr_tables
+	needs an interrupt vector table created. Only disable this if the
+	platform does not use a vector table at all, or requires the vector
+	table to be in a format that is not an array of function pointers
+	indexed by IRQ line. In the latter case, the vector table must be
+	supplied by the application or architecture code.
+
+config GEN_SW_ISR_TABLE
+	bool
+	prompt "Generate a software ISR table"
+	default y
+	depends on GEN_ISR_TABLES
+	help
+	This option controls whether a platform using gen_isr_tables
+	needs a software ISR table table created. This is an array of struct
+	_isr_table_entry containing the interrupt service routine and supplied
+	parameter.
+
+config GEN_IRQ_START_VECTOR
+	int
+	default 0
+	depends on GEN_ISR_TABLES
+	help
+	On some architectures, part of the vector table may be reserved for
+	system exceptions and is declared separately from the tables
+	created by gen_isr_tables.py. When creating these tables, this value
+	will be subtracted from CONFIG_NUM_IRQS to properly size them.
+	This is a hidden option which needs to be set per architecture and
+	left alone.
+
 source "arch/*/Kconfig"
 
 source "boards/Kconfig"

arch/Makefile

@@ -1 +1 @@
-obj-y += $(ARCH)/
+obj-y += common/ $(ARCH)/

arch/arc/Kconfig

@@ -3,17 +3,7 @@
 #
 # Copyright (c) 2014 Wind River Systems, Inc.
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 
 choice
@@ -34,6 +24,21 @@ config ARCH_DEFCONFIG
 	string
 	default "arch/arc/defconfig"
 
+config CPU_HAS_MPU
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	help
+	  This option is enabled when the CPU has a Memory Protection Unit (MPU).
+
+config CPU_HAS_FPU
+	# Hidden config selected by CPU family
+	bool
+	default n
+	help
+	This option is enabled when the CPU has hardware floating point
+	unit.
+
 menu "ARC EM4 processor options"
 
 config	CPU_ARCEM4
@@ -51,21 +56,9 @@ menu "ARCv2 Family Options"
 config	CPU_ARCV2
 	bool
 	default y
-	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
 	help
 	  This option signifies the use of a CPU of the ARCv2 family.
 
-config NSIM
-	prompt "Running on the MetaWare nSIM simulator"
-	bool
-	default n
-	help
-	  For running on nSIM simulator.
-
-	  a) Uses non-XIP to run in RAM.
-	  b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
-	     a pc_size of 16 (default).
-
 config	DATA_ENDIANNESS_LITTLE
 	bool
 	default y
@@ -108,20 +101,12 @@ config	RGF_NUM_BANKS
 	register bank, in the set, will be used by FIRQ interrupts.
 	If fast interrupts are supported but there is only 1
 	register bank, the fast interrupt handler must save
-	and restore general purpose regsiters.
-
-config	FIRQ_STACK_SIZE
-	int
-	prompt "Size of stack for FIRQs (in bytes)"
-	depends on CPU_ARCV2
-	default 1024
-	help
-	  FIRQs and regular IRQs have different stacks so that a FIRQ can start
-	  running without doing stack switching in software.
+	and restore general purpose registers.
 
 config	ARC_STACK_CHECKING
 	bool "Enable Stack Checking"
 	depends on CPU_ARCV2
+	select THREAD_STACK_INFO
 	default n
 	help
 	  ARCV2 has a special feature allowing to check stack overflows. This
@@ -155,13 +140,66 @@ config	XIP
 	default n if NSIM
 	default y
 
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_START_VECTOR
+	default 16
+
 config HARVARD
 	prompt "Harvard Architecture"
 	bool
 	default n
 	help
-	  The ARC CPU can be configured to have two busses;
-	  one for instruction fetching and another that serves as a data bus.
+	The ARC CPU can be configured to have two busses;
+	one for instruction fetching and another that serves as a data bus.
+
+config CODE_DENSITY
+	prompt "Code Density Option"
+	bool
+	default n
+	help
+	Enable code density option to get better code density
+
+menu "Floating Point Options"
+depends on CPU_HAS_FPU
+
+config FLOAT
+	bool
+	prompt "Floating point registers"
+	default n
+	help
+	This option allows tasks and fibers to use the floating point registers.
+	By default, only a single task or fiber may use the registers.
+
+	Disabling this option means that any task or fiber that uses a
+	floating point register will get a fatal exception.
+
+config FP_SHARING
+	bool
+	prompt "Floating point register sharing"
+	depends on FLOAT
+	default n
+	help
+	This option allows multiple tasks and fibers to use the floating point
+	registers.
+
+endmenu
+
+menu "ARC MPU Options"
+depends on CPU_HAS_MPU
+
+config ARC_MPU_ENABLE
+	bool "Enable MPU"
+	depends on CPU_HAS_MPU
+	select ARC_MPU
+	default n
+	help
+	  Enable MPU
+
+source "arch/arc/core/mpu/Kconfig"
+
+endmenu
 
 config ICCM_SIZE
 	int "ICCM Size in kB"
@@ -219,56 +257,6 @@ config FLASH_BASE_ADDRESS
 	normally set by the board's defconfig file and the user should generally
 	avoid modifying it via the menu configuration.
 
-config SW_ISR_TABLE
-	bool
-	prompt "Enable software interrupt handler table"
-	default y
-	help
-	  Enable an interrupt handler table implemented in software. This
-	  table, unlike ISRs connected directly in the vector table, allow
-	  a parameter to be passed to the interrupt handlers. Also, invoking
-	  the exeception/interrupt exit stub is automatically done.
-
-config IRQ_VECTOR_TABLE_CUSTOM
-	bool
-	prompt "Projects provide a custom static IRQ part of vector table"
-	depends on !SW_ISR_TABLE
-	default n
-	help
-	  Projects, not the BSP, provide the IRQ part of the vector table.
-
-	  This is the table of interrupt handlers with the best potential
-	  performance, but is the less flexible.
-
-	  The ISRs are installed directly in the vector table, thus are
-	  directly called by the CPU when an interrupt is taken. This adds
-	  the least overhead when handling an interrupt.
-
-	  Downsides:
-
-	  - ISRs cannot have a parameter
-	  - ISRs cannot be connected at runtime
-	  - ISRs must notify the kernel manually by invoking _ExcExit() when
-	    then are about to return.
-
-config	IRQ_VECTOR_TABLE_BSP
-	bool
-	# omit prompt to signify a "hidden" option
-	depends on SW_ISR_TABLE || !IRQ_VECTOR_TABLE_CUSTOM
-	default y
-	help
-	  Not user-selectable, helps build system logic.
-
-config ARCH_HAS_TASK_ABORT
-	bool
-	# omit prompt to signify a "hidden" option
-	default n
-
-config ARCH_HAS_NANO_FIBER_ABORT
-	bool
-	# omit prompt to signify a "hidden" option
-	default n
-
 config CACHE_LINE_SIZE_DETECT
 	bool
 	prompt "Detect d-cache line size at runtime"

arch/arc/Makefile

@@ -1,5 +1,15 @@
+# Enable debug support in mdb
+# Dwarf version 2 can be recognized by mdb
+# The default dwarf version in gdb is not recognized by mdb
+cflags-y += $(call cc-option, -g3 -gdwarf-2)
+
 cflags-y += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
-cflags-$(CONFIG_ARC_STACK_CHECKING) = $(call cc-option,-fomit-frame-pointer)
+
+# Without this (poorly named) option, compiler may generate undefined
+# references to abort().
+# See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63691
+cflags-y += $(call cc-option,-fno-delete-null-pointer-checks)
+
 cflags-$(CONFIG_LTO) = $(call cc-option,-flto,)
 
 include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
@@ -12,4 +22,3 @@ soc-aflags ?= $(soc-cflags)
 KBUILD_CFLAGS += $(soc-cflags)
 KBUILD_CXXFLAGS += $(soc-cxxflags)
 KBUILD_AFLAGS += $(soc-aflags)
-

arch/arc/core/Makefile

@@ -1,10 +1,10 @@
-ccflags-y += -I$(srctree)/kernel/unified/include
+ccflags-y += -I$(srctree)/kernel/include
 ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
 
 obj-y += thread.o thread_entry_wrapper.o \
 	cpu_idle.o  fast_irq.o  fatal.o  fault.o  \
-	fault_s.o  irq_manage.o cache.o  \
-	isr_wrapper.o  regular_irq.o  swap_macros.h  swap.o \
+	fault_s.o  irq_manage.o cache.o timestamp.o  \
+	isr_wrapper.o  regular_irq.o  swap.o \
 	sys_fatal_error_handler.o
 
 obj-y += prep_c.o \
@@ -16,5 +16,5 @@ obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
 # Some ARC cores like the EM4 lack the atomic LLOCK/SCOND and
 # can't use these.
 obj-$(CONFIG_ATOMIC_OPERATIONS_CUSTOM) += atomic.o
-obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
-obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o
+
+obj-$(CONFIG_CPU_HAS_MPU) += mpu/

arch/arc/core/atomic.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -26,10 +16,8 @@
  * where they are not supported on ARC EM family processors.
  */
 
-#define _ASMLANGUAGE
-
 #include <toolchain.h>
-#include <sections.h>
+#include <linker/sections.h>
 
 /* exports */
 

arch/arc/core/cache.c

@@ -3,17 +3,7 @@
 /*
  * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -23,12 +13,12 @@
  * This module contains functions for manipulation of the d-cache.
  */
 
-#include <nanokernel.h>
+#include <kernel.h>
 #include <arch/cpu.h>
 #include <misc/util.h>
 #include <toolchain.h>
 #include <cache.h>
-#include <linker-defs.h>
+#include <linker/linker-defs.h>
 #include <arch/arc/v2/aux_regs.h>
 #include <nano_internal.h>
 #include <misc/__assert.h>
@@ -66,7 +56,7 @@ static int dcache_available(void)
 	return (val == 0)?0:1;
 }
 
-static void dcache_dc_ctrl(uint32_t dcache_en_mask)
+static void dcache_dc_ctrl(u32_t dcache_en_mask)
 {
 	if (!dcache_available())
 		return;
@@ -95,9 +85,9 @@ static void dcache_enable(void)
  *
  * @return N/A
  */
-static void dcache_flush_mlines(uint32_t start_addr, uint32_t size)
+static void dcache_flush_mlines(u32_t start_addr, u32_t size)
 {
-	uint32_t end_addr;
+	u32_t end_addr;
 	unsigned int key;
 
 	if (!dcache_available() || (size == 0)) {
@@ -105,7 +95,7 @@ static void dcache_flush_mlines(uint32_t start_addr, uint32_t size)
 	}
 
 	end_addr = start_addr + size - 1;
-	start_addr &= (uint32_t)(~(DCACHE_LINE_SIZE - 1));
+	start_addr &= (u32_t)(~(DCACHE_LINE_SIZE - 1));
 
 	key = irq_lock(); /* --enter critical section-- */
 
@@ -147,7 +137,7 @@ static void dcache_flush_mlines(uint32_t start_addr, uint32_t size)
 
 void sys_cache_flush(vaddr_t start_addr, size_t size)
 {
-	dcache_flush_mlines((uint32_t)start_addr, (uint32_t)size);
+	dcache_flush_mlines((u32_t)start_addr, (u32_t)size);
 }
 
 
@@ -155,7 +145,7 @@ void sys_cache_flush(vaddr_t start_addr, size_t size)
 size_t sys_cache_line_size;
 static void init_dcache_line_size(void)
 {
-	uint32_t val;
+	u32_t val;
 
 	val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
 	__ASSERT((val&0xff) != 0, "d-cache is not present");

arch/arc/core/cpu_idle.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,19 +11,18 @@
  * CPU power management routines.
  */
 
-#define _ASMLANGUAGE
-
 #include <kernel_structs.h>
 #include <offsets_short.h>
 #include <toolchain.h>
-#include <sections.h>
+#include <linker/sections.h>
 #include <arch/cpu.h>
 
-GTEXT(nano_cpu_idle)
-GTEXT(nano_cpu_atomic_idle)
-GDATA(nano_cpu_sleep_mode)
+GTEXT(k_cpu_idle)
+GTEXT(k_cpu_atomic_idle)
+GDATA(k_cpu_sleep_mode)
 
-SECTION_VAR(BSS, nano_cpu_sleep_mode)
+SECTION_VAR(BSS, k_cpu_sleep_mode)
+	.balign 4
 	.word 0
 
 /*
@@ -44,7 +33,7 @@ SECTION_VAR(BSS, nano_cpu_sleep_mode)
  * void nanCpuIdle(void)
  */
 
-SECTION_FUNC(TEXT, nano_cpu_idle)
+SECTION_FUNC(TEXT, k_cpu_idle)
 
 #ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
 	push_s blink
@@ -52,7 +41,7 @@ SECTION_FUNC(TEXT, nano_cpu_idle)
 	pop_s blink
 #endif
 
-	ld r1, [nano_cpu_sleep_mode]
+	ld r1, [k_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
 	j_s [blink]
@@ -63,9 +52,9 @@ SECTION_FUNC(TEXT, nano_cpu_idle)
  *
  * This function exits with interrupts restored to <key>.
  *
- * void nano_cpu_atomic_idle(unsigned int key)
+ * void k_cpu_atomic_idle(unsigned int key)
  */
-SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
+SECTION_FUNC(TEXT, k_cpu_atomic_idle)
 
 #ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
 	push_s blink
@@ -73,7 +62,7 @@ SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
 	pop_s blink
 #endif
 
-	ld r1, [nano_cpu_sleep_mode]
+	ld r1, [k_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
 	j_s.d [blink]

arch/arc/core/fast_irq.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -23,35 +13,21 @@
  * See isr_wrapper.S for details.
  */
 
-#define _ASMLANGUAGE
-
 #include <kernel_structs.h>
 #include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
-#include "swap_macros.h"
+#include <swap_macros.h>
 
 GTEXT(_firq_enter)
 GTEXT(_firq_exit)
-GTEXT(_firq_stack_setup)
 
-#if CONFIG_RGF_NUM_BANKS != 1
-GDATA(_firq_stack)
-GTEXT(_is_next_thread_current)
-
-SECTION_VAR(NOINIT, _firq_stack)
-	.space CONFIG_FIRQ_STACK_SIZE
-#else
-GDATA(saved_r0)
-#endif
-
-.macro _firq_return
+GDATA(exc_nest_count)
 #if CONFIG_RGF_NUM_BANKS == 1
-	b _firq_no_reschedule
+GDATA(saved_r0)
 #else
-	rtie
+GDATA(saved_sp)
 #endif
-.endm
 
 /**
  *
@@ -76,15 +52,13 @@ GDATA(saved_r0)
  */
 
 SECTION_FUNC(TEXT, _firq_enter)
-
 /*
  * ATTENTION:
  * If CONFIG_RGF_NUM_BANKS>1, firq uses a 2nd register bank so GPRs do
  * not need to be saved.
  * If CONFIG_RGF_NUM_BANKS==1, firq must use the stack to save registers.
- * This has already been done by _isr_enter.
+ * This has already been done by _isr_wrapper.
  */
-
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* disable stack checking */
 	lr r2, [_ARC_V2_STATUS32]
@@ -105,8 +79,41 @@ SECTION_FUNC(TEXT, _firq_enter)
 #endif
 #endif
 
+	ld r1, [exc_nest_count]
+	add r0, r1, 1
+	st r0, [exc_nest_count]
+	cmp r1, 0
+
+	bgt.d  firq_nest
+	mov r0, sp
+
+	mov r1, _kernel
+	ld sp, [r1, _kernel_offset_to_irq_stack]
+#if CONFIG_RGF_NUM_BANKS != 1
+	b firq_nest_1
+firq_nest:
+	mov r1, ilink
+	lr r0, [_ARC_V2_STATUS32]
+	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
+	kflag r0
+
+	st sp, [saved_sp]
+
+	lr ilink, [_ARC_V2_STATUS32]
+	or ilink, ilink, _ARC_V2_STATUS32_RB(1)
+	kflag ilink
+	mov r0, sp
+	ld sp, [saved_sp]
+	mov ilink, r1
+firq_nest_1:
+#else
+firq_nest:
+#endif
+	push_s r0
 	j @_isr_demux
 
+
+
 /**
  *
  * @brief Work to be done exiting a FIRQ
@@ -116,6 +123,8 @@ SECTION_FUNC(TEXT, _firq_enter)
 
 SECTION_FUNC(TEXT, _firq_exit)
 
+	pop sp
+
 #if CONFIG_RGF_NUM_BANKS != 1
 #ifndef CONFIG_FIRQ_NO_LPCC
 	/* restore lp_count, lp_start, lp_end from r23-r25 */
@@ -124,58 +133,35 @@ SECTION_FUNC(TEXT, _firq_exit)
 	sr r25, [_ARC_V2_LP_END]
 #endif
 #endif
+	/* check if we're a nested interrupt: if so, let the interrupted
+	 * interrupt handle the reschedule */
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	cmp	r0, 0
+	bne.d	_firq_no_reschedule
+	st	r0, [r1]
+
+#ifdef CONFIG_PREEMPT_ENABLED
 
 	mov_s r1, _kernel
 	ld_s r2, [r1, _kernel_offset_to_current]
 
-#if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
-	/* check if we're a nested interrupt: if so, let the interrupted
-	 * interrupt handle the reschedule */
-
-	lr r3, [_ARC_V2_AUX_IRQ_ACT]
-
-	/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
-	 * AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is not 1, it
-	 * means that another bit is set so an interrupt was interrupted.
-	 */
-
-	breq r3, 1, _firq_check_for_swap
-
-	_firq_return
-#endif
-
-.balign 4
-_firq_check_for_swap:
-	/* coop thread ? do not schedule */
-	ld_s r0, [r2, _thread_offset_to_prio]
-	brlt r0, 0, _firq_no_reschedule
-
-	/* scheduler locked ? do not schedule */
-	ld_s r0, [r2, _thread_offset_to_sched_locked]
-	brgt r0, 0, _firq_no_reschedule
-
-	/* check if the current thread needs to be rescheduled */
-	push_s r2
-	push_s r1
-	push_s blink
-	jl _is_next_thread_current
-	pop_s blink
-	pop_s r1
-	pop_s r2
-#if CONFIG_RGF_NUM_BANKS != 1
-#ifndef CONFIG_FIRQ_NO_LPCC
 	/*
-	 * restore lp_count, lp_start, lp_end from r23-r25 in case
-	 * _is_next_thread_current() routine used them
+	 * Non-preemptible thread ? Do not schedule (see explanation of
+	 * preempt field in kernel_struct.h).
 	 */
-	mov lp_count,r23
-	sr r24, [_ARC_V2_LP_START]
-	sr r25, [_ARC_V2_LP_END]
-#endif
-#endif
-	breq r0, 0, _firq_reschedule
+	ldh_s r0, [r2, _thread_offset_to_preempt]
+	brhs r0, _NON_PREEMPT_THRESHOLD, _firq_no_reschedule
+
+	/* Check if the current thread (in r2) is the cached thread */
+	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
+	brne r0, r2, _firq_reschedule
+
 	/* fall to no rescheduling */
 
+#endif /* CONFIG_PREEMPT_ENABLED */
+
 .balign 4
 _firq_no_reschedule:
 	/*
@@ -204,11 +190,21 @@ _firq_no_reschedule:
 	sr r0, [_ARC_V2_LP_START]
 	pop_s r0
 	mov lp_count,r0
+#ifdef CONFIG_CODE_DENSITY
+	pop_s r0
+	sr r0, [_ARC_V2_EI_BASE]
+	pop_s r0
+	sr r0, [_ARC_V2_LDI_BASE]
+	pop_s r0
+	sr r0, [_ARC_V2_JLI_BASE]
+#endif
 	ld r0,[saved_r0]
 	add sp,sp,8 /* don't need ilink & status32_po from stack */
 #endif
 	rtie
 
+#ifdef CONFIG_PREEMPT_ENABLED
+
 .balign 4
 _firq_reschedule:
 
@@ -245,26 +241,15 @@ _firq_reschedule:
 
 	st _CAUSE_FIRQ, [r2, _thread_offset_to_relinquish_cause]
 
-	/*
-	 * Save needed registers to callee saved ones. It is faster than
-	 * pushing them to stack. It is possible to do since program has
-	 * just saved them and the calling routine will save them in turn
-	 * if it uses them.
-	 */
-	mov_s r13, blink
-	mov_s r14, r1
-	jl _get_next_ready_thread
-	mov_s blink, r13
-	mov_s r1, r14
-	mov_s r2, r0
+	ld_s r2, [r1, _kernel_offset_to_ready_q_cache]
 	st_s r2, [r1, _kernel_offset_to_current]
 
 #ifdef CONFIG_ARC_STACK_CHECKING
-	/* Use stack top and down registers from restored context */
-	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
-	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld_s r3, [r2, _thread_offset_to_stack_top]
+	/* Use stack top and base registers from restored context */
+	ld r3, [r2, _thread_offset_to_stack_base]
 	sr r3, [_ARC_V2_KSTACK_BASE]
+	ld r3, [r2, _thread_offset_to_stack_top]
+	sr r3, [_ARC_V2_KSTACK_TOP]
 #endif
 	/*
 	 * _load_callee_saved_regs expects incoming thread in r2.
@@ -272,6 +257,13 @@ _firq_reschedule:
 	 */
 	_load_callee_saved_regs
 
+#ifdef CONFIG_MPU_STACK_GUARD
+	push_s r2
+	mov r0, r2
+	bl configure_mpu_stack_guard
+	pop_s r2
+#endif
+
 	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
 
 	breq r3, _CAUSE_RIRQ, _firq_return_from_rirq
@@ -319,32 +311,4 @@ _firq_return_from_firq:
 	/* LP registers are already restored, just switch back to bank 0 */
 	rtie
 
-
-/**
- *
- * @brief Install the FIRQ stack in register bank 1 if CONFIG_RGF_NUM_BANK!=1
- *
- * @return N/A
- */
-
-SECTION_FUNC(TEXT, _firq_stack_setup)
-
-#if CONFIG_RGF_NUM_BANKS != 1
-	lr r0, [_ARC_V2_STATUS32]
-	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
-	or r0, r0, _ARC_V2_STATUS32_RB(1)
-	kflag r0
-
-	mov sp, _firq_stack
-	add sp, sp, CONFIG_FIRQ_STACK_SIZE
-
-	/*
-	 * We have to reload r0 here, because it is bank1 r0 which contains
-	 * garbage, not bank0 r0 containing the previous value of status32.
-	 */
-	lr r0, [_ARC_V2_STATUS32]
-	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
-	kflag r0
-#endif
-
-	j_s [blink]
+#endif /* CONFIG_PREEMPT_ENABLED */

arch/arc/core/fatal.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -26,13 +16,7 @@
 #include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
-
-#ifdef CONFIG_PRINTK
 #include <misc/printk.h>
-#define PR_EXC(...) printk(__VA_ARGS__)
-#else
-#define PR_EXC(...)
-#endif /* CONFIG_PRINTK */
 
 const NANO_ESF _default_esf = {
 	0xdeaddead, /* placeholder */
@@ -40,7 +24,7 @@ const NANO_ESF _default_esf = {
 
 /**
  *
- * @brief Nanokernel fatal error handler
+ * @brief Kernel fatal error handler
  *
  * This routine is called when fatal error conditions are detected by software
  * and is responsible only for reporting the error. Once reported, it then
@@ -57,25 +41,36 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 							const NANO_ESF *pEsf)
 {
 	switch (reason) {
-	case _NANO_ERR_INVALID_TASK_EXIT:
-		PR_EXC("***** Invalid Exit Software Error! *****\n");
+	case _NANO_ERR_HW_EXCEPTION:
 		break;
 
-#if defined(CONFIG_STACK_CANARIES)
+	case _NANO_ERR_INVALID_TASK_EXIT:
+		printk("***** Invalid Exit Software Error! *****\n");
+		break;
+
+#if defined(CONFIG_STACK_CANARIES) || defined(CONFIG_ARC_STACK_CHECKING)
 	case _NANO_ERR_STACK_CHK_FAIL:
-		PR_EXC("***** Stack Check Fail! *****\n");
+		printk("***** Stack Check Fail! *****\n");
 		break;
 #endif
 
 	case _NANO_ERR_ALLOCATION_FAIL:
-		PR_EXC("**** Kernel Allocation Failure! ****\n");
+		printk("**** Kernel Allocation Failure! ****\n");
+		break;
+
+	case _NANO_ERR_KERNEL_OOPS:
+		printk("***** Kernel OOPS! *****\n");
+		break;
+
+	case _NANO_ERR_KERNEL_PANIC:
+		printk("***** Kernel Panic! *****\n");
 		break;
 
 	default:
-		PR_EXC("**** Unknown Fatal Error %d! ****\n", reason);
+		printk("**** Unknown Fatal Error %d! ****\n", reason);
 		break;
 	}
-	PR_EXC("Current thread ID = %p\n"
+	printk("Current thread ID = %p\n"
 	       "Faulting instruction address = 0x%lx\n",
 	       k_current_get(),
 	       _arc_v2_aux_reg_read(_ARC_V2_ERET));

arch/arc/core/fault.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -22,54 +12,12 @@
  */
 
 #include <toolchain.h>
-#include <sections.h>
+#include <linker/sections.h>
 #include <inttypes.h>
 
-#include <nanokernel.h>
+#include <kernel.h>
 #include <kernel_structs.h>
-
-#ifdef CONFIG_PRINTK
 #include <misc/printk.h>
-#define PR_EXC(...) printk(__VA_ARGS__)
-#else
-#define PR_EXC(...)
-#endif /* CONFIG_PRINTK */
-
-#if (CONFIG_FAULT_DUMP > 0)
-#define FAULT_DUMP(esf, fault) _FaultDump(esf, fault)
-#else
-#define FAULT_DUMP(esf, fault) \
-	do {                   \
-		(void) esf;    \
-		(void) fault;  \
-	} while ((0))
-#endif
-
-#if (CONFIG_FAULT_DUMP > 0)
-/*
- * @brief Dump information regarding fault (FAULT_DUMP > 0)
- *
- * Dump information regarding the fault when CONFIG_FAULT_DUMP is set to 1
- * (short form).
- *
- * @return N/A
- */
-void _FaultDump(const NANO_ESF *esf, int fault)
-{
-	ARG_UNUSED(esf);
-#ifdef CONFIG_PRINTK
-	uint32_t exc_addr = _arc_v2_aux_reg_read(_ARC_V2_EFA);
-	uint32_t ecr = _arc_v2_aux_reg_read(_ARC_V2_ECR);
-
-	PR_EXC("Exception vector: 0x%" PRIx32 ", cause code: 0x%" PRIx32
-	       ", parameter 0x%" PRIx32 "\n",
-	       _ARC_V2_ECR_VECTOR(ecr),
-	       _ARC_V2_ECR_CODE(ecr),
-	       _ARC_V2_ECR_PARAMETER(ecr));
-	PR_EXC("Address 0x%" PRIx32 "\n", exc_addr);
-#endif
-}
-#endif /* CONFIG_FAULT_DUMP */
 
 /*
  * @brief Fault handler
@@ -83,9 +31,24 @@ void _FaultDump(const NANO_ESF *esf, int fault)
  */
 void _Fault(void)
 {
-	uint32_t ecr = _arc_v2_aux_reg_read(_ARC_V2_ECR);
+	u32_t vector, code, parameter;
+	u32_t exc_addr = _arc_v2_aux_reg_read(_ARC_V2_EFA);
+	u32_t ecr = _arc_v2_aux_reg_read(_ARC_V2_ECR);
 
-	FAULT_DUMP(&_default_esf, ecr);
+	vector = _ARC_V2_ECR_VECTOR(ecr);
+	code =  _ARC_V2_ECR_CODE(ecr);
+	parameter = _ARC_V2_ECR_PARAMETER(ecr);
 
-	_SysFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, &_default_esf);
+	printk("Exception vector: 0x%x, cause code: 0x%x, parameter 0x%x\n",
+	       vector, code, parameter);
+	printk("Address 0x%x\n", exc_addr);
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* Vector 6 = EV_ProV. Regardless of code, parameter 2 means stack
+	 * check violation
+	 */
+	if (vector == 6 && parameter == 2) {
+		_NanoFatalErrorHandler(_NANO_ERR_STACK_CHK_FAIL, &_default_esf);
+	}
+#endif
+	_NanoFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, &_default_esf);
 }

arch/arc/core/fault_s.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,12 +11,10 @@
  * Fault handlers for ARCv2 processors.
  */
 
-#define _ASMLANGUAGE
-
 #include <toolchain.h>
-#include <sections.h>
+#include <linker/sections.h>
 #include <arch/cpu.h>
-#include "swap_macros.h"
+#include <swap_macros.h>
 
 GTEXT(_Fault)
 
@@ -45,17 +33,7 @@ GTEXT(__ev_div_zero)
 GTEXT(__ev_dc_error)
 GTEXT(__ev_maligned)
 
-SECTION_VAR(BSS, saved_stack_pointer)
-	.word 0
-
-#if CONFIG_RGF_NUM_BANKS == 1
-GDATA(_exception_stack)
-SECTION_VAR(NOINIT, _exception_stack)
-	.space 512
-/* note: QUARK_SE_C1000_SS can't afford 512B */
-#else
-GDATA(_firq_stack)
-#endif
+GDATA(exc_nest_count)
 
 /*
  * @brief Fault handler installed in the fault and reserved vectors
@@ -93,15 +71,6 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 	pop_s r2
 #endif
 
-	st sp, [saved_stack_pointer]
-#if CONFIG_RGF_NUM_BANKS == 1
-	mov_s sp, _exception_stack
-	add sp, sp, 512
-#else
-	mov_s sp, _firq_stack
-	add sp, sp, CONFIG_FIRQ_STACK_SIZE
-#endif
-
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
@@ -110,13 +79,32 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 	lr r0,[_ARC_V2_ERET]
 	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
 
+
+	ld r1, [exc_nest_count]
+	add r0, r1, 1
+	st r0, [exc_nest_count]
+	cmp r1, 0
+
+	bgt.d  exc_nest_handle
+	mov r0, sp
+
+	mov r1, _kernel
+	ld sp, [r1, _kernel_offset_to_irq_stack]
+exc_nest_handle:
+	push_s r0
+
 	jl _Fault
 
+	pop sp
+
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st 	r0, [r1]
+
 	/* if _Fault returns, restore the registers */
 	_pop_irq_stack_frame
 
-	/* now restore the stack */
-	ld sp,[saved_stack_pointer]
 	rtie
 
 #ifdef CONFIG_IRQ_OFFLOAD
@@ -147,63 +135,58 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	lr r0,[_ARC_V2_ERET]
 	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
 
+	ld r1, [exc_nest_count]
+	add r0, r1, 1
+	st r0, [exc_nest_count]
+	cmp r1, 0
+
+	bgt.d  trap_nest_handle
+	mov r0, sp
+
+	mov r1, _kernel
+	ld sp, [r1, _kernel_offset_to_irq_stack]
+trap_nest_handle:
+	push_s r0
+
 	jl _irq_do_offload
 
-	mov_s r1, _kernel
-	ld_s r2, [r1, _kernel_offset_to_current]
+	pop sp
+
 	/* check if we're a nested interrupt: if so, let the
 	 * interrupted interrupt handle the reschedule
 	 */
-	lr r3, [_ARC_V2_AUX_IRQ_ACT]
-	/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
-	 * AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is 0, it
-	 * means trap was taken from outside an interrupt handler.
-	 * But if it was inside, let that handler do the swap.
-	 */
-	breq r3, 0, _trap_check_for_swap
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	cmp	r0, 0
+	beq.d	_trap_check_for_swap
+	st 	r0, [r1]
+
 _trap_return:
 	_pop_irq_stack_frame
 	rtie
 
 .balign 4
 _trap_check_for_swap:
-	/* coop thread ? do not schedule */
-	ld_s r0, [r2, _thread_offset_to_prio]
-	brlt r0, 0, _trap_return
-
-	/* scheduler locked ? do not schedule */
-	ld_s r0, [r2, _thread_offset_to_sched_locked]
-	brgt r0, 0, _trap_return
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+	/*
+	 * Non-preemptible thread ? Do not schedule (see explanation of
+	 * preempt field in kernel_struct.h).
+	 */
+	ldh_s r0, [r2, _thread_offset_to_preempt]
+	brhs r0, _NON_PREEMPT_THRESHOLD, _trap_return
 
 	/* check if the current thread needs to be rescheduled */
-	push_s r2
-	push_s r1
-	push_s blink
-	jl _is_next_thread_current
-	pop_s blink
-	pop_s r1
-	pop_s r2
-	brne r0, 0, _trap_return
+	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
+	breq r0, r2, _trap_return
 
 	_save_callee_saved_regs
 
 	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
 	/* note: Ok to use _CAUSE_RIRQ since everything is saved */
 
-	/*
-	 * Save needed registers to callee saved ones. It is faster than
-	 * pushing registers to stack. It is possible to do since program has
-	 * just saved them and the calling routine will save them in turn
-	 * if it uses them.
-	 */
-	mov_s r13, blink
-	mov_s r14, r0
-	mov_s r15, r1
-	jl _get_next_ready_thread
-	mov_s r2, r0
-	mov_s r1, r15
-	mov_s r0, r14
-	mov_s blink, r13
+	ld_s r2, [r1, _kernel_offset_to_ready_q_cache]
 	st_s r2, [r1, _kernel_offset_to_current]
 
 	/* clear AE bit to forget this was an exception */

arch/arc/core/irq_manage.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -27,11 +17,11 @@
  * number from 16 to last IRQ number on the platform.
  */
 
-#include <nanokernel.h>
+#include <kernel.h>
 #include <arch/cpu.h>
 #include <misc/__assert.h>
 #include <toolchain.h>
-#include <sections.h>
+#include <linker/sections.h>
 #include <sw_isr_table.h>
 #include <irq.h>
 
@@ -84,7 +74,7 @@ void _arch_irq_disable(unsigned int irq)
  * @return N/A
  */
 
-void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
 {
 	ARG_UNUSED(flags);
 

arch/arc/core/irq_offload.c

@@ -1,24 +1,14 @@
 /*
  * Copyright (c) 2015 Intel corporation
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * @file Software interrupts utility code - ARC implementation
  */
 
-#include <nanokernel.h>
+#include <kernel.h>
 #include <irq_offload.h>
 
 static irq_offload_routine_t offload_routine;

arch/arc/core/irq_vector_table.c

@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @brief IRQ part of vector table for Quark SE Sensor Subsystem
- *
- * This file contains the IRQ part of the vector table. It is meant to be used
- * for one of two cases:
- *
- * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
- * binds _IsrWrapper() to all the IRQ entries in the vector table.
- *
- * b) When the BSP is written so that device ISRs are installed directly in the
- * vector table, they are enumerated here.
- *
- */
-
-#include <toolchain.h>
-#include <sections.h>
-
-extern void _isr_enter(void);
-typedef void (*vth)(void); /* Vector Table Handler */
-
-#if defined(CONFIG_SW_ISR_TABLE)
-
-vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS - 16] = {
-	[0 ...(CONFIG_NUM_IRQS - 17)] = _isr_enter
-};
-
-#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
-
-extern void _SpuriousIRQ(void);
-
-/* placeholders: fill with real ISRs */
-
-vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS - 16] = {
-	[0 ...(CONFIG_NUM_IRQS - 17)] = _SpuriousIRQ
-};
-
-#endif /* CONFIG_SW_ISR_TABLE */

arch/arc/core/isr_wrapper.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -23,23 +13,34 @@
  * a parameter.
  */
 
-#define _ASMLANGUAGE
-
 #include <offsets_short.h>
 #include <toolchain.h>
-#include <sections.h>
+#include <linker/sections.h>
 #include <sw_isr_table.h>
 #include <kernel_structs.h>
 #include <arch/cpu.h>
 
-GTEXT(_isr_enter)
+GTEXT(_isr_wrapper)
 GTEXT(_isr_demux)
 
+GDATA(exc_nest_count)
+SECTION_VAR(BSS, exc_nest_count)
+	.balign 4
+	.word 0
+
+
 #if CONFIG_RGF_NUM_BANKS == 1
 GDATA(saved_r0)
 
 SECTION_VAR(BSS, saved_r0)
-        .word 0
+	.balign 4
+	.word 0
+#else
+GDATA(saved_sp)
+
+SECTION_VAR(BSS, saved_sp)
+	.balign 4
+	.word 0
 #endif
 
 #if defined(CONFIG_SYS_POWER_MANAGEMENT)
@@ -52,9 +53,9 @@ _rirq_enter/_firq_enter: they are jump points.
 
 The flow is the following:
 
-ISR -> _isr_enter -- + -> _rirq_enter -> _isr_demux -> ISR -> _rirq_exit
-                     |
-                     + -> _firq_enter -> _isr_demux -> ISR -> _firq_exit
+ISR -> _isr_wrapper -- + -> _rirq_enter -> _isr_demux -> ISR -> _rirq_exit
+                       |
+                       + -> _firq_enter -> _isr_demux -> ISR -> _firq_exit
 
 Context switch explanation:
 
@@ -227,7 +228,7 @@ From RIRQ:
     interrupt.
  */
 
-SECTION_FUNC(TEXT, _isr_enter)
+SECTION_FUNC(TEXT, _isr_wrapper)
 #if CONFIG_RGF_NUM_BANKS == 1
 	st r0,[saved_r0]
 #endif
@@ -241,6 +242,14 @@ SECTION_FUNC(TEXT, _isr_enter)
 	push_s r0
 	mov r0,ilink
 	push_s r0
+#ifdef CONFIG_CODE_DENSITY
+	lr r0, [_ARC_V2_JLI_BASE]
+	push_s r0
+	lr r0, [_ARC_V2_LDI_BASE]
+	push_s r0
+	lr r0, [_ARC_V2_EI_BASE]
+	push_s r0
+#endif
 	mov r0,lp_count
 	push_s r0
 	lr r0, [_ARC_V2_LP_START]
@@ -336,6 +345,7 @@ _skip_sys_power_save_idle_exit:
 SECTION_FUNC(TEXT, _isr_demux)
 	push_s r3
 
+
 	/* cannot be done before this point because we must be able to run C */
 	/* r0 is available to be stomped here, and exit_tickless_idle uses it */
 	exit_tickless_idle
@@ -343,6 +353,12 @@ SECTION_FUNC(TEXT, _isr_demux)
 	log_sleep_k_event
 
 	lr r0, [_ARC_V2_ICAUSE]
+	/* handle software triggered interrupt */
+	lr	r3, [_ARC_V2_AUX_IRQ_HINT]
+	brne	r3, r0, irq_hint_handled
+	sr	0, [_ARC_V2_AUX_IRQ_HINT]
+irq_hint_handled:
+
 	sub r0, r0, 16
 
 	mov r1, _sw_isr_table

arch/arc/core/mpu/Kconfig

@@ -0,0 +1,39 @@
+# Kconfig - Memory Protection Unit (MPU) configuration options
+
+#
+# Copyright (c) 2017 Synopsys
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+config ARC_MPU_VER
+	int
+	prompt "ARC MPU version"
+	range 2 4
+	default 2
+	help
+	ARC MPU has several versions. For MPU v2, the minimum region is 2048 bytes;
+	For MPU v3, the minimum region is 32 bytes
+
+config ARC_CORE_MPU
+	bool "ARC Core MPU functionalities"
+	depends on CPU_HAS_MPU
+	default n
+	help
+	  ARC core MPU functionalities
+
+config MPU_STACK_GUARD
+	bool "Thread Stack Guards"
+	depends on ARC_CORE_MPU && !ARC_STACK_CHECKING
+	select THREAD_STACK_INFO
+	default n
+	help
+	  Enable thread stack guards via MPU. ARC supports built-in stack protection.
+	  If your core supports that, it is preferred over MPU stack guard
+
+config ARC_MPU
+	bool "ARC MPU Support"
+	depends on CPU_HAS_MPU
+	select ARC_CORE_MPU
+	default n
+	help
+	  Target has ARC MPU (currently only works for EMSK 2.2 ARCEM7D)

arch/arc/core/mpu/Makefile

@@ -0,0 +1,2 @@
+obj-$(CONFIG_ARC_CORE_MPU) += arc_core_mpu.o
+obj-$(CONFIG_ARC_MPU) += arc_mpu.o

arch/arc/core/mpu/arc_core_mpu.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2017 Synopsys.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+#include <kernel.h>
+#include <soc.h>
+#include <arch/arc/v2/mpu/arc_core_mpu.h>
+
+#if defined(CONFIG_MPU_STACK_GUARD)
+/*
+ * @brief Configure MPU stack guard
+ *
+ * This function configures per thread stack guards reprogramming the MPU.
+ * The functionality is meant to be used during context switch.
+ *
+ * @param thread thread info data structure.
+ */
+void configure_mpu_stack_guard(struct k_thread *thread)
+{
+	arc_core_mpu_disable();
+	arc_core_mpu_configure(THREAD_STACK_GUARD_REGION,
+			       thread->stack_info.start - STACK_GUARD_SIZE,
+			       thread->stack_info.size);
+	arc_core_mpu_enable();
+}
+#endif

arch/arc/core/mpu/arc_mpu.c

@@ -0,0 +1,242 @@
+/*
+ * Copyright (c) 2017 Synopsys.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+#include <kernel.h>
+#include <soc.h>
+#include <arch/arc/v2/aux_regs.h>
+#include <arch/arc/v2/mpu/arc_mpu.h>
+#include <arch/arc/v2/mpu/arc_core_mpu.h>
+#include <logging/sys_log.h>
+
+
+#define AUX_MPU_RDB_VALID_MASK (0x1)
+#define AUX_MPU_EN_ENABLE   (0x40000000)
+#define AUX_MPU_EN_DISABLE  (0xBFFFFFFF)
+
+#define AUX_MPU_RDP_REGION_SIZE(bits)  \
+			(((bits - 1) & 0x3) | (((bits - 1) & 0x1C) << 7))
+#define AUX_MPU_RDP_ATTR_MASK (0xFFF)
+
+#define _ARC_V2_MPU_EN   (0x409)
+#define _ARC_V2_MPU_RDB0 (0x422)
+#define _ARC_V2_MPU_RDP0 (0x423)
+
+/* For MPU version 2, the minimum protection region size is 2048 bytes */
+/* FOr MPU version 3, the minimum protection region size is 32 bytes */
+#if CONFIG_ARC_MPU_VER == 2
+#define ARC_FEATURE_MPU_ALIGNMENT_BITS 11
+#elif CONFIG_ARC_MPU_VER == 3
+#define ARC_FEATURE_MPU_ALIGNMENT_BITS 5
+#endif
+
+/**
+ * @brief Get the number of supported mpu regions
+ *
+ */
+static inline u8_t _get_num_regions(void)
+{
+	u32_t num = _arc_v2_aux_reg_read(_ARC_V2_MPU_BUILD);
+
+	num = (num & 0xFF00) >> 8;
+
+	return (u8_t)num;
+}
+
+
+/**
+ * This internal function is utilized by the MPU driver to parse the intent
+ * type (i.e. THREAD_STACK_REGION) and return the correct parameter set.
+ */
+static inline u32_t _get_region_attr_by_type(u32_t type, u32_t size)
+{
+	switch (type) {
+	case THREAD_STACK_REGION:
+		return 0;
+	case THREAD_STACK_GUARD_REGION:
+	/* no Read, Write and Execute to guard region */
+		return  AUX_MPU_RDP_REGION_SIZE(
+			ARC_FEATURE_MPU_ALIGNMENT_BITS);
+	default:
+		/* Size 0 region */
+		return 0;
+	}
+}
+
+static inline void _region_init(u32_t index, u32_t region_addr,
+			 u32_t region_attr)
+{
+
+	index = 2 * index;
+
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_RDP0 + index, region_attr);
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_RDB0 + index, region_addr);
+}
+
+
+/* ARC Core MPU Driver API Implementation for ARC MPU */
+
+/**
+ * @brief enable the MPU
+ */
+void arc_core_mpu_enable(void)
+{
+	/* Enable MPU */
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_EN,
+		_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) | AUX_MPU_EN_ENABLE);
+}
+
+/**
+ * @brief disable the MPU
+ */
+void arc_core_mpu_disable(void)
+{
+	/* Disable MPU */
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_EN,
+		_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) & AUX_MPU_EN_DISABLE);
+}
+
+
+/**
+ * @brief configure the base address and size for an MPU region
+ *
+ * @param   type    MPU region type
+ * @param   base    base address in RAM
+ * @param   size    size of the region
+ */
+void arc_core_mpu_configure(u8_t type, u32_t base, u32_t size)
+{
+	u32_t region_index;
+	u32_t region_attr;
+
+	SYS_LOG_DBG("Region info: 0x%x 0x%x", base, size);
+	/*
+	 * The new MPU regions are allocated per type before
+	 * the statically configured regions.
+	 *
+	 * For ARC MPU v2, MPU regions can be overlapped, smaller
+	 * region index has higher priority.
+	 */
+
+	region_index = _get_num_regions() - mpu_config.num_regions;
+
+	if (type > region_index) {
+		return;
+	}
+
+	region_index -= type;
+	region_attr = _get_region_attr_by_type(type, size);
+
+	if (region_attr == 0) {
+		return;
+	}
+
+	base |= AUX_MPU_RDB_VALID_MASK;
+
+	_region_init(region_index, base, region_attr);
+}
+
+/**
+ * @brief configure the default region
+ *
+ * @param   region_attr region attribute of default region
+ */
+void arc_core_mpu_default(u32_t region_attr)
+{
+	u32_t val =  _arc_v2_aux_reg_read(_ARC_V2_MPU_EN) &
+			(~AUX_MPU_RDP_ATTR_MASK);
+
+	region_attr &= AUX_MPU_RDP_ATTR_MASK;
+
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, region_attr | val);
+}
+
+
+/**
+ * @brief configure the mpu region
+ *
+ * @param   index   MPU region index
+ * @param   base    base address
+ * @param   region_attr region attribute
+ */
+void arc_core_mpu_region(u32_t index, u32_t base, u32_t region_attr)
+{
+	if (index >= _get_num_regions()) {
+		return;
+	}
+
+	base |= AUX_MPU_RDB_VALID_MASK;
+	region_attr &= AUX_MPU_RDP_ATTR_MASK;
+
+	_region_init(index, base, region_attr);
+}
+
+/* ARC MPU Driver Initial Setup */
+
+/*
+ * @brief MPU default configuration
+ *
+ * This function provides the default configuration mechanism for the Memory
+ * Protection Unit (MPU).
+ */
+static void _arc_mpu_config(void)
+{
+	u32_t r_index;
+	u32_t num_regions;
+	u32_t i;
+
+	num_regions = _get_num_regions();
+
+	/* ARC MPU supports up to 16 Regions */
+	if (mpu_config.num_regions > num_regions) {
+		return;
+	}
+
+	/*
+	 * the MPU regions are filled in the reverse order.
+	 * According to ARCv2 ISA, the mpu region with smaller
+	 * index has higher priority. The static background mpu
+	 * regions in mpu_config will be in the bottom. Then
+	 * the special type regions will be above.
+	 *
+	 */
+	r_index = num_regions - mpu_config.num_regions;
+	/* Disable MPU */
+	arc_core_mpu_disable();
+
+	/* clear the regions reserved for special type */
+	for (i = 0; i < r_index; i++) {
+		_region_init(i, 0, 0);
+	}
+
+	/* configure the static regions */
+	for (r_index = 0; i < num_regions; i++) {
+		_region_init(i,
+			mpu_config.mpu_regions[r_index].base
+			| AUX_MPU_RDB_VALID_MASK,
+			mpu_config.mpu_regions[r_index].attr);
+		r_index++;
+	}
+
+	/* default region: no read, write and execute */
+	arc_core_mpu_default(0);
+
+	/* Enable MPU */
+	arc_core_mpu_enable();
+}
+
+static int arc_mpu_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	_arc_mpu_config();
+
+	return 0;
+}
+
+SYS_INIT(arc_mpu_init, PRE_KERNEL_1,
+	 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/core/offsets/offsets.c

@@ -1,30 +1,19 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * @file
- * @brief ARCv2 nano kernel structure member offset definition file
+ * @brief ARCv2 kernel structure member offset definition file
  *
  * This module is responsible for the generation of the absolute symbols whose
- * value represents the member offsets for various ARCv2 nanokernel
- * structures.
+ * value represents the member offsets for various ARCv2 kernel structures.
  *
  * All of the absolute symbols defined by this module will be present in the
- * final microkernel or nanokernel ELF image (due to the linker's reference to
- * the _OffsetAbsSyms symbol).
+ * final kernel ELF image (due to the linker's reference to the _OffsetAbsSyms
+ * symbol).
  *
  * INTERNAL
  * It is NOT necessary to define the offset for every member of a structure.
@@ -41,7 +30,7 @@ GEN_OFFSET_SYM(_thread_arch_t, intlock_key);
 GEN_OFFSET_SYM(_thread_arch_t, relinquish_cause);
 GEN_OFFSET_SYM(_thread_arch_t, return_value);
 #ifdef CONFIG_ARC_STACK_CHECKING
-GEN_OFFSET_SYM(_thread_arch_t, stack_top);
+GEN_OFFSET_SYM(_thread_arch_t, stack_base);
 #endif
 
 /* ARCv2-specific IRQ stack frame structure member offsets */
@@ -63,6 +52,11 @@ GEN_OFFSET_SYM(_isf_t, blink);
 GEN_OFFSET_SYM(_isf_t, lp_end);
 GEN_OFFSET_SYM(_isf_t, lp_start);
 GEN_OFFSET_SYM(_isf_t, lp_count);
+#ifdef CONFIG_CODE_DENSITY
+GEN_OFFSET_SYM(_isf_t, ei_base);
+GEN_OFFSET_SYM(_isf_t, ldi_base);
+GEN_OFFSET_SYM(_isf_t, jli_base);
+#endif
 GEN_OFFSET_SYM(_isf_t, pc);
 GEN_OFFSET_SYM(_isf_t, status32);
 GEN_ABSOLUTE_SYM(___isf_t_SIZEOF, sizeof(_isf_t));
@@ -86,6 +80,19 @@ GEN_OFFSET_SYM(_callee_saved_stack_t, r25);
 GEN_OFFSET_SYM(_callee_saved_stack_t, r26);
 GEN_OFFSET_SYM(_callee_saved_stack_t, fp);
 GEN_OFFSET_SYM(_callee_saved_stack_t, r30);
+#ifdef CONFIG_FP_SHARING
+GEN_OFFSET_SYM(_callee_saved_stack_t, r58);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r59);
+GEN_OFFSET_SYM(_callee_saved_stack_t, fpu_status);
+GEN_OFFSET_SYM(_callee_saved_stack_t, fpu_ctrl);
+#ifdef CONFIG_FP_FPU_DA
+GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp2h);
+GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp2l);
+GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp1h);
+GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp1l);
+#endif
+
+#endif
 GEN_ABSOLUTE_SYM(___callee_saved_stack_t_SIZEOF, sizeof(_callee_saved_stack_t));
 
 GEN_ABSOLUTE_SYM(_K_THREAD_NO_FLOAT_SIZEOF, sizeof(struct k_thread));

arch/arc/core/prep_c.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -26,14 +16,16 @@
  * initialization is performed.
  */
 
-#include <stdint.h>
+#include <zephyr/types.h>
 #include <toolchain.h>
-#include <linker-defs.h>
+#include <linker/linker-defs.h>
 #include <arch/arc/v2/aux_regs.h>
 #include <kernel_structs.h>
 #include <nano_internal.h>
 
 
+/* XXX - keep for future use in full-featured cache APIs */
+#if 0
 /**
  *
  * @brief Disable the i-cache if present
@@ -79,7 +71,7 @@ static void invalidate_dcache(void)
 	}
 	_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
 }
-
+#endif
 
 /**
  *
@@ -121,8 +113,7 @@ extern FUNC_NORETURN void _Cstart(void);
 
 void _PrepC(void)
 {
-	disable_icache();
-	invalidate_dcache();
+	_icache_setup();
 	adjust_vector_table_base();
 	_bss_zero();
 	_data_copy();

arch/arc/core/regular_irq.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -24,18 +14,16 @@
  * See isr_wrapper.S for details.
  */
 
-#define _ASMLANGUAGE
-
 #include <kernel_structs.h>
 #include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
-#include "swap_macros.h"
+#include <swap_macros.h>
 
 GTEXT(_rirq_enter)
 GTEXT(_rirq_exit)
 GTEXT(_rirq_common_interrupt_swap)
-GTEXT(_is_next_thread_current)
+GDATA(exc_nest_count)
 
 #if 0 /* TODO: when FIRQ is not present, all would be regular */
 #define NUM_REGULAR_IRQ_PRIO_LEVELS CONFIG_NUM_IRQ_PRIO_LEVELS
@@ -47,14 +35,6 @@ GTEXT(_is_next_thread_current)
  * TODO: Revist this if FIRQ becomes configurable.
  */
 
-#if NUM_REGULAR_IRQ_PRIO_LEVELS > 1
-#error "nested regular interrupts are not supported."
-/*
- * Nesting of Regularing interrupts is not yet supported.
- * Set CONFIG_NUM_IRQ_PRIO_LEVELS to 2 even if SOC supports more.
- */
-#endif
-
 
 /**
  *
@@ -71,20 +51,28 @@ GTEXT(_is_next_thread_current)
 
 SECTION_FUNC(TEXT, _rirq_enter)
 
-	mov r1, _kernel
+
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* disable stack checking */
 	lr r2, [_ARC_V2_STATUS32]
 	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
 	kflag r2
 #endif
-	ld_s r2, [r1, _kernel_offset_to_current]
-#if NUM_REGULAR_IRQ_PRIO_LEVELS == 1
-	st sp, [r2, _thread_offset_to_sp]
+	clri
+	ld r1, [exc_nest_count]
+	add r0, r1, 1
+	st r0, [exc_nest_count]
+	cmp r1, 0
+
+	bgt.d  rirq_nest
+	mov r0, sp
+
+	mov r1, _kernel
 	ld sp, [r1, _kernel_offset_to_irq_stack]
-#else
-#error regular irq nesting is not implemented
-#endif
+rirq_nest:
+	push_s r0
+
+	seti
 	j _isr_demux
 
 
@@ -96,6 +84,18 @@ SECTION_FUNC(TEXT, _rirq_enter)
  */
 
 SECTION_FUNC(TEXT, _rirq_exit)
+	clri
+
+	pop sp
+
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	cmp	r0, 0
+	bne.d	_rirq_return_from_rirq
+	st	r0, [r1]
+
+#ifdef CONFIG_PREEMPT_ENABLED
 
 	mov r1, _kernel
 	ld_s r2, [r1, _kernel_offset_to_current]
@@ -105,70 +105,32 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	 * point on until return from interrupt.
 	 */
 
-	clri
-
-#if NUM_REGULAR_IRQ_PRIO_LEVELS > 1
-	/* check if we're a nested interrupt: if so, let the interrupted interrupt
-	 * handle the reschedule */
-
-	lr r3, [_ARC_V2_AUX_IRQ_ACT]
-	ffs r0, r3
-
-	asl r0, 1, r0
-
-	/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
-	 * AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is greater
-	 * than FFS(AUX_IRQ_ACT), it means that another bit is set so an
-	 * interrupt was interrupted.
-	 */
-
-	cmp r0, r3
-	brgt _rirq_return_from_rirq
-	ld sp, [r2, _thread_offset_to_sp]
-#endif
 
 	/*
-	 * Both (a)reschedule and (b)non-reschedule cases need to load the current
-	 * thread's stack, but don't have to use it until the decision is taken:
-	 * load the delay slots with the 'load stack pointer' instruction.
+	 * Non-preemptible thread ? Do not schedule (see explanation of
+	 * preempt field in kernel_struct.h).
+	 */
+	ldh_s r0, [r2, _thread_offset_to_preempt]
+	mov r3, _NON_PREEMPT_THRESHOLD
+	cmp_s r0, r3
+	bhs.d _rirq_no_reschedule
+
+	/*
+	 * Both (a)reschedule and (b)non-reschedule cases need to load the
+	 * current thread's stack, but don't have to use it until the decision
+	 * is taken: load the delay slots with the 'load stack pointer'
+	 * instruction.
 	 *
 	 * a) needs to load it to save outgoing context.
 	 * b) needs to load it to restore the interrupted context.
 	 */
 
-	/* coop thread ? do not schedule */
-	ld_s r0, [r2, _thread_offset_to_prio]
-	cmp_s r0, 0
-	blt.d _rirq_no_reschedule
-	ld sp, [r2, _thread_offset_to_sp]
-
-	/* scheduler locked ? do not schedule */
-	ld_s r0, [r2, _thread_offset_to_sched_locked]
-	brgt.d r0, 0,  _rirq_no_reschedule
-	ld sp, [r2, _thread_offset_to_sp]
-
 	/* check if the current thread needs to be rescheduled */
-	push_s r2
-	push_s r1
-	push_s blink
-	jl _is_next_thread_current
-	pop_s blink
-	pop_s r1
-	pop_s r2
-	brne.d r0, 0, _rirq_no_reschedule
-	ld sp, [r2, _thread_offset_to_sp]
+	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
+	cmp_s r0, r2
+	beq _rirq_no_reschedule
 
-	/*
-	 * Get the next scheduled thread. On _get_next_ready_thread
-	 * return it is stored in r0.
-	 */
-	push_s r2
-	push_s r1
-	push_s blink
-	jl _get_next_ready_thread
-	pop_s blink
-	pop_s r1
-	pop_s r2
+	/* cached thread to run is in r0, fall through */
 
 .balign 4
 _rirq_reschedule:
@@ -187,11 +149,11 @@ _rirq_common_interrupt_swap:
 	/* r2 contains pointer to new thread */
 
 #ifdef CONFIG_ARC_STACK_CHECKING
-	/* Use stack top and down registers from restored context */
-	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
-	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld_s r3, [r2, _thread_offset_to_stack_top]
+	/* Use stack top and base registers from restored context */
+	ld r3, [r2, _thread_offset_to_stack_base]
 	sr r3, [_ARC_V2_KSTACK_BASE]
+	ld r3, [r2, _thread_offset_to_stack_top]
+	sr r3, [_ARC_V2_KSTACK_TOP]
 #endif
 	/*
 	 * _load_callee_saved_regs expects incoming thread in r2.
@@ -199,6 +161,13 @@ _rirq_common_interrupt_swap:
 	 */
 	_load_callee_saved_regs
 
+#ifdef CONFIG_MPU_STACK_GUARD
+	push_s r2
+	mov r0, r2
+	bl configure_mpu_stack_guard
+	pop_s r2
+#endif
+
 	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
 
 	breq r3, _CAUSE_RIRQ, _rirq_return_from_rirq
@@ -245,15 +214,15 @@ _rirq_return_from_coop:
 
 	/* fall through to rtie instruction */
 
-.balign 4
-_rirq_return_from_firq:
-_rirq_return_from_rirq:
-
 	/* rtie will pop the rest from the stack */
 
 	/* fall through to rtie instruction */
 
+#endif /* CONFIG_PREEMPT_ENABLED */
+
 .balign 4
+_rirq_return_from_firq:
+_rirq_return_from_rirq:
 _rirq_no_reschedule:
 
 	rtie

arch/arc/core/reset.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,34 +11,19 @@
  * Reset handler that prepares the system for running C code.
  */
 
-#define _ASMLANGUAGE
-
 // #include <board.h>
 #include <toolchain.h>
-#include <sections.h>
+#include <linker/sections.h>
 #include <arch/cpu.h>
 
 GDATA(_interrupt_stack)
-GDATA(_firq_stack)
 GDATA(_main_stack)
 
 /* use one of the available interrupt stacks during init */
 
-/* FIRQ only ? */
-#if CONFIG_NUM_IRQ_PRIO_LEVELS == 1
 
-	/* FIRQ, but uses _interrupt_stack ? */
-	#if CONFIG_RGF_NUM_BANKS == 1
-		#define INIT_STACK _interrupt_stack
-		#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
-	#else
-		#define INIT_STACK _firq_stack
-		#define INIT_STACK_SIZE CONFIG_FIRQ_STACK_SIZE
-	#endif
-#else
-	#define INIT_STACK _interrupt_stack
-	#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
-#endif
+#define INIT_STACK _interrupt_stack
+#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
 
 GTEXT(__reset)
 GTEXT(__start)
@@ -73,6 +48,37 @@ SECTION_FUNC(TEXT,__start)
 	/* lock interrupts: will get unlocked when switch to main task */
 	clri
 
+	mov r1, 1
+
+invalidate_and_disable_icache:
+
+	lr r0, [_ARC_V2_I_CACHE_BUILD]
+	and.f r0, r0, 0xff
+	bz.nd invalidate_dcache
+
+	mov_s r2, 0
+	sr r2, [_ARC_V2_IC_IVIC]
+	/* writing to IC_IVIC needs 3 NOPs */
+	nop
+	nop
+	nop
+	sr r1, [_ARC_V2_IC_CTRL]
+
+invalidate_dcache:
+
+	lr r3, [_ARC_V2_D_CACHE_BUILD]
+	and.f r3, r3, 0xff
+	bz.nd done_cache_invalidate
+
+	sr r1, [_ARC_V2_DC_IVDC]
+
+done_cache_invalidate:
+
+#if defined(CONFIG_SYS_POWER_DEEP_SLEEP) && \
+	!defined(CONFIG_BOOTLOADER_CONTEXT_RESTORE)
+        jl @_sys_soc_resume_from_deep_sleep
+#endif
+
 #ifdef CONFIG_INIT_STACKS
 	/*
 	 * use the main stack to call memset on the interrupt stack and the
@@ -87,13 +93,6 @@ SECTION_FUNC(TEXT,__start)
 	mov_s r2, CONFIG_ISR_STACK_SIZE
 	jl memset
 
-#if CONFIG_RGF_NUM_BANKS != 1
-	mov_s r0, _firq_stack
-	mov_s r1, 0xaa
-	mov_s r2, CONFIG_FIRQ_STACK_SIZE
-	jl memset
-#endif
-
 #endif /* CONFIG_INIT_STACKS */
 
 	mov sp, INIT_STACK

arch/arc/core/sw_isr_table.S

@@ -1,64 +0,0 @@
-/* sw_isr_table.S - ISR table for static ISR declarations for ARC */
-
-/*
- * Copyright (c) 2015 Intel Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#define _ASMLANGUAGE
-
-#include <toolchain.h>
-#include <sections.h>
-#include <arch/cpu.h>
-
-/*
- * enable preprocessor features, such
- * as %expr - evaluate the expression and use it as a string
- */
-.altmacro
-
-/*
- * Define an ISR table entry
- * Define symbol as weak and give the section .gnu.linkonce
- * prefix. This allows linker overload the symbol and the
- * whole section by the one defined by a device driver
- */
-.macro _isr_table_entry_declare index
-	WDATA(_isr_irq\index)
-	.section .gnu.linkonce.isr_irq\index
-	_isr_irq\index: .word 0xABAD1DEA, _irq_spurious
-.endm
-
-/*
- * Declare the ISR table
- */
-.macro _isr_table_declare from, to
-	counter = \from
-	.rept (\to - \from)
-		_isr_table_entry_declare %counter
-		counter = counter + 1
-	.endr
-.endm
-
-GTEXT(_irq_spurious)
-GDATA(_sw_isr_table)
-
-.section .isr_irq16
-.align
-_sw_isr_table:
-
-/*In ARC architecture, IRQ 0-15 are reserved for the system and are not
-assignable by the user, for that reason the isr table linker section
-start at IRQ 16*/
-_isr_table_declare 16 CONFIG_NUM_IRQS

arch/arc/core/swap.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -24,17 +14,14 @@
  * See isr_wrapper.S for details.
  */
 
-#define _ASMLANGUAGE
-
 #include <kernel_structs.h>
 #include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
 #include <v2/irq.h>
-#include "swap_macros.h"
+#include <swap_macros.h>
 
-GTEXT(_Swap)
-GTEXT(_get_next_ready_thread)
+GTEXT(__swap)
 GDATA(_k_neg_eagain)
 GDATA(_kernel)
 
@@ -42,36 +29,37 @@ GDATA(_kernel)
  *
  * @brief Initiate a cooperative context switch
  *
- * The _Swap() routine is invoked by various nanokernel services to effect
- * a cooperative context switch.  Prior to invoking _Swap(), the caller
- * disables interrupts via nanoCpuIntLock() and the return 'key' is passed as a
- * parameter to _Swap(). The key is in fact the value stored in the register
+ * The __swap() routine is invoked by various kernel services to effect
+ * a cooperative context switch.  Prior to invoking __swap(), the caller
+ * disables interrupts via irq_lock() and the return 'key' is passed as a
+ * parameter to __swap(). The key is in fact the value stored in the register
  * operand of a CLRI instruction.
  *
  * It stores the intlock key parameter into current->intlock_key.
 
- * Given that _Swap() is called to effect a cooperative context switch,
+ * Given that __swap() is called to effect a cooperative context switch,
  * the caller-saved integer registers are saved on the stack by the function
- * call preamble to _Swap(). This creates a custom stack frame that will be
- * popped when returning from _Swap(), but is not suitable for handling a return
- * from an exception. Thus, the fact that the thread is pending because of a
- * cooperative call to _Swap() has to be recorded via the _CAUSE_COOP code in
- * the relinquish_cause of the thread's k_thread structure. The
+ * call preamble to __swap(). This creates a custom stack frame that will be
+ * popped when returning from __swap(), but is not suitable for handling a
+ * return from an exception. Thus, the fact that the thread is pending because
+ * of a cooperative call to __swap() has to be recorded via the _CAUSE_COOP code
+ * in the relinquish_cause of the thread's k_thread structure. The
  * _IrqExit()/_FirqExit() code will take care of doing the right thing to
  * restore the thread status.
  *
- * When _Swap() is invoked, we know the decision to perform a context switch or
+ * When __swap() is invoked, we know the decision to perform a context switch or
  * not has already been taken and a context switch must happen.
  *
- * @return may contain a return value setup by a call to fiberRtnValueSet()
+ * @return may contain a return value setup by a call to
+ * _set_thread_return_value()
  *
  * C function prototype:
  *
- * unsigned int _Swap (unsigned int key);
+ * unsigned int __swap (unsigned int key);
  *
  */
 
-SECTION_FUNC(TEXT, _Swap)
+SECTION_FUNC(TEXT, __swap)
 
 	/* interrupts are locked, interrupt key is in r0 */
 
@@ -86,7 +74,7 @@ SECTION_FUNC(TEXT, _Swap)
          * Carve space for the return value. Setting it to a defafult of
          * -EAGAIN eliminates the need for the timeout code to set it.
          * If another value is ever needed, it can be modified with
-         * fiberRtnValueSet().
+         * _set_thread_return_value().
          */
 	ld r3, [_k_neg_eagain]
 	st_s r3, [r2, _thread_offset_to_return_value]
@@ -106,36 +94,29 @@ SECTION_FUNC(TEXT, _Swap)
 
 	_save_callee_saved_regs
 
-	/* find out incoming thread (fiber or task) */
-
-	/*
-	 * Save needed registers to callee saved ones. It is faster than
-	 * pushing them to stack. It is possible to do since program has
-	 * just saved them and the calling routine will save them in turn
-	 * if it uses them.
-	 */
-	mov_s r13, blink
-	mov_s r14, r0
-	mov_s r15, r1
-	jl _get_next_ready_thread
-	mov_s r2, r0
-	mov_s r1, r15
-	mov_s r0, r14
-	mov_s blink, r13
+	/* get the cached thread to run */
+	ld_s r2, [r1, _kernel_offset_to_ready_q_cache]
 
 	/* entering here, r2 contains the new current thread */
 #ifdef CONFIG_ARC_STACK_CHECKING
-	/* Use stack top and down registers from restored context */
-	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
-	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld_s r3, [r2, _thread_offset_to_stack_top]
+	/* Use stack top and base registers from restored context */
+	ld r3, [r2, _thread_offset_to_stack_base]
 	sr r3, [_ARC_V2_KSTACK_BASE]
+	ld r3, [r2, _thread_offset_to_stack_top]
+	sr r3, [_ARC_V2_KSTACK_TOP]
 #endif
 	/* XXX - can be moved to delay slot of _CAUSE_RIRQ ? */
 	st_s r2, [r1, _kernel_offset_to_current]
 
 	_load_callee_saved_regs
 
+#ifdef CONFIG_MPU_STACK_GUARD
+	push_s r2
+	mov r0, r2
+	bl configure_mpu_stack_guard
+	pop_s r2
+#endif
+
 	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
 
 	breq r3, _CAUSE_RIRQ, _swap_return_from_rirq

arch/arc/core/swap_macros.h

@@ -1,171 +0,0 @@
-/* swap_macros.h - helper macros for context switch */
-
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _SWAP_MACROS__H_
-#define _SWAP_MACROS__H_
-
-#include <kernel_structs.h>
-#include <offsets_short.h>
-#include <toolchain.h>
-#include <arch/cpu.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef _ASMLANGUAGE
-
-/* entering this macro, current is in r2 */
-.macro _save_callee_saved_regs
-
-	sub_s sp, sp, ___callee_saved_stack_t_SIZEOF
-
-	/* save regs on stack */
-	st_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
-	st_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
-	st_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
-	st r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
-	st r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
-	st r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
-	st r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
-	st r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
-	st r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
-	st r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
-	st r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
-	st r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
-	st r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
-	st r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
-	st fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
-	st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
-
-	/* save stack pointer in struct tcs */
-	st sp, [r2, _thread_offset_to_sp]
-.endm
-
-/* entering this macro, current is in r2 */
-.macro _load_callee_saved_regs
-	/* restore stack pointer from struct tcs */
-	ld sp, [r2, _thread_offset_to_sp]
-
-	ld_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
-	ld_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
-	ld_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
-	ld r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
-	ld r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
-	ld r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
-	ld r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
-	ld r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
-	ld r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
-	ld r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
-	ld r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
-	ld r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
-	ld r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
-	ld r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
-	ld fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
-	ld r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
-
-	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
-
-.endm
-
-/*
- * Must be called with interrupts locked or in P0.
- * Upon exit, sp will be pointing to the stack frame.
- */
-.macro _create_irq_stack_frame
-
-	sub_s sp, sp, ___isf_t_SIZEOF
-
-	st blink, [sp, ___isf_t_blink_OFFSET]
-
-	/* store these right away so we can use them if needed */
-
-	st_s r13, [sp, ___isf_t_r13_OFFSET]
-	st_s r12, [sp, ___isf_t_r12_OFFSET]
-	st   r11, [sp, ___isf_t_r11_OFFSET]
-	st   r10, [sp, ___isf_t_r10_OFFSET]
-	st   r9,  [sp, ___isf_t_r9_OFFSET]
-	st   r8,  [sp, ___isf_t_r8_OFFSET]
-	st   r7,  [sp, ___isf_t_r7_OFFSET]
-	st   r6,  [sp, ___isf_t_r6_OFFSET]
-	st   r5,  [sp, ___isf_t_r5_OFFSET]
-	st   r4,  [sp, ___isf_t_r4_OFFSET]
-	st_s r3,  [sp, ___isf_t_r3_OFFSET]
-	st_s r2,  [sp, ___isf_t_r2_OFFSET]
-	st_s r1,  [sp, ___isf_t_r1_OFFSET]
-	st_s r0,  [sp, ___isf_t_r0_OFFSET]
-
-	mov r0, lp_count
-	st_s r0, [sp, ___isf_t_lp_count_OFFSET]
-	lr r1, [_ARC_V2_LP_START]
-	lr r0, [_ARC_V2_LP_END]
-	st_s r1, [sp, ___isf_t_lp_start_OFFSET]
-	st_s r0, [sp, ___isf_t_lp_end_OFFSET]
-
-.endm
-
-/*
- * Must be called with interrupts locked or in P0.
- * sp must be pointing the to stack frame.
- */
-.macro _pop_irq_stack_frame
-
-	ld blink, [sp, ___isf_t_blink_OFFSET]
-
-	ld_s r0, [sp, ___isf_t_lp_count_OFFSET]
-	mov lp_count, r0
-	ld_s r1, [sp, ___isf_t_lp_start_OFFSET]
-	ld_s r0, [sp, ___isf_t_lp_end_OFFSET]
-	sr r1, [_ARC_V2_LP_START]
-	sr r0, [_ARC_V2_LP_END]
-
-	ld_s r13, [sp, ___isf_t_r13_OFFSET]
-	ld_s r12, [sp, ___isf_t_r12_OFFSET]
-	ld   r11, [sp, ___isf_t_r11_OFFSET]
-	ld   r10, [sp, ___isf_t_r10_OFFSET]
-	ld   r9,  [sp, ___isf_t_r9_OFFSET]
-	ld   r8,  [sp, ___isf_t_r8_OFFSET]
-	ld   r7,  [sp, ___isf_t_r7_OFFSET]
-	ld   r6,  [sp, ___isf_t_r6_OFFSET]
-	ld   r5,  [sp, ___isf_t_r5_OFFSET]
-	ld   r4,  [sp, ___isf_t_r4_OFFSET]
-	ld_s r3,  [sp, ___isf_t_r3_OFFSET]
-	ld_s r2,  [sp, ___isf_t_r2_OFFSET]
-	ld_s r1,  [sp, ___isf_t_r1_OFFSET]
-	ld_s r0,  [sp, ___isf_t_r0_OFFSET]
-
-	/*
-	 * All gprs have been reloaded, the only one that is still usable is
-	 * ilink.
-	 *
-	 * The pc and status32 values will still be on the stack. We cannot
-	 * pop them yet because the callers of _pop_irq_stack_frame must reload
-	 * status32 differently depending on the execution context they are running
-	 * in (_Swap(), firq or exception).
-	 */
-	add_s sp, sp, ___isf_t_SIZEOF
-
-.endm
-
-#endif /* _ASMLANGUAGE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*  _SWAP_MACROS__H_ */

arch/arc/core/sys_fatal_error_handler.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,9 +11,9 @@
  * This module provides the _SysFatalErrorHandler() routine for ARCv2 BSPs.
  */
 
-#include <nanokernel.h>
+#include <kernel.h>
 #include <toolchain.h>
-#include <sections.h>
+#include <linker/sections.h>
 #include <kernel_structs.h>
 #include <misc/printk.h>
 
@@ -47,20 +37,30 @@
  *
  * @return N/A
  */
-FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
-					 const NANO_ESF *pEsf)
+FUNC_NORETURN __weak void _SysFatalErrorHandler(unsigned int reason,
+						const NANO_ESF *pEsf)
 {
-	ARG_UNUSED(reason);
 	ARG_UNUSED(pEsf);
 
+#if !defined(CONFIG_SIMPLE_FATAL_ERROR_HANDLER)
+	if (reason == _NANO_ERR_KERNEL_PANIC) {
+		goto hang_system;
+	}
 	if (k_is_in_isr() || _is_thread_essential()) {
 		printk("Fatal fault in %s! Spinning...\n",
 		       k_is_in_isr() ? "ISR" : "essential thread");
-		for (;;)
-			; /* spin forever */
+		goto hang_system;
 	}
-	printk("Fatal fault in thread! Aborting.\n");
+	printk("Fatal fault in thread %p! Aborting.\n", _current);
 	k_thread_abort(_current);
 
+hang_system:
+#else
+	ARG_UNUSED(reason);
+#endif
+
+	for (;;) {
+		k_cpu_idle();
+	}
 	CODE_UNREACHABLE;
 }

arch/arc/core/thread.c

@@ -1,28 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * @file
  * @brief New thread creation for ARCv2
  *
- * Core nanokernel fiber related primitives for the ARCv2 processor
- * architecture.
+ * Core thread related primitives for the ARCv2 processor architecture.
  */
 
-#include <nanokernel.h>
+#include <kernel.h>
 #include <toolchain.h>
 #include <kernel_structs.h>
 #include <offsets_short.h>
@@ -32,33 +21,14 @@
 #endif /* CONFIG_INIT_STACKS */
 /*  initial stack frame */
 struct init_stack_frame {
-	uint32_t pc;
-	uint32_t status32;
-	uint32_t r3;
-	uint32_t r2;
-	uint32_t r1;
-	uint32_t r0;
+	u32_t pc;
+	u32_t status32;
+	u32_t r3;
+	u32_t r2;
+	u32_t r1;
+	u32_t r0;
 };
 
-#if defined(CONFIG_THREAD_MONITOR)
-/*
- * Add a thread to the kernel's list of active threads.
- */
-static ALWAYS_INLINE void thread_monitor_init(struct k_thread *thread)
-{
-	unsigned int key;
-
-	key = irq_lock();
-	thread->next_thread = _kernel.threads;
-	_kernel.threads = thread;
-	irq_unlock(key);
-}
-#else
-#define thread_monitor_init(thread) \
-	do {/* do nothing */     \
-	} while ((0))
-#endif /* CONFIG_THREAD_MONITOR */
-
 /*
  * @brief Initialize a new thread from its stack space
  *
@@ -84,32 +54,28 @@ static ALWAYS_INLINE void thread_monitor_init(struct k_thread *thread)
  *
  * @return N/A
  */
-void _new_thread(char *pStackMem, size_t stackSize,
-		 _thread_entry_t pEntry,
+void _new_thread(struct k_thread *thread, k_thread_stack_t stack,
+		 size_t stackSize, _thread_entry_t pEntry,
 		 void *parameter1, void *parameter2, void *parameter3,
-		 int priority, unsigned options)
+		 int priority, unsigned int options)
 {
+	char *pStackMem = K_THREAD_STACK_BUFFER(stack);
 	_ASSERT_VALID_PRIO(priority, pEntry);
 
 	char *stackEnd = pStackMem + stackSize;
 	struct init_stack_frame *pInitCtx;
 
-	struct k_thread *thread = (struct k_thread *) pStackMem;
-
-#ifdef CONFIG_INIT_STACKS
-	memset(pStackMem, 0xaa, stackSize);
-#endif
+	_new_thread_init(thread, pStackMem, stackSize, priority, options);
 
 	/* carve the thread entry struct from the "base" of the stack */
-
 	pInitCtx = (struct init_stack_frame *)(STACK_ROUND_DOWN(stackEnd) -
 				       sizeof(struct init_stack_frame));
 
-	pInitCtx->pc = ((uint32_t)_thread_entry_wrapper);
-	pInitCtx->r0 = (uint32_t)pEntry;
-	pInitCtx->r1 = (uint32_t)parameter1;
-	pInitCtx->r2 = (uint32_t)parameter2;
-	pInitCtx->r3 = (uint32_t)parameter3;
+	pInitCtx->pc = ((u32_t)_thread_entry_wrapper);
+	pInitCtx->r0 = (u32_t)pEntry;
+	pInitCtx->r1 = (u32_t)parameter1;
+	pInitCtx->r2 = (u32_t)parameter2;
+	pInitCtx->r3 = (u32_t)parameter3;
 	/*
 	 * For now set the interrupt priority to 15
 	 * we can leave interrupt enable flag set to 0 as
@@ -119,23 +85,11 @@ void _new_thread(char *pStackMem, size_t stackSize,
 	 */
 #ifdef CONFIG_ARC_STACK_CHECKING
 	pInitCtx->status32 = _ARC_V2_STATUS32_SC | _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
-	thread->arch.stack_top = (uint32_t) stackEnd;
+	thread->arch.stack_base = (u32_t) stackEnd;
 #else
 	pInitCtx->status32 = _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
 #endif
 
-	_init_thread_base(&thread->base, priority, K_PRESTART, options);
-
-	/* static threads overwrite them afterwards with real values */
-	thread->init_data = NULL;
-	thread->fn_abort = NULL;
-
-#ifdef CONFIG_THREAD_CUSTOM_DATA
-	/* Initialize custom data field (value is opaque to kernel) */
-
-	thread->custom_data = NULL;
-#endif
-
 #ifdef CONFIG_THREAD_MONITOR
 	/*
 	 * In debug mode thread->entry give direct access to the thread entry
@@ -153,7 +107,7 @@ void _new_thread(char *pStackMem, size_t stackSize,
 	thread->arch.intlock_key = 0x3F;
 	thread->arch.relinquish_cause = _CAUSE_COOP;
 	thread->callee_saved.sp =
-		(uint32_t)pInitCtx - ___callee_saved_stack_t_SIZEOF;
+		(u32_t)pInitCtx - ___callee_saved_stack_t_SIZEOF;
 
 	/* initial values in all other regs/k_thread entries are irrelevant */
 

arch/arc/core/thread_entry_wrapper.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,10 +11,8 @@
  * Wrapper for _thread_entry routine when called from the initial context.
  */
 
-#define _ASMLANGUAGE
-
 #include <toolchain.h>
-#include <sections.h>
+#include <linker/sections.h>
 
 GTEXT(_thread_entry_wrapper)
 GTEXT(_thread_entry)

arch/arc/core/timestamp.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2017 Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Time Stamp API for ARCv2
+ *
+ * Provide 64-bit time stamp API
+ */
+
+#include <kernel.h>
+#include <toolchain.h>
+#include <kernel_structs.h>
+
+extern volatile u64_t _sys_clock_tick_count;
+extern int sys_clock_hw_cycles_per_tick;
+
+/*
+ * @brief Read 64-bit timestamp value
+ *
+ * This function returns a 64-bit bit time stamp value that is clocked
+ * at the same frequency as the CPU.
+ *
+ * @return 64-bit time stamp value
+ */
+u64_t _tsc_read(void)
+{
+	unsigned int key;
+	u64_t t;
+	u32_t count;
+
+	key = irq_lock();
+	t = (u64_t)_sys_clock_tick_count;
+	count = _arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT);
+	irq_unlock(key);
+	t *= (u64_t)sys_clock_hw_cycles_per_tick;
+	t += (u64_t)count;
+	return t;
+}

arch/arc/core/vector_table.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -33,44 +23,44 @@
  * swapped.
  */
 
-#include <stdint.h>
+#include <zephyr/types.h>
 #include <toolchain.h>
 #include "vector_table.h"
 
 struct vector_table {
-	uint32_t reset;
-	uint32_t memory_error;
-	uint32_t instruction_error;
-	uint32_t ev_machine_check;
-	uint32_t ev_tlb_miss_i;
-	uint32_t ev_tlb_miss_d;
-	uint32_t ev_prot_v;
-	uint32_t ev_privilege_v;
-	uint32_t ev_swi;
-	uint32_t ev_trap;
-	uint32_t ev_extension;
-	uint32_t ev_div_zero;
-	uint32_t ev_dc_error;
-	uint32_t ev_maligned;
-	uint32_t unused_1;
-	uint32_t unused_2;
+	u32_t reset;
+	u32_t memory_error;
+	u32_t instruction_error;
+	u32_t ev_machine_check;
+	u32_t ev_tlb_miss_i;
+	u32_t ev_tlb_miss_d;
+	u32_t ev_prot_v;
+	u32_t ev_privilege_v;
+	u32_t ev_swi;
+	u32_t ev_trap;
+	u32_t ev_extension;
+	u32_t ev_div_zero;
+	u32_t ev_dc_error;
+	u32_t ev_maligned;
+	u32_t unused_1;
+	u32_t unused_2;
 };
 
 struct vector_table _VectorTable _GENERIC_SECTION(.exc_vector_table) = {
-	(uint32_t)__reset,
-	(uint32_t)__memory_error,
-	(uint32_t)__instruction_error,
-	(uint32_t)__ev_machine_check,
-	(uint32_t)__ev_tlb_miss_i,
-	(uint32_t)__ev_tlb_miss_d,
-	(uint32_t)__ev_prot_v,
-	(uint32_t)__ev_privilege_v,
-	(uint32_t)__ev_swi,
-	(uint32_t)__ev_trap,
-	(uint32_t)__ev_extension,
-	(uint32_t)__ev_div_zero,
-	(uint32_t)__ev_dc_error,
-	(uint32_t)__ev_maligned,
+	(u32_t)__reset,
+	(u32_t)__memory_error,
+	(u32_t)__instruction_error,
+	(u32_t)__ev_machine_check,
+	(u32_t)__ev_tlb_miss_i,
+	(u32_t)__ev_tlb_miss_d,
+	(u32_t)__ev_prot_v,
+	(u32_t)__ev_privilege_v,
+	(u32_t)__ev_swi,
+	(u32_t)__ev_trap,
+	(u32_t)__ev_extension,
+	(u32_t)__ev_div_zero,
+	(u32_t)__ev_dc_error,
+	(u32_t)__ev_maligned,
 	0,
 	0
 };

arch/arc/include/kernel_arch_data.h

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014-2016 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -35,89 +25,90 @@ extern "C" {
 #endif
 
 #include <toolchain.h>
-#include <sections.h>
+#include <linker/sections.h>
 #include <arch/cpu.h>
 #include <vector_table.h>
+#include <kernel_arch_thread.h>
 
 #ifndef _ASMLANGUAGE
 #include <kernel.h>
 #include <nano_internal.h>
-#include <stdint.h>
+#include <zephyr/types.h>
 #include <misc/util.h>
 #include <misc/dlist.h>
 #endif
 
 #ifndef _ASMLANGUAGE
-
-struct _caller_saved {
-	/*
-	 * Saved on the stack as part of handling a regular IRQ or by the
-	 * kernel when calling the FIRQ return code.
-	 */
-};
-
-typedef struct _caller_saved _caller_saved_t;
-
 struct _irq_stack_frame {
-	uint32_t r0;
-	uint32_t r1;
-	uint32_t r2;
-	uint32_t r3;
-	uint32_t r4;
-	uint32_t r5;
-	uint32_t r6;
-	uint32_t r7;
-	uint32_t r8;
-	uint32_t r9;
-	uint32_t r10;
-	uint32_t r11;
-	uint32_t r12;
-	uint32_t r13;
-	uint32_t blink;
-	uint32_t lp_end;
-	uint32_t lp_start;
-	uint32_t lp_count;
+	u32_t r0;
+	u32_t r1;
+	u32_t r2;
+	u32_t r3;
+	u32_t r4;
+	u32_t r5;
+	u32_t r6;
+	u32_t r7;
+	u32_t r8;
+	u32_t r9;
+	u32_t r10;
+	u32_t r11;
+	u32_t r12;
+	u32_t r13;
+	u32_t blink;
+	u32_t lp_end;
+	u32_t lp_start;
+	u32_t lp_count;
 #ifdef CONFIG_CODE_DENSITY
 	/*
 	 * Currently unsupported. This is where those registers are
 	 * automatically pushed on the stack by the CPU when taking a regular
 	 * IRQ.
 	 */
-	uint32_t ei_base;
-	uint32_t ldi_base;
-	uint32_t jli_base;
+	u32_t ei_base;
+	u32_t ldi_base;
+	u32_t jli_base;
 #endif
-	uint32_t pc;
-	uint32_t status32;
+	u32_t pc;
+	u32_t status32;
 };
 
 typedef struct _irq_stack_frame _isf_t;
 
-struct _callee_saved {
-	uint32_t sp; /* r28 */
-};
-typedef struct _callee_saved _callee_saved_t;
+
 
 /* callee-saved registers pushed on the stack, not in k_thread */
 struct _callee_saved_stack {
-	uint32_t r13;
-	uint32_t r14;
-	uint32_t r15;
-	uint32_t r16;
-	uint32_t r17;
-	uint32_t r18;
-	uint32_t r19;
-	uint32_t r20;
-	uint32_t r21;
-	uint32_t r22;
-	uint32_t r23;
-	uint32_t r24;
-	uint32_t r25;
-	uint32_t r26;
-	uint32_t fp; /* r27 */
+	u32_t r13;
+	u32_t r14;
+	u32_t r15;
+	u32_t r16;
+	u32_t r17;
+	u32_t r18;
+	u32_t r19;
+	u32_t r20;
+	u32_t r21;
+	u32_t r22;
+	u32_t r23;
+	u32_t r24;
+	u32_t r25;
+	u32_t r26;
+	u32_t fp; /* r27 */
 	/* r28 is the stack pointer and saved separately */
 	/* r29 is ILINK and does not need to be saved */
-	uint32_t r30;
+	u32_t r30;
+#ifdef CONFIG_FP_SHARING
+	u32_t r58;
+	u32_t r59;
+	u32_t fpu_status;
+	u32_t fpu_ctrl;
+#ifdef CONFIG_FP_FPU_DA
+	u32_t dpfp2h;
+	u32_t dpfp2l;
+	u32_t dpfp1h;
+	u32_t dpfp1l;
+#endif
+
+#endif
 	/*
 	 * No need to save r31 (blink), it's either alread pushed as the pc or
 	 * blink on an irq stack frame.
@@ -126,45 +117,6 @@ struct _callee_saved_stack {
 
 typedef struct _callee_saved_stack _callee_saved_stack_t;
 
-#endif /* _ASMLANGUAGE */
-
-/* stacks */
-
-#define STACK_ALIGN_SIZE 4
-
-#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
-#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
-
-/*
- * Reason a thread has relinquished control: fibers can only be in the NONE
- * or COOP state, tasks can be one in the four.
- */
-#define _CAUSE_NONE 0
-#define _CAUSE_COOP 1
-#define _CAUSE_RIRQ 2
-#define _CAUSE_FIRQ 3
-
-#ifndef _ASMLANGUAGE
-
-struct _thread_arch {
-
-	/* interrupt key when relinquishing control */
-	uint32_t intlock_key;
-
-	/* one of the _CAUSE_xxxx definitions above */
-	int relinquish_cause;
-
-	/* return value from _Swap */
-	unsigned int return_value;
-
-#ifdef CONFIG_ARC_STACK_CHECKING
-	/* top of stack for hardware stack checking */
-	uint32_t stack_top;
-#endif
-};
-
-typedef struct _thread_arch _thread_arch_t;
-
 struct _kernel_arch {
 
 	char *rirq_sp; /* regular IRQ stack pointer base */
@@ -180,6 +132,13 @@ typedef struct _kernel_arch _kernel_arch_t;
 
 #endif /* _ASMLANGUAGE */
 
+/* stacks */
+
+#define STACK_ALIGN_SIZE 4
+
+#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
+#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
+
 #ifdef __cplusplus
 }
 #endif

arch/arc/include/kernel_arch_func.h

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014-2016 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -41,9 +31,8 @@ extern "C" {
 #include <v2/irq.h>
 #endif
 
-static ALWAYS_INLINE void nanoArchInit(void)
+static ALWAYS_INLINE void kernel_arch_init(void)
 {
-	_icache_setup();
 	_irq_setup();
 }
 
@@ -55,7 +44,7 @@ _set_thread_return_value(struct k_thread *thread, unsigned int value)
 
 static ALWAYS_INLINE int _is_in_isr(void)
 {
-	uint32_t act = _arc_v2_aux_reg_read(_ARC_V2_AUX_IRQ_ACT);
+	u32_t act = _arc_v2_aux_reg_read(_ARC_V2_AUX_IRQ_ACT);
 #if CONFIG_IRQ_OFFLOAD
 	/* Check if we're in a TRAP_S exception as well */
 	if (_arc_v2_aux_reg_read(_ARC_V2_STATUS32) & _ARC_V2_STATUS32_AE &&
@@ -69,14 +58,14 @@ static ALWAYS_INLINE int _is_in_isr(void)
 
 /**
  *
- * @bried Indicates the interrupt number of the highest priority
+ * @brief Indicates the interrupt number of the highest priority
  * active interrupt
  *
  * @return IRQ number
  */
 static ALWAYS_INLINE int _INTERRUPT_CAUSE(void)
 {
-	uint32_t irq_num = _arc_v2_aux_reg_read(_ARC_V2_ICAUSE);
+	u32_t irq_num = _arc_v2_aux_reg_read(_ARC_V2_ICAUSE);
 
 	return irq_num;
 }

arch/arc/include/kernel_arch_thread.h

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Per-arch thread definition
+ *
+ * This file contains defintions for
+ *
+ *  struct _thread_arch
+ *  struct _callee_saved
+ *  struct _caller_saved
+ *
+ * necessary to instantiate instances of struct k_thread.
+ */
+
+#ifndef _kernel_arch_thread__h_
+#define _kernel_arch_thread__h_
+
+/*
+ * Reason a thread has relinquished control: fibers can only be in the NONE
+ * or COOP state, tasks can be one in the four.
+ */
+#define _CAUSE_NONE 0
+#define _CAUSE_COOP 1
+#define _CAUSE_RIRQ 2
+#define _CAUSE_FIRQ 3
+
+#ifndef _ASMLANGUAGE
+#include <zephyr/types.h>
+
+struct _caller_saved {
+	/*
+	 * Saved on the stack as part of handling a regular IRQ or by the
+	 * kernel when calling the FIRQ return code.
+	 */
+};
+
+typedef struct _caller_saved _caller_saved_t;
+
+struct _callee_saved {
+	u32_t sp; /* r28 */
+};
+typedef struct _callee_saved _callee_saved_t;
+
+struct _thread_arch {
+
+	/* interrupt key when relinquishing control */
+	u32_t intlock_key;
+
+	/* one of the _CAUSE_xxxx definitions above */
+	int relinquish_cause;
+
+	/* return value from _Swap */
+	unsigned int return_value;
+
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* High address of stack region, stack grows downward from this
+	 * location. Usesd for hardware stack checking
+	 */
+	u32_t stack_base;
+#endif
+};
+
+typedef struct _thread_arch _thread_arch_t;
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* _kernel_arch_thread__h_ */

arch/arc/include/kernel_event_logger_arch.h

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2016 Intel Corporation
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**

arch/arc/include/offsets_short_arch.h

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2016 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 #ifndef _offsets_short_arch__h_
@@ -36,12 +26,14 @@
 #define _thread_offset_to_return_value \
 	(___thread_t_arch_OFFSET + ___thread_arch_t_return_value_OFFSET)
 
-#define _thread_offset_to_stack_top \
-	(___thread_t_arch_OFFSET + ___thread_arch_t_stack_top_OFFSET)
+#define _thread_offset_to_stack_base \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_stack_base_OFFSET)
 
 #define _thread_offset_to_sp \
 	(___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET)
 
+#define _thread_offset_to_stack_top \
+	(___thread_t_stack_info_OFFSET + ___thread_stack_info_t_start_OFFSET)
 
 /* end - threads */
 

arch/arc/include/start_task_arch.h

@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file
- * @brief ARC nanokernel declarations to start a task
- *
- * ARC-specific parts of start_task().
- *
- * Currently empty, only here for abstraction.
- */
-
-#ifndef _START_TASK_ARCH__H_
-#define _START_TASK_ARCH__H_
-
-#include <toolchain.h>
-#include <sections.h>
-
-#include <micro_private.h>
-#include <kernel_structs.h>
-#include <microkernel/task.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define _START_TASK_ARCH(task, opt_ptr) \
-	do {/* nothing */              \
-	} while ((0))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _START_TASK_ARCH__H_ */

arch/arc/include/swap_macros.h

@@ -0,0 +1,227 @@
+/* swap_macros.h - helper macros for context switch */
+
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SWAP_MACROS__H_
+#define _SWAP_MACROS__H_
+
+#include <kernel_structs.h>
+#include <offsets_short.h>
+#include <toolchain.h>
+#include <arch/cpu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef _ASMLANGUAGE
+
+/* entering this macro, current is in r2 */
+.macro _save_callee_saved_regs
+
+	sub_s sp, sp, ___callee_saved_stack_t_SIZEOF
+
+	/* save regs on stack */
+	st_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
+	st_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
+	st_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
+	st r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
+	st r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
+	st r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
+	st r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
+	st r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
+	st r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
+	st r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
+	st r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
+	st r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
+	st r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
+	st r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
+	st fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
+	st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
+
+#ifdef CONFIG_FP_SHARING
+	st r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
+	st r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
+	lr r13, [_ARC_V2_FPU_STATUS]
+	st_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
+	lr r13, [_ARC_V2_FPU_CTRL]
+	st_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
+
+#ifdef CONFIG_FP_FPU_DA
+	lr r13, [_ARC_V2_FPU_DPFP1L]
+	st_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
+	lr r13, [_ARC_V2_FPU_DPFP1H]
+	st_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
+	lr r13, [_ARC_V2_FPU_DPFP2L]
+	st_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
+	lr r13, [_ARC_V2_FPU_DPFP2H]
+	st_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
+#endif
+
+#endif
+
+	/* save stack pointer in struct tcs */
+	st sp, [r2, _thread_offset_to_sp]
+.endm
+
+/* entering this macro, current is in r2 */
+.macro _load_callee_saved_regs
+	/* restore stack pointer from struct tcs */
+	ld sp, [r2, _thread_offset_to_sp]
+
+#ifdef CONFIG_FP_SHARING
+	ld r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
+	ld r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
+
+	ld_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
+	sr r13, [_ARC_V2_FPU_STATUS]
+	ld_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
+	sr r13, [_ARC_V2_FPU_CTRL]
+
+#ifdef CONFIG_FP_FPU_DA
+	ld_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
+	sr r13, [_ARC_V2_FPU_DPFP1L]
+	ld_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
+	sr r13, [_ARC_V2_FPU_DPFP1H]
+	ld_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
+	sr r13, [_ARC_V2_FPU_DPFP2L]
+	ld_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
+	sr r13, [_ARC_V2_FPU_DPFP2H]
+#endif
+
+#endif
+
+	ld_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
+	ld_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
+	ld_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
+	ld r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
+	ld r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
+	ld r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
+	ld r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
+	ld r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
+	ld r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
+	ld r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
+	ld r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
+	ld r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
+	ld r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
+	ld r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
+	ld fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
+	ld r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
+
+	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
+
+.endm
+
+.macro _discard_callee_saved_regs
+	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
+.endm
+
+/*
+ * Must be called with interrupts locked or in P0.
+ * Upon exit, sp will be pointing to the stack frame.
+ */
+.macro _create_irq_stack_frame
+
+	sub_s sp, sp, ___isf_t_SIZEOF
+
+	st blink, [sp, ___isf_t_blink_OFFSET]
+
+	/* store these right away so we can use them if needed */
+
+	st_s r13, [sp, ___isf_t_r13_OFFSET]
+	st_s r12, [sp, ___isf_t_r12_OFFSET]
+	st   r11, [sp, ___isf_t_r11_OFFSET]
+	st   r10, [sp, ___isf_t_r10_OFFSET]
+	st   r9,  [sp, ___isf_t_r9_OFFSET]
+	st   r8,  [sp, ___isf_t_r8_OFFSET]
+	st   r7,  [sp, ___isf_t_r7_OFFSET]
+	st   r6,  [sp, ___isf_t_r6_OFFSET]
+	st   r5,  [sp, ___isf_t_r5_OFFSET]
+	st   r4,  [sp, ___isf_t_r4_OFFSET]
+	st_s r3,  [sp, ___isf_t_r3_OFFSET]
+	st_s r2,  [sp, ___isf_t_r2_OFFSET]
+	st_s r1,  [sp, ___isf_t_r1_OFFSET]
+	st_s r0,  [sp, ___isf_t_r0_OFFSET]
+
+	mov r0, lp_count
+	st_s r0, [sp, ___isf_t_lp_count_OFFSET]
+	lr r1, [_ARC_V2_LP_START]
+	lr r0, [_ARC_V2_LP_END]
+	st_s r1, [sp, ___isf_t_lp_start_OFFSET]
+	st_s r0, [sp, ___isf_t_lp_end_OFFSET]
+
+#ifdef CONFIG_CODE_DENSITY
+	lr r1, [_ARC_V2_JLI_BASE]
+	lr r0, [_ARC_V2_LDI_BASE]
+	lr r2, [_ARC_V2_EI_BASE]
+	st_s r1, [sp, ___isf_t_jli_base_OFFSET]
+	st_s r0, [sp, ___isf_t_ldi_base_OFFSET]
+	st_s r2, [sp, ___isf_t_ei_base_OFFSET]
+#endif
+
+.endm
+
+/*
+ * Must be called with interrupts locked or in P0.
+ * sp must be pointing the to stack frame.
+ */
+.macro _pop_irq_stack_frame
+
+	ld blink, [sp, ___isf_t_blink_OFFSET]
+
+#ifdef CONFIG_CODE_DENSITY
+	ld_s r1, [sp, ___isf_t_jli_base_OFFSET]
+	ld_s r0, [sp, ___isf_t_ldi_base_OFFSET]
+	ld_s r2, [sp, ___isf_t_ei_base_OFFSET]
+	sr r1, [_ARC_V2_JLI_BASE]
+	sr r0, [_ARC_V2_LDI_BASE]
+	sr r2, [_ARC_V2_EI_BASE]
+#endif
+
+	ld_s r0, [sp, ___isf_t_lp_count_OFFSET]
+	mov lp_count, r0
+	ld_s r1, [sp, ___isf_t_lp_start_OFFSET]
+	ld_s r0, [sp, ___isf_t_lp_end_OFFSET]
+	sr r1, [_ARC_V2_LP_START]
+	sr r0, [_ARC_V2_LP_END]
+
+	ld_s r13, [sp, ___isf_t_r13_OFFSET]
+	ld_s r12, [sp, ___isf_t_r12_OFFSET]
+	ld   r11, [sp, ___isf_t_r11_OFFSET]
+	ld   r10, [sp, ___isf_t_r10_OFFSET]
+	ld   r9,  [sp, ___isf_t_r9_OFFSET]
+	ld   r8,  [sp, ___isf_t_r8_OFFSET]
+	ld   r7,  [sp, ___isf_t_r7_OFFSET]
+	ld   r6,  [sp, ___isf_t_r6_OFFSET]
+	ld   r5,  [sp, ___isf_t_r5_OFFSET]
+	ld   r4,  [sp, ___isf_t_r4_OFFSET]
+	ld_s r3,  [sp, ___isf_t_r3_OFFSET]
+	ld_s r2,  [sp, ___isf_t_r2_OFFSET]
+	ld_s r1,  [sp, ___isf_t_r1_OFFSET]
+	ld_s r0,  [sp, ___isf_t_r0_OFFSET]
+
+
+	/*
+	 * All gprs have been reloaded, the only one that is still usable is
+	 * ilink.
+	 *
+	 * The pc and status32 values will still be on the stack. We cannot
+	 * pop them yet because the callers of _pop_irq_stack_frame must reload
+	 * status32 differently depending on the execution context they are
+	 * running in (_Swap(), firq or exception).
+	 */
+	add_s sp, sp, ___isf_t_SIZEOF
+
+.endm
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*  _SWAP_MACROS__H_ */

arch/arc/include/v2/cache.h

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -46,11 +36,11 @@ extern "C" {
  */
 static ALWAYS_INLINE void _icache_setup(void)
 {
-	uint32_t icache_config = (
+	u32_t icache_config = (
 		IC_CACHE_DIRECT | /* direct mapping (one-way assoc.) */
 		IC_CACHE_ENABLE   /* i-cache enabled */
 	);
-	uint32_t val;
+	u32_t val;
 
 	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
 	val &= 0xff;

arch/arc/include/v2/irq.h

@@ -1,24 +1,14 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * @file
  * @brief Interrupt helper functions (ARC)
  *
- * This file contains private nanokernel structures definitions and various
+ * This file contains private kernel structures definitions and various
  * other definitions for the ARCv2 processor architecture.
  */
 
@@ -36,13 +26,13 @@ extern "C" {
 #define _ARC_V2_AUX_IRQ_CTRL_16_REGS 8
 #define _ARC_V2_AUX_IRQ_CTRL_32_REGS 16
 
+
 #define _ARC_V2_DEF_IRQ_LEVEL (CONFIG_NUM_IRQ_PRIO_LEVELS-1)
 #define _ARC_V2_WAKE_IRQ_LEVEL _ARC_V2_DEF_IRQ_LEVEL
 
 #ifndef _ASMLANGUAGE
 
-extern void _firq_stack_setup(void);
-extern char _interrupt_stack[];
+extern K_THREAD_STACK_DEFINE(_interrupt_stack, CONFIG_ISR_STACK_SIZE);
 
 /*
  * _irq_setup
@@ -51,17 +41,20 @@ extern char _interrupt_stack[];
  */
 static ALWAYS_INLINE void _irq_setup(void)
 {
-	uint32_t aux_irq_ctrl_value = (
+	u32_t aux_irq_ctrl_value = (
 		_ARC_V2_AUX_IRQ_CTRL_LOOP_REGS | /* save lp_xxx registers */
+#ifdef CONFIG_CODE_DENSITY
+		_ARC_V2_AUX_IRQ_CTRL_LP | /* save code density registers */
+#endif
 		_ARC_V2_AUX_IRQ_CTRL_BLINK     | /* save blink */
 		_ARC_V2_AUX_IRQ_CTRL_14_REGS     /* save r0 -> r13 (caller-saved) */
 	);
 
-	nano_cpu_sleep_mode = _ARC_V2_WAKE_IRQ_LEVEL;
+	k_cpu_sleep_mode = _ARC_V2_WAKE_IRQ_LEVEL;
 	_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_CTRL, aux_irq_ctrl_value);
 
-	_kernel.irq_stack = _interrupt_stack + CONFIG_ISR_STACK_SIZE;
-	_firq_stack_setup();
+	_kernel.irq_stack =
+		K_THREAD_STACK_BUFFER(_interrupt_stack) + CONFIG_ISR_STACK_SIZE;
 }
 
 #endif /* _ASMLANGUAGE */

arch/arc/include/vector_table.h

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -41,7 +31,7 @@ extern "C" {
 
 #include <board.h>
 #include <toolchain.h>
-#include <sections.h>
+#include <linker/sections.h>
 
 GTEXT(__start)
 GTEXT(_VectorTable)

arch/arc/soc/em11d/Kconfig.defconfig

@@ -2,17 +2,7 @@
 # Copyright (c) 2014 Wind River Systems, Inc.
 # Copyright (c) 2016 Synopsys, Inc. All rights reserved.
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 
 if SOC_EM11D
@@ -23,13 +13,12 @@ config SOC
 config NUM_IRQ_PRIO_LEVELS
 	# This processor supports 4 priority levels:
 	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
-	# TODO: But regular irq nesting is not implemented --
-	# so this must be 2 for now.
-	default 2
+	default 4
 
 config NUM_IRQS
 	# must be > the highest interrupt number used
-	default 36
+	default 38 if BOARD_EM_STARTERKIT_R23
+	default 36 if BOARD_EM_STARTERKIT_R22
 
 config RGF_NUM_BANKS
 	default 2
@@ -68,192 +57,7 @@ config DCCM_SIZE
 config CACHE_FLUSHING
 	def_bool y
 
-if GPIO
-
-config GPIO_DW
+config FP_FPU_DA
 	def_bool y
 
-if GPIO_DW
-
-config GPIO_DW_0
-	def_bool y
-
-if GPIO_DW_0
-
-config GPIO_DW_0_NAME
-	default "GPIO_PORTA"
-
-config GPIO_DW_0_IRQ_PRI
-	default 1
-
-endif # GPIO_DW_0
-
-config GPIO_DW_1
-	def_bool y
-
-if GPIO_DW_1
-
-config GPIO_DW_1_NAME
-	default "GPIO_PORTB"
-
-config GPIO_DW_1_IRQ_PRI
-	default 1
-
-endif # GPIO_DW_1
-
-config GPIO_DW_2
-	def_bool y
-
-if GPIO_DW_2
-
-config GPIO_DW_2_IRQ_PRI
-	default 1
-
-config GPIO_DW_2_NAME
-	default "GPIO_PORTC"
-
-endif # GPIO_DW_2
-
-config GPIO_DW_3
-	def_bool y
-
-if GPIO_DW_3
-
-config GPIO_DW_3_IRQ_PRI
-	default 1
-
-config GPIO_DW_3_NAME
-	default "GPIO_PORTD"
-
-endif # GPIO_DW_3
-
-endif # GPIO_DW
-
-endif # GPIO
-
-if I2C
-
-config I2C_CLOCK_SPEED
-	default 100
-
-config I2C_DW
-	def_bool y
-
-if I2C_DW
-
-config I2C_0
-	def_bool y
-
-if I2C_0
-
-config I2C_0_NAME
-	default "I2C_0"
-config I2C_0_DEFAULT_CFG
-	default 0x3
-config I2C_0_IRQ_PRI
-	default 1
-
-endif # I2C_0
-
-config I2C_1
-	def_bool y
-
-if I2C_1
-
-config I2C_1_NAME
-	default "I2C_1"
-config I2C_1_DEFAULT_CFG
-	default 0x3
-config I2C_1_IRQ_PRI
-	default 1
-
-endif # I2C_1
-
-endif # I2C_DW
-
-endif # I2C
-
-if UART_NS16550
-
-config UART_NS16550_PORT_0
-	def_bool n
-
-if UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_0_NAME
-	default "UART_0"
-config UART_NS16550_PORT_0_IRQ_PRI
-	default 1
-config UART_NS16550_PORT_0_BAUD_RATE
-	default 115200
-config UART_NS16550_PORT_0_OPTIONS
-	default 0
-
-endif # UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_1
-	def_bool y
-
-if UART_NS16550_PORT_1
-
-config UART_NS16550_PORT_1_NAME
-	default "UART_1"
-config UART_NS16550_PORT_1_IRQ_PRI
-	default 1
-config UART_NS16550_PORT_1_BAUD_RATE
-	default 115200
-config UART_NS16550_PORT_1_OPTIONS
-	default 0
-
-endif # UART_NS16550_PORT_1
-
-endif # UART_NS16550
-
-if UART_CONSOLE
-
-config UART_CONSOLE_ON_DEV_NAME
-	default "UART_1"
-
-endif
-
-if SPI
-
-config SPI_DW
-	def_bool y
-
-if SPI_DW
-
-config SPI_DW_CLOCK_GATE
-	def_bool n
-
-config SPI_DW_FIFO_DEPTH
-	default 32
-
-config SPI_DW_ARC_AUX_REGS
-	def_bool n
-
-config SPI_0
-	def_bool y
-
-if SPI_0
-
-config SPI_0_IRQ_PRI
-	default 0
-
-endif # SPI_0
-
-config SPI_1
-	def_bool y
-
-if SPI_1
-
-config SPI_1_IRQ_PRI
-	default 0
-
-endif # SPI_1
-
-endif # SPI_DW
-
-endif # SPI
-
 endif #SOC_EM11D

arch/arc/soc/em11d/Kconfig.soc

@@ -1,3 +1,5 @@
 
 config SOC_EM11D
 	bool "Synopsys ARC EM11D"
+	select CPU_HAS_FPU
+

arch/arc/soc/em11d/Makefile

@@ -1,2 +1,16 @@
-soc-cflags = $(call cc-option,-mARCv2EM) \
-                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)
+#  -mcpu=em4_fpuda is added to KBUILD_CFLAGS to make cc-option check the options correctly
+KBUILD_CFLAGS += -mcpu=em4_fpuda
+
+soc-cflags += $(call cc-option, -mcpu=em4_fpuda -mno-sdata -mdiv-rem -mswap -mnorm) \
+		$(call cc-option,-mmpy-option=6 -mbarrel-shifter) \
+		$(call cc-option,--param l1-cache-size=16384) \
+		$(call cc-option,--param l1-cache-line-size=32)
+
+ifeq ($(CONFIG_CODE_DENSITY), y)
+soc-cflags += $(call cc-option, -mcode-density)
+endif
+
+ifeq ($(CONFIG_FLOAT), y)
+soc-cflags += $(call cc-option, -mfpu=fpuda_all)
+endif
+

arch/arc/soc/em11d/linker.ld

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**

arch/arc/soc/em11d/soc.c

@@ -3,44 +3,12 @@
 /*
  * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * This module provides routines to initialize and support board-level hardware
  * for the ARC EM Starter kit board.
+ *
+ * Nothing to be done for now.
  */
-
-#include <nanokernel.h>
-#include "soc.h"
-#include <init.h>
-
-
-/**
- *
- * @brief perform basic hardware initialization
- *
- * Hardware initialized:
- * - interrupt unit
- *
- * RETURNS: N/A
- */
-static int em11d_arc_init(struct device *arg)
-{
-	ARG_UNUSED(arg);
-
-	_arc_v2_irq_unit_init();
-	return 0;
-}
-
-SYS_INIT(em11d_arc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em11d/soc.h

@@ -1,17 +1,7 @@
 /*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ * Copyright (c) 2016-2017 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,87 +11,74 @@
  * aspects for the target.
  */
 
-#ifndef _BOARD__H_
-#define _BOARD__H_
+#ifndef _SOC__H_
+#define _SOC__H_
 
 #include <misc/util.h>
 
 /* default system clock */
-
-#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
 /* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+#define SYSCLK_DEFAULT_IOSC_HZ			MHZ(50)
 
 
-/* IRQs */
+/* ARC EM Core IRQs */
+#define IRQ_TIMER0				16
+#define IRQ_TIMER1				17
 
-#define IRQ_TIMER0 16
-#define IRQ_TIMER1 17
+#define IRQ_CORE_DMA_COMPLETE			20
+#define IRQ_CORE_DMA_ERROR			21
 
 #ifndef _ASMLANGUAGE
 
 #include <misc/util.h>
 #include <drivers/rand32.h>
 
-#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
-#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+#define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
+#define ARCV2_TIMER0_INT_PRI			0
 
-#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
-#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+#define ARCV2_TIMER1_INT_LVL			IRQ_TIMER1
+#define ARCV2_TIMER1_INT_PRI			1
 
-#define INT_ENABLE_ARC					~(0x00000001 << 8)
-#define INT_ENABLE_ARC_BIT_POS				(8)
+#define CONFIG_ARCV2_TIMER1_INT_LVL		IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI		1
+
+#define INT_ENABLE_ARC				~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS			(8)
 
 /* I2C */
-
 /* I2C_0 is on Pmod2 connector */
-#define I2C_DW_0_BASE_ADDR                      0xF0004000
-#define I2C_DW_0_IRQ                            23
-
+#define I2C_DW_0_BASE_ADDR			0xF0004000
 
 /* I2C_1 is on Pmod4 connector */
-#define I2C_DW_1_BASE_ADDR                      0xF0005000
-#define I2C_DW_1_IRQ                            24
+#define I2C_DW_1_BASE_ADDR			0xF0005000
 
 #define I2C_DW_IRQ_FLAGS			0
 
 /* GPIO */
-#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
-#define GPIO_DW_0_IRQ                           22
-#define GPIO_DW_0_BITS                          32
-#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_BASE_ADDR			0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_BITS				32
+#define GPIO_DW_PORT_0_INT_MASK			0 /* n/a */
 #define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
 
-#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
-#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
-#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+#define GPIO_DW_1_BASE_ADDR			0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_BITS				9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
-#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_2_BITS                          32
-#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+#define GPIO_DW_2_BASE_ADDR			0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_BITS				32
+#define GPIO_DW_PORT_2_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
-#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_3_BITS                          12
-#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
-
-/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
-/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
-/* undef CONFIG_GPIO_DW_CLOCK_GATE */
-/* undef CONFIG_SOC_QUARK_SE_C1000_SS */
+#define GPIO_DW_3_BASE_ADDR			0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_BITS				12
+#define GPIO_DW_PORT_3_INT_MASK			0 /* n/a */
 
 /* SPI */
+#define SPI_DW_SPI_CLOCK			SYSCLK_DEFAULT_IOSC_HZ
 
-#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+#define SPI_DW_PORT_0_REGS			0xF0006000
+#define SPI_DW_PORT_1_REGS			0xF0007000
 
-#define SPI_DW_PORT_0_REGS   0xF0006000
-#define SPI_DW_PORT_1_REGS   0xF0007000
-
-#define SPI_DW_PORT_0_IRQ    25
-#define SPI_DW_PORT_1_IRQ    26
-
-#define SPI_DW_IRQ_FLAGS     0
+#define SPI_DW_IRQ_FLAGS			0
 
 /*
  * SPI Chip Select Assignments on EM Starter Kit
@@ -115,20 +92,46 @@
  */
 
 /*
- * UART
-     UART0 vector 27 0xF0008000
-     UART1 vector 28 0xF0009000
-     UART2 vector 29 0xF000A000
+ * UARTs: UART0 & UART1 & UART2
  */
-#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
-#define UART_NS16550_PORT_0_IRQ				27
-#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_0_BASE_ADDR		0xF0008000
+#define UART_NS16550_PORT_0_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
 
-#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
-#define UART_NS16550_PORT_1_IRQ				28
-#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_1_BASE_ADDR		0xF0009000
+#define UART_NS16550_PORT_1_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_2_BASE_ADDR		0xF000A000
+#define UART_NS16550_PORT_2_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_IRQ_FLAGS				0 /* Default */
+
+/**
+ * Peripheral Interrupt Connection Configurations
+ */
+#ifdef CONFIG_BOARD_EM_STARTERKIT_R23
+#define GPIO_DW_0_IRQ				24
+#define I2C_DW_0_IRQ				25
+#define I2C_DW_1_IRQ				26
+#define SPI_DW_PORT_0_IRQ			27
+#define SPI_DW_PORT_1_IRQ			28
+#define UART_NS16550_PORT_0_IRQ			29
+#define UART_NS16550_PORT_1_IRQ			30
+#define UART_NS16550_PORT_2_IRQ			31
+#else /* CONFIG_BOARD_EM_STARTERKIT_R23 */
+#define GPIO_DW_0_IRQ				22
+#define I2C_DW_0_IRQ				23
+#define I2C_DW_1_IRQ				24
+#define SPI_DW_PORT_0_IRQ			25
+#define SPI_DW_PORT_1_IRQ			26
+#define UART_NS16550_PORT_0_IRQ			27
+#define UART_NS16550_PORT_1_IRQ			28
+#define UART_NS16550_PORT_2_IRQ			29
+#endif /* !CONFIG_BOARD_EM_STARTERKIT_R23 */
+
+#define GPIO_DW_1_IRQ				0	/* can't interrupt */
+#define GPIO_DW_2_IRQ				0	/* can't interrupt */
+#define GPIO_DW_3_IRQ				0	/* can't interrupt */
 
-#define UART_IRQ_FLAGS					0 /* Default */
 #endif /* !_ASMLANGUAGE */
 
-#endif /* _BOARD__H_ */
+#endif /* _SOC__H_ */

arch/arc/soc/em11d/soc_config.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <device.h>

arch/arc/soc/em7d/Kbuild

@@ -5,4 +5,6 @@ ccflags-y +=-I$(srctree)/drivers
 
 asflags-y := ${ccflags-y}
 
-obj-y = soc.o soc_config.o
+obj-y += soc.o soc_config.o
+
+obj-$(CONFIG_ARC_MPU_ENABLE) += arc_mpu_regions.o

arch/arc/soc/em7d/Kconfig.defconfig

@@ -2,17 +2,7 @@
 # Copyright (c) 2014 Wind River Systems, Inc.
 # Copyright (c) 2016 Synopsys, Inc. All rights reserved.
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 
 if SOC_EM7D
@@ -23,19 +13,19 @@ config SOC
 config NUM_IRQ_PRIO_LEVELS
 	# This processor supports 4 priority levels:
 	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
-	# TODO: But regular irq nesting is not implemented --
-	# so this must be 2 for now.
-	default 2
+	default 4
 
 config NUM_IRQS
 	# must be > the highest interrupt number used
-	default 36
+	default 38 if BOARD_EM_STARTERKIT_R23
+	default 36 if BOARD_EM_STARTERKIT_R22
 
 config RGF_NUM_BANKS
 	default 1
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 30000000
+	default 25000000 if BOARD_EM_STARTERKIT_R23
+	default 30000000 if BOARD_EM_STARTERKIT_R22
 
 config HARVARD
 	def_bool n
@@ -68,192 +58,4 @@ config DCCM_SIZE
 config CACHE_FLUSHING
 	def_bool y
 
-if GPIO
-
-config GPIO_DW
-	def_bool y
-
-if GPIO_DW
-
-config GPIO_DW_0
-	def_bool y
-
-if GPIO_DW_0
-
-config GPIO_DW_0_NAME
-	default "GPIO_PORTA"
-
-config GPIO_DW_0_IRQ_PRI
-	default 1
-
-endif # GPIO_DW_0
-
-config GPIO_DW_1
-	def_bool y
-
-if GPIO_DW_1
-
-config GPIO_DW_1_NAME
-	default "GPIO_PORTB"
-
-config GPIO_DW_1_IRQ_PRI
-	default 1
-
-endif # GPIO_DW_1
-
-config GPIO_DW_2
-	def_bool y
-
-if GPIO_DW_2
-
-config GPIO_DW_2_IRQ_PRI
-	default 1
-
-config GPIO_DW_2_NAME
-	default "GPIO_PORTC"
-
-endif # GPIO_DW_2
-
-config GPIO_DW_3
-	def_bool y
-
-if GPIO_DW_3
-
-config GPIO_DW_3_IRQ_PRI
-	default 1
-
-config GPIO_DW_3_NAME
-	default "GPIO_PORTD"
-
-endif # GPIO_DW_3
-
-endif # GPIO_DW
-
-endif # GPIO
-
-if I2C
-
-config I2C_CLOCK_SPEED
-	default 100
-
-config I2C_DW
-	def_bool y
-
-if I2C_DW
-
-config I2C_0
-	def_bool y
-
-if I2C_0
-
-config I2C_0_NAME
-	default "I2C_0"
-config I2C_0_DEFAULT_CFG
-	default 0x3
-config I2C_0_IRQ_PRI
-	default 1
-
-endif # I2C_0
-
-config I2C_1
-	def_bool y
-
-if I2C_1
-
-config I2C_1_NAME
-	default "I2C_1"
-config I2C_1_DEFAULT_CFG
-	default 0x3
-config I2C_1_IRQ_PRI
-	default 1
-
-endif # I2C_1
-
-endif # I2C_DW
-
-endif # I2C
-
-if UART_NS16550
-
-config UART_NS16550_PORT_0
-	def_bool n
-
-if UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_0_NAME
-	default "UART_0"
-config UART_NS16550_PORT_0_IRQ_PRI
-	default 1
-config UART_NS16550_PORT_0_BAUD_RATE
-	default 115200
-config UART_NS16550_PORT_0_OPTIONS
-	default 0
-
-endif # UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_1
-	def_bool y
-
-if UART_NS16550_PORT_1
-
-config UART_NS16550_PORT_1_NAME
-	default "UART_1"
-config UART_NS16550_PORT_1_IRQ_PRI
-	default 1
-config UART_NS16550_PORT_1_BAUD_RATE
-	default 115200
-config UART_NS16550_PORT_1_OPTIONS
-	default 0
-
-endif # UART_NS16550_PORT_1
-
-endif # UART_NS16550
-
-if UART_CONSOLE
-
-config UART_CONSOLE_ON_DEV_NAME
-	default "UART_1"
-
-endif
-
-if SPI
-
-config SPI_DW
-	def_bool y
-
-if SPI_DW
-
-config SPI_DW_CLOCK_GATE
-	def_bool n
-
-config SPI_DW_FIFO_DEPTH
-	default 32
-
-config SPI_DW_ARC_AUX_REGS
-	def_bool n
-
-config SPI_0
-	def_bool y
-
-if SPI_0
-
-config SPI_0_IRQ_PRI
-	default 0
-
-endif # SPI_0
-
-config SPI_1
-	def_bool y
-
-if SPI_1
-
-config SPI_1_IRQ_PRI
-	default 0
-
-endif # SPI_1
-
-endif # SPI_DW
-
-endif # SPI
-
 endif #SOC_EM7D

arch/arc/soc/em7d/Kconfig.soc

@@ -1,3 +1,4 @@
 
 config SOC_EM7D
 	bool "Synopsys ARC EM7D"
+	select CPU_HAS_MPU

arch/arc/soc/em7d/Makefile

@@ -1,2 +1,16 @@
-soc-cflags = $(call cc-option,-mARCv2EM) \
-                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)
+#  -mcpu=em4_dmips is added to KBUILD_CFLAGS to make cc-option check the options correctly
+KBUILD_CFLAGS += -mcpu=em4_dmips
+
+soc-cflags += $(call cc-option,-mcpu=em4_dmips -mno-sdata) \
+		$(call cc-option,-mdiv-rem -mswap -mnorm) \
+		$(call cc-option,-mmpy-option=6 -mbarrel-shifter) \
+		$(call cc-option,--param l1-cache-size=16384) \
+		$(call cc-option,--param l1-cache-line-size=32)
+
+ifeq ($(CONFIG_CODE_DENSITY), y)
+soc-cflags += $(call cc-option,-mcode-density)
+endif
+
+ifeq ($(CONFIG_BOARD_EM_STARTERKIT_R23), y)
+$(error em7d from em starterkit 2.3 is not supported)
+endif

arch/arc/soc/em7d/arc_mpu_regions.c

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2017 Synopsys
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ #include <soc.h>
+ #include <arch/arc/v2/mpu/arc_mpu.h>
+
+static struct arc_mpu_region mpu_regions[] = {
+#if CONFIG_ICCM_SIZE > 0
+	/* Region ICCM */
+	MPU_REGION_ENTRY("ICCM",
+			 CONFIG_ICCM_BASE_ADDRESS,
+			 REGION_FLASH_ATTR(REGION_256K)),
+#endif
+#if CONFIG_DCCM_SIZE > 0
+	/* Region DCCM */
+	MPU_REGION_ENTRY("DCCM",
+			 CONFIG_DCCM_BASE_ADDRESS,
+			 REGION_RAM_ATTR(REGION_128K)),
+#endif
+#if CONFIG_SRAM_SIZE > 0
+	/* Region DDR RAM */
+	MPU_REGION_ENTRY("DDR RAM",
+			CONFIG_SRAM_BASE_ADDRESS,
+			REGION_ALL_ATTR(REGION_128M)),
+#endif
+	/* Region Peripheral */
+	MPU_REGION_ENTRY("PERIPHERAL",
+			 0xF0000000,
+			 REGION_IO_ATTR(REGION_64K)),
+};
+
+struct arc_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};

arch/arc/soc/em7d/linker.ld

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**

arch/arc/soc/em7d/soc.c

@@ -3,44 +3,12 @@
 /*
  * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * This module provides routines to initialize and support board-level hardware
  * for the ARC EM Starter kit board.
+ *
+ * Nothing to be done for now.
  */
-
-#include <nanokernel.h>
-#include "soc.h"
-#include <init.h>
-
-
-/**
- *
- * @brief perform basic hardware initialization
- *
- * Hardware initialized:
- * - interrupt unit
- *
- * RETURNS: N/A
- */
-static int em7d_arc_init(struct device *arg)
-{
-	ARG_UNUSED(arg);
-
-	_arc_v2_irq_unit_init();
-	return 0;
-}
-
-SYS_INIT(em7d_arc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em7d/soc.h

@@ -1,17 +1,7 @@
 /*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ * Copyright (c) 2016-2017 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,87 +11,83 @@
  * aspects for the target.
  */
 
-#ifndef _BOARD__H_
-#define _BOARD__H_
+#ifndef _SOC__H_
+#define _SOC__H_
 
 #include <misc/util.h>
 
 /* default system clock */
-
-#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
 /* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+#define SYSCLK_DEFAULT_IOSC_HZ			MHZ(50)
 
 
-/* IRQs */
+/* ARC EM Core IRQs */
+#define IRQ_TIMER0				16
+#define IRQ_TIMER1				17
 
-#define IRQ_TIMER0 16
-#define IRQ_TIMER1 17
+#if defined(CONFIG_BOARD_EM_STARTERKIT_R23) && defined(CONFIG_SOC_EM7D)
+#define IRQ_SEC_TIMER0				20
+#endif /* CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EM7D */
+
+#if defined(CONFIG_BOARD_EM_STARTERKIT_R23) && defined(CONFIG_SOC_EM7D)
+#define IRQ_CORE_DMA_COMPLETE			22
+#define IRQ_CORE_DMA_ERROR			23
+#else /* CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EM7D */
+#define IRQ_CORE_DMA_COMPLETE			20
+#define IRQ_CORE_DMA_ERROR			21
+#endif /* !(CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EM7D) */
 
 #ifndef _ASMLANGUAGE
 
 #include <misc/util.h>
 #include <drivers/rand32.h>
 
-#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
-#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+#define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
+#define ARCV2_TIMER0_INT_PRI			0
 
-#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
-#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+#define ARCV2_TIMER1_INT_LVL			IRQ_TIMER1
+#define ARCV2_TIMER1_INT_PRI			1
 
-#define INT_ENABLE_ARC					~(0x00000001 << 8)
-#define INT_ENABLE_ARC_BIT_POS				(8)
+#define CONFIG_ARCV2_TIMER1_INT_LVL		IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI		1
+
+#define INT_ENABLE_ARC				~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS			(8)
 
 /* I2C */
-
 /* I2C_0 is on Pmod2 connector */
-#define I2C_DW_0_BASE_ADDR                      0xF0004000
-#define I2C_DW_0_IRQ                            23
-
+#define I2C_DW_0_BASE_ADDR			0xF0004000
 
 /* I2C_1 is on Pmod4 connector */
-#define I2C_DW_1_BASE_ADDR                      0xF0005000
-#define I2C_DW_1_IRQ                            24
+#define I2C_DW_1_BASE_ADDR			0xF0005000
 
 #define I2C_DW_IRQ_FLAGS			0
 
 /* GPIO */
-#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
-#define GPIO_DW_0_IRQ                           22
-#define GPIO_DW_0_BITS                          32
-#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_BASE_ADDR			0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_BITS				32
+#define GPIO_DW_PORT_0_INT_MASK			0 /* n/a */
 #define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
 
-#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
-#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
-#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+#define GPIO_DW_1_BASE_ADDR			0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_BITS				9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
-#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_2_BITS                          32
-#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+#define GPIO_DW_2_BASE_ADDR			0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_BITS				32
+#define GPIO_DW_PORT_2_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
-#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_3_BITS                          12
-#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
-
-/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
-/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
-/* undef CONFIG_GPIO_DW_CLOCK_GATE */
-/* undef CONFIG_SOC_QUARK_SE_C1000_SS */
+#define GPIO_DW_3_BASE_ADDR			0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_BITS				12
+#define GPIO_DW_PORT_3_INT_MASK			0 /* n/a */
 
 /* SPI */
+#define SPI_DW_SPI_CLOCK			SYSCLK_DEFAULT_IOSC_HZ
 
-#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+#define SPI_DW_PORT_0_REGS			0xF0006000
+#define SPI_DW_PORT_1_REGS			0xF0007000
 
-#define SPI_DW_PORT_0_REGS   0xF0006000
-#define SPI_DW_PORT_1_REGS   0xF0007000
-
-#define SPI_DW_PORT_0_IRQ    25
-#define SPI_DW_PORT_1_IRQ    26
-
-#define SPI_DW_IRQ_FLAGS     0
+#define SPI_DW_IRQ_FLAGS			0
 
 /*
  * SPI Chip Select Assignments on EM Starter Kit
@@ -115,20 +101,46 @@
  */
 
 /*
- * UART
-     UART0 vector 27 0xF0008000
-     UART1 vector 28 0xF0009000
-     UART2 vector 29 0xF000A000
+ * UARTs: UART0 & UART1 & UART2
  */
-#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
-#define UART_NS16550_PORT_0_IRQ				27
-#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_0_BASE_ADDR		0xF0008000
+#define UART_NS16550_PORT_0_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
 
-#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
-#define UART_NS16550_PORT_1_IRQ				28
-#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_1_BASE_ADDR		0xF0009000
+#define UART_NS16550_PORT_1_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_2_BASE_ADDR		0xF000A000
+#define UART_NS16550_PORT_2_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_IRQ_FLAGS				0 /* Default */
+
+/**
+ * Peripheral Interrupt Connection Configurations
+ */
+#ifdef CONFIG_BOARD_EM_STARTERKIT_R23
+#define GPIO_DW_0_IRQ				24
+#define I2C_DW_0_IRQ				25
+#define I2C_DW_1_IRQ				26
+#define SPI_DW_PORT_0_IRQ			27
+#define SPI_DW_PORT_1_IRQ			28
+#define UART_NS16550_PORT_0_IRQ			29
+#define UART_NS16550_PORT_1_IRQ			30
+#define UART_NS16550_PORT_2_IRQ			31
+#else /* CONFIG_BOARD_EM_STARTERKIT_R23 */
+#define GPIO_DW_0_IRQ				22
+#define I2C_DW_0_IRQ				23
+#define I2C_DW_1_IRQ				24
+#define SPI_DW_PORT_0_IRQ			25
+#define SPI_DW_PORT_1_IRQ			26
+#define UART_NS16550_PORT_0_IRQ			27
+#define UART_NS16550_PORT_1_IRQ			28
+#define UART_NS16550_PORT_2_IRQ			29
+#endif /* !CONFIG_BOARD_EM_STARTERKIT_R23 */
+
+#define GPIO_DW_1_IRQ				0	/* can't interrupt */
+#define GPIO_DW_2_IRQ				0	/* can't interrupt */
+#define GPIO_DW_3_IRQ				0	/* can't interrupt */
 
-#define UART_IRQ_FLAGS					0 /* Default */
 #endif /* !_ASMLANGUAGE */
 
-#endif /* _BOARD__H_ */
+#endif /* _SOC__H_ */

arch/arc/soc/em7d/soc_config.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <device.h>

arch/arc/soc/em9d/Kconfig.defconfig

@@ -2,17 +2,7 @@
 # Copyright (c) 2014 Wind River Systems, Inc.
 # Copyright (c) 2016 Synopsys, Inc. All rights reserved.
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 
 if SOC_EM9D
@@ -23,13 +13,12 @@ config SOC
 config NUM_IRQ_PRIO_LEVELS
 	# This processor supports 4 priority levels:
 	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
-	# TODO: But regular irq nesting is not implemented --
-	# so this must be 2 for now.
-	default 2
+	default 4
 
 config NUM_IRQS
 	# must be > the highest interrupt number used
-	default 36
+	default 38 if BOARD_EM_STARTERKIT_R23
+	default 36 if BOARD_EM_STARTERKIT_R22
 
 config RGF_NUM_BANKS
 	default 2
@@ -66,192 +55,4 @@ config DCCM_BASE_ADDRESS
 config DCCM_SIZE
 	default 128
 
-if GPIO
-
-config GPIO_DW
-	def_bool y
-
-if GPIO_DW
-
-config GPIO_DW_0
-	def_bool y
-
-if GPIO_DW_0
-
-config GPIO_DW_0_NAME
-	default "GPIO_PORTA"
-
-config GPIO_DW_0_IRQ_PRI
-	default 1
-
-endif # GPIO_DW_0
-
-config GPIO_DW_1
-	def_bool y
-
-if GPIO_DW_1
-
-config GPIO_DW_1_NAME
-	default "GPIO_PORTB"
-
-config GPIO_DW_1_IRQ_PRI
-	default 1
-
-endif # GPIO_DW_1
-
-config GPIO_DW_2
-	def_bool y
-
-if GPIO_DW_2
-
-config GPIO_DW_2_IRQ_PRI
-	default 1
-
-config GPIO_DW_2_NAME
-	default "GPIO_PORTC"
-
-endif # GPIO_DW_2
-
-config GPIO_DW_3
-	def_bool y
-
-if GPIO_DW_3
-
-config GPIO_DW_3_IRQ_PRI
-	default 1
-
-config GPIO_DW_3_NAME
-	default "GPIO_PORTD"
-
-endif # GPIO_DW_3
-
-endif # GPIO_DW
-
-endif # GPIO
-
-if I2C
-
-config I2C_CLOCK_SPEED
-	default 100
-
-config I2C_DW
-	def_bool y
-
-if I2C_DW
-
-config I2C_0
-	def_bool y
-
-if I2C_0
-
-config I2C_0_NAME
-	default "I2C_0"
-config I2C_0_DEFAULT_CFG
-	default 0x3
-config I2C_0_IRQ_PRI
-	default 1
-
-endif # I2C_0
-
-config I2C_1
-	def_bool y
-
-if I2C_1
-
-config I2C_1_NAME
-	default "I2C_1"
-config I2C_1_DEFAULT_CFG
-	default 0x3
-config I2C_1_IRQ_PRI
-	default 1
-
-endif # I2C_1
-
-endif # I2C_DW
-
-endif # I2C
-
-if UART_NS16550
-
-config UART_NS16550_PORT_0
-	def_bool n
-
-if UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_0_NAME
-	default "UART_0"
-config UART_NS16550_PORT_0_IRQ_PRI
-	default 1
-config UART_NS16550_PORT_0_BAUD_RATE
-	default 115200
-config UART_NS16550_PORT_0_OPTIONS
-	default 0
-
-endif # UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_1
-	def_bool y
-
-if UART_NS16550_PORT_1
-
-config UART_NS16550_PORT_1_NAME
-	default "UART_1"
-config UART_NS16550_PORT_1_IRQ_PRI
-	default 1
-config UART_NS16550_PORT_1_BAUD_RATE
-	default 115200
-config UART_NS16550_PORT_1_OPTIONS
-	default 0
-
-endif # UART_NS16550_PORT_1
-
-endif # UART_NS16550
-
-if UART_CONSOLE
-
-config UART_CONSOLE_ON_DEV_NAME
-	default "UART_1"
-
-endif
-
-if SPI
-
-config SPI_DW
-	def_bool y
-
-if SPI_DW
-
-config SPI_DW_CLOCK_GATE
-	def_bool n
-
-config SPI_DW_FIFO_DEPTH
-	default 32
-
-config SPI_DW_ARC_AUX_REGS
-	def_bool n
-
-config SPI_0
-	def_bool y
-
-if SPI_0
-
-config SPI_0_IRQ_PRI
-	default 0
-
-endif # SPI_0
-
-config SPI_1
-	def_bool y
-
-if SPI_1
-
-config SPI_1_IRQ_PRI
-	default 0
-
-endif # SPI_1
-
-endif # SPI_DW
-
-endif # SPI
-
 endif #SOC_EM9D

arch/arc/soc/em9d/Kconfig.soc

@@ -1,3 +1,4 @@
 
 config SOC_EM9D
 	bool "Synopsys ARC EM9D"
+	select CPU_HAS_FPU

arch/arc/soc/em9d/Makefile

@@ -1,2 +1,14 @@
-soc-cflags = $(call cc-option,-mARCv2EM) \
-                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)
+#  -mcpu=em4_dmips is added to KBUILD_CFLAGS to make cc-option check the options correctly
+KBUILD_CFLAGS += -mcpu=em4_fpus
+
+soc-cflags += $(call cc-option,-mcpu=em4_fpus -mno-sdata) \
+		$(call cc-option,-mdiv-rem -mswap -mnorm) \
+		$(call cc-option,-mmpy-option=6 -mbarrel-shifter)
+
+ifeq ($(CONFIG_CODE_DENSITY), y)
+soc-cflags += $(call cc-option,-mcode-density)
+endif
+
+ifeq ($(CONFIG_FLOAT), y)
+soc-cflags += $(call cc-option,-mfpu=fpus_all)
+endif

arch/arc/soc/em9d/linker.ld

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**

arch/arc/soc/em9d/soc.c

@@ -3,44 +3,12 @@
 /*
  * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * This module provides routines to initialize and support board-level hardware
  * for the ARC EM Starter kit board.
+ *
+ * Nothing to be done for now.
  */
-
-#include <nanokernel.h>
-#include "soc.h"
-#include <init.h>
-
-
-/**
- *
- * @brief perform basic hardware initialization
- *
- * Hardware initialized:
- * - interrupt unit
- *
- * RETURNS: N/A
- */
-static int em9d_arc_init(struct device *arg)
-{
-	ARG_UNUSED(arg);
-
-	_arc_v2_irq_unit_init();
-	return 0;
-}
-
-SYS_INIT(em9d_arc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em9d/soc.h

@@ -1,17 +1,7 @@
 /*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ * Copyright (c) 2016-2017 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,87 +11,74 @@
  * aspects for the target.
  */
 
-#ifndef _BOARD__H_
-#define _BOARD__H_
+#ifndef _SOC__H_
+#define _SOC__H_
 
 #include <misc/util.h>
 
 /* default system clock */
-
-#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
 /* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+#define SYSCLK_DEFAULT_IOSC_HZ			MHZ(50)
 
 
-/* IRQs */
+/* ARC EM Core IRQs */
+#define IRQ_TIMER0				16
+#define IRQ_TIMER1				17
 
-#define IRQ_TIMER0 16
-#define IRQ_TIMER1 17
+#define IRQ_CORE_DMA_COMPLETE			20
+#define IRQ_CORE_DMA_ERROR			21
 
 #ifndef _ASMLANGUAGE
 
 #include <misc/util.h>
 #include <drivers/rand32.h>
 
-#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
-#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+#define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
+#define ARCV2_TIMER0_INT_PRI			0
 
-#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
-#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+#define ARCV2_TIMER1_INT_LVL			IRQ_TIMER1
+#define ARCV2_TIMER1_INT_PRI			1
 
-#define INT_ENABLE_ARC					~(0x00000001 << 8)
-#define INT_ENABLE_ARC_BIT_POS				(8)
+#define CONFIG_ARCV2_TIMER1_INT_LVL		IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI		1
+
+#define INT_ENABLE_ARC				~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS			(8)
 
 /* I2C */
-
 /* I2C_0 is on Pmod2 connector */
-#define I2C_DW_0_BASE_ADDR                      0xF0004000
-#define I2C_DW_0_IRQ                            23
-
+#define I2C_DW_0_BASE_ADDR			0xF0004000
 
 /* I2C_1 is on Pmod4 connector */
-#define I2C_DW_1_BASE_ADDR                      0xF0005000
-#define I2C_DW_1_IRQ                            24
+#define I2C_DW_1_BASE_ADDR			0xF0005000
 
 #define I2C_DW_IRQ_FLAGS			0
 
 /* GPIO */
-#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
-#define GPIO_DW_0_IRQ                           22
-#define GPIO_DW_0_BITS                          32
-#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_BASE_ADDR			0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_BITS				32
+#define GPIO_DW_PORT_0_INT_MASK			0 /* n/a */
 #define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
 
-#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
-#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
-#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+#define GPIO_DW_1_BASE_ADDR			0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_BITS				9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
-#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_2_BITS                          32
-#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+#define GPIO_DW_2_BASE_ADDR			0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_BITS				32
+#define GPIO_DW_PORT_2_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
-#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_3_BITS                          12
-#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
-
-/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
-/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
-/* undef CONFIG_GPIO_DW_CLOCK_GATE */
-/* undef CONFIG_SOC_QUARK_SE_C1000_SS */
+#define GPIO_DW_3_BASE_ADDR			0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_BITS				12
+#define GPIO_DW_PORT_3_INT_MASK			0 /* n/a */
 
 /* SPI */
+#define SPI_DW_SPI_CLOCK			SYSCLK_DEFAULT_IOSC_HZ
 
-#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+#define SPI_DW_PORT_0_REGS			0xF0006000
+#define SPI_DW_PORT_1_REGS			0xF0007000
 
-#define SPI_DW_PORT_0_REGS   0xF0006000
-#define SPI_DW_PORT_1_REGS   0xF0007000
-
-#define SPI_DW_PORT_0_IRQ    25
-#define SPI_DW_PORT_1_IRQ    26
-
-#define SPI_DW_IRQ_FLAGS     0
+#define SPI_DW_IRQ_FLAGS			0
 
 /*
  * SPI Chip Select Assignments on EM Starter Kit
@@ -115,20 +92,46 @@
  */
 
 /*
- * UART
-     UART0 vector 27 0xF0008000
-     UART1 vector 28 0xF0009000
-     UART2 vector 29 0xF000A000
+ * UARTs: UART0 & UART1 & UART2
  */
-#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
-#define UART_NS16550_PORT_0_IRQ				27
-#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_0_BASE_ADDR		0xF0008000
+#define UART_NS16550_PORT_0_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
 
-#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
-#define UART_NS16550_PORT_1_IRQ				28
-#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_1_BASE_ADDR		0xF0009000
+#define UART_NS16550_PORT_1_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_2_BASE_ADDR		0xF000A000
+#define UART_NS16550_PORT_2_CLK_FREQ		SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_IRQ_FLAGS				0 /* Default */
+
+/**
+ * Peripheral Interrupt Connection Configurations
+ */
+#ifdef CONFIG_BOARD_EM_STARTERKIT_R23
+#define GPIO_DW_0_IRQ				24
+#define I2C_DW_0_IRQ				25
+#define I2C_DW_1_IRQ				26
+#define SPI_DW_PORT_0_IRQ			27
+#define SPI_DW_PORT_1_IRQ			28
+#define UART_NS16550_PORT_0_IRQ			29
+#define UART_NS16550_PORT_1_IRQ			30
+#define UART_NS16550_PORT_2_IRQ			31
+#else /* CONFIG_BOARD_EM_STARTERKIT_R23 */
+#define GPIO_DW_0_IRQ				22
+#define I2C_DW_0_IRQ				23
+#define I2C_DW_1_IRQ				24
+#define SPI_DW_PORT_0_IRQ			25
+#define SPI_DW_PORT_1_IRQ			26
+#define UART_NS16550_PORT_0_IRQ			27
+#define UART_NS16550_PORT_1_IRQ			28
+#define UART_NS16550_PORT_2_IRQ			29
+#endif /* !CONFIG_BOARD_EM_STARTERKIT_R23 */
+
+#define GPIO_DW_1_IRQ				0	/* can't interrupt */
+#define GPIO_DW_2_IRQ				0	/* can't interrupt */
+#define GPIO_DW_3_IRQ				0	/* can't interrupt */
 
-#define UART_IRQ_FLAGS					0 /* Default */
 #endif /* !_ASMLANGUAGE */
 
-#endif /* _BOARD__H_ */
+#endif /* _SOC__H_ */

arch/arc/soc/em9d/soc_config.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <device.h>

arch/arc/soc/quark_se_c1000_ss/Kbuild

@@ -1,4 +1,3 @@
-ccflags-y +=-I$(srctree)/arch/x86/soc/intel_quark
 ccflags-y +=-I$(srctree)/include
 ccflags-y +=-I$(srctree)/include/drivers
 ccflags-y +=-I$(srctree)/drivers
@@ -6,4 +5,4 @@ ccflags-$(CONFIG_ADC) +=-I$(srctree)/drivers/adc
 
 asflags-y := ${ccflags-y}
 
-obj-y = soc.o soc_config.o power.o
+obj-y = soc.o soc_config.o soc_power.o power.o

arch/arc/soc/quark_se_c1000_ss/Kconfig

@@ -1,17 +1,7 @@
 #
 # Copyright (c) 2016 Intel Corporation
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 
 if ARC && SOC_QUARK_SE_C1000_SS

arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig

@@ -2,17 +2,7 @@
 # Copyright (c) 2014 Wind River Systems, Inc.
 # Copyright (c) 2015-2016 Intel Corporation
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 
 if SOC_QUARK_SE_C1000_SS
@@ -80,10 +70,20 @@ config RTC_0_IRQ_PRI
 
 endif # RTC
 
+if PWM
+config PWM_QMSI
+	def_bool y
+endif # PWM
+
+if PINMUX
+config PINMUX_QMSI
+	def_bool y
+endif
+
 if GPIO
 
 config GPIO_QMSI
-	def_bool y
+	def_bool n
 
 if GPIO_QMSI
 
@@ -92,6 +92,9 @@ config GPIO_QMSI_0
 
 if GPIO_QMSI_0
 
+config GPIO_QMSI_0_NAME
+	default "GPIO_2"
+
 config GPIO_QMSI_0_IRQ_PRI
 	default 1
 
@@ -102,6 +105,9 @@ config GPIO_QMSI_1
 
 if GPIO_QMSI_1
 
+config GPIO_QMSI_1_NAME
+	default "GPIO_3"
+
 config GPIO_QMSI_1_IRQ_PRI
 	default 1
 
@@ -119,6 +125,9 @@ config GPIO_QMSI_SS_0
 
 if GPIO_QMSI_SS_0
 
+config GPIO_QMSI_SS_0_NAME
+	default "GPIO_0"
+
 config GPIO_QMSI_SS_0_IRQ_PRI
 	default 1
 
@@ -129,6 +138,9 @@ config GPIO_QMSI_SS_1
 
 if GPIO_QMSI_SS_1
 
+config GPIO_QMSI_SS_1_NAME
+	default "GPIO_1"
+
 config GPIO_QMSI_SS_1_IRQ_PRI
 	default 1
 
@@ -141,40 +153,75 @@ endif # GPIO
 
 if I2C
 
-config I2C_QMSI_SS
-	def_bool y
+config I2C_QMSI
+	def_bool n
 
+if I2C_QMSI
 config I2C_0
 	def_bool y
 
 config I2C_0_NAME
-	default "I2C_0"
+	default "I2C_2"
+
+config I2C_0_IRQ_PRI
+	default 1
 
 config I2C_0_DEFAULT_CFG
 	default 0x12
 
-config I2C_0_IRQ_PRI
-	default 2
-
-if I2C_1
+config I2C_1
+	def_bool y
 
 config I2C_1_NAME
-	default "I2C_1"
+	default "I2C_3"
+
+config I2C_1_IRQ_PRI
+	default 1
 
 config I2C_1_DEFAULT_CFG
 	default 0x12
 
-config I2C_1_IRQ_PRI
+config I2C_SDA_SETUP
 	default 2
 
-endif # I2C_1
+config I2C_SDA_TX_HOLD
+	default 16
 
-config I2C_SDA_SETUP
+config I2C_SDA_RX_HOLD
+	default 24
+
+endif
+
+config I2C_QMSI_SS
+	def_bool y
+
+if I2C_QMSI_SS
+config I2C_SS_0
+	def_bool y
+
+config I2C_SS_0_NAME
+	default "I2C_0"
+
+config I2C_SS_0_DEFAULT_CFG
+	default 0x12
+
+config I2C_SS_1
+	def_bool y
+
+config I2C_SS_1_NAME
+	default "I2C_1"
+
+config I2C_SS_1_DEFAULT_CFG
+	default 0x12
+
+config I2C_SS_SDA_SETUP
 	default 2
 
 config I2C_SS_SDA_HOLD
 	default 10
 
+endif
+
 endif # I2C
 
 if ADC
@@ -182,11 +229,24 @@ config ADC_QMSI_SS
 	def_bool y
 endif
 
+if BT_H4
+
+config BT_UART_ON_DEV_NAME
+	default UART_QMSI_0_NAME
 
-if UART_QMSI
 config UART_QMSI_0
 	def_bool y
 
+config UART_QMSI_0_BAUDRATE
+	default 1000000
+
+config UART_QMSI_0_HW_FC
+	def_bool y
+
+endif # BT_H4
+
+if UART_QMSI
+
 if UART_QMSI_0
 
 config UART_QMSI_0_IRQ_PRI
@@ -215,19 +275,54 @@ endif
 
 if SPI
 
-config SPI_QMSI_SS
-	def_bool y
+config SPI_QMSI
+	def_bool n
 
+if SPI_QMSI
 config SPI_0
 	def_bool y
 
+config SPI_0_NAME
+	default "SPI_2"
+
 config SPI_0_IRQ_PRI
 	default 1
+
 config SPI_1
 	def_bool y
 
+config SPI_1_NAME
+	default "SPI_3"
+
 config SPI_1_IRQ_PRI
 	default 1
+
+endif
+
+config SPI_QMSI_SS
+	def_bool y
+
+if SPI_QMSI_SS
+config SPI_SS_0
+	def_bool y
+
+config SPI_SS_0_NAME
+	default "SPI_0"
+
+config SPI_SS_0_IRQ_PRI
+	default 1
+
+config SPI_SS_1
+	def_bool y
+
+config SPI_SS_1_NAME
+	default "SPI_1"
+
+config SPI_SS_1_IRQ_PRI
+	default 1
+
+endif
+
 endif # SPI
 
 if AIO_COMPARATOR

arch/arc/soc/quark_se_c1000_ss/Kconfig.soc

@@ -2,4 +2,5 @@
 config SOC_QUARK_SE_C1000_SS
 	bool "Intel Quark SE C1000- Sensor Sub System"
 	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select SYS_POWER_DEEP_SLEEP_SUPPORTED
 	select HAS_QMSI

arch/arc/soc/quark_se_c1000_ss/Makefile

@@ -1,8 +1,10 @@
-soc-cflags = $(call cc-option,-mARCv2EM) \
-                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)
+soc-cflags = $(call cc-option,-mcpu=quarkse_em) \
+             $(call cc-option,-mno-sdata)
+
 soc-aflags = $(soc-cflags)
 soc-cxxflags = $(soc-cflags)
 soc-cflags += -DQM_SENSOR=1
+soc-cflags += -I$(srctree)/arch/x86/soc/intel_quark
 
 ## FIXME
 SOC_SERIES = quark_se

arch/arc/soc/quark_se_c1000_ss/linker.ld

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**

arch/arc/soc/quark_se_c1000_ss/power.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2016 Intel Corporation.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <zephyr.h>
@@ -21,104 +11,95 @@
 #include <soc_power.h>
 #include <init.h>
 #include <kernel_structs.h>
+#include <soc.h>
 
+#include "power_states.h"
 #include "ss_power_states.h"
+#include "vreg.h"
 
-#define SLEEP_MODE_CORE_OFF (0x0)
-#define SLEEP_MODE_CORE_TIMERS_RTC_OFF (0x60)
-#define ENABLE_INTERRUPTS (BIT(4) | _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL))
+#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
+extern void _power_soc_sleep(void);
+extern void _power_soc_deep_sleep(void);
+extern void _power_soc_deep_sleep_2(void);
 
-#define ARC_SS1 (SLEEP_MODE_CORE_OFF | ENABLE_INTERRUPTS)
-#define ARC_SS2 (SLEEP_MODE_CORE_TIMERS_RTC_OFF | ENABLE_INTERRUPTS)
-
-#if (CONFIG_RTC)
-static unsigned int rtc_trigger;
-#endif
-#if (CONFIG_COUNTER)
-static unsigned int aonpt_trigger;
-#endif
-
-/* QMSI does not set the interrupt enable bit in the sleep operand.
- * For the time being, implement this in Zephyr.
- * This will be removed once QMSI is fixed.
- */
-static void enter_arc_state(int mode)
+static void _deep_sleep(enum power_states state)
 {
-	/* The sensor cannot be woken up with an edge triggered
-	 * interrupt from the RTC and the AON Counter.
-	 * Switch to Level triggered interrupts and restore
-	 * the setting when waking up.
-	 */
-#if (CONFIG_RTC)
-	rtc_trigger = _arc_v2_irq_unit_trigger_get(QM_IRQ_RTC_0_INT_VECTOR);
-	_arc_v2_irq_unit_trigger_set(QM_IRQ_RTC_0_INT_VECTOR,
-			_ARC_V2_INT_LEVEL);
-#endif
+	qm_power_soc_set_ss_restore_flag();
 
-#if (CONFIG_COUNTER)
-	aonpt_trigger = _arc_v2_irq_unit_trigger_get(QM_IRQ_AONPT_0_INT_VECTOR);
-	_arc_v2_irq_unit_trigger_set(QM_IRQ_AONPT_0_INT_VECTOR,
-			_ARC_V2_INT_LEVEL);
-#endif
-
-	/* Enter SSx */
-	__asm__ volatile("sleep %0"
-			: /* No output operands. */
-			: /* Input operands. */
-			"r"(mode));
+	switch (state) {
+	case SYS_POWER_STATE_DEEP_SLEEP_1:
+		_power_soc_sleep();
+		break;
+	case SYS_POWER_STATE_DEEP_SLEEP:
+		_power_soc_deep_sleep();
+		break;
+	default:
+		break;
+	}
 }
+#endif
 
 void _sys_soc_set_power_state(enum power_states state)
 {
 	switch (state) {
 	case SYS_POWER_STATE_CPU_LPS:
-		ss_power_soc_lpss_enable();
-		enter_arc_state(ARC_SS2);
+		qm_ss_power_soc_lpss_enable();
+		qm_ss_power_cpu_ss2();
 		break;
 	case SYS_POWER_STATE_CPU_LPS_1:
-		enter_arc_state(ARC_SS2);
+		qm_ss_power_cpu_ss2();
 		break;
 	case SYS_POWER_STATE_CPU_LPS_2:
-		enter_arc_state(ARC_SS1);
+		qm_ss_power_cpu_ss1(QM_SS_POWER_CPU_SS1_TIMER_ON);
 		break;
+#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
 	case SYS_POWER_STATE_DEEP_SLEEP:
 	case SYS_POWER_STATE_DEEP_SLEEP_1:
-		/* Sleep states are not yet supported for ARC. */
+		_deep_sleep(state);
 		break;
+	case SYS_POWER_STATE_DEEP_SLEEP_2:
+		qm_ss_power_soc_lpss_enable();
+		qm_power_soc_set_ss_restore_flag();
+		_power_soc_deep_sleep_2();
+		break;
+#endif
 	default:
 		break;
 	}
 }
 
-static void restore_interrupt_trigger(void)
-{
-	/* Restore the RTC and AONC interrupt trigger after wake up */
-#if (CONFIG_RTC)
-	_arc_v2_irq_unit_trigger_set(QM_IRQ_RTC_0_INT_VECTOR, rtc_trigger);
-#endif
-
-#if (CONFIG_COUNTER)
-	_arc_v2_irq_unit_trigger_set(QM_IRQ_AONPT_0_INT_VECTOR, aonpt_trigger);
-#endif
-}
-
 void _sys_soc_power_state_post_ops(enum power_states state)
 {
-	uint32_t limit;
+	u32_t limit;
 
 	switch (state) {
-	case SYS_POWER_STATE_CPU_LPS_2:
-		/* Restore interrupts to their previous trigger type. */
-		restore_interrupt_trigger();
-		break;
 	case SYS_POWER_STATE_CPU_LPS:
-		ss_power_soc_lpss_disable();
+		qm_ss_power_soc_lpss_disable();
 	case SYS_POWER_STATE_CPU_LPS_1:
-		restore_interrupt_trigger();
 		/* Expire the timer as it is disabled in SS2. */
 		limit = _arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT);
 		_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, limit - 1);
 		break;
+	case SYS_POWER_STATE_DEEP_SLEEP:
+	case SYS_POWER_STATE_DEEP_SLEEP_1:
+		__builtin_arc_seti(0);
+		break;
+	case SYS_POWER_STATE_DEEP_SLEEP_2:
+		qm_ss_power_soc_lpss_disable();
+
+		/* If flag is cleared it means the system entered in
+		 * sleep state while we were in LPS. In that case, we
+		 * must set ARC_READY flag so x86 core can continue
+		 * its execution.
+		 */
+		if ((QM_SCSS_GP->gp0 & GP0_BIT_SLEEP_READY) == 0) {
+			_quark_se_ss_ready();
+			__builtin_arc_seti(0);
+		} else {
+			QM_SCSS_GP->gp0 &= ~GP0_BIT_SLEEP_READY;
+			QM_SCSS_GP->gps0 &= ~QM_GPS0_BIT_SENSOR_WAKEUP;
+		}
+		break;
 	default:
 		break;
 	}

arch/arc/soc/quark_se_c1000_ss/soc.c

@@ -3,17 +3,7 @@
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,28 +11,22 @@
  * for the Quark SE platform.
  */
 
-#include <nanokernel.h>
+#include <kernel.h>
 #include "soc.h"
 #include <init.h>
-#include <quark_se/shared_mem.h>
-
 
 /**
- *
  * @brief perform basic hardware initialization
  *
- * Hardware initialized:
- * - interrupt unit
- *
  * RETURNS: N/A
  */
 static int quark_se_arc_init(struct device *arg)
 {
 	ARG_UNUSED(arg);
 
-	_arc_v2_irq_unit_init();
-	shared_data->flags |= ARC_READY;
+	_quark_se_ss_ready();
+
 	return 0;
 }
 
-SYS_INIT(quark_se_arc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+SYS_INIT(quark_se_arc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/quark_se_c1000_ss/soc.h

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -116,6 +106,7 @@
 
 #include <misc/util.h>
 #include <drivers/rand32.h>
+#include <quark_se/shared_mem.h>
 
 #define INT_ENABLE_ARC					~(0x00000001 << 8)
 #define INT_ENABLE_ARC_BIT_POS				(8)
@@ -159,6 +150,9 @@
 #if defined(CONFIG_IOAPIC)
 #define GPIO_DW_0_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
 #define GPIO_DW_1_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
+#else
+#define GPIO_DW_0_IRQ_FLAGS			0
+#define GPIO_DW_1_IRQ_FLAGS			0
 #endif
 
 /*
@@ -194,6 +188,11 @@
 
 #define SPI_DW_IRQ_FLAGS				0
 
+static inline void _quark_se_ss_ready(void)
+{
+	shared_data->flags |= ARC_READY;
+}
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _BOARD__H_ */

arch/arc/soc/quark_se_c1000_ss/soc_config.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2015 Intel Corporation
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <device.h>

arch/arc/soc/quark_se_c1000_ss/soc_power.S

@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2016 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <toolchain.h>
+#include <arch/arc/v2/aux_regs.h>
+#include <swap_macros.h>
+
+#ifdef CONFIG_SYS_POWER_DEEP_SLEEP
+GDATA(_pm_arc_context)
+
+GTEXT(_sys_soc_resume_from_deep_sleep)
+GTEXT(_power_restore_cpu_context)
+GTEXT(_power_soc_sleep)
+GTEXT(_power_soc_deep_sleep)
+GTEXT(_power_soc_deep_sleep_2)
+
+#define GPS0_REGISTER  0xb0800100
+#define GP0_REGISTER 0xb0800114
+#define GP0_BIT_SLEEP_READY 0
+#define RESTORE_SS_BIT 2
+#define SLEEP_INTR_ENABLED_BIT 4
+#define SLEEP_MODE_RTC_ENABLED_BIT 5
+
+SECTION_FUNC(TEXT, _sys_soc_resume_from_deep_sleep)
+        /* Check is this wakeup after sleep event. */
+        ld r0,[GPS0_REGISTER]
+        bbit1 r0,RESTORE_SS_BIT,restore
+	j_s [blink] /* Jump to context of BLINK register. */
+
+restore:
+        bclr_s r0,r0,RESTORE_SS_BIT
+        st r0,[GPS0_REGISTER]
+
+	/* Enable I-Cache */
+        sr 1, [_ARC_V2_IC_CTRL]
+
+	j @_sys_soc_restore_cpu_context
+
+SECTION_FUNC(TEXT, save_cpu_context)
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+
+	_save_callee_saved_regs
+
+	j_s [blink] /* Jump to context of BLINK register. */
+
+SECTION_FUNC(TEXT, _power_soc_sleep)
+	/*
+	 * Save the return address.
+	 * The restore function will pop this and jump
+	 * back to the caller.
+	 */
+	push_s blink
+
+	/* Do not link to preserve blink */
+	jl @save_cpu_context
+	j @qm_power_soc_sleep
+	/* Does not return */
+
+SECTION_FUNC(TEXT, _power_soc_deep_sleep)
+	/*
+	 * Save the return address.
+	 * The restore function will pop this and jump
+	 * back to the caller.
+	 */
+	push_s blink
+
+	/* Do not link to preserve blink */
+	jl @save_cpu_context
+	j @qm_power_soc_deep_sleep
+	/* Does not return */
+
+SECTION_FUNC(TEXT, _power_soc_deep_sleep_2)
+	/*
+	 * Setup 'sleep' instruction operand.
+	 */
+
+	/* Get interrupt priority from status32 registers. */
+	lr r0, [_ARC_V2_STATUS32]
+	lsr r0, r0
+	and r0, r0, 0xF
+
+	/* Enable interrupts */
+	bset r0, r0, SLEEP_INTR_ENABLED_BIT
+
+	/* Set 'sleep' mode corresponding to SS2 state i.e. core disabled,
+	 * timers disabled, RTC enabled.
+	 */
+	bset r0, r0, SLEEP_MODE_RTC_ENABLED_BIT
+
+	/*
+	 * Save the return address.
+	 * The restore function will pop this and jump
+	 * back to the caller.
+	 */
+	push_s blink
+
+	jl @save_cpu_context
+
+	ld r1, [GP0_REGISTER]
+	bset r1, r1, GP0_BIT_SLEEP_READY
+	st r1, [GP0_REGISTER]
+	sleep r0
+
+	/* If we reach this code it means the x86 core didn't put the
+	 * system in SYS_POWER_STATE_DEEP_SLEEP_2 state while we were
+	 * in LPS. Then discard saved context.
+	 */
+	_discard_callee_saved_regs
+
+	pop_s blink
+	j_s [blink]
+
+SECTION_FUNC(TEXT, _sys_soc_restore_cpu_context)
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+
+	_load_callee_saved_regs
+
+	/* Restore return address */
+	pop_s blink
+
+	j_s [blink] /* Jump to context of BLINK register. */
+#endif

arch/arc/soc/quark_se_c1000_ss/soc_power.h

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2016 Intel Corporation.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 #ifndef _SOC_POWER_H_
@@ -21,12 +11,24 @@
 extern "C" {
 #endif
 
+/*
+ * Bit 0 from GP0 register is used internally by the kernel
+ * to handle PM multicore support. Any change on QMSI and/or
+ * bootloader which affects this bit should take it in
+ * consideration.
+ */
+#define GP0_BIT_SLEEP_READY BIT(0)
+
 enum power_states {
 	SYS_POWER_STATE_CPU_LPS,       /* SS2 with LPSS enabled state */
 	SYS_POWER_STATE_CPU_LPS_1,     /* SS2 state */
 	SYS_POWER_STATE_CPU_LPS_2,     /* SS1 state with Timer ON */
 	SYS_POWER_STATE_DEEP_SLEEP,    /* DEEP SLEEP state */
 	SYS_POWER_STATE_DEEP_SLEEP_1,  /* SLEEP state */
+	SYS_POWER_STATE_DEEP_SLEEP_2,  /* Multicore DEEP SLEEP state.
+					* Execution context is saved
+					* and core enters in LPS state.
+					*/
 	SYS_POWER_STATE_MAX
 };
 
@@ -52,6 +54,9 @@ enum power_states {
  * SYS_POWER_STATE_DEEP_SLEEP_1: Only Always-On peripherals can wake up
  * the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.
  *
+ * SYS_POWER_STATE_DEEP_SLEEP_2: Only Always-On peripherals can wake up
+ * the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.
+ *
  * Considerations around SYS_POWER_STATE_CPU_LPS (LPSS state):
  * -----------------------------------------------------------
  *

arch/arm/Kconfig

@@ -3,17 +3,7 @@
 #
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 
 choice

arch/arm/Makefile

@@ -57,9 +57,3 @@ KBUILD_CFLAGS += $(soc-cflags)
 KBUILD_CXXFLAGS += $(soc-cxxflags)
 KBUILD_AFLAGS += $(soc-aflags)
 
-QEMU_CPU_TYPE_arm = cortex-m3
-QEMU_FLAGS_arm = -cpu  $(QEMU_CPU_TYPE_arm) \
-		-machine lm3s6965evb -nographic -vga none
-QEMU_arm = qemu-system-arm
-
-export QEMU_FLAGS_arm QEMU_arm