release: Update release notes with GitHub issues

List all issues closed after the date of the 1.10 release (8th December
2017).

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>

.checkpatch.conf

@@ -5,6 +5,7 @@
 --show-types
 --max-line-length=80
 --min-conf-desc-length=1
+--typedefsfile=scripts/checkpatch/typedefsfile
 
 --ignore BRACES
 --ignore PRINTK_WITHOUT_KERN_LEVEL

.codecov.yml

@@ -0,0 +1,31 @@
+codecov:
+  notify:
+    require_ci_to_pass: yes
+
+coverage:
+  precision: 2
+  round: down
+  range: "70...100"
+
+  status:
+    project: yes
+    patch: yes
+    changes: no
+
+#ignore:
+#  - "tests/**/*"
+#  - "samples/**/*"
+#  - "ext/hal/**/*"
+
+parsers:
+  gcov:
+    branch_detection:
+      conditional: yes
+      loop: yes
+      method: no
+      macro: no
+
+comment:
+  layout: "reach, diff, flags, files, footer"
+  behavior: default
+  require_changes: no

.gitignore

@@ -7,6 +7,8 @@
 *.swp
 *.swo
 *~
+build
+build-*
 cscope.*
 .dir
 outdir
@@ -30,8 +32,10 @@ sanity-out/
 scripts/grub
 doc/reference/kconfig/CONFIG_*
 doc/reference/kconfig/index.rst
+doc/doc.warnings
 tags
 .project
 .cproject
 .xxproject
 .envrc
+.vscode

.gitlint

@@ -1,6 +1,6 @@
 # All these sections are optional, edit this file as you like.
 [general]
-ignore=title-trailing-punctuation, T3, title-max-length, T1
+ignore=title-trailing-punctuation, T3, title-max-length, T1, body-hard-tab, B3, B1
 # verbosity should be a value between 1 and 3, the commandline -v flags take precedence over this
 verbosity = 3
 # By default gitlint will ignore merge commits. Set to 'false' to disable.
@@ -15,6 +15,9 @@ extra-path=scripts/gitlint
 [title-max-length-no-revert]
 line-length=72
 
+[body-min-line-count]
+min-line-count=1
+
 [body-max-line-count]
 max-line-count=200
 
@@ -25,7 +28,7 @@ regex = ^(([^:]+):)(\s([^:]+):)*\s(.+)$
 # Comma-separated list of words that should not occur in the title. Matching is case
 # insensitive. It's fine if the keyword occurs as part of a larger word (so "WIPING"
 # will not cause a violation, but "WIP: my title" will.
-words=wip,title
+words=wip
 
 [title-match-regex]
 # python like regex (https://docs.python.org/2/library/re.html) that the

.known-issues/doc/bluetooth.conf

@@ -37,6 +37,14 @@
 ^.*bt_gatt_read_params.__unnamed__.*
 ^[- \t]*\^
 #
-# Bluetooth packed
+# Bluetooth mesh unnamed struct definition
 #
-^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: cpp:typeOrConcept targets a member \(__packed\).$
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_mesh_model.__unnamed__.*
+^[- \t]*\^

.known-issues/doc/display.conf

@@ -0,0 +1,15 @@
+#
+# Display
+#
+#
+# include
+#
+^(?P<filename>[-._/\w]+/doc/api/display_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*mb_image.__unnamed__
+^[- \t]*\^

.known-issues/doc/header_footer.conf

@@ -1,18 +0,0 @@
-#
-# KERNELVERSION not being defined in local builds, kill that warning,
-# can ignore it
-#
-^.*/Kconfig.zephyr:[0-9]+: warning: The symbol KERNELVERSION references the non-existent environment variable KERNELVERSION.*
-#
-# Documentation generation, early message
-#
-^cd .* && doxygen doc/doxygen.config
-^srctree=.* SRCARCH=\w+ python scripts/genrest/genrest.py .*$
-# This cuts the sphinx build line; has to be separate because in the
-# middle, we have removed the KERNELVERSION one and a full regex won't match
-^sphinx-build -t \w+ -b html .*
-#
-# Documentation generation, footer message
-#
-^[ \t]*
-^Build finished. The HTML pages are in [-._/\w]+

.known-issues/doc/kernel.conf

@@ -1,14 +1,24 @@
 #
-# Kernel unnamed struct definition
+# Kernel
 #
-# FIXME: all these should match the relative filename
 #
-^(?P<filename>[-._/\w]+/doc/api/kernel_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
-^[ \t]*$
-^[ \t]*\^$
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
-^[ \t]*$
-^[ \t]*\^$
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]$
-^.*k_msg.extra.*$
-^[- \t]*\^$
+# include/kernel.h warnings
+#
+^(?P<filename>[-._/\w]+/doc/api/kernel_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*k_poll_event.__unnamed__
+^[- \t]*\^

.known-issues/doc/misc.conf

@@ -0,0 +1,15 @@
+#
+# Display
+#
+#
+# include
+#
+^(?P<filename>[-._/\w]+/doc/api/misc_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*json_obj_descr.__unnamed__
+^[- \t]*\^

.known-issues/doc/networking.conf

@@ -17,25 +17,6 @@
 ^.*in[_6]+addr.in[46]_u
 ^[- \t]*\^
 #
-# include/net/net_if.h warnings
-#
-^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Error when parsing function declaration.
-^\If the function has no return type:
-^[ \t]*Error in declarator or parameters and qualifiers
-^[ \t]*Invalid definition: Expected identifier in nested name, got keyword: struct \[error at [0-9]+]
-^.*struct net_if __aligned\(32\)
-^[- \t]*\^
-^\If the function has a return type:
-^[ \t]*Error in declarator or parameters and qualifiers
-^[ \t]*If pointer to member declarator:
-^[ \t]*Invalid definition: Expected \'::\' in pointer to member \(function\). \[error at [0-9]+]
-^.*struct net_if __aligned\(32\)
-^[- \t]*\^
-^[ \t]*If declarator-id:
-^[ \t]*Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^.*struct net_if __aligned\(32\)
-^[- \t]*\^
-#
 # include/net/net_mgmt.h
 #
 ^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
@@ -71,43 +52,3 @@
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
 ^.*ieee802154_req_params.__unnamed__
 ^[- \t]*\^
-#
-# Various warning about net_mgmt declarations
-#
-^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Error when parsing function declaration\.
-^If the function has no return type\:
-^[ \t]*Error in declarator or parameters and qualifiers
-^[ \t]*Invalid definition: Expected identifier in nested name\. \[error at [0-9]+\]
-^[ \t]*NET_MGMT_DEFINE_.*?$
-^[- \t]*\^
-#
-^If the function has a return type\:
-^[ \t]*Error in declarator
-^[ \t]*If pointer to member declarator:
-^[ \t]*Invalid definition: Expected identifier in nested name\. \[error at [0-9]+\]
-^[ \t]*NET_MGMT_DEFINE_.*?$
-^[- \t]*\^
-#
-^[ \t]*If declId, parameters, and qualifiers\:
-^[ \t]*Invalid definition: Expected identifier in nested name\. \[error at [0-9]+\]
-^[ \t]*NET_MGMT_DEFINE_.*?$
-^[- \t]*\^
-#
-^[ \t]*If parenthesis in noptr-declarator\:
-^[ \t]*Error in declarator
-^[ \t]*If pointer to member declarator:
-^[ \t]*Invalid definition: Expected identifier in nested name\. \[error at [0-9]+\]
-^[ \t]*NET_MGMT_DEFINE_.*?$
-^[- \t]*\^
-#
-^[ \t]*If parenthesis in noptr-declarator\:
-^[ \t]*Error in declarator or parameters and qualifiers
-^[ \t]*If pointer to member declarator:
-^[ \t]*Invalid definition: Expected \'\:\:\' in pointer to member \(function\)\. \[error at [0-9]+\]
-^[ \t]*NET_MGMT_DEFINE_.*?$
-^[- \t]*\^
-#
-^[ \t]*If declarator-id:
-^[ \t]*Invalid definition: Expecting \"\(\" in parameters_and_qualifiers\. \[error at [0-9]+\]
-^[ \t]*NET_MGMT_DEFINE_.*?$
-^[- \t]*\^

.known-issues/doc/sensor.conf

@@ -1,12 +0,0 @@
-#
-# Sensor value unnamed struct definition
-#
-^(?P<filename>[-._/\w]+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*sensor_value.__unnamed__.*
-^[- \t]*\^

.shippable.yml

@@ -4,18 +4,18 @@ compiler: gcc
 
 env:
     global:
-        - SDK=0.9.1
-        - SANITYCHECK_OPTIONS=" --inline-logs -R"
+        - SDK=0.9.2
+        - SANITYCHECK_OPTIONS=" --inline-logs"
         - SANITYCHECK_OPTIONS_RETRY="${SANITYCHECK_OPTIONS} --only-failed --outdir=out-2nd-pass"
-        - ZEPHYR_SDK_INSTALL_DIR=/opt/sdk/zephyr-sdk-0.9.1
-        - ZEPHYR_GCC_VARIANT=zephyr
-        - USE_CCACHE=1
-        - MATRIX_BUILDS="2"
-        - MATRIX_BUILDS_EXTRA="3"
+        - ZEPHYR_SDK_INSTALL_DIR=/opt/sdk/zephyr-sdk-0.9.2
+        - ZEPHYR_TOOLCHAIN_VARIANT=zephyr
+        - MATRIX_BUILDS="4"
+        - MATRIX_BUILDS_EXTRA="4"
     matrix:
         - MATRIX_BUILD="1"
         - MATRIX_BUILD="2"
         - MATRIX_BUILD="3"
+        - MATRIX_BUILD="4"
 
 build:
     cache: true
@@ -23,58 +23,70 @@ build:
         - ${SHIPPABLE_BUILD_DIR}/ccache
     pre_ci_boot:
         image_name: zephyrprojectrtos/ci
-        image_tag: master.27
+        image_tag: v0.3
         pull: true
         options: "-e HOME=/home/buildslave --privileged=true --tty --net=bridge --user buildslave"
 
     ci:
       - export CCACHE_DIR=${SHIPPABLE_BUILD_DIR}/ccache/.ccache
-      - git rebase origin/${PULL_REQUEST_BASE_BRANCH}
+      - >
+        if [ "$IS_PULL_REQUEST" = "true" ]; then
+          git rebase origin/${PULL_REQUEST_BASE_BRANCH};
+        fi
       - source zephyr-env.sh
       - ccache -c -s --max-size=2000M
-      - make host-tools
-      - export PREBUILT_HOST_TOOLS=${ZEPHYR_BASE}/bin
       - >
-          if [ "$MATRIX_BUILD" = "3" -a "$IS_PULL_REQUEST" = "true" ]; then
+          if [ "$MATRIX_BUILD" = "4" -a "$IS_PULL_REQUEST" = "true" ]; then
             export COMMIT_RANGE=origin/${PULL_REQUEST_BASE_BRANCH}..HEAD
             echo "Building a Pull Request";
             echo "- Building Documentation";
             echo "Commit range:" ${COMMIT_RANGE}
-            make htmldocs > doc.log 2>&1;
-            ./scripts/filter-known-issues.py --config-dir .known-issues/doc/ doc.log > doc.warnings;
-
-            if [ "$?" != 0 ]; then
-              echo " ==> Error running filter script"
-              exit 1
-            fi;
-            if [ -s doc.warnings ]; then
+            make htmldocs
+            if [ "$?" != "0" ]; then
+              echo "Documentation build failed";
+              exit 1;
+            fi
+            if [ -s doc/doc.warnings ]; then
               echo " => New documentation warnings/errors";
+              cp doc/doc.warnings doc.warnings
             fi;
-            echo "- Verify commit message and coding style";
+            echo "- Verify commit message, coding style, doc build";
             ./scripts/ci/check-compliance.py --commits ${COMMIT_RANGE} || true;
           fi;
       - >
-          sudo pip3 install sh;
-          ./scripts/ci/get_modified_tests.py --commits origin/${PULL_REQUEST_BASE_BRANCH}..HEAD > modified_tests.args;
-          ./scripts/ci/get_modified_boards.py --commits origin/${PULL_REQUEST_BASE_BRANCH}..HEAD > modified_boards.args;
+          if [ "$IS_PULL_REQUEST" = "true" ]; then
+            ./scripts/ci/get_modified_tests.py --commits origin/${PULL_REQUEST_BASE_BRANCH}..HEAD > modified_tests.args;
+            ./scripts/ci/get_modified_boards.py --commits origin/${PULL_REQUEST_BASE_BRANCH}..HEAD > modified_boards.args;
 
-          if [ -s modified_boards.args ]; then
-            ./scripts/sanitycheck --subset ${MATRIX_BUILD}/${MATRIX_BUILDS_EXTRA} +modified_boards.args || ./scripts/sanitycheck +modified_boards.args --only-failed;
-            cp ./scripts/sanity_chk/last_sanity.xml modified_boards.xml;
-          fi;
-          if [ -s modified_tests.args ]; then
-            ./scripts/sanitycheck --subset ${MATRIX_BUILD}/${MATRIX_BUILDS_EXTRA} +modified_tests.args || ./scripts/sanitycheck +modified_tests.args --only-failed
-            cp ./scripts/sanity_chk/last_sanity.xml modified_tests.xml;
-          fi;
-          rm -f modified_tests.args modified_boards.args;
-      - >
-          if [ "$MATRIX_BUILD" != "3" ]; then
-             ./scripts/sanitycheck ${PLATFORMS} --subset ${MATRIX_BUILD}/${MATRIX_BUILDS} ${COVERAGE} ${SANITYCHECK_OPTIONS} || ./scripts/sanitycheck ${PLATFORMS} ${COVERAGE} ${SANITYCHECK_OPTIONS_RETRY} || ./scripts/sanitycheck ${PLATFORMS} ${COVERAGE} ${SANITYCHECK_OPTIONS_RETRY}
+            if [ -s modified_boards.args ]; then
+              ./scripts/sanitycheck ${SANITYCHECK_OPTIONS} +modified_boards.args --save-tests test_file.txt;
+            fi;
+            if [ -s modified_tests.args ]; then
+              ./scripts/sanitycheck ${SANITYCHECK_OPTIONS} +modified_tests.args --save-tests test_file.txt;
+            fi;
+            rm -f modified_tests.args modified_boards.args;
           fi;
+      - ./scripts/sanitycheck ${SANITYCHECK_OPTIONS} --save-tests test_file.txt
+      - ./scripts/sanitycheck ${SANITYCHECK_OPTIONS} --load-tests test_file.txt --subset ${MATRIX_BUILD}/${MATRIX_BUILDS} || ./scripts/sanitycheck ${SANITYCHECK_OPTIONS_RETRY} || ./scripts/sanitycheck ${SANITYCHECK_OPTIONS_RETRY}
+      - rm test_file.txt
       - ccache -s
     on_failure:
-      - rm -rf sanity-out out-2nd-pass
+      - rm -rf ccache
       - mkdir -p shippable/testresults
+      - mkdir -p shippable/codecoverage
+      - source zephyr-env.sh
+      - >
+         if [ "$MATRIX_BUILD" = "1" ]; then
+            gcovr -r ${ZEPHYR_BASE} -x > shippable/codecoverage/coverage.xml;
+            lcov --capture --directory sanity-out/native_posix/ --directory sanity-out/unit_testing/ --output-file lcov.pre.info -q --rc lcov_branch_coverage=1;
+            lcov -q --remove lcov.pre.info *generated* -o lcov.info --rc lcov_branch_coverage=1;
+            rm lcov.pre.info;
+            rm -rf sanity-out out-2nd-pass;
+            bash <(curl -s https://codecov.io/bash) -f "lcov.info" -X coveragepy -X fixes;
+            rm lcov.info;
+         else
+            rm -rf sanity-out out-2nd-pass;
+         fi;
       - >
           if [ -e compliance.xml ]; then
             cp compliance.xml shippable/testresults/;
@@ -83,13 +95,23 @@ build:
           if [ -e ./scripts/sanity_chk/last_sanity.xml ]; then
             cp ./scripts/sanity_chk/last_sanity.xml shippable/testresults/;
           fi;
-      - >
-          if [ -e ./modified_tests.xml ]; then
-            cp ./modified_tests.xml shippable/testresults/;
-          fi;
     on_success:
-      - rm -rf sanity-out out-2nd-pass
+      - rm -rf ccache
       - mkdir -p shippable/testresults
+      - mkdir -p shippable/codecoverage
+      - source zephyr-env.sh
+      - >
+         if [ "$MATRIX_BUILD" = "1" ]; then
+            gcovr -r ${ZEPHYR_BASE} -x > shippable/codecoverage/coverage.xml;
+            lcov --capture --directory sanity-out/native_posix/ --directory sanity-out/unit_testing/ --output-file lcov.pre.info -q --rc lcov_branch_coverage=1;
+            lcov -q --remove lcov.pre.info *generated* -o lcov.info --rc lcov_branch_coverage=1;
+            rm lcov.pre.info;
+            rm -rf sanity-out out-2nd-pass;
+            bash <(curl -s https://codecov.io/bash) -f "lcov.info" -X coveragepy -X fixes;
+            rm lcov.info;
+         else
+            rm -rf sanity-out out-2nd-pass;
+         fi;
       - >
           if [ -e compliance.xml ]; then
             cp compliance.xml shippable/testresults/;
@@ -98,10 +120,6 @@ build:
           if [ -e ./scripts/sanity_chk/last_sanity.xml ]; then
             cp ./scripts/sanity_chk/last_sanity.xml shippable/testresults/;
           fi;
-      - >
-          if [ -e ./modified_tests.xml ]; then
-            cp ./modified_tests.xml shippable/testresults/;
-          fi;
 
 integrations:
   notifications:

CODEOWNERS

@@ -10,21 +10,24 @@ MAINTAINERS                              @inakypg @nashif
 arch/arc/*                               @cjordan44 @ruuddw
 arch/arc/core/*                          @andrewboie
 arch/arm/*                               @MaureenHelm @galak
-arch/arm/core/*                          @andrewboie
 arch/arm/soc/arm/mps2/*                  @fvincenzo
+arch/arm/soc/atmel_sam/sam4s             @fallrisk
+arch/arm/soc/nxp*/                       @MaureenHelm
 arch/arm/soc/st_stm32/*                  @erwango
 arch/arm/soc/st_stm32/stm32f4/*          @rsalveti @idlethread
 arch/arm/soc/ti_simplelink/cc32xx        @GAnthony
-arch/nios2/*                             @andrewboie
-arch/nios2/core/*                        @andrewboie
-arch/riscv32                             @fractalclone
+arch/arm/soc/ti_simplelink/msp432p4xx    @Mani-Sadhasivam
+arch/nios2/*                             @andrewboie @ramakrishnapallala
+arch/nios2/core/*                        @andrewboie @ramakrishnapallala
+arch/posix/*                             @aescolar-ot
+arch/riscv32                             @fractalclone @kgugala @pgielda
 arch/x86/*                               @andrewboie @youvedeep
 arch/x86/core/*                          @andrewboie
 arch/x86/core/crt0.S                     @youvedeep @nashif
 arch/x86/soc/intel_quark/quark_d2000/*   @nashif
 arch/x86/soc/intel_quark/quark_se/*      @nashif
 arch/x86/soc/intel_quark/quark_x1000/*   @nashif
-arch/xtensa/*                            @andrewboie
+arch/xtensa/*                            @andrewboie @rgundi @andyross
 boards/arc/*                             @cjordan44 @ruuddw
 boards/arc/arduino_101_sss/*             @nashif
 boards/arc/em_starterkit/*               @cjordan44
@@ -32,54 +35,69 @@ boards/arc/quark_se_c1000_ss_devboard/*  @nashif
 boards/arm/*                             @MaureenHelm @galak
 boards/arm/96b_carbon/*                  @rsalveti @idlethread
 boards/arm/96b_nitrogen/*                @idlethread
+boards/arm/96b_neonkey/*                 @Mani-Sadhasivam
 boards/arm/arduino_101_ble/*             @jhedberg
 boards/arm/cc3220sf_launchxl/*           @GAnthony
 boards/arm/disco_l475_iot1/*             @erwango
-boards/arm/frdm_k64f/*                   @MaureenHelm
-boards/arm/frdm_kw41z/*                  @MaureenHelm
-boards/arm/hexiwear_k64/*                @MaureenHelm
+boards/arm/frdm*/*                       @MaureenHelm
+boards/arm/hexiwear*/*                   @MaureenHelm
+boards/arm/lpcxpresso*/*                 @MaureenHelm
+boards/arm/mimxrt*/*                     @MaureenHelm
 boards/arm/mps2_an385/*                  @fvincenzo
+boards/arm/msp_exp432p401r_launchxl/*    @Mani-Sadhasivam
 boards/arm/nrf51_blenano/*               @rsalveti
 boards/arm/nrf52_pca10040/*              @carlescufi
 boards/arm/nucleo_f401re/*               @rsalveti @idlethread
+boards/arm/sam4s_xplained                @fallrisk
 boards/arm/v2m_beetle/*                  @fvincenzo
 boards/arm/olimexino_stm32/*             @ydamigos
 boards/arm/stm32f3_disco/*               @ydamigos
-boards/nios2/*                           @andrewboie
-boards/nios2/altera_max10/*              @andrewboie
-boards/riscv32                           @fractalclone
-boards/x86/*                             @andrewboie @youvedeep
+boards/nios2/*                           @ramakrishnapallala
+boards/nios2/altera_max10/*              @ramakrishnapallala
+boards/posix/*                           @aescolar-ot
+boards/riscv32                           @fractalclone @kgugala @pgielda
+boards/x86/*                             @andrewboie @nashif
 boards/x86/arduino_101/*                 @nashif
 boards/x86/galileo/*                     @nashif
 boards/x86/quark_d2000_crb/*             @nashif
 boards/x86/quark_se_c1000_devboard/*     @nashif
-boards/xtensa/*                          @andrewboie
+boards/xtensa/*                          @andrewboie @ramakrishnapallala
+# All cmake related files
+cmake/*                                  @nashif @SebastianBoe
+/CMakeLists.txt                          @nashif @SebastianBoe
 doc/*                                    @dbkinder
 doc/subsystems/bluetooth/*               @sjanc @jhedberg @Vudentz
+drivers/*/*mcux*                         @MaureenHelm
 drivers/*/*qmsi*                         @nashif
 drivers/*/*stm32*                        @erwango
+drivers/*/*native_posix*                 @aescolar-ot
+drivers/adc/*                            @anangl
 drivers/bluetooth/*                      @sjanc @jhedberg @Vudentz
 drivers/clock_control/*stm32f4*          @rsalveti @idlethread
+drivers/counter/*                        @anangl
 drivers/ethernet/*                       @jukkar @tbursztyka
 drivers/flash/*                          @nashif
+drivers/flash/*stm32*                    @superna9999
 drivers/gpio/*stm32*                     @rsalveti @idlethread
-drivers/gpio/gpio_pulpino.c              @fractalclone
+drivers/gpio/gpio_pulpino.c              @fractalclone @kgugala @pgielda
 drivers/ieee802154/*                     @jukkar @tbursztyka
 drivers/interrupt_controller/*           @andrewboie
+drivers/led_strip/*                      @mbolivar
 drivers/pinmux/stm32/*                   @rsalveti @idlethread
 drivers/sensor/*                         @bogdan-davidoaia
-drivers/serial/uart_altera_jtag.c        @andrewboie
-drivers/serial/uart_riscv_qemu.c         @fractalclone
-drivers/slip/*                           @jukkar @tbursztyka
+drivers/serial/uart_altera_jtag.c        @ramakrishnapallala
+drivers/serial/uart_riscv_qemu.c         @fractalclone @kgugala @pgielda
+drivers/net/slip/*                       @jukkar @tbursztyka
 drivers/spi/*                            @tbursztyka
-drivers/spi/spi_ll_stm32.*               @superna9999 @mbolivar
-drivers/timer/altera_avalon_timer.c      @andrewboie
-drivers/timer/pulpino_timer.c            @fractalclone
-drivers/timer/riscv_machine_timer.c      @fractalclone
+drivers/spi/spi_ll_stm32.*               @superna9999
+drivers/timer/altera_avalon_timer.c      @ramakrishnapallala
+drivers/timer/pulpino_timer.c            @fractalclone @kgugala @pgielda
+drivers/timer/riscv_machine_timer.c      @fractalclone @kgugala @pgielda
 drivers/usb                              @youvedeep @andyross
+drivers/usb/device/usb_dc_stm32.c        @ydamigos @loicpoulain
 drivers/i2c/i2c_ll_stm32*                @ldts @ydamigos
 dts/arm/st/*                             @erwango
-ext/fs/*                                 @nashif
+ext/fs/*                                 @nashif @ramakrishnapallala
 ext/hal/cmsis/*                          @MaureenHelm @galak
 ext/hal/nordic/mdk/*                     @carlescufi
 ext/hal/nxp/mcux/*                       @MaureenHelm
@@ -87,6 +105,7 @@ ext/hal/qmsi/*                           @nashif
 ext/hal/st/stm32cube/*                   @erwango
 ext/lib/crypto/mbedtls/*                 @nashif
 ext/lib/crypto/tinycrypt/*               @lpereira
+include/adc.h                            @anangl
 include/arch/arc/*                       @cjordan44 @ruuddw
 include/arch/arc/arch.h                  @andrewboie
 include/arch/arc/v2/irq.h                @andrewboie
@@ -94,27 +113,27 @@ include/arch/arm/*                       @MaureenHelm @galak
 include/arch/arm/cortex_m/irq.h          @andrewboie
 include/arch/nios2/*                     @andrewboie
 include/arch/nios2/arch.h                @andrewboie
-include/arch/riscv32                     @fractalclone
+include/arch/riscv32                     @fractalclone @kgugala @pgielda
 include/arch/x86/*                       @andrewboie @youvedeep
 include/arch/x86/arch.h                  @andrewboie
 include/arch/xtensa/*                    @andrewboie
 include/atomic.h                         @andrewboie @andyross
 include/bluetooth/*                      @sjanc @jhedberg @Vudentz
 include/cache.h                          @andrewboie @andyross
+include/counter.h                        @anangl
 include/device.h                         @youvedeep @nashif
 include/drivers/bluetooth/*              @sjanc @jhedberg @Vudentz
 include/drivers/ioapic.h                 @andrewboie
 include/drivers/loapic.h                 @andrewboie
 include/drivers/mvic.h                   @andrewboie
-include/fs.h                             @nashif
-include/fs/*                             @nashif
+include/fs.h                             @nashif @ramakrishnapallala
+include/fs/*                             @nashif @ramakrishnapallala
 include/init.h                           @andrewboie @andyross
-include/init.h                           @youvedeep @nashif
-include/irq.h                            @andrewboie
 include/irq.h                            @andrewboie @andyross
 include/irq_offload.h                    @andrewboie @andyross
 include/kernel.h                         @andrewboie @andyross
 include/kernel_version.h                 @andrewboie @andyross
+include/led_strip.h                      @mbolivar
 include/linker/linker-defs.h             @andrewboie @andyross
 include/linker/linker-tool-gcc.h         @andrewboie @andyross
 include/linker/linker-tool.h             @andrewboie @andyross
@@ -134,6 +153,7 @@ include/toolchain.h                      @andrewboie @andyross
 include/toolchain/*                      @andrewboie @andyross
 include/zephyr.h                         @andrewboie @andyross
 kernel/*                                 @andrewboie @andyross
+kernel/posix/*				 @youvedeep
 kernel/device.c                          @youvedeep @nashif
 kernel/idle.c                            @youvedeep @nashif
 samples/bluetooth/*                      @sjanc @jhedberg @Vudentz
@@ -142,15 +162,16 @@ samples/net/*                            @jukkar @tbursztyka
 samples/net/dns_resolve/*                @jukkar @tbursztyka
 samples/net/http_server/*                @jukkar @tbursztyka
 samples/net/lwm2m_client/*               @mike-scott
-samples/net/mbedtls_sslclient/*          @nashif
+samples/net/mbedtls_sslclient/*          @jukkar
 samples/net/mqtt_publisher/*             @jukkar @tbursztyka
-samples/net/zoap_client/*                @vcgomes
-samples/net/zoap_server/*                @vcgomes
+samples/net/coap_client/*                @rveerama1
+samples/net/coap_server/*                @rveerama1
 samples/sensor/*                         @bogdan-davidoaia
 samples/subsys/usb                       @youvedeep @andyross
 scripts/expr_parser.py                   @andrewboie
 scripts/sanity_chk/*                     @andrewboie
-scripts/sanitycheck                      @andrewboie
+scripts/sanitycheck                      @andrewboie @nashif
+scripts/support/runner/*                 @mbolivar
 subsys/bluetooth/*                       @sjanc @jhedberg @Vudentz
 subsys/bluetooth/controller/*            @carlescufi @cvinayak
 subsys/fs/*                              @nashif
@@ -161,7 +182,7 @@ subsys/net/lib/dns/*                     @jukkar @tbursztyka
 subsys/net/lib/http/*                    @jukkar @tbursztyka
 subsys/net/lib/lwm2m/*                   @mike-scott
 subsys/net/lib/mqtt/*                    @jukkar @tbursztyka
-subsys/net/lib/zoap/*                    @vcgomes
+subsys/net/lib/coap/*                    @rveerama1
 subsys/usb                               @youvedeep @andyross
 tests/bluetooth/*                        @sjanc @jhedberg @Vudentz
 tests/crypto/*                           @lpereira
@@ -173,5 +194,5 @@ tests/net/buf/*                          @jukkar @jhedberg @tbursztyka
 tests/net/lib/*                          @jukkar @tbursztyka
 tests/net/lib/http_header_fields/*       @jukkar @tbursztyka
 tests/net/lib/mqtt_packet/*              @jukkar @tbursztyka
-tests/net/lib/zoap/*                     @vcgomes
-tests/subsys/fs/*                        @nashif
+tests/net/lib/coap/*                     @rveerama1
+tests/subsys/fs/*                        @nashif @ramakrishnapallala

CONTRIBUTING.rst

@@ -10,7 +10,6 @@ This document explains how to participate in project conversations, log bugs
 and enhancement requests, and submit patches to the project so your patch will
 be accepted quickly in the codebase.
 
-
 Licensing
 *********
 
@@ -22,21 +21,51 @@ software continues to be available under the terms that the author desired.
 
 .. _GitHub repo: https://github.com/zephyrproject-rtos/zephyr
 
-Zephyr uses the `Apache 2.0 license`_ (as found in the LICENSE file in the
-project's `GitHub repo`_) to strike a balance between open contribution and
-allowing you to use the software however you would like to. There are some
-imported or reused components of the Zephyr project that use other licensing,
-as described in `Zephyr Licensing`_.
+Zephyr uses the `Apache 2.0 license`_ (as found in the LICENSE file in
+the project's `GitHub repo`_) to strike a balance between open
+contribution and allowing you to use the software however you would like
+to.  The Apache 2.0 license is a permissive open source license that
+allows you to freely use, modify, distribute and sell your own products
+that include Apache 2.0 licensed software.  (For more information about
+this, check out articles such as `Why choose Apache 2.0 licensing`_ and
+`Top 10 Apache License Questions Answered`_).
 
-.. _Zephyr Licensing:
-   https://www.zephyrproject.org/doc/LICENSING.html
+.. _Why choose Apache 2.0 licensing:
+   https://www.zephyrproject.org/about/#faq
 
-The license tells you what rights you have as a developer, provided by the
+.. _Top 10 Apache License Questions Answered:
+   https://www.whitesourcesoftware.com/whitesource-blog/top-10-apache-license-questions-answered/
+
+A license tells you what rights you have as a developer, as provided by the
 copyright holder. It is important that the contributor fully understands the
 licensing rights and agrees to them. Sometimes the copyright holder isn't the
 contributor, such as when the contributor is doing work on behalf of a
 company.
 
+Components using other Licenses
+===============================
+
+There are some imported or reused components of the Zephyr project that
+use other licensing, as described in `Zephyr Licensing`_.
+
+.. _Zephyr Licensing:
+   https://www.zephyrproject.org/doc/LICENSING.html
+
+Importing code into the Zephyr OS from other projects that use a license
+other than the Apache 2.0 license needs to be fully understood in
+context and approved by the Zephyr governing board.
+
+By carefully reviewing potential contributions and also enforcing a
+:ref:`DCO` for contributed code, we can ensure that
+the Zephyr community can develop products with the Zephyr Project
+without concerns over patent or copyright issues.
+
+See `Contributing non-Apache 2.0 components`_ for more information about
+this contributing and review process for imported components.
+
+.. _Contributing non-Apache 2.0 components:
+   https://www.zephyrproject.org/doc/contribute/contribute_non-apache.html
+
 .. _DCO:
 
 Developer Certification of Origin (DCO)
@@ -55,7 +84,6 @@ When a developer submits a patch, it is a commitment that the contributor has
 the right to submit the patch per the license.  The DCO agreement is shown
 below and at http://developercertificate.org/.
 
-
 .. code-block:: none
 
     Developer's Certificate of Origin 1.1
@@ -99,7 +127,6 @@ to add the sign-off you can also amend a previous commit with the sign-off by
 running ``git commit --amend -s``. If you've pushed your changes to GitHub
 already you'll need to force push your branch after this with ``git push -f``.
 
-
 Prerequisites
 *************
 
@@ -113,19 +140,28 @@ and how to set up your development environment as introduced in the Zephyr
 .. _Getting Started Guide:
    https://www.zephyrproject.org/doc/getting_started/getting_started.html
 
-The examples below use a Linux host environment for Zephyr development.
-You should be familiar with common developer tools such as Git and Make, and
+You should be familiar with common developer tools such as Git and CMake, and
 platforms such as GitHub.
 
 If you haven't already done so, you'll need to create a (free) GitHub account
 on http://github.com and have Git tools available on your development system.
 
+.. note::
+   The Zephyr development workflow supports all 3 major operating systems
+   (Linux, macOS, and Windows) but some of the tools used in the sections below
+   are only available on Linux and macOS. On Windows, instead of running these
+   tools yourself, you will need to rely on the Continuous Integration (CI)
+   service ``shippable``, which runs automatically on GitHub when you submit
+   your Pull Request (PR).  You can see any failure results in the Shippable
+   details link near the end of the PR conversation list. See
+   `Continuous Integration`_ for more information
+
 Repository layout
 *****************
 
 To clone the main Zephyr Project repository use::
 
-    $ git clone https://github.com/zephyrproject-rtos/zephyr
+    git clone https://github.com/zephyrproject-rtos/zephyr
 
 The Zephyr project directory structure is described in `Source Tree Structure`_
 documentation. In addition to the Zephyr kernel itself, you'll also find the
@@ -139,14 +175,14 @@ available for developers to contribute to and enhance.
 Pull Requests and Issues
 ************************
 
-.. _Zephyr Project Issues: https://jira.zephyrproject.org
+.. _Zephyr Project Issues: https://github.com/zephyrproject-rtos/zephyr/issues
 
 .. _open pull requests: https://github.com/zephyrproject-rtos/zephyr/pulls
 
 .. _Zephyr-devel mailing list:
    https://lists.zephyrproject.org/mailman/listinfo/zephyr-devel
 
-Before starting on a patch, first check in our Jira `Zephyr Project Issues`_
+Before starting on a patch, first check in our issues `Zephyr Project Issues`_
 system to see what's been reported on the issue you'd like to address.  Have a
 conversation on the `Zephyr-devel mailing list`_ (or the #zephyrproject IRC
 channel on freenode.net) to see what others think of your issue (and proposed
@@ -155,40 +191,89 @@ finding, or that have similar ideas for changes or additions.  Send a message
 to the `Zephyr-devel mailing list`_ to introduce and discuss your idea with
 the development community.
 
+Please note that it's common practice on IRC to be away from the
+channel, but still have a client logged in to receive traffic. If you
+ask a question to a particular person and they don't answer, **try
+to stay signed in to the channel** if you can, so they have time to
+respond to you. This is especially important given the many different
+timezones Zephyr developers live in. If you don't get a timely
+response on IRC, try sending a message to the mailing list instead.
+
 It's always a good practice to search for existing or related issues before
 submitting your own. When you submit an issue (bug or feature request), the
 triage team will review and comment on the submission, typically within a few
 business days.
 
 You can find all `open pull requests`_ on GitHub and open `Zephyr Project
-Issues`_ in Jira.
+Issues`_ in Github issues.
 
-Development Tools and Git Setup
-*******************************
+ .. _Continuous Integration:
+
+Continuous Integration (CI)
+***************************
+
+The Zephyr Project operates a Continuous Integration (CI) system that runs on
+every Pull Request (PR) in order to verify several aspects of the PR:
+
+* Git commit formatting
+* Coding Style
+* Sanity Check builds for multiple architectures and boards
+* Documentation build to verify any doc changes
+
+CI is run on the ``shippable`` cloud service and it uses the same tools
+described in the `Contribution Tools`_ section.
+The CI results must be green indicating "All checks have passed" before
+the Pull Request can be merged.  CI is run when the PR is created, and
+again every time the PR is modified with a commit.  You can also force
+the CI system to recheck a PR by adding a comment to the PR saying
+simply ``retest`` in the message (helpful if the CI system fails unexpectedly).
+
+The current status of the CI run can always be found at the bottom of the
+GitHub PR page, below the review status. Depending on the success or failure
+of the run you will see:
+
+* "All checks have passed"
+* "All checks have failed"
+
+In case of failure you can click on the "Details" link presented below the
+failure message in order to navigate to ``shippable`` and inspect the results.
+Once you click on the link you will be taken to the ``shippable`` summary
+results page where a table with all the different builds will be shown. To see
+what build or test failed click on the row that contains the failed (i.e.
+non-green) build and then click on the "Tests" tab to see the console output
+messages indicating the failure.
+
+ .. _Contribution Tools:
+
+Contribution Tools and Git Setup
+********************************
 
 Signed-off-by
 =============
 
 The name in the commit message ``Signed-off-by:`` line and your email must
-match the change authorship information. Make sure your *.git/config* is set
-up correctly::
+match the change authorship information. Make sure your :file:`.gitconfig`
+is set up correctly:
 
-   $ git config --global user.name "David Developer"
-   $ git config --global user.email "david.developer@company.com"
+.. code-block:: console
+
+   git config --global user.name "David Developer"
+   git config --global user.email "david.developer@company.com"
 
 gitlint
-=========
+=======
 
 When you submit a pull request to the project, a series of checks are
 performed to verify your commit messages meet the requirements. The same step
-done during the CI process can be performed locally using the the *gitlint*
+done during the CI process can be performed locally using the the `gitlint`
 command.
 
-Install gitlint and run it locally in your tree and branch where your patches
-have been committed::
+Run `gitlint` locally in your tree and branch where your patches have been
+committed:
 
-     $ sudo pip3 install gitlint
-     $ gitlint
+.. code-block:: console
+
+     gitlint
 
 Note, gitlint only checks HEAD (the most recent commit), so you should run it
 after each commit, or use the ``--commits`` option to specify a commit range
@@ -197,25 +282,48 @@ covering all the development patches to be submitted.
 sanitycheck
 ===========
 
+.. note::
+   sanitycheck does not currently run on Windows.
+
 To verify that your changes did not break any tests or samples, please run the
 ``sanitycheck`` script locally before submitting your pull request to GitHub. To
 run the same tests the CI system runs, follow these steps from within your
-local Zephyr source working directory::
+local Zephyr source working directory:
 
-    $ source zephyr-env.sh
-    $ make host-tools
-    $ export PREBUILT_HOST_TOOLS=${ZEPHYR_BASE}/bin
-    $ export USE_CCACHE=1
-    $ ./scripts/sanitycheck
+.. code-block:: console
+
+    source zephyr-env.sh
+    ./scripts/sanitycheck
 
 The above will execute the basic sanitycheck script, which will run various
 kernel tests using the QEMU emulator.  It will also do some build tests on
 various samples with advanced features that can't run in QEMU.
 
-We highly recommend you run these tests locally to avoid any CI failures.
-Using CCACHE and pre-built host tools is optional, however it speeds up the
-execution time considerably.
+We highly recommend you run these tests locally to avoid any CI
+failures.
 
+uncrustify
+==========
+
+The `uncrustify tool <https://sourceforge.net/projects/uncrustify>`_ can
+be helpful to quickly reformat your source code to our `Coding Style`_
+standards together with a configuration file we've provided:
+
+.. code-block:: bash
+
+   # On Linux/macOS
+   uncrustify --replace --no-backup -l C -c $ZEPHYR_BASE/scripts/uncrustify.cfg my_source_file.c
+   # On Windows
+   uncrustify --replace --no-backup -l C -c %ZEPHYR_BASE%\scripts\uncrustify.cfg my_source_file.c
+
+On Linux systems, you can install uncrustify with
+
+.. code-block:: bash
+
+   sudo apt install uncrustify
+
+For Windows installation instructions see the `sourceforge listing for
+uncrustify <https://sourceforge.net/projects/uncrustify>`_.
 
 Coding Style
 ************
@@ -226,7 +334,6 @@ project's style and naming conventions.
 .. _Linux kernel coding style:
    https://kernel.org/doc/html/latest/process/coding-style.html
 
-
 In general, follow the `Linux kernel coding style`_, with the
 following exceptions:
 
@@ -238,15 +345,24 @@ following exceptions:
   comment, ``//``, is not allowed.
 * Use ``/**  */`` for doxygen comments that need to appear in the documentation.
 
-The Linux kernel GPL-licensed tool ``checkpatch`` is used to check coding
-style conformity. Checkpatch is available in the scripts directory. To invoke
-it when committing code, edit your *.git/hooks/pre-commit* file to contain:
+
+The Linux kernel GPL-licensed tool ``checkpatch`` is used to check
+coding style conformity.
+
+.. note::
+   checkpatch does not currently run on Windows.
+
+Checkpatch is available in the scripts directory. To invoke it when committing
+code, make the file *$ZEPHYR_BASE/.git/hooks/pre-commit* executable and edit
+it to contain:
 
 .. code-block:: bash
 
     #!/bin/sh
     set -e exec
-    exec git diff --cached | ${ZEPHYR_BASE}/scripts/checkpatch.pl - || true
+    exec git diff --cached | ${ZEPHYR_BASE}/scripts/checkpatch.pl -
+
+.. _Contribution workflow:
 
 Contribution Workflow
 *********************
@@ -268,31 +384,31 @@ workflow here:
    https://github.com/zephyrproject-rtos/zephyr#fork-destination-box
 
 #. `Create a Fork of Zephyr`_
-   to your personal account on GitHub.  (Click on the fork button in the top
+   to your personal account on GitHub. (Click on the fork button in the top
    right corner of the Zephyr project repo page in GitHub.)
 
 #. On your development computer, clone the fork you just made::
 
-     $ git clone https://github.com/<your github id>/zephyr
+     git clone https://github.com/<your github id>/zephyr
 
    This would be a good time to let Git know about the upstream repo too::
 
-     $ git remote add upstream https://github.com/zephyrproject-rtos/zephyr.git
+     git remote add upstream https://github.com/zephyrproject-rtos/zephyr.git
 
    and verify the remote repos::
 
-     $ git remote -v
+     git remote -v
 
 #. Create a topic branch (off of master) for your work (if you're addressing
-   Jira issue, we suggest including the Jira issue number in the branch name)::
+   an issue, we suggest including the issue number in the branch name)::
 
-     $ git checkout master
-     $ git checkout -b fix_comment_typo
+     git checkout master
+     git checkout -b fix_comment_typo
 
    Some Zephyr subsystems do development work on a separate branch from
    master so you may need to indicate this in your checkout::
 
-     $ git checkout -b fix_out_of_date_patch origin/net
+     git checkout -b fix_out_of_date_patch origin/net
 
 #. Make changes, test locally, change, test, test again, ...  (Check out the
    prior chapter on `sanitycheck`_ as well).
@@ -300,19 +416,19 @@ workflow here:
 #. When things look good, start the pull request process by adding your changed
    files::
 
-     $ git add [file(s) that changed, add -p if you want to be more specific]
+     git add [file(s) that changed, add -p if you want to be more specific]
 
    You can see files that are not yet staged using::
 
-     $ git status
+     git status
 
 #. Verify changes to be committed look as you expected::
 
-     $ git diff --cached
+     git diff --cached
 
 #. Commit your changes to your local repo::
 
-     $ git commit -s
+     git commit -s
 
    The ``-s`` option automatically adds your ``Signed-off-by:`` to your commit
    message.  Your commit will be rejected without this line that indicates your
@@ -322,7 +438,7 @@ workflow here:
 #. Push your topic branch with your changes to your fork in your personal
    GitHub account::
 
-     $ git push origin fix_comment_typo
+     git push origin fix_comment_typo
 
 #. In your web browser, go to your forked repo and click on the
    ``Compare & pull request`` button for the branch you just worked on and
@@ -348,21 +464,21 @@ workflow here:
    can create another branch to work on another issue. (Be sure to make your
    new branch off of master and not the previous branch.)::
 
-     $ git checkout master
-     $ git checkout -b fix_another_issue
+     git checkout master
+     git checkout -b fix_another_issue
 
    and use the same process described above to work on this new topic branch.
 
 #. If reviewers do request changes to your patch, you can interactively rebase
    commit(s) to fix review issues.  In your development repo::
 
-     $ git fetch --all
-     $ git rebase --ignore-whitespace upstream/master
+     git fetch --all
+     git rebase --ignore-whitespace upstream/master
 
    The ``--ignore-whitespace`` option stops ``git apply`` (called by rebase)
    from changing any whitespace. Continuing::
 
-     $ git rebase -i <offending-commit-id>^
+     git rebase -i <offending-commit-id>^
 
    In the interactive rebase editor, replace ``pick`` with ``edit`` to select
    a specific commit (if there's more than one in your pull request), or
@@ -372,16 +488,20 @@ workflow here:
    As before, inspect and test your changes. When ready, continue the
    patch submission::
 
-     $ git add [file(s)]
-     $ git rebase --continue
+     git add [file(s)]
+     git rebase --continue
 
    Update commit comment if needed, and continue::
 
-     $ git push --force origin fix_comment_typo
+     git push --force origin fix_comment_typo
 
    By force pushing your update, your original pull request will be updated
    with your changes so you won't need to resubmit the pull request.
 
+#. If the CI run fails, you will need to make changes to your code in order
+   to fix the issues and amend your commits by rebasing as described above.
+   Additional information about the CI system can be found in
+   `Continuous Integration`_.
 
 Commit Guidelines
 *****************
@@ -402,9 +522,9 @@ Changes are submitted as Git commits. Each commit message must contain:
 * A Signed-off-by line, ``Signed-off-by: <name> <email>`` typically added
   automatically by using ``git commit -s``
 
-* If the change address a Jira issue, include a line of the form::
+* If the change addresses an issue, include a line of the form::
 
-      Jira: ZEP-xxx
+      Fixes #<issue number>.
 
 
 All changes and topics sent to GitHub must be well-formed, as described above.
@@ -413,9 +533,11 @@ Commit Message Body
 ===================
 
 When editing the commit message, please briefly explain what your change
-does and why it's needed. A change summary of ``"Fixes stuff"`` will be rejected. An
-empty change summary is only acceptable for trivial changes fully described by
-the commit title (e.g., ``doc: fix misspellings in CONTRIBUTING doc``)
+does and why it's needed. A change summary of ``"Fixes stuff"`` will be rejected.
+
+.. warning::
+   An empty change summary body is not permitted. Even for trivial changes, please
+   include a summary body in the commmit message.
 
 The description body of the commit message must include:
 
@@ -433,7 +555,8 @@ Other Commit Expectations
 * Commits must build cleanly when applied on top of each other, thus avoiding
   breaking bisectability.
 
-* Commits must pass the *scripts/checkpatch.pl* requirements.
+* Commits must pass all CI checks (see `Continuous Integration`_ for more
+  information)
 
 * Each commit must address a single identifiable issue and must be
   logically self-contained. Unrelated changes should be submitted as

Kbuild

@@ -1,56 +0,0 @@
-# vim: filetype=make
-
-define filechk_configs.c
-	(echo "/* file is auto-generated, do not modify ! */"; \
-	echo; \
-	echo "#include <toolchain.h>"; \
-	echo; \
-	echo "GEN_ABS_SYM_BEGIN (_ConfigAbsSyms)"; \
-	echo; \
-	cat $(CURDIR)/include/generated/autoconf.h | sed \
-	's/".*"/1/' | awk  \
-	'/#define/{printf "GEN_ABSOLUTE_SYM(%s, %s);\n", $$2, $$3}'; \
-	echo; \
-	echo "GEN_ABS_SYM_END";)
-endef
-
-misc/generated/configs.c: include/config/auto.conf FORCE
-	$(call filechk,configs.c)
-
-targets := misc/generated/configs.c
-targets += include/generated/offsets.h
-
-
-always := misc/generated/configs.c
-always += include/generated/offsets.h
-
-define rule_cc_o_c_1
-	$(call echo-cmd,cc_o_c_1) $(cmd_cc_o_c_1);
-endef
-
-cmd_cc_o_c_1 = $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(ZEPHYRINCLUDE) -c -o $@ $<
-
-arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c $(KCONFIG_CONFIG) \
-				include/generated/generated_dts_board.h
-	$(Q)mkdir -p $(dir $@)
-	$(call if_changed,cc_o_c_1)
-
-
-define offsetchk
-	$(Q)set -e;                                                \
-	$(kecho) '  CHK     $@';                                   \
-	mkdir -p $(dir $@);                                        \
-	$(srctree)/scripts/gen_offset_header.py -i $(1) -o $@.tmp; \
-	if [ -r $@ ] && cmp -s $@ $@.tmp; then                     \
-	rm -f $@.tmp;                                              \
-	else                                                       \
-	$(kecho) '  UPD     $@';                                   \
-	mv -f $@.tmp $@;                                           \
-	fi
-endef
-
-include/generated/offsets.h: arch/$(ARCH)/core/offsets/offsets.o \
-			     include/config/auto.conf FORCE
-	$(call offsetchk,arch/$(ARCH)/core/offsets/offsets.o)
-
-

Kconfig.zephyr

@@ -10,6 +10,14 @@ config KERNELVERSION
 	string
 	option env="KERNELVERSION"
 
+config ENV_VAR_SYM_BOARD_DIR
+	string
+	option env="ENV_VAR_BOARD_DIR"
+
+config ENV_VAR_SYM_ARCH
+	string
+	option env="ENV_VAR_ARCH"
+
 source "arch/Kconfig"
 
 source "kernel/Kconfig"
@@ -37,5 +45,5 @@ source "tests/Kconfig"
 # Board defaults should be parsed after SoC defaults
 # because board usually overrides SoC values.
 #
-source "arch/*/soc/*/Kconfig.defconfig"
-source "boards/*/*/Kconfig.defconfig"
+source "arch/$ENV_VAR_SYM_ARCH/soc/*/Kconfig.defconfig"
+source "$ENV_VAR_SYM_BOARD_DIR/Kconfig.defconfig"

MAINTAINERS

@@ -1,493 +0,0 @@
-Originally from the Linux Kernel.
-# Licensed under the terms of the GNU GPL License version 2
-
-Descriptions of section entries:
-
-	P: Person (obsolete)
-	M: Mail patches to: FullName <address@domain>
-	R: Designated reviewer: FullName <address@domain>
-	   These reviewers should be CCed on patches.
-	L: Mailing list that is relevant to this area
-	W: Web-page with status/info
-	Q: Patchwork web based patch tracking system site
-	T: SCM tree type and location.
-	   Type is one of: git, hg, quilt, stgit, topgit
-	S: Status, one of the following:
-	   Supported:	Someone is actually paid to look after this.
-	   Maintained:	Someone actually looks after it.
-	   Odd Fixes:	It has a maintainer but they don't have time to do
-			much other than throw the odd patch in. See below..
-	   Orphan:	No current maintainer [but maybe you could take the
-			role as you write your new code].
-	   Obsolete:	Old code. Something tagged obsolete generally means
-			it has been replaced by a better system and you
-			should be using that.
-	F: Files and directories with wildcard patterns.
-	   A trailing slash includes all files and subdirectory files.
-	   F:	drivers/net/	all files in and below drivers/net
-	   F:	drivers/net/*	all files in drivers/net, but not below
-	   F:	*/net/*		all files in "any top level directory"/net
-	   One pattern per line.  Multiple F: lines acceptable.
-	N: Files and directories with regex patterns.
-	   N:	[^a-z]tegra	all files whose path contains the word tegra
-	   One pattern per line.  Multiple N: lines acceptable.
-	   scripts/get_maintainer.pl has different behavior for files that
-	   match F: pattern and matches of N: patterns.  By default,
-	   get_maintainer will not look at git log history when an F: pattern
-	   match occurs.  When an N: match occurs, git log history is used
-	   to also notify the people that have git commit signatures.
-	X: Files and directories that are NOT maintained, same rules as F:
-	   Files exclusions are tested before file matches.
-	   Can be useful for excluding a specific subdirectory, for instance:
-	   F:	net/
-	   X:	net/ipv6/
-	   matches all files in and below net excluding net/ipv6/
-	K: Keyword perl extended regex pattern to match content in a
-	   patch or file.  For instance:
-	   K: of_get_profile
-	      matches patches or files that contain "of_get_profile"
-	   K: \b(printk|pr_(info|err))\b
-	      matches patches or files that contain one or more of the words
-	      printk, pr_info or pr_err
-	   One regex pattern per line.  Multiple K: lines acceptable.
-
-Note: For the hard of thinking, this list is meant to remain in alphabetical
-order. If you could add yourselves to it in alphabetical order that would be
-so much easier [Ed]
-
-Maintainers List (try to look for most precise areas first)
-
-		-----------------------------------
-
-ARC ARCHITECTURE
-M:	Ruud Derwig <Ruud.Derwig@synopsys.com>
-M:	Chuck Jordan <cjordan@synopsys.com>
-S:	Supported
-F:	arch/arc/
-F:	include/arch/arc/
-F:	boards/arc/
-
-ARM ARCHITECTURE
-M:	Maureen Helm <maureen.helm@nxp.com>
-M:	Kumar Gala <kumar.gala@linaro.org>
-S:	Supported
-F:	arch/arm/
-F:	include/arch/arm/
-F:	boards/arm/
-
-ARM CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD (CMSIS)
-M:	Maureen Helm <maureen.helm@nxp.com>
-M:	Kumar Gala <kumar.gala@linaro.org>
-S:	Supported
-F:	ext/hal/cmsis/
-
-BOARDS/ARC - ARDUINO 101 SSS
-M:      Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	boards/arc/arduino_101_sss/
-
-BOARDS/ARC - EM Starterkit
-M:	Chuck Jordan <cjordan@synopsys.com>
-S:	Supported
-F:	boards/arc/em_starterkit/
-
-BOARDS/ARC - QUARK SE C1000 SS Devboard
-M:      Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	boards/arc/quark_se_c1000_ss_devboard/
-
-BOARDS/ARM - 96Boards CARBON
-M:	Amit Kucheria <amit.kucheria@linaro.org>
-M:	Ricardo Salveti <ricardo.salveti@linaro.org>
-S:	Supported
-F:	boards/arm/96b_carbon/
-
-BOARDS/ARM - 96Boards NITROGEN
-M:	Amit Kucheria <amit.kucheria@linaro.org>
-S:	Supported
-F:	boards/arm/96b_nitrogen/
-
-BOARDS/ARM - ARDUINO 101 BLE
-M:	Johan Hedberg <johan.hedberg@intel.com>
-S:	Supported
-F:	boards/arm/arduino_101_ble/
-
-BOARDS/ARM - CC32XX LAUNCHXL
-M:      Gil Pitney <gil.pitney@linaro.org>
-S:      Supported
-F:      boards/arm/cc3220sf_launchxl/
-
-BOARDS/ARM - NXP FRDM-K64F
-M:	Maureen Helm <maureen.helm@nxp.com>
-S:	Supported
-F:	boards/arm/frdm_k64f/
-
-BOARDS/ARM - NXP FRDM-KW41Z
-M:	Maureen Helm <maureen.helm@nxp.com>
-S:	Supported
-F:	boards/arm/frdm_kw41z/
-
-BOARDS/ARM - NXP Hexiwear
-M:	Maureen Helm <maureen.helm@nxp.com>
-S:	Supported
-F:	boards/arm/hexiwear_k64/
-
-BOARDS/ARM - NORDIC NRF51 REDBEAR BLENANO
-M:	Ricardo Salveti <ricardo.salveti@linaro.org>
-S:	Supported
-F:	boards/arm/nrf51_blenano/
-
-BOARDS/ARM - NORDIC NRF52 PCA10040
-M:	Carles Cufi <carles.cufi@nordicsemi.no>
-S:	Supported
-F:	boards/arm/nrf52_pca10040/
-
-BOARDS/ARM - NUCLEO-64 F401RE Devboard
-M:	Amit Kucheria <amit.kucheria@linaro.org>
-M:	Ricardo Salveti <ricardo.salveti@linaro.org>
-S:	Supported
-F:	boards/arm/nucleo_f401re/
-
-BOARDS/ARM - ARM LTD V2M Beetle
-M:	Vincenzo Frascino <vincenzo.frascino@linaro.org>
-S:	Supported
-F:	boards/arm/v2m_beetle/
-
-BOARDS/NIOS2 - ALTERA MAX10
-M:	Andrew Boie <andrew.p.boie@intel.com>
-S:	Supported
-F:	boards/nios2/altera_max10/
-
-BOARDS/X86 - ARDUINO 101
-M:      Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	boards/x86/arduino_101/
-
-BOARDS/X86 - Galileo
-M:      Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	boards/x86/galileo/
-
-BOARDS/X86 - QUARK D2000 Devboard
-M:      Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	boards/x86/quark_d2000_crb/
-
-BOARDS/X86 - QUARK SE C1000 Devboard
-M:      Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	boards/x86/quark_se_c1000_devboard/
-
-BLUETOOTH
-M:	Johan Hedberg <johan.hedberg@intel.com>
-M:	Luiz Augusto von Dentz <luiz.dentz@gmail.com>
-M:	Szymon Janc <szymon.janc@gmail.com>
-S:	Supported
-W:	https://www.zephyrproject.org/doc/subsystems/bluetooth/bluetooth.html
-F:	subsys/bluetooth/
-F:	include/bluetooth/
-F:	include/drivers/bluetooth/
-F:	drivers/bluetooth/
-F:	samples/bluetooth/
-F:	tests/bluetooth/
-F:	doc/subsystems/bluetooth/
-
-BLUETOOTH CONTROLLER
-M:	Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
-M:	Carles Cufi <carles.cufi@nordicsemi.no>
-S:	Supported
-F:	subsys/bluetooth/controller/
-
-CC32XX SDK
-M:      Gil Pitney <gil.pitney@linaro.org>
-S:      Supported
-F:      ext/hal/ti/simplelink
-
-CC32XX SOC - TI SIMPLELINK
-M:      Gil Pitney <gil.pitney@linaro.org>
-S:      Supported
-F:      arch/arm/soc/ti_simplelink/cc32xx
-
-DOCUMENTATION
-M:	David Kinder <david.b.kinder@intel.com>
-M:	Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
-S:	Supported
-F:	doc/
-F:	*.rst
-
-FILE SYSTEM
-M:	Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	ext/fs/
-F:	subsys/fs/
-F:	include/fs/
-F:	include/fs.h
-F:	tests/subsys/fs
-
-FLASH DRIVER
-M:	Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	drivers/flash/
-
-INTERRUPTS
-M:	Andrew Boie <andrew.p.boie@intel.com>
-S:	Supported
-F:	drivers/interrupt_controller/
-F:	arch/arc/core/
-F:	arch/arm/core/
-F:	arch/nios2/core/
-F:	arch/x86/core/
-F:	include/irq.h
-F:	include/arch/x86/arch.h
-F:	include/arch/arm/cortex_m/irq.h
-F:	include/arch/nios2/arch.h
-F:	include/arch/arc/arch.h
-F:	include/arch/arc/v2/irq.h
-F:	include/drivers/loapic.h
-F:	include/drivers/ioapic.h
-F:	include/drivers/mvic.h
-
-KERNEL CORE
-M:	Andrew Boie <andrew.p.boie@intel.com>
-M:	Andy Ross <andrew.j.ross@intel.com>
-S:	Supported
-F:	kernel/
-F:	include/misc/
-F:	include/toolchain/
-F:	include/atomic.h
-F:	include/cache.h
-F:	include/init.h
-F:	include/irq.h
-F:	include/irq_offload.h
-F:	include/kernel_version.h
-F:	include/linker/linker-defs.h
-F:	include/linker/linker-tool-gcc.h
-F:	include/linker/linker-tool.h
-F:	include/linker/section_tags.h
-F:	include/linker/sections.h
-F:	include/shared_irq.h
-F:	include/sw_isr_table.h
-F:	include/sys_clock.h
-F:	include/sys_io.h
-F:	include/toolchain.h
-F:	include/zephyr.h
-F:	include/kernel.h
-F:	tests/kernel/
-
-KNOWN ISSUES
-M:	Anas Nashif <anas.nashif@intel.com>
-M:	Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
-F:	.known-issues/
-
-LWM2M
-M:	Michael Scott <michael.scott@linaro.org>
-S:	Supported
-F:	subsys/net/lib/lwm2m/
-F:	samples/net/lwm2m_client/
-
-MAINTAINERS
-M:	Anas Nashif <anas.nashif@intel.com>
-M:	Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
-S:	Supported
-F:	MAINTAINERS
-
-MBEDTLS
-M:	Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	ext/lib/crypto/mbedtls/
-F:	samples/net/mbedtls_sslclient/
-F:	tests/crypto/mbedtls/
-
-MCUXPRESSO SOFTWARE DEVELOPMENT KIT (MCUX)
-M:	Maureen Helm <maureen.helm@nxp.com>
-S:	Supported
-F:	ext/hal/nxp/mcux/
-
-MPS2 - ARM LTD CORTEX-M PROTOTYPING SYSTEM
-M:	Vincenzo Frascino <vincenzo.frascino@linaro.org>
-S:	Supported
-F:	arch/arm/soc/arm/mps2/
-F:	boards/arm/mps2_an385/
-
-NETWORKING
-M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
-M:	Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
-S:	Supported
-W:	https://www.zephyrproject.org/doc/subsystems/networking/networking.html
-F:	subsys/net/ip/
-F:	subsys/net/lib/
-F:	include/net/
-F:	samples/net/
-F:	tests/net/
-F:	tests/net/lib/
-F:	drivers/ethernet/
-F:	drivers/ieee802154/
-F:	drivers/slip/
-
-NETWORK APPLICATIONS
-M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
-M:	Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
-S:	Supported
-F:	subsys/net/lib/dns/
-F:	subsys/net/lib/http/
-F:	subsys/net/lib/mqtt/
-F:	samples/net/dns_resolve/
-F:	samples/net/http_server/
-F:	samples/net/mqtt_publisher/
-F:	tests/net/lib/http_header_fields/
-F:	tests/net/lib/mqtt_packet/
-
-NETWORK BUFFERS
-M:	Johan Hedberg <johan.hedberg@intel.com>
-M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
-M:	Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
-S:	Supported
-W:	https://www.zephyrproject.org/doc/subsystems/networking/buffers.html
-F:	subsys/net/buf.c
-F:	include/net/buf.h
-F:	tests/net/buf/
-
-NIOS II
-M:	Andrew Boie <andrew.p.boie@intel.com>
-S:	Supported
-F:	arch/nios2/
-F:	include/arch/nios2/
-F:	drivers/serial/uart_altera_jtag.c
-F:	drivers/timer/altera_avalon_timer.c
-F:	boards/nios2/
-
-NORDIC MDK
-M:	Carles Cufi <carles.cufi@nordicsemi.no>
-S:	Supported
-F:	ext/hal/nordic/mdk/
-
-POWER MANAGEMENT
-M:	Anas Nashif <anas.nashif@intel.com>
-M:	Youvedeep Singh <youvedeep.singh@intel.com>
-S:	Supported
-F:	arch/x86/core/crt0.S
-F:	include/device.h
-F:	include/init.h
-F:	include/power.h
-F:	kernel/idle.c
-F:	kernel/device.c
-F:	samples/boards/quark_se_c1000/power*/
-
-QMSI
-M:	Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	ext/hal/qmsi/
-
-QMSI DRIVERS
-M:      Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	drivers/*/*qmsi*
-
-QUARK D2000 SOC
-M:      Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	arch/x86/soc/intel_quark/quark_d2000/
-
-QUARK SE C1000 SOC
-M:      Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	arch/x86/soc/intel_quark/quark_se/
-
-QUARK X1000 SOC
-M:      Anas Nashif <anas.nashif@intel.com>
-S:	Supported
-F:	arch/x86/soc/intel_quark/quark_x1000/
-
-SANITYCHECK
-M:	Andrew Boie <andrew.p.boie@intel.com>
-S:	Supported
-F:	scripts/sanitycheck
-F:	scripts/expr_parser.py
-F:	scripts/sanity_chk/
-
-SENSOR DRIVERS
-M:	Bogdan Davidoaia <bogdan.davidoaia@gmail.com>
-M:	Murtaza Alexandru <murtaza.alexandru1995@gmail.com>
-S:	Maintained
-W:	https://www.zephyrproject.org/doc/subsystems/sensor.html
-F:	include/sensor.h
-F:	drivers/sensor/
-F:	samples/sensor/
-
-STM32CUBE SDK
-M:	Erwan Gouriou <erwan.gouriou@linaro.org>
-S:	Supported
-F:	ext/hal/st/stm32cube/
-
-STM32F4X SoC FAMILY and DRIVERS
-M:	Amit Kucheria <amit.kucheria@linaro.org>
-M:	Ricardo Salveti <ricardo.salveti@linaro.org>
-S:	Supported
-F:	arch/arm/soc/st_stm32/stm32f4/
-F:	drivers/pinmux/stm32/
-F:	drivers/gpio/*stm32*
-F:	drivers/clock_control/*stm32f4*
-
-TINYCRYPT
-M:	Constanza Heath <constanza.m.heath@intel.com>
-S:	Supported
-F:	ext/lib/crypto/tinycrypt/
-F:	tests/crypto/
-
-SPI
-M:	Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
-S:	Supported
-F:	drivers/spi/
-F:	include/spi.h
-F:	tests/drivers/spi/
-
-USB
-M:	Youvedeep Singh <youvedeep.singh@intel.com>
-M:	Andy Ross <andrew.j.ross@intel.com>
-S:	Supported
-F:	subsys/usb
-F:	drivers/usb
-F:	samples/subsys/usb
-
-X86 ARCH
-M:	Andrew Boie <andrew.p.boie@intel.com>
-M:	Youvedeep Singh <youvedeep.singh@intel.com>
-S:	Supported
-F:	arch/x86/
-F:	include/arch/x86/
-F:	boards/x86/
-
-XTENSA ARCH
-M:	Andrew Boie <andrew.p.boie@intel.com>
-S:	Supported
-F:	arch/xtensa
-F:	include/arch/xtensa/
-F:	boards/xtensa/
-
-RISCV32 ARCH
-M:	Jean-Paul Etienne <fractalclone@gmail.com>
-S:	Supported
-F:	arch/riscv32
-F:	include/arch/riscv32
-F:	boards/riscv32
-F:	drivers/serial/uart_riscv_qemu.c
-F:	drivers/timer/pulpino_timer.c
-F:	drivers/timer/riscv_machine_timer.c
-F:	drivers/gpio/gpio_pulpino.c
-
-ZOAP
-M:	Vinicius Costa Gomes <vinicius.gomes@intel.com>
-S:	Supported
-F:	subsys/net/lib/zoap/
-F:	samples/net/zoap_client/
-F:	samples/net/zoap_server/
-F:	tests/net/lib/zoap/
-
-THE REST
-M:	Anas Nashif <anas.nashif@intel.com>
-M:	Kumar Gala <kumar.gala@linaro.org>
-L:	devel@lists.zephyrproject.com
-T:	git https://github.com/zephyrproject-rtos/zephyr
-S:	Buried alive in reporters
-F:	*
-F:	*/

Makefile.inc

@@ -1,148 +0,0 @@
-# vim: filetype=make
-#
-
-UNAME := $(shell uname)
-ifeq (MINGW, $(findstring MINGW, $(UNAME)))
-DQUOTE = '
-# '
-PROJECT_BASE ?= $(shell sh -c "pwd -W")
-else
-DQUOTE = "
-# "
-PROJECT_BASE ?= $(CURDIR)
-endif
-
-ifdef BOARD
-KBUILD_DEFCONFIG_PATH=$(wildcard $(ZEPHYR_BASE)/boards/*/*/$(BOARD)_defconfig)
-ifeq ($(KBUILD_DEFCONFIG_PATH),)
-$(error Board $(BOARD) not found!)
-endif
-else
-$(error BOARD is not defined!)
-endif
-
-# Choose a default output directory if one wasn't supplied.  Note that
-# PRISTINE_O depends on whether this is default or not.  If building
-# in-tree, we want to remove the whole outdir and not just the BOARD
-# specified (thus "pristine").  Out of tree, we can obviously remove
-# only what we were told to build.
-ifndef O
-PRISTINE_O = outdir
-O = $(PROJECT_BASE)/outdir/$(BOARD)
-else
-PRISTINE_O = $(O)
-endif
-
-# Turn O into an absolute path; we call the main Kbuild with $(MAKE) -C
-# which changes the working directory, relative paths don't work right.
-# Need to create the directory first to make realpath happy
-
-ifneq ($(MAKECMDGOALS),help)
-$(shell mkdir -p $(O))
-override O := $(realpath $(O))
-endif
-
-export ARCH QEMU_EXTRA_FLAGS PROJECT_BASE
-
-override CONF_FILE := $(strip $(subst $(DQUOTE),,$(CONF_FILE)))
-
-SOURCE_DIR ?= $(PROJECT_BASE)/src/
-override SOURCE_DIR := $(realpath $(SOURCE_DIR))
-override SOURCE_DIR := $(subst \,/,$(SOURCE_DIR))
-override SOURCE_DIR_PARENT := $(patsubst %, %/.., $(SOURCE_DIR))
-override SOURCE_DIR_PARENT := $(abspath $(SOURCE_DIR_PARENT))
-override SOURCE_DIR_PARENT := $(subst \,/,$(SOURCE_DIR_PARENT))
-export SOURCE_DIR SOURCE_DIR_PARENT
-
-ifeq ("$(origin V)", "command line")
-  KBUILD_VERBOSE = $(V)
-endif
-ifndef KBUILD_VERBOSE
-  KBUILD_VERBOSE = 0
-endif
-
-ifeq ($(KBUILD_VERBOSE),1)
-  Q =
-  S =
-else
-  Q = @
-  S = -s
-endif
-
-export CFLAGS
-
-zephyrmake	= +$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) \
-			PROJECT=$(PROJECT_BASE) SOURCE_DIR=$(DQUOTE)$(SOURCE_DIR)$(DQUOTE) $(2)
-
-BOARDCONFIG = $(O)/.board_$(BOARD)
-
-DOTCONFIG = $(O)/.config
-
-all: $(DOTCONFIG)
-	$(Q)$(call zephyrmake,$(O),$@)
-
-debug:	$(DOTCONFIG)
-	$(Q)$(call zephyrmake,$(O),$@)
-
-flash: $(DOTCONFIG)
-	$(Q)$(call zephyrmake,$(O),$@)
-
-run: $(DOTCONFIG)
-	$(Q)$(call zephyrmake,$(O),$@)
-
-ifeq ($(MAKECMDGOALS),debugserver)
-ARCH = $(notdir $(subst /$(BOARD),,$(wildcard $(ZEPHYR_BASE)/boards/*/$(BOARD))))
-BOARD_DIR = $(dir $(wildcard $(ZEPHYR_BASE)/boards/*/*/$(BOARD)_defconfig))
--include $(BOARD_DIR)/Makefile.board
--include $(ZEPHYR_BASE)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
-BOARD_NAME = $(BOARD)
-export BOARD_NAME
-endif
-
-debugserver: FORCE
-	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/support/$(DEBUG_SCRIPT) debugserver
-
-initconfig: $(DOTCONFIG)
-
-$(BOARDCONFIG):
-	@rm -f $(O)/.board_*
-	@touch $@
-
-ram_report: initconfig
-	$(Q)$(call zephyrmake,$(O),$@)
-
-rom_report: initconfig
-	$(Q)$(call zephyrmake,$(O),$@)
-
-outputexports: initconfig
-	$(Q)$(call zephyrmake,$(O),$@)
-
-dts: initconfig
-	$(Q)$(call zephyrmake,$(O),$@)
-
-config-sanitycheck: dts
-	$(Q)$(call zephyrmake,$(O),$@)
-
-menuconfig: initconfig
-	$(Q)$(call zephyrmake,$(O),$@)
-
-help:
-	$(Q)$(MAKE) -s -C $(ZEPHYR_BASE) $@
-
-# Catch all
-%:
-	$(Q)$(call zephyrmake,$(O),$@)
-
-$(DOTCONFIG): $(BOARDCONFIG) $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
-	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/kconfig/merge_config.sh \
-		-q -m -O $(O) $(KBUILD_DEFCONFIG_PATH) $(OVERLAY_CONFIG) $(CONF_FILE) \
-			      $(wildcard $(O)/*.conf)
-	$(Q)$(MAKE) $(S) -C $(ZEPHYR_BASE) O=$(O) PROJECT=$(PROJECT_BASE) oldnoconfig
-
-pristine:
-	$(Q)rm -rf $(PRISTINE_O)
-
-PHONY += FORCE initconfig
-FORCE:
-
-.PHONY: $(PHONY)

Makefile.test

@@ -1,4 +0,0 @@
-
-OVERLAY_CONFIG += $(ZEPHYR_BASE)/tests/include/test.config
-
-include ${ZEPHYR_BASE}/Makefile.inc

README.rst

@@ -5,6 +5,9 @@ Zephyr Project
 
    <a href="https://bestpractices.coreinfrastructure.org/projects/74"><img
    src="https://bestpractices.coreinfrastructure.org/projects/74/badge"></a>
+   <img
+   src="https://api.shippable.com/projects/58ffb2b8baa5e307002e1d79/badge?branch=master">
+
 
 The Zephyr Project is a scalable real-time operating system (RTOS) supporting
 multiple hardware architectures, optimized for resource constrained devices,
@@ -48,7 +51,7 @@ support systems:
   `Zephyr Introduction`_ and `Getting Started Guide`_.
 
 * **Releases**: Source code for Zephyr kernel releases are available at
-  https://zephyrproject.org/downloads. On this page,
+  https://zephyrproject.org/developers/#downloads. On this page,
   you'll find release information, and links to download or clone source
   code from our GitHub repository.  You'll also find links for the Zephyr
   SDK, a moderated collection of tools and libraries used to develop your
@@ -69,15 +72,18 @@ support systems:
   the `Zephyr GitHub wiki`_.
 
 * **Issue Reporting and Tracking**: Requirements and Issue tracking is done in
-  our JIRA system: https://jira.zephyrproject.org. You can browse through the
-  reported issues and submit issues of your own.
+  the Github issues system: https://github.com/zephyrproject-rtos/zephyr/issues.
+  You can browse through the reported issues and submit issues of your own.
 
-* **Security-related Issue Reporting**: For security-related inquiries or
-  reporting suspected security-related bugs in the Zephyr OS, please
-  send email to vulnerabilities@zephyrproject.org.  We will assess and fix
-  flaws according to our security policy outlined in the Zephyr Project
+* **Security-related Issue Reporting and Tracking**: For security-related
+  inquiries or reporting suspected security-related bugs in the Zephyr OS,
+  please send email to vulnerabilities@zephyrproject.org.  We will assess and
+  fix flaws according to our security policy outlined in the Zephyr Project
   `Security Overview`_.
 
+  Security related issue tracking is done in JIRA.  The location of this JIRA
+  is https://zephyrprojectsec.atlassian.net.
+
 * **Mailing List**: The `Zephyr Mailing Lists`_ are perhaps the most convenient
   way to track developer discussions and to ask your own support questions to
   the Zephyr project community.

VERSION

@@ -0,0 +1,5 @@
+VERSION_MAJOR = 1
+VERSION_MINOR = 11
+PATCHLEVEL = 0
+VERSION_TWEAK = 0
+EXTRAVERSION =

arch/CMakeLists.txt

@@ -0,0 +1,2 @@
+add_subdirectory(common)
+add_subdirectory(${ARCH})

arch/Kconfig

@@ -18,6 +18,7 @@ config ARC
 
 config ARM
 	bool "ARM architecture"
+	select ARCH_HAS_THREAD_ABORT
 
 config X86
 	bool "x86 architecture"
@@ -33,8 +34,161 @@ config RISCV32
 config XTENSA
 	bool "Xtensa architecture"
 
+config ARCH_POSIX
+	bool "POSIX (native) architecture"
+	select ATOMIC_OPERATIONS_BUILTIN
+	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
+	select ARCH_HAS_CUSTOM_BUSY_WAIT
+	select ARCH_HAS_THREAD_ABORT
+	select NATIVE_APPLICATION
+
 endchoice
 
+
+menu "General Architecture Options"
+
+config HW_STACK_PROTECTION
+	bool "Hardware Stack Protection"
+	depends on ARCH_HAS_STACK_PROTECTION
+	help
+	  Select this option to enable hardware-based platform features to
+	  catch stack overflows when the system is running in privileged
+	  mode. If CONFIG_USERSPACE is not enabled, the system is always
+	  running in privileged mode.
+
+	  Note that this does not necessarily prevent corruption and assertions
+	  about the overall system state when a fault is triggered cannot be
+	  made.
+
+config USERSPACE
+	bool "User mode threads (EXPERIMENTAL)"
+	depends on ARCH_HAS_USERSPACE
+	help
+	  When enabled, threads may be created or dropped down to user mode,
+	  which has significantly restricted permissions and must interact
+	  with the kernel via system calls. See Zephyr documentation for more
+	  details	about this feature.
+
+	  If a user thread overflows its stack, this will be caught and the
+	  kernel itself will be shielded from harm. Enabling this option
+	  may or may not catch stack overflows when the system is in
+	  privileged mode or handling a system call; to ensure these are always
+	  caught, enable CONFIG_HW_STACK_PROTECTION.
+
+	  This feature is under heavy development and APIs related to it are
+	  subject to change, even if declared non-private.
+
+config PRIVILEGED_STACK_SIZE
+	int "Size of privileged stack"
+	default 256
+	depends on ARCH_HAS_USERSPACE
+	help
+	  This option sets the privileged stack region size that will be used
+	  in addition to the user mode thread stack.  During normal execution,
+	  this region will be inaccessible from user mode.  During system calls,
+	  this region will be utilized by the system call.
+
+config MAX_THREAD_BYTES
+	int "Bytes to use when tracking object thread permissions"
+	default 2
+	depends on USERSPACE
+	help
+	  Every kernel object will have an associated bitfield to store
+	  thread permissions for that object. This controls the size of the
+	  bitfield (in bytes) and imposes a limit on how many threads can
+	  be created in the system.
+
+config SIMPLE_FATAL_ERROR_HANDLER
+	prompt "Simple system fatal error handler"
+	bool
+	default n
+	default y if !MULTITHREADING
+	help
+	  Provides an implementation of _SysFatalErrorHandler() that hard hangs
+	  instead of aborting the faulting thread, and does not print anything,
+	  for footprint-concerned systems. Only enable this option if you do not
+	  want debug capabilities in case of system fatal error.
+
+menu "Interrupt Configuration"
+#
+# Interrupt related configs
+#
+config GEN_ISR_TABLES
+	bool
+	prompt "Use generated IRQ tables"
+	default n
+	help
+	  This option controls whether a platform uses the gen_isr_tables
+	  script to generate its interrupt tables. This mechanism will create
+	  an appropriate hardware vector table and/or software IRQ table.
+
+config GEN_IRQ_VECTOR_TABLE
+	bool
+	prompt "Generate an interrupt vector table"
+	default y
+	depends on GEN_ISR_TABLES
+	help
+	  This option controls whether a platform using gen_isr_tables
+	  needs an interrupt vector table created. Only disable this if the
+	  platform does not use a vector table at all, or requires the vector
+	  table to be in a format that is not an array of function pointers
+	  indexed by IRQ line. In the latter case, the vector table must be
+	  supplied by the application or architecture code.
+
+config GEN_SW_ISR_TABLE
+	bool
+	prompt "Generate a software ISR table"
+	default y
+	depends on GEN_ISR_TABLES
+	help
+	  This option controls whether a platform using gen_isr_tables
+	  needs a software ISR table table created. This is an array of struct
+	  _isr_table_entry containing the interrupt service routine and supplied
+	  parameter.
+
+config GEN_IRQ_START_VECTOR
+	int
+	default 0
+	depends on GEN_ISR_TABLES
+	help
+	  On some architectures, part of the vector table may be reserved for
+	  system exceptions and is declared separately from the tables
+	  created by gen_isr_tables.py. When creating these tables, this value
+	  will be subtracted from CONFIG_NUM_IRQS to properly size them.
+	  This is a hidden option which needs to be set per architecture and
+	  left alone.
+
+
+config IRQ_OFFLOAD
+	bool "Enable IRQ offload"
+	default n
+	help
+	  Enable irq_offload() API which allows functions to be synchronously
+	  run in interrupt context. Mainly useful for test cases.
+
+endmenu # Interrupt configuration
+
+endmenu
+
+#
+# Architecture Capabilities
+#
+config ARCH_HAS_STACK_PROTECTION
+	bool
+
+config ARCH_HAS_USERSPACE
+	bool
+
+config ARCH_HAS_EXECUTABLE_PAGE_BIT
+	bool
+
+#
+# Other architecture related options
+#
+
+config ARCH_HAS_THREAD_ABORT
+	bool
+
 #
 # Hidden PM feature configs which are to be selected by
 # individual SoC.
@@ -44,35 +198,76 @@ config SYS_POWER_LOW_POWER_STATE_SUPPORTED
 	bool
 	default n
 	help
-	This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
-	configuration option.
+	  This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
+	  configuration option.
 
 config SYS_POWER_DEEP_SLEEP_SUPPORTED
 	# Hidden
 	bool
 	default n
 	help
-	This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
-	configuration option.
+	  This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
+	  configuration option.
 
 config BOOTLOADER_CONTEXT_RESTORE_SUPPORTED
 	# Hidden
 	bool
 	default n
 	help
-	This option signifies that the target has options of bootloaders
-	that support context restore upon resume from deep sleep
+	  This option signifies that the target has options of bootloaders
+	  that support context restore upon resume from deep sleep
 
-config SIMPLE_FATAL_ERROR_HANDLER
-	prompt "Simple system fatal error handler"
+
+# End hidden CPU family configs
+#
+
+config CPU_HAS_FPU
 	bool
 	default n
-	default y if !MULTITHREADING
 	help
-	Provides an implementation of _SysFatalErrorHandler() that hard hangs
-	instead of aborting the faulting thread, and does not print anything,
-	for footprint-concerned systems. Only enable this option if you do not
-	want debug capabilities in case of system fatal error.
+	  This option is enabled when the CPU has hardware floating point
+	  unit.
+
+config CPU_HAS_MPU
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	help
+	  This option is enabled when the CPU has a Memory Protection Unit (MPU).
+
+config MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	help
+	  This option is enabled when the MPU requires a power of two alignment
+	  and size for MPU regions.
+
+
+menu "Floating Point Options"
+depends on CPU_HAS_FPU
+
+config FLOAT
+	bool
+	prompt "Floating point registers"
+	default n
+	help
+	  This option allows threads to use the floating point registers.
+	  By default, only a single thread may use the registers.
+
+	  Disabling this option means that any thread that uses a
+	  floating point register will get a fatal exception.
+
+config FP_SHARING
+	bool
+	prompt "Floating point register sharing"
+	depends on FLOAT
+	default n
+	help
+	  This option allows multiple threads to use the floating point
+	  registers.
+
+endmenu
 
 #
 # End hidden PM feature configs
@@ -81,88 +276,40 @@ config SIMPLE_FATAL_ERROR_HANDLER
 config ARCH
 	string
 	help
-	System architecture string.
+	  System architecture string.
 
 config SOC
 	string
 	help
-	SoC name which can be found under arch/<arch>/soc/<soc name>.
-	This option holds the directory name used by the build system to locate
-	the correct linker and header files for the SoC. This option will go away
-	once all SoCs are using family/series structure.
+	  SoC name which can be found under arch/<arch>/soc/<soc name>.
+	  This option holds the directory name used by the build system to locate
+	  the correct linker and header files for the SoC. This option will go away
+	  once all SoCs are using family/series structure.
 
 config SOC_SERIES
 	string
 	help
-	SoC series name which can be found under arch/<arch>/soc/<family>/<series>.
-	This option holds the directory name used by the build system to locate
-	the correct linker and header files.
+	  SoC series name which can be found under arch/<arch>/soc/<family>/<series>.
+	  This option holds the directory name used by the build system to locate
+	  the correct linker and header files.
 
 config SOC_FAMILY
 	string
 	help
-	SoC family name which can be found under arch/<arch>/soc/<family>.
-	This option holds the directory name used by the build system to locate
-	the correct linker and header files.
+	  SoC family name which can be found under arch/<arch>/soc/<family>.
+	  This option holds the directory name used by the build system to locate
+	  the correct linker and header files.
 
 config BOARD
 	string
 	help
-	This option holds the name of the board and is used to locate the files
-	related to the board in the source tree (under boards/).
-	The Board is the first location where we search for a linker.ld file,
-	if not found we look for the linker file in
-	arch/<arch>/soc/<family>/<series>
+	  This option holds the name of the board and is used to locate the files
+	  related to the board in the source tree (under boards/).
+	  The Board is the first location where we search for a linker.ld file,
+	  if not found we look for the linker file in
+	  arch/<arch>/soc/<family>/<series>
 
-#
-# Interrupt related configs
-#
 
-config GEN_ISR_TABLES
-	bool
-	prompt "Use generated IRQ tables"
-	default n
-	help
-	This option controls whether a platform uses the gen_isr_tables
-	script to generate its interrupt tables. This mechanism will create
-	an appropriate hardware vector table and/or software IRQ table.
-
-config GEN_IRQ_VECTOR_TABLE
-	bool
-	prompt "Generate an interrupt vector table"
-	default y
-	depends on GEN_ISR_TABLES
-	help
-	This option controls whether a platform using gen_isr_tables
-	needs an interrupt vector table created. Only disable this if the
-	platform does not use a vector table at all, or requires the vector
-	table to be in a format that is not an array of function pointers
-	indexed by IRQ line. In the latter case, the vector table must be
-	supplied by the application or architecture code.
-
-config GEN_SW_ISR_TABLE
-	bool
-	prompt "Generate a software ISR table"
-	default y
-	depends on GEN_ISR_TABLES
-	help
-	This option controls whether a platform using gen_isr_tables
-	needs a software ISR table table created. This is an array of struct
-	_isr_table_entry containing the interrupt service routine and supplied
-	parameter.
-
-config GEN_IRQ_START_VECTOR
-	int
-	default 0
-	depends on GEN_ISR_TABLES
-	help
-	On some architectures, part of the vector table may be reserved for
-	system exceptions and is declared separately from the tables
-	created by gen_isr_tables.py. When creating these tables, this value
-	will be subtracted from CONFIG_NUM_IRQS to properly size them.
-	This is a hidden option which needs to be set per architecture and
-	left alone.
-
-source "arch/*/Kconfig"
+source "arch/$ENV_VAR_SYM_ARCH/Kconfig"
 
 source "boards/Kconfig"

arch/Makefile

@@ -1 +0,0 @@
-obj-y += common/ $(ARCH)/

arch/arc/CMakeLists.txt

@@ -0,0 +1,16 @@
+# Enable debug support in mdb
+# Dwarf version 2 can be recognized by mdb
+# The default dwarf version in gdb is not recognized by mdb
+zephyr_cc_option(-g3 -gdwarf-2)
+
+# Without this (poorly named) option, compiler may generate undefined
+# references to abort().
+# See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63691
+zephyr_cc_option(-fno-delete-null-pointer-checks)
+
+zephyr_cc_option_ifdef (CONFIG_LTO         -flto)
+
+set_property(GLOBAL PROPERTY E_KERNEL_ENTRY  -e${CONFIG_KERNEL_ENTRY})
+
+add_subdirectory(soc/${SOC_PATH})
+add_subdirectory(core)

arch/arc/Kbuild

@@ -1,6 +0,0 @@
-subdir-ccflags-y +=-I$(srctree)/include/drivers
-subdir-ccflags-y +=-I$(srctree)/drivers
-subdir-asflags-y += $(subdir-ccflags-y)
-
-obj-y += soc/$(SOC_PATH)/
-obj-y += core/

arch/arc/Kconfig

@@ -24,21 +24,6 @@ config ARCH_DEFCONFIG
 	string
 	default "arch/arc/defconfig"
 
-config CPU_HAS_MPU
-	bool
-	# Omit prompt to signify "hidden" option
-	default n
-	help
-	  This option is enabled when the CPU has a Memory Protection Unit (MPU).
-
-config CPU_HAS_FPU
-	# Hidden config selected by CPU family
-	bool
-	default n
-	help
-	This option is enabled when the CPU has hardware floating point
-	unit.
-
 menu "ARC EM4 processor options"
 
 config	CPU_ARCEM4
@@ -47,7 +32,7 @@ config	CPU_ARCEM4
 	select CPU_ARCV2
 	select ATOMIC_OPERATIONS_C
 	help
-	This option signifies the use of an ARC EM4 CPU
+	  This option signifies the use of an ARC EM4 CPU
 
 endmenu
 
@@ -55,6 +40,8 @@ menu "ARCv2 Family Options"
 
 config	CPU_ARCV2
 	bool
+	select		ARCH_HAS_STACK_PROTECTION
+	select ARCH_HAS_USERSPACE if ARC_CORE_MPU
 	default y
 	help
 	  This option signifies the use of a CPU of the ARCv2 family.
@@ -96,18 +83,28 @@ config	RGF_NUM_BANKS
 	range 1 2
 	default 2
 	help
-	The ARC CPU can be configured to have more than one register
-	bank. If fast interrupts are supported (FIRQ), the 2nd
-	register bank, in the set, will be used by FIRQ interrupts.
-	If fast interrupts are supported but there is only 1
-	register bank, the fast interrupt handler must save
-	and restore general purpose registers.
+	  The ARC CPU can be configured to have more than one register
+	  bank. If fast interrupts are supported (FIRQ), the 2nd
+	  register bank, in the set, will be used by FIRQ interrupts.
+	  If fast interrupts are supported but there is only 1
+	  register bank, the fast interrupt handler must save
+	  and restore general purpose registers.
+
+config ARC_FIRQ
+	bool
+	prompt "FIRQ enable"
+	default y
+	help
+	  Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts
+	  with highest priority, status32 and pc will be saved in aux regs,
+	  other regs will be saved according to the number of register bank;
+	  If FIRQ is disabled, the handle of interrupts with highest priority
+	  will be same with other interrupts.
 
 config	ARC_STACK_CHECKING
-	bool "Enable Stack Checking"
-	depends on CPU_ARCV2
+	bool
+	default y if HW_STACK_PROTECTION
 	select THREAD_STACK_INFO
-	default n
 	help
 	  ARCV2 has a special feature allowing to check stack overflows. This
 	  enables code that allows using this debug feature
@@ -118,23 +115,15 @@ config	FAULT_DUMP
 	default 2
 	range 0 2
 	help
-	Different levels for display information when a fault occurs.
+	  Different levels for display information when a fault occurs.
 
-	2: The default. Display specific and verbose information. Consumes
+	  2: The default. Display specific and verbose information. Consumes
 		the most memory (long strings).
 
-	1: Display general and short information. Consumes less memory
+	  1: Display general and short information. Consumes less memory
 		(short strings).
 
-	0: Off.
-
-config IRQ_OFFLOAD
-	bool "Enable IRQ offload"
-	default n
-	help
-	Enable irq_offload() API which allows functions to be synchronously
-	run in interrupt context. Uses one entry in the	IDT.  Mainly useful
-	for test cases.
+	  0: Off.
 
 config	XIP
 	default n if NSIM
@@ -151,40 +140,22 @@ config HARVARD
 	bool
 	default n
 	help
-	The ARC CPU can be configured to have two busses;
-	one for instruction fetching and another that serves as a data bus.
+	  The ARC CPU can be configured to have two busses;
+	  one for instruction fetching and another that serves as a data bus.
 
 config CODE_DENSITY
 	prompt "Code Density Option"
 	bool
 	default n
 	help
-	Enable code density option to get better code density
+	  Enable code density option to get better code density
 
-menu "Floating Point Options"
-depends on CPU_HAS_FPU
-
-config FLOAT
+config ARC_HAS_SECURE
 	bool
-	prompt "Floating point registers"
+	#  a hidden option
 	default n
 	help
-	This option allows tasks and fibers to use the floating point registers.
-	By default, only a single task or fiber may use the registers.
-
-	Disabling this option means that any task or fiber that uses a
-	floating point register will get a fatal exception.
-
-config FP_SHARING
-	bool
-	prompt "Floating point register sharing"
-	depends on FLOAT
-	default n
-	help
-	This option allows multiple tasks and fibers to use the floating point
-	registers.
-
-endmenu
+	  This option is enabled when ARC core supports secure mode
 
 menu "ARC MPU Options"
 depends on CPU_HAS_MPU
@@ -201,82 +172,84 @@ source "arch/arc/core/mpu/Kconfig"
 
 endmenu
 
+if !HAS_DTS
 config ICCM_SIZE
 	int "ICCM Size in kB"
 	help
-	This option specifies the size of the ICCM in kB.  It is normally set by
-	the board's defconfig file and the user should generally avoid modifying
-	it via the menu configuration.
+	  This option specifies the size of the ICCM in kB.  It is normally set by
+	  the board's defconfig file and the user should generally avoid modifying
+	  it via the menu configuration.
 
 config ICCM_BASE_ADDRESS
 	hex "ICCM Base Address"
 	help
-	This option specifies the base address of the ICCM on the board.  It is
-	normally set by the board's defconfig file and the user should generally
-	avoid modifying it via the menu configuration.
+	  This option specifies the base address of the ICCM on the board.  It is
+	  normally set by the board's defconfig file and the user should generally
+	  avoid modifying it via the menu configuration.
 
 config DCCM_SIZE
 	int "DCCM Size in kB"
 	help
-	This option specifies the size of the DCCM in kB.  It is normally set by
-	the board's defconfig file and the user should generally avoid modifying
-	it via the menu configuration.
+	  This option specifies the size of the DCCM in kB.  It is normally set by
+	  the board's defconfig file and the user should generally avoid modifying
+	  it via the menu configuration.
 
 config DCCM_BASE_ADDRESS
 	hex "DCCM Base Address"
 	help
-	This option specifies the base address of the DCCM on the board.  It is
-	normally set by the board's defconfig file and the user should generally
-	avoid modifying it via the menu configuration.
+	  This option specifies the base address of the DCCM on the board.  It is
+	  normally set by the board's defconfig file and the user should generally
+	  avoid modifying it via the menu configuration.
 
 config SRAM_SIZE
 	int "SRAM Size in kB"
 	help
-	This option specifies the size of the SRAM in kB.  It is normally set by
-	the board's defconfig file and the user should generally avoid modifying
-	it via the menu configuration.
+	  This option specifies the size of the SRAM in kB.  It is normally set by
+	  the board's defconfig file and the user should generally avoid modifying
+	  it via the menu configuration.
 
 config SRAM_BASE_ADDRESS
 	hex "SRAM Base Address"
 	help
-	This option specifies the base address of the SRAM on the board.  It is
-	normally set by the board's defconfig file and the user should generally
-	avoid modifying it via the menu configuration.
+	  This option specifies the base address of the SRAM on the board.  It is
+	  normally set by the board's defconfig file and the user should generally
+	  avoid modifying it via the menu configuration.
 
 config FLASH_SIZE
 	int "Flash Size in kB"
 	help
-	This option specifies the size of the flash in kB.  It is normally set by
-	the board's defconfig file and the user should generally avoid modifying
-	it via the menu configuration.
+	  This option specifies the size of the flash in kB.  It is normally set by
+	  the board's defconfig file and the user should generally avoid modifying
+	  it via the menu configuration.
 
 config FLASH_BASE_ADDRESS
 	hex "Flash Base Address"
 	help
-	This option specifies the base address of the flash on the board.  It is
-	normally set by the board's defconfig file and the user should generally
-	avoid modifying it via the menu configuration.
+	  This option specifies the base address of the flash on the board.  It is
+	  normally set by the board's defconfig file and the user should generally
+	  avoid modifying it via the menu configuration.
+endif
 
 config CACHE_LINE_SIZE_DETECT
 	bool
 	prompt "Detect d-cache line size at runtime"
 	default n
 	help
-	This option enables querying the d-cache build register for finding
-	the d-cache line size at the expense of taking more memory and code
-	and a slightly increased boot time.
+	  This option enables querying the d-cache build register for finding
+	  the d-cache line size at the expense of taking more memory and code
+	  and a slightly increased boot time.
 
-	If the CPU's d-cache line size is known in advance, disable this
-	option and manually enter the value for CACHE_LINE_SIZE.
+	  If the CPU's d-cache line size is known in advance, disable this
+	  option and manually enter the value for CACHE_LINE_SIZE.
 
 config CACHE_LINE_SIZE
 	int
 	prompt "Cache line size" if !CACHE_LINE_SIZE_DETECT
 	default 32
 	help
-	Size in bytes of a CPU d-cache line.
+	  Size in bytes of a CPU d-cache line.
 
-	Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
+	  Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
 
 config ARCH_CACHE_FLUSH_DETECT
 	bool
@@ -287,10 +260,10 @@ config CACHE_FLUSHING
 	default n
 	prompt "Enable d-cache flushing mechanism"
 	help
-	This links in the sys_cache_flush() function, which provides a
-	way to flush multiple lines of the d-cache.
-	If the d-cache is present, set this to y.
-	If the d-cache is NOT present, set this to n.
+	  This links in the sys_cache_flush() function, which provides a
+	  way to flush multiple lines of the d-cache.
+	  If the d-cache is present, set this to y.
+	  If the d-cache is NOT present, set this to n.
 
 endmenu
 

arch/arc/Makefile

@@ -1,24 +0,0 @@
-# Enable debug support in mdb
-# Dwarf version 2 can be recognized by mdb
-# The default dwarf version in gdb is not recognized by mdb
-cflags-y += $(call cc-option, -g3 -gdwarf-2)
-
-cflags-y += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
-
-# Without this (poorly named) option, compiler may generate undefined
-# references to abort().
-# See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63691
-cflags-y += $(call cc-option,-fno-delete-null-pointer-checks)
-
-cflags-$(CONFIG_LTO) = $(call cc-option,-flto,)
-
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
-
-KBUILD_CFLAGS += $(cflags-y)
-KBUILD_CXXFLAGS += $(cflags-y)
-
-soc-cxxflags ?= $(soc-cflags)
-soc-aflags ?= $(soc-cflags)
-KBUILD_CFLAGS += $(soc-cflags)
-KBUILD_CXXFLAGS += $(soc-cxxflags)
-KBUILD_AFLAGS += $(soc-aflags)

arch/arc/core/CMakeLists.txt

@@ -0,0 +1,25 @@
+zephyr_sources(
+	thread.c
+	thread_entry_wrapper.S
+	cpu_idle.S
+	fatal.c
+	fault.c
+	fault_s.S
+	irq_manage.c
+	cache.c
+	timestamp.c
+	isr_wrapper.S
+	regular_irq.S
+	swap.S
+	sys_fatal_error_handler.c
+	prep_c.c
+	reset.S
+	vector_table.c
+	)
+
+zephyr_sources_ifdef(CONFIG_ARC_FIRQ fast_irq.S)
+
+zephyr_sources_if_kconfig(irq_offload.c)
+zephyr_sources_ifdef(CONFIG_ATOMIC_OPERATIONS_CUSTOM atomic.c)
+add_subdirectory_ifdef(CONFIG_CPU_HAS_MPU mpu)
+zephyr_sources_ifdef(CONFIG_USERSPACE userspace.S)

arch/arc/core/Makefile

@@ -1,20 +0,0 @@
-ccflags-y += -I$(srctree)/kernel/include
-ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
-
-obj-y += thread.o thread_entry_wrapper.o \
-	cpu_idle.o  fast_irq.o  fatal.o  fault.o  \
-	fault_s.o  irq_manage.o cache.o timestamp.o  \
-	isr_wrapper.o  regular_irq.o  swap.o \
-	sys_fatal_error_handler.o
-
-obj-y += prep_c.o \
-         reset.o \
-         vector_table.o
-
-obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
-
-# Some ARC cores like the EM4 lack the atomic LLOCK/SCOND and
-# can't use these.
-obj-$(CONFIG_ATOMIC_OPERATIONS_CUSTOM) += atomic.o
-
-obj-$(CONFIG_CPU_HAS_MPU) += mpu/

arch/arc/core/cache.c

@@ -20,7 +20,7 @@
 #include <cache.h>
 #include <linker/linker-defs.h>
 #include <arch/arc/v2/aux_regs.h>
-#include <nano_internal.h>
+#include <kernel_internal.h>
 #include <misc/__assert.h>
 #include <init.h>
 

arch/arc/core/fast_irq.S

@@ -257,10 +257,10 @@ _firq_reschedule:
 	 */
 	_load_callee_saved_regs
 
-#ifdef CONFIG_MPU_STACK_GUARD
+#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
 	push_s r2
 	mov r0, r2
-	bl configure_mpu_stack_guard
+	bl configure_mpu_thread
 	pop_s r2
 #endif
 

arch/arc/core/fatal.c

@@ -44,10 +44,6 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 	case _NANO_ERR_HW_EXCEPTION:
 		break;
 
-	case _NANO_ERR_INVALID_TASK_EXIT:
-		printk("***** Invalid Exit Software Error! *****\n");
-		break;
-
 #if defined(CONFIG_STACK_CANARIES) || defined(CONFIG_ARC_STACK_CHECKING)
 	case _NANO_ERR_STACK_CHK_FAIL:
 		printk("***** Stack Check Fail! *****\n");
@@ -88,3 +84,10 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 	for (;;)
 		;
 }
+
+
+FUNC_NORETURN void _arch_syscall_oops(void *ssf_ptr)
+{
+	_SysFatalErrorHandler(_NANO_ERR_KERNEL_OOPS, ssf_ptr);
+	CODE_UNREACHABLE;
+}

arch/arc/core/fault_s.S

@@ -47,7 +47,7 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_tlb_miss_d)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_prot_v)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_privilege_v)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_swi)
-#ifndef CONFIG_IRQ_OFFLOAD
+#if !defined(CONFIG_IRQ_OFFLOAD) && !defined(CONFIG_USERSPACE)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 #endif
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_extension)
@@ -79,7 +79,7 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 	lr r0,[_ARC_V2_ERET]
 	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
 
-
+#ifndef CONFIG_USERSPACE
 	ld r1, [exc_nest_count]
 	add r0, r1, 1
 	st r0, [exc_nest_count]
@@ -92,16 +92,18 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 	ld sp, [r1, _kernel_offset_to_irq_stack]
 exc_nest_handle:
 	push_s r0
+#endif
 
 	jl _Fault
 
+#ifndef CONFIG_USERSPACE
 	pop sp
 
 	mov	r1, exc_nest_count
 	ld	r0, [r1]
 	sub	r0, r0, 1
 	st 	r0, [r1]
-
+#endif
 	/* if _Fault returns, restore the registers */
 	_pop_irq_stack_frame
 
@@ -109,8 +111,38 @@ exc_nest_handle:
 
 #ifdef CONFIG_IRQ_OFFLOAD
 GTEXT(_irq_do_offload);
+#endif
 
+#if defined(CONFIG_IRQ_OFFLOAD) || defined(CONFIG_USERSPACE)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
+#ifdef CONFIG_USERSPACE
+	/* get the id of trap_s */
+	lr ilink, [_ARC_V2_ECR]
+	and ilink, ilink, 0x3f
+	cmp ilink, 0x3
+	bne _do_other_trap
+/* do sys_call */
+	mov ilink, _SYSCALL_LIMIT
+	cmp r6, ilink
+	blt valid_syscall_id
+
+	mov r0, r6
+	mov r6, _SYSCALL_BAD
+
+valid_syscall_id:
+	lr ilink, [_ARC_V2_ERET]
+	push ilink
+	lr ilink, [_ARC_V2_ERSTATUS]
+	push ilink
+
+	bclr ilink, ilink, _ARC_V2_STATUS32_U_BIT
+	sr ilink, [_ARC_V2_ERSTATUS]
+
+	mov ilink, _arc_do_syscall
+	sr ilink, [_ARC_V2_ERET]
+
+	rtie
+
 	/*
 	 * Before invoking exception handler, the kernel switches to an exception
 	 * stack to save the faulting thread's registers.
@@ -118,6 +150,8 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	 * a diagnostic message and halt.
 	 */
 
+_do_other_trap:
+#endif /* CONFIG_USERSPACE */
 #ifdef CONFIG_ARC_STACK_CHECKING
 	push_s r2
 	/* disable stack checking */
@@ -148,7 +182,9 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 trap_nest_handle:
 	push_s r0
 
+#ifdef CONFIG_IRQ_OFFLOAD
 	jl _irq_do_offload
+#endif
 
 	pop sp
 
@@ -200,5 +236,4 @@ _trap_check_for_swap:
 
 	/* Assumption: r2 has current thread */
 	b _rirq_common_interrupt_swap
-
-#endif /* CONFIG_IRQ_OFFLOAD */
+#endif /* CONFIG_IRQ_OFFLOAD || CONFIG_USERSPACE */

arch/arc/core/irq_manage.c

@@ -24,6 +24,7 @@
 #include <linker/sections.h>
 #include <sw_isr_table.h>
 #include <irq.h>
+#include <misc/printk.h>
 
 /*
  * @brief Enable an interrupt line
@@ -95,7 +96,6 @@ void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
  * @return N/A
  */
 
-#include <misc/printk.h>
 void _irq_spurious(void *unused)
 {
 	ARG_UNUSED(unused);

arch/arc/core/isr_wrapper.S

@@ -120,8 +120,8 @@ registers (to avoid stack accesses). It is possible to register a FIRQ
 handler that operates outside of the kernel, but care must be taken to only
 use instructions that only use the banked registers.
 
-The kernel is able to handle transitions to and from FIRQ, RIRQ and threads
-(fibers/task). The contexts are saved 'lazily': the minimum amount of work is
+The kernel is able to handle transitions to and from FIRQ, RIRQ and threads.
+The contexts are saved 'lazily': the minimum amount of work is
 done upfront, and the rest is done when needed:
 
 o RIRQ
@@ -129,7 +129,7 @@ o RIRQ
   All needed regisers to run C code in the ISR are saved automatically
   on the outgoing thread's stack: loop, status32, pc, and the caller-
   saved GPRs. That stack frame layout is pre-determined. If returning
-  to a fiber, the stack is popped and no registers have to be saved by
+  to a thread, the stack is popped and no registers have to be saved by
   the kernel. If a context switch is required, the callee-saved GPRs
   are then saved in the thread control structure (TCS).
 
@@ -151,7 +151,7 @@ o FIRQ
   During early initialization, the sp in the 2nd register bank is made to
   refer to _firq_stack. This allows for the FIRQ handler to use its own stack.
   GPRs are banked, loop registers are saved in unused callee saved regs upon
-  interrupt entry. If returning to a fiber, loop registers are restored and the
+  interrupt entry. If returning to a thread, loop registers are restored and the
   CPU switches back to bank 0 for the GPRs. If a context switch is
   needed, at this point only are all the registers saved. First, a
   stack frame with the same layout as the automatic RIRQ one is created
@@ -229,6 +229,7 @@ From RIRQ:
  */
 
 SECTION_FUNC(TEXT, _isr_wrapper)
+#if CONFIG_ARC_FIRQ
 #if CONFIG_RGF_NUM_BANKS == 1
 	st r0,[saved_r0]
 #endif
@@ -286,6 +287,11 @@ rirq_path:
 	mov.nz r2, _rirq_enter
 	j_s [r2]
 #endif
+#else
+	mov r3, _rirq_exit
+	mov r2, _rirq_enter
+	j_s [r2]
+#endif
 
 #ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
 GTEXT(_sys_k_event_logger_exit_sleep)

arch/arc/core/mpu/CMakeLists.txt

@@ -0,0 +1,2 @@
+zephyr_sources_if_kconfig(arc_core_mpu.c)
+zephyr_sources_if_kconfig(arc_mpu.c)

arch/arc/core/mpu/Kconfig

@@ -11,8 +11,8 @@ config ARC_MPU_VER
 	range 2 4
 	default 2
 	help
-	ARC MPU has several versions. For MPU v2, the minimum region is 2048 bytes;
-	For MPU v3, the minimum region is 32 bytes
+	  ARC MPU has several versions. For MPU v2, the minimum region is 2048 bytes;
+	  For MPU v3, the minimum region is 32 bytes
 
 config ARC_CORE_MPU
 	bool "ARC Core MPU functionalities"
@@ -24,7 +24,6 @@ config ARC_CORE_MPU
 config MPU_STACK_GUARD
 	bool "Thread Stack Guards"
 	depends on ARC_CORE_MPU && !ARC_STACK_CHECKING
-	select THREAD_STACK_INFO
 	default n
 	help
 	  Enable thread stack guards via MPU. ARC supports built-in stack protection.
@@ -34,6 +33,8 @@ config ARC_MPU
 	bool "ARC MPU Support"
 	depends on CPU_HAS_MPU
 	select ARC_CORE_MPU
+	select THREAD_STACK_INFO
+	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if ARC_MPU_VER = 2
 	default n
 	help
-	  Target has ARC MPU (currently only works for EMSK 2.2 ARCEM7D)
+	  Target has ARC MPU (currently only works for EMSK 2.2/2.3 ARCEM7D)

arch/arc/core/mpu/Makefile

@@ -1,2 +0,0 @@
-obj-$(CONFIG_ARC_CORE_MPU) += arc_core_mpu.o
-obj-$(CONFIG_ARC_MPU) += arc_mpu.o

arch/arc/core/mpu/arc_core_mpu.c

@@ -9,6 +9,28 @@
 #include <kernel.h>
 #include <soc.h>
 #include <arch/arc/v2/mpu/arc_core_mpu.h>
+#include <logging/sys_log.h>
+
+/*
+ * @brief Configure MPU for the thread
+ *
+ * This function configures per thread memory map reprogramming the MPU.
+ *
+ * @param thread thread info data structure.
+ */
+void configure_mpu_thread(struct k_thread *thread)
+{
+	arc_core_mpu_disable();
+#if defined(CONFIG_MPU_STACK_GUARD)
+	configure_mpu_stack_guard(thread);
+#endif
+
+#if defined(CONFIG_USERSPACE)
+	configure_mpu_user_context(thread);
+	configure_mpu_mem_domain(thread);
+#endif
+	arc_core_mpu_enable();
+}
 
 #if defined(CONFIG_MPU_STACK_GUARD)
 /*
@@ -21,10 +43,107 @@
  */
 void configure_mpu_stack_guard(struct k_thread *thread)
 {
-	arc_core_mpu_disable();
+#if defined(CONFIG_USERSPACE)
+	if (thread->thread_base.user_options & K_USER) {
+		/* the areas before and after the user stack of thread is
+		 * kernel only. These area can be used as stack guard.
+		 * -----------------------
+		 * |  kernel only area   |
+		 * |---------------------|
+		 * |  user stack         |
+		 * |---------------------|
+		 * |privilege stack guard|
+		 * |---------------------|
+		 * |  privilege stack    |
+		 * -----------------------
+		 */
+		arc_core_mpu_configure(THREAD_STACK_GUARD_REGION,
+			thread->arch.priv_stack_start - STACK_GUARD_SIZE,
+			STACK_GUARD_SIZE);
+	}
+#endif
 	arc_core_mpu_configure(THREAD_STACK_GUARD_REGION,
 			       thread->stack_info.start - STACK_GUARD_SIZE,
-			       thread->stack_info.size);
-	arc_core_mpu_enable();
+			       STACK_GUARD_SIZE);
+
 }
 #endif
+
+#if defined(CONFIG_USERSPACE)
+/*
+ * @brief Configure MPU user context
+ *
+ * This function configures the thread's user context.
+ * The functionality is meant to be used during context switch.
+ *
+ * @param thread thread info data structure.
+ */
+void configure_mpu_user_context(struct k_thread *thread)
+{
+	SYS_LOG_DBG("configure user thread %p's context", thread);
+	arc_core_mpu_configure_user_context(thread);
+}
+
+
+/*
+ * @brief Configure MPU memory domain
+ *
+ * This function configures per thread memory domain reprogramming the MPU.
+ * The functionality is meant to be used during context switch.
+ *
+ * @param thread thread info data structure.
+ */
+void configure_mpu_mem_domain(struct k_thread *thread)
+{
+	SYS_LOG_DBG("configure thread %p's domain", thread);
+	arc_core_mpu_configure_mem_domain(thread->mem_domain_info.mem_domain);
+}
+
+int _arch_mem_domain_max_partitions_get(void)
+{
+	return arc_core_mpu_get_max_domain_partition_regions();
+}
+
+/*
+ * Reset MPU region for a single memory partition
+ */
+void _arch_mem_domain_partition_remove(struct k_mem_domain *domain,
+				       u32_t  partition_id)
+{
+	ARG_UNUSED(domain);
+
+	arc_core_mpu_disable();
+	arc_core_mpu_mem_partition_remove(partition_id);
+	arc_core_mpu_enable();
+
+}
+
+/*
+ * Configure MPU memory domain
+ */
+void _arch_mem_domain_configure(struct k_thread *thread)
+{
+	configure_mpu_mem_domain(thread);
+}
+
+/*
+ * Destroy MPU regions for the mem domain
+ */
+void _arch_mem_domain_destroy(struct k_mem_domain *domain)
+{
+	ARG_UNUSED(domain);
+
+	arc_core_mpu_disable();
+	arc_core_mpu_configure_mem_domain(NULL);
+	arc_core_mpu_enable();
+}
+
+/*
+ * Validate the given buffer is user accessible or not
+ */
+int _arch_buffer_validate(void *addr, size_t size, int write)
+{
+	return arc_core_mpu_buffer_validate(addr, size, write);
+}
+
+#endif

arch/arc/core/mpu/arc_mpu.c

@@ -11,6 +11,7 @@
 #include <arch/arc/v2/aux_regs.h>
 #include <arch/arc/v2/mpu/arc_mpu.h>
 #include <arch/arc/v2/mpu/arc_core_mpu.h>
+#include <linker/linker-defs.h>
 #include <logging/sys_log.h>
 
 
@@ -20,12 +21,20 @@
 
 #define AUX_MPU_RDP_REGION_SIZE(bits)  \
 			(((bits - 1) & 0x3) | (((bits - 1) & 0x1C) << 7))
+
 #define AUX_MPU_RDP_ATTR_MASK (0xFFF)
 
 #define _ARC_V2_MPU_EN   (0x409)
 #define _ARC_V2_MPU_RDB0 (0x422)
 #define _ARC_V2_MPU_RDP0 (0x423)
 
+/* aux regs added in MPU version 3 */
+#define _ARC_V2_MPU_INDEX	(0x448) /* MPU index */
+#define _ARC_V2_MPU_RSTART	(0x449) /* MPU region start address */
+#define _ARC_V2_MPU_REND	(0x44A) /* MPU region end address */
+#define _ARC_V2_MPU_RPER	(0x44B) /* MPU region permission register */
+#define _ARC_V2_MPU_PROBE	(0x44C) /* MPU probe register */
+
 /* For MPU version 2, the minimum protection region size is 2048 bytes */
 /* FOr MPU version 3, the minimum protection region size is 32 bytes */
 #if CONFIG_ARC_MPU_VER == 2
@@ -34,8 +43,12 @@
 #define ARC_FEATURE_MPU_ALIGNMENT_BITS 5
 #endif
 
+#define CALC_REGION_END_ADDR(start, size) \
+		(start + size - (1 << ARC_FEATURE_MPU_ALIGNMENT_BITS))
+
+
 /**
- * @brief Get the number of supported mpu regions
+ * @brief Get the number of supported MPU regions
  *
  */
 static inline u8_t _get_num_regions(void)
@@ -47,36 +60,225 @@ static inline u8_t _get_num_regions(void)
 	return (u8_t)num;
 }
 
-
 /**
  * This internal function is utilized by the MPU driver to parse the intent
  * type (i.e. THREAD_STACK_REGION) and return the correct parameter set.
  */
-static inline u32_t _get_region_attr_by_type(u32_t type, u32_t size)
+static inline u32_t _get_region_attr_by_type(u32_t type)
 {
 	switch (type) {
+	case THREAD_STACK_USER_REGION:
+		return REGION_RAM_ATTR;
 	case THREAD_STACK_REGION:
-		return 0;
+		return  AUX_MPU_RDP_KW | AUX_MPU_RDP_KR;
+	case THREAD_APP_DATA_REGION:
+		return REGION_RAM_ATTR;
 	case THREAD_STACK_GUARD_REGION:
-	/* no Read, Write and Execute to guard region */
-		return  AUX_MPU_RDP_REGION_SIZE(
-			ARC_FEATURE_MPU_ALIGNMENT_BITS);
+	/* no Write and Execute to guard region */
+		return AUX_MPU_RDP_UR | AUX_MPU_RDP_KR;
 	default:
 		/* Size 0 region */
 		return 0;
 	}
 }
 
-static inline void _region_init(u32_t index, u32_t region_addr,
+static inline void _region_init(u32_t index, u32_t region_addr, u32_t size,
 			 u32_t region_attr)
 {
-
+/* ARC MPU version 2 and version 3 have different aux reg interface */
+#if CONFIG_ARC_MPU_VER == 2
+	u8_t bits = find_msb_set(size) - 1;
 	index = 2 * index;
 
+	if (bits < ARC_FEATURE_MPU_ALIGNMENT_BITS) {
+		bits = ARC_FEATURE_MPU_ALIGNMENT_BITS;
+	}
+
+	if ((1 << bits) < size) {
+		bits++;
+	}
+
+	if (size > 0) {
+		region_attr |= AUX_MPU_RDP_REGION_SIZE(bits);
+		region_addr |= AUX_MPU_RDB_VALID_MASK;
+	} else {
+		region_addr = 0;
+	}
+
 	_arc_v2_aux_reg_write(_ARC_V2_MPU_RDP0 + index, region_attr);
 	_arc_v2_aux_reg_write(_ARC_V2_MPU_RDB0 + index, region_addr);
+
+#elif CONFIG_ARC_MPU_VER == 3
+#define AUX_MPU_RPER_SID1	0x10000
+	if (size < (1 << ARC_FEATURE_MPU_ALIGNMENT_BITS)) {
+		size = (1 << ARC_FEATURE_MPU_ALIGNMENT_BITS);
+	}
+
+/* all MPU regions SID are the same: 1, the default SID */
+	if (region_attr) {
+		region_attr |=  (AUX_MPU_RDB_VALID_MASK | AUX_MPU_RDP_S |
+				 AUX_MPU_RPER_SID1);
+	}
+
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, index);
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_RSTART, region_addr);
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_REND,
+				CALC_REGION_END_ADDR(region_addr, size));
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_RPER, region_attr);
+#endif
 }
 
+#if CONFIG_ARC_MPU_VER == 3
+static inline s32_t _mpu_probe(u32_t addr)
+{
+	u32_t val;
+
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_PROBE, addr);
+	val = _arc_v2_aux_reg_read(_ARC_V2_MPU_INDEX);
+
+	/* if no match or multiple regions match, return error */
+	if (val & 0xC0000000) {
+		return -1;
+	} else {
+		return val;
+	}
+}
+#endif
+
+/**
+ * This internal function is utilized by the MPU driver to parse the intent
+ * type (i.e. THREAD_STACK_REGION) and return the correct region index.
+ */
+static inline u32_t _get_region_index_by_type(u32_t type)
+{
+	/*
+	 * The new MPU regions are allocated per type after the statically
+	 * configured regions. The type is one-indexed rather than
+	 * zero-indexed.
+	 *
+	 * For ARC MPU v2, the smaller index has higher priority, so the
+	 * index is allocated in reverse order. Static regions start from
+	 * the biggest index, then thread related regions.
+	 *
+	 * For ARC MPU v3, each index has the same priority, so the index is
+	 * allocated from small to big. Static regions start from 0, then
+	 * thread related regions.
+	 */
+	switch (type) {
+#if CONFIG_ARC_MPU_VER  == 2
+	case THREAD_STACK_USER_REGION:
+		return _get_num_regions() - mpu_config.num_regions
+		 - THREAD_STACK_REGION;
+	case THREAD_STACK_REGION:
+	case THREAD_APP_DATA_REGION:
+	case THREAD_STACK_GUARD_REGION:
+		return _get_num_regions() - mpu_config.num_regions - type;
+	case THREAD_DOMAIN_PARTITION_REGION:
+#if defined(CONFIG_MPU_STACK_GUARD)
+		return _get_num_regions() - mpu_config.num_regions - type;
+#else
+		/*
+		 * Start domain partition region from stack guard region
+		 * since stack guard is not enabled.
+		 */
+		return _get_num_regions() - mpu_config.num_regions - type + 1;
+#endif
+#elif CONFIG_ARC_MPU_VER == 3
+	case THREAD_STACK_USER_REGION:
+		return mpu_config.num_regions + THREAD_STACK_REGION - 1;
+	case THREAD_STACK_REGION:
+	case THREAD_APP_DATA_REGION:
+	case THREAD_STACK_GUARD_REGION:
+		return mpu_config.num_regions + type - 1;
+	case THREAD_DOMAIN_PARTITION_REGION:
+#if defined(CONFIG_MPU_STACK_GUARD)
+		return mpu_config.num_regions + type - 1;
+#else
+		/*
+		 * Start domain partition region from stack guard region
+		 * since stack guard is not enabled.
+		 */
+		return mpu_config.num_regions + type - 2;
+#endif
+#endif
+	default:
+		__ASSERT(0, "Unsupported type");
+		return 0;
+	}
+}
+
+/**
+ * This internal function checks if region is enabled or not
+ */
+static inline int _is_enabled_region(u32_t r_index)
+{
+#if CONFIG_ARC_MPU_VER == 2
+	return ((_arc_v2_aux_reg_read(_ARC_V2_MPU_RDB0 + 2 * r_index)
+		& AUX_MPU_RDB_VALID_MASK) == AUX_MPU_RDB_VALID_MASK);
+#elif CONFIG_ARC_MPU_VER == 3
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, r_index);
+	return ((_arc_v2_aux_reg_read(_ARC_V2_MPU_RPER) &
+		 AUX_MPU_RDB_VALID_MASK) == AUX_MPU_RDB_VALID_MASK);
+#endif
+}
+
+/**
+ * This internal function check if the given buffer in in the region
+ */
+static inline int _is_in_region(u32_t r_index, u32_t start, u32_t size)
+{
+#if CONFIG_ARC_MPU_VER == 2
+	u32_t r_addr_start;
+	u32_t r_addr_end;
+	u32_t r_size_lshift;
+
+	r_addr_start = _arc_v2_aux_reg_read(_ARC_V2_MPU_RDB0 + 2 * r_index)
+			& (~AUX_MPU_RDB_VALID_MASK);
+	r_size_lshift = _arc_v2_aux_reg_read(_ARC_V2_MPU_RDP0 + 2 * r_index)
+			& AUX_MPU_RDP_ATTR_MASK;
+	r_size_lshift = (r_size_lshift & 0x3) | ((r_size_lshift >> 7) & 0x1C);
+	r_addr_end = r_addr_start  + (1 << (r_size_lshift + 1));
+
+	if (start >= r_addr_start && (start + size) < r_addr_end) {
+		return 1;
+	}
+
+#elif CONFIG_ARC_MPU_VER == 3
+
+	if ((r_index == _mpu_probe(start)) &&
+		(r_index == _mpu_probe(start + size))) {
+		return 1;
+	}
+#endif
+
+
+
+	return 0;
+}
+
+/**
+ * This internal function check if the region is user accessible or not
+ */
+static inline int _is_user_accessible_region(u32_t r_index, int write)
+{
+	u32_t r_ap;
+
+#if CONFIG_ARC_MPU_VER == 2
+	r_ap = _arc_v2_aux_reg_read(_ARC_V2_MPU_RDP0 + 2 * r_index);
+#elif CONFIG_ARC_MPU_VER == 3
+	_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, r_index);
+	r_ap = _arc_v2_aux_reg_read(_ARC_V2_MPU_RPER);
+#endif
+	r_ap &= AUX_MPU_RDP_ATTR_MASK;
+
+	if (write) {
+		return ((r_ap & (AUX_MPU_RDP_UW | AUX_MPU_RDP_KW)) ==
+			(AUX_MPU_RDP_UW | AUX_MPU_RDP_KW));
+	}
+
+	return ((r_ap & (AUX_MPU_RDP_UR | AUX_MPU_RDP_KR)) ==
+			(AUX_MPU_RDP_UR | AUX_MPU_RDP_KR));
+}
 
 /* ARC Core MPU Driver API Implementation for ARC MPU */
 
@@ -85,9 +287,17 @@ static inline void _region_init(u32_t index, u32_t region_addr,
  */
 void arc_core_mpu_enable(void)
 {
+#if CONFIG_ARC_MPU_VER == 2
 	/* Enable MPU */
 	_arc_v2_aux_reg_write(_ARC_V2_MPU_EN,
 		_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) | AUX_MPU_EN_ENABLE);
+
+	/* MPU is always enabled, use default region to
+	 * simulate MPU enable
+	 */
+#elif CONFIG_ARC_MPU_VER == 3
+	arc_core_mpu_default(0);
+#endif
 }
 
 /**
@@ -95,12 +305,18 @@ void arc_core_mpu_enable(void)
  */
 void arc_core_mpu_disable(void)
 {
+#if CONFIG_ARC_MPU_VER == 2
 	/* Disable MPU */
 	_arc_v2_aux_reg_write(_ARC_V2_MPU_EN,
 		_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) & AUX_MPU_EN_DISABLE);
+#elif CONFIG_ARC_MPU_VER == 3
+	/* MPU is always enabled, use default region to
+	 * simulate MPU disable
+	 */
+	arc_core_mpu_default(REGION_ALL_ATTR);
+#endif
 }
 
-
 /**
  * @brief configure the base address and size for an MPU region
  *
@@ -110,34 +326,81 @@ void arc_core_mpu_disable(void)
  */
 void arc_core_mpu_configure(u8_t type, u32_t base, u32_t size)
 {
-	u32_t region_index;
-	u32_t region_attr;
+	u32_t region_index =  _get_region_index_by_type(type);
+	u32_t region_attr = _get_region_attr_by_type(type);
 
 	SYS_LOG_DBG("Region info: 0x%x 0x%x", base, size);
-	/*
-	 * The new MPU regions are allocated per type before
-	 * the statically configured regions.
-	 *
-	 * For ARC MPU v2, MPU regions can be overlapped, smaller
-	 * region index has higher priority.
-	 */
-
-	region_index = _get_num_regions() - mpu_config.num_regions;
-
-	if (type > region_index) {
-		return;
-	}
-
-	region_index -= type;
-	region_attr = _get_region_attr_by_type(type, size);
 
 	if (region_attr == 0) {
 		return;
 	}
+	/*
+	 * The new MPU regions are allocated per type before
+	 * the statically configured regions.
+	 */
+#if CONFIG_ARC_MPU_VER == 2
+	/*
+	 * For ARC MPU v2, MPU regions can be overlapped, smaller
+	 * region index has higher priority.
+	 */
+	_region_init(region_index, base, size, region_attr);
+#elif CONFIG_ARC_MPU_VER == 3
+	static s32_t last_index;
+	s32_t index;
+	u32_t last_region = _get_num_regions() - 1;
 
-	base |= AUX_MPU_RDB_VALID_MASK;
 
-	_region_init(region_index, base, region_attr);
+	/* use hardware probe to find the region maybe split.
+	 * another way is to look up the mpu_config.mpu_regions
+	 * in software, which is time consuming.
+	 */
+	index = _mpu_probe(base);
+
+	/* ARC MPU version 3 doesn't support region overlap.
+	 * So it can not be directly used for stack/stack guard protect
+	 * One way to do this is splitting the ram region as follow:
+	 *
+	 *  Take THREAD_STACK_GUARD_REGION as example:
+	 *  RAM region 0: the ram region before THREAD_STACK_GUARD_REGION, rw
+	 *  RAM THREAD_STACK_GUARD_REGION: RO
+	 *  RAM region 1: the region after THREAD_STACK_GUARD_REGION, same
+	 *                as region 0
+	 *  if region_index == index, it means the same thread comes back,
+	 *  no need to split
+	 */
+
+	if (index >= 0 && region_index != index) {
+		/* need to split, only 1 split is allowed */
+		/* find the correct region to mpu_config.mpu_regions */
+		if (index == last_region) {
+			/* already split */
+			index = last_index;
+		} else {
+			/* new split */
+			last_index = index;
+		}
+
+		_region_init(index,
+			mpu_config.mpu_regions[index].base,
+			base - mpu_config.mpu_regions[index].base,
+			mpu_config.mpu_regions[index].attr);
+
+#if defined(CONFIG_MPU_STACK_GUARD)
+		if (type != THREAD_STACK_USER_REGION)
+			/*
+			 * USER REGION is continuous with MPU_STACK_GUARD.
+			 * In current implementation, THREAD_STACK_GUARD_REGION is
+			 * configured before THREAD_STACK_USER_REGION
+			 */
+#endif
+			_region_init(last_region, base + size,
+				(mpu_config.mpu_regions[index].base +
+				mpu_config.mpu_regions[index].size - base - size),
+				mpu_config.mpu_regions[index].attr);
+	}
+
+	_region_init(region_index, base, size, region_attr);
+#endif
 }
 
 /**
@@ -155,26 +418,216 @@ void arc_core_mpu_default(u32_t region_attr)
 	_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, region_attr | val);
 }
 
-
 /**
- * @brief configure the mpu region
+ * @brief configure the MPU region
  *
  * @param   index   MPU region index
  * @param   base    base address
  * @param   region_attr region attribute
  */
-void arc_core_mpu_region(u32_t index, u32_t base, u32_t region_attr)
+void arc_core_mpu_region(u32_t index, u32_t base, u32_t size,
+			u32_t region_attr)
 {
 	if (index >= _get_num_regions()) {
 		return;
 	}
 
-	base |= AUX_MPU_RDB_VALID_MASK;
 	region_attr &= AUX_MPU_RDP_ATTR_MASK;
 
-	_region_init(index, base, region_attr);
+	_region_init(index, base, size, region_attr);
 }
 
+#if defined(CONFIG_USERSPACE)
+void arc_core_mpu_configure_user_context(struct k_thread *thread)
+{
+	u32_t base = (u32_t)thread->stack_obj;
+	u32_t size = thread->stack_info.size;
+
+	/* for kernel threads, no need to configure user context */
+	if (!thread->arch.priv_stack_start) {
+		return;
+	}
+
+	arc_core_mpu_configure(THREAD_STACK_USER_REGION, base, size);
+
+	/* configure app data portion */
+#ifdef CONFIG_APPLICATION_MEMORY
+#if CONFIG_ARC_MPU_VER == 2
+	/*
+	 * _app_ram_size is guaranteed to be power of two, and
+	 * _app_ram_start is guaranteed to be aligned _app_ram_size
+	 * in linker template
+	 */
+	base = (u32_t)&__app_ram_start;
+	size = (u32_t)&__app_ram_size;
+
+	/* set up app data region if exists, otherwise disable */
+	if (size > 0) {
+		arc_core_mpu_configure(THREAD_APP_DATA_REGION, base, size);
+	}
+#elif CONFIG_ARC_MPU_VER == 3
+	/*
+	 * ARC MPV v3 doesn't support MPU region overlap.
+	 * Application memory should be a static memory, defined in mpu_config
+	 */
+#endif
+#endif
+}
+
+/**
+ * @brief configure MPU regions for the memory partitions of the memory domain
+ *
+ * @param   mem_domain    memory domain that thread belongs to
+ */
+void arc_core_mpu_configure_mem_domain(struct k_mem_domain *mem_domain)
+{
+	s32_t region_index =
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
+	u32_t num_partitions;
+	struct k_mem_partition *pparts;
+
+	if (mem_domain) {
+		SYS_LOG_DBG("configure domain: %p", mem_domain);
+		num_partitions = mem_domain->num_partitions;
+		pparts = mem_domain->partitions;
+	} else {
+		SYS_LOG_DBG("disable domain partition regions");
+		num_partitions = 0;
+		pparts = NULL;
+	}
+#if CONFIG_ARC_MPU_VER == 2
+	for (; region_index >= 0; region_index--) {
+#elif CONFIG_ARC_MPU_VER == 3
+/*
+ * Note: For ARC MPU v3, overlapping is not allowed, so the following
+ * partitions/region may be overlapped with each other or regions in
+ * mpu_config. This will cause EV_MachineCheck exception (ECR = 0x030600).
+ * Although split mechanism is used for stack guard region to avoid this,
+ * it doesn't work for memory domain, because the dynamic region numbers.
+ * So be careful to avoid the overlap situation.
+ */
+	for (; region_index <  _get_num_regions() - 1; region_index++) {
+#endif
+		if (num_partitions && pparts->size) {
+			SYS_LOG_DBG("set region 0x%x 0x%x 0x%x",
+				    region_index, pparts->start, pparts->size);
+			_region_init(region_index, pparts->start, pparts->size,
+					pparts->attr);
+			num_partitions--;
+		} else {
+			SYS_LOG_DBG("disable region 0x%x", region_index);
+			/* Disable region */
+			_region_init(region_index, 0, 0, 0);
+		}
+		pparts++;
+	}
+}
+
+/**
+ * @brief configure MPU region for a single memory partition
+ *
+ * @param   part_index  memory partition index
+ * @param   part        memory partition info
+ */
+void arc_core_mpu_configure_mem_partition(u32_t part_index,
+					  struct k_mem_partition *part)
+{
+	u32_t region_index =
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
+
+	SYS_LOG_DBG("configure partition index: %u", part_index);
+
+	if (part) {
+		SYS_LOG_DBG("set region 0x%x 0x%x 0x%x",
+			    region_index + part_index, part->start, part->size);
+		_region_init(region_index, part->start, part->size,
+				part->attr);
+	} else {
+		SYS_LOG_DBG("disable region 0x%x", region_index + part_index);
+		/* Disable region */
+		_region_init(region_index + part_index, 0, 0, 0);
+	}
+}
+
+/**
+ * @brief Reset MPU region for a single memory partition
+ *
+ * @param   part_index  memory partition index
+ */
+void arc_core_mpu_mem_partition_remove(u32_t part_index)
+{
+	u32_t region_index =
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
+
+	SYS_LOG_DBG("disable region 0x%x", region_index + part_index);
+	/* Disable region */
+	_region_init(region_index + part_index, 0, 0, 0);
+}
+
+/**
+ * @brief get the maximum number of free regions for memory domain partitions
+ */
+int arc_core_mpu_get_max_domain_partition_regions(void)
+{
+#if CONFIG_ARC_MPU_VER == 2
+	return _get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION) + 1;
+#elif CONFIG_ARC_MPU_VER == 3
+	/*
+	 * Subtract the start of domain partition regions and 1 reserved region
+	 * from total regions will get the maximum number of free regions for
+	 * memory domain partitions.
+	 */
+	return _get_num_regions() -
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION) - 1;
+#endif
+}
+
+/**
+ * @brief validate the given buffer is user accessible or not
+ */
+int arc_core_mpu_buffer_validate(void *addr, size_t size, int write)
+{
+	s32_t r_index;
+
+
+	/*
+	 * For ARC MPU v2, smaller region number takes priority.
+	 * we can stop the iteration immediately once we find the
+	 * matched region that grants permission or denies access.
+	 *
+	 * For ARC MPU v3, overlapping is not supported.
+	 * we can stop the iteration immediately once we find the
+	 * matched region that grants permission or denies access.
+	 */
+#if CONFIG_ARC_MPU_VER == 2
+	for (r_index = 0; r_index < _get_num_regions(); r_index++) {
+		if (!_is_enabled_region(r_index) ||
+		    !_is_in_region(r_index, (u32_t)addr, size)) {
+			continue;
+		}
+
+		if (_is_user_accessible_region(r_index, write)) {
+			return 0;
+		} else {
+			return -EPERM;
+		}
+	}
+#elif CONFIG_ARC_MPU_VER == 3
+	r_index = _mpu_probe((u32_t)addr);
+	/*  match and the area is in one region */
+	if (r_index >= 0 && r_index == _mpu_probe((u32_t)addr + size)) {
+		if (_is_user_accessible_region(r_index, write)) {
+			return 0;
+		} else {
+			return -EPERM;
+		}
+	}
+#endif
+
+	return -EPERM;
+}
+#endif /* CONFIG_USERSPACE */
+
 /* ARC MPU Driver Initial Setup */
 
 /*
@@ -185,7 +638,6 @@ void arc_core_mpu_region(u32_t index, u32_t base, u32_t region_attr)
  */
 static void _arc_mpu_config(void)
 {
-	u32_t r_index;
 	u32_t num_regions;
 	u32_t i;
 
@@ -196,35 +648,50 @@ static void _arc_mpu_config(void)
 		return;
 	}
 
+	/* Disable MPU */
+	arc_core_mpu_disable();
+
+#if CONFIG_ARC_MPU_VER == 2
+	u32_t r_index;
 	/*
 	 * the MPU regions are filled in the reverse order.
-	 * According to ARCv2 ISA, the mpu region with smaller
-	 * index has higher priority. The static background mpu
+	 * According to ARCv2 ISA, the MPU region with smaller
+	 * index has higher priority. The static background MPU
 	 * regions in mpu_config will be in the bottom. Then
 	 * the special type regions will be above.
 	 *
 	 */
 	r_index = num_regions - mpu_config.num_regions;
-	/* Disable MPU */
-	arc_core_mpu_disable();
 
-	/* clear the regions reserved for special type */
+	/* clear all the regions first */
 	for (i = 0; i < r_index; i++) {
-		_region_init(i, 0, 0);
+		_region_init(i, 0, 0, 0);
 	}
 
 	/* configure the static regions */
-	for (r_index = 0; i < num_regions; i++) {
-		_region_init(i,
-			mpu_config.mpu_regions[r_index].base
-			| AUX_MPU_RDB_VALID_MASK,
-			mpu_config.mpu_regions[r_index].attr);
+	for (i = 0; i < mpu_config.num_regions; i++) {
+		_region_init(r_index,
+			mpu_config.mpu_regions[i].base,
+			mpu_config.mpu_regions[i].size,
+			mpu_config.mpu_regions[i].attr);
 		r_index++;
 	}
 
 	/* default region: no read, write and execute */
 	arc_core_mpu_default(0);
 
+#elif CONFIG_ARC_MPU_VER == 3
+	for (i = 0; i < mpu_config.num_regions; i++) {
+		_region_init(i,
+			mpu_config.mpu_regions[i].base,
+			mpu_config.mpu_regions[i].size,
+			mpu_config.mpu_regions[i].attr);
+	}
+
+	for (; i < num_regions; i++) {
+		_region_init(i, 0, 0, 0);
+	}
+#endif
 	/* Enable MPU */
 	arc_core_mpu_enable();
 }

arch/arc/core/offsets/offsets.c

@@ -79,6 +79,14 @@ GEN_OFFSET_SYM(_callee_saved_stack_t, r24);
 GEN_OFFSET_SYM(_callee_saved_stack_t, r25);
 GEN_OFFSET_SYM(_callee_saved_stack_t, r26);
 GEN_OFFSET_SYM(_callee_saved_stack_t, fp);
+#ifdef CONFIG_USERSPACE
+#ifdef CONFIG_ARC_HAS_SECURE
+GEN_OFFSET_SYM(_callee_saved_stack_t, kernel_sp);
+GEN_OFFSET_SYM(_callee_saved_stack_t, user_sp);
+#else
+GEN_OFFSET_SYM(_callee_saved_stack_t, user_sp);
+#endif
+#endif
 GEN_OFFSET_SYM(_callee_saved_stack_t, r30);
 #ifdef CONFIG_FP_SHARING
 GEN_OFFSET_SYM(_callee_saved_stack_t, r58);

arch/arc/core/prep_c.c

@@ -21,7 +21,7 @@
 #include <linker/linker-defs.h>
 #include <arch/arc/v2/aux_regs.h>
 #include <kernel_structs.h>
-#include <nano_internal.h>
+#include <kernel_internal.h>
 
 
 /* XXX - keep for future use in full-featured cache APIs */
@@ -87,6 +87,10 @@ static void invalidate_dcache(void)
 
 static void adjust_vector_table_base(void)
 {
+#ifdef CONFIG_ARC_HAS_SECURE
+#undef _ARC_V2_IRQ_VECT_BASE
+#define _ARC_V2_IRQ_VECT_BASE _ARC_V2_IRQ_VECT_BASE_S
+#endif
 	extern struct vector_table _VectorTable;
 	unsigned int vbr;
 	/* if the compiled-in vector table is different

arch/arc/core/regular_irq.S

@@ -161,10 +161,10 @@ _rirq_common_interrupt_swap:
 	 */
 	_load_callee_saved_regs
 
-#ifdef CONFIG_MPU_STACK_GUARD
+#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
 	push_s r2
 	mov r0, r2
-	bl configure_mpu_stack_guard
+	bl configure_mpu_thread
 	pop_s r2
 #endif
 
@@ -180,27 +180,27 @@ _rirq_common_interrupt_swap:
 .balign 4
 _rirq_return_from_coop:
 
-	/* status32 and pc (blink) are already on the stack in the right order */
+	/*
+	 * status32, sec_stat (when CONFIG_ARC_HAS_SECURE is enabled) and pc
+	 * (blink) are already on the stack in the right order
+	 */
+	ld_s r0, [sp, ___isf_t_status32_OFFSET - ___isf_t_pc_OFFSET]
 
 	/* update status32.ie (explanation in firq_exit:_firq_return_from_coop) */
-	ld_s r0, [sp, 4]
+
 	ld_s r3, [r2, _thread_offset_to_intlock_key]
 	st  0, [r2, _thread_offset_to_intlock_key]
 	cmp r3, 0
 	or.ne r0, r0, _ARC_V2_STATUS32_IE
-	st_s r0, [sp, 4]
+
+	st_s r0, [sp, ___isf_t_status32_OFFSET - ___isf_t_pc_OFFSET]
 
 	/* carve fake stack */
+	sub sp, sp, ___isf_t_pc_OFFSET
 
-	/*
-	 * a) status32/pc are already on the stack
-	 * b) a real value will be pushed in r0
-	 */
-	sub sp, sp, (___isf_t_SIZEOF - 12)
-
-	/* push return value on stack */
+	/* update return value on stack */
 	ld_s r0, [r2, _thread_offset_to_return_value]
-	push_s r0
+	st_s r0, [sp, ___isf_t_r0_OFFSET]
 
 	/*
 	 * r13 is part of both the callee and caller-saved register sets because

arch/arc/core/reset.S

@@ -11,7 +11,6 @@
  * Reset handler that prepares the system for running C code.
  */
 
-// #include <board.h>
 #include <toolchain.h>
 #include <linker/sections.h>
 #include <arch/cpu.h>
@@ -48,6 +47,11 @@ SECTION_FUNC(TEXT,__start)
 	/* lock interrupts: will get unlocked when switch to main task */
 	clri
 
+#if CONFIG_USERSPACE
+	lr r0, [_ARC_V2_STATUS32]
+	bset r0, r0, _ARC_V2_STATUS32_US_BIT
+	kflag r0
+#endif
 	mov r1, 1
 
 invalidate_and_disable_icache:

arch/arc/core/swap.S

@@ -71,7 +71,7 @@ SECTION_FUNC(TEXT, __swap)
 	st _CAUSE_COOP, [r2, _thread_offset_to_relinquish_cause]
 
 	/*
-         * Carve space for the return value. Setting it to a defafult of
+         * Carve space for the return value. Setting it to a default of
          * -EAGAIN eliminates the need for the timeout code to set it.
          * If another value is ever needed, it can be modified with
          * _set_thread_return_value().
@@ -90,6 +90,11 @@ SECTION_FUNC(TEXT, __swap)
 	bclr r3, r3, _ARC_V2_STATUS32_SC_BIT
 	kflag r3
 #endif
+
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr r3, [_ARC_V2_SEC_STAT]
+	push_s r3
+#endif
 	push_s blink
 
 	_save_callee_saved_regs
@@ -110,10 +115,10 @@ SECTION_FUNC(TEXT, __swap)
 
 	_load_callee_saved_regs
 
-#ifdef CONFIG_MPU_STACK_GUARD
+#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
 	push_s r2
 	mov r0, r2
-	bl configure_mpu_stack_guard
+	bl configure_mpu_thread
 	pop_s r2
 #endif
 
@@ -137,6 +142,12 @@ _swap_return_from_coop:
 	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
 
 	pop_s blink /* pc into blink */
+#ifdef CONFIG_ARC_HAS_SECURE
+	pop_s r3    /* pop SEC_STAT */
+	/* sflag r3 */
+	/* sflag instruction is not supported in current ARC GNU */
+	.long 0x00ff302f
+#endif
 	pop_s r3    /* status32 into r3 */
 	kflag r3    /* write status32 */
 
@@ -152,10 +163,21 @@ _swap_return_from_firq:
 	bbit1 r3, _ARC_V2_STATUS32_AE_BIT, _return_from_exc_irq
 
 	/* pretend interrupt happened to use rtie instruction */
-	lr r3, [_ARC_V2_AUX_IRQ_ACT]
-	brne r3,0,_swap_already_in_irq
 
-	or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1)) /* use lowest */
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr r3, [_ARC_V2_SEC_STAT]
+	/* set SEC_STAT.IRM = SECURE for interrupt return */
+	bset r3, r3, 3
+	/* sflag r3 */
+	/* sflag instruction is not supported in current ARC GNU */
+	.long 0x00ff302f
+#endif
+
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	brne r3, 0, _swap_already_in_irq
+
+	/* use lowest interrupt priority */
+	or r3, r3, (1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1))
 	sr r3, [_ARC_V2_AUX_IRQ_ACT]
 
 _swap_already_in_irq:
@@ -164,7 +186,7 @@ _swap_already_in_irq:
 .balign 4
 _return_from_exc_irq:
 	_pop_irq_stack_frame
-	sub_s sp, sp, 8
+	sub_s sp, sp, ___isf_t_status32_OFFSET - ___isf_t_pc_OFFSET + 4
 
 _return_from_exc:
 
@@ -172,8 +194,10 @@ _return_from_exc:
 	ld ilink, [sp] /* pc into ilink */
 	sr ilink, [_ARC_V2_ERET]
 
+	/* SEC_STAT is bypassed when CONFIG_ARC_HAS_SECURE */
+
 	/* put status32 into estatus */
-	ld ilink, [sp, 4] /* status32 into ilink */
+	ld ilink, [sp, ___isf_t_status32_OFFSET - ___isf_t_pc_OFFSET]
 	sr ilink, [_ARC_V2_ERSTATUS]
-	add_s sp, sp, 8
+	add_s sp, sp, ___isf_t_status32_OFFSET - ___isf_t_pc_OFFSET + 4
 	rtie

arch/arc/core/thread.c

@@ -19,9 +19,17 @@
 #ifdef CONFIG_INIT_STACKS
 #include <string.h>
 #endif /* CONFIG_INIT_STACKS */
+
+#ifdef CONFIG_USERSPACE
+#include <arch/arc/v2/mpu/arc_core_mpu.h>
+#endif
+
 /*  initial stack frame */
 struct init_stack_frame {
 	u32_t pc;
+#ifdef CONFIG_ARC_HAS_SECURE
+	u32_t sec_stat;
+#endif
 	u32_t status32;
 	u32_t r3;
 	u32_t r2;
@@ -54,24 +62,62 @@ struct init_stack_frame {
  *
  * @return N/A
  */
-void _new_thread(struct k_thread *thread, k_thread_stack_t stack,
-		 size_t stackSize, _thread_entry_t pEntry,
+void _new_thread(struct k_thread *thread, k_thread_stack_t *stack,
+		 size_t stackSize, k_thread_entry_t pEntry,
 		 void *parameter1, void *parameter2, void *parameter3,
 		 int priority, unsigned int options)
 {
 	char *pStackMem = K_THREAD_STACK_BUFFER(stack);
 	_ASSERT_VALID_PRIO(priority, pEntry);
 
-	char *stackEnd = pStackMem + stackSize;
+	char *stackEnd;
 	struct init_stack_frame *pInitCtx;
 
+#if CONFIG_USERSPACE
+#if CONFIG_ARC_MPU_VER == 2
+	stackSize = POW2_CEIL(STACK_SIZE_ALIGN(stackSize));
+#elif CONFIG_ARC_MPU_VER == 3
+	stackSize = ROUND_UP(stackSize, STACK_ALIGN);
+#endif
+#endif
+	stackEnd = pStackMem + stackSize;
+
+#if CONFIG_USERSPACE
+	/* for kernel thread, the privilege stack is merged into thread stack */
+	if (!(options & K_USER)) {
+	/* if MPU_STACK_GUARD is enabled, reserve the the stack area
+	 * |---------------------|    |----------------|
+	 * |  user stack         |    | stack guard    |
+	 * |---------------------| to |----------------|
+	 * |  stack guard        |    | kernel thread  |
+	 * |---------------------|    | stack          |
+	 * |  privilege stack    |    |                |
+	 * ---------------------------------------------
+	 */
+		pStackMem += STACK_GUARD_SIZE;
+		stackSize = stackSize + CONFIG_PRIVILEGED_STACK_SIZE;
+		stackEnd += CONFIG_PRIVILEGED_STACK_SIZE + STACK_GUARD_SIZE;
+	}
+#endif
 	_new_thread_init(thread, pStackMem, stackSize, priority, options);
 
 	/* carve the thread entry struct from the "base" of the stack */
 	pInitCtx = (struct init_stack_frame *)(STACK_ROUND_DOWN(stackEnd) -
 				       sizeof(struct init_stack_frame));
-
+#if CONFIG_USERSPACE
+	if (options & K_USER) {
+		pInitCtx->pc = ((u32_t)_user_thread_entry_wrapper);
+	} else {
+		pInitCtx->pc = ((u32_t)_thread_entry_wrapper);
+	}
+#else
 	pInitCtx->pc = ((u32_t)_thread_entry_wrapper);
+#endif
+
+#ifdef CONFIG_ARC_HAS_SECURE
+	pInitCtx->sec_stat = _arc_v2_aux_reg_read(_ARC_V2_SEC_STAT);
+#endif
+
 	pInitCtx->r0 = (u32_t)pEntry;
 	pInitCtx->r1 = (u32_t)parameter1;
 	pInitCtx->r2 = (u32_t)parameter2;
@@ -84,12 +130,34 @@ void _new_thread(struct k_thread *thread, k_thread_stack_t stack,
 	 * value.
 	 */
 #ifdef CONFIG_ARC_STACK_CHECKING
-	pInitCtx->status32 = _ARC_V2_STATUS32_SC | _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
+	pInitCtx->status32 = _ARC_V2_STATUS32_SC |
+		 _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
 	thread->arch.stack_base = (u32_t) stackEnd;
 #else
 	pInitCtx->status32 = _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
 #endif
 
+#if CONFIG_USERSPACE
+	/*
+	 * enable US bit, US is read as zero in user mode. This will allow use
+	 * mode sleep instructions, and it enables a form of denial-of-service
+	 * attack by putting the processor in sleep mode, but since interrupt
+	 * level/mask can't be set from user space that's not worse than
+	 * executing a loop without yielding.
+	 */
+	pInitCtx->status32 |= _ARC_V2_STATUS32_US;
+
+	if (options & K_USER) {
+		thread->arch.priv_stack_start =
+			(u32_t) (stackEnd + STACK_GUARD_SIZE);
+		thread->arch.priv_stack_size =
+			(u32_t)CONFIG_PRIVILEGED_STACK_SIZE;
+	} else {
+		thread->arch.priv_stack_start = 0;
+		thread->arch.priv_stack_size = 0;
+	}
+#endif
+
 #ifdef CONFIG_THREAD_MONITOR
 	/*
 	 * In debug mode thread->entry give direct access to the thread entry
@@ -113,3 +181,42 @@ void _new_thread(struct k_thread *thread, k_thread_stack_t stack,
 
 	thread_monitor_init(thread);
 }
+
+
+#ifdef CONFIG_USERSPACE
+
+FUNC_NORETURN void _arch_user_mode_enter(k_thread_entry_t user_entry,
+	void *p1, void *p2, void *p3)
+{
+	_current->base.user_options |= K_USER;
+
+	/*
+	 * ajust the thread stack layout
+	 * |----------------|    |---------------------|
+	 * | stack guard    |    |  user stack         |
+	 * |----------------| to |---------------------|
+	 * | kernel thread  |    |  stack guard        |
+	 * | stack          |    |---------------------|
+	 * |                |    |  privilege stack    |
+	 * ---------------------------------------------
+	 */
+	_current->stack_info.start = (u32_t)_current->stack_obj;
+	_current->stack_info.size -= CONFIG_PRIVILEGED_STACK_SIZE;
+
+	_current->arch.priv_stack_start =
+			(u32_t) (_current->stack_info.start +
+				 _current->stack_info.size + STACK_GUARD_SIZE);
+	_current->arch.priv_stack_size =
+			(u32_t)CONFIG_PRIVILEGED_STACK_SIZE;
+
+	/* possible optimizaiton: no need to load mem domain anymore */
+	/* need to lock cpu here ? */
+	configure_mpu_thread(_current);
+
+	_arc_userspace_enter(user_entry, p1, p2, p3,
+			     (u32_t)_current->stack_obj,
+			     _current->stack_info.size);
+	CODE_UNREACHABLE;
+}
+
+#endif

arch/arc/core/thread_entry_wrapper.S

@@ -15,7 +15,6 @@
 #include <linker/sections.h>
 
 GTEXT(_thread_entry_wrapper)
-GTEXT(_thread_entry)
 
 /*
  * @brief Wrapper for _thread_entry

arch/arc/core/userspace.S

@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2017 Synopsys.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <offsets_short.h>
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <kernel_structs.h>
+#include <arch/cpu.h>
+#include <syscall.h>
+
+.macro clear_scratch_regs
+	mov	r1, 0
+	mov 	r2, 0
+	mov	r3, 0
+	mov	r4, 0
+	mov	r5, 0
+	mov	r6, 0
+	mov	r7, 0
+	mov	r8, 0
+	mov 	r9, 0
+	mov	r10, 0
+	mov	r11, 0
+	mov	r12, 0
+
+	mov 	fp, 0
+	mov 	r29, 0
+	mov 	r30, 0
+	mov	blink, 0
+.endm
+
+.macro clear_callee_regs
+	mov	r25, 0
+	mov	r24, 0
+	mov	r23, 0
+	mov	r22, 0
+	mov	r21, 0
+	mov	r20, 0
+	mov	r19, 0
+	mov	r18, 0
+	mov	r17, 0
+	mov	r16, 0
+
+	mov	r15, 0
+	mov	r14, 0
+	mov	r13, 0
+.endm
+
+GTEXT(_arc_userspace_enter)
+GTEXT(_arc_do_syscall)
+GTEXT(_user_thread_entry_wrapper)
+
+
+
+/*
+ * @brief Wrapper for _thread_entry in the case of user thread
+ *
+ * @return N/A
+ */
+SECTION_FUNC(TEXT, _user_thread_entry_wrapper)
+	/* sp the  user stack pointer,  r0-r4 are in stack */
+	mov r5, sp
+	/* start of privilege stack */
+	add blink, r5, CONFIG_PRIVILEGED_STACK_SIZE+16
+
+	/* r4<- start  of user stack region */
+	mov r0, _kernel
+	ld_s r1, [r0, _kernel_offset_to_current]
+	ld r4, [r1, ___thread_stack_info_t_start_OFFSET]
+
+/*
+ * when CONFIG_INIT_STACK is enable, stack will be initialized
+ * in _new_thread_init.
+ */
+	j _arc_go_to_user_space
+
+/**
+ *
+ * User space entry function
+ *
+ * This function is the entry point to user mode from privileged execution.
+ * The conversion is one way, and threads which transition to user mode do
+ * not transition back later, unless they are doing system calls.
+ *
+ */
+SECTION_FUNC(TEXT, _arc_userspace_enter)
+	/*
+	 * In ARCv2, the U bit can only be set through exception return
+	 */
+	/* the end of user stack in r5 */
+	add r5, r4, r5
+	/* start of privilege stack */
+	add blink, r5, CONFIG_PRIVILEGED_STACK_SIZE
+	mov sp, r5
+
+	push_s r0
+	push_s r1
+	push_s r2
+	push_s r3
+
+	mov r5, sp /* skip r0, r1, r2, r3 */
+
+#ifdef CONFIG_INIT_STACKS
+	mov r0, 0xaaaaaaaa
+#else
+	mov r0, 0x0
+#endif
+_clear_user_stack:
+	st.ab r0, [r4, 4]
+	cmp r4, r5
+	jlt _clear_user_stack
+
+_arc_go_to_user_space:
+	lr r0, [_ARC_V2_STATUS32]
+	bset r0, r0, _ARC_V2_STATUS32_U_BIT
+
+	mov r1, _thread_entry_wrapper
+
+	/* fake exception return */
+	kflag _ARC_V2_STATUS32_AE
+
+	sr r0, [_ARC_V2_ERSTATUS]
+	sr r1, [_ARC_V2_ERET]
+
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr r0, [_ARC_V2_SEC_STAT]
+	/* the mode returns from exception return is secure mode */
+	bset r0, r0, 31
+	sr r0, [_ARC_V2_ERSEC_STAT]
+	sr r5, [_ARC_V2_SEC_U_SP]
+#else
+	/* when exception returns from kernel to user, sp and _ARC_V2_USER_SP
+	 * will be switched
+	 */
+	sr r5, [_ARC_V2_USER_SP]
+#endif
+	mov sp, blink
+
+	mov r0, 0
+
+	clear_callee_regs
+
+	clear_scratch_regs
+
+	rtie
+
+/**
+ *
+ * Userspace system call function
+ *
+ * This function is used to do system calls from unprivileged code.  This
+ * function is responsible for the following:
+ * 1) Dispatching the system call
+ * 2) Restoring stack and calling back to the caller of the system call
+ *
+ */
+SECTION_FUNC(TEXT, _arc_do_syscall)
+	/* r0-r5: arg1-arg6, r6 is call id */
+	/* the call id is already checked in trap_s handler */
+	push_s blink
+
+	mov blink, _k_syscall_table
+	ld.as r6, [blink, r6]
+
+	jl [r6]
+
+	pop_s blink
+
+	/* through fake exception return, go back to the caller */
+	kflag _ARC_V2_STATUS32_AE
+
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr r6, [_ARC_V2_SEC_STAT]
+	/* the mode returns from exception return is secure mode */
+	bset r6, r6, 31
+	sr r6, [_ARC_V2_ERSEC_STAT]
+#endif
+	/* the status and return addesss are saved in trap_s handler */
+	pop r6
+	sr r6, [_ARC_V2_ERSTATUS]
+	pop r6
+	sr r6, [_ARC_V2_ERET]
+
+	/* no nned to clear callee regs */
+	clear_scratch_regs
+
+	rtie

arch/arc/include/kernel_arch_data.h

@@ -32,13 +32,48 @@ extern "C" {
 
 #ifndef _ASMLANGUAGE
 #include <kernel.h>
-#include <nano_internal.h>
+#include <kernel_internal.h>
 #include <zephyr/types.h>
 #include <misc/util.h>
 #include <misc/dlist.h>
 #endif
 
 #ifndef _ASMLANGUAGE
+#ifdef CONFIG_ARC_HAS_SECURE
+struct _irq_stack_frame {
+	u32_t lp_end;
+	u32_t lp_start;
+	u32_t lp_count;
+#ifdef CONFIG_CODE_DENSITY
+	/*
+	 * Currently unsupported. This is where those registers are
+	 * automatically pushed on the stack by the CPU when taking a regular
+	 * IRQ.
+	 */
+	u32_t ei_base;
+	u32_t ldi_base;
+	u32_t jli_base;
+#endif
+	u32_t r0;
+	u32_t r1;
+	u32_t r2;
+	u32_t r3;
+	u32_t r4;
+	u32_t r5;
+	u32_t r6;
+	u32_t r7;
+	u32_t r8;
+	u32_t r9;
+	u32_t r10;
+	u32_t r11;
+	u32_t r12;
+	u32_t r13;
+	u32_t blink;
+	u32_t pc;
+	u32_t sec_stat;
+	u32_t status32;
+};
+#else
 struct _irq_stack_frame {
 	u32_t r0;
 	u32_t r1;
@@ -71,6 +106,7 @@ struct _irq_stack_frame {
 	u32_t pc;
 	u32_t status32;
 };
+#endif
 
 typedef struct _irq_stack_frame _isf_t;
 
@@ -93,6 +129,15 @@ struct _callee_saved_stack {
 	u32_t r25;
 	u32_t r26;
 	u32_t fp; /* r27 */
+
+#ifdef CONFIG_USERSPACE
+#ifdef CONFIG_ARC_HAS_SECURE
+	u32_t user_sp;
+	u32_t kernel_sp;
+#else
+	u32_t user_sp;
+#endif
+#endif
 	/* r28 is the stack pointer and saved separately */
 	/* r29 is ILINK and does not need to be saved */
 	u32_t r30;

arch/arc/include/kernel_arch_func.h

@@ -72,12 +72,16 @@ static ALWAYS_INLINE int _INTERRUPT_CAUSE(void)
 
 
 extern void _thread_entry_wrapper(void);
+extern void _user_thread_entry_wrapper(void);
 
 static inline void _IntLibInit(void)
 {
 	/* nothing needed, here because the kernel requires it */
 }
 
+extern void _arc_userspace_enter(k_thread_entry_t user_entry, void *p1,
+		 void *p2, void *p3, u32_t stack, u32_t size);
+
 #endif /* _ASMLANGUAGE */
 
 #ifdef __cplusplus

arch/arc/include/kernel_arch_thread.h

@@ -8,7 +8,7 @@
  * @file
  * @brief Per-arch thread definition
  *
- * This file contains defintions for
+ * This file contains definitions for
  *
  *  struct _thread_arch
  *  struct _callee_saved
@@ -21,8 +21,8 @@
 #define _kernel_arch_thread__h_
 
 /*
- * Reason a thread has relinquished control: fibers can only be in the NONE
- * or COOP state, tasks can be one in the four.
+ * Reason a thread has relinquished control: threads can only be in the NONE
+ * or COOP state, threads can be one in the four.
  */
 #define _CAUSE_NONE 0
 #define _CAUSE_COOP 1
@@ -63,6 +63,11 @@ struct _thread_arch {
 	 */
 	u32_t stack_base;
 #endif
+
+#ifdef CONFIG_USERSPACE
+	u32_t priv_stack_start;
+	u32_t priv_stack_size;
+#endif
 };
 
 typedef struct _thread_arch _thread_arch_t;

arch/arc/include/swap_macros.h

@@ -41,6 +41,18 @@ extern "C" {
 	st r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
 	st r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
 	st fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
+
+#ifdef CONFIG_USERSPACE
+#ifdef CONFIG_ARC_HAS_SECURE
+	lr r13, [_ARC_V2_SEC_U_SP]
+	st r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
+	lr r13, [_ARC_V2_SEC_K_SP]
+	st r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
+#else
+	lr r13, [_ARC_V2_USER_SP]
+	st r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
+#endif
+#endif
 	st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
 
 #ifdef CONFIG_FP_SHARING
@@ -93,6 +105,18 @@ extern "C" {
 	sr r13, [_ARC_V2_FPU_DPFP2H]
 #endif
 
+#endif
+
+#ifdef CONFIG_USERSPACE
+#ifdef CONFIG_ARC_HAS_SECURE
+	ld r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
+	sr r13, [_ARC_V2_SEC_U_SP]
+	ld r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
+	sr r13, [_ARC_V2_SEC_K_SP]
+#else
+	ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
+	sr r13, [_ARC_V2_USER_SP]
+#endif
 #endif
 
 	ld_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]

arch/arc/include/v2/irq.h

@@ -21,6 +21,7 @@ extern "C" {
 
 #define _ARC_V2_AUX_IRQ_CTRL_BLINK (1 << 9)
 #define _ARC_V2_AUX_IRQ_CTRL_LOOP_REGS (1 << 10)
+#define _ARC_V2_AUX_IRQ_CTRL_U (1 << 11)
 #define _ARC_V2_AUX_IRQ_CTRL_LP (1 << 13)
 #define _ARC_V2_AUX_IRQ_CTRL_14_REGS 7
 #define _ARC_V2_AUX_IRQ_CTRL_16_REGS 8

arch/arc/soc/em11d/CMakeLists.txt

@@ -0,0 +1,14 @@
+zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
+
+zephyr_cc_option(-mcpu=em4_fpuda -mno-sdata -mdiv-rem -mswap -mnorm)
+zephyr_cc_option(-mmpy-option=6 -mbarrel-shifter)
+zephyr_cc_option(--param l1-cache-size=16384)
+zephyr_cc_option(--param l1-cache-line-size=32)
+zephyr_cc_option_ifdef(CONFIG_CODE_DENSITY -mcode-density)
+zephyr_cc_option_ifdef(CONFIG_FLOAT -mfpu=fpuda_all)
+
+
+zephyr_sources(
+  soc.c
+  soc_config.c
+  )

arch/arc/soc/em11d/Kbuild

@@ -1,8 +0,0 @@
-ccflags-y +=-I$(srctree)/arch/arc/soc/
-ccflags-y +=-I$(srctree)/include
-ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/drivers
-
-asflags-y := ${ccflags-y}
-
-obj-y = soc.o soc_config.o

arch/arc/soc/em11d/Makefile

@@ -1,16 +0,0 @@
-#  -mcpu=em4_fpuda is added to KBUILD_CFLAGS to make cc-option check the options correctly
-KBUILD_CFLAGS += -mcpu=em4_fpuda
-
-soc-cflags += $(call cc-option, -mcpu=em4_fpuda -mno-sdata -mdiv-rem -mswap -mnorm) \
-		$(call cc-option,-mmpy-option=6 -mbarrel-shifter) \
-		$(call cc-option,--param l1-cache-size=16384) \
-		$(call cc-option,--param l1-cache-line-size=32)
-
-ifeq ($(CONFIG_CODE_DENSITY), y)
-soc-cflags += $(call cc-option, -mcode-density)
-endif
-
-ifeq ($(CONFIG_FLOAT), y)
-soc-cflags += $(call cc-option, -mfpu=fpuda_all)
-endif
-

arch/arc/soc/em11d/soc.h

@@ -31,7 +31,7 @@
 #ifndef _ASMLANGUAGE
 
 #include <misc/util.h>
-#include <drivers/rand32.h>
+#include <random/rand32.h>
 
 #define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
 #define ARCV2_TIMER0_INT_PRI			0

arch/arc/soc/em7d/CMakeLists.txt

@@ -0,0 +1,14 @@
+zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
+
+zephyr_cc_option(-mcpu=em4_dmips -mno-sdata)
+zephyr_cc_option(-mdiv-rem -mswap -mnorm)
+zephyr_cc_option(-mmpy-option=6 -mbarrel-shifter)
+zephyr_cc_option(--param l1-cache-size=16384)
+zephyr_cc_option(--param l1-cache-line-size=32)
+
+zephyr_cc_option_ifdef(CONFIG_CODE_DENSITY -mcode-density)
+
+zephyr_sources(
+  soc.c
+  soc_config.c
+  )

arch/arc/soc/em7d/Kbuild

@@ -1,10 +0,0 @@
-ccflags-y +=-I$(srctree)/arch/arc/soc/
-ccflags-y +=-I$(srctree)/include
-ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/drivers
-
-asflags-y := ${ccflags-y}
-
-obj-y += soc.o soc_config.o
-
-obj-$(CONFIG_ARC_MPU_ENABLE) += arc_mpu_regions.o

arch/arc/soc/em7d/Kconfig.defconfig

@@ -20,6 +20,10 @@ config NUM_IRQS
 	default 38 if BOARD_EM_STARTERKIT_R23
 	default 36 if BOARD_EM_STARTERKIT_R22
 
+config ARC_MPU_VER
+	default 3 if BOARD_EM_STARTERKIT_R23
+	default 2 if BOARD_EM_STARTERKIT_R22
+
 config RGF_NUM_BANKS
 	default 1
 
@@ -28,7 +32,11 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 30000000 if BOARD_EM_STARTERKIT_R22
 
 config HARVARD
-	def_bool n
+	def_bool y
+
+config ARC_FIRQ
+	def_bool n if BOARD_EM_STARTERKIT_R23
+	def_bool y if BOARD_EM_STARTERKIT_R22
 
 config FLASH_BASE_ADDRESS
 	default 0x00000000
@@ -58,4 +66,21 @@ config DCCM_SIZE
 config CACHE_FLUSHING
 	def_bool y
 
+if (ARC_MPU_VER = 2)
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+if ZTEST
+
+config ZTEST_STACKSIZE
+	default 2048
+
+endif # ZTEST
+
+endif # ARC_MPU_VER
+
 endif #SOC_EM7D

arch/arc/soc/em7d/Kconfig.soc

@@ -2,3 +2,4 @@
 config SOC_EM7D
 	bool "Synopsys ARC EM7D"
 	select CPU_HAS_MPU
+	select ARC_HAS_SECURE if BOARD_EM_STARTERKIT_R23

arch/arc/soc/em7d/Makefile

@@ -1,16 +0,0 @@
-#  -mcpu=em4_dmips is added to KBUILD_CFLAGS to make cc-option check the options correctly
-KBUILD_CFLAGS += -mcpu=em4_dmips
-
-soc-cflags += $(call cc-option,-mcpu=em4_dmips -mno-sdata) \
-		$(call cc-option,-mdiv-rem -mswap -mnorm) \
-		$(call cc-option,-mmpy-option=6 -mbarrel-shifter) \
-		$(call cc-option,--param l1-cache-size=16384) \
-		$(call cc-option,--param l1-cache-line-size=32)
-
-ifeq ($(CONFIG_CODE_DENSITY), y)
-soc-cflags += $(call cc-option,-mcode-density)
-endif
-
-ifeq ($(CONFIG_BOARD_EM_STARTERKIT_R23), y)
-$(error em7d from em starterkit 2.3 is not supported)
-endif

arch/arc/soc/em7d/arc_mpu_regions.c

@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2017 Synopsys
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
- #include <soc.h>
- #include <arch/arc/v2/mpu/arc_mpu.h>
-
-static struct arc_mpu_region mpu_regions[] = {
-#if CONFIG_ICCM_SIZE > 0
-	/* Region ICCM */
-	MPU_REGION_ENTRY("ICCM",
-			 CONFIG_ICCM_BASE_ADDRESS,
-			 REGION_FLASH_ATTR(REGION_256K)),
-#endif
-#if CONFIG_DCCM_SIZE > 0
-	/* Region DCCM */
-	MPU_REGION_ENTRY("DCCM",
-			 CONFIG_DCCM_BASE_ADDRESS,
-			 REGION_RAM_ATTR(REGION_128K)),
-#endif
-#if CONFIG_SRAM_SIZE > 0
-	/* Region DDR RAM */
-	MPU_REGION_ENTRY("DDR RAM",
-			CONFIG_SRAM_BASE_ADDRESS,
-			REGION_ALL_ATTR(REGION_128M)),
-#endif
-	/* Region Peripheral */
-	MPU_REGION_ENTRY("PERIPHERAL",
-			 0xF0000000,
-			 REGION_IO_ATTR(REGION_64K)),
-};
-
-struct arc_mpu_config mpu_config = {
-	.num_regions = ARRAY_SIZE(mpu_regions),
-	.mpu_regions = mpu_regions,
-};

arch/arc/soc/em7d/soc.h

@@ -40,7 +40,7 @@
 #ifndef _ASMLANGUAGE
 
 #include <misc/util.h>
-#include <drivers/rand32.h>
+#include <random/rand32.h>
 
 #define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
 #define ARCV2_TIMER0_INT_PRI			0

arch/arc/soc/em9d/CMakeLists.txt

@@ -0,0 +1,14 @@
+zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
+
+zephyr_cc_option(-mcpu=em4_fpus -mno-sdata -mdiv-rem -mswap -mnorm)
+zephyr_cc_option(-mdiv-rem -mswap -mnorm)
+zephyr_cc_option(-mmpy-option=6 -mbarrel-shifter)
+
+zephyr_cc_option_ifdef(CONFIG_CODE_DENSITY -mcode-density)
+zephyr_cc_option_ifdef(CONFIG_FLOAT -mfpu=fpuda_all)
+
+
+zephyr_sources(
+  soc.c
+  soc_config.c
+  )

arch/arc/soc/em9d/Kbuild

@@ -1,8 +0,0 @@
-ccflags-y +=-I$(srctree)/arch/arc/soc/
-ccflags-y +=-I$(srctree)/include
-ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/drivers
-
-asflags-y := ${ccflags-y}
-
-obj-y = soc.o soc_config.o

arch/arc/soc/em9d/Makefile

@@ -1,14 +0,0 @@
-#  -mcpu=em4_dmips is added to KBUILD_CFLAGS to make cc-option check the options correctly
-KBUILD_CFLAGS += -mcpu=em4_fpus
-
-soc-cflags += $(call cc-option,-mcpu=em4_fpus -mno-sdata) \
-		$(call cc-option,-mdiv-rem -mswap -mnorm) \
-		$(call cc-option,-mmpy-option=6 -mbarrel-shifter)
-
-ifeq ($(CONFIG_CODE_DENSITY), y)
-soc-cflags += $(call cc-option,-mcode-density)
-endif
-
-ifeq ($(CONFIG_FLOAT), y)
-soc-cflags += $(call cc-option,-mfpu=fpus_all)
-endif

arch/arc/soc/em9d/soc.h

@@ -31,7 +31,7 @@
 #ifndef _ASMLANGUAGE
 
 #include <misc/util.h>
-#include <drivers/rand32.h>
+#include <random/rand32.h>
 
 #define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
 #define ARCV2_TIMER0_INT_PRI			0

arch/arc/soc/quark_se_c1000_ss/CMakeLists.txt

@@ -0,0 +1,17 @@
+zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
+zephyr_include_directories(${PROJECT_SOURCE_DIR}/arch/x86/soc/intel_quark)
+
+zephyr_cc_option(-mcpu=quarkse_em -mno-sdata)
+
+zephyr_compile_definitions_ifdef(
+  CONFIG_SOC_QUARK_SE_C1000_SS
+  QM_SENSOR=1
+  SOC_SERIES=quark_se
+  )
+
+zephyr_sources(
+  soc.c
+  soc_config.c
+  power.c
+  soc_power.S
+  )

arch/arc/soc/quark_se_c1000_ss/Kbuild

@@ -1,8 +0,0 @@
-ccflags-y +=-I$(srctree)/include
-ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/drivers
-ccflags-$(CONFIG_ADC) +=-I$(srctree)/drivers/adc
-
-asflags-y := ${ccflags-y}
-
-obj-y = soc.o soc_config.o soc_power.o power.o

arch/arc/soc/quark_se_c1000_ss/Kconfig

@@ -11,8 +11,8 @@ config QUARK_SE_SS_IPM_IRQ_PRI
 	int "IPM interrupt priority"
 	default 1
 	help
-	Priority level for interrupts coming in from the inter-processor
-	mailboxes.
+	  Priority level for interrupts coming in from the inter-processor
+	  mailboxes.
 
 endif # IPM
 endif # SOC_QUARK_SE_C1000_SS

arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig

@@ -28,6 +28,7 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config HARVARD
 	def_bool n
 
+if !HAS_DTS
 config FLASH_BASE_ADDRESS
 	default 0x40000000
 
@@ -40,7 +41,7 @@ config SRAM_BASE_ADDRESS
 
 config SRAM_SIZE
 	default 16 if NSIM
-	default 24
+	default 27
 
 config ICCM_BASE_ADDRESS
 	default 0xFFFFFFFF
@@ -53,6 +54,7 @@ config DCCM_BASE_ADDRESS
 
 config DCCM_SIZE
 	default 8
+endif
 
 config QMSI
 	def_bool y
@@ -266,7 +268,7 @@ endif # UART_QMSI_1
 
 endif # UART_QMSI
 
-if UART_CONSOLE
+if UART_CONSOLE && !HAS_DTS
 
 config UART_CONSOLE_ON_DEV_NAME
 	default "UART_1"

arch/arc/soc/quark_se_c1000_ss/Makefile

@@ -1,10 +0,0 @@
-soc-cflags = $(call cc-option,-mcpu=quarkse_em) \
-             $(call cc-option,-mno-sdata)
-
-soc-aflags = $(soc-cflags)
-soc-cxxflags = $(soc-cflags)
-soc-cflags += -DQM_SENSOR=1
-soc-cflags += -I$(srctree)/arch/x86/soc/intel_quark
-
-## FIXME
-SOC_SERIES = quark_se

arch/arc/soc/quark_se_c1000_ss/dts.fixup

@@ -0,0 +1,20 @@
+/* SoC level DTS fixup file */
+
+#define CONFIG_UART_QMSI_0_BAUDRATE	INTEL_QMSI_UART_B0002000_CURRENT_SPEED
+#define CONFIG_UART_QMSI_0_NAME		INTEL_QMSI_UART_B0002000_LABEL
+#define CONFIG_UART_QMSI_0_IRQ		INTEL_QMSI_UART_B0002000_IRQ_0
+
+#define CONFIG_UART_QMSI_1_BAUDRATE	INTEL_QMSI_UART_B0002400_CURRENT_SPEED
+#define CONFIG_UART_QMSI_1_NAME		INTEL_QMSI_UART_B0002400_LABEL
+#define CONFIG_UART_QMSI_1_IRQ		INTEL_QMSI_UART_B0002400_IRQ_0
+
+#define SRAM_START			CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE			CONFIG_SRAM_SIZE
+
+#define FLASH_START			CONFIG_FLASH_BASE_ADDRESS
+#define FLASH_SIZE      		CONFIG_FLASH_SIZE
+
+#define CONFIG_DCCM_BASE_ADDRESS       ARC_DCCM_80000000_BASE_ADDRESS
+#define CONFIG_DCCM_SIZE               ARC_DCCM_80000000_SIZE
+
+/* End of SoC Level DTS fixup file */

arch/arc/soc/quark_se_c1000_ss/linker.ld

@@ -26,4 +26,5 @@
 #define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
 #define DCCM_SIZE		CONFIG_DCCM_SIZE
 
+#include <generated_dts_board.h>
 #include <arch/arc/v2/linker.ld>

arch/arc/soc/quark_se_c1000_ss/soc.h

@@ -105,7 +105,7 @@
 #ifndef _ASMLANGUAGE
 
 #include <misc/util.h>
-#include <drivers/rand32.h>
+#include <random/rand32.h>
 #include <quark_se/shared_mem.h>
 
 #define INT_ENABLE_ARC					~(0x00000001 << 8)

arch/arm/CMakeLists.txt

@@ -0,0 +1,23 @@
+zephyr_cc_option_ifdef(CONFIG_LTO -flto)
+
+set(ARCH_FOR_cortex-m0     armv6-m     )
+set(ARCH_FOR_cortex-m0plus armv6-m     )
+set(ARCH_FOR_cortex-m3     armv7-m     )
+set(ARCH_FOR_cortex-m4     armv7e-m    )
+set(ARCH_FOR_cortex-m23    armv8-m.base)
+set(ARCH_FOR_cortex-m33    armv8-m.main)
+
+set_property(GLOBAL PROPERTY E_KERNEL_ENTRY  -e${CONFIG_KERNEL_ENTRY})
+
+if(${ARCH_FOR_${GCC_M_CPU}})
+    set(ARCH_FLAG -march=${ARCH_FOR_${GCC_M_CPU}})
+endif()
+
+zephyr_compile_options(
+  -mabi=aapcs
+  ${TOOLCHAIN_C_FLAGS}
+  ${ARCH_FLAG}
+  )
+
+add_subdirectory(soc)
+add_subdirectory(core)

arch/arm/Kbuild

@@ -1,11 +0,0 @@
-subdir-ccflags-y +=-I$(srctree)/include/drivers
-subdir-ccflags-y +=-I$(srctree)/drivers
-subdir-asflags-y := ${subdir-ccflags-y}
-
-ifneq ($(SOC_FAMILY),)
-obj-y += soc/$(SOC_FAMILY)/
-else
-obj-y += soc/$(SOC_PATH)/
-endif
-
-obj-y += core/

arch/arm/Makefile

@@ -1,59 +0,0 @@
-KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
-
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
-
-cflags-$(CONFIG_LTO) += $(call cc-option,-flto,)
-
-cflags-cortex-m0 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m0) \
-			$(call cc-option,-mthumb -march=armv6-m)
-cflags-cortex-m0+ = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m0plus) \
-			$(call cc-option,-mthumb -march=armv6-m)
-cflags-cortex-m1 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m1) \
-			$(call cc-option,-mthumb -march=armv6-m)
-cflags-cortex-m3 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m3) \
-			$(call cc-option,-mthumb -march=armv7-m)
-cflags-cortex-m4 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m4) \
-			$(call cc-option,-mthumb -march=armv7e-m)
-cflags-cortex-m7 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m7)
-
-ifeq ($(CONFIG_FLOAT), y)
-ifeq ($(CONFIG_FP_SOFTABI), y)
-cflags-cortex-m4 += $(call cc-option,-mfloat-abi=softfp -mfpu=fpv4-sp-d16)
-cflags-cortex-m7 += $(call cc-option,-mfloat-abi=softfp -mfpu=fpv5-d16)
-endif
-ifeq ($(CONFIG_FP_HARDABI), y)
-cflags-cortex-m4 += $(call cc-option,-mfloat-abi=hard -mfpu=fpv4-sp-d16)
-cflags-cortex-m7 += $(call cc-option,-mfloat-abi=hard -mfpu=fpv5-d16)
-endif
-endif
-
-aflags-$(CONFIG_CPU_CORTEX_M0) += $(cflags-cortex-m0)
-cflags-$(CONFIG_CPU_CORTEX_M0) += $(cflags-cortex-m0)
-cxxflags-$(CONFIG_CPU_CORTEX_M0) += $(cflags-cortex-m0)
-
-aflags-$(CONFIG_CPU_CORTEX_M0PLUS) += $(cflags-cortex-m0+)
-cflags-$(CONFIG_CPU_CORTEX_M0PLUS) += $(cflags-cortex-m0+)
-cxxflags-$(CONFIG_CPU_CORTEX_M0PLUS) += $(cflags-cortex-m0+)
-
-aflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
-cflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
-cxxflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
-
-aflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
-cflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
-cxxflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
-
-aflags-$(CONFIG_CPU_CORTEX_M7) += $(cflags-cortex-m7)
-cflags-$(CONFIG_CPU_CORTEX_M7) += $(cflags-cortex-m7)
-cxxflags-$(CONFIG_CPU_CORTEX_M7) += $(cflags-cortex-m7)
-
-KBUILD_AFLAGS += $(aflags-y)
-KBUILD_CFLAGS += $(cflags-y)
-KBUILD_CXXFLAGS += $(cflags-y)
-
-soc-cxxflags ?= $(soc-cflags)
-soc-aflags ?= $(soc-cflags)
-KBUILD_CFLAGS += $(soc-cflags)
-KBUILD_CXXFLAGS += $(soc-cxxflags)
-KBUILD_AFLAGS += $(soc-aflags)
-

arch/arm/core/CMakeLists.txt

@@ -0,0 +1,22 @@
+zephyr_sources(
+  exc_exit.S
+  irq_init.c
+  swap.S
+  fault.c
+  irq_manage.c
+  thread.c
+  cpu_idle.S
+  fault_s.S
+  fatal.c
+  sys_fatal_error_handler.c
+  thread_abort.c
+)
+
+zephyr_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
+zephyr_sources_ifdef(CONFIG_CPLUSPLUS __aeabi_atexit.c)
+zephyr_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
+zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M0 irq_relay.S)
+zephyr_sources_ifdef(CONFIG_USERSPACE userspace.S)
+
+add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M cortex_m)
+add_subdirectory_ifdef(CONFIG_CPU_HAS_MPU  cortex_m/mpu)

arch/arm/core/Kconfig

@@ -11,7 +11,7 @@ config CPU_CORTEX
 	# Omit prompt to signify "hidden" option
 	default n
 	help
-	This option signifies the use of a CPU of the Cortex family.
+	  This option signifies the use of a CPU of the Cortex family.
 
 config CPU_CORTEX_M
 	bool
@@ -22,54 +22,29 @@ config CPU_CORTEX_M
 	select HAS_CMSIS
 	select HAS_FLASH_LOAD_OFFSET
 	select HAS_DTS
+	select ARCH_HAS_STACK_PROTECTION if ARM_CORE_MPU
+	select ARCH_HAS_USERSPACE if ARM_CORE_MPU
 	help
-	This option signifies the use of a CPU of the Cortex-M family.
+	  This option signifies the use of a CPU of the Cortex-M family.
 
 config CPU_HAS_SYSTICK
 	bool
 	# Omit prompt to signify "hidden" option
 	default n
 	help
-	This option is enabled when the CPU has systick timer implemented.
+	  This option is enabled when the CPU has systick timer implemented.
 
-config CPU_HAS_MPU
+config ARM_STACK_PROTECTION
 	bool
-	# Omit prompt to signify "hidden" option
-	default n
+	default y if HW_STACK_PROTECTION
+	select MPU_STACK_GUARD
 	help
-	  This option is enabled when the CPU has a Memory Protection Unit (MPU).
+	  This option enables MPU stack guard to cause a system fatal error
+	  if the bounds of the current process stack are overflowed.
 
-config CPU_HAS_FPU
-	# Hidden config selected by CPU family
-	bool
-	default n
-	help
-	This option is enabled when the CPU has a hardware floating point
-	unit.
-
-menu "Floating Point Options"
+menu "Architectue Floating Point Options"
 depends on CPU_HAS_FPU
 
-config	FLOAT
-	bool
-	prompt "Floating point registers"
-	default n
-	help
-	This option allows tasks and fibers to use the floating point registers.
-	By default, only a single task or fiber may use the registers.
-
-	Disabling this option means that any task or fiber that uses a
-	floating point register will get a fatal exception.
-
-config	FP_SHARING
-	bool
-	prompt "Floating point register sharing"
-	depends on FLOAT
-	default n
-	help
-	This option allows multiple tasks and fibers to use the floating point
-	registers.
-
 choice
 	prompt "Floating point ABI"
 	default FP_HARDABI
@@ -79,16 +54,16 @@ config FP_HARDABI
 	bool "Floating point Hard ABI"
 	depends on FLOAT
 	help
-	This option selects the Floating point ABI in which hardware floating
-	point instructions are generated and uses FPU-specific calling
-	conventions
+	  This option selects the Floating point ABI in which hardware floating
+	  point instructions are generated and uses FPU-specific calling
+	  conventions
 
 config FP_SOFTABI
 	bool "Floating point Soft ABI"
 	depends on FLOAT
 	help
-	This option selects the Floating point ABI in which hardware floating
-	point instructions are generated but soft-float calling conventions.
+	  This option selects the Floating point ABI in which hardware floating
+	  point instructions are generated but soft-float calling conventions.
 
 endchoice
 

arch/arm/core/Makefile

@@ -1,11 +0,0 @@
-ccflags-y += -I$(srctree)/kernel/include
-asflags-y := ${ccflags-y}
-
-obj-y = exc_exit.o irq_init.o swap.o fault.o irq_manage.o thread.o \
-	cpu_idle.o fault_s.o fatal.o sys_fatal_error_handler.o thread_abort.o
-
-obj-$(CONFIG_GEN_SW_ISR_TABLE) += isr_wrapper.o
-obj-$(CONFIG_CPLUSPLUS) += __aeabi_atexit.o
-obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
-obj-$(CONFIG_CPU_CORTEX_M) += cortex_m/
-obj-$(CONFIG_CPU_HAS_MPU) += cortex_m/mpu/

arch/arm/core/cortex_m/CMakeLists.txt

@@ -0,0 +1,9 @@
+zephyr_sources(
+  vector_table.S
+  reset.S
+  nmi_on_reset.S
+  prep_c.c
+  scb.c
+  nmi.c
+  exc_manage.c
+  )

arch/arm/core/cortex_m/Kconfig

@@ -11,100 +11,151 @@ config ISA_THUMB2
 	# Omit prompt to signify "hidden" option
 	default n
 	help
-	From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
+	  From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
 
-	Thumb-2 technology is the instruction set underlying the ARM Cortex
-	architecture which provides enhanced levels of performance, energy
-	efficiency, and code density for a wide range of embedded
-	applications.
+	  Thumb-2 technology is the instruction set underlying the ARM Cortex
+	  architecture which provides enhanced levels of performance, energy
+	  efficiency, and code density for a wide range of embedded
+	  applications.
 
-	Thumb-2 technology builds on the success of Thumb, the innovative
-	high code density instruction set for ARM microprocessor cores, to
-	increase the power of the ARM microprocessor core available to
-	developers of low cost, high performance systems.
+	  Thumb-2 technology builds on the success of Thumb, the innovative
+	  high code density instruction set for ARM microprocessor cores, to
+	  increase the power of the ARM microprocessor core available to
+	  developers of low cost, high performance systems.
 
-	The technology is backwards compatible with existing ARM and Thumb
-	solutions, while significantly extending the features available to
-	the Thumb instructions set. This allows more of the application to
-	benefit from the best in class code density of Thumb.
+	  The technology is backwards compatible with existing ARM and Thumb
+	  solutions, while significantly extending the features available to
+	  the Thumb instructions set. This allows more of the application to
+	  benefit from the best in class code density of Thumb.
 
-	For performance optimized code Thumb-2 technology uses 31 percent
-	less memory to reduce system cost, while providing up to 38 percent
-	higher performance than existing high density code, which can be used
-	to prolong battery-life or to enrich the product feature set. Thumb-2
-	technology is featured in the  processor, and in all ARMv7
-	architecture-based processors.
+	  For performance optimized code Thumb-2 technology uses 31 percent
+	  less memory to reduce system cost, while providing up to 38 percent
+	  higher performance than existing high density code, which can be used
+	  to prolong battery-life or to enrich the product feature set. Thumb-2
+	  technology is featured in the  processor, and in all ARMv7
+	  architecture-based processors.
 
 config CPU_CORTEX_M_HAS_BASEPRI
 	bool
 	# Omit prompt to signify "hidden" option
 	default n
 	help
-	This option signifies the CPU has the BASEPRI register.
+	  This option signifies the CPU has the BASEPRI register.
+
+config CPU_CORTEX_M_HAS_VTOR
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	help
+	  This option signifies the CPU has the VTOR register.
 
 config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
 	bool
 	# Omit prompt to signify "hidden" option
 	default n
 	help
-	This option signifies the CPU faults other than the hard fault, and
-	needs to reserve a priority for them.
+	  This option signifies the CPU faults other than the hard fault, and
+	  needs to reserve a priority for them.
 
-config ARMV6_M
+config CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	help
+	  This option signifies the Cortex-M0 has some mechanisms that can map
+	  the vector table to SRAM
+
+config ARMV6_M_ARMV8_M_BASELINE
 	bool
 	# Omit prompt to signify "hidden" option
 	default n
 	select ATOMIC_OPERATIONS_C
 	select ISA_THUMB2
 	help
-	This option signifies the use of an ARMv6-M processor implementation.
+	  This option signifies the use of an ARMv6-M processor
+	  implementation, or the use of an ARMv8-M processor
+	  supporting the Baseline implementation.
 
-config ARMV7_M
+	  Notes:
+	  - A Processing Element (PE) without the Main Extension
+	  is also referred to as a Baseline Implementation. A
+	  Baseline implementation has a subset of the instructions,
+	  registers, and features, of a Mainline implementation.
+	  - ARMv6-M compatibility is provided by all ARMv8-M
+	  implementations.
+
+config ARMV7_M_ARMV8_M_MAINLINE
 	bool
 	# Omit prompt to signify "hidden" option
 	default n
 	select ATOMIC_OPERATIONS_BUILTIN
 	select ISA_THUMB2
 	select CPU_CORTEX_M_HAS_BASEPRI
+	select CPU_CORTEX_M_HAS_VTOR
 	select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
 	help
-	This option signifies the use of an ARMv7-M processor implementation.
+	  This option signifies the use of an ARMv7-M processor
+	  implementation, or the use of an ARMv8-M processor
+	  implementation supporting the Main Extension.
+
+	  Notes:
+	  - A Processing Element (PE) with the Main Extension is also
+	  referred to as a Mainline Implementation.
+	  - ARMv7-M compatibility requires the Main Extension.
+
+	  From https://developer.arm.com/products/architecture/m-profile:
+	  The Main Extension provides backwards compatibility
+	  with ARMv7-M.
 
 config CPU_CORTEX_M0
 	bool
 	# Omit prompt to signify "hidden" option
-	select ARMV6_M
+	select ARMV6_M_ARMV8_M_BASELINE
 	help
-	This option signifies the use of a Cortex-M0 CPU
+	  This option signifies the use of a Cortex-M0 CPU
 
 config CPU_CORTEX_M0PLUS
 	bool
 	# Omit prompt to signify "hidden" option
-	select ARMV6_M
+	select ARMV6_M_ARMV8_M_BASELINE
 	help
-	This option signifies the use of a Cortex-M0+ CPU
+	  This option signifies the use of a Cortex-M0+ CPU
 
 config CPU_CORTEX_M3
 	bool
 	# Omit prompt to signify "hidden" option
-	select ARMV7_M
+	select ARMV7_M_ARMV8_M_MAINLINE
 	help
-	This option signifies the use of a Cortex-M3 CPU
+	  This option signifies the use of a Cortex-M3 CPU
 
 config CPU_CORTEX_M4
 	bool
 	# Omit prompt to signify "hidden" option
-	select ARMV7_M
+	select ARMV7_M_ARMV8_M_MAINLINE
 	help
-	This option signifies the use of a Cortex-M4 CPU
+	  This option signifies the use of a Cortex-M4 CPU
+
+config CPU_CORTEX_M23
+	bool
+	# Omit prompt to signify "hidden" option
+	select ARMV6_M_ARMV8_M_BASELINE
+	help
+	  This option signifies the use of a Cortex-M23 CPU
+
+config CPU_CORTEX_M33
+	bool
+	# Omit prompt to signify "hidden" option
+	select ARMV7_M_ARMV8_M_MAINLINE
+	help
+	  This option signifies the use of a Cortex-M33 CPU
 
 config CPU_CORTEX_M7
 	bool
 	# Omit prompt to signify "hidden" option
-	select ARMV7_M
+	select ARMV7_M_ARMV8_M_MAINLINE
 	default n
 	help
-	This option signifies the use of a Cortex-M7 CPU
+	  This option signifies the use of a Cortex-M7 CPU
 
 menu "ARM Cortex-M options"
 	depends on CPU_CORTEX_M
@@ -117,17 +168,17 @@ config DATA_ENDIANNESS_LITTLE
 	bool
 	default y
 	help
-	This is driven by the processor implementation, since it is fixed in
-	hardware. The board should set this value to 'n' if the data is
-	implemented as big endian.
+	  This is driven by the processor implementation, since it is fixed in
+	  hardware. The board should set this value to 'n' if the data is
+	  implemented as big endian.
 
 config STACK_ALIGN_DOUBLE_WORD
 	bool
 	prompt "Align stacks on double-words (8 octets)"
 	default y
 	help
-	This is needed to conform to AAPCS, the procedure call standard for
-	the ARM. It wastes stack space.
+	  This is needed to conform to AAPCS, the procedure call standard for
+	  the ARM. It wastes stack space.
 
 config RUNTIME_NMI
 	bool
@@ -135,10 +186,10 @@ config RUNTIME_NMI
 	select REBOOT
 	default n
 	help
-	The kernel provides a simple NMI handler that simply hangs in a tight
-	loop if triggered. This fills the requirement that there must be an
-	NMI handler installed when the CPU boots. If a custom handler is
-	needed, enable this option and attach it via _NmiHandlerSet().
+	  The kernel provides a simple NMI handler that simply hangs in a tight
+	  loop if triggered. This fills the requirement that there must be an
+	  NMI handler installed when the CPU boots. If a custom handler is
+	  needed, enable this option and attach it via _NmiHandlerSet().
 
 config FAULT_DUMP
 	int
@@ -146,30 +197,22 @@ config FAULT_DUMP
 	default 2
 	range 0 2
 	help
-	Different levels for display information when a fault occurs.
+	  Different levels for display information when a fault occurs.
 
-	2: The default. Display specific and verbose information. Consumes
+	  2: The default. Display specific and verbose information. Consumes
 		the most memory (long strings).
 
-	1: Display general and short information. Consumes less memory
+	  1: Display general and short information. Consumes less memory
 		(short strings).
 
-	0: Off.
+	  0: Off.
 
 config XIP
 	default y
 endmenu
 
-menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
-	depends on ARMV6_M || ARMV7_M
-
-config IRQ_OFFLOAD
-	bool "Enable IRQ offload"
-	default n
-	help
-	Enable irq_offload() API which allows functions to be synchronously
-	run in interrupt context. Adds some overhead to context switching.
-	Mainly useful for test cases.
+menu "ARM Cortex-M0/M0+/M3/M4/M7/M23/M33 options"
+    depends on ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE
 
 config GEN_ISR_TABLES
 	default y
@@ -180,19 +223,27 @@ config ZERO_LATENCY_IRQS
 	default n
 	depends on CPU_CORTEX_M_HAS_BASEPRI
 	help
-	Interrupt locking is done by setting exception masking to priority
-	one, thus allowing exception of priority zero to still come in. By
-	default, the kernel verifies, via __ASSERT() statements, that the
-	interrupt priority is not set to zero when either connecting them or
-	setting their priority. Enabling this option disables the check,
-	thus allowing setting the priority of interrupts to zero.
+	  Interrupt locking is done by setting exception masking to priority
+	  one, thus allowing exception of priority zero to still come in. By
+	  default, the kernel verifies, via __ASSERT() statements, that the
+	  interrupt priority is not set to zero when either connecting them or
+	  setting their priority. Enabling this option disables the check,
+	  thus allowing setting the priority of interrupts to zero.
 
-	Note that this is a somewhat dangerous option: ISRs of priority zero
-	interrupts cannot use any kernel functionality.
+	  Note that this is a somewhat dangerous option: ISRs of priority zero
+	  interrupts cannot use any kernel functionality.
 
-config ARCH_HAS_THREAD_ABORT
+config SW_VECTOR_RELAY
 	bool
-	# omit prompt to signify a "hidden" option
-	default y
-
+	prompt "Enable Software Vector Relay"
+	default n
+	default y if BOOTLOADER_MCUBOOT
+	depends on ARMV6_M_ARMV8_M_BASELINE && !(CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP || CPU_CORTEX_M_HAS_VTOR)
+	help
+	  Add Vector Table relay handler and relay vector table, to
+	  relay interrupts based on a vector table pointer. This is only
+	  required for Cortex-M0 (or an Armv8-M baseline core) with no hardware
+	  vector table relocation mechanisms or for Cortex-M0+
+	  (or an Armv8-M baseline core) with no VTOR and no other hardware
+	  relocation table mechanisms.
 endmenu

arch/arm/core/cortex_m/Makefile

@@ -1,11 +0,0 @@
-ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/arch/arm/soc/$(SOC_PATH)
-ccflags-y +=-I$(srctree)/kernel/include
-ccflags-y +=-I$(srctree)/include/
-
-asflags-y = $(ccflags-y)
-
-obj-y = vector_table.o reset.o \
-	nmi_on_reset.o prep_c.o scb.o nmi.o \
-	exc_manage.o
-

arch/arm/core/cortex_m/mpu/CMakeLists.txt

@@ -0,0 +1,3 @@
+zephyr_sources_ifdef(CONFIG_ARM_CORE_MPU arm_core_mpu.c)
+zephyr_sources_if_kconfig(               arm_mpu.c)
+zephyr_sources_if_kconfig(               nxp_mpu.c)

arch/arm/core/cortex_m/mpu/Kconfig

@@ -24,8 +24,10 @@ config MPU_STACK_GUARD
 config ARM_MPU
 	bool "ARM MPU Support"
 	depends on CPU_HAS_MPU
-	depends on SOC_FAMILY_ARM || SOC_FAMILY_STM32 || SOC_FAMILY_NRF5
+	depends on SOC_FAMILY_ARM || SOC_FAMILY_STM32 || SOC_FAMILY_NRF5 || SOC_FAMILY_IMX
 	select ARM_CORE_MPU
+	select ARCH_HAS_EXECUTABLE_PAGE_BIT
+	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
 	default n
 	help
 	  MCU has ARM MPU
@@ -35,6 +37,7 @@ config NXP_MPU
 	depends on CPU_HAS_MPU
 	depends on SOC_FAMILY_KINETIS
 	select ARM_CORE_MPU
+	select ARCH_HAS_EXECUTABLE_PAGE_BIT
 	default n
 	help
 	  MCU has NXP MPU

arch/arm/core/cortex_m/mpu/Makefile

@@ -1,3 +0,0 @@
-obj-$(CONFIG_ARM_CORE_MPU) += arm_core_mpu.o
-obj-$(CONFIG_ARM_MPU) += arm_mpu.o
-obj-$(CONFIG_NXP_MPU) += nxp_mpu.o

arch/arm/core/cortex_m/mpu/arm_core_mpu.c

@@ -10,6 +10,7 @@
 #include <soc.h>
 #include <arch/arm/cortex_m/cmsis.h>
 #include <arch/arm/cortex_m/mpu/arm_core_mpu.h>
+#include <logging/sys_log.h>
 
 #if defined(CONFIG_MPU_STACK_GUARD)
 /*
@@ -22,10 +23,97 @@
  */
 void configure_mpu_stack_guard(struct k_thread *thread)
 {
+	u32_t guard_size = MPU_GUARD_ALIGN_AND_SIZE;
+#if defined(CONFIG_USERSPACE)
+	u32_t guard_start = thread->arch.priv_stack_start ?
+			    (u32_t)thread->arch.priv_stack_start :
+			    (u32_t)thread->stack_obj;
+#else
+	u32_t guard_start = thread->stack_info.start;
+#endif
+
 	arm_core_mpu_disable();
-	arm_core_mpu_configure(THREAD_STACK_GUARD_REGION,
-			thread->stack_info.start - MPU_GUARD_ALIGN_AND_SIZE,
-			thread->stack_info.size);
+	arm_core_mpu_configure(THREAD_STACK_GUARD_REGION, guard_start,
+			       guard_size);
 	arm_core_mpu_enable();
 }
 #endif
+
+#if defined(CONFIG_USERSPACE)
+/*
+ * @brief Configure MPU user context
+ *
+ * This function configures the thread's user context.
+ * The functionality is meant to be used during context switch.
+ *
+ * @param thread thread info data structure.
+ */
+void configure_mpu_user_context(struct k_thread *thread)
+{
+	SYS_LOG_DBG("configure user thread %p's context", thread);
+	arm_core_mpu_disable();
+	arm_core_mpu_configure_user_context(thread);
+	arm_core_mpu_enable();
+}
+
+/*
+ * @brief Configure MPU memory domain
+ *
+ * This function configures per thread memory domain reprogramming the MPU.
+ * The functionality is meant to be used during context switch.
+ *
+ * @param thread thread info data structure.
+ */
+void configure_mpu_mem_domain(struct k_thread *thread)
+{
+	SYS_LOG_DBG("configure thread %p's domain", thread);
+	arm_core_mpu_disable();
+	arm_core_mpu_configure_mem_domain(thread->mem_domain_info.mem_domain);
+	arm_core_mpu_enable();
+}
+
+void _arch_mem_domain_configure(struct k_thread *thread)
+{
+	configure_mpu_mem_domain(thread);
+}
+
+int _arch_mem_domain_max_partitions_get(void)
+{
+	return arm_core_mpu_get_max_domain_partition_regions();
+}
+
+/*
+ * Reset MPU region for a single memory partition
+ */
+void _arch_mem_domain_partition_remove(struct k_mem_domain *domain,
+				       u32_t  partition_id)
+{
+	ARG_UNUSED(domain);
+
+	arm_core_mpu_disable();
+	arm_core_mpu_mem_partition_remove(partition_id);
+	arm_core_mpu_enable();
+
+}
+
+/*
+ * Destroy MPU regions for the mem domain
+ */
+void _arch_mem_domain_destroy(struct k_mem_domain *domain)
+{
+	ARG_UNUSED(domain);
+
+	arm_core_mpu_disable();
+	arm_core_mpu_configure_mem_domain(NULL);
+	arm_core_mpu_enable();
+}
+
+/*
+ * Validate the given buffer is user accessible or not
+ */
+int _arch_buffer_validate(void *addr, size_t size, int write)
+{
+	return arm_core_mpu_buffer_validate(addr, size, write);
+}
+
+#endif

arch/arm/core/cortex_m/mpu/arm_mpu.c

@@ -12,6 +12,7 @@
 #include <arch/arm/cortex_m/mpu/arm_mpu.h>
 #include <arch/arm/cortex_m/mpu/arm_core_mpu.h>
 #include <logging/sys_log.h>
+#include <linker/linker-defs.h>
 
 #define ARM_MPU_DEV ((volatile struct arm_mpu *) ARM_MPU_BASE)
 
@@ -31,18 +32,52 @@ static inline u32_t _get_region_attr(u32_t xn, u32_t ap, u32_t tex,
 		| (c << 17) | (b << 16) | (srd << 5) | (size));
 }
 
+/**
+ * This internal function converts the region size to
+ * the SIZE field value of MPU_RASR.
+ */
+static inline u32_t _size_to_mpu_rasr_size(u32_t size)
+{
+	/* The minimal supported region size is 32 bytes */
+	if (size <= 32) {
+		return REGION_32B;
+	}
+
+	/*
+	 * A size value greater than 2^31 could not be handled by
+	 * round_up_to_next_power_of_two() properly. We handle
+	 * it separately here.
+	 */
+	if (size > (1 << 31)) {
+		return REGION_4G;
+	}
+
+	size = 1 << (32 - __builtin_clz(size - 1));
+	return (32 - __builtin_clz(size) - 2) << 1;
+}
+
+
 /**
  * This internal function is utilized by the MPU driver to parse the intent
  * type (i.e. THREAD_STACK_REGION) and return the correct parameter set.
  */
 static inline u32_t _get_region_attr_by_type(u32_t type, u32_t size)
 {
+	int region_size = _size_to_mpu_rasr_size(size);
+
 	switch (type) {
+	case THREAD_STACK_USER_REGION:
+		return _get_region_attr(1, P_RW_U_RW, 0, 1, 0,
+					1, 0, region_size);
 	case THREAD_STACK_REGION:
-		return 0;
+		return _get_region_attr(1, P_RW_U_RW, 0, 1, 0,
+					1, 0, region_size);
 	case THREAD_STACK_GUARD_REGION:
-		return _get_region_attr(1, P_RO_U_RO, 0, 1, 0,
-					1, 0, REGION_32B);
+		return _get_region_attr(1, P_RO_U_NA, 0, 1, 0,
+					1, 0, region_size);
+	case THREAD_APP_DATA_REGION:
+		return _get_region_attr(1, P_RW_U_RW, 0, 1, 0,
+					1, 0, region_size);
 	default:
 		/* Size 0 region */
 		return 0;
@@ -67,6 +102,99 @@ static void _region_init(u32_t index, u32_t region_addr,
 	ARM_MPU_DEV->rbar = (region_addr & REGION_BASE_ADDR_MASK)
 				| REGION_VALID | index;
 	ARM_MPU_DEV->rasr = region_attr | REGION_ENABLE;
+	SYS_LOG_DBG("[%d] 0x%08x 0x%08x", index, region_addr, region_attr);
+}
+
+/**
+ * This internal function is utilized by the MPU driver to parse the intent
+ * type (i.e. THREAD_STACK_REGION) and return the correct region index.
+ */
+static inline u32_t _get_region_index_by_type(u32_t type)
+{
+	/*
+	 * The new MPU regions are allocated per type after the statically
+	 * configured regions. The type is one-indexed rather than
+	 * zero-indexed, therefore we need to subtract by one to get the region
+	 * index.
+	 */
+	switch (type) {
+	case THREAD_STACK_USER_REGION:
+		return mpu_config.num_regions + THREAD_STACK_REGION - 1;
+	case THREAD_STACK_REGION:
+	case THREAD_STACK_GUARD_REGION:
+	case THREAD_APP_DATA_REGION:
+		return mpu_config.num_regions + type - 1;
+	case THREAD_DOMAIN_PARTITION_REGION:
+#if defined(CONFIG_USERSPACE)
+		return mpu_config.num_regions + type - 1;
+#elif defined(CONFIG_MPU_STACK_GUARD)
+		return mpu_config.num_regions + type - 2;
+#else
+		/*
+		 * Start domain partition region from stack guard region
+		 * since stack guard is not enabled.
+		 */
+		return mpu_config.num_regions + type - 3;
+#endif
+	default:
+		__ASSERT(0, "Unsupported type");
+		return 0;
+	}
+}
+
+/**
+ * This internal function check if region is enabled or not
+ */
+static inline int _is_enabled_region(u32_t r_index)
+{
+	ARM_MPU_DEV->rnr = r_index;
+
+	return ARM_MPU_DEV->rasr & REGION_ENABLE_MASK;
+}
+
+/**
+ * This internal function check if the given buffer in in the region
+ */
+static inline int _is_in_region(u32_t r_index, u32_t start, u32_t size)
+{
+	u32_t r_addr_start;
+	u32_t r_size_lshift;
+	u32_t r_addr_end;
+
+	ARM_MPU_DEV->rnr = r_index;
+	r_addr_start = ARM_MPU_DEV->rbar & REGION_BASE_ADDR_MASK;
+	r_size_lshift = ((ARM_MPU_DEV->rasr & REGION_SIZE_MASK) >>
+			REGION_SIZE_OFFSET) + 1;
+	r_addr_end = r_addr_start + (1 << r_size_lshift) - 1;
+
+	if (start >= r_addr_start && (start + size - 1) <= r_addr_end) {
+		return 1;
+	}
+
+	return 0;
+}
+
+/**
+ * This internal function check if the region is user accessible or not
+ */
+static inline int _is_user_accessible_region(u32_t r_index, int write)
+{
+	u32_t r_ap;
+
+	ARM_MPU_DEV->rnr = r_index;
+	r_ap = ARM_MPU_DEV->rasr & ACCESS_PERMS_MASK;
+
+	/* always return true if this is the thread stack region */
+	if (_get_region_index_by_type(THREAD_STACK_REGION) == r_index) {
+		return 1;
+	}
+
+	if (write) {
+		return r_ap == P_RW_U_RW;
+	}
+
+	/* For all user accessible permissions, their AP[1] bit is l */
+	return r_ap & (0x2 << ACCESS_PERMS_OFFSET);
 }
 
 /* ARM Core MPU Driver API Implementation for ARM MPU */
@@ -107,13 +235,7 @@ void arm_core_mpu_disable(void)
 void arm_core_mpu_configure(u8_t type, u32_t base, u32_t size)
 {
 	SYS_LOG_DBG("Region info: 0x%x 0x%x", base, size);
-	/*
-	 * The new MPU regions are allocated per type after the statically
-	 * configured regions. The type is one-indexed rather than
-	 * zero-indexed, therefore we need to subtract by one to get the region
-	 * index.
-	 */
-	u32_t region_index = mpu_config.num_regions + type - 1;
+	u32_t region_index = _get_region_index_by_type(type);
 	u32_t region_attr = _get_region_attr_by_type(type, size);
 
 	/* ARM MPU supports up to 16 Regions */
@@ -124,6 +246,167 @@ void arm_core_mpu_configure(u8_t type, u32_t base, u32_t size)
 	_region_init(region_index, base, region_attr);
 }
 
+#if defined(CONFIG_USERSPACE)
+void arm_core_mpu_configure_user_context(struct k_thread *thread)
+{
+	u32_t base = (u32_t)thread->stack_obj;
+	u32_t size = thread->stack_info.size;
+	u32_t index = _get_region_index_by_type(THREAD_STACK_USER_REGION);
+	u32_t region_attr = _get_region_attr_by_type(THREAD_STACK_USER_REGION,
+						     size);
+
+	if (!thread->arch.priv_stack_start) {
+		ARM_MPU_DEV->rnr = index;
+		ARM_MPU_DEV->rbar = 0;
+		ARM_MPU_DEV->rasr = 0;
+		return;
+	}
+	/* configure stack */
+	_region_init(index, base, region_attr);
+
+#if defined(CONFIG_APPLICATION_MEMORY)
+	/* configure app data portion */
+	index = _get_region_index_by_type(THREAD_APP_DATA_REGION);
+	size = (u32_t)&__app_ram_end - (u32_t)&__app_ram_start;
+	region_attr = _get_region_attr_by_type(THREAD_APP_DATA_REGION, size);
+	if (size > 0)
+		_region_init(index, (u32_t)&__app_ram_start, region_attr);
+#endif
+}
+
+/**
+ * @brief configure MPU regions for the memory partitions of the memory domain
+ *
+ * @param   mem_domain    memory domain that thread belongs to
+ */
+void arm_core_mpu_configure_mem_domain(struct k_mem_domain *mem_domain)
+{
+	u32_t region_index =
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
+	u32_t region_attr;
+	u32_t num_partitions;
+	struct k_mem_partition *pparts;
+
+	if (mem_domain) {
+		SYS_LOG_DBG("configure domain: %p", mem_domain);
+		num_partitions = mem_domain->num_partitions;
+		pparts = mem_domain->partitions;
+	} else {
+		SYS_LOG_DBG("disable domain partition regions");
+		num_partitions = 0;
+		pparts = NULL;
+	}
+
+	for (; region_index < _get_num_regions(); region_index++) {
+		if (num_partitions && pparts->size) {
+			SYS_LOG_DBG("set region 0x%x 0x%x 0x%x",
+				    region_index, pparts->start, pparts->size);
+			region_attr = pparts->attr |
+				      _size_to_mpu_rasr_size(pparts->size);
+			_region_init(region_index, pparts->start, region_attr);
+			num_partitions--;
+		} else {
+			SYS_LOG_DBG("disable region 0x%x", region_index);
+			/* Disable region */
+			ARM_MPU_DEV->rnr = region_index;
+			ARM_MPU_DEV->rbar = 0;
+			ARM_MPU_DEV->rasr = 0;
+		}
+		pparts++;
+	}
+}
+
+/**
+ * @brief configure MPU region for a single memory partition
+ *
+ * @param   part_index  memory partition index
+ * @param   part        memory partition info
+ */
+void arm_core_mpu_configure_mem_partition(u32_t part_index,
+					  struct k_mem_partition *part)
+{
+	u32_t region_index =
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
+	u32_t region_attr;
+
+	SYS_LOG_DBG("configure partition index: %u", part_index);
+
+	if (part) {
+		SYS_LOG_DBG("set region 0x%x 0x%x 0x%x",
+			    region_index + part_index, part->start, part->size);
+		region_attr = part->attr | _size_to_mpu_rasr_size(part->size);
+		_region_init(region_index + part_index, part->start,
+			     region_attr);
+	} else {
+		SYS_LOG_DBG("disable region 0x%x", region_index + part_index);
+		/* Disable region */
+		ARM_MPU_DEV->rnr = region_index + part_index;
+		ARM_MPU_DEV->rbar = 0;
+		ARM_MPU_DEV->rasr = 0;
+	}
+}
+
+/**
+ * @brief Reset MPU region for a single memory partition
+ *
+ * @param   part_index  memory partition index
+ */
+void arm_core_mpu_mem_partition_remove(u32_t part_index)
+{
+	u32_t region_index =
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
+
+	SYS_LOG_DBG("disable region 0x%x", region_index + part_index);
+	/* Disable region */
+	ARM_MPU_DEV->rnr = region_index + part_index;
+	ARM_MPU_DEV->rbar = 0;
+	ARM_MPU_DEV->rasr = 0;
+}
+
+/**
+ * @brief get the maximum number of free regions for memory domain partitions
+ */
+int arm_core_mpu_get_max_domain_partition_regions(void)
+{
+	/*
+	 * Subtract the start of domain partition regions from total regions
+	 * will get the maximum number of free regions for memory domain
+	 * partitions.
+	 */
+	return _get_num_regions() -
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
+}
+
+/**
+ * @brief validate the given buffer is user accessible or not
+ */
+int arm_core_mpu_buffer_validate(void *addr, size_t size, int write)
+{
+	u32_t r_index;
+
+	/* Iterate all mpu regions in reversed order */
+	for (r_index = _get_num_regions() + 1; r_index-- > 0;) {
+		if (!_is_enabled_region(r_index) ||
+		    !_is_in_region(r_index, (u32_t)addr, size)) {
+			continue;
+		}
+
+		/* For ARM MPU, higher region number takes priority.
+		 * Since we iterate all mpu regions in reversed order, so
+		 * we can stop the iteration immediately once we find the
+		 * matched region that grants permission or denies access.
+		 */
+		if (_is_user_accessible_region(r_index, write)) {
+			return 0;
+		} else {
+			return -EPERM;
+		}
+	}
+
+	return -EPERM;
+}
+#endif /* CONFIG_USERSPACE */
+
 /* ARM MPU Driver Initial Setup */
 
 /*

arch/arm/core/cortex_m/mpu/nxp_mpu.c

@@ -12,8 +12,7 @@
 #include <arch/arm/cortex_m/mpu/nxp_mpu.h>
 #include <logging/sys_log.h>
 #include <misc/__assert.h>
-
-#define STACK_GUARD_REGION_SIZE 32
+#include <linker/linker-defs.h>
 
 /* NXP MPU Enabled state */
 static u8_t nxp_mpu_enabled;
@@ -25,11 +24,15 @@ static u8_t nxp_mpu_enabled;
 static inline u32_t _get_region_attr_by_type(u32_t type)
 {
 	switch (type) {
+	case THREAD_STACK_USER_REGION:
+		return REGION_USER_MODE_ATTR;
 	case THREAD_STACK_REGION:
-		return 0;
+		return REGION_RAM_ATTR;
 	case THREAD_STACK_GUARD_REGION:
 		/* The stack guard region has to be not accessible */
 		return REGION_RO_ATTR;
+	case THREAD_APP_DATA_REGION:
+		return REGION_USER_MODE_ATTR;
 	default:
 		/* Size 0 region */
 		return 0;
@@ -54,11 +57,11 @@ static void _region_init(u32_t index, u32_t region_base,
 		 */
 		__ASSERT(region_base == SYSMPU->WORD[index][0],
 			 "Region %d base address got 0x%08x expected 0x%08x",
-			 index, region_base, SYSMPU->WORD[index][0]);
+			 index, region_base, (u32_t)SYSMPU->WORD[index][0]);
 
 		__ASSERT(region_end == SYSMPU->WORD[index][1],
 			 "Region %d end address got 0x%08x expected 0x%08x",
-			 index, region_end, SYSMPU->WORD[index][1]);
+			 index, region_end, (u32_t)SYSMPU->WORD[index][1]);
 
 		/* Changes to the RGD0_WORD2 alterable fields should be done
 		 * via a write to RGDAAC0.
@@ -79,6 +82,126 @@ static void _region_init(u32_t index, u32_t region_base,
 		    SYSMPU->WORD[index][3]);
 }
 
+/**
+ * This internal function is utilized by the MPU driver to parse the intent
+ * type (i.e. THREAD_STACK_REGION) and return the correct region index.
+ */
+static inline u32_t _get_region_index_by_type(u32_t type)
+{
+	/*
+	 * The new MPU regions are allocated per type after the statically
+	 * configured regions. The type is one-indexed rather than
+	 * zero-indexed, therefore we need to subtract by one to get the region
+	 * index.
+	 */
+	switch (type) {
+	case THREAD_STACK_USER_REGION:
+		return mpu_config.num_regions + THREAD_STACK_REGION - 1;
+	case THREAD_STACK_REGION:
+	case THREAD_STACK_GUARD_REGION:
+	case THREAD_APP_DATA_REGION:
+		return mpu_config.num_regions + type - 1;
+	case THREAD_DOMAIN_PARTITION_REGION:
+#if defined(CONFIG_USERSPACE)
+		return mpu_config.num_regions + type - 1;
+#elif defined(CONFIG_MPU_STACK_GUARD)
+		return mpu_config.num_regions + type - 2;
+#else
+		/*
+		 * Start domain partition region from stack guard region
+		 * since stack guard is not enabled.
+		 */
+		return mpu_config.num_regions + type - 3;
+#endif
+	default:
+		__ASSERT(0, "Unsupported type");
+		return 0;
+	}
+}
+
+/**
+ * This internal function check if region is enabled or not
+ */
+static inline int _is_enabled_region(u32_t r_index)
+{
+	return SYSMPU->WORD[r_index][3] & SYSMPU_WORD_VLD_MASK;
+}
+
+/**
+ * This internal function check if the given buffer in in the region
+ */
+static inline int _is_in_region(u32_t r_index, u32_t start, u32_t size)
+{
+	u32_t r_addr_start;
+	u32_t r_addr_end;
+
+	r_addr_start = SYSMPU->WORD[r_index][0];
+	r_addr_end = SYSMPU->WORD[r_index][1];
+
+	if (start >= r_addr_start && (start + size - 1) <= r_addr_end) {
+		return 1;
+	}
+
+	return 0;
+}
+
+/**
+ * This internal function check if the region is user accessible or not
+ */
+static inline int _is_user_accessible_region(u32_t r_index, int write)
+{
+	u32_t r_ap = SYSMPU->WORD[r_index][2];
+
+	/* always return true if this is the thread stack region */
+	if (_get_region_index_by_type(THREAD_STACK_REGION) == r_index) {
+		return 1;
+	}
+
+	if (write) {
+		return (r_ap & MPU_REGION_WRITE) == MPU_REGION_WRITE;
+	}
+
+	return (r_ap & MPU_REGION_READ) == MPU_REGION_READ;
+}
+
+static void nxp_mpu_setup_sram_region(u32_t base, u32_t size)
+{
+	u32_t last_region = _get_num_regions() - 1;
+
+	/*
+	 * The NXP MPU manages the permissions of the overlapping regions
+	 * doing the logic OR in between them, hence they can't be used
+	 * for stack/stack guard protection. For this reason the last region of
+	 * the MPU will be reserved.
+	 *
+	 * A consequence of this is that the SRAM is split in different
+	 * regions. In example if THREAD_STACK_GUARD_REGION is selected:
+	 * - SRAM before THREAD_STACK_GUARD_REGION: RW
+	 * - SRAM THREAD_STACK_GUARD_REGION: RO
+	 * - SRAM after THREAD_STACK_GUARD_REGION: RW
+	 */
+
+	/* Configure SRAM_0 region
+	 *
+	 * The mpu_config.sram_region contains the index of the region in
+	 * the mpu_config.mpu_regions array but the region 0 on the NXP MPU
+	 * is the background region, so on this MPU the regions are mapped
+	 * starting from 1, hence the mpu_config.sram_region on the data
+	 * structure is mapped on the mpu_config.sram_region + 1 region of
+	 * the MPU.
+	 */
+	_region_init(mpu_config.sram_region,
+		     mpu_config.mpu_regions[mpu_config.sram_region].base,
+		     ENDADDR_ROUND(base),
+		     mpu_config.mpu_regions[mpu_config.sram_region].attr);
+
+	/* Configure SRAM_1 region */
+	_region_init(last_region, base + size,
+	   ENDADDR_ROUND(mpu_config.mpu_regions[mpu_config.sram_region].end),
+			mpu_config.mpu_regions[mpu_config.sram_region].attr);
+
+}
+
 /* ARM Core MPU Driver API Implementation for NXP MPU */
 
 /**
@@ -119,68 +242,192 @@ void arm_core_mpu_disable(void)
 void arm_core_mpu_configure(u8_t type, u32_t base, u32_t size)
 {
 	SYS_LOG_DBG("Region info: 0x%x 0x%x", base, size);
-	/*
-	 * The new MPU regions are allocated per type after the statically
-	 * configured regions. The type is one-indexed rather than
-	 * zero-indexed, therefore we need to subtract by one to get the region
-	 * index.
-	 */
-	u32_t region_index = mpu_config.num_regions + type - 1;
+	u32_t region_index = _get_region_index_by_type(type);
 	u32_t region_attr = _get_region_attr_by_type(type);
-	u32_t last_region = _get_num_regions() - 1;
 
-	/*
-	 * The NXP MPU manages the permissions of the overlapping regions
-	 * doing the logic OR in between them, hence they can't be used
-	 * for stack/stack guard protection. For this reason the last region of
-	 * the MPU will be reserved.
-	 *
-	 * A consequence of this is that the SRAM is splitted in different
-	 * regions. In example if THREAD_STACK_GUARD_REGION is selected:
-	 * - SRAM before THREAD_STACK_GUARD_REGION: RW
-	 * - SRAM THREAD_STACK_GUARD_REGION: RO
-	 * - SRAM after THREAD_STACK_GUARD_REGION: RW
-	 */
 	/* NXP MPU supports up to 16 Regions */
 	if (region_index > _get_num_regions() - 2) {
 		return;
 	}
 
-	/* Configure SRAM_0 region */
-	/*
-	 * The mpu_config.sram_region contains the index of the region in
-	 * the mpu_config.mpu_regions array but the region 0 on the NXP MPU
-	 * is the background region, so on this MPU the regions are mapped
-	 * starting from 1, hence the mpu_config.sram_region on the data
-	 * structure is mapped on the mpu_config.sram_region + 1 region of
-	 * the MPU.
-	 */
-	_region_init(mpu_config.sram_region,
-		     mpu_config.mpu_regions[mpu_config.sram_region].base,
-		     ENDADDR_ROUND(base),
-		     mpu_config.mpu_regions[mpu_config.sram_region].attr);
+	_region_init(region_index, base,
+		     ENDADDR_ROUND(base + size),
+		     region_attr);
+	if (type == THREAD_STACK_GUARD_REGION) {
+		nxp_mpu_setup_sram_region(base, size);
+	}
+}
 
-	switch (type) {
-	case THREAD_STACK_REGION:
-		break;
-	case THREAD_STACK_GUARD_REGION:
-		_region_init(region_index, base,
-			     ENDADDR_ROUND(base + STACK_GUARD_REGION_SIZE),
+#if defined(CONFIG_USERSPACE)
+void arm_core_mpu_configure_user_context(struct k_thread *thread)
+{
+	u32_t base = (u32_t)thread->stack_info.start;
+	u32_t size = thread->stack_info.size;
+	u32_t index = _get_region_index_by_type(THREAD_STACK_USER_REGION);
+	u32_t region_attr = _get_region_attr_by_type(THREAD_STACK_USER_REGION);
+
+	/* configure stack */
+	_region_init(index, base, ENDADDR_ROUND(base + size), region_attr);
+
+#if defined(CONFIG_APPLICATION_MEMORY)
+	/* configure app data portion */
+	index = _get_region_index_by_type(THREAD_APP_DATA_REGION);
+	region_attr = _get_region_attr_by_type(THREAD_APP_DATA_REGION);
+	base = (u32_t)&__app_ram_start;
+	size = (u32_t)&__app_ram_end - (u32_t)&__app_ram_start;
+
+	/* set up app data region if exists, otherwise disable */
+	if (size > 0) {
+		_region_init(index, base, ENDADDR_ROUND(base + size),
 			     region_attr);
-		break;
-	default:
-		break;
+	} else {
+		SYSMPU->WORD[index][3] = 0;
+	}
+#endif
+}
+
+/**
+ * @brief configure MPU regions for the memory partitions of the memory domain
+ *
+ * @param   mem_domain    memory domain that thread belongs to
+ */
+void arm_core_mpu_configure_mem_domain(struct k_mem_domain *mem_domain)
+{
+	u32_t region_index =
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
+	u32_t region_attr;
+	u32_t num_partitions;
+	struct k_mem_partition *pparts;
+
+	if (mem_domain) {
+		SYS_LOG_DBG("configure domain: %p", mem_domain);
+		num_partitions = mem_domain->num_partitions;
+		pparts = mem_domain->partitions;
+	} else {
+		SYS_LOG_DBG("disable domain partition regions");
+		num_partitions = 0;
+		pparts = NULL;
 	}
 
-	/* Configure SRAM_1 region */
-	_region_init(last_region,
-		     base + STACK_GUARD_REGION_SIZE,
-		     ENDADDR_ROUND(
-			    mpu_config.mpu_regions[mpu_config.sram_region].end),
-		     mpu_config.mpu_regions[mpu_config.sram_region].attr);
-
+	/*
+	 * Don't touch the last region, it is reserved for SRAM_1 region.
+	 * See comments in arm_core_mpu_configure().
+	 */
+	for (; region_index < _get_num_regions() - 1; region_index++) {
+		if (num_partitions && pparts->size) {
+			SYS_LOG_DBG("set region 0x%x 0x%x 0x%x",
+				    region_index, pparts->start, pparts->size);
+			region_attr = pparts->attr;
+			_region_init(region_index, pparts->start,
+				     ENDADDR_ROUND(pparts->start+pparts->size),
+				     region_attr);
+			num_partitions--;
+		} else {
+			SYS_LOG_DBG("disable region 0x%x", region_index);
+			/* Disable region */
+			SYSMPU->WORD[region_index][0] = 0;
+			SYSMPU->WORD[region_index][1] = 0;
+			SYSMPU->WORD[region_index][2] = 0;
+			SYSMPU->WORD[region_index][3] = 0;
+		}
+		pparts++;
+	}
 }
 
+/**
+ * @brief configure MPU region for a single memory partition
+ *
+ * @param   part_index  memory partition index
+ * @param   part        memory partition info
+ */
+void arm_core_mpu_configure_mem_partition(u32_t part_index,
+					  struct k_mem_partition *part)
+{
+	u32_t region_index =
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
+	u32_t region_attr;
+
+	SYS_LOG_DBG("configure partition index: %u", part_index);
+
+	if (part) {
+		SYS_LOG_DBG("set region 0x%x 0x%x 0x%x",
+			    region_index + part_index, part->start, part->size);
+		region_attr = part->attr;
+		_region_init(region_index + part_index, part->start,
+			     ENDADDR_ROUND(part->start + part->size),
+			     region_attr);
+	} else {
+		SYS_LOG_DBG("disable region 0x%x", region_index);
+		/* Disable region */
+		SYSMPU->WORD[region_index + part_index][0] = 0;
+		SYSMPU->WORD[region_index + part_index][1] = 0;
+		SYSMPU->WORD[region_index + part_index][2] = 0;
+		SYSMPU->WORD[region_index + part_index][3] = 0;
+	}
+}
+
+/**
+ * @brief Reset MPU region for a single memory partition
+ *
+ * @param   part_index  memory partition index
+ */
+void arm_core_mpu_mem_partition_remove(u32_t part_index)
+{
+	u32_t region_index =
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
+
+	SYS_LOG_DBG("disable region 0x%x", region_index);
+	/* Disable region */
+	SYSMPU->WORD[region_index + part_index][0] = 0;
+	SYSMPU->WORD[region_index + part_index][1] = 0;
+	SYSMPU->WORD[region_index + part_index][2] = 0;
+	SYSMPU->WORD[region_index + part_index][3] = 0;
+}
+
+/**
+ * @brief get the maximum number of free regions for memory domain partitions
+ */
+int arm_core_mpu_get_max_domain_partition_regions(void)
+{
+	/*
+	 * Subtract the start of domain partition regions from total regions
+	 * should get the maximum number of free regions for memory domain
+	 * partitions. But we need to consume an extra 1 region to make
+	 * stack/stack guard protection work properly.
+	 * See the comments in arm_core_mpu_configure().
+	 */
+	return _get_num_regions() -
+		_get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION) - 1;
+}
+
+/**
+ * @brief validate the given buffer is user accessible or not
+ */
+int arm_core_mpu_buffer_validate(void *addr, size_t size, int write)
+{
+	u32_t r_index;
+
+	/* Iterate all mpu regions */
+	for (r_index = 0; r_index < _get_num_regions(); r_index++) {
+		if (!_is_enabled_region(r_index) ||
+		    !_is_in_region(r_index, (u32_t)addr, size)) {
+			continue;
+		}
+
+		/* For NXP MPU, priority given to granting permission over
+		 * denying access for overlapping region.
+		 * So we can stop the iteration immediately once we find the
+		 * matched region that grants permission.
+		 */
+		if (_is_user_accessible_region(r_index, write)) {
+			return 0;
+		}
+	}
+
+	return -EPERM;
+}
+#endif /* CONFIG_USERSPACE */
+
 /* NXP MPU Driver Initial Setup */
 
 /*

arch/arm/core/cortex_m/prep_c.c

@@ -20,23 +20,12 @@
 #include <zephyr/types.h>
 #include <toolchain.h>
 #include <linker/linker-defs.h>
-#include <nano_internal.h>
+#include <kernel_internal.h>
 #include <arch/arm/cortex_m/cmsis.h>
 #include <string.h>
 
-#ifdef CONFIG_ARMV6_M
+#ifdef CONFIG_CPU_CORTEX_M_HAS_VTOR
 
-#define VECTOR_ADDRESS 0
-static inline void relocate_vector_table(void)
-{
-#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \
-    !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
-	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
-	memcpy(VECTOR_ADDRESS, _vector_start, vector_size);
-#endif
-}
-
-#elif defined(CONFIG_ARMV7_M)
 #ifdef CONFIG_XIP
 #define VECTOR_ADDRESS ((uintptr_t)&_image_rom_start + \
 			CONFIG_TEXT_SECTION_OFFSET)
@@ -49,9 +38,26 @@ static inline void relocate_vector_table(void)
 	__DSB();
 	__ISB();
 }
+
 #else
-#error Unknown ARM architecture
-#endif /* CONFIG_ARMv6_M */
+
+#if defined(CONFIG_SW_VECTOR_RELAY)
+_GENERIC_SECTION(.vt_pointer_section) void *_vector_table_pointer;
+#endif
+
+#define VECTOR_ADDRESS 0
+void __weak relocate_vector_table(void)
+{
+#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \
+    !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
+	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
+	memcpy(VECTOR_ADDRESS, _vector_start, vector_size);
+#elif defined(CONFIG_SW_VECTOR_RELAY)
+	_vector_table_pointer = _vector_start;
+#endif
+}
+
+#endif /* CONFIG_CPU_CORTEX_M_HAS_VTOR */
 
 #ifdef CONFIG_FLOAT
 static inline void enable_floating_point(void)
@@ -73,7 +79,7 @@ static inline void enable_floating_point(void)
 	 * Although automatic state preservation is enabled, the processor
 	 * does not automatically save the volatile FP registers until they
 	 * have first been touched. Perform a dummy move operation so that
-	 * the stack frames are created as expected before any task or fiber
+	 * the stack frames are created as expected before any thread
 	 * context switching can occur.
 	 */
 	__asm__ volatile(

arch/arm/core/cortex_m/reset.S

@@ -58,14 +58,14 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset)
 SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
 
     /* lock interrupts: will get unlocked when switch to main task */
-#if defined(CONFIG_ARMV6_M)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
     cpsid i
-#elif defined(CONFIG_ARMV7_M)
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
     movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
     msr BASEPRI, r0
 #else
 #error Unknown ARM architecture
-#endif /* CONFIG_ARMV6_M */
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 
 #ifdef CONFIG_WDOG_INIT
     /* board-specific watchdog initialization is necessary */
@@ -81,7 +81,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
 
     /*
      * Set PSP and use it to boot without using MSP, so that it
-     * gets set to _interrupt_stack during nanoInit().
+     * gets set to _interrupt_stack during initialisation.
      */
     ldr r0, =_interrupt_stack
     ldr r1, =CONFIG_ISR_STACK_SIZE

arch/arm/core/cortex_m/vector_table.S

@@ -39,7 +39,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
     .word __nmi
 
     .word __hard_fault
-#if defined(CONFIG_ARMV6_M)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
     .word __reserved
     .word __reserved
     .word __reserved
@@ -49,7 +49,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
     .word __reserved
     .word __svc
     .word __reserved
-#elif defined(CONFIG_ARMV7_M)
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
     .word __mpu_fault
     .word __bus_fault
     .word __usage_fault
@@ -61,7 +61,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
     .word __debug_monitor
 #else
 #error Unknown ARM architecture
-#endif /* CONFIG_ARMV6_M */
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
     .word __reserved
     .word __pendsv
 #if defined(CONFIG_CORTEX_M_SYSTICK)

arch/arm/core/cortex_m/vector_table.h

@@ -38,9 +38,9 @@ GTEXT(_vector_table)
 GTEXT(__reset)
 GTEXT(__nmi)
 GTEXT(__hard_fault)
-#if defined(CONFIG_ARMV6_M)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
 GTEXT(__svc)
-#elif defined(CONFIG_ARMV7_M)
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 GTEXT(__mpu_fault)
 GTEXT(__bus_fault)
 GTEXT(__usage_fault)
@@ -48,7 +48,7 @@ GTEXT(__svc)
 GTEXT(__debug_monitor)
 #else
 #error Unknown ARM architecture
-#endif /* CONFIG_ARMV6_M */
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 GTEXT(__pendsv)
 GTEXT(__reserved)
 

arch/arm/core/cpu_idle.S

@@ -120,15 +120,15 @@ SECTION_FUNC(TEXT, k_cpu_idle)
 	mov lr, r0
 #endif
 
-#if defined(CONFIG_ARMV6_M)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
 	cpsie i
-#elif defined(CONFIG_ARMV7_M)
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	/* clear BASEPRI so wfi is awakened by incoming interrupts */
 	eors.n r0, r0
 	msr BASEPRI, r0
 #else
 #error Unknown ARM architecture
-#endif /* CONFIG_ARMV6_M */
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 
 	wfi
 
@@ -177,7 +177,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
 
 	/* r0: interrupt mask from caller */
 
-#if defined(CONFIG_ARMV6_M)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
 	/* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
 	wfe
 
@@ -186,7 +186,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
 	cpsie i
 _irq_disabled:
 
-#elif defined(CONFIG_ARMV7_M)
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	/* r1: zero, for setting BASEPRI (needs a register) */
 	eors.n r1, r1
 
@@ -199,5 +199,5 @@ _irq_disabled:
 	cpsie i
 #else
 #error Unknown ARM architecture
-#endif /* CONFIG_ARMV6_M  */
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 	bx lr

arch/arm/core/exc_exit.S

@@ -90,12 +90,12 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _ExcExit)
 #ifdef CONFIG_TIMESLICING
     push {lr}
     bl _update_time_slice_before_swap
-#if defined(CONFIG_ARMV6_M)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
     pop {r0}
     mov lr, r0
 #else
     pop {lr}
-#endif /* CONFIG_ARMV6_M */
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 #endif /* CONFIG_TIMESLICING */
 
     /* context switch required, pend the PendSV exception */
@@ -111,12 +111,12 @@ _EXIT_EXC:
 #ifdef CONFIG_STACK_SENTINEL
     push {lr}
     bl _check_stack_sentinel
-#if defined(CONFIG_ARMV6_M)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
     pop {r0}
     mov lr, r0
 #else
     pop {lr}
-#endif /* CONFIG_ARMV6_M */
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 #endif /* CONFIG_STACK_SENTINEL */
 
     bx lr