release: Zephyr 2.2.0

Bump version to 2.2.0 final.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>

.checkpatch.conf

@@ -1,4 +1,3 @@
---mailback
 --emacs
 --summary-file
 --show-types

.editorconfig

@@ -9,6 +9,7 @@ charset = utf-8
 end_of_line = lf
 insert_final_newline = true
 trim_trailing_whitespace = true
+max_line_length = 80
 
 # C
 [*.{c,h}]

.github/license_config.yml

@@ -0,0 +1,16 @@
+license:
+  main: apache-2.0
+  report_missing: true
+  category: Permissive
+copyright:
+  check: true
+exclude:
+  extensions:
+    - yml
+    - yaml
+    - html
+    - rst
+    - conf
+    - cfg
+  langs:
+    - HTML

.github/workflows/doc-build.yml

@@ -0,0 +1,65 @@
+# Copyright (c) 2020 Linaro Limited.
+# SPDX-License-Identifier: Apache-2.0
+
+name: Documentation GitHub Workflow
+
+on: [pull_request]
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+
+    steps:
+    - name: Update PATH for west
+      run: |
+        echo "::add-path::$HOME/.local/bin"
+
+    - name: checkout
+      uses: actions/checkout@v2
+
+    - name: install-pkgs
+      run: |
+        sudo apt-get install -y ninja-build doxygen
+
+    - name: cache-pip
+      uses: actions/cache@v1
+      with:
+        path: ~/.cache/pip
+        key: ${{ runner.os }}-doc-pip
+
+    - name: install-pip
+      run: |
+        pip3 install setuptools
+        pip3 install 'breathe>=4.9.1' 'docutils>=0.14' \
+                     'sphinx>=1.7.5' sphinx_rtd_theme sphinx-tabs \
+                     sphinxcontrib-svg2pdfconverter 'west>=0.6.2'
+        pip3 install pyelftools
+
+    - name: west setup
+      run: |
+        west init -l . || true
+
+    - name: build-docs
+      run: |
+        source zephyr-env.sh
+        make htmldocs
+        tar cvf htmldocs.tar --directory=./doc/_build html
+
+    - name: upload-build
+      uses: actions/upload-artifact@master
+      continue-on-error: True
+      with:
+        name: htmldocs.tar
+        path: htmldocs.tar
+
+    - name: check-warns
+      run: |
+        if [ -s doc/_build/doc.warnings ]; then
+           docwarn=$(cat doc/_build/doc.warnings)
+           docwarn="${docwarn//'%'/'%25'}"
+           docwarn="${docwarn//$'\n'/'%0A'}"
+           docwarn="${docwarn//$'\r'/'%0D'}"
+           # We treat doc warnings as errors
+           echo "::error file=doc.warnings::$docwarn"
+           exit 1
+        fi

.github/workflows/doc-publish.yml

@@ -0,0 +1,112 @@
+# Copyright (c) 2020 Linaro Limited.
+# SPDX-License-Identifier: Apache-2.0
+
+name: Doc build for Release or Daily
+
+# Either a daily based on schedule/cron or only on tag push
+on:
+  schedule:
+    - cron:  '50 22 * * *'
+  push:
+    tags:
+    - '*'
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+
+    steps:
+    - name: Update PATH for west
+      run: |
+        echo "::add-path::$HOME/.local/bin"
+
+    - name: Determine tag
+      id: tag
+      run: |
+        # We expect to get here either due to a schedule event in which
+        # case we are doing a daily build of the docs, or because a new
+        # tag was pushed, in which case we are building docs for a release
+        if [ ${GITHUB_EVENT_NAME} == "schedule" ]; then
+           echo ::set-output name=TYPE::daily;
+           echo ::set-output name=RELEASE::latest;
+        elif [ ${GITHUB_EVENT_NAME} == "push" ]; then
+           # If push due to a tag GITHUB_REF will look like refs/tags/TAG-FOO
+           # chop of 'refs/tags' so RELEASE=TAG-FOO
+           echo ::set-output name=TYPE::release;
+           echo ::set-output name=RELEASE::${GITHUB_REF/refs\/tags\//};
+        else
+           exit 1
+        fi
+
+    - name: Configure AWS Credentials
+      uses: aws-actions/configure-aws-credentials@v1
+      with:
+        aws-access-key-id: ${{ secrets.AWS_ACCESS_KEY_ID }}
+        aws-secret-access-key: ${{ secrets.AWS_SECRET_ACCESS_KEY }}
+        aws-region: us-east-1
+
+    - name: checkout
+      uses: actions/checkout@v2
+
+    - name: install-pkgs
+      run: |
+        sudo apt-get install -y ninja-build doxygen
+
+    - name: cache-pip
+      uses: actions/cache@v1
+      with:
+        path: ~/.cache/pip
+        key: ${{ runner.os }}-doc-pip
+
+    - name: install-pip
+      run: |
+        pip3 install setuptools
+        pip3 install 'breathe>=4.9.1' 'docutils>=0.14' \
+                     'sphinx>=1.7.5' sphinx_rtd_theme sphinx-tabs \
+                     sphinxcontrib-svg2pdfconverter 'west>=0.6.2'
+        pip3 install pyelftools
+
+    - name: west setup
+      run: |
+        west init -l . || true
+
+    - name: build-docs
+      env:
+        DOC_TAG: ${{ steps.tag.outputs.TYPE }}
+      run: |
+        source zephyr-env.sh
+        make DOC_TAG=${DOC_TAG} htmldocs
+
+    - name: check-warns
+      run: |
+        if [ -s doc/_build/doc.warnings ]; then
+           docwarn=$(cat doc/_build/doc.warnings)
+           docwarn="${docwarn//'%'/'%25'}"
+           docwarn="${docwarn//$'\n'/'%0A'}"
+           docwarn="${docwarn//$'\r'/'%0D'}"
+           # We treat doc warnings as errors
+           echo "::error file=doc.warnings::$docwarn"
+           exit 1
+        fi
+
+    - name: Upload to AWS S3
+      env:
+        RELEASE: ${{ steps.tag.outputs.RELEASE }}
+      run: |
+        echo "DOC_RELEASE=[$RELEASE]"
+        if [ "$RELEASE" == "latest" ]; then
+           export
+           echo "publish latest docs"
+           aws s3 sync  --quiet doc/_build/html s3://docs.zephyrproject.org/latest --delete
+           echo "success sync of latest docs"
+        else
+           DOC_RELEASE=${RELEASE}.0
+           echo "publish release docs: ${DOC_RELEASE}"
+           aws s3 sync  --quiet doc/_build/html s3://docs.zephyrproject.org/${DOC_RELEASE}
+           echo "success sync of rel docs"
+        fi
+        if [ -d doc/_build/doxygen/html ]; then
+           echo "publish doxygen"
+           aws s3 sync  --quiet doc/_build/doxygen/html s3://docs.zephyrproject.org/apidoc/${RELEASE} --delete
+           echo "success publish of doxygen"
+        fi

.github/workflows/license_check.yml

@@ -0,0 +1,32 @@
+name: Scancode
+
+on: [pull_request]
+
+jobs:
+  scancode_job:
+    runs-on: ubuntu-latest
+    name: Scan code for licenses
+    steps:
+    - name: Checkout the code
+      uses: actions/checkout@v1
+    - name: Scan the code
+      id: scancode
+      uses: zephyrproject-rtos/action_scancode@v3
+      with:
+        directory-to-scan: 'scan/'
+    - name: Artifact Upload
+      uses: actions/upload-artifact@v1
+      with:
+        name: scancode
+        path: ./artifacts
+
+    - name: Verify
+      run: |
+        if [ -s ./artifacts/report.txt ]; then
+          report=$(cat ./artifacts/report.txt)
+          report="${report//'%'/'%25'}"
+          report="${report//$'\n'/'%0A'}"
+          report="${report//$'\r'/'%0D'}"
+          echo "::error file=./artifacts/report.txt::$report"
+          exit 1
+        fi

.github/workflows/west_cmds.yml

@@ -0,0 +1,65 @@
+# Copyright (c) 2020 Linaro Limited.
+# SPDX-License-Identifier: Apache-2.0
+
+name: Zephyr West Command Tests
+
+on:
+  push:
+    paths:
+    - 'scripts/west-commands.yml'
+    - 'scripts/west_commands/**'
+  pull_request:
+    paths:
+    - 'scripts/west-commands.yml'
+    - 'scripts/west_commands/**'
+
+jobs:
+  build:
+    runs-on: ${{ matrix.os }}
+    strategy:
+      matrix:
+        python-version: [3.6, 3.7, 3.8]
+        os: [ubuntu-latest, macos-latest, windows-latest]
+    steps:
+    - name: checkout
+      uses: actions/checkout@v2
+    - name: Set up Python ${{ matrix.python-version }}
+      uses: actions/setup-python@v1
+      with:
+        python-version: ${{ matrix.python-version }}
+    - name: cache-pip-linux
+      if: startsWith(runner.os, 'Linux')
+      uses: actions/cache@v1
+      with:
+        path: ~/.cache/pip
+        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
+        restore-keys: |
+          ${{ runner.os }}-pip-${{ matrix.python-version }}
+    - name: cache-pip-mac
+      if: startsWith(runner.os, 'macOS')
+      uses: actions/cache@v1
+      with:
+        path: ~/Library/Caches/pip
+        # Trailing '-' was just to get a different cache name
+        key: ${{ runner.os }}-pip-${{ matrix.python-version }}-
+        restore-keys: |
+          ${{ runner.os }}-pip-${{ matrix.python-version }}-
+    - name: cache-pip-win
+      if: startsWith(runner.os, 'Windows')
+      uses: actions/cache@v1
+      with:
+        path: ~\AppData\Local\pip\Cache
+        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
+        restore-keys: |
+          ${{ runner.os }}-pip-${{ matrix.python-version }}
+    - name: install pytest
+      run: |
+        pip3 install pytest west pyelftools
+    - name: run pytest-win
+      if: runner.os == 'Windows'
+      run: |
+        cmd /C "set PYTHONPATH=.\scripts\west_commands && pytest ./scripts/west_commands/tests/"
+    - name: run pytest-mac-linux
+      if: runner.os != 'Windows'
+      run: |
+        PYTHONPATH=./scripts/west_commands pytest ./scripts/west_commands/tests/

.gitignore

@@ -8,6 +8,7 @@
 *.swo
 *~
 build*/
+!doc/guides/build
 cscope.*
 .dir
 

.known-issues/doc/bluetooth.conf

@@ -48,3 +48,21 @@
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
 ^.*bt_mesh_model.__unnamed__.*
 ^[- \t]*\^
+#
+# Bluetooth mesh pub struct definition
+#
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]bluetooth[/\\]mesh[/\\]access.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_mesh_model_pub.*
+^[- \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_mesh_model_pub.*
+^[- \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_mesh_model_pub.*
+^[- \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_mesh_model_pub.*
+^[- \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_mesh_model_pub.*
+^[- \t]*\^

.known-issues/doc/duplicate.conf

@@ -1,6 +1,6 @@
 #
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]file_system[/\\]index.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration.
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]file_system[/\\]index.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)
 #
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]dma.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration.
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]dma.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)
 #
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]sensor.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration.
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]sensor.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)

.known-issues/doc/networking.conf

@@ -67,4 +67,4 @@
 #
 # stray duplicate definition warnings
 #
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]networking[/\\]net_if.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration.
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]networking[/\\]net_if.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)

.mailmap

@@ -28,3 +28,5 @@ Jun Li <jun.r.li@intel.com>
 Xiaorui Hu <xiaorui.hu@linaro.org>
 Yannis Damigos <giannis.damigos@gmail.com> <ydamigos@iccs.gr>
 Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no> <vinayak.kariappa.chettimada@nordicsemi.no> <vich@nordicsemi.no> <vinayak.kariappa@gmail.com>
+Sean Nyekjaer <sean@geanix.com> <sean.nyekjaer@prevas.dk>
+Sean Nyekjaer <sean@geanix.com> <sean@nyekjaer.dk>

.shippable.yml

@@ -4,7 +4,7 @@ compiler: gcc
 
 env:
     global:
-        - ZEPHYR_SDK_INSTALL_DIR=/opt/sdk/zephyr-sdk-0.10.3
+        - ZEPHYR_SDK_INSTALL_DIR=/opt/sdk/zephyr-sdk-0.11.2
         - ZEPHYR_TOOLCHAIN_VARIANT=zephyr
         - MATRIX_BUILDS="5"
     matrix:
@@ -20,7 +20,7 @@ build:
         - ${SHIPPABLE_BUILD_DIR}/ccache
     pre_ci_boot:
         image_name: zephyrprojectrtos/ci
-        image_tag: v0.9
+        image_tag: v0.11.4
         pull: true
         options: "-e HOME=/home/buildslave --privileged=true --tty --net=bridge --user buildslave"
 

CMakeLists.txt

@@ -35,12 +35,10 @@ endif()
 # For Zephyr more specifically this breaks (at least)
 #     -fmacro-prefix-map=${ZEPHYR_BASE}=
 
-project(Zephyr-Kernel VERSION ${PROJECT_VERSION})
-enable_language(C CXX ASM)
 
 # Verify that the toolchain can compile a dummy file, if it is not we
 # won't be able to test for compatibility with certain C flags.
-check_c_compiler_flag("" toolchain_is_ok)
+zephyr_check_compiler_flag(C "" toolchain_is_ok)
 assert(toolchain_is_ok "The toolchain is unable to build a dummy C file. See CMakeError.log.")
 
 # In some cases the "final" things are not used at all and "_prebuilt"
@@ -52,7 +50,6 @@ set(ZEPHYR_FINAL_EXECUTABLE    zephyr_final)
 
 # Set some phony targets to collect dependencies
 set(OFFSETS_H_TARGET           offsets_h)
-set(SYSCALL_MACROS_H_TARGET    syscall_macros_h_target)
 set(SYSCALL_LIST_H_TARGET      syscall_list_h_target)
 set(DRIVER_VALIDATION_H_TARGET driver_validation_h_target)
 set(KOBJ_TYPES_H_TARGET        kobj_types_h_target)
@@ -75,10 +72,7 @@ add_library(zephyr_interface INTERFACE)
 zephyr_library_named(zephyr)
 
 zephyr_include_directories(
-  kernel/include
-  ${ARCH_DIR}/${ARCH}/include
   include
-  include/drivers
   ${PROJECT_BINARY_DIR}/include/generated
   ${USERINCLUDE}
   ${STDINCLUDE}
@@ -148,6 +142,13 @@ else()
   assert(0 "Unreachable code. Expected optimization level to have been chosen. See Kconfig.zephyr")
 endif()
 
+if(NOT CONFIG_ARCH_IS_SET)
+  message(WARNING "\
+None of the CONFIG_<arch> (e.g. CONFIG_X86) symbols are set. \
+Select one of them from the SOC_SERIES_* symbol or, lacking that, from the \
+SOC_* symbol.")
+endif()
+
 # Apply the final optimization flag(s)
 zephyr_compile_options(${OPTIMIZATION_FLAG})
 
@@ -333,12 +334,14 @@ zephyr_cc_option_ifdef(CONFIG_STACK_USAGE            -fstack-usage)
 # in binaries, makes failure logs more deterministic and most
 # importantly makes builds more deterministic
 
-# If both match then the last one wins. This matters for tests/ and
-# samples/ inside *both* CMAKE_SOURCE_DIR and ZEPHYR_BASE: for them
-# let's strip the shortest prefix.
+# If several match then the last one wins. This matters for instances
+# like tests/ and samples/: they're inside all of them! Then let's
+# strip as little as possible.
 zephyr_cc_option(-fmacro-prefix-map=${CMAKE_SOURCE_DIR}=CMAKE_SOURCE_DIR)
 zephyr_cc_option(-fmacro-prefix-map=${ZEPHYR_BASE}=ZEPHYR_BASE)
-# TODO: -fmacro-prefix-map=modules/etc. "build/zephyr_modules.txt" might help.
+if(WEST_TOPDIR)
+  zephyr_cc_option(-fmacro-prefix-map=${WEST_TOPDIR}=WEST_TOPDIR)
+endif()
 
 # TODO: Archiver arguments
 # ar_option(D)
@@ -405,11 +408,11 @@ set_ifndef(  DTS_BOARD_FIXUP_FILE                                   ${BOARD_DIR}
 set_ifndef(    DTS_SOC_FIXUP_FILE                 ${SOC_DIR}/${ARCH}/${SOC_PATH}/dts_fixup.h)
 set(           DTS_APP_FIXUP_FILE                      ${APPLICATION_SOURCE_DIR}/dts_fixup.h)
 
-set_ifndef(DTS_CAT_OF_FIXUP_FILES ${ZEPHYR_BINARY_DIR}/include/generated/generated_dts_board_fixups.h)
+set_ifndef(DTS_CAT_OF_FIXUP_FILES ${ZEPHYR_BINARY_DIR}/include/generated/devicetree_fixups.h)
 
 # Concatenate the fixups into a single header file for easy
 # #include'ing
-file(WRITE ${DTS_CAT_OF_FIXUP_FILES} "/* May only be included by generated_dts_board.h */\n\n")
+file(WRITE ${DTS_CAT_OF_FIXUP_FILES} "/* May only be included by devicetree.h */\n\n")
 foreach(fixup_file
     ${DTS_BOARD_FIXUP_FILE}
     ${DTS_SOC_FIXUP_FILE}
@@ -460,6 +463,7 @@ add_subdirectory(drivers)
 if(EXISTS ${CMAKE_BINARY_DIR}/zephyr_modules.txt)
 	file(STRINGS ${CMAKE_BINARY_DIR}/zephyr_modules.txt ZEPHYR_MODULES_TXT
 		ENCODING UTF-8)
+  set(module_names)
 
   foreach(module ${ZEPHYR_MODULES_TXT})
     # Match "<name>":"<path>" for each line of file, each corresponding to
@@ -467,28 +471,27 @@ if(EXISTS ${CMAKE_BINARY_DIR}/zephyr_modules.txt)
     # lazy regexes (it supports greedy only).
     string(REGEX REPLACE "\"(.*)\":\".*\"" "\\1" module_name ${module})
     string(REGEX REPLACE "\".*\":\"(.*)\"" "\\1" module_path ${module})
-    message("Including module: ${module_name} in path: ${module_path}")
+
+    list(APPEND module_names ${module_name})
+
+    string(TOUPPER ${module_name} MODULE_NAME_UPPER)
+    set(ZEPHYR_${MODULE_NAME_UPPER}_MODULE_DIR ${module_path})
+  endforeach()
+
+  foreach(module_name ${module_names})
     # Note the second, binary_dir parameter requires the added
     # subdirectory to have its own, local cmake target(s). If not then
     # this binary_dir is created but stays empty. Object files land in
     # the main binary dir instead.
     # https://cmake.org/pipermail/cmake/2019-June/069547.html
-    add_subdirectory(${module_path} ${CMAKE_BINARY_DIR}/modules/${module_name})
+    string(TOUPPER ${module_name} MODULE_NAME_UPPER)
+    set(ZEPHYR_CURRENT_MODULE_DIR ${ZEPHYR_${MODULE_NAME_UPPER}_MODULE_DIR})
+    add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR} ${CMAKE_BINARY_DIR}/modules/${module_name})
   endforeach()
+  # Done processing modules, clear ZEPHYR_CURRENT_MODULE_DIR.
+  set(ZEPHYR_CURRENT_MODULE_DIR)
 endif()
 
-set(syscall_macros_h ${ZEPHYR_BINARY_DIR}/include/generated/syscall_macros.h)
-
-add_custom_target(${SYSCALL_MACROS_H_TARGET} DEPENDS ${syscall_macros_h})
-add_custom_command(                          OUTPUT  ${syscall_macros_h}
-  COMMAND
-  ${PYTHON_EXECUTABLE}
-  ${ZEPHYR_BASE}/scripts/gen_syscall_header.py
-  > ${syscall_macros_h}
-  DEPENDS ${ZEPHYR_BASE}/scripts/gen_syscall_header.py
-  )
-
-
 set(syscall_list_h ${CMAKE_CURRENT_BINARY_DIR}/include/generated/syscall_list.h)
 set(syscalls_json  ${CMAKE_CURRENT_BINARY_DIR}/misc/generated/syscalls.json)
 
@@ -564,12 +567,21 @@ else()
   set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${syscalls_subdirs_txt})
 endif()
 
-# SYSCALL_INCLUDE_DIRECTORY will include the directories that needs to be
-# searched for syscall declarations if CONFIG_APPLICATION_DEFINED_SYSCALL is set
+# syscall declarations are searched for in the SYSCALL_INCLUDE_DIRS
 if(CONFIG_APPLICATION_DEFINED_SYSCALL)
-  set(SYSCALL_INCLUDE_DIRECTORY --include ${APPLICATION_SOURCE_DIR})
+  list(APPEND SYSCALL_INCLUDE_DIRS ${APPLICATION_SOURCE_DIR})
 endif()
 
+if(CONFIG_ZTEST)
+  list(APPEND SYSCALL_INCLUDE_DIRS ${ZEPHYR_BASE}/subsys/testsuite/ztest/include)
+endif()
+
+foreach(d ${SYSCALL_INCLUDE_DIRS})
+  list(APPEND parse_syscalls_include_args
+    --include ${d}
+    )
+endforeach()
+
 add_custom_command(
   OUTPUT
   ${syscalls_json}
@@ -577,12 +589,20 @@ add_custom_command(
   ${PYTHON_EXECUTABLE}
   ${ZEPHYR_BASE}/scripts/parse_syscalls.py
    --include          ${ZEPHYR_BASE}/include        # Read files from this dir
-  ${SYSCALL_INCLUDE_DIRECTORY}
+  ${parse_syscalls_include_args}                    # Read files from these dirs also
   --json-file        ${syscalls_json}              # Write this file
   DEPENDS ${syscalls_subdirs_trigger} ${PARSE_SYSCALLS_HEADER_DEPENDS}
   )
 
 add_custom_target(${SYSCALL_LIST_H_TARGET} DEPENDS             ${syscall_list_h})
+
+# 64-bit systems do not require special handling of 64-bit system call
+# parameters or return values, indicate this to the system call boilerplate
+# generation script.
+if(CONFIG_64BIT)
+  set(SYSCALL_LONG_REGISTERS_ARG --long-registers)
+endif()
+
 add_custom_command(OUTPUT include/generated/syscall_dispatch.c ${syscall_list_h}
   # Also, some files are written to include/generated/syscalls/
   COMMAND
@@ -592,6 +612,7 @@ add_custom_command(OUTPUT include/generated/syscall_dispatch.c ${syscall_list_h}
   --base-output      include/generated/syscalls           # Write to this dir
   --syscall-dispatch include/generated/syscall_dispatch.c # Write this file
   --syscall-list     ${syscall_list_h}
+  ${SYSCALL_LONG_REGISTERS_ARG}
   WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
   DEPENDS ${syscalls_json}
   )
@@ -612,6 +633,14 @@ add_custom_target(${DRIVER_VALIDATION_H_TARGET} DEPENDS ${DRV_VALIDATION})
 include($ENV{ZEPHYR_BASE}/cmake/kobj.cmake)
 gen_kobj(KOBJ_INCLUDE_PATH)
 
+# Add a pseudo-target that is up-to-date when all generated headers
+# are up-to-date.
+
+add_custom_target(zephyr_generated_headers)
+add_dependencies(zephyr_generated_headers
+  offsets_h
+  )
+
 # Generate offsets.c.obj from offsets.c
 # Generate offsets.h     from offsets.c.obj
 
@@ -621,10 +650,13 @@ set(OFFSETS_C_PATH ${ARCH_DIR}/${ARCH}/core/offsets/offsets.c)
 set(OFFSETS_H_PATH ${PROJECT_BINARY_DIR}/include/generated/offsets.h)
 
 add_library(          ${OFFSETS_LIB} OBJECT ${OFFSETS_C_PATH})
+target_include_directories(${OFFSETS_LIB} PRIVATE
+  kernel/include
+  ${ARCH_DIR}/${ARCH}/include
+  )
 target_link_libraries(${OFFSETS_LIB} zephyr_interface)
 add_dependencies(     ${OFFSETS_LIB}
   ${SYSCALL_LIST_H_TARGET}
-  ${SYSCALL_MACROS_H_TARGET}
   ${DRIVER_VALIDATION_H_TARGET}
   ${KOBJ_TYPES_H_TARGET}
   )
@@ -651,7 +683,7 @@ get_property(ZEPHYR_LIBS_PROPERTY GLOBAL PROPERTY ZEPHYR_LIBS)
 
 foreach(zephyr_lib ${ZEPHYR_LIBS_PROPERTY})
   # TODO: Could this become an INTERFACE property of zephyr_interface?
-  add_dependencies(${zephyr_lib} ${OFFSETS_H_TARGET})
+  add_dependencies(${zephyr_lib} zephyr_generated_headers)
 endforeach()
 
 get_property(OUTPUT_FORMAT        GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT)
@@ -666,7 +698,7 @@ configure_linker_script(
   ${PRIV_STACK_DEP}
   ${APP_SMEM_ALIGNED_DEP}
   ${CODE_RELOCATION_DEP}
-  ${OFFSETS_H_TARGET}
+  zephyr_generated_headers
   )
 
 add_custom_target(
@@ -780,6 +812,10 @@ if(CONFIG_ARM AND CONFIG_USERSPACE)
     )
   add_custom_target(priv_stacks DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${PRIV_STACKS})
 
+  if(${GPERF} STREQUAL GPERF-NOTFOUND)
+    message(FATAL_ERROR "Unable to find gperf")
+  endif()
+
   # Use gperf to generate C code (PRIV_STACKS_OUTPUT_SRC_PRE) which implements a
   # perfect hashtable based on PRIV_STACKS
   add_custom_command(
@@ -1044,8 +1080,8 @@ if(CONFIG_USERSPACE)
   if(CONFIG_NEWLIB_LIBC)
     set(NEWLIB_PART -l libc.a z_libc_partition)
   endif()
-  if(CONFIG_MBEDTLS)
-    set(MBEDTLS_PART -l lib..__modules__crypto__mbedtls.a k_mbedtls_partition)
+  if(CONFIG_NEWLIB_LIBC_NANO)
+    set(NEWLIB_PART -l libc_nano.a z_libc_partition)
   endif()
 
   add_custom_command(
@@ -1054,12 +1090,14 @@ if(CONFIG_USERSPACE)
     ${ZEPHYR_BASE}/scripts/gen_app_partitions.py
     -d ${OBJ_FILE_DIR}
     -o ${APP_SMEM_UNALIGNED_LD}
-    ${NEWLIB_PART} ${MBEDTLS_PART}
+    ${NEWLIB_PART}
+    $<TARGET_PROPERTY:zephyr_property_target,COMPILE_OPTIONS>
     $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
     DEPENDS
     kernel
     ${ZEPHYR_LIBS_PROPERTY}
     WORKING_DIRECTORY ${PROJECT_BINARY_DIR}/
+    COMMAND_EXPAND_LISTS
     COMMENT "Generating app_smem_unaligned linker section"
     )
 
@@ -1069,7 +1107,7 @@ if(CONFIG_USERSPACE)
     ${CODE_RELOCATION_DEP}
     ${APP_SMEM_UNALIGNED_DEP}
     ${APP_SMEM_UNALIGNED_LD}
-    ${OFFSETS_H_TARGET}
+    zephyr_generated_headers
     )
 
   add_custom_target(
@@ -1103,13 +1141,15 @@ if(CONFIG_USERSPACE)
     ${ZEPHYR_BASE}/scripts/gen_app_partitions.py
     -e $<TARGET_FILE:app_smem_unaligned_prebuilt>
     -o ${APP_SMEM_ALIGNED_LD}
-    ${NEWLIB_PART} ${MBEDTLS_PART}
+    ${NEWLIB_PART}
+    $<TARGET_PROPERTY:zephyr_property_target,COMPILE_OPTIONS>
     $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
     DEPENDS
     kernel
     ${ZEPHYR_LIBS_PROPERTY}
     app_smem_unaligned_prebuilt
     WORKING_DIRECTORY ${PROJECT_BINARY_DIR}/
+    COMMAND_EXPAND_LISTS
     COMMENT "Generating app_smem_aligned linker section"
     )
 endif()
@@ -1121,7 +1161,7 @@ if(CONFIG_USERSPACE AND CONFIG_ARM)
     ${CODE_RELOCATION_DEP}
     ${APP_SMEM_ALIGNED_DEP}
     ${APP_SMEM_ALIGNED_LD}
-    ${OFFSETS_H_TARGET}
+    zephyr_generated_headers
     )
 
   add_custom_target(
@@ -1179,7 +1219,7 @@ else()
     ${PRIV_STACK_DEP}
     ${CODE_RELOCATION_DEP}
     ${ZEPHYR_PREBUILT_EXECUTABLE}
-    ${OFFSETS_H_TARGET}
+    zephyr_generated_headers
     )
 
   set(LINKER_PASS_FINAL_SCRIPT_TARGET linker_pass_final_script_target)
@@ -1461,6 +1501,8 @@ if(HEX_FILES_TO_MERGE)
 
   add_custom_target(mergehex ALL DEPENDS ${MERGED_HEX_NAME})
   list(APPEND FLASH_DEPS mergehex)
+
+  message(VERBOSE "Merging hex files: ${HEX_FILES_TO_MERGE}")
 endif()
 
 if(EMU_PLATFORM)
@@ -1479,24 +1521,48 @@ add_subdirectory(cmake/flash)
 add_subdirectory(cmake/usage)
 add_subdirectory(cmake/reports)
 
+add_subdirectory_ifdef(
+  CONFIG_MAKEFILE_EXPORTS
+  cmake/makefile_exports
+  )
+
 if(NOT CONFIG_TEST)
 if(CONFIG_ASSERT AND (NOT CONFIG_FORCE_NO_ASSERT))
-  message(WARNING "
-      ------------------------------------------------------------
-      --- WARNING:  __ASSERT() statements are globally ENABLED ---
-      --- The kernel will run more slowly and use more memory  ---
-      ------------------------------------------------------------"
-  )
+  message(WARNING "__ASSERT() statements are globally ENABLED")
 endif()
 endif()
 
-if(CONFIG_BOARD_DEPRECATED)
+if(CONFIG_BOARD_DEPRECATED_RELEASE)
   message(WARNING "
       WARNING:  The board '${BOARD}' is deprecated and will be
-      removed in version ${CONFIG_BOARD_DEPRECATED}"
+      removed in version ${CONFIG_BOARD_DEPRECATED_RELEASE}"
   )
 endif()
 
+if(CONFIG_SOC_DEPRECATED_RELEASE)
+  message(WARNING "
+      WARNING:  The SoC '${SOC_NAME}' is deprecated and will be
+      removed in version ${CONFIG_SOC_DEPRECATED_RELEASE}"
+  )
+endif()
+
+# In CMake projects, 'CMAKE_BUILD_TYPE' usually determines the
+# optimization flag, but in Zephyr it is determined through
+# Kconfig. Here we give a warning when there is a mismatch between the
+# two in case the user is not aware of this.
+set(build_types None Debug Release RelWithDebInfo MinSizeRel)
+
+if((CMAKE_BUILD_TYPE IN_LIST build_types) AND (NOT NO_BUILD_TYPE_WARNING))
+  string(TOUPPER ${CMAKE_BUILD_TYPE} CMAKE_BUILD_TYPE_uppercase)
+
+  if(NOT (${OPTIMIZATION_FLAG} IN_LIST CMAKE_C_FLAGS_${CMAKE_BUILD_TYPE_uppercase}))
+    message(WARNING "
+      The CMake build type was set to '${CMAKE_BUILD_TYPE}', but the optimization flag was set to '${OPTIMIZATION_FLAG}'.
+      This may be intentional and the warning can be turned off by setting the CMake variable 'NO_BUILD_TYPE_WARNING'"
+      )
+  endif()
+endif()
+
 # @Intent: Set compiler specific flags for standard C includes
 # Done at the very end, so any other system includes which may
 # be added by Zephyr components were first in list.

CODEOWNERS

@@ -5,50 +5,53 @@
 # Order is important; for each modified file, the last matching
 # pattern takes the most precedence.
 # That is, with the last pattern being
-# *.rst                                     @dbkinder
-# if only .rst files are being modified, only dbkinder is
+# *.rst                                     @nashif
+# if only .rst files are being modified, only nashif is
 # automatically requested for review, but you can manually
 # add others as needed.
 
 # Do not use wildcard on all source yet
 # *                                        @galak @nashif
 
-/.known-issues/                           @inakypg @nashif
+/.known-issues/                           @nashif
+/.github/				  @nashif
+/.github/workflows/                       @galak @nashif
 /arch/arc/                                @vonhust @ruuddw
 /arch/arm/                                @MaureenHelm @galak @ioannisg
-/arch/arm/core/cortex_m/cmse/             @ioannisg
-/arch/arm/include/cortex_m/cmse.h         @ioannisg
-/arch/arm/core/cortex_r/                  @MaureenHelm @galak @ioannisg @bbolen
+/arch/arm/core/aarch32/cortex_m/cmse/     @ioannisg
+/arch/arm/core/aarch64/                   @carlocaione
+/arch/arm/include/aarch32/cortex_m/cmse.h @ioannisg
+/arch/arm/include/aarch64/                @carlocaione
+/arch/arm/core/aarch32/cortex_r/          @MaureenHelm @galak @ioannisg @bbolen @stephanosio
 /arch/common/                             @andrewboie @ioannisg @andyross
-/arch/x86_64/                             @andyross
 /soc/arc/snps_*/                          @vonhust @ruuddw
 /soc/nios2/                               @nashif @wentongwu
 /soc/arm/                                 @MaureenHelm @galak @ioannisg
 /soc/arm/arm/mps2/                        @fvincenzo
 /soc/arm/atmel_sam/sam3x/                 @ioannisg
+/soc/arm/atmel_sam/sam4e/                 @nandojve
 /soc/arm/atmel_sam/sam4s/                 @fallrisk
+/soc/arm/atmel_sam/samv71/                @nandojve
+/soc/arm/bcm*/                            @sbranden
 /soc/arm/nxp*/                            @MaureenHelm
 /soc/arm/nordic_nrf/                      @ioannisg
+/soc/arm/qemu_cortex_a53/                 @carlocaione
 /soc/arm/st_stm32/                        @erwango
 /soc/arm/st_stm32/stm32f4/                @rsalveti @idlethread
-/soc/arm/st_stm32/stm32mp1/               @arnop2
+/soc/arm/st_stm32/stm32mp1/               @arnopo
 /soc/arm/ti_simplelink/cc13x2_cc26x2/     @bwitherspoon
 /soc/arm/ti_simplelink/cc32xx/            @vanti
 /soc/arm/ti_simplelink/msp432p4xx/        @Mani-Sadhasivam
+/soc/arm/xilinx_zynqmp/                   @stephanosio
 /soc/xtensa/intel_s1000/                  @sathishkuttan @dcpleung
-/soc/x86_64/                              @andyross
-/arch/x86/                                @andrewboie @gnuless
+/arch/x86/                                @andrewboie
 /arch/nios2/                              @andrewboie @wentongwu
 /arch/posix/                              @aescolar
 /arch/riscv/                              @kgugala @pgielda @nategraff-sifive
 /soc/posix/                               @aescolar
 /soc/riscv/                               @kgugala @pgielda @nategraff-sifive
 /soc/riscv/openisa*/                      @MaureenHelm
-/arch/x86/core/                           @andrewboie @gnuless
-/arch/x86/core/ia32/crt0.S                @andrewboie @gnuless
-/arch/x86/core/pcie.c                     @gnuless
-/arch/x86/core/multiboot.c                @gnuless
-/soc/x86/                                 @andrewboie @gnuless
+/soc/x86/                                 @andrewboie
 /arch/xtensa/                             @andrewboie @dcpleung @andyross
 /soc/xtensa/                              @andrewboie @dcpleung @andyross
 /boards/arc/                              @vonhust @ruuddw
@@ -68,6 +71,7 @@
 /boards/arm/disco_l475_iot1/              @erwango
 /boards/arm/frdm*/                        @MaureenHelm
 /boards/arm/frdm*/doc/                    @MaureenHelm @MeganHansen
+/boards/arm/google_*/                     @jackrosenthal
 /boards/arm/hexiwear*/                    @MaureenHelm
 /boards/arm/hexiwear*/doc/                @MaureenHelm @MeganHansen
 /boards/arm/lpcxpresso*/                  @MaureenHelm
@@ -79,12 +83,21 @@
 /boards/arm/nrf*/                         @carlescufi @lemrey @ioannisg
 /boards/arm/nucleo*/                      @erwango
 /boards/arm/nucleo_f401re/                @rsalveti @idlethread
+/boards/arm/qemu_cortex_a53/              @carlocaione
+/boards/arm/qemu_cortex_r*/               @stephanosio
+/boards/arm/qemu_cortex_m*/               @ioannisg
+/boards/arm/sam4e_xpro/                   @nandojve
 /boards/arm/sam4s_xplained/               @fallrisk
+/boards/arm/sam_v71_xult/                 @nandojve
 /boards/arm/v2m_beetle/                   @fvincenzo
 /boards/arm/olimexino_stm32/              @ydamigos
+/boards/arm/sensortile_box/               @avisconti
+/boards/arm/steval_fcu001v1/              @Navin-Sankar
+/boards/arm/stm32l1_disco/                @karlp
 /boards/arm/stm32*_disco/                 @erwango
 /boards/arm/stm32f3_disco/                @ydamigos
 /boards/arm/stm32*_eval/                  @erwango
+/boards/common/                           @mbolivar
 /boards/nios2/                            @wentongwu
 /boards/nios2/altera_max10/               @wentongwu
 /boards/arm/stm32_min_dev/                @cbsiddharth
@@ -93,9 +106,9 @@
 /boards/riscv/rv32m1_vega/                @MaureenHelm
 /boards/shields/                          @erwango
 /boards/x86/                              @andrewboie @nashif
-/boards/x86/up_squared/                   @gnuless
 /boards/xtensa/                           @nashif @dcpleung
 /boards/xtensa/intel_s1000_crb/           @sathishkuttan @dcpleung
+/boards/xtensa/odroid_go/                 @ydamigos
 # All cmake related files
 /cmake/                                   @SebastianBoe @nashif
 /CMakeLists.txt                           @SebastianBoe @nashif
@@ -105,9 +118,11 @@
 /doc/scripts/                             @carlescufi
 /doc/guides/bluetooth/                    @joerchan @jhedberg @Vudentz
 /doc/reference/bluetooth/                 @joerchan @jhedberg @Vudentz
+/doc/reference/kernel/other/resource_mgmt.rst @pabigot
+/doc/reference/networking/can*            @alexanderwachter
+/drivers/debug/                           @nashif
 /drivers/*/*cc13xx_cc26xx*                @bwitherspoon
 /drivers/*/*mcux*                         @MaureenHelm
-/drivers/*/*qmsi*                         @nashif
 /drivers/*/*stm32*                        @erwango
 /drivers/*/*native_posix*                 @aescolar
 /drivers/adc/                             @anangl
@@ -115,31 +130,55 @@
 /drivers/bluetooth/                       @joerchan @jhedberg @Vudentz
 /drivers/can/                             @alexanderwachter
 /drivers/can/*mcp2515*                    @karstenkoenig
+/drivers/clock_control/*nrf*              @nordic-krch
 /drivers/counter/                         @nordic-krch
-/drivers/counter/counter_cmos.c           @gnuless
+/drivers/counter/counter_cmos.c           @andrewboie
 /drivers/display/                         @vanwinkeljan
-/drivers/display/display_framebuf.c       @gnuless
+/drivers/display/display_framebuf.c       @andrewboie
+/drivers/dma/*dw*                         @tbursztyka
 /drivers/dma/*sam0*                       @Sizurka
+/drivers/dma/dma_stm32*                   @cybertale
+/drivers/eeprom/                          @henrikbrixandersen
+/drivers/eeprom/eeprom_stm32.c            @KwonTae-young
+/drivers/entropy/*rv32m1*                 @MaureenHelm
 /drivers/espi/                            @albertofloyd @franciscomunoz @scottwcpg
+/drivers/ps2/                             @albertofloyd @franciscomunoz @scottwcpg
+/drivers/kscan/                           @albertofloyd @franciscomunoz @scottwcpg
 /drivers/ethernet/                        @jukkar @tbursztyka @pfalcon
-/drivers/flash/                           @nashif
-/drivers/flash/*native_posix*             @vanwinkeljan @aescolar
+/drivers/entropy/*litex*                  @mateusz-holenko @kgugala @pgielda
+/drivers/flash/                           @nashif @nvlsianpu
+/drivers/flash/*nrf*                      @nvlsianpu
+/drivers/flash/*spi_nor*                  @pabigot
 /drivers/flash/*stm32*                    @superna9999
+/drivers/gpio/                            @mnkp @pabigot
 /drivers/gpio/*ht16k33*                   @henrikbrixandersen
-/drivers/gpio/*stm32*                     @rsalveti @idlethread
+/drivers/gpio/*lmp90xxx*                  @henrikbrixandersen
+/drivers/gpio/*stm32*                     @erwango
+/drivers/gpio/*sx1509b*                   @pabigot
+/drivers/gpio/*litex*                     @mateusz-holenko @kgugala @pgielda
 /drivers/hwinfo/                          @alexanderwachter
+/drivers/i2c/*litex*                      @mateusz-holenko @kgugala @pgielda
 /drivers/i2s/i2s_ll_stm32*                @avisconti
+/drivers/i2c/i2c_shell.c                  @nashif
 /drivers/ieee802154/                      @jukkar @tbursztyka
+/drivers/ieee802154/ieee802154_rf2xx*     @jukkar @tbursztyka @nandojve
 /drivers/interrupt_controller/            @andrewboie
+/drivers/interrupt_controller/intc_gic.c  @stephanosio
+/drivers/*/intc_vexriscv_litex.c          @mateusz-holenko @kgugala @pgielda
 /drivers/ipm/ipm_mhu*                     @karl-zh
-/drivers/ipm/ipm_stm32_ipcc.c             @arnop2
-/drivers/*/vexriscv_litex.c               @mateusz-holenko @kgugala @pgielda
+/drivers/ipm/Kconfig.nrfx                 @masz-nordic @ioannisg
+/drivers/ipm/Kconfig.nrfx_ipc_channel     @masz-nordic @ioannisg
+/drivers/ipm/ipm_nrfx_ipc.c               @masz-nordic @ioannisg
+/drivers/ipm/ipm_nrfx_ipc.h               @masz-nordic @ioannisg
+/drivers/ipm/ipm_stm32_ipcc.c             @arnopo
 /drivers/led/                             @Mani-Sadhasivam
 /drivers/led_strip/                       @mbolivar
+/drivers/lora/                            @Mani-Sadhasivam
 /drivers/modem/                           @mike-scott
-/drivers/pci/                             @gnuless
-/drivers/pcie/                            @gnuless
+/drivers/pcie/                            @andrewboie
 /drivers/pinmux/stm32/                    @rsalveti @idlethread
+/drivers/pinmux/*hsdk*                    @iriszzw
+/drivers/pwm/*litex*                      @mateusz-holenko @kgugala @pgielda
 /drivers/sensor/                          @MaureenHelm
 /drivers/sensor/ams_iAQcore/              @alexanderwachter
 /drivers/sensor/ens210/                   @alexanderwachter
@@ -149,7 +188,7 @@
 /drivers/sensor/lsm*/                     @avisconti
 /drivers/sensor/st*/                      @avisconti
 /drivers/serial/uart_altera_jtag_hal.c    @wentongwu
-/drivers/serial/*ns16550*                 @gnuless
+/drivers/serial/*ns16550*                 @andrewboie
 /drivers/serial/Kconfig.litex             @mateusz-holenko @kgugala @pgielda
 /drivers/serial/uart_liteuart.c           @mateusz-holenko @kgugala @pgielda
 /drivers/serial/Kconfig.rtt               @carlescufi @pkral78
@@ -158,42 +197,62 @@
 /drivers/serial/uart_xlnx_ps.c            @wjliang
 /drivers/net/                             @jukkar @tbursztyka
 /drivers/ptp_clock/                       @jukkar
+/drivers/pwm/*rv32m1*                     @henrikbrixandersen
+/drivers/pwm/pwm_shell.c                  @henrikbrixandersen
 /drivers/spi/                             @tbursztyka
 /drivers/spi/spi_ll_stm32.*               @superna9999
-/drivers/timer/apic_timer.c               @gnuless
+/drivers/spi/spi_rv32m1_lpspi*            @karstenkoenig
+/drivers/timer/apic_timer.c               @andrewboie
+/drivers/timer/arm_arch_timer.c           @carlocaione
 /drivers/timer/cortex_m_systick.c         @ioannisg
 /drivers/timer/altera_avalon_timer_hal.c  @wentongwu
 /drivers/timer/riscv_machine_timer.c      @nategraff-sifive @kgugala @pgielda
 /drivers/timer/litex_timer.c              @mateusz-holenko @kgugala @pgielda
 /drivers/timer/xlnx_psttc_timer.c         @wjliang
+/drivers/timer/cc13x2_cc26x2_rtc_timer.c  @vanti
 /drivers/usb/                             @jfischer-phytec-iot @finikorg
 /drivers/usb/device/usb_dc_stm32.c        @ydamigos @loicpoulain
+/drivers/video/                           @loicpoulain
 /drivers/i2c/i2c_ll_stm32*                @ldts @ydamigos
 /drivers/i2c/i2c_rv32m1_lpi2c*            @henrikbrixandersen
 /drivers/i2c/*sam0*                       @Sizurka
-/drivers/i2c/i2c_dw*                      @gnuless
+/drivers/i2c/i2c_dw*                      @dcpleung
 /drivers/*/*xec*                          @franciscomunoz @albertofloyd @scottwcpg
+/drivers/watchdog/*gecko*                 @oanerer
+/drivers/watchdog/wdt_handlers.c          @andrewboie
 /drivers/wifi/                            @jukkar @tbursztyka @pfalcon
 /drivers/wifi/eswifi/                     @loicpoulain
 /dts/arc/                                 @vonhust @ruuddw @iriszzw
+/dts/arm/atmel/sam4e*                     @nandojve
 /dts/arm/atmel/samr21.dtsi                @benpicco
+/dts/arm/atmel/sam*5*.dtsi                @benpicco
+/dts/arm/atmel/samv71*                    @nandojve
+/dts/arm/broadcom/                        @sbranden
+/dts/arm/qemu-virt/                       @carlocaione
 /dts/arm/st/                              @erwango
 /dts/arm/ti/cc13?2*                       @bwitherspoon
 /dts/arm/ti/cc26?2*                       @bwitherspoon
+/dts/arm/ti/cc3235*                       @vanti
 /dts/arm/nordic/                          @ioannisg @carlescufi
 /dts/arm/nxp/                             @MaureenHelm
 /dts/arm/microchip/                       @franciscomunoz @albertofloyd @scottwcpg
+/dts/arm/silabs/efm32gg11b*               @oanerer
+/dts/arm/silabs/efm32_jg_pg*              @chrta
+/dts/arm/silabs/efm32jg12b*               @chrta
+/dts/arm/silabs/efm32pg12b*               @chrta
 /dts/riscv/microsemi-miv.dtsi             @galak
 /dts/riscv/rv32m1*                        @MaureenHelm
 /dts/riscv/riscv32-fe310.dtsi             @nategraff-sifive
 /dts/riscv/riscv32-litex-vexriscv.dtsi    @mateusz-holenko @kgugala @pgielda
-/dts/arm/armv7-r.dtsi                     @bbolen
-/dts/arm/xilinx/                          @bbolen
+/dts/arm/armv7-r.dtsi                     @bbolen @stephanosio
+/dts/arm/armv8-a.dtsi                     @carlocaione
+/dts/arm/xilinx/                          @bbolen @stephanosio
 /dts/xtensa/xtensa.dtsi                   @ydamigos
+/dts/xtensa/intel/                        @dcpleung
 /dts/bindings/                            @galak
 /dts/bindings/can/                        @alexanderwachter
 /dts/bindings/iio/adc/st*stm32-adc.yaml   @cybertale
-/dts/bindings/serial/ns16550.yaml         @gnuless
+/dts/bindings/serial/ns16550.yaml         @andrewboie
 /dts/bindings/*/nordic*                   @anangl
 /dts/bindings/*/nxp*                      @MaureenHelm
 /dts/bindings/*/openisa*                  @MaureenHelm
@@ -205,58 +264,63 @@
 /dts/posix/                               @aescolar @vanwinkeljan
 /dts/bindings/sensor/*bme680*             @BoschSensortec
 /dts/bindings/sensor/st*                  @avisconti
-/ext/hal/cmsis/                           @MaureenHelm @galak
+/ext/hal/cmsis/                           @MaureenHelm @galak @stephanosio
 /ext/lib/crypto/tinycrypt/                @ceolin
 /include/                                 @nashif @carlescufi @galak @MaureenHelm
 /include/drivers/adc.h                    @anangl
 /include/drivers/can.h                    @alexanderwachter
 /include/drivers/counter.h                @nordic-krch
 /include/drivers/display.h                @vanwinkeljan
+/include/drivers/espi.h                   @albertofloyd @franciscomunoz @scottwcpg
 /include/drivers/bluetooth/               @joerchan @jhedberg @Vudentz
+/include/drivers/flash.h                  @nashif @carlescufi @galak @MaureenHelm @nvlsianpu
 /include/drivers/led/ht16k33.h            @henrikbrixandersen
-/include/drivers/interrupt_controller/    @andrewboie @gnuless
-/include/drivers/pcie/                    @gnuless
+/include/drivers/interrupt_controller/    @andrewboie
+/include/drivers/interrupt_controller/gic.h @stephanosio
+/include/drivers/pcie/                    @andrewboie
 /include/drivers/hwinfo.h                 @alexanderwachter
 /include/drivers/led.h                    @Mani-Sadhasivam
 /include/drivers/led_strip.h              @mbolivar
 /include/drivers/sensor.h                 @MaureenHelm
 /include/drivers/spi.h                    @tbursztyka
+/include/drivers/lora.h                   @Mani-Sadhasivam
 /include/app_memory/                      @andrewboie
 /include/arch/arc/                        @vonhust @ruuddw
 /include/arch/arc/arch.h                  @andrewboie
 /include/arch/arc/v2/irq.h                @andrewboie
-/include/arch/arm/                        @MaureenHelm @galak @ioannisg
-/include/arch/arm/irq.h                   @andrewboie
+/include/arch/arm/aarch32/                @MaureenHelm @galak @ioannisg
+/include/arch/arm/aarch32/cortex_r/       @stephanosio
+/include/arch/arm/aarch64/                @carlocaione
+/include/arch/arm/aarch32/irq.h           @andrewboie
 /include/arch/nios2/                      @andrewboie
 /include/arch/nios2/arch.h                @andrewboie
 /include/arch/posix/                      @aescolar
 /include/arch/riscv/                      @nategraff-sifive @kgugala @pgielda
 /include/arch/x86/                        @andrewboie @wentongwu
 /include/arch/common/                     @andrewboie @andyross @nashif
-/include/arch/x86/ia32/arch.h             @andrewboie
-/include/arch/x86/multiboot.h             @gnuless
 /include/arch/xtensa/                     @andrewboie
 /include/sys/atomic.h                     @andrewboie @andyross
 /include/bluetooth/                       @joerchan @jhedberg @Vudentz
 /include/cache.h                          @andrewboie @andyross
+/include/canbus/                          @alexanderwachter
+/include/tracing/                         @wentongwu @nashif
+/include/debug/                           @nashif
 /include/device.h                         @wentongwu @nashif
 /include/display/                         @vanwinkeljan
-/include/display/framebuf.h               @gnuless
 /include/dt-bindings/clock/kinetis_mcg.h  @henrikbrixandersen
 /include/dt-bindings/clock/kinetis_scg.h  @henrikbrixandersen
-/include/dt-bindings/pcie/                @gnuless
+/include/dt-bindings/dma/stm32_dma.h      @cybertale
+/include/dt-bindings/pcie/                @andrewboie
 /include/dt-bindings/usb/usb.h            @galak @finikorg
 /include/fs/                              @nashif @wentongwu
 /include/init.h                           @andrewboie @andyross
 /include/irq.h                            @andrewboie @andyross
 /include/irq_offload.h                    @andrewboie @andyross
-/include/espi.h                           @albertofloyd @franciscomunoz @scottwcpg
 /include/kernel.h                         @andrewboie @andyross
 /include/kernel_version.h                 @andrewboie @andyross
 /include/linker/app_smem*.ld              @andrewboie
 /include/linker/                          @andrewboie @andyross
 /include/logging/                         @nordic-krch
-/include/misc/                            @andrewboie @andyross
 /include/net/                             @jukkar @tbursztyka @pfalcon
 /include/net/buf.h                        @jukkar @jhedberg @tbursztyka @pfalcon
 /include/posix/                           @pfalcon
@@ -269,11 +333,9 @@
 /include/sys/sys_io.h                     @andrewboie @andyross
 /include/toolchain.h                      @andrewboie @andyross @nashif
 /include/toolchain/                       @andrewboie @andyross
-/include/updatehub.h                      @chtavares592 @otavio
 /include/zephyr.h                         @andrewboie @andyross
 /kernel/                                  @andrewboie @andyross
 /lib/gui/                                 @vanwinkeljan
-/lib/libc/                                @nashif
 /lib/os/                                  @andrewboie @andyross
 /lib/posix/                               @pfalcon
 /lib/cmsis_rtos_v2/                       @nashif
@@ -285,28 +347,28 @@
 /samples/                                 @nashif
 /samples/basic/minimal/                   @carlescufi
 /samples/basic/servo_motor/*microbit*     @jhe
-/samples/bluetooth/                       @joerchan @jhedberg @Vudentz
 /lib/updatehub/                           @chtavares592 @otavio
-/samples/bluetooth/                       @sjanc @jhedberg @Vudentz
+/samples/bluetooth/                       @jhedberg @Vudentz @joerchan
 /samples/boards/intel_s1000_crb/          @sathishkuttan @dcpleung @nashif
 /samples/display/                         @vanwinkeljan
 /samples/drivers/CAN/                     @alexanderwachter
+/samples/drivers/display/                 @vanwinkeljan
 /samples/drivers/ht16k33/                 @henrikbrixandersen
-/samples/gui/                             @vanwinkeljan
+/samples/drivers/lora/                    @Mani-Sadhasivam
 /samples/net/                             @jukkar @tbursztyka @pfalcon
 /samples/net/dns_resolve/                 @jukkar @tbursztyka @pfalcon
 /samples/net/lwm2m_client/                @mike-scott
 /samples/net/mqtt_publisher/              @jukkar @tbursztyka
 /samples/net/sockets/coap_*/              @rveerama1
 /samples/net/sockets/                     @jukkar @tbursztyka @pfalcon
-/samples/sensor/                          @MaureenHelm
 /samples/net/updatehub/                   @chtavares592 @otavio
-/samples/sensor/                          @bogdan-davidoaia
+/samples/sensor/                          @MaureenHelm
 /samples/shields/                         @avisconti
 /samples/subsys/logging/                  @nordic-krch @jakub-uC
 /samples/subsys/shell/                    @jakub-uC @nordic-krch
 /samples/subsys/usb/                      @jfischer-phytec-iot @finikorg
-/samples/subsys/power/                    @wentongwu @pizi-nordic
+/samples/subsys/power/                    @wentongwu @pabigot
+/samples/userspace/                       @andrewboie
 /scripts/coccicheck                       @himanshujha199640 @JuliaLawall
 /scripts/coccinelle/                      @himanshujha199640 @JuliaLawall
 /scripts/kconfig/                         @ulfalizer
@@ -314,24 +376,31 @@
 /scripts/sanity_chk/expr_parser.py        @nashif
 /scripts/gen_app_partitions.py            @andrewboie
 /scripts/dts/                             @ulfalizer @galak
+/scripts/release/                         @nashif
 /arch/x86/gen_gdt.py                      @andrewboie
 /arch/x86/gen_idt.py                      @andrewboie
 /scripts/gen_kobject_list.py              @andrewboie
 /scripts/gen_priv_stacks.py               @andrewboie @agross-oss @ioannisg
-/scripts/gen_syscall_header.py            @andrewboie
 /scripts/gen_syscalls.py                  @andrewboie
+/scripts/net/                             @jukkar @pfl
 /scripts/process_gperf.py                 @andrewboie
 /scripts/gen_relocate_app.py              @wentongwu
+/scripts/tracing/                         @wentongwu
 /scripts/sanity_chk/                      @nashif
 /scripts/sanitycheck                      @nashif
 /scripts/series-push-hook.sh              @erwango
 /scripts/west_commands/                   @mbolivar
 /scripts/west-commands.yml                @mbolivar
 /scripts/zephyr_module.py                 @tejlmand
+/scripts/valgrind.supp                    @aescolar
 /subsys/bluetooth/                        @joerchan @jhedberg @Vudentz
 /subsys/bluetooth/controller/             @carlescufi @cvinayak @thoh-ot
 /subsys/bluetooth/mesh/                   @jhedberg @trond-snekvik @joerchan @Vudentz
+/subsys/canbus/                           @alexanderwachter
+/subsys/cpp/                              @pabigot @vanwinkeljan
 /subsys/debug/                            @nashif
+/subsys/tracing/                          @nashif @wentongwu
+/subsys/debug/asan_hacks.c                @vanwinkeljan @aescolar
 /subsys/disk/disk_access_spi_sdhc.c       @JunYangNXP
 /subsys/disk/disk_access_sdhc.h           @JunYangNXP
 /subsys/disk/disk_access_usdhc.c          @JunYangNXP
@@ -342,13 +411,14 @@
 /subsys/fs/littlefs_fs.c                  @pabigot
 /subsys/fs/nvs/                           @Laczen
 /subsys/logging/                          @nordic-krch
+/subsys/logging/log_backend_net.c         @nordic-krch @jukkar
 /subsys/mgmt/                             @carlescufi @nvlsianpu
 /subsys/net/buf.c                         @jukkar @jhedberg @tbursztyka @pfalcon
 /subsys/net/ip/                           @jukkar @tbursztyka @pfalcon
 /subsys/net/lib/                          @jukkar @tbursztyka @pfalcon
 /subsys/net/lib/dns/                      @jukkar @tbursztyka @pfalcon
 /subsys/net/lib/lwm2m/                    @mike-scott
-/subsys/net/lib/config/                   @jukkar @tbursztyka
+/subsys/net/lib/config/                   @jukkar @tbursztyka @pfalcon
 /subsys/net/lib/mqtt/                     @jukkar @tbursztyka @rlubos
 /subsys/net/lib/openthread/               @rlubos
 /subsys/net/lib/coap/                     @rveerama1
@@ -356,7 +426,8 @@
 /subsys/net/lib/tls_credentials/          @rlubos
 /subsys/net/l2/                           @jukkar @tbursztyka
 /subsys/net/l2/canbus/                    @alexanderwachter @jukkar
-/subsys/power/                            @wentongwu @pizi-nordic
+/subsys/power/                            @wentongwu @pabigot
+/subsys/random/                           @dleach02
 /subsys/settings/                         @nvlsianpu
 /subsys/shell/                            @jakub-uC @nordic-krch
 /subsys/storage/                          @nvlsianpu
@@ -368,11 +439,13 @@
 /tests/boards/native_posix/               @aescolar
 /tests/boards/intel_s1000_crb/            @dcpleung @sathishkuttan
 /tests/bluetooth/                         @joerchan @jhedberg @Vudentz
+/tests/bluetooth/bsim_bt/                 @joerchan @jhedberg @Vudentz @aescolar
 /tests/posix/                             @pfalcon
 /tests/crypto/                            @ceolin
 /tests/crypto/mbedtls/                    @nashif @ceolin
 /tests/drivers/can/                       @alexanderwachter
 /tests/drivers/flash_simulator/           @nvlsianpu
+/tests/drivers/gpio/                      @mnkp @pabigot
 /tests/drivers/hwinfo/                    @alexanderwachter
 /tests/drivers/spi/                       @tbursztyka
 /tests/drivers/uart/uart_async_api/       @Mierunski
@@ -389,5 +462,5 @@
 /tests/subsys/settings/                   @nvlsianpu
 /tests/subsys/shell/                      @jakub-uC @nordic-krch
 # Get all docs reviewed
-*.rst                                     @dbkinder
-*posix*.rst                               @dbkinder @aescolar
+*.rst                                     @nashif
+*posix*.rst                               @aescolar

Kconfig

@@ -1,10 +1,8 @@
-# Kconfig - general configuration options
+# General configuration options
 
-#
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
-#
 # SPDX-License-Identifier: Apache-2.0
-#
+
 mainmenu "Zephyr Kernel Configuration"
 
 source "Kconfig.zephyr"

Kconfig.zephyr

@@ -1,11 +1,8 @@
-# Kconfig - general configuration options
+# General configuration options
 
-#
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # Copyright (c) 2016 Intel Corporation
-#
 # SPDX-License-Identifier: Apache-2.0
-#
 
 menu "Modules"
 
@@ -14,37 +11,30 @@ source "modules/Kconfig"
 
 endmenu
 
-# Include these first so that any properties (e.g. defaults) below can be
-# overridden in *.defconfig files (by defining symbols in multiple locations).
-# After merging all the symbol definitions, Kconfig picks the first property
-# (e.g. the first default) with a satisfied condition.
+# Include Kconfig.defconfig files first so that they can override defaults and
+# other symbol/choice properties by adding extra symbol/choice definitions.
+# After merging all definitions for a symbol/choice, Kconfig picks the first
+# property (e.g. the first default) with a satisfied condition.
 #
-# Board defaults should be parsed before SoC defaults, because boards usually
-# overrides SoC values.
+# Shield defaults should have precedence over board defaults, which should have
+# precedence over SoC defaults, so include them in that order.
 #
-# Note: $ARCH and $BOARD_DIR might be glob patterns.
+# $ARCH and $BOARD_DIR will be glob patterns when building documentation.
+source "boards/shields/*/Kconfig.defconfig"
 source "$(BOARD_DIR)/Kconfig.defconfig"
-
 source "$(SOC_DIR)/$(ARCH)/*/Kconfig.defconfig"
 
 source "boards/Kconfig"
-
 source "$(SOC_DIR)/Kconfig"
-
 source "arch/Kconfig"
-
 source "kernel/Kconfig"
-
 source "dts/Kconfig"
-
 source "drivers/Kconfig"
-
 source "lib/Kconfig"
-
 source "subsys/Kconfig"
-
 source "ext/Kconfig"
 
+osource "$(TOOLCHAIN_KCONFIG_DIR)/Kconfig"
 
 menu "Build and Link Features"
 
@@ -74,9 +64,9 @@ config LINKER_ORPHAN_SECTION_ERROR
 endchoice
 
 config CODE_DATA_RELOCATION
-       bool "Relocate code/data sections"
-       depends on ARM
-       help
+	bool "Relocate code/data sections"
+	depends on ARM
+	help
 	  When selected this will relocate .text, data and .bss sections from
 	  the specified files and places it in the required memory region. The
 	  files should be specified in the CMakeList.txt file with
@@ -88,17 +78,24 @@ config HAS_FLASH_LOAD_OFFSET
 	  This option is selected by targets having a FLASH_LOAD_OFFSET
 	  and FLASH_LOAD_SIZE.
 
-config USE_CODE_PARTITION
-	bool "link into code-partition"
-	depends on HAS_FLASH_LOAD_OFFSET
+if HAS_FLASH_LOAD_OFFSET
+
+config USE_DT_CODE_PARTITION
+	bool "Link application into /chosen/zephyr,code-partition from devicetree"
 	help
-	  When selected application will be linked into chosen code-partition.
+	  When enabled, the application will be linked into the flash partition
+	  selected by the zephyr,code-partition property in /chosen in devicetree.
+	  When this is disabled, the flash load offset and size can be set manually
+	  below.
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
 
 config FLASH_LOAD_OFFSET
-	hex "Kernel load offset"
-	default $(dt_hex_val,DT_CODE_PARTITION_OFFSET) if USE_CODE_PARTITION
+	# Only user-configurable when USE_DT_CODE_PARTITION is disabled
+	hex "Kernel load offset" if !USE_DT_CODE_PARTITION
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_DT_CODE_PARTITION
 	default 0
-	depends on HAS_FLASH_LOAD_OFFSET
 	help
 	  This option specifies the byte offset from the beginning of flash that
 	  the kernel should be loaded into. Changing this value from zero will
@@ -108,10 +105,10 @@ config FLASH_LOAD_OFFSET
 	  If unsure, leave at the default value 0.
 
 config FLASH_LOAD_SIZE
-	hex "Kernel load size"
-	default $(dt_hex_val,DT_CODE_PARTITION_SIZE) if USE_CODE_PARTITION
+	# Only user-configurable when USE_DT_CODE_PARTITION is disabled
+	hex "Kernel load size" if !USE_DT_CODE_PARTITION
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_DT_CODE_PARTITION
 	default 0
-	depends on HAS_FLASH_LOAD_OFFSET
 	help
 	  If non-zero, this option specifies the size, in bytes, of the flash
 	  area that the Zephyr image will be allowed to occupy.  If zero, the
@@ -120,6 +117,8 @@ config FLASH_LOAD_SIZE
 
 	  If unsure, leave at the default value 0.
 
+endif # HAS_FLASH_LOAD_OFFSET
+
 config TEXT_SECTION_OFFSET
 	hex
 	prompt "TEXT section offset" if !BOOTLOADER_MCUBOOT
@@ -176,12 +175,6 @@ config CUSTOM_SECTIONS_LD
 	  Include a customized linker script fragment for inserting additional
 	  arbitrary sections.
 
-config LINK_WHOLE_ARCHIVE
-	bool "Allow linking with --whole-archive"
-	help
-	  This options allows linking external libraries with the
-	  --whole-archive option to keep all symbols.
-
 config KERNEL_ENTRY
 	string "Kernel entry symbol"
 	default "__start"
@@ -254,6 +247,28 @@ config COMPILER_OPT
 
 endmenu
 
+choice
+	prompt "Error checking behavior for CHECK macro"
+	default RUNTIME_ERROR_CHECKS
+
+config ASSERT_ON_ERRORS
+	bool "Assert on all errors"
+	help
+	  Assert on errors covered with the CHECK macro.
+
+config NO_RUNTIME_CHECKS
+	bool "No runtime error checks"
+	help
+	  Do not do any runtime checks or asserts when using the CHECK macro.
+
+config RUNTIME_ERROR_CHECKS
+	bool "Enable runtime error checks"
+	help
+	  Always perform runtime checks covered with the CHECK macro. This
+	  option is the default and the only option used during testing.
+
+endchoice
+
 menu "Build Options"
 
 config KERNEL_BIN_NAME
@@ -315,7 +330,6 @@ config BUILD_OUTPUT_S19
 
 config BUILD_NO_GAP_FILL
 	bool "Don't fill gaps in generated hex/bin/s19 files."
-	depends on BUILD_OUTPUT_HEX || BUILD_OUTPUT_BIN || BUILD_OUTPUT_S19
 
 config BUILD_OUTPUT_STRIPPED
 	bool "Build a stripped binary"
@@ -329,6 +343,12 @@ config APPLICATION_DEFINED_SYSCALL
 	  Scan additional folders inside application source folder
 	  for application defined syscalls.
 
+config MAKEFILE_EXPORTS
+	bool "Generate build metadata files named Makefile.exports"
+	help
+	  Generates a file with build information that can be read by
+	  third party Makefile-based build systems.
+
 endmenu
 endmenu
 
@@ -357,7 +377,7 @@ config BOOTLOADER_SRAM_SIZE
 
 config BOOTLOADER_MCUBOOT
 	bool "MCUboot bootloader support"
-	select USE_CODE_PARTITION
+	select USE_DT_CODE_PARTITION
 	help
 	  This option signifies that the target uses MCUboot as a bootloader,
 	  or in other words that the image is to be chain-loaded by MCUboot.
@@ -369,8 +389,6 @@ config BOOTLOADER_MCUBOOT
 	      for the MCUboot image header
 	    * Activating SW_VECTOR_RELAY on Cortex-M0 (or Armv8-M baseline)
 	      targets with no built-in vector relocation mechanisms
-	    * Including dts/common/mcuboot.overlay when building the Device
-	      Tree in order to place and link the image at the slot0 offset
 
 config BOOTLOADER_ESP_IDF
 	bool "ESP-IDF bootloader support"
@@ -414,7 +432,6 @@ config MISRA_SANE
 
 endmenu
 
-
 menu "Compatibility"
 
 config COMPAT_INCLUDES

README.rst

@@ -1,4 +1,3 @@
-
 .. raw:: html
 
    <a href="https://www.zephyrproject.org">
@@ -41,6 +40,8 @@ Community Support
 Community support is provided via mailing lists and Slack; see the Resources
 below for details.
 
+.. _project-resources:
+
 Resources
 *********
 

VERSION

@@ -1,5 +1,5 @@
 VERSION_MAJOR = 2
-VERSION_MINOR = 0
+VERSION_MINOR = 2
 PATCHLEVEL = 0
 VERSION_TWEAK = 0
 EXTRAVERSION =

arch/CMakeLists.txt

@@ -2,5 +2,10 @@
 
 add_definitions(-D__ZEPHYR_SUPERVISOR__)
 
+include_directories(
+  ${ZEPHYR_BASE}/kernel/include
+  ${ZEPHYR_BASE}/arch/${ARCH}/include
+  )
+
 add_subdirectory(common)
 add_subdirectory(${ARCH_DIR}/${ARCH} arch/${ARCH})

arch/Kconfig

@@ -1,12 +1,9 @@
-# Kconfig - general architecture configuration options
+# General architecture configuration options
 
-#
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # Copyright (c) 2015 Intel Corporation
 # Copyright (c) 2016 Cadence Design Systems, Inc.
-#
 # SPDX-License-Identifier: Apache-2.0
-#
 
 # Include these first so that any properties (e.g. defaults) below can be
 # overridden (by defining symbols in multiple locations)
@@ -14,52 +11,75 @@
 # Note: $ARCH might be a glob pattern
 source "$(ARCH_DIR)/$(ARCH)/Kconfig"
 
-choice ARCH_CHOICE
-	prompt "Architecture"
-	default X86
+# Architecture symbols
+#
+# Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
+# by SOC_*.
 
 config ARC
-	bool "ARC architecture"
+	bool
+	select ARCH_IS_SET
 	select HAS_DTS
+	help
+	  ARC architecture
 
 config ARM
-	bool "ARM architecture"
+	bool
+	select ARCH_IS_SET
 	select HAS_DTS
+	help
+	  ARM architecture
 
 config X86
-	bool "x86 architecture"
+	bool
+	select ARCH_IS_SET
 	select ATOMIC_OPERATIONS_BUILTIN
 	select HAS_DTS
-
-config X86_64
-	bool "x86_64 architecture"
-	select ATOMIC_OPERATIONS_BUILTIN
-	select SCHED_IPI_SUPPORTED
+	help
+	  x86 architecture
 
 config NIOS2
-	bool "Nios II Gen 2 architecture"
+	bool
+	select ARCH_IS_SET
 	select ATOMIC_OPERATIONS_C
 	select HAS_DTS
+	help
+	  Nios II Gen 2 architecture
 
 config RISCV
-	bool "RISCV architecture"
+	bool
+	select ARCH_IS_SET
 	select HAS_DTS
+	help
+	  RISCV architecture
 
 config XTENSA
-	bool "Xtensa architecture"
+	bool
+	select ARCH_IS_SET
 	select HAS_DTS
+	select USE_SWITCH
+	select USE_SWITCH_SUPPORTED
+	select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
+	help
+	  Xtensa architecture
 
 config ARCH_POSIX
-	bool "POSIX (native) architecture"
+	bool
+	select ARCH_IS_SET
 	select ATOMIC_OPERATIONS_BUILTIN
 	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
 	select ARCH_HAS_CUSTOM_BUSY_WAIT
 	select ARCH_HAS_THREAD_ABORT
 	select NATIVE_APPLICATION
 	select HAS_COVERAGE_SUPPORT
+	help
+	  POSIX (native) architecture
 
-endchoice
-
+config ARCH_IS_SET
+	bool
+	help
+	  Helper symbol to detect SoCs forgetting to select one of the arch
+	  symbols above. See the top-level CMakeLists.txt.
 
 menu "General Architecture Options"
 
@@ -72,15 +92,14 @@ module-str = mpu
 source "subsys/logging/Kconfig.template.log_config"
 
 config BIG_ENDIAN
-       bool
-       help
-         This option tells the build system that the target system is
-         big-endian.  Little-endian architecture is the default and
-         should leave this option unselected.  This option is selected
-         by arch/$ARCH/Kconfig, soc/**/Kconfig, or boards/**/Kconfig
-         and the user should generally avoid modifying it.  The option
-         is used to select linker script OUTPUT_FORMAT and command
-         line option for gen_isr_tables.py.
+	bool
+	help
+	  This option tells the build system that the target system is big-endian.
+	  Little-endian architecture is the default and should leave this option
+	  unselected.  This option is selected by arch/$ARCH/Kconfig,
+	  soc/**/Kconfig, or boards/**/Kconfig and the user should generally avoid
+	  modifying it.  The option is used to select linker script OUTPUT_FORMAT
+	  and command line option for gen_isr_tables.py.
 
 config 64BIT
 	bool
@@ -91,27 +110,33 @@ config 64BIT
 	  soc/**/Kconfig, or boards/**/Kconfig and the user should generally
 	  avoid modifying it.
 
-if ARC || ARM || NIOS2 || X86 || X86_64
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_SRAM := zephyr,sram
 
 config SRAM_SIZE
 	int "SRAM Size in kB"
-	default $(dt_int_val,DT_SRAM_SIZE)
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K)
 	help
-	  This option specifies the size of the SRAM in kB.  It is normally set by
-	  the board's defconfig file and the user should generally avoid modifying
-	  it via the menu configuration.
+	  The SRAM size in kB. The default value comes from /chosen/zephyr,sram in
+	  devicetree. The user should generally avoid changing it via menuconfig or
+	  in configuration files.
 
 config SRAM_BASE_ADDRESS
 	hex "SRAM Base Address"
-	default $(dt_hex_val,DT_SRAM_BASE_ADDRESS)
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))
 	help
-	  This option specifies the base address of the SRAM on the board.  It is
-	  normally set by the board's defconfig file and the user should generally
-	  avoid modifying it via the menu configuration.
+	  The SRAM base address. The default value comes from from
+	  /chosen/zephyr,sram in devicetree. The user should generally avoid
+	  changing it via menuconfig or in configuration files.
+
+if ARC || ARM || NIOS2 || X86
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_FLASH := zephyr,flash
 
 config FLASH_SIZE
 	int "Flash Size in kB"
-	default $(dt_int_val,DT_FLASH_SIZE) if (XIP && ARM) || !ARM
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && ARM) || !ARM
 	help
 	  This option specifies the size of the flash in kB.  It is normally set by
 	  the board's defconfig file and the user should generally avoid modifying
@@ -119,13 +144,13 @@ config FLASH_SIZE
 
 config FLASH_BASE_ADDRESS
 	hex "Flash Base Address"
-	default $(dt_hex_val,DT_FLASH_BASE_ADDRESS) if (XIP && ARM) || !ARM
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && ARM) || !ARM
 	help
 	  This option specifies the base address of the flash on the board. It is
 	  normally set by the board's defconfig file and the user should generally
 	  avoid modifying it via the menu configuration.
 
-endif # ARM || ARC || NIOS2 || X86 || X86_64
+endif # ARM || ARC || NIOS2 || X86
 
 if ARCH_HAS_TRUSTED_EXECUTION
 
@@ -172,6 +197,7 @@ config HW_STACK_PROTECTION
 config USERSPACE
 	bool "User mode threads"
 	depends on ARCH_HAS_USERSPACE
+	depends on RUNTIME_ERROR_CHECKS
 	help
 	  When enabled, threads may be created or dropped down to user mode,
 	  which has significantly restricted permissions and must interact
@@ -217,6 +243,14 @@ config STACK_GROWS_UP
 	  Select this option if the architecture has upward growing thread
 	  stacks. This is not common.
 
+config NO_UNUSED_STACK_INSPECTION
+	bool
+	help
+	  Selected if the architecture will generate a fault if unused stack
+	  memory is examined, which is the region between the current stack
+	  pointer and the deepest available address in the current stack
+	  region.
+
 config MAX_THREAD_BYTES
 	int "Bytes to use when tracking object thread permissions"
 	default 2
@@ -231,31 +265,26 @@ config DYNAMIC_OBJECTS
 	bool "Allow kernel objects to be allocated at runtime"
 	depends on USERSPACE
 	help
-	Enabling this option allows for kernel objects to be requested from
-	the calling thread's resource pool, at a slight cost in performance
-	due to the supplemental run-time tables required to validate such
-	objects.
+	  Enabling this option allows for kernel objects to be requested from
+	  the calling thread's resource pool, at a slight cost in performance
+	  due to the supplemental run-time tables required to validate such
+	  objects.
 
-	Objects allocated in this way can be freed with a supervisor-only
-	API call, or when the number of references to that object drops to
-	zero.
-
-if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
+	  Objects allocated in this way can be freed with a supervisor-only
+	  API call, or when the number of references to that object drops to
+	  zero.
 
 config NOCACHE_MEMORY
 	bool "Support for uncached memory"
+	depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT
 	help
 	  Add a "nocache" read-write memory section that is configured to
 	  not be cached. This memory section can be used to perform DMA
 	  transfers when cache coherence issues are not optimal or can not
 	  be solved using cache maintenance operations.
 
-endif # ARCH_HAS_NOCACHE_MEMORY_SUPPORT
-
 menu "Interrupt Configuration"
-#
-# Interrupt related configs
-#
+
 config DYNAMIC_INTERRUPTS
 	bool "Enable installation of IRQs at runtime"
 	help
@@ -314,12 +343,13 @@ config GEN_IRQ_START_VECTOR
 	  This is a hidden option which needs to be set per architecture and
 	  left alone.
 
-
 config IRQ_OFFLOAD
 	bool "Enable IRQ offload"
+	depends on TEST
 	help
 	  Enable irq_offload() API which allows functions to be synchronously
-	  run in interrupt context. Mainly useful for test cases.
+	  run in interrupt context. Only useful for test cases that need
+	  to validate the correctness of kernel objects in IRQ context.
 
 endmenu # Interrupt configuration
 
@@ -328,6 +358,7 @@ endmenu
 #
 # Architecture Capabilities
 #
+
 config ARCH_HAS_TRUSTED_EXECUTION
 	bool
 
@@ -346,6 +377,9 @@ config ARCH_HAS_NOCACHE_MEMORY_SUPPORT
 config ARCH_HAS_RAMFUNC_SUPPORT
 	bool
 
+config ARCH_HAS_NESTED_EXCEPTION_DETECTION
+	bool
+
 #
 # Other architecture related options
 #
@@ -357,57 +391,51 @@ config ARCH_HAS_THREAD_ABORT
 # Hidden PM feature configs which are to be selected by
 # individual SoC.
 #
+
 config HAS_SYS_POWER_STATE_SLEEP_1
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_SLEEP_1
 	  configuration option.
 
 config HAS_SYS_POWER_STATE_SLEEP_2
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_SLEEP_2
 	  configuration option.
 
 config HAS_SYS_POWER_STATE_SLEEP_3
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_SLEEP_3
 	  configuration option.
 
 config HAS_SYS_POWER_STATE_DEEP_SLEEP_1
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_1
 	  configuration option.
 
 config HAS_SYS_POWER_STATE_DEEP_SLEEP_2
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_2
 	  configuration option.
 
 config HAS_SYS_POWER_STATE_DEEP_SLEEP_3
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_3
 	  configuration option.
 
 config BOOTLOADER_CONTEXT_RESTORE_SUPPORTED
-	# Hidden
 	bool
 	help
 	  This option signifies that the target has options of bootloaders
 	  that support context restore upon resume from deep sleep
 
-
-# End hidden CPU family configs
+#
+# Hidden CPU family configs
 #
 
 config CPU_HAS_TEE
@@ -417,6 +445,12 @@ config CPU_HAS_TEE
 	  Execution Environment (e.g. when it has a security attribution
 	  unit).
 
+config CPU_HAS_DCLS
+	bool
+	help
+	  This option is enabled when the processor hardware is configured in
+	  Dual-redundant Core Lock-step (DCLS) topology.
+
 config CPU_HAS_FPU
 	bool
 	help
@@ -425,13 +459,11 @@ config CPU_HAS_FPU
 
 config CPU_HAS_MPU
 	bool
-	# Omit prompt to signify "hidden" option
 	help
 	  This option is enabled when the CPU has a Memory Protection Unit (MPU).
 
 config MEMORY_PROTECTION
 	bool
-	# Omit prompt to signify "hidden" option
 	help
 	  This option is enabled when Memory Protection features are supported.
 	  Memory protection support is currently available on ARC, ARM, and x86
@@ -439,18 +471,41 @@ config MEMORY_PROTECTION
 
 config MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
 	bool
-	# Omit prompt to signify "hidden" option
 	help
 	  This option is enabled when the MPU requires a power of two alignment
 	  and size for MPU regions.
 
 config MPU_REQUIRES_NON_OVERLAPPING_REGIONS
 	bool
-	# Omit prompt to signify "hidden" option
 	help
 	  This option is enabled when the MPU requires the active (i.e. enabled)
 	  MPU regions to be non-overlapping with each other.
 
+config MPU_GAP_FILLING
+	bool "Force MPU to be filling in background memory regions"
+	depends on MPU_REQUIRES_NON_OVERLAPPING_REGIONS
+	default y if !USERSPACE
+	help
+	  This Kconfig option instructs the MPU driver to enforce
+	  a full kernel SRAM partitioning, when it programs the
+	  dynamic MPU regions (user thread stack, PRIV stack guard
+	  and application memory domains) during context-switch. We
+	  allow this to be a configurable option, in order to be able
+	  to switch the option off and have an increased number of MPU
+	  regions available for application memory domain programming.
+
+	  Notes:
+	  An increased number of MPU regions should only be required,
+	  when building with USERSPACE support. As a result, when we
+	  build without USERSPACE support, gap filling should always
+	  be required.
+
+	  When the option is switched off, access to memory areas not
+	  covered by explicit MPU regions is restricted to privileged
+	  code on an ARCH-specific basis. Refer to ARCH-specific
+	  documentation for more information on how this option is
+	  used.
+
 menuconfig FLOAT
 	bool "Floating point"
 	depends on CPU_HAS_FPU
@@ -462,20 +517,13 @@ menuconfig FLOAT
 	  Disabling this option means that any thread that uses a
 	  floating point register will get a fatal exception.
 
-if FLOAT
-
 config FP_SHARING
 	bool "Floating point register sharing"
+	depends on FLOAT
 	help
 	  This option allows multiple threads to use the floating point
 	  registers.
 
-endif # FLOAT
-
-#
-# End hidden PM feature configs
-#
-
 config ARCH
 	string
 	help

arch/arc/Kconfig

@@ -1,10 +1,7 @@
 # ARC options
 
-#
 # Copyright (c) 2014, 2019 Wind River Systems, Inc.
-#
 # SPDX-License-Identifier: Apache-2.0
-#
 
 menu "ARC Options"
 	depends on ARC
@@ -16,14 +13,14 @@ choice
 	prompt "ARC core family"
 	default CPU_ARCEM
 
-config	CPU_ARCEM
+config CPU_ARCEM
 	bool "ARC EM cores"
 	select CPU_ARCV2
 	select ATOMIC_OPERATIONS_C
 	help
 	  This option signifies the use of an ARC EM CPU
 
-config	CPU_ARCHS
+config CPU_ARCHS
 	bool "ARC HS cores"
 	select CPU_ARCV2
 	select ATOMIC_OPERATIONS_BUILTIN
@@ -32,9 +29,39 @@ config	CPU_ARCHS
 
 endchoice
 
+config CPU_EM4
+	bool
+	help
+	  If y, the SoC uses an ARC EM4 CPU
+
+config CPU_EM4_DMIPS
+	bool
+	help
+	  If y, the SoC uses an ARC EM4 DMIPS CPU
+
+config CPU_EM4_FPUS
+	bool
+	help
+	  If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision
+	  floating-point extension
+
+config CPU_EM4_FPUDA
+	bool
+	help
+	  If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision
+	  floating-point and double assist instructions
+
+config CPU_EM6
+	bool
+	help
+	  If y, the SoC uses an ARC EM6 CPU
+
+config FP_FPU_DA
+	bool
+
 menu "ARCv2 Family Options"
 
-config	CPU_ARCV2
+config CPU_ARCV2
 	bool
 	select ARCH_HAS_STACK_PROTECTION if ARC_HAS_STACK_CHECKING || ARC_MPU
 	select ARCH_HAS_USERSPACE if ARC_MPU
@@ -44,15 +71,7 @@ config	CPU_ARCV2
 	help
 	  This option signifies the use of a CPU of the ARCv2 family.
 
-config	DATA_ENDIANNESS_LITTLE
-	bool
-	default y
-	help
-	  This is driven by the processor implementation, since it is fixed in
-	  hardware. The BSP should set this value to 'n' if the data is
-	  implemented as big endian.
-
-config	NUM_IRQ_PRIO_LEVELS
+config NUM_IRQ_PRIO_LEVELS
 	int "Number of supported interrupt priority levels"
 	range 1 16
 	help
@@ -61,7 +80,7 @@ config	NUM_IRQ_PRIO_LEVELS
 
 	  The BSP must provide a valid default for proper operation.
 
-config	NUM_IRQS
+config NUM_IRQS
 	int "Upper limit of interrupt numbers/IDs used"
 	range 17 256
 	help
@@ -72,7 +91,7 @@ config	NUM_IRQS
 	  The BSP must provide a valid default. This drives the size of the
 	  vector table.
 
-config	RGF_NUM_BANKS
+config RGF_NUM_BANKS
 	int "Number of General Purpose Register Banks"
 	depends on CPU_ARCV2
 	range 1 2
@@ -95,7 +114,21 @@ config ARC_FIRQ
 	  If FIRQ is disabled, the handle of interrupts with highest priority
 	  will be same with other interrupts.
 
-config 	ARC_HAS_STACK_CHECKING
+config ARC_FIRQ_STACK
+	bool "Enable separate firq stack"
+	depends on ARC_FIRQ && RGF_NUM_BANKS > 1
+	help
+	  Use separate stack for FIRQ handing. When the fast irq is also a direct
+	  irq, this will get the minimal interrupt latency.
+
+config ARC_FIRQ_STACK_SIZE
+	int "FIRQ stack size"
+	depends on ARC_FIRQ_STACK
+	default 1024
+	help
+	  The size of firq stack.
+
+config ARC_HAS_STACK_CHECKING
 	bool "ARC has STACK_CHECKING"
 	default y
 	help
@@ -103,19 +136,20 @@ config 	ARC_HAS_STACK_CHECKING
 	  checking stack accesses and raising an exception when a stack
 	  overflow or underflow is detected.
 
-config	ARC_CONNECT
+config ARC_CONNECT
 	bool "ARC has ARC connect"
 	select SCHED_IPI_SUPPORTED
 	help
 	  ARC is configured with ARC CONNECT which is a hardware for connecting
 	  multi cores.
 
-config  ARC_STACK_CHECKING
+config ARC_STACK_CHECKING
 	bool
+	select NO_UNUSED_STACK_INSPECTION
 	help
 	  Use ARC STACK_CHECKING to do stack protection
 
-config	ARC_STACK_PROTECTION
+config ARC_STACK_PROTECTION
 	bool
 	default y if HW_STACK_PROTECTION
 	select ARC_STACK_CHECKING if ARC_HAS_STACK_CHECKING
@@ -131,9 +165,8 @@ config	ARC_STACK_PROTECTION
 	  selection of the ARC stack checking is
 	  prioritized over the MPU-based stack guard.
 
-config	ARC_USE_UNALIGNED_MEM_ACCESS
+config ARC_USE_UNALIGNED_MEM_ACCESS
 	bool "Enable unaligned access in HW"
-	default n if CPU_ARCEM
 	default y if CPU_ARCHS
 	depends on (CPU_ARCEM && !ARC_HAS_SECURE) || CPU_ARCHS
 	help
@@ -141,7 +174,7 @@ config	ARC_USE_UNALIGNED_MEM_ACCESS
 	  to support unaligned memory access which is then disabled by default.
 	  Enable unaligned access in hardware and make software to use it.
 
-config	FAULT_DUMP
+config FAULT_DUMP
 	int "Fault dump level"
 	default 2
 	range 0 2
@@ -156,7 +189,7 @@ config	FAULT_DUMP
 
 	  0: Off.
 
-config	XIP
+config XIP
 	default y if !UART_NSIM
 
 config GEN_ISR_TABLES
@@ -201,8 +234,7 @@ config SJLI_TABLE_SIZE
 	  sjli instruction.
 
 config ARC_SECURE_FIRMWARE
-	prompt "Generate Secure Firmware"
-	bool
+	bool "Generate Secure Firmware"
 	depends on ARC_HAS_SECURE
 	default y if TRUSTED_EXECUTION_SECURE
 	help
@@ -218,8 +250,7 @@ config ARC_SECURE_FIRMWARE
 	  and normal resources of the ARC processors.
 
 config ARC_NORMAL_FIRMWARE
-	prompt "Generate Normal Firmware"
-	bool
+	bool "Generate Normal Firmware"
 	depends on !ARC_SECURE_FIRMWARE
 	depends on ARC_HAS_SECURE
 	default y if TRUSTED_EXECUTION_NONSECURE
@@ -280,6 +311,15 @@ config CACHE_FLUSHING
 	  If the d-cache is present, set this to y.
 	  If the d-cache is NOT present, set this to n.
 
+config ARC_EXCEPTION_STACK_SIZE
+	int "ARC exception handling stack size"
+	default 768
+	help
+	  Size in bytes of exception handling stack which is at the top of
+	  interrupt stack to get smaller memory footprint because exception
+	  is not frequent. To reduce the impact on interrupt handling,
+	  especially nested interrupt, it cannot be too large.
+
 endmenu
 
 config ARC_EXCEPTION_DEBUG

arch/arc/core/CMakeLists.txt

@@ -3,28 +3,32 @@
 zephyr_library()
 
 zephyr_library_sources(
-	thread.c
-	thread_entry_wrapper.S
-	cpu_idle.S
-	fatal.c
-	fault.c
-	fault_s.S
-	irq_manage.c
-	timestamp.c
-	isr_wrapper.S
-	regular_irq.S
-	switch.S
-	prep_c.c
-	reset.S
-	vector_table.c
-	)
+  thread.c
+  thread_entry_wrapper.S
+  cpu_idle.S
+  fatal.c
+  fault.c
+  fault_s.S
+  irq_manage.c
+  timestamp.c
+  isr_wrapper.S
+  regular_irq.S
+  switch.S
+  prep_c.c
+  reset.S
+  vector_table.c
+  )
 
 zephyr_library_sources_ifdef(CONFIG_CACHE_FLUSHING cache.c)
 zephyr_library_sources_ifdef(CONFIG_ARC_FIRQ fast_irq.S)
 
 zephyr_library_sources_if_kconfig(irq_offload.c)
-add_subdirectory_ifdef(CONFIG_ARC_CORE_MPU mpu)
-add_subdirectory_ifdef(CONFIG_ARC_SECURE_FIRMWARE secureshield)
+
 zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
 zephyr_library_sources_ifdef(CONFIG_ARC_CONNECT arc_connect.c)
-zephyr_library_sources_ifdef(CONFIG_SMP arc_smp.c)
+zephyr_library_sources_ifdef(CONFIG_ARC_CONNECT arc_smp.c)
+
+add_subdirectory_ifdef(CONFIG_ARC_CORE_MPU mpu)
+add_subdirectory_ifdef(CONFIG_ARC_SECURE_FIRMWARE secureshield)
+
+zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)

arch/arc/core/arc_connect.c

@@ -223,7 +223,7 @@ u64_t z_arc_connect_gfrc_read(void)
 	 * sub-components. For GFRC, HW allows simultaneously accessing to
 	 * counters. So an irq lock is enough.
 	 */
-	key = z_arch_irq_lock();
+	key = arch_irq_lock();
 
 	z_arc_connect_cmd(ARC_CONNECT_CMD_GFRC_READ_LO, 0);
 	low = z_arc_connect_cmd_readback();
@@ -231,7 +231,7 @@ u64_t z_arc_connect_gfrc_read(void)
 	z_arc_connect_cmd(ARC_CONNECT_CMD_GFRC_READ_HI, 0);
 	high = z_arc_connect_cmd_readback();
 
-	z_arch_irq_unlock(key);
+	arch_irq_unlock(key);
 
 	return (((u64_t)high) << 32) | low;
 }
@@ -349,7 +349,7 @@ u32_t z_arc_connect_idu_read_mode(u32_t irq_num)
 void z_arc_connect_idu_set_dest(u32_t irq_num, u32_t core_mask)
 {
 	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_IDU_SET_MODE,
+		z_arc_connect_cmd_data(ARC_CONNECT_CMD_IDU_SET_DEST,
 			irq_num, core_mask);
 	}
 }

arch/arc/core/arc_smp.c

@@ -6,7 +6,7 @@
 
 /**
  * @file
- * @brief codes required for ARC smp support
+ * @brief codes required for ARC multicore and Zephyr smp support
  *
  */
 #include <device.h>
@@ -23,6 +23,70 @@
 
 #define ARCV2_ICI_IRQ_PRIORITY 1
 
+volatile struct {
+	arch_cpustart_t fn;
+	void *arg;
+} arc_cpu_init[CONFIG_MP_NUM_CPUS];
+
+/*
+ * arc_cpu_wake_flag is used to sync up master core and slave cores
+ * Slave core will spin for arc_cpu_wake_flag until master core sets
+ * it to the core id of slave core. Then, slave core clears it to notify
+ * master core that it's waken
+ *
+ */
+volatile u32_t arc_cpu_wake_flag;
+
+volatile char *arc_cpu_sp;
+/*
+ * _curr_cpu is used to record the struct of _cpu_t of each cpu.
+ * for efficient usage in assembly
+ */
+volatile _cpu_t *_curr_cpu[CONFIG_MP_NUM_CPUS];
+
+/* Called from Zephyr initialization */
+void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
+		    arch_cpustart_t fn, void *arg)
+{
+	_curr_cpu[cpu_num] = &(_kernel.cpus[cpu_num]);
+	arc_cpu_init[cpu_num].fn = fn;
+	arc_cpu_init[cpu_num].arg = arg;
+
+	/* set the initial sp of target sp through arc_cpu_sp
+	 * arc_cpu_wake_flag will protect arc_cpu_sp that
+	 * only one slave cpu can read it per time
+	 */
+	arc_cpu_sp = Z_THREAD_STACK_BUFFER(stack) + sz;
+
+	arc_cpu_wake_flag = cpu_num;
+
+	/* wait slave cpu to start */
+	while (arc_cpu_wake_flag != 0) {
+		;
+	}
+}
+
+/* the C entry of slave cores */
+void z_arc_slave_start(int cpu_num)
+{
+	arch_cpustart_t fn;
+
+#ifdef CONFIG_SMP
+	z_icache_setup();
+	z_irq_setup();
+
+	z_arc_connect_ici_clear();
+	z_irq_priority_set(IRQ_ICI, ARCV2_ICI_IRQ_PRIORITY, 0);
+	irq_enable(IRQ_ICI);
+#endif
+	/* call the function set by arch_start_cpu */
+	fn = arc_cpu_init[cpu_num].fn;
+
+	fn(arc_cpu_init[cpu_num].arg);
+}
+
+#ifdef CONFIG_SMP
+
 static void sched_ipi_handler(void *unused)
 {
 	ARG_UNUSED(unused);
@@ -38,89 +102,36 @@ static void sched_ipi_handler(void *unused)
  *  use register r0 and register r1 as return value, r0 has
  *  new thread, r1 has old thread. If r0 == 0, it means no thread switch.
  */
-u64_t z_arch_smp_switch_in_isr(void)
+u64_t z_arc_smp_switch_in_isr(void)
 {
 	u64_t ret = 0;
 	u32_t new_thread;
 	u32_t old_thread;
 
-	if (!_current_cpu->swap_ok) {
-		return 0;
-	}
-
 	old_thread = (u32_t)_current;
 
 	new_thread = (u32_t)z_get_next_ready_thread();
 
 	if (new_thread != old_thread) {
+#ifdef CONFIG_TIMESLICING
+		z_reset_time_slice();
+#endif
 		_current_cpu->swap_ok = 0;
 		((struct k_thread *)new_thread)->base.cpu =
-				z_arch_curr_cpu()->id;
-		_current = (struct k_thread *) new_thread;
+				arch_curr_cpu()->id;
+		_current_cpu->current = (struct k_thread *) new_thread;
 		ret = new_thread | ((u64_t)(old_thread) << 32);
 	}
 
 	return ret;
 }
 
-volatile struct {
-	void (*fn)(int, void*);
-	void *arg;
-} arc_cpu_init[CONFIG_MP_NUM_CPUS];
-
-/*
- * arc_cpu_wake_flag is used to sync up master core and slave cores
- * Slave core will spin for arc_cpu_wake_flag until master core sets
- * it to the core id of slave core. Then, slave core clears it to notify
- * master core that it's waken
- *
- */
-volatile u32_t arc_cpu_wake_flag;
-/*
- * _curr_cpu is used to record the struct of _cpu_t of each cpu.
- * for efficient usage in assembly
- */
-volatile _cpu_t *_curr_cpu[CONFIG_MP_NUM_CPUS];
-
-/* Called from Zephyr initialization */
-void z_arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
-		     void (*fn)(int, void *), void *arg)
-{
-	_curr_cpu[cpu_num] = &(_kernel.cpus[cpu_num]);
-	arc_cpu_init[cpu_num].fn = fn;
-	arc_cpu_init[cpu_num].arg = arg;
-
-	arc_cpu_wake_flag = cpu_num;
-
-	/* wait slave cpu to start */
-	while (arc_cpu_wake_flag != 0) {
-		;
-	}
-}
-
-/* the C entry of slave cores */
-void z_arch_slave_start(int cpu_num)
-{
-	void (*fn)(int, void*);
-
-	z_icache_setup();
-	z_irq_setup();
-
-	z_irq_priority_set(IRQ_ICI, ARCV2_ICI_IRQ_PRIORITY, 0);
-	irq_enable(IRQ_ICI);
-
-	/* call the function set by z_arch_start_cpu */
-	fn = arc_cpu_init[cpu_num].fn;
-
-	fn(cpu_num, arc_cpu_init[cpu_num].arg);
-}
-
 /* arch implementation of sched_ipi */
-void z_arch_sched_ipi(void)
+void arch_sched_ipi(void)
 {
 	u32_t i;
 
-	/* broadcast sched_ipi request to all cores
+	/* broadcast sched_ipi request to other cores
 	 * if the target is current core, hardware will ignore it
 	 */
 	for (i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
@@ -143,6 +154,7 @@ static int arc_smp_init(struct device *dev)
 
 	if (bcr.ipi) {
 	/* register ici interrupt, just need master core to register once */
+		z_arc_connect_ici_clear();
 		IRQ_CONNECT(IRQ_ICI, ARCV2_ICI_IRQ_PRIORITY,
 		    sched_ipi_handler, NULL, 0);
 
@@ -170,3 +182,4 @@ static int arc_smp_init(struct device *dev)
 }
 
 SYS_INIT(arc_smp_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+#endif

arch/arc/core/cpu_idle.S

@@ -17,11 +17,11 @@
 #include <linker/sections.h>
 #include <arch/cpu.h>
 
-GTEXT(k_cpu_idle)
-GTEXT(k_cpu_atomic_idle)
-GDATA(k_cpu_sleep_mode)
+GTEXT(arch_cpu_idle)
+GTEXT(arch_cpu_atomic_idle)
+GDATA(z_arc_cpu_sleep_mode)
 
-SECTION_VAR(BSS, k_cpu_sleep_mode)
+SECTION_VAR(BSS, z_arc_cpu_sleep_mode)
 	.balign 4
 	.word 0
 
@@ -33,17 +33,29 @@ SECTION_VAR(BSS, k_cpu_sleep_mode)
  * void nanCpuIdle(void)
  */
 
-SECTION_FUNC(TEXT, k_cpu_idle)
+SECTION_FUNC(TEXT, arch_cpu_idle)
 
 #ifdef CONFIG_TRACING
 	push_s blink
-	jl    z_sys_trace_idle
+	jl    sys_trace_idle
 	pop_s blink
 #endif
 
-	ld r1, [k_cpu_sleep_mode]
+	ld r1, [z_arc_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
+/*
+ * It's found that (in nsim_hs_smp), when cpu
+ * is sleeping, no response to inter-processor interrupt
+ * although it's pending and interrupts are enabled.
+ * here is a workround
+ */
+#if !defined(CONFIG_SOC_NSIM) && !defined(CONFIG_SMP)
 	sleep r1
+#else
+	seti r1
+_z_arc_idle_loop:
+	b _z_arc_idle_loop
+#endif
 	j_s [blink]
 	nop
 
@@ -52,17 +64,17 @@ SECTION_FUNC(TEXT, k_cpu_idle)
  *
  * This function exits with interrupts restored to <key>.
  *
- * void k_cpu_atomic_idle(unsigned int key)
+ * void arch_cpu_atomic_idle(unsigned int key)
  */
-SECTION_FUNC(TEXT, k_cpu_atomic_idle)
+SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
 
 #ifdef CONFIG_TRACING
 	push_s blink
-	jl    z_sys_trace_idle
+	jl    sys_trace_idle
 	pop_s blink
 #endif
 
-	ld r1, [k_cpu_sleep_mode]
+	ld r1, [z_arc_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
 	j_s.d [blink]

arch/arc/core/fast_irq.S

@@ -16,6 +16,7 @@
 #include <kernel_structs.h>
 #include <offsets_short.h>
 #include <toolchain.h>
+#include <linker/sections.h>
 #include <arch/cpu.h>
 #include <swap_macros.h>
 
@@ -80,7 +81,7 @@ SECTION_FUNC(TEXT, _firq_enter)
 	_check_and_inc_int_nest_counter r0, r1
 
 	bne.d firq_nest
-	mov r0, sp
+	mov_s r0, sp
 
 	_get_curr_cpu_irq_stack sp
 #if CONFIG_RGF_NUM_BANKS != 1
@@ -101,20 +102,25 @@ firq_nest:
 	 * save original value of _ARC_V2_USER_SP and ilink into
 	 * the stack of interrupted context first, then restore them later
 	 */
-	st ilink, [sp]
-	lr ilink, [_ARC_V2_USER_SP]
-	st ilink, [sp, -4]
+	push ilink
+	PUSHAX ilink, _ARC_V2_USER_SP
+
 	/* sp here is the sp of interrupted context */
 	sr sp, [_ARC_V2_USER_SP]
+	/* here, bank 0 sp must go back to the value before push and
+	 * PUSHAX as we will switch to bank1, the pop and POPAX later will
+	 * change bank1's sp, not bank0's sp
+	 */
+	add sp, sp, 8
 
 	/* switch back to banked reg, only ilink can be used */
 	lr ilink, [_ARC_V2_STATUS32]
 	or ilink, ilink, _ARC_V2_STATUS32_RB(1)
 	kflag ilink
 	lr sp, [_ARC_V2_USER_SP]
-	ld ilink, [sp, -4]
-	sr ilink, [_ARC_V2_USER_SP]
-	ld ilink, [sp]
+
+	POPAX ilink, _ARC_V2_USER_SP
+	pop ilink
 firq_nest_1:
 #else
 firq_nest:
@@ -149,10 +155,8 @@ SECTION_FUNC(TEXT, _firq_exit)
 	bl z_check_stack_sentinel
 #endif
 
-#ifdef CONFIG_PREEMPT_ENABLED
-
 #ifdef CONFIG_SMP
-	bl z_arch_smp_switch_in_isr
+	bl z_arc_smp_switch_in_isr
 	/* r0 points to new thread, r1 points to old thread */
 	brne r0, 0, _firq_reschedule
 #else
@@ -165,8 +169,6 @@ SECTION_FUNC(TEXT, _firq_exit)
 #endif
 	/* fall to no rescheduling */
 
-#endif /* CONFIG_PREEMPT_ENABLED */
-
 .balign 4
 _firq_no_reschedule:
 	pop sp
@@ -180,8 +182,6 @@ _firq_no_reschedule:
 #endif
 	rtie
 
-#ifdef CONFIG_PREEMPT_ENABLED
-
 .balign 4
 _firq_reschedule:
 	pop sp
@@ -201,12 +201,36 @@ _firq_reschedule:
 	 * point, so when switching back to register bank 0, it will contain the
 	 * registers from the interrupted thread.
 	 */
-
+#if defined(CONFIG_USERSPACE)
+/* when USERSPACE is configured, here need to consider the case where firq comes
+ * out in user mode, according to ARCv2 ISA and nsim, the following micro ops
+ * will be executed:
+ *	sp<-reg bank1'sp
+ *      switch between sp and _ARC_V2_USER_SP
+ * then:
+ *      sp is the sp of kernel stack of interrupted thread
+ *      _ARC_V2_USER_SP is reg bank1'sp
+ *      the sp of user stack of interrupted thread is reg bank0'sp
+ * if firq comes out in kernel mode, the following micro ops will be executed:
+ *      sp<-reg bank'sp
+ * so, sw needs to do necessary handling to set up the correct sp
+ */
+	lr r0, [_ARC_V2_AUX_IRQ_ACT]
+	bbit0 r0, 31, _firq_from_kernel
+	aex sp, [_ARC_V2_USER_SP]
+	lr r0, [_ARC_V2_STATUS32]
+	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
+	kflag r0
+	aex sp, [_ARC_V2_USER_SP]
+	b _firq_create_irq_stack_frame
+_firq_from_kernel:
+#endif
 	/* chose register bank #0 */
 	lr r0, [_ARC_V2_STATUS32]
 	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
 	kflag r0
 
+_firq_create_irq_stack_frame:
 	/* we're back on the outgoing thread's stack */
 	_create_irq_stack_frame
 
@@ -219,6 +243,7 @@ _firq_reschedule:
 	st_s r0, [sp, ___isf_t_status32_OFFSET]
 
 	st ilink, [sp, ___isf_t_pc_OFFSET] /* ilink into pc */
+
 #ifdef CONFIG_SMP
 /*
  * load r0, r1 from irq stack
@@ -229,8 +254,18 @@ _firq_reschedule:
 #endif
 #endif
 
+#if defined(CONFIG_USERSPACE)
+/*
+ * need to remember the user/kernel status of interrupted thread, will be
+ * restored when thread switched back
+ */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	and r3, r3, 0x80000000
+	push_s r3
+#endif
+
 #ifdef CONFIG_SMP
-	mov r2, r1
+	mov_s r2, r1
 #else
 	mov_s r1, _kernel
 	ld_s r2, [r1, _kernel_offset_to_current]
@@ -240,7 +275,7 @@ _firq_reschedule:
 	st _CAUSE_FIRQ, [r2, _thread_offset_to_relinquish_cause]
 
 #ifdef CONFIG_SMP
-	mov r2, r0
+	mov_s r2, r0
 #else
 	ld_s r2, [r1, _kernel_offset_to_ready_q_cache]
 	st_s r2, [r1, _kernel_offset_to_current]
@@ -257,7 +292,7 @@ _firq_reschedule:
 
 #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
 	push_s r2
-	mov r0, r2
+	mov_s r0, r2
 	bl configure_mpu_thread
 	pop_s r2
 #endif
@@ -273,9 +308,9 @@ _firq_reschedule:
 	ld r3, [r2, _thread_offset_to_relinquish_cause]
 
 	breq r3, _CAUSE_RIRQ, _firq_return_from_rirq
-	nop
+	nop_s
 	breq r3, _CAUSE_FIRQ, _firq_return_from_firq
-	nop
+	nop_s
 
 	/* fall through */
 
@@ -283,7 +318,7 @@ _firq_reschedule:
 _firq_return_from_coop:
 	/* pc into ilink */
 	pop_s r0
-	mov ilink, r0
+	mov_s ilink, r0
 
 	pop_s r0 /* status32 into r0 */
 	sr r0, [_ARC_V2_STATUS32_P0]
@@ -294,6 +329,16 @@ _firq_return_from_coop:
 _firq_return_from_rirq:
 _firq_return_from_firq:
 
+#if defined(CONFIG_USERSPACE)
+/*
+ * need to recover the user/kernel status of interrupted thread
+ */
+	pop_s r3
+	lr r2, [_ARC_V2_AUX_IRQ_ACT]
+	or r2, r2, r3
+	sr r2, [_ARC_V2_AUX_IRQ_ACT]
+#endif
+
 	_pop_irq_stack_frame
 
 	ld ilink, [sp, -4] /* status32 into ilink */
@@ -302,5 +347,3 @@ _firq_return_from_firq:
 
 	/* LP registers are already restored, just switch back to bank 0 */
 	rtie
-
-#endif /* CONFIG_PREEMPT_ENABLED */

arch/arc/core/fatal.c

@@ -12,24 +12,33 @@
  * ARCv2 CPUs.
  */
 
-#include <kernel_structs.h>
+#include <kernel.h>
 #include <offsets_short.h>
-#include <toolchain.h>
 #include <arch/cpu.h>
-#include <logging/log_ctrl.h>
+#include <logging/log.h>
+LOG_MODULE_DECLARE(os);
 
 void z_arc_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
 {
 	if (reason == K_ERR_CPU_EXCEPTION) {
-		z_fatal_print("Faulting instruction address = 0x%lx",
-			      z_arc_v2_aux_reg_read(_ARC_V2_ERET));
+		LOG_ERR("Faulting instruction address = 0x%lx",
+			z_arc_v2_aux_reg_read(_ARC_V2_ERET));
 	}
 
 	z_fatal_error(reason, esf);
 }
 
-FUNC_NORETURN void z_arch_syscall_oops(void *ssf_ptr)
+FUNC_NORETURN void arch_syscall_oops(void *ssf_ptr)
 {
 	z_arc_fatal_error(K_ERR_KERNEL_OOPS, ssf_ptr);
 	CODE_UNREACHABLE;
 }
+
+FUNC_NORETURN void arch_system_halt(unsigned int reason)
+{
+	ARG_UNUSED(reason);
+
+	__asm__("brk");
+
+	CODE_UNREACHABLE;
+}

arch/arc/core/fault.c

@@ -16,16 +16,17 @@
 #include <inttypes.h>
 
 #include <kernel.h>
+#include <kernel_internal.h>
 #include <kernel_structs.h>
 #include <exc_handle.h>
-#include <logging/log_ctrl.h>
-
+#include <logging/log.h>
+LOG_MODULE_DECLARE(os);
 
 #ifdef CONFIG_USERSPACE
-Z_EXC_DECLARE(z_arch_user_string_nlen);
+Z_EXC_DECLARE(z_arc_user_string_nlen);
 
 static const struct z_exc_handle exceptions[] = {
-	Z_EXC_HANDLE(z_arch_user_string_nlen)
+	Z_EXC_HANDLE(z_arc_user_string_nlen)
 };
 #endif
 
@@ -154,32 +155,32 @@ static void dump_protv_exception(u32_t cause, u32_t parameter)
 {
 	switch (cause) {
 	case 0x0:
-		z_fatal_print("Instruction fetch violation (%s)",
-			      get_protv_access_err(parameter));
+		LOG_ERR("Instruction fetch violation (%s)",
+			get_protv_access_err(parameter));
 		break;
 	case 0x1:
-		z_fatal_print("Memory read protection violation (%s)",
-			      get_protv_access_err(parameter));
+		LOG_ERR("Memory read protection violation (%s)",
+			get_protv_access_err(parameter));
 		break;
 	case 0x2:
-		z_fatal_print("Memory write protection violation (%s)",
-			      get_protv_access_err(parameter));
+		LOG_ERR("Memory write protection violation (%s)",
+			get_protv_access_err(parameter));
 		break;
 	case 0x3:
-		z_fatal_print("Memory read-modify-write violation (%s)",
-			      get_protv_access_err(parameter));
+		LOG_ERR("Memory read-modify-write violation (%s)",
+			get_protv_access_err(parameter));
 		break;
 	case 0x10:
-		z_fatal_print("Normal vector table in secure memory");
+		LOG_ERR("Normal vector table in secure memory");
 		break;
 	case 0x11:
-		z_fatal_print("NS handler code located in S memory");
+		LOG_ERR("NS handler code located in S memory");
 		break;
 	case 0x12:
-		z_fatal_print("NSC Table Range Violation");
+		LOG_ERR("NSC Table Range Violation");
 		break;
 	default:
-		z_fatal_print("unknown");
+		LOG_ERR("unknown");
 		break;
 	}
 }
@@ -188,46 +189,46 @@ static void dump_machine_check_exception(u32_t cause, u32_t parameter)
 {
 	switch (cause) {
 	case 0x0:
-		z_fatal_print("double fault");
+		LOG_ERR("double fault");
 		break;
 	case 0x1:
-		z_fatal_print("overlapping TLB entries");
+		LOG_ERR("overlapping TLB entries");
 		break;
 	case 0x2:
-		z_fatal_print("fatal TLB error");
+		LOG_ERR("fatal TLB error");
 		break;
 	case 0x3:
-		z_fatal_print("fatal cache error");
+		LOG_ERR("fatal cache error");
 		break;
 	case 0x4:
-		z_fatal_print("internal memory error on instruction fetch");
+		LOG_ERR("internal memory error on instruction fetch");
 		break;
 	case 0x5:
-		z_fatal_print("internal memory error on data fetch");
+		LOG_ERR("internal memory error on data fetch");
 		break;
 	case 0x6:
-		z_fatal_print("illegal overlapping MPU entries");
+		LOG_ERR("illegal overlapping MPU entries");
 		if (parameter == 0x1) {
-			z_fatal_print(" - jump and branch target");
+			LOG_ERR(" - jump and branch target");
 		}
 		break;
 	case 0x10:
-		z_fatal_print("secure vector table not located in secure memory");
+		LOG_ERR("secure vector table not located in secure memory");
 		break;
 	case 0x11:
-		z_fatal_print("NSC jump table not located in secure memory");
+		LOG_ERR("NSC jump table not located in secure memory");
 		break;
 	case 0x12:
-		z_fatal_print("secure handler code not located in secure memory");
+		LOG_ERR("secure handler code not located in secure memory");
 		break;
 	case 0x13:
-		z_fatal_print("NSC target address not located in secure memory");
+		LOG_ERR("NSC target address not located in secure memory");
 		break;
 	case 0x80:
-		z_fatal_print("uncorrectable ECC or parity error in vector memory");
+		LOG_ERR("uncorrectable ECC or parity error in vector memory");
 		break;
 	default:
-		z_fatal_print("unknown");
+		LOG_ERR("unknown");
 		break;
 	}
 }
@@ -236,54 +237,54 @@ static void dump_privilege_exception(u32_t cause, u32_t parameter)
 {
 	switch (cause) {
 	case 0x0:
-		z_fatal_print("Privilege violation");
+		LOG_ERR("Privilege violation");
 		break;
 	case 0x1:
-		z_fatal_print("disabled extension");
+		LOG_ERR("disabled extension");
 		break;
 	case 0x2:
-		z_fatal_print("action point hit");
+		LOG_ERR("action point hit");
 		break;
 	case 0x10:
 		switch (parameter) {
 		case 0x1:
-			z_fatal_print("N to S return using incorrect return mechanism");
+			LOG_ERR("N to S return using incorrect return mechanism");
 			break;
 		case 0x2:
-			z_fatal_print("N to S return with incorrect operating mode");
+			LOG_ERR("N to S return with incorrect operating mode");
 			break;
 		case 0x3:
-			z_fatal_print("IRQ/exception return fetch from wrong mode");
+			LOG_ERR("IRQ/exception return fetch from wrong mode");
 			break;
 		case 0x4:
-			z_fatal_print("attempt to halt secure processor in NS mode");
+			LOG_ERR("attempt to halt secure processor in NS mode");
 			break;
 		case 0x20:
-			z_fatal_print("attempt to access secure resource from normal mode");
+			LOG_ERR("attempt to access secure resource from normal mode");
 			break;
 		case 0x40:
-			z_fatal_print("SID violation on resource access (APEX/UAUX/key NVM)");
+			LOG_ERR("SID violation on resource access (APEX/UAUX/key NVM)");
 			break;
 		default:
-			z_fatal_print("unknown");
+			LOG_ERR("unknown");
 			break;
 		}
 		break;
 	case 0x13:
 		switch (parameter) {
 		case 0x20:
-			z_fatal_print("attempt to access secure APEX feature from NS mode");
+			LOG_ERR("attempt to access secure APEX feature from NS mode");
 			break;
 		case 0x40:
-			z_fatal_print("SID violation on access to APEX feature");
+			LOG_ERR("SID violation on access to APEX feature");
 			break;
 		default:
-			z_fatal_print("unknown");
+			LOG_ERR("unknown");
 			break;
 		}
 		break;
 	default:
-		z_fatal_print("unknown");
+		LOG_ERR("unknown");
 		break;
 	}
 }
@@ -291,7 +292,7 @@ static void dump_privilege_exception(u32_t cause, u32_t parameter)
 static void dump_exception_info(u32_t vector, u32_t cause, u32_t parameter)
 {
 	if (vector >= 0x10 && vector <= 0xFF) {
-		z_fatal_print("interrupt %u", vector);
+		LOG_ERR("interrupt %u", vector);
 		return;
 	}
 
@@ -300,55 +301,55 @@ static void dump_exception_info(u32_t vector, u32_t cause, u32_t parameter)
 	 */
 	switch (vector) {
 	case ARC_EV_RESET:
-		z_fatal_print("Reset");
+		LOG_ERR("Reset");
 		break;
 	case ARC_EV_MEM_ERROR:
-		z_fatal_print("Memory Error");
+		LOG_ERR("Memory Error");
 		break;
 	case ARC_EV_INS_ERROR:
-		z_fatal_print("Instruction Error");
+		LOG_ERR("Instruction Error");
 		break;
 	case ARC_EV_MACHINE_CHECK:
-		z_fatal_print("EV_MachineCheck");
+		LOG_ERR("EV_MachineCheck");
 		dump_machine_check_exception(cause, parameter);
 		break;
 	case ARC_EV_TLB_MISS_I:
-		z_fatal_print("EV_TLBMissI");
+		LOG_ERR("EV_TLBMissI");
 		break;
 	case ARC_EV_TLB_MISS_D:
-		z_fatal_print("EV_TLBMissD");
+		LOG_ERR("EV_TLBMissD");
 		break;
 	case ARC_EV_PROT_V:
-		z_fatal_print("EV_ProtV");
+		LOG_ERR("EV_ProtV");
 		dump_protv_exception(cause, parameter);
 		break;
 	case ARC_EV_PRIVILEGE_V:
-		z_fatal_print("EV_PrivilegeV");
+		LOG_ERR("EV_PrivilegeV");
 		dump_privilege_exception(cause, parameter);
 		break;
 	case ARC_EV_SWI:
-		z_fatal_print("EV_SWI");
+		LOG_ERR("EV_SWI");
 		break;
 	case ARC_EV_TRAP:
-		z_fatal_print("EV_Trap");
+		LOG_ERR("EV_Trap");
 		break;
 	case ARC_EV_EXTENSION:
-		z_fatal_print("EV_Extension");
+		LOG_ERR("EV_Extension");
 		break;
 	case ARC_EV_DIV_ZERO:
-		z_fatal_print("EV_DivZero");
+		LOG_ERR("EV_DivZero");
 		break;
 	case ARC_EV_DC_ERROR:
-		z_fatal_print("EV_DCError");
+		LOG_ERR("EV_DCError");
 		break;
 	case ARC_EV_MISALIGNED:
-		z_fatal_print("EV_Misaligned");
+		LOG_ERR("EV_Misaligned");
 		break;
 	case ARC_EV_VEC_UNIT:
-		z_fatal_print("EV_VecUnit");
+		LOG_ERR("EV_VecUnit");
 		break;
 	default:
-		z_fatal_print("unknown");
+		LOG_ERR("unknown");
 		break;
 	}
 }
@@ -401,9 +402,9 @@ void _Fault(z_arch_esf_t *esf, u32_t old_sp)
 		return;
 	}
 
-	z_fatal_print("***** Exception vector: 0x%x, cause code: 0x%x, parameter 0x%x",
-	       vector, cause, parameter);
-	z_fatal_print("Address 0x%x", exc_addr);
+	LOG_ERR("***** Exception vector: 0x%x, cause code: 0x%x, parameter 0x%x",
+		vector, cause, parameter);
+	LOG_ERR("Address 0x%x", exc_addr);
 #ifdef CONFIG_ARC_EXCEPTION_DEBUG
 	dump_exception_info(vector, cause, parameter);
 #endif

arch/arc/core/fault_s.S

@@ -38,8 +38,17 @@ GTEXT(__ev_maligned)
 GTEXT(z_irq_do_offload);
 #endif
 
-/* the necessary stack size for exception handling */
-#define EXCEPTION_STACK_SIZE 384
+
+/*
+ * The exception handling will use top part of interrupt stack to
+ * get smaller memory footprint, because exception is not frequent.
+ * To reduce the impact on interrupt handling, especially nested interrupt
+ * the top part of interrupt stack cannot be too large, so add a check
+ * here
+ */
+#if CONFIG_ARC_EXCEPTION_STACK_SIZE > (CONFIG_ISR_STACK_SIZE >> 1)
+#error "interrupt stack size is too small"
+#endif
 
 /*
  * @brief Fault handler installed in the fault and reserved vectors
@@ -65,9 +74,9 @@ _exc_entry:
 	 * and exception is raised, then here it's guaranteed that
 	 * exception handling has necessary stack to use
 	 */
-	mov ilink, sp
+	mov_s ilink, sp
 	_get_curr_cpu_irq_stack sp
-	sub sp, sp, (CONFIG_ISR_STACK_SIZE - EXCEPTION_STACK_SIZE)
+	sub sp, sp, (CONFIG_ISR_STACK_SIZE - CONFIG_ARC_EXCEPTION_STACK_SIZE)
 
 	/*
 	 * save caller saved registers
@@ -91,9 +100,9 @@ _exc_entry:
 	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
 
 	/* sp is parameter of _Fault */
-	mov r0, sp
+	mov_s r0, sp
 	/* ilink is the thread's original sp */
-	mov r1, ilink
+	mov_s r1, ilink
 	jl _Fault
 
 _exc_return:
@@ -105,11 +114,10 @@ _exc_return:
  * exception comes out,  thread context?irq_context?nest irq context?
  */
 
-#ifdef CONFIG_PREEMPT_ENABLED
 #ifdef CONFIG_SMP
-	bl z_arch_smp_switch_in_isr
+	bl z_arc_smp_switch_in_isr
 	breq r0, 0, _exc_return_from_exc
-	mov r2, r0
+	mov_s r2, r0
 #else
 	mov_s r1, _kernel
 	ld_s r2, [r1, _kernel_offset_to_current]
@@ -143,7 +151,7 @@ _exc_return:
 	/* save r2 in ilink because of the possible following reg
 	 * bank switch
 	 */
-	mov ilink, r2
+	mov_s ilink, r2
 #endif
 	lr r3, [_ARC_V2_STATUS32]
 	and r3,r3,(~(_ARC_V2_STATUS32_AE | _ARC_V2_STATUS32_RB(7)))
@@ -156,18 +164,18 @@ _exc_return:
 	 */
 
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
-	mov r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
+	mov_s r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
 #else
-	mov r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
+	mov_s r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
 #endif
 
 #ifdef CONFIG_ARC_NORMAL_FIRMWARE
-	push r2
-	mov r0, _ARC_V2_AUX_IRQ_ACT
-	mov r1, r3
-	mov r6, ARC_S_CALL_AUX_WRITE
+	push_s r2
+	mov_s r0, _ARC_V2_AUX_IRQ_ACT
+	mov_s r1, r3
+	mov_s r6, ARC_S_CALL_AUX_WRITE
 	sjli SJLI_CALL_ARC_SECURE
-	pop r2
+	pop_s r2
 #else
 	sr r3, [_ARC_V2_AUX_IRQ_ACT]
 #endif
@@ -178,14 +186,13 @@ _exc_return:
 
 	/* Assumption: r2 has current thread */
 	b _rirq_common_interrupt_swap
-#endif
 
 _exc_return_from_exc:
 	ld_s r0, [sp, ___isf_t_pc_OFFSET]
 	sr r0, [_ARC_V2_ERET]
 
 	_pop_irq_stack_frame
-	mov sp, ilink
+	mov_s sp, ilink
 	rtie
 
 
@@ -196,30 +203,36 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 #ifdef CONFIG_USERSPACE
 	cmp ilink, _TRAP_S_CALL_SYSTEM_CALL
 	bne _do_non_syscall_trap
-/* do sys_call */
-	mov ilink, K_SYSCALL_LIMIT
+	/* do sys_call */
+	mov_s ilink, K_SYSCALL_LIMIT
 	cmp r6, ilink
-	blt valid_syscall_id
+	blo valid_syscall_id
 
-	mov r0, r6
-	mov r6, K_SYSCALL_BAD
+	mov_s r0, r6
+	mov_s r6, K_SYSCALL_BAD
 
 valid_syscall_id:
+	/* create a sys call frame
+	 * caller regs (r0 - 12) are saved in _create_irq_stack_frame
+	 * ok to use them later
+	 */
+	_create_irq_stack_frame
+
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
-	lr ilink, [_ARC_V2_ERSEC_STAT]
-	push ilink
+	/* ERSEC_STAT is IOW/RAZ in normal mode */
+	lr r0, [_ARC_V2_ERSEC_STAT]
+	st_s r0, [sp, ___isf_t_sec_stat_OFFSET]
 #endif
-	lr ilink, [_ARC_V2_ERET]
-	push ilink
-	lr ilink, [_ARC_V2_ERSTATUS]
-	push ilink
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, ___isf_t_status32_OFFSET]
 
+	bclr r0, r0, _ARC_V2_STATUS32_U_BIT
+	sr r0, [_ARC_V2_ERSTATUS]
 
-	bclr ilink, ilink, _ARC_V2_STATUS32_U_BIT
-	sr ilink, [_ARC_V2_ERSTATUS]
-
-	mov ilink, _arc_do_syscall
-	sr ilink, [_ARC_V2_ERET]
+	mov_s r0, _arc_do_syscall
+	sr r0, [_ARC_V2_ERET]
 
 	rtie
 
@@ -250,7 +263,7 @@ _do_non_syscall_trap:
 	_check_and_inc_int_nest_counter r0, r1
 
 	bne.d exc_nest_handle
-	mov r0, sp
+	mov_s r0, sp
 
 	_get_curr_cpu_irq_stack sp
 exc_nest_handle:
@@ -262,83 +275,6 @@ exc_nest_handle:
 
 	_dec_int_nest_counter r0, r1
 
-	lr  r0, [_ARC_V2_AUX_IRQ_ACT]
-	and r0, r0, 0xffff
-	cmp r0, 0
-	bne _exc_return_from_exc
-
-#ifdef CONFIG_PREEMPT_ENABLED
-#ifdef CONFIG_SMP
-	bl z_arch_smp_switch_in_isr
-	breq r0, 0, _exc_return_from_irqoffload_trap
-	mov r2, r1
-
-	_save_callee_saved_regs
-
-	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
-	mov r2, r0
-#else
-	mov_s r1, _kernel
-	ld_s r2, [r1, _kernel_offset_to_current]
-
-	/* check if the current thread needs to be rescheduled */
-	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
-	breq r0, r2, _exc_return_from_irqoffload_trap
-#endif
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	/*
-	 * sync up the ERSEC_STAT.ERM and SEC_STAT.IRM.
-	 * use a fake interrupt return to simulate an exception turn.
-	 * ERM and IRM record which mode the cpu should return, 1: secure
-	 * 0: normal
-	 */
-	lr r3,[_ARC_V2_ERSEC_STAT]
-	btst r3, 31
-	bset.nz r3, r3, _ARC_V2_SEC_STAT_IRM_BIT
-	bclr.z r3, r3, _ARC_V2_SEC_STAT_IRM_BIT
-	sflag r3
-	/* save  _ARC_V2_SEC_STAT */
-	and r3, r3, 0xff
-	push r3
-#endif
-
-	_save_callee_saved_regs
-
-	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
-	/* note: Ok to use _CAUSE_RIRQ since everything is saved */
-
-	mov r2, r0
-#ifndef CONFIG_SMP
-	st_s r2, [r1, _kernel_offset_to_current]
-#endif
-	/* clear AE bit to forget this was an exception */
-	lr r3, [_ARC_V2_STATUS32]
-	and r3,r3,(~_ARC_V2_STATUS32_AE)
-	kflag r3
-	/* pretend lowest priority interrupt happened to use common handler */
-	lr r3, [_ARC_V2_AUX_IRQ_ACT]
-
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	or r3, r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
-#else
-	or r3, r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
-#endif
-
-#ifdef CONFIG_ARC_NORMAL_FIRMWARE
-	push_s r2
-	mov r0, _ARC_V2_AUX_IRQ_ACT
-	mov r1, r3
-	mov r6, ARC_S_CALL_AUX_WRITE
-	sjli SJLI_CALL_ARC_SECURE
-	pop_s r2
-#else
-	sr r3, [_ARC_V2_AUX_IRQ_ACT]
-#endif
-	/* Assumption: r2 has current thread */
-	b _rirq_common_interrupt_swap
-#endif
-
-_exc_return_from_irqoffload_trap:
 	_pop_irq_stack_frame
 	rtie
 #endif /* CONFIG_IRQ_OFFLOAD */

arch/arc/core/irq_manage.c

@@ -26,6 +26,63 @@
 #include <irq.h>
 #include <sys/printk.h>
 
+
+/*
+ * storage space for the interrupt stack of fast_irq
+ */
+#if defined(CONFIG_ARC_FIRQ_STACK)
+#if defined(CONFIG_SMP)
+K_THREAD_STACK_ARRAY_DEFINE(_firq_interrupt_stack, CONFIG_MP_NUM_CPUS,
+			    CONFIG_ARC_FIRQ_STACK_SIZE);
+#else
+K_THREAD_STACK_DEFINE(_firq_interrupt_stack, CONFIG_ARC_FIRQ_STACK_SIZE);
+#endif
+
+/*
+ * @brief Set the stack pointer for firq handling
+ *
+ * @return N/A
+ */
+void z_arc_firq_stack_set(void)
+{
+#ifdef CONFIG_SMP
+	char *firq_sp = Z_THREAD_STACK_BUFFER(
+		  _firq_interrupt_stack[z_arc_v2_core_id()]) +
+		  CONFIG_ARC_FIRQ_STACK_SIZE;
+#else
+	char *firq_sp = Z_THREAD_STACK_BUFFER(_firq_interrupt_stack) +
+		  CONFIG_ARC_FIRQ_STACK_SIZE;
+#endif
+
+/* the z_arc_firq_stack_set must be called when irq diasbled, as
+ * it can be called not only in the init phase but also other places
+ */
+	unsigned int key = irq_lock();
+
+	__asm__ volatile (
+/* only ilink will not be banked, so use ilink as channel
+ * between 2 banks
+ */
+	"mov ilink, %0		\n\t"
+	"lr %0, [%1]		\n\t"
+	"or %0, %0, %2		\n\t"
+	"kflag %0		\n\t"
+	"mov sp, ilink		\n\t"
+/* switch back to bank0, use ilink to avoid the pollution of
+ * bank1's gp regs.
+ */
+	"lr ilink, [%1]		\n\t"
+	"and ilink, ilink, %3	\n\t"
+	"kflag ilink		\n\t"
+	:
+	: "r"(firq_sp), "i"(_ARC_V2_STATUS32),
+	  "i"(_ARC_V2_STATUS32_RB(1)),
+	  "i"(~_ARC_V2_STATUS32_RB(7))
+	);
+	irq_unlock(key);
+}
+#endif
+
 /*
  * @brief Enable an interrupt line
  *
@@ -36,7 +93,7 @@
  * @return N/A
  */
 
-void z_arch_irq_enable(unsigned int irq)
+void arch_irq_enable(unsigned int irq)
 {
 	unsigned int key = irq_lock();
 
@@ -53,7 +110,7 @@ void z_arch_irq_enable(unsigned int irq)
  * @return N/A
  */
 
-void z_arch_irq_disable(unsigned int irq)
+void arch_irq_disable(unsigned int irq)
 {
 	unsigned int key = irq_lock();
 
@@ -61,6 +118,17 @@ void z_arch_irq_disable(unsigned int irq)
 	irq_unlock(key);
 }
 
+/**
+ * @brief Return IRQ enable state
+ *
+ * @param irq IRQ line
+ * @return interrupt enable state, true or false
+ */
+int arch_irq_is_enabled(unsigned int irq)
+{
+	return z_arc_v2_irq_unit_int_enabled(irq);
+}
+
 /*
  * @internal
  *
@@ -113,9 +181,9 @@ void z_irq_spurious(void *unused)
 }
 
 #ifdef CONFIG_DYNAMIC_INTERRUPTS
-int z_arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
-			      void (*routine)(void *parameter), void *parameter,
-			      u32_t flags)
+int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
+			     void (*routine)(void *parameter), void *parameter,
+			     u32_t flags)
 {
 	z_isr_install(irq, routine, parameter);
 	z_irq_priority_set(irq, priority, flags);

arch/arc/core/irq_offload.c

@@ -20,11 +20,9 @@ void z_irq_do_offload(void)
 	offload_routine(offload_param);
 }
 
-void irq_offload(irq_offload_routine_t routine, void *parameter)
+void arch_irq_offload(irq_offload_routine_t routine, void *parameter)
 {
-	unsigned int key;
 
-	key = irq_lock();
 	offload_routine = routine;
 	offload_param = parameter;
 
@@ -32,6 +30,4 @@ void irq_offload(irq_offload_routine_t routine, void *parameter)
 		:
 		: [id] "i"(_TRAP_S_SCALL_IRQ_OFFLOAD) : );
 
-	irq_unlock(key);
 }
-

arch/arc/core/isr_wrapper.S

@@ -68,7 +68,7 @@ The context switch code adopts this standard so that it is easier to follow:
     transition from outgoing thread to incoming thread
 
 Not loading _kernel into r0 allows loading _kernel without stomping on
-the parameter in r0 in z_arch_switch().
+the parameter in r0 in arch_switch().
 
 
 ARCv2 processors have two kinds of interrupts: fast (FIRQ) and regular. The
@@ -168,7 +168,7 @@ From FIRQ:
 
   o to coop
 
-    The address of the returning instruction from z_arch_switch() is loaded
+    The address of the returning instruction from arch_switch() is loaded
     in ilink and the saved status32 in status32_p0.
 
   o to any irq
@@ -209,27 +209,27 @@ SECTION_FUNC(TEXT, _isr_wrapper)
  * in fact is an action like nop.
  * for firq,  r0 will be restored later
  */
-  st r0, [sp]
+	st_s r0, [sp]
 #endif
 	lr r0, [_ARC_V2_AUX_IRQ_ACT]
 	ffs r0, r0
 	cmp r0, 0
 #if CONFIG_RGF_NUM_BANKS == 1
 	bnz rirq_path
-  ld r0, [sp]
+	ld_s r0, [sp]
 	/* 1-register bank FIRQ handling must save registers on stack */
 	_create_irq_stack_frame
 	lr r0, [_ARC_V2_STATUS32_P0]
 	st_s r0, [sp, ___isf_t_status32_OFFSET]
-  lr r0, [_ARC_V2_ERET]
+	lr r0, [_ARC_V2_ERET]
 	st_s r0, [sp, ___isf_t_pc_OFFSET]
 
-	mov r3, _firq_exit
-	mov r2, _firq_enter
+	mov_s r3, _firq_exit
+	mov_s r2, _firq_enter
 	j_s [r2]
 rirq_path:
-	mov r3, _rirq_exit
-	mov r2, _rirq_enter
+	mov_s r3, _rirq_exit
+	mov_s r2, _rirq_enter
 	j_s [r2]
 #else
 	mov.z r3, _firq_exit
@@ -239,25 +239,13 @@ rirq_path:
 	j_s [r2]
 #endif
 #else
-	mov r3, _rirq_exit
-	mov r2, _rirq_enter
+	mov_s r3, _rirq_exit
+	mov_s r2, _rirq_enter
 	j_s [r2]
 #endif
 
 #if defined(CONFIG_TRACING)
-GTEXT(z_sys_trace_isr_enter)
-
-.macro log_interrupt_k_event
-	clri r0 /* do not interrupt event logger operations */
-	push_s r0
-	push_s blink
-	jl z_sys_trace_isr_enter
-	pop_s blink
-	pop_s r0
-	seti r0
-.endm
-#else
-	#define log_interrupt_k_event
+GTEXT(sys_trace_isr_enter)
 #endif
 
 #if defined(CONFIG_SYS_POWER_MANAGEMENT)
@@ -303,7 +291,6 @@ SECTION_FUNC(TEXT, _isr_demux)
 	/* cannot be done before this point because we must be able to run C */
 	/* r0 is available to be stomped here, and exit_tickless_idle uses it */
 	exit_tickless_idle
-	log_interrupt_k_event
 
 	lr r0, [_ARC_V2_ICAUSE]
 	/* handle software triggered interrupt */
@@ -314,7 +301,7 @@ irq_hint_handled:
 
 	sub r0, r0, 16
 
-	mov r1, _sw_isr_table
+	mov_s r1, _sw_isr_table
 	add3 r0, r1, r0   /* table entries are 8-bytes wide */
 
 	ld_s r1, [r0, 4] /* ISR into r1 */
@@ -339,4 +326,4 @@ irq_hint_handled:
 	/* back from ISR, jump to exit stub */
 	pop_s r3
 	j_s [r3]
-	nop
+	nop_s

arch/arc/core/mpu/Kconfig

@@ -1,10 +1,8 @@
-# Kconfig - Memory Protection Unit (MPU) configuration options
+# Memory Protection Unit (MPU) configuration options
 
-#
 # Copyright (c) 2017 Synopsys
-#
 # SPDX-License-Identifier: Apache-2.0
-#
+
 config ARC_MPU_VER
 	int "ARC MPU version"
 	range 2 4

arch/arc/core/mpu/arc_core_mpu.c

@@ -27,7 +27,7 @@ void configure_mpu_thread(struct k_thread *thread)
 
 #if defined(CONFIG_USERSPACE)
 
-int z_arch_mem_domain_max_partitions_get(void)
+int arch_mem_domain_max_partitions_get(void)
 {
 	return arc_core_mpu_get_max_domain_partition_regions();
 }
@@ -35,8 +35,8 @@ int z_arch_mem_domain_max_partitions_get(void)
 /*
  * Reset MPU region for a single memory partition
  */
-void z_arch_mem_domain_partition_remove(struct k_mem_domain *domain,
-				       u32_t partition_id)
+void arch_mem_domain_partition_remove(struct k_mem_domain *domain,
+				      u32_t partition_id)
 {
 	if (_current->mem_domain_info.mem_domain != domain) {
 		return;
@@ -50,7 +50,7 @@ void z_arch_mem_domain_partition_remove(struct k_mem_domain *domain,
 /*
  * Configure MPU memory domain
  */
-void z_arch_mem_domain_thread_add(struct k_thread *thread)
+void arch_mem_domain_thread_add(struct k_thread *thread)
 {
 	if (_current != thread) {
 		return;
@@ -64,7 +64,7 @@ void z_arch_mem_domain_thread_add(struct k_thread *thread)
 /*
  * Destroy MPU regions for the mem domain
  */
-void z_arch_mem_domain_destroy(struct k_mem_domain *domain)
+void arch_mem_domain_destroy(struct k_mem_domain *domain)
 {
 	if (_current->mem_domain_info.mem_domain != domain) {
 		return;
@@ -75,25 +75,25 @@ void z_arch_mem_domain_destroy(struct k_mem_domain *domain)
 	arc_core_mpu_enable();
 }
 
-void z_arch_mem_domain_partition_add(struct k_mem_domain *domain,
-				    u32_t partition_id)
+void arch_mem_domain_partition_add(struct k_mem_domain *domain,
+				   u32_t partition_id)
 {
 	/* No-op on this architecture */
 }
 
-void z_arch_mem_domain_thread_remove(struct k_thread *thread)
+void arch_mem_domain_thread_remove(struct k_thread *thread)
 {
 	if (_current != thread) {
 		return;
 	}
 
-	z_arch_mem_domain_destroy(thread->mem_domain_info.mem_domain);
+	arch_mem_domain_destroy(thread->mem_domain_info.mem_domain);
 }
 
 /*
  * Validate the given buffer is user accessible or not
  */
-int z_arch_buffer_validate(void *addr, size_t size, int write)
+int arch_buffer_validate(void *addr, size_t size, int write)
 {
 	return arc_core_mpu_buffer_validate(addr, size, write);
 }

arch/arc/core/mpu/arc_mpu_v3_internal.h

@@ -656,7 +656,7 @@ int arc_core_mpu_get_max_domain_partition_regions(void)
 int arc_core_mpu_buffer_validate(void *addr, size_t size, int write)
 {
 	int r_index;
-
+	int key = arch_irq_lock();
 
 	/*
 	 * For ARC MPU v3, overlapping is not supported.
@@ -667,13 +667,17 @@ int arc_core_mpu_buffer_validate(void *addr, size_t size, int write)
 	/*  match and the area is in one region */
 	if (r_index >= 0 && r_index == _mpu_probe((u32_t)addr + (size - 1))) {
 		if (_is_user_accessible_region(r_index, write)) {
-			return 0;
+			r_index = 0;
 		} else {
-			return -EPERM;
+			r_index = -EPERM;
 		}
+	} else {
+		r_index = -EPERM;
 	}
 
-	return -EPERM;
+	arch_irq_unlock(key);
+
+	return r_index;
 }
 #endif /* CONFIG_USERSPACE */
 
@@ -711,9 +715,9 @@ static int arc_mpu_init(struct device *arg)
 
 		/* record the static region which can be split */
 		if (mpu_config.mpu_regions[i].attr & REGION_DYNAMIC) {
-			if (dynamic_regions_num >
+			if (dynamic_regions_num >=
 			MPU_DYNAMIC_REGION_AREAS_NUM) {
-				LOG_ERR("no enough dynamic regions %d",
+				LOG_ERR("not enough dynamic regions %d",
 				 dynamic_regions_num);
 				return -EINVAL;
 			}

arch/arc/core/offsets/offsets.c

@@ -22,8 +22,9 @@
  * completeness.
  */
 
+#include <kernel.h>
+#include <kernel_arch_data.h>
 #include <gen_offset.h>
-#include <kernel_structs.h>
 #include <kernel_offsets.h>
 
 GEN_OFFSET_SYM(_thread_arch_t, relinquish_cause);

arch/arc/core/regular_irq.S

@@ -17,6 +17,7 @@
 #include <kernel_structs.h>
 #include <offsets_short.h>
 #include <toolchain.h>
+#include <linker/sections.h>
 #include <arch/cpu.h>
 #include <swap_macros.h>
 
@@ -63,7 +64,7 @@ PRE-CONTEXT-SWITCH STACK
 
          --------------------------------------
   SP ->  | Return address; PC (Program Counter), in fact value taken from
-         | BLINK register in z_arch_switch()
+         | BLINK register in arch_switch()
          --------------------------------------
          | STATUS32 value, we explicitly save it here for later usage, read-on
          --------------------------------------
@@ -233,7 +234,7 @@ SECTION_FUNC(TEXT, _rirq_enter)
 	_check_and_inc_int_nest_counter r0, r1
 
 	bne.d rirq_nest
-	mov r0, sp
+	mov_s r0, sp
 
 	_get_curr_cpu_irq_stack sp
 rirq_nest:
@@ -265,16 +266,14 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	bl z_check_stack_sentinel
 #endif
 
-#ifdef CONFIG_PREEMPT_ENABLED
-
 #ifdef CONFIG_SMP
-	bl z_arch_smp_switch_in_isr
+	bl z_arc_smp_switch_in_isr
 	/* r0 points to new thread, r1 points to old thread */
-	cmp r0, 0
+	cmp_s r0, 0
 	beq _rirq_no_reschedule
-	mov r2, r1
+	mov_s r2, r1
 #else
-	mov r1, _kernel
+	mov_s r1, _kernel
 	ld_s r2, [r1, _kernel_offset_to_current]
 
 	/*
@@ -300,7 +299,16 @@ _rirq_reschedule:
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	/* here need to remember SEC_STAT.IRM bit */
 	lr r3, [_ARC_V2_SEC_STAT]
-	push r3
+	push_s r3
+#endif
+
+#if defined(CONFIG_USERSPACE)
+/*
+ * need to remember the user/kernel status of interrupted thread
+ */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	and r3, r3, 0x80000000
+	push_s r3
 #endif
 	/* _save_callee_saved_regs expects outgoing thread in r2 */
 	_save_callee_saved_regs
@@ -308,10 +316,10 @@ _rirq_reschedule:
 	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
 
 #ifdef CONFIG_SMP
-	mov r2, r0
+	mov_s r2, r0
 #else
 	/* incoming thread is in r0: it becomes the new 'current' */
-	mov r2, r0
+	mov_s r2, r0
 	st_s r2, [r1, _kernel_offset_to_current]
 #endif
 
@@ -330,7 +338,7 @@ _rirq_common_interrupt_swap:
 
 #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
 	push_s r2
-	mov r0, r2
+	mov_s r0, r2
 	bl configure_mpu_thread
 	pop_s r2
 #endif
@@ -354,9 +362,9 @@ _rirq_common_interrupt_swap:
 	ld r3, [r2, _thread_offset_to_relinquish_cause]
 
 	breq r3, _CAUSE_RIRQ, _rirq_return_from_rirq
-	nop
+	nop_s
 	breq r3, _CAUSE_FIRQ, _rirq_return_from_firq
-	nop
+	nop_s
 
 	/* fall through */
 
@@ -394,14 +402,21 @@ _rirq_return_from_coop:
 	/* rtie will pop the rest from the stack */
 	rtie
 
-#endif /* CONFIG_PREEMPT_ENABLED */
-
 .balign 4
 _rirq_return_from_firq:
 _rirq_return_from_rirq:
+#if defined(CONFIG_USERSPACE)
+/*
+ * need to recover the user/kernel status of interrupted thread
+ */
+	pop_s r3
+	lr r2, [_ARC_V2_AUX_IRQ_ACT]
+	or r2, r2, r3
+	sr r2, [_ARC_V2_AUX_IRQ_ACT]
+#endif
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	/* here need to recover SEC_STAT.IRM bit */
-	pop r3
+	pop_s r3
 	sflag r3
 #endif
 _rirq_no_reschedule:

arch/arc/core/reset.S

@@ -17,7 +17,7 @@
 #include <swap_macros.h>
 
 GDATA(_interrupt_stack)
-GDATA(_main_stack)
+GDATA(z_main_stack)
 GDATA(_VectorTable)
 
 /* use one of the available interrupt stacks during init */
@@ -48,7 +48,7 @@ SECTION_FUNC(TEXT,__start)
 	/* lock interrupts: will get unlocked when switch to main task
 	 * also make sure the processor in the correct status
 	 */
-	mov r0, 0
+	mov_s r0, 0
 	kflag r0
 
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
@@ -60,9 +60,9 @@ SECTION_FUNC(TEXT,__start)
 	 * ARCV2 timer (timer0) is a free run timer, let it start to count
 	 * here.
 	 */
-	mov r0, 0xffffffff
+	mov_s r0, 0xffffffff
 	sr r0, [_ARC_V2_TMR0_LIMIT]
-	mov r0, 0
+	mov_s r0, 0
 	sr r0, [_ARC_V2_TMR0_COUNT]
 #endif
 	/* interrupt related init */
@@ -76,7 +76,7 @@ SECTION_FUNC(TEXT,__start)
 	/* set the vector table base early,
 	 * so that exception vectors can be handled.
 	 */
-	mov r0, _VectorTable
+	mov_s r0, _VectorTable
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	sr r0, [_ARC_V2_IRQ_VECT_BASE_S]
 #else
@@ -95,7 +95,7 @@ SECTION_FUNC(TEXT,__start)
 	kflag r0
 #endif
 
-	mov r1, 1
+	mov_s r1, 1
 
 invalidate_and_disable_icache:
 
@@ -106,9 +106,9 @@ invalidate_and_disable_icache:
 	mov_s r2, 0
 	sr r2, [_ARC_V2_IC_IVIC]
 	/* writing to IC_IVIC needs 3 NOPs */
-	nop
-	nop
-	nop
+	nop_s
+	nop_s
+	nop_s
 	sr r1, [_ARC_V2_IC_CTRL]
 
 invalidate_dcache:
@@ -126,7 +126,7 @@ done_cache_invalidate:
         jl @_sys_resume_from_deep_sleep
 #endif
 
-#ifdef CONFIG_SMP
+#if CONFIG_MP_NUM_CPUS  > 1
 	_get_cpu_id r0
 	breq r0, 0, _master_core_startup
 
@@ -137,13 +137,14 @@ _slave_core_wait:
 	ld r1, [arc_cpu_wake_flag]
 	brne r0, r1, _slave_core_wait
 
+	ld sp, [arc_cpu_sp]
 	/* signal master core that slave core runs */
 	st 0, [arc_cpu_wake_flag]
 
-	/* get sp set by master core */
-	_get_curr_cpu_irq_stack sp
-
-	j z_arch_slave_start
+#if defined(CONFIG_ARC_FIRQ_STACK)
+	jl z_arc_firq_stack_set
+#endif
+	j z_arc_slave_start
 
 _master_core_startup:
 #endif
@@ -154,7 +155,7 @@ _master_core_startup:
 	 * FIRQ stack when CONFIG_INIT_STACKS is enabled before switching to
 	 * one of them for the rest of the early boot
 	 */
-	mov sp, _main_stack
+	mov_s sp, z_main_stack
 	add sp, sp, CONFIG_MAIN_STACK_SIZE
 
 	mov_s r0, _interrupt_stack
@@ -164,7 +165,11 @@ _master_core_startup:
 
 #endif /* CONFIG_INIT_STACKS */
 
-	mov sp, INIT_STACK
+	mov_s sp, INIT_STACK
 	add sp, sp, INIT_STACK_SIZE
 
+#if defined(CONFIG_ARC_FIRQ_STACK)
+	jl z_arc_firq_stack_set
+#endif
+
 	j @_PrepC

arch/arc/core/secureshield/CMakeLists.txt

@@ -6,7 +6,7 @@
 zephyr_library()
 
 zephyr_library_sources(
-	arc_sjli.c
-	arc_secure.S
-	secure_sys_services.c
-)
+  arc_sjli.c
+  arc_secure.S
+  secure_sys_services.c
+  )

arch/arc/core/switch.S

@@ -17,41 +17,42 @@
 #include <kernel_structs.h>
 #include <offsets_short.h>
 #include <toolchain.h>
+#include <linker/sections.h>
 #include <arch/cpu.h>
 #include <v2/irq.h>
 #include <swap_macros.h>
 
-GTEXT(z_arch_switch)
+GTEXT(arch_switch)
 
 /**
  *
  * @brief Initiate a cooperative context switch
  *
- * The z_arch_switch routine is invoked by various kernel services to effect
- * a cooperative context switch. Prior to invoking z_arch_switch, the caller
+ * The arch_switch routine is invoked by various kernel services to effect
+ * a cooperative context switch. Prior to invoking arch_switch, the caller
  * disables interrupts via irq_lock()
 
- * Given that z_arch_switch() is called to effect a cooperative context switch,
+ * Given that arch_switch() is called to effect a cooperative context switch,
  * the caller-saved integer registers are saved on the stack by the function
- * call preamble to z_arch_switch. This creates a custom stack frame that will
- * be popped when returning from z_arch_switch, but is not suitable for handling
+ * call preamble to arch_switch. This creates a custom stack frame that will
+ * be popped when returning from arch_switch, but is not suitable for handling
  * a return from an exception. Thus, the fact that the thread is pending because
- * of a cooperative call to z_arch_switch() has to be recorded via the
+ * of a cooperative call to arch_switch() has to be recorded via the
  * _CAUSE_COOP code in the relinquish_cause of the thread's k_thread structure.
  * The _rirq_exit()/_firq_exit() code will take care of doing the right thing
  * to restore the thread status.
  *
- * When z_arch_switch() is invoked, we know the decision to perform a context
+ * When arch_switch() is invoked, we know the decision to perform a context
  * switch or not has already been taken and a context switch must happen.
  *
  *
  * C function prototype:
  *
- * void z_arch_switch(void *switch_to, void **switched_from);
+ * void arch_switch(void *switch_to, void **switched_from);
  *
  */
 
-SECTION_FUNC(TEXT, z_arch_switch)
+SECTION_FUNC(TEXT, arch_switch)
 
 #ifdef CONFIG_EXECUTION_BENCHMARKING
 	push_s r0
@@ -89,7 +90,7 @@ SECTION_FUNC(TEXT, z_arch_switch)
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	lr r3, [_ARC_V2_SEC_STAT]
 #else
-	mov r3, 0
+	mov_s r3, 0
 #endif
 	push_s r3
 #endif
@@ -113,7 +114,7 @@ SECTION_FUNC(TEXT, z_arch_switch)
 
 _switch_to_target_thread:
 
-	mov r2, r0
+	mov_s r2, r0
 
 	/* entering here, r2 contains the new current thread */
 #ifdef CONFIG_ARC_STACK_CHECKING
@@ -131,9 +132,9 @@ _switch_to_target_thread:
 	ld r3, [r2, _thread_offset_to_relinquish_cause]
 
 	breq r3, _CAUSE_RIRQ, _switch_return_from_rirq
-	nop
+	nop_s
 	breq r3, _CAUSE_FIRQ, _switch_return_from_firq
-	nop
+	nop_s
 
 	/* fall through to _switch_return_from_coop */
 
@@ -161,9 +162,19 @@ return_loc:
 _switch_return_from_rirq:
 _switch_return_from_firq:
 
+#if defined(CONFIG_USERSPACE)
+/*
+ * need to recover the user/kernel status of interrupted thread
+ */
+	pop_s r3
+	lr r2, [_ARC_V2_AUX_IRQ_ACT]
+	or r2, r2, r3
+	sr r2, [_ARC_V2_AUX_IRQ_ACT]
+#endif
+
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	/* here need to recover SEC_STAT.IRM bit */
-	pop r3
+	pop_s r3
 	sflag r3
 #endif
 
@@ -176,9 +187,9 @@ _switch_return_from_firq:
 #endif
 
 #ifdef CONFIG_ARC_NORMAL_FIRMWARE
-	mov r0, _ARC_V2_AUX_IRQ_ACT
-	mov r1, r3
-	mov r6, ARC_S_CALL_AUX_WRITE
+	mov_s r0, _ARC_V2_AUX_IRQ_ACT
+	mov_s r1, r3
+	mov_s r6, ARC_S_CALL_AUX_WRITE
 	sjli SJLI_CALL_ARC_SECURE
 #else
 	sr r3, [_ARC_V2_AUX_IRQ_ACT]

arch/arc/core/thread.c

@@ -12,8 +12,7 @@
  */
 
 #include <kernel.h>
-#include <toolchain.h>
-#include <kernel_structs.h>
+#include <ksched.h>
 #include <offsets_short.h>
 #include <wait_q.h>
 
@@ -59,10 +58,10 @@ struct init_stack_frame {
  *
  * @return N/A
  */
-void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
-		 size_t stackSize, k_thread_entry_t pEntry,
-		 void *parameter1, void *parameter2, void *parameter3,
-		 int priority, unsigned int options)
+void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
+		     size_t stackSize, k_thread_entry_t pEntry,
+		     void *parameter1, void *parameter2, void *parameter3,
+		     int priority, unsigned int options)
 {
 	char *pStackMem = Z_THREAD_STACK_BUFFER(stack);
 	Z_ASSERT_VALID_PRIO(priority, pEntry);
@@ -93,7 +92,7 @@ void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 			(u32_t)(stackEnd + STACK_GUARD_SIZE);
 
 		stackAdjEnd = (char *)STACK_ROUND_DOWN(stackEnd +
-				Z_ARCH_THREAD_STACK_RESERVED);
+				ARCH_THREAD_STACK_RESERVED);
 
 		/* reserve 4 bytes for the start of user sp */
 		stackAdjEnd -= 4;
@@ -123,7 +122,7 @@ void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	 */
 		pStackMem += STACK_GUARD_SIZE;
 		stackAdjSize = stackAdjSize + CONFIG_PRIVILEGED_STACK_SIZE;
-		stackEnd += Z_ARCH_THREAD_STACK_RESERVED;
+		stackEnd += ARCH_THREAD_STACK_RESERVED;
 
 		thread->arch.priv_stack_start = 0;
 
@@ -162,7 +161,7 @@ void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	 */
 	pInitCtx->status32 |= _ARC_V2_STATUS32_US;
 #else /* For no USERSPACE feature */
-	pStackMem += Z_ARCH_THREAD_STACK_RESERVED;
+	pStackMem += ARCH_THREAD_STACK_RESERVED;
 	stackEnd = pStackMem + stackSize;
 
 	z_new_thread_init(thread, pStackMem, stackSize, priority, options);
@@ -200,7 +199,7 @@ void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 		thread->arch.k_stack_top =
 			 (u32_t)(stackEnd + STACK_GUARD_SIZE);
 		thread->arch.k_stack_base = (u32_t)
-		(stackEnd + Z_ARCH_THREAD_STACK_RESERVED);
+		(stackEnd + ARCH_THREAD_STACK_RESERVED);
 	} else {
 		thread->arch.k_stack_top = (u32_t)pStackMem;
 		thread->arch.k_stack_base = (u32_t)stackEnd;
@@ -228,8 +227,8 @@ void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 
 #ifdef CONFIG_USERSPACE
 
-FUNC_NORETURN void z_arch_user_mode_enter(k_thread_entry_t user_entry,
-	void *p1, void *p2, void *p3)
+FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
+					void *p1, void *p2, void *p3)
 {
 
 	/*
@@ -271,7 +270,7 @@ FUNC_NORETURN void z_arch_user_mode_enter(k_thread_entry_t user_entry,
 #endif
 
 #if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
-int z_arch_float_disable(struct k_thread *thread)
+int arch_float_disable(struct k_thread *thread)
 {
 	unsigned int key;
 
@@ -288,7 +287,7 @@ int z_arch_float_disable(struct k_thread *thread)
 }
 
 
-int z_arch_float_enable(struct k_thread *thread)
+int arch_float_enable(struct k_thread *thread)
 {
 	unsigned int key;
 

arch/arc/core/thread_entry_wrapper.S

@@ -22,7 +22,7 @@ GTEXT(z_thread_entry_wrapper1)
  * @brief Wrapper for z_thread_entry
  *
  * The routine pops parameters for the z_thread_entry from stack frame, prepared
- * by the z_new_thread() routine.
+ * by the arch_new_thread() routine.
  *
  * @return N/A
  */

arch/arc/core/timestamp.c

@@ -33,7 +33,7 @@ u64_t z_tsc_read(void)
 	t = (u64_t)z_tick_get();
 	count = z_arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT);
 	irq_unlock(key);
-	t *= (u64_t)sys_clock_hw_cycles_per_tick();
+	t *= k_ticks_to_cyc_floor64(1);
 	t += (u64_t)count;
 	return t;
 }

arch/arc/core/userspace.S

@@ -14,44 +14,44 @@
 #include <v2/irq.h>
 
 .macro clear_scratch_regs
-	mov r1, 0
-	mov r2, 0
-	mov r3, 0
-	mov r4, 0
-	mov r5, 0
-	mov r6, 0
-	mov r7, 0
-	mov r8, 0
-	mov r9, 0
-	mov r10, 0
-	mov r11, 0
-	mov r12, 0
+	mov_s r1, 0
+	mov_s r2, 0
+	mov_s r3, 0
+	mov_s r4, 0
+	mov_s r5, 0
+	mov_s r6, 0
+	mov_s r7, 0
+	mov_s r8, 0
+	mov_s r9, 0
+	mov_s r10, 0
+	mov_s r11, 0
+	mov_s r12, 0
 .endm
 
 .macro clear_callee_regs
-	mov r25, 0
-	mov r24, 0
-	mov r23, 0
-	mov r22, 0
-	mov r21, 0
-	mov r20, 0
-	mov r19, 0
-	mov r18, 0
-	mov r17, 0
-	mov r16, 0
+	mov_s r25, 0
+	mov_s r24, 0
+	mov_s r23, 0
+	mov_s r22, 0
+	mov_s r21, 0
+	mov_s r20, 0
+	mov_s r19, 0
+	mov_s r18, 0
+	mov_s r17, 0
+	mov_s r16, 0
 
-	mov r15, 0
-	mov r14, 0
-	mov r13, 0
+	mov_s r15, 0
+	mov_s r14, 0
+	mov_s r13, 0
 .endm
 
 GTEXT(z_arc_userspace_enter)
 GTEXT(_arc_do_syscall)
 GTEXT(z_user_thread_entry_wrapper)
-GTEXT(z_arch_user_string_nlen)
-GTEXT(z_arch_user_string_nlen_fault_start)
-GTEXT(z_arch_user_string_nlen_fault_end)
-GTEXT(z_arch_user_string_nlen_fixup)
+GTEXT(arch_user_string_nlen)
+GTEXT(z_arc_user_string_nlen_fault_start)
+GTEXT(z_arc_user_string_nlen_fault_end)
+GTEXT(z_arc_user_string_nlen_fixup)
 /*
  * @brief Wrapper for z_thread_entry in the case of user thread
  * The init parameters are in privileged stack
@@ -67,7 +67,7 @@ SECTION_FUNC(TEXT, z_user_thread_entry_wrapper)
 /* the start of user sp is in r5 */
 	pop r5
 /* start of privilege stack in blink */
-	mov blink, sp
+	mov_s blink, sp
 
 	st.aw r0, [r5, -4]
 	st.aw r1, [r5, -4]
@@ -109,7 +109,7 @@ SECTION_FUNC(TEXT, z_arc_userspace_enter)
 	add r5, r4, r5
 	/* start of privilege stack */
 	add blink, r5, CONFIG_PRIVILEGED_STACK_SIZE+STACK_GUARD_SIZE
-	mov sp, r5
+	mov_s sp, r5
 
 	push_s r0
 	push_s r1
@@ -119,9 +119,9 @@ SECTION_FUNC(TEXT, z_arc_userspace_enter)
 	mov r5, sp /* skip r0, r1, r2, r3 */
 
 #ifdef CONFIG_INIT_STACKS
-	mov r0, 0xaaaaaaaa
+	mov_s r0, 0xaaaaaaaa
 #else
-	mov r0, 0x0
+	mov_s r0, 0x0
 #endif
 _clear_user_stack:
 	st.ab r0, [r4, 4]
@@ -129,7 +129,7 @@ _clear_user_stack:
 	jlt _clear_user_stack
 
 #ifdef CONFIG_ARC_STACK_CHECKING
-	mov r1, _kernel
+	mov_s r1, _kernel
 	ld_s r2, [r1, _kernel_offset_to_current]
 
 	_load_stack_check_regs
@@ -149,7 +149,7 @@ _arc_go_to_user_space:
 	lr r0, [_ARC_V2_STATUS32]
 	bset r0, r0, _ARC_V2_STATUS32_U_BIT
 
-	mov r1, z_thread_entry_wrapper1
+	mov_s r1, z_thread_entry_wrapper1
 
 	sr r0, [_ARC_V2_ERSTATUS]
 	sr r1, [_ARC_V2_ERET]
@@ -171,18 +171,18 @@ _arc_go_to_user_space:
 #else
 	sr r5, [_ARC_V2_USER_SP]
 #endif
-	mov sp, blink
+	mov_s sp, blink
 
-	mov r0, 0
+	mov_s r0, 0
 
 	clear_callee_regs
 
 	clear_scratch_regs
 
-	mov fp, 0
-	mov r29, 0
-	mov r30, 0
-	mov blink, 0
+	mov_s fp, 0
+	mov_s r29, 0
+	mov_s r30, 0
+	mov_s blink, 0
 
 #ifdef CONFIG_EXECUTION_BENCHMARKING
 	b _capture_value_for_benchmarking_userspace
@@ -202,50 +202,55 @@ return_loc_userspace_enter:
  *
  */
 SECTION_FUNC(TEXT, _arc_do_syscall)
-	/* r0-r5: arg1-arg6, r6 is call id */
-	/* the call id is already checked in trap_s handler */
-	push_s blink
+	/*
+	 * r0-r5: arg1-arg6, r6 is call id which is already checked in
+	 * trap_s handler, r7 is the system call stack frame pointer
+	 * need to recover r0, r1, r2 because they will be modified in
+	 * _create_irq_stack_frame. If a specific syscall frame (different
+	 * with irq stack frame) is defined, the cover of r0, r1, r2 can be
+	 * optimized.
+	 */
+	ld_s r0, [sp, ___isf_t_r0_OFFSET]
+	ld_s r1, [sp, ___isf_t_r1_OFFSET]
+	ld_s r2, [sp, ___isf_t_r2_OFFSET]
 
-	mov blink, _k_syscall_table
+	mov r7, sp
+
+	mov_s blink, _k_syscall_table
 	ld.as r6, [blink, r6]
 
 	jl [r6]
 
-	/*
-	 * no need to clear callee regs, as they will be saved and restored
-	 * automatically
-	 */
-	clear_scratch_regs
+	/* save return value */
+	st_s r0, [sp, ___isf_t_r0_OFFSET]
 
-	mov r29, 0
-	mov r30, 0
-
-	pop_s blink
+	mov_s r29, 0
+	mov_s r30, 0
 
 	/* through fake exception return, go back to the caller */
-	lr r6, [_ARC_V2_STATUS32]
-	bclr r6, r6, _ARC_V2_STATUS32_AE_BIT
-	kflag r6
+	lr r0, [_ARC_V2_STATUS32]
+	bset r0, r0, _ARC_V2_STATUS32_AE_BIT
+	kflag r0
+
 
-	/* the status and return address are saved in trap_s handler */
-	pop r6
-	sr r6, [_ARC_V2_ERSTATUS]
-	pop r6
-	sr r6, [_ARC_V2_ERET]
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
-	pop r6
-	sr r6, [_ARC_V2_ERSEC_STAT]
+	ld_s r0, [sp, ___isf_t_sec_stat_OFFSET]
+	sr r0,[_ARC_V2_ERSEC_STAT]
 #endif
+	ld_s r0, [sp, ___isf_t_status32_OFFSET]
+	sr r0,[_ARC_V2_ERSTATUS]
 
-	mov r6, 0
+	ld_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
+	sr r0,[_ARC_V2_ERET]
+
+	_pop_irq_stack_frame
 
 	rtie
 
-
 /*
- * size_t z_arch_user_string_nlen(const char *s, size_t maxsize, int *err_arg)
+ * size_t arch_user_string_nlen(const char *s, size_t maxsize, int *err_arg)
  */
-SECTION_FUNC(TEXT, z_arch_user_string_nlen)
+SECTION_FUNC(TEXT, arch_user_string_nlen)
 	/* int err; */
 	sub_s sp,sp,0x4
 
@@ -264,11 +269,11 @@ SECTION_FUNC(TEXT, z_arch_user_string_nlen)
 	mov lp_count, r1
 
 strlen_loop:
-z_arch_user_string_nlen_fault_start:
+z_arc_user_string_nlen_fault_start:
 	/* is the byte at ++r12 a NULL? if so, we're done. Might fault! */
 	ldb.aw r1, [r12, 1]
 
-z_arch_user_string_nlen_fault_end:
+z_arc_user_string_nlen_fault_end:
 	brne_s r1, 0, not_null
 
 strlen_done:
@@ -276,7 +281,7 @@ strlen_done:
 	mov_s r1, 0
 	st_s r1, [sp, 0]
 
-z_arch_user_string_nlen_fixup:
+z_arc_user_string_nlen_fixup:
 	/* *err_arg = err; Pop stack and return */
 	ld_s r1, [sp, 0]
 	add_s sp, sp, 4

arch/arc/core/vector_table.c

@@ -64,4 +64,3 @@ struct vector_table _VectorTable Z_GENERIC_SECTION(.exc_vector_table) = {
 	0,
 	0
 };
-

arch/arc/core/vector_table.ld

@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2019 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* when !XIP, .text is in RAM, and vector table must be at its very start */
+
+KEEP(*(.exc_vector_table))
+KEEP(*(".exc_vector_table.*"))
+KEEP(*(IRQ_VECTOR_TABLE))

arch/arc/include/kernel_arch_data.h

@@ -24,11 +24,9 @@
 #include <linker/sections.h>
 #include <arch/cpu.h>
 #include <vector_table.h>
-#include <kernel_arch_thread.h>
 
 #ifndef _ASMLANGUAGE
 #include <kernel.h>
-#include <kernel_internal.h>
 #include <zephyr/types.h>
 #include <sys/util.h>
 #include <sys/dlist.h>

arch/arc/include/kernel_arch_func.h

@@ -22,6 +22,8 @@
 
 #if !defined(_ASMLANGUAGE)
 
+#include <kernel_arch_data.h>
+
 #ifdef CONFIG_CPU_ARCV2
 #include <v2/cache.h>
 #include <v2/irq.h>
@@ -31,20 +33,7 @@
 extern "C" {
 #endif
 
-static ALWAYS_INLINE _cpu_t *z_arch_curr_cpu(void)
-{
-#ifdef CONFIG_SMP
-	u32_t core;
-
-	core = z_arc_v2_core_id();
-
-	return &_kernel.cpus[core];
-#else
-	return &_kernel.cpus[0];
-#endif
-}
-
-static ALWAYS_INLINE void kernel_arch_init(void)
+static ALWAYS_INLINE void arch_kernel_init(void)
 {
 	z_irq_setup();
 	_current_cpu->irq_stack =
@@ -66,7 +55,10 @@ static ALWAYS_INLINE int Z_INTERRUPT_CAUSE(void)
 	return irq_num;
 }
 
-#define z_is_in_isr	z_arc_v2_irq_unit_is_in_isr
+static inline bool arch_is_in_isr(void)
+{
+	return z_arc_v2_irq_unit_is_in_isr();
+}
 
 extern void z_thread_entry_wrapper(void);
 extern void z_user_thread_entry_wrapper(void);
@@ -75,10 +67,10 @@ extern void z_arc_userspace_enter(k_thread_entry_t user_entry, void *p1,
 		 void *p2, void *p3, u32_t stack, u32_t size);
 
 
-extern void z_arch_switch(void *switch_to, void **switched_from);
+extern void arch_switch(void *switch_to, void **switched_from);
 extern void z_arc_fatal_error(unsigned int reason, const z_arch_esf_t *esf);
 
-extern void z_arch_sched_ipi(void);
+extern void arch_sched_ipi(void);
 
 #ifdef __cplusplus
 }

arch/arc/include/kernel_arch_thread.h

@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2017 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Per-arch thread definition
- *
- * This file contains definitions for
- *
- *  struct _thread_arch
- *  struct _callee_saved
- *
- * necessary to instantiate instances of struct k_thread.
- */
-
-#ifndef ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_THREAD_H_
-#define ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_THREAD_H_
-
-/*
- * Reason a thread has relinquished control.
- */
-#define _CAUSE_NONE 0
-#define _CAUSE_COOP 1
-#define _CAUSE_RIRQ 2
-#define _CAUSE_FIRQ 3
-
-#ifndef _ASMLANGUAGE
-#include <zephyr/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct _callee_saved {
-	u32_t sp; /* r28 */
-};
-typedef struct _callee_saved _callee_saved_t;
-
-struct _thread_arch {
-
-	/* one of the _CAUSE_xxxx definitions above */
-	int relinquish_cause;
-
-#ifdef CONFIG_ARC_STACK_CHECKING
-	/* High address of stack region, stack grows downward from this
-	 * location. Usesd for hardware stack checking
-	 */
-	u32_t k_stack_base;
-	u32_t k_stack_top;
-#ifdef CONFIG_USERSPACE
-	u32_t u_stack_base;
-	u32_t u_stack_top;
-#endif
-#endif
-
-#ifdef CONFIG_USERSPACE
-	u32_t priv_stack_start;
-#endif
-};
-
-typedef struct _thread_arch _thread_arch_t;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ASMLANGUAGE */
-
-
-#endif /* ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_THREAD_H_ */

arch/arc/include/swap_macros.h

@@ -42,18 +42,18 @@
 #ifdef CONFIG_ARC_HAS_SECURE
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	lr r13, [_ARC_V2_SEC_U_SP]
-	st r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
+	st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
 	lr r13, [_ARC_V2_SEC_K_SP]
-	st r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
+	st_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
 #else
 	lr r13, [_ARC_V2_USER_SP]
-	st r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
+	st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
 	lr r13, [_ARC_V2_KERNEL_SP]
-	st r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
+	st_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
 #endif /* CONFIG_ARC_SECURE_FIRMWARE */
 #else
 	lr r13, [_ARC_V2_USER_SP]
-	st r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
+	st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
 #endif
 #endif
 	st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
@@ -64,7 +64,7 @@
 #endif
 
 #ifdef CONFIG_FP_SHARING
-	ld r13, [r2, ___thread_base_t_user_options_OFFSET]
+	ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
 	/* K_FP_REGS is bit 1 */
 	bbit0 r13, 1, 1f
 	lr r13, [_ARC_V2_FPU_STATUS]
@@ -100,7 +100,7 @@
 #endif
 
 #ifdef CONFIG_FP_SHARING
-	ld r13, [r2, ___thread_base_t_user_options_OFFSET]
+	ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
 	/* K_FP_REGS is bit 1 */
 	bbit0 r13, 1, 2f
 
@@ -125,18 +125,18 @@
 #ifdef CONFIG_USERSPACE
 #ifdef CONFIG_ARC_HAS_SECURE
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
-	ld r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
+	ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
 	sr r13, [_ARC_V2_SEC_U_SP]
-	ld r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
+	ld_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
 	sr r13, [_ARC_V2_SEC_K_SP]
 #else
 	ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
 	sr r13, [_ARC_V2_USER_SP]
-	ld r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
+	ld_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
 	sr r13, [_ARC_V2_KERNEL_SP]
 #endif /* CONFIG_ARC_SECURE_FIRMWARE */
 #else
-	ld r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
+	ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
 	sr r13, [_ARC_V2_USER_SP]
 #endif
 #endif
@@ -258,7 +258,7 @@
 	 * The pc and status32 values will still be on the stack. We cannot
 	 * pop them yet because the callers of _pop_irq_stack_frame must reload
 	 * status32 differently depending on the execution context they are
-	 * running in (z_arch_switch(), firq or exception).
+	 * running in (arch_switch(), firq or exception).
 	 */
 	add_s sp, sp, ___isf_t_SIZEOF
 
@@ -365,6 +365,18 @@
 #endif
 .endm
 
+/* macro to push aux reg through reg */
+.macro PUSHAX reg aux
+	lr \reg, [\aux]
+	st.a \reg, [sp, -4]
+.endm
+
+/* macro to pop aux reg through reg */
+.macro POPAX reg aux
+	ld.ab \reg, [sp, 4]
+	sr \reg, [\aux]
+.endm
+
 #endif /* _ASMLANGUAGE */
 
 #endif /*  ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_ */

arch/arc/include/v2/irq.h

@@ -65,7 +65,7 @@ static ALWAYS_INLINE void z_irq_setup(void)
 		_ARC_V2_AUX_IRQ_CTRL_14_REGS     /* save r0 -> r13 (caller-saved) */
 	);
 
-	k_cpu_sleep_mode = _ARC_V2_WAKE_IRQ_LEVEL;
+	z_arc_cpu_sleep_mode = _ARC_V2_WAKE_IRQ_LEVEL;
 
 #ifdef CONFIG_ARC_NORMAL_FIRMWARE
 	/* normal mode cannot write irq_ctrl, ignore it */

arch/arm/CMakeLists.txt

@@ -1,26 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
-set(ARCH_FOR_cortex-m0        armv6s-m        )
-set(ARCH_FOR_cortex-m0plus    armv6s-m        )
-set(ARCH_FOR_cortex-m3        armv7-m         )
-set(ARCH_FOR_cortex-m4        armv7e-m        )
-set(ARCH_FOR_cortex-m23       armv8-m.base    )
-set(ARCH_FOR_cortex-m33       armv8-m.main+dsp)
-set(ARCH_FOR_cortex-m33+nodsp armv8-m.main    )
-set(ARCH_FOR_cortex-r4        armv7-r         )
-
-if(ARCH_FOR_${GCC_M_CPU})
-    set(ARCH_FLAG -march=${ARCH_FOR_${GCC_M_CPU}})
+if(CONFIG_ARM64)
+  include(aarch64.cmake)
+else()
+  include(aarch32.cmake)
 endif()
-
-zephyr_compile_options(
-  -mabi=aapcs
-  ${ARCH_FLAG}
-  )
-
-zephyr_ld_options(
-  -mabi=aapcs
-  ${ARCH_FLAG}
-  )
-
-add_subdirectory(core)

arch/arm/Kconfig

@@ -1,18 +1,19 @@
-# Kconfig - ARM architecture configuration options
+# ARM architecture configuration options
 
-#
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
-#
 # SPDX-License-Identifier: Apache-2.0
-#
-
 
 menu "ARM Options"
 	depends on ARM
 
-source "arch/arm/core/Kconfig"
+rsource "core/aarch32/Kconfig"
+rsource "core/aarch64/Kconfig"
 
 config ARCH
 	default "arm"
 
+config ARM64
+	bool
+	select 64BIT
+
 endmenu

arch/arm/aarch32.cmake

@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(ARCH_FOR_cortex-m0        armv6s-m        )
+set(ARCH_FOR_cortex-m0plus    armv6s-m        )
+set(ARCH_FOR_cortex-m3        armv7-m         )
+set(ARCH_FOR_cortex-m4        armv7e-m        )
+set(ARCH_FOR_cortex-m23       armv8-m.base    )
+set(ARCH_FOR_cortex-m33       armv8-m.main+dsp)
+set(ARCH_FOR_cortex-m33+nodsp armv8-m.main    )
+set(ARCH_FOR_cortex-r4        armv7-r         )
+
+if(ARCH_FOR_${GCC_M_CPU})
+    set(ARCH_FLAG -march=${ARCH_FOR_${GCC_M_CPU}})
+endif()
+
+zephyr_compile_options(
+  -mabi=aapcs
+  ${ARCH_FLAG}
+  )
+
+zephyr_ld_options(
+  -mabi=aapcs
+  ${ARCH_FLAG}
+  )
+
+set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-little${ARCH}) # BFD format
+
+add_subdirectory(core/aarch32)

arch/arm/aarch64.cmake

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf64-littleaarch64) # BFD format
+
+add_subdirectory(core/aarch64)

arch/arm/core/CMakeLists.txt

@@ -1,37 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library()
-
-zephyr_compile_options_ifdef(CONFIG_COVERAGE_GCOV
-  -ftest-coverage
-  -fprofile-arcs
-  -fno-inline
-  )
-
-zephyr_library_sources(
-  exc_exit.S
-  swap.c
-  swap_helper.S
-  irq_manage.c
-  thread.c
-  cpu_idle.S
-  fault_s.S
-  fatal.c
-  nmi.c
-  nmi_on_reset.S
-  prep_c.c
-)
-
-zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
-zephyr_library_sources_ifdef(CONFIG_CPLUSPLUS __aeabi_atexit.c)
-zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
-zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M0 irq_relay.S)
-zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
-
-add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M cortex_m)
-add_subdirectory_ifdef(CONFIG_ARM_MPU cortex_m/mpu)
-add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M_HAS_CMSE cortex_m/cmse)
-add_subdirectory_ifdef(CONFIG_ARM_SECURE_FIRMWARE cortex_m/tz)
-add_subdirectory_ifdef(CONFIG_ARM_NONSECURE_FIRMWARE cortex_m/tz)
-
-add_subdirectory_ifdef(CONFIG_CPU_CORTEX_R cortex_r)

arch/arm/core/Kconfig

@@ -1,282 +0,0 @@
-# Kconfig - ARM core configuration options
-
-#
-# Copyright (c) 2015 Wind River Systems, Inc.
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-config CPU_CORTEX
-	bool
-	# Omit prompt to signify "hidden" option
-	help
-	  This option signifies the use of a CPU of the Cortex family.
-
-config CPU_CORTEX_M
-	bool
-	# Omit prompt to signify "hidden" option
-	select CPU_CORTEX
-	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
-	select HAS_CMSIS
-	select HAS_FLASH_LOAD_OFFSET
-	select ARCH_HAS_THREAD_ABORT
-	select ARCH_HAS_TRUSTED_EXECUTION if ARM_TRUSTZONE_M
-	select ARCH_HAS_STACK_PROTECTION if ARM_MPU || CPU_CORTEX_M_HAS_SPLIM
-	select ARCH_HAS_USERSPACE if ARM_MPU
-	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_CORTEX_M7
-	select ARCH_HAS_RAMFUNC_SUPPORT
-	select SWAP_NONATOMIC
-	help
-	  This option signifies the use of a CPU of the Cortex-M family.
-
-config CPU_CORTEX_R
-	bool
-	select CPU_CORTEX
-	select HAS_FLASH_LOAD_OFFSET
-	help
-	  This option signifies the use of a CPU of the Cortex-R family.
-
-config ISA_THUMB2
-	bool
-	help
-	  From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
-
-	  Thumb-2 technology is the instruction set underlying the ARM Cortex
-	  architecture which provides enhanced levels of performance, energy
-	  efficiency, and code density for a wide range of embedded
-	  applications.
-
-	  Thumb-2 technology builds on the success of Thumb, the innovative
-	  high code density instruction set for ARM microprocessor cores, to
-	  increase the power of the ARM microprocessor core available to
-	  developers of low cost, high performance systems.
-
-	  The technology is backwards compatible with existing ARM and Thumb
-	  solutions, while significantly extending the features available to
-	  the Thumb instructions set. This allows more of the application to
-	  benefit from the best in class code density of Thumb.
-
-	  For performance optimized code Thumb-2 technology uses 31 percent
-	  less memory to reduce system cost, while providing up to 38 percent
-	  higher performance than existing high density code, which can be used
-	  to prolong battery-life or to enrich the product feature set. Thumb-2
-	  technology is featured in the  processor, and in all ARMv7
-	  architecture-based processors.
-
-config ISA_ARM
-	bool
-	help
-	  From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets
-
-	  A32 instructions, known as Arm instructions in pre-Armv8 architectures,
-	  are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
-	  are supported by both A-profile and R-profile architectures.
-
-	  A32 was traditionally used in applications requiring the highest
-	  performance, or for handling hardware exceptions such as interrupts and
-	  processor start-up. Much of its functionality was subsumed into T32 with
-	  the introduction of Thumb-2 technology.
-
-config DATA_ENDIANNESS_LITTLE
-	bool
-	default y if CPU_CORTEX
-	help
-	  This is driven by the processor implementation, since it is fixed in
-	  hardware. The board should set this value to 'n' if the data is
-	  implemented as big endian.
-
-config STACK_ALIGN_DOUBLE_WORD
-	bool "Align stacks on double-words (8 octets)"
-	default y
-	help
-	  This is needed to conform to AAPCS, the procedure call standard for
-	  the ARM. It wastes stack space. The option also enforces alignment
-	  of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M).
-	  Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment
-	  on exception entry is enabled by default and it is not configurable.
-
-config RUNTIME_NMI
-	bool "Attach an NMI handler at runtime"
-	select REBOOT
-	help
-	  The kernel provides a simple NMI handler that simply hangs in a tight
-	  loop if triggered. This fills the requirement that there must be an
-	  NMI handler installed when the CPU boots. If a custom handler is
-	  needed, enable this option and attach it via _NmiHandlerSet().
-
-config FAULT_DUMP
-	int "Fault dump level"
-	default 2
-	range 0 2
-	help
-	  Different levels for display information when a fault occurs.
-
-	  2: The default. Display specific and verbose information. Consumes
-		the most memory (long strings).
-
-	  1: Display general and short information. Consumes less memory
-		(short strings).
-
-	  0: Off.
-
-config BUILTIN_STACK_GUARD
-	bool "Thread Stack Guards based on built-in ARM stack limit checking"
-	depends on CPU_CORTEX_M_HAS_SPLIM
-	select THREAD_STACK_INFO
-	help
-	  Enable Thread/Interrupt Stack Guards via built-in Stack Pointer
-	  limit checking. The functionality must be supported by HW.
-
-config ARM_STACK_PROTECTION
-	bool
-	default y if HW_STACK_PROTECTION
-	imply BUILTIN_STACK_GUARD if CPU_CORTEX_M_HAS_SPLIM
-	select MPU_STACK_GUARD if (!BUILTIN_STACK_GUARD && ARM_MPU)
-	help
-	  This option enables either:
-	  - The built-in Stack Pointer limit checking, or
-	  - the MPU-based stack guard
-	  to cause a system fatal error
-	  if the bounds of the current process stack are overflowed.
-	  The two stack guard options are mutually exclusive. The
-	  selection of the built-in Stack Pointer limit checking is
-	  prioritized over the MPU-based stack guard. The developer
-	  still has the option to manually select the MPU-based
-	  stack guard, if this is desired.
-
-config ARM_SECURE_FIRMWARE
-	bool
-	depends on ARMV8_M_SE
-	default y if TRUSTED_EXECUTION_SECURE
-	help
-	  This option indicates that we are building a Zephyr image that
-	  is intended to execute in Secure state. The option is only
-	  applicable to ARMv8-M MCUs that implement the Security Extension.
-
-	  This option enables Zephyr to include code that executes in
-	  Secure state, as well as to exclude code that is designed to
-	  execute only in Non-secure state.
-
-	  Code executing in Secure state has access to both the Secure
-	  and Non-Secure resources of the Cortex-M MCU.
-
-	  Code executing in Non-Secure state may trigger Secure Faults,
-	  if Secure MCU resources are accessed from the Non-Secure state.
-	  Secure Faults may only be handled by code executing in Secure
-	  state.
-
-config ARM_NONSECURE_FIRMWARE
-	bool
-	depends on !ARM_SECURE_FIRMWARE
-	depends on ARMV8_M_SE
-	default y if TRUSTED_EXECUTION_NONSECURE
-	help
-	  This option indicates that we are building a Zephyr image that
-	  is intended to execute in Non-Secure state. Execution of this
-	  image is triggered by Secure firmware that executes in Secure
-	  state. The option is only applicable to ARMv8-M MCUs that
-	  implement the Security Extension.
-
-	  This option enables Zephyr to include code that executes in
-	  Non-Secure state only, as well as to exclude code that is
-	  designed to execute only in Secure state.
-
-	  Code executing in Non-Secure state has no access to Secure
-	  resources of the Cortex-M MCU, and, therefore, it shall avoid
-	  accessing them.
-
-
-menu "ARM TrustZone Options"
-depends on ARM_SECURE_FIRMWARE || ARM_NONSECURE_FIRMWARE
-
-comment "Secure firmware"
-	depends on ARM_SECURE_FIRMWARE
-
-comment "Non-secure firmware"
-	depends on !ARM_SECURE_FIRMWARE
-
-config ARM_SECURE_BUSFAULT_HARDFAULT_NMI
-	bool "BusFault, HardFault, and NMI target Secure state"
-	depends on ARM_SECURE_FIRMWARE
-	help
-	  Force NMI, HardFault, and BusFault (in Mainline ARMv8-M)
-	  exceptions as Secure exceptions.
-
-config ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS
-	bool "Secure Firmware has Secure Entry functions"
-	depends on ARM_SECURE_FIRMWARE
-	help
-	  Option indicates that ARM Secure Firmware contains
-	  Secure Entry functions that may be called from
-	  Non-Secure state. Secure Entry functions must be
-	  located in Non-Secure Callable memory regions.
-
-config ARM_NSC_REGION_BASE_ADDRESS
-	hex "ARM Non-Secure Callable Region base address"
-	depends on ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS
-	default 0
-	help
-	  Start address of Non-Secure Callable section.
-
-	  Notes:
-	  - The default value (i.e. when the user does not configure
-	  the option explicitly) instructs the linker script to
-	  place the Non-Secure Callable section, automatically,
-	  inside the .text area.
-	  - Certain requirements/restrictions may apply regarding
-	  the size and the alignment of the starting address for
-	  a Non-Secure Callable section, depending on the available
-	  security attribution unit (SAU or IDAU) for a given SOC.
-
-config ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS
-	bool "Non-Secure Firmware uses Secure Entry functions"
-	depends on ARM_NONSECURE_FIRMWARE
-	help
-	  Option indicates that ARM Non-Secure Firmware uses Secure
-	  Entry functions provided by the Secure Firmware. The Secure
-	  Firmware must be configured to provide these functions.
-
-config ARM_ENTRY_VENEERS_LIB_NAME
-	string "Entry Veneers symbol file"
-	depends on ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS \
-	        || ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS
-	default "libentryveneers.a"
-	help
-	  Library file to find the symbol table for the entry veneers.
-	  The library will typically come from building the Secure
-	  Firmware that contains secure entry functions, and allows
-	  the Non-Secure Firmware to call into the Secure Firmware.
-
-endmenu
-
-menu "Architecture Floating Point Options"
-depends on CPU_HAS_FPU
-
-choice
-	prompt "Floating point ABI"
-	default FP_HARDABI
-	depends on FLOAT
-
-config FP_HARDABI
-	bool "Floating point Hard ABI"
-	help
-	  This option selects the Floating point ABI in which hardware floating
-	  point instructions are generated and uses FPU-specific calling
-	  conventions
-
-config FP_SOFTABI
-	bool "Floating point Soft ABI"
-	help
-	  This option selects the Floating point ABI in which hardware floating
-	  point instructions are generated but soft-float calling conventions.
-
-endchoice
-
-endmenu
-
-source "arch/arm/core/cortex_m/Kconfig"
-source "arch/arm/core/cortex_r/Kconfig"
-
-source "arch/arm/core/cortex_m/mpu/Kconfig"
-
-source "arch/arm/core/cortex_m/tz/Kconfig"

arch/arm/core/aarch32/CMakeLists.txt

@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+if (CONFIG_COVERAGE)
+  toolchain_cc_coverage()
+endif ()
+
+zephyr_library_sources(
+  exc_exit.S
+  swap.c
+  swap_helper.S
+  irq_manage.c
+  thread.c
+  cpu_idle.S
+  fault_s.S
+  fatal.c
+  nmi.c
+  nmi_on_reset.S
+  prep_c.c
+)
+
+zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
+zephyr_library_sources_ifdef(CONFIG_CPLUSPLUS __aeabi_atexit.c)
+zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
+zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M0 irq_relay.S)
+zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
+
+add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M cortex_m)
+add_subdirectory_ifdef(CONFIG_ARM_MPU cortex_m/mpu)
+add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M_HAS_CMSE cortex_m/cmse)
+add_subdirectory_ifdef(CONFIG_ARM_SECURE_FIRMWARE cortex_m/tz)
+add_subdirectory_ifdef(CONFIG_ARM_NONSECURE_FIRMWARE cortex_m/tz)
+
+add_subdirectory_ifdef(CONFIG_CPU_CORTEX_R cortex_r)
+
+zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)

arch/arm/core/aarch32/Kconfig

@@ -0,0 +1,279 @@
+# ARM core configuration options
+
+# Copyright (c) 2015 Wind River Systems, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if !ARM64
+
+config CPU_CORTEX
+	bool
+	help
+	  This option signifies the use of a CPU of the Cortex family.
+
+config CPU_CORTEX_M
+	bool
+	select CPU_CORTEX
+	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
+	select HAS_CMSIS_CORE
+	select HAS_FLASH_LOAD_OFFSET
+	select ARCH_HAS_THREAD_ABORT
+	select ARCH_HAS_TRUSTED_EXECUTION if ARM_TRUSTZONE_M
+	select ARCH_HAS_STACK_PROTECTION if (ARM_MPU && !ARMV6_M_ARMV8_M_BASELINE) || CPU_CORTEX_M_HAS_SPLIM
+	select ARCH_HAS_USERSPACE if ARM_MPU
+	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_CORTEX_M7
+	select ARCH_HAS_RAMFUNC_SUPPORT
+	select ARCH_HAS_NESTED_EXCEPTION_DETECTION
+	select SWAP_NONATOMIC
+	help
+	  This option signifies the use of a CPU of the Cortex-M family.
+
+config CPU_CORTEX_R
+	bool
+	select CPU_CORTEX
+	select HAS_CMSIS_CORE
+	select HAS_FLASH_LOAD_OFFSET
+	help
+	  This option signifies the use of a CPU of the Cortex-R family.
+
+config ISA_THUMB2
+	bool
+	help
+	  From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
+
+	  Thumb-2 technology is the instruction set underlying the ARM Cortex
+	  architecture which provides enhanced levels of performance, energy
+	  efficiency, and code density for a wide range of embedded
+	  applications.
+
+	  Thumb-2 technology builds on the success of Thumb, the innovative
+	  high code density instruction set for ARM microprocessor cores, to
+	  increase the power of the ARM microprocessor core available to
+	  developers of low cost, high performance systems.
+
+	  The technology is backwards compatible with existing ARM and Thumb
+	  solutions, while significantly extending the features available to
+	  the Thumb instructions set. This allows more of the application to
+	  benefit from the best in class code density of Thumb.
+
+	  For performance optimized code Thumb-2 technology uses 31 percent
+	  less memory to reduce system cost, while providing up to 38 percent
+	  higher performance than existing high density code, which can be used
+	  to prolong battery-life or to enrich the product feature set. Thumb-2
+	  technology is featured in the  processor, and in all ARMv7
+	  architecture-based processors.
+
+config ISA_ARM
+	bool
+	help
+	  From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets
+
+	  A32 instructions, known as Arm instructions in pre-Armv8 architectures,
+	  are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
+	  are supported by both A-profile and R-profile architectures.
+
+	  A32 was traditionally used in applications requiring the highest
+	  performance, or for handling hardware exceptions such as interrupts and
+	  processor start-up. Much of its functionality was subsumed into T32 with
+	  the introduction of Thumb-2 technology.
+
+config NUM_IRQS
+	int
+
+config STACK_ALIGN_DOUBLE_WORD
+	bool "Align stacks on double-words (8 octets)"
+	default y
+	help
+	  This is needed to conform to AAPCS, the procedure call standard for
+	  the ARM. It wastes stack space. The option also enforces alignment
+	  of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M).
+	  Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment
+	  on exception entry is enabled by default and it is not configurable.
+
+config RUNTIME_NMI
+	bool "Attach an NMI handler at runtime"
+	select REBOOT
+	help
+	  The kernel provides a simple NMI handler that simply hangs in a tight
+	  loop if triggered. This fills the requirement that there must be an
+	  NMI handler installed when the CPU boots. If a custom handler is
+	  needed, enable this option and attach it via _NmiHandlerSet().
+
+config PLATFORM_SPECIFIC_INIT
+	bool "Enable platform (SOC) specific startup hook"
+	help
+	  The platform specific initialization code (z_platform_init) is executed
+	  at the beginning of the startup code (__start).
+
+config FAULT_DUMP
+	int "Fault dump level"
+	default 2
+	range 0 2
+	help
+	  Different levels for display information when a fault occurs.
+
+	  2: The default. Display specific and verbose information. Consumes
+		the most memory (long strings).
+
+	  1: Display general and short information. Consumes less memory
+		(short strings).
+
+	  0: Off.
+
+config BUILTIN_STACK_GUARD
+	bool "Thread Stack Guards based on built-in ARM stack limit checking"
+	depends on CPU_CORTEX_M_HAS_SPLIM
+	select THREAD_STACK_INFO
+	help
+	  Enable Thread/Interrupt Stack Guards via built-in Stack Pointer
+	  limit checking. The functionality must be supported by HW.
+
+config ARM_STACK_PROTECTION
+	bool
+	default y if HW_STACK_PROTECTION
+	imply BUILTIN_STACK_GUARD if CPU_CORTEX_M_HAS_SPLIM
+	select MPU_STACK_GUARD if (!BUILTIN_STACK_GUARD && ARM_MPU)
+	help
+	  This option enables either:
+	  - The built-in Stack Pointer limit checking, or
+	  - the MPU-based stack guard
+	  to cause a system fatal error
+	  if the bounds of the current process stack are overflowed.
+	  The two stack guard options are mutually exclusive. The
+	  selection of the built-in Stack Pointer limit checking is
+	  prioritized over the MPU-based stack guard. The developer
+	  still has the option to manually select the MPU-based
+	  stack guard, if this is desired.
+
+config ARM_SECURE_FIRMWARE
+	bool
+	depends on ARMV8_M_SE
+	default y if TRUSTED_EXECUTION_SECURE
+	help
+	  This option indicates that we are building a Zephyr image that
+	  is intended to execute in Secure state. The option is only
+	  applicable to ARMv8-M MCUs that implement the Security Extension.
+
+	  This option enables Zephyr to include code that executes in
+	  Secure state, as well as to exclude code that is designed to
+	  execute only in Non-secure state.
+
+	  Code executing in Secure state has access to both the Secure
+	  and Non-Secure resources of the Cortex-M MCU.
+
+	  Code executing in Non-Secure state may trigger Secure Faults,
+	  if Secure MCU resources are accessed from the Non-Secure state.
+	  Secure Faults may only be handled by code executing in Secure
+	  state.
+
+config ARM_NONSECURE_FIRMWARE
+	bool
+	depends on !ARM_SECURE_FIRMWARE
+	depends on ARMV8_M_SE
+	default y if TRUSTED_EXECUTION_NONSECURE
+	help
+	  This option indicates that we are building a Zephyr image that
+	  is intended to execute in Non-Secure state. Execution of this
+	  image is triggered by Secure firmware that executes in Secure
+	  state. The option is only applicable to ARMv8-M MCUs that
+	  implement the Security Extension.
+
+	  This option enables Zephyr to include code that executes in
+	  Non-Secure state only, as well as to exclude code that is
+	  designed to execute only in Secure state.
+
+	  Code executing in Non-Secure state has no access to Secure
+	  resources of the Cortex-M MCU, and, therefore, it shall avoid
+	  accessing them.
+
+
+menu "ARM TrustZone Options"
+depends on ARM_SECURE_FIRMWARE || ARM_NONSECURE_FIRMWARE
+
+comment "Secure firmware"
+	depends on ARM_SECURE_FIRMWARE
+
+comment "Non-secure firmware"
+	depends on !ARM_SECURE_FIRMWARE
+
+config ARM_SECURE_BUSFAULT_HARDFAULT_NMI
+	bool "BusFault, HardFault, and NMI target Secure state"
+	depends on ARM_SECURE_FIRMWARE
+	help
+	  Force NMI, HardFault, and BusFault (in Mainline ARMv8-M)
+	  exceptions as Secure exceptions.
+
+config ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS
+	bool "Secure Firmware has Secure Entry functions"
+	depends on ARM_SECURE_FIRMWARE
+	help
+	  Option indicates that ARM Secure Firmware contains
+	  Secure Entry functions that may be called from
+	  Non-Secure state. Secure Entry functions must be
+	  located in Non-Secure Callable memory regions.
+
+config ARM_NSC_REGION_BASE_ADDRESS
+	hex "ARM Non-Secure Callable Region base address"
+	depends on ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS
+	default 0
+	help
+	  Start address of Non-Secure Callable section.
+
+	  Notes:
+	  - The default value (i.e. when the user does not configure
+	  the option explicitly) instructs the linker script to
+	  place the Non-Secure Callable section, automatically,
+	  inside the .text area.
+	  - Certain requirements/restrictions may apply regarding
+	  the size and the alignment of the starting address for
+	  a Non-Secure Callable section, depending on the available
+	  security attribution unit (SAU or IDAU) for a given SOC.
+
+config ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS
+	bool "Non-Secure Firmware uses Secure Entry functions"
+	depends on ARM_NONSECURE_FIRMWARE
+	help
+	  Option indicates that ARM Non-Secure Firmware uses Secure
+	  Entry functions provided by the Secure Firmware. The Secure
+	  Firmware must be configured to provide these functions.
+
+config ARM_ENTRY_VENEERS_LIB_NAME
+	string "Entry Veneers symbol file"
+	depends on ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS \
+	        || ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS
+	default "libentryveneers.a"
+	help
+	  Library file to find the symbol table for the entry veneers.
+	  The library will typically come from building the Secure
+	  Firmware that contains secure entry functions, and allows
+	  the Non-Secure Firmware to call into the Secure Firmware.
+
+endmenu
+
+choice
+	prompt "Floating point ABI"
+	default FP_HARDABI
+	depends on FLOAT
+
+config FP_HARDABI
+	bool "Floating point Hard ABI"
+	help
+	  This option selects the Floating point ABI in which hardware floating
+	  point instructions are generated and uses FPU-specific calling
+	  conventions
+
+config FP_SOFTABI
+	bool "Floating point Soft ABI"
+	help
+	  This option selects the Floating point ABI in which hardware floating
+	  point instructions are generated but soft-float calling conventions.
+
+endchoice
+
+rsource "cortex_m/Kconfig"
+rsource "cortex_r/Kconfig"
+
+rsource "cortex_m/mpu/Kconfig"
+
+rsource "cortex_m/tz/Kconfig"
+
+endif # !ARM64

arch/arm/core/aarch32/cortex_m/CMakeLists.txt

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+  vector_table.S
+  reset.S
+  fault.c
+  scb.c
+  irq_init.c
+  thread_abort.c
+  )
+
+zephyr_linker_sources_ifdef(CONFIG_SW_VECTOR_RELAY
+  ROM_START
+  SORT_KEY 0x0relay_vectors
+  relay_vector_table.ld
+  )
+
+zephyr_linker_sources_ifdef(CONFIG_SW_VECTOR_RELAY
+  RAM_SECTIONS
+  vt_pointer_section.ld
+  )

arch/arm/core/aarch32/cortex_m/Kconfig

@@ -0,0 +1,282 @@
+# ARM Cortex-M platform configuration options
+
+# Copyright (c) 2014-2015 Wind River Systems, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# NOTE: We have the specific core implementations first and outside of the
+# if CPU_CORTEX_M block so that SoCs can select which core they are using
+# without having to select all the options related to that core.  Everything
+# else is captured inside the if CPU_CORTEX_M block so they are not exposed
+# if one select a differnet ARM Cortex Family (Cortex-A or Cortex-R)
+
+config CPU_CORTEX_M0
+	bool
+	select CPU_CORTEX_M
+	select ARMV6_M_ARMV8_M_BASELINE
+	help
+	  This option signifies the use of a Cortex-M0 CPU
+
+config CPU_CORTEX_M0PLUS
+	bool
+	select CPU_CORTEX_M
+	select ARMV6_M_ARMV8_M_BASELINE
+	help
+	  This option signifies the use of a Cortex-M0+ CPU
+
+config CPU_CORTEX_M3
+	bool
+	select CPU_CORTEX_M
+	select ARMV7_M_ARMV8_M_MAINLINE
+	help
+	  This option signifies the use of a Cortex-M3 CPU
+
+config CPU_CORTEX_M4
+	bool
+	select CPU_CORTEX_M
+	select ARMV7_M_ARMV8_M_MAINLINE
+	select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU
+	help
+	  This option signifies the use of a Cortex-M4 CPU
+
+config CPU_CORTEX_M23
+	bool
+	select CPU_CORTEX_M
+	select ARMV8_M_BASELINE
+	select ARMV8_M_SE if CPU_HAS_TEE
+	help
+	  This option signifies the use of a Cortex-M23 CPU
+
+config CPU_CORTEX_M33
+	bool
+	select CPU_CORTEX_M
+	select ARMV8_M_MAINLINE
+	select ARMV8_M_SE if CPU_HAS_TEE
+	select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU
+	help
+	  This option signifies the use of a Cortex-M33 CPU
+
+config CPU_CORTEX_M7
+	bool
+	select CPU_CORTEX_M
+	select ARMV7_M_ARMV8_M_MAINLINE
+	select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU
+	help
+	  This option signifies the use of a Cortex-M7 CPU
+
+if CPU_CORTEX_M
+
+config CPU_CORTEX_M_HAS_SYSTICK
+	bool
+	help
+	  This option is enabled when the CPU implements the SysTick timer.
+
+config CPU_CORTEX_M_HAS_DWT
+	bool
+	depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS
+	help
+	  This option signifies that the CPU implements the Data Watchpoint and
+	  Trace (DWT) unit specified by the ARMv7-M and above.
+
+	  While ARMv6-M does define a "DWT" unit, this is significantly different
+	  from the DWT specified by the ARMv7-M and above in terms of both feature
+	  set and register mappings.
+
+config CPU_CORTEX_M_HAS_BASEPRI
+	bool
+	depends on ARMV7_M_ARMV8_M_MAINLINE
+	help
+	  This option signifies the CPU has the BASEPRI register.
+
+	  The BASEPRI register defines the minimum priority for
+	  exception processing. When BASEPRI is set to a nonzero
+	  value, it prevents the activation of all exceptions with
+	  the same or lower priority level as the BASEPRI value.
+	  Always present in CPUs that implement the ARMv7-M or
+	  ARM8-M Mainline architectures.
+
+config CPU_CORTEX_M_HAS_VTOR
+	bool
+	depends on !CPU_CORTEX_M0
+	help
+	  This option signifies the CPU has the VTOR register.
+	  The VTOR indicates the offset of the vector table base
+	  address from memory address 0x00000000. Always present
+	  in CPUs implementing the ARMv7-M or ARMv8-M architectures.
+	  Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline
+	  architectures (except for Cortex-M0, where it is never
+	  implemented).
+
+config CPU_CORTEX_M_HAS_SPLIM
+	bool
+	depends on ARMV8_M_MAINLINE || (ARMV8_M_SE && !ARM_NONSECURE_FIRMWARE)
+	help
+	  This option signifies the CPU has the MSPLIM, PSPLIM registers.
+
+	  The stack pointer limit registers, MSPLIM, PSPLIM, limit the
+	  extend to which the Main and Process Stack Pointers, respectively,
+	  can descend. MSPLIM, PSPLIM are always present in ARMv8-M
+	  MCUs that implement the ARMv8-M Main Extension (Mainline).
+
+	  In an ARMv8-M Mainline implementation with the Security Extension
+	  the MSPLIM, PSPLIM registers have additional Secure instances.
+	  In an ARMv8-M Baseline implementation with the Security Extension
+	  the MSPLIM, PSPLIM registers have only Secure instances.
+
+config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
+	bool
+	depends on ARMV7_M_ARMV8_M_MAINLINE
+	help
+	  This option signifies the CPU may trigger system faults
+	  (other than HardFault) with configurable priority, and,
+	  therefore, it needs to reserve a priority level for them.
+
+config CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
+	bool
+	help
+	  This option signifies the Cortex-M0 has some mechanisms that can map
+	  the vector table to SRAM
+
+config CPU_CORTEX_M_HAS_CMSE
+	bool
+	depends on ARMV8_M_BASELINE || ARMV8_M_MAINLINE
+	help
+	  This option signifies the Cortex-M CPU has the CMSE intrinsics.
+
+config ARMV6_M_ARMV8_M_BASELINE
+	bool
+	select ATOMIC_OPERATIONS_C
+	select ISA_THUMB2
+	help
+	  This option signifies the use of an ARMv6-M processor
+	  implementation, or the use of an ARMv8-M processor
+	  supporting the Baseline implementation.
+
+	  Notes:
+	  - A Processing Element (PE) without the Main Extension
+	  is also referred to as a Baseline Implementation. A
+	  Baseline implementation has a subset of the instructions,
+	  registers, and features, of a Mainline implementation.
+	  - ARMv6-M compatibility is provided by all ARMv8-M
+	  implementations.
+
+config ARMV8_M_BASELINE
+	bool
+	select ARMV6_M_ARMV8_M_BASELINE
+	select CPU_CORTEX_M_HAS_CMSE
+	help
+	  This option signifies the use of an ARMv8-M processor
+	  implementation.
+
+	  ARMv8-M Baseline includes additional features
+	  not present in the ARMv6-M architecture.
+
+config ARMV7_M_ARMV8_M_MAINLINE
+	bool
+	select ATOMIC_OPERATIONS_BUILTIN
+	select ISA_THUMB2
+	select CPU_CORTEX_M_HAS_BASEPRI
+	select CPU_CORTEX_M_HAS_VTOR
+	select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
+	select CPU_CORTEX_M_HAS_SYSTICK
+	help
+	  This option signifies the use of an ARMv7-M processor
+	  implementation, or the use of a backwards-compatible
+	  ARMv8-M processor implementation supporting the Main
+	  Extension.
+
+	  Notes:
+	  - A Processing Element (PE) with the Main Extension is also
+	  referred to as a Mainline Implementation.
+	  - ARMv7-M compatibility requires the Main Extension.
+
+	  From https://developer.arm.com/products/architecture/m-profile:
+	  The Main Extension provides backwards compatibility
+	  with ARMv7-M.
+
+config ARMV8_M_MAINLINE
+	bool
+	select ARMV7_M_ARMV8_M_MAINLINE
+	select CPU_CORTEX_M_HAS_SPLIM
+	select CPU_CORTEX_M_HAS_CMSE
+	help
+	  This option signifies the use of an ARMv8-M processor
+	  implementation, supporting the Main Extension.
+
+	  ARMv8-M Main Extension includes additional features
+	  not present in the ARMv7-M architecture.
+
+config ARMV8_M_SE
+	bool
+	depends on ARMV8_M_BASELINE || ARMV8_M_MAINLINE
+	select CPU_CORTEX_M_HAS_SPLIM if !ARM_NONSECURE_FIRMWARE
+	help
+	  This option signifies the use of an ARMv8-M processor
+	  implementation (Baseline or Mainline) supporting the
+	  Security Extensions.
+
+config ARMV7_M_ARMV8_M_FP
+	bool
+	depends on ARMV7_M_ARMV8_M_MAINLINE && !CPU_CORTEX_M3
+	help
+	  This option signifies the use of an ARMv7-M processor
+	  implementation, or the use of an ARMv8-M processor
+	  implementation supporting the Floating-Point Extension.
+
+config ARMV8_M_DSP
+	bool
+	depends on ARMV8_M_MAINLINE
+	help
+	  This option signifies the use of an ARMv8-M processor
+	  implementation supporting the DSP Extension.
+
+config XIP
+	default y
+
+menu "ARM Cortex-M0/M0+/M3/M4/M7/M23/M33 options"
+    depends on ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE
+
+config GEN_ISR_TABLES
+	default y
+
+config ZERO_LATENCY_IRQS
+	bool "Enable zero-latency interrupts"
+	depends on CPU_CORTEX_M_HAS_BASEPRI
+	help
+	  The kernel may reserve some of the highest interrupts priorities in
+	  the system for its own use. These interrupts will not be masked
+	  by interrupt locking.
+	  When connecting interrupts the kernel will offset all interrupts
+	  to lower priority than those reserved by the kernel.
+	  Zero-latency interrupt can be used to set up an interrupt at the
+	  highest interrupt priority which will not be blocked by interrupt
+	  locking.
+	  Since Zero-latency ISRs will run in the same priority or possibly at
+	  higher priority than the rest of the kernel they cannot use any
+	  kernel functionality.
+
+config DYNAMIC_DIRECT_INTERRUPTS
+	bool "Enable support for dynamic direct interrupts"
+	depends on DYNAMIC_INTERRUPTS
+	help
+	  Direct interrupts are designed for performance-critical interrupt
+	  handling and do not go through all of the common interrupt handling
+	  code. This option enables the installation of interrupt service
+	  routines for direct interrupts at runtime.
+	  Note: this requires enabling support for dynamic interrupts in the
+	  kernel.
+
+config SW_VECTOR_RELAY
+	bool "Enable Software Vector Relay"
+	default y if BOOTLOADER_MCUBOOT
+	depends on ARMV6_M_ARMV8_M_BASELINE && !(CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP || CPU_CORTEX_M_HAS_VTOR)
+	help
+	  Add Vector Table relay handler and relay vector table, to
+	  relay interrupts based on a vector table pointer. This is only
+	  required for Cortex-M0 (or an Armv8-M baseline core) with no hardware
+	  vector table relocation mechanisms or for Cortex-M0+
+	  (or an Armv8-M baseline core) with no VTOR and no other hardware
+	  relocation table mechanisms.
+
+endmenu
+
+endif # CPU_CORTEX_M

arch/arm/core/aarch32/cortex_m/cmse/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(arm_core_cmse.c)

arch/arm/core/aarch32/cortex_m/cmse/arm_core_cmse.c

@@ -5,7 +5,7 @@
  */
 
 #include <zephyr.h>
-#include <cortex_m/cmse.h>
+#include <aarch32/cortex_m/cmse.h>
 
 int arm_cmse_mpu_region_get(u32_t addr)
 {

arch/arm/core/aarch32/cortex_m/irq_init.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief ARM Cortex-M interrupt initialization
+ *
+ */
+
+#include <arch/cpu.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
+
+/**
+ *
+ * @brief Initialize interrupts
+ *
+ * Ensures all interrupts have their priority set to _EXC_IRQ_DEFAULT_PRIO and
+ * not 0, which they have it set to when coming out of reset. This ensures that
+ * interrupt locking via BASEPRI works as expected.
+ *
+ * @return N/A
+ */
+
+void z_arm_int_lib_init(void)
+{
+	int irq = 0;
+
+	for (; irq < CONFIG_NUM_IRQS; irq++) {
+		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
+	}
+}

arch/arm/core/aarch32/cortex_m/mpu/Kconfig

@@ -0,0 +1,102 @@
+# Memory Protection Unit (MPU) configuration options
+
+# Copyright (c) 2017 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+if CPU_HAS_MPU
+
+config ARM_MPU
+	bool "ARM MPU Support"
+	select MEMORY_PROTECTION
+	select THREAD_STACK_INFO
+	select ARCH_HAS_EXECUTABLE_PAGE_BIT
+	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(CPU_HAS_NXP_MPU || ARMV8_M_BASELINE || ARMV8_M_MAINLINE)
+	select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if CPU_HAS_ARM_MPU && (ARMV8_M_BASELINE || ARMV8_M_MAINLINE)
+	help
+	  MCU implements Memory Protection Unit.
+
+	  Notes:
+	  The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
+	  alignment of MPU region base address and size.
+
+	  The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
+	  to have power-of-two alignment for base address and region size.
+
+	  The ARMv8-M MPU requires the active MPU regions be non-overlapping.
+	  As a result of this, the ARMv8-M MPU needs to fully partition the
+	  memory map when programming dynamic memory regions (e.g. PRIV stack
+	  guard, user thread stack, and application memory domains), if the
+	  system requires PRIV access policy different from the access policy
+	  of the ARMv8-M background memory map. The application developer may
+	  enforce full PRIV (kernel) memory partition by enabling the
+	  CONFIG_MPU_GAP_FILLING option.
+	  By not enforcing full partition, MPU may leave part of kernel
+	  SRAM area covered only by the default ARMv8-M memory map. This
+	  is fine for User Mode, since the background ARM map does not
+	  allow nPRIV access at all. However, since the background map
+	  policy allows instruction fetches by privileged code, forcing
+	  this Kconfig option off prevents the system from directly
+	  triggering MemManage exceptions upon accidental attempts to
+	  execute code from SRAM in XIP builds.
+	  Since this does not compromise User Mode, we make the skipping
+	  of full partitioning the default behavior for the ARMv8-M MPU
+	  driver.
+
+config ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
+	int
+	default 256 if ARM_MPU && ARMV6_M_ARMV8_M_BASELINE && !ARMV8_M_BASELINE
+	default 32 if ARM_MPU
+	default 4
+	help
+	  Minimum size (and alignment) of an ARM MPU region. Use this
+	  symbol to guarantee minimum size and alignment of MPU regions.
+	  A minimum 4-byte alignment is enforced in ARM builds without
+	  support for Memory Protection.
+
+if ARM_MPU
+
+config MPU_STACK_GUARD
+	bool "Thread Stack Guards"
+	help
+	  Enable Thread Stack Guards via MPU
+
+config MPU_STACK_GUARD_MIN_SIZE_FLOAT
+	int
+	depends on MPU_STACK_GUARD
+	depends on FP_SHARING
+	default 128
+	help
+	  Minimum size (and alignment when applicable) of an ARM MPU
+	  region, which guards the stack of a thread that is using the
+	  Floating Point (FP) context. The width of the guard is set to
+	  128, to accommodate the length of a Cortex-M exception stack
+	  frame when the floating point context is active. The FP context
+	  is only stacked in sharing FP registers mode, therefore, the
+	  option is applicable only when FP_SHARING is selected.
+
+config MPU_ALLOW_FLASH_WRITE
+	bool "Add MPU access to write to flash"
+	help
+	  Enable this to allow MPU RWX access to flash memory
+
+config CUSTOM_SECTION_ALIGN
+	bool "Custom Section Align"
+	help
+	  MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT(ARMv7-M) sometimes cause memory
+	  wasting in linker scripts defined memory sections. Use this symbol
+	  to guarantee user custom section align size to avoid more memory used
+	  for respect alignment. But that needs carefully configure MPU region
+	  and sub-regions(ARMv7-M) to cover this feature.
+
+config CUSTOM_SECTION_MIN_ALIGN_SIZE
+	int "Custom Section Align Size"
+	default 32
+	help
+	  Custom align size of memory section in linker scripts. Usually
+	  it should consume less alignment memory. Although this alignment
+	  size is configured by users, it must also respect the power of
+	  two regulation if hardware requires.
+
+endif # ARM_MPU
+
+endif # CPU_HAS_MPU

arch/arm/core/aarch32/cortex_m/mpu/arm_core_mpu.c

@@ -23,7 +23,7 @@ LOG_MODULE_REGISTER(mpu);
  * available MPU regions for dynamic programming depends on the number of the
  * static MPU regions currently being programmed, and the total number of HW-
  * available MPU regions. This macro is only used internally in function
- * z_arch_configure_dynamic_mpu_regions(), to reserve sufficient area for the
+ * z_arm_configure_dynamic_mpu_regions(), to reserve sufficient area for the
  * array of dynamic regions passed to the underlying driver.
  */
 #if defined(CONFIG_USERSPACE)
@@ -59,7 +59,7 @@ LOG_MODULE_REGISTER(mpu);
  * For some MPU architectures, such as the unmodified ARMv8-M MPU,
  * the function must execute with MPU enabled.
  */
-void z_arch_configure_static_mpu_regions(void)
+void z_arm_configure_static_mpu_regions(void)
 {
 #if defined(CONFIG_COVERAGE_GCOV) && defined(CONFIG_USERSPACE)
 		const struct k_mem_partition gcov_region =
@@ -142,7 +142,7 @@ void z_arch_configure_static_mpu_regions(void)
  * For some MPU architectures, such as the unmodified ARMv8-M MPU,
  * the function must execute with MPU enabled.
  */
-void z_arch_configure_dynamic_mpu_regions(struct k_thread *thread)
+void z_arm_configure_dynamic_mpu_regions(struct k_thread *thread)
 {
 	/* Define an array of k_mem_partition objects to hold the configuration
 	 * of the respective dynamic MPU regions to be programmed for
@@ -259,13 +259,7 @@ void z_arch_configure_dynamic_mpu_regions(struct k_thread *thread)
 }
 
 #if defined(CONFIG_USERSPACE)
-
-/**
- * @brief Get the maximum number of partitions for a memory domain
- *        that is supported by the MPU hardware, and with respect
- *        to the current static memory region configuration.
- */
-int z_arch_mem_domain_max_partitions_get(void)
+int arch_mem_domain_max_partitions_get(void)
 {
 	int available_regions = arm_core_mpu_get_max_available_dyn_regions();
 
@@ -280,10 +274,7 @@ int z_arch_mem_domain_max_partitions_get(void)
 	return ARM_CORE_MPU_MAX_DOMAIN_PARTITIONS_GET(available_regions);
 }
 
-/**
- * @brief Configure the memory domain of the thread.
- */
-void z_arch_mem_domain_thread_add(struct k_thread *thread)
+void arch_mem_domain_thread_add(struct k_thread *thread)
 {
 	if (_current != thread) {
 		return;
@@ -293,16 +284,10 @@ void z_arch_mem_domain_thread_add(struct k_thread *thread)
 	 * This triggers re-programming of the entire dynamic
 	 * memory map.
 	 */
-	z_arch_configure_dynamic_mpu_regions(thread);
+	z_arm_configure_dynamic_mpu_regions(thread);
 }
 
-/*
- * @brief Reset the MPU configuration related to the memory domain
- *        partitions
- *
- * @param domain pointer to the memory domain (must be valid)
- */
-void z_arch_mem_domain_destroy(struct k_mem_domain *domain)
+void arch_mem_domain_destroy(struct k_mem_domain *domain)
 {
 	/* This function will reset the access permission configuration
 	 * of the active partitions of the memory domain.
@@ -332,15 +317,8 @@ void z_arch_mem_domain_destroy(struct k_mem_domain *domain)
 	}
 }
 
-/*
- * @brief Remove a partition from the memory domain
- *
- * @param domain pointer to the memory domain (must be valid
- * @param partition_id the ID (sequence) number of the memory domain
- *        partition (must be a valid partition).
- */
-void z_arch_mem_domain_partition_remove(struct k_mem_domain *domain,
-				       u32_t  partition_id)
+void arch_mem_domain_partition_remove(struct k_mem_domain *domain,
+				      u32_t partition_id)
 {
 	/* Request to remove a partition from a memory domain.
 	 * This resets the access permissions of the partition
@@ -356,25 +334,22 @@ void z_arch_mem_domain_partition_remove(struct k_mem_domain *domain,
 		&domain->partitions[partition_id], &reset_attr);
 }
 
-void z_arch_mem_domain_partition_add(struct k_mem_domain *domain,
-				    u32_t partition_id)
+void arch_mem_domain_partition_add(struct k_mem_domain *domain,
+				   u32_t partition_id)
 {
 	/* No-op on this architecture */
 }
 
-void z_arch_mem_domain_thread_remove(struct k_thread *thread)
+void arch_mem_domain_thread_remove(struct k_thread *thread)
 {
 	if (_current != thread) {
 		return;
 	}
 
-	z_arch_mem_domain_destroy(thread->mem_domain_info.mem_domain);
+	arch_mem_domain_destroy(thread->mem_domain_info.mem_domain);
 }
 
-/*
- * Validate the given buffer is user accessible or not
- */
-int z_arch_buffer_validate(void *addr, size_t size, int write)
+int arch_buffer_validate(void *addr, size_t size, int write)
 {
 	return arm_core_mpu_buffer_validate(addr, size, write);
 }

arch/arm/core/aarch32/cortex_m/mpu/arm_core_mpu_dev.h

@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_
-#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_
+#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_
 
 #include <zephyr/types.h>
 
@@ -28,7 +28,8 @@ struct k_thread;
  *
  * @param mpu_regions_num the number of available HW MPU regions.
  */
-#if defined(CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS)
+#if defined(CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS) && \
+	defined(CONFIG_MPU_GAP_FILLING)
 /*
  * For ARM MPU architectures, where the domain partitions cannot be defined
  * on top of the statically configured memory regions, the maximum number of
@@ -53,7 +54,8 @@ struct k_thread;
  * @brief Maximum number of MPU regions required to configure a
  *        memory region for (user) Thread Stack.
  */
-#if defined(CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS)
+#if defined(CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS) && \
+	defined(CONFIG_MPU_GAP_FILLING)
 /* When dynamic regions may not be defined on top of statically
  * allocated memory regions, defining a region for a thread stack
  * requires two additional MPU regions to be configured; one for
@@ -73,7 +75,8 @@ struct k_thread;
  * @brief Maximum number of MPU regions required to configure a
  *        memory region for a (supervisor) Thread Stack Guard.
  */
-#if defined(CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS) \
+#if (defined(CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS) && \
+		defined(CONFIG_MPU_GAP_FILLING)) \
 	|| defined(CONFIG_CPU_HAS_NXP_MPU)
 /*
  * When dynamic regions may not be defined on top of statically
@@ -265,4 +268,4 @@ int arm_core_mpu_buffer_validate(void *addr, size_t size, int write);
 }
 #endif
 
-#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_ */

arch/arm/core/aarch32/cortex_m/mpu/arm_mpu.c

@@ -9,7 +9,6 @@
 #include <kernel.h>
 #include <soc.h>
 #include "arm_core_mpu_dev.h"
-#include <arch/arm/cortex_m/mpu/arm_core_mpu.h>
 #include <linker/linker-defs.h>
 
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
@@ -100,6 +99,45 @@ static int mpu_configure_region(const u8_t index,
 		(const struct arm_mpu_region *)&region_conf);
 }
 
+#if !defined(CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS) || \
+	!defined(CONFIG_MPU_GAP_FILLING)
+/* This internal function programs a set of given MPU regions
+ * over a background memory area, optionally performing a
+ * sanity check of the memory regions to be programmed.
+ */
+static int mpu_configure_regions(const struct k_mem_partition
+	*regions[], u8_t regions_num, u8_t start_reg_index,
+	bool do_sanity_check)
+{
+	int i;
+	int reg_index = start_reg_index;
+
+	for (i = 0; i < regions_num; i++) {
+		if (regions[i]->size == 0U) {
+			continue;
+		}
+		/* Non-empty region. */
+
+		if (do_sanity_check &&
+				(!mpu_partition_is_valid(regions[i]))) {
+			LOG_ERR("Partition %u: sanity check failed.", i);
+			return -EINVAL;
+		}
+
+		reg_index = mpu_configure_region(reg_index, regions[i]);
+
+		if (reg_index == -EINVAL) {
+			return reg_index;
+		}
+
+		/* Increment number of programmed MPU indices. */
+		reg_index++;
+	}
+
+	return reg_index;
+}
+#endif
+
 /* ARM Core MPU Driver API Implementation for ARM MPU */
 
 /**

arch/arm/core/aarch32/cortex_m/mpu/arm_mpu_v7_internal.h

@@ -5,10 +5,12 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_
-#define ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_
+#ifndef ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_
+#define ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_
 
 
+#include <sys/math_extras.h>
+
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
 #include <logging/log.h>
 
@@ -151,8 +153,16 @@ static inline u32_t mpu_region_get_size(u32_t index)
  */
 static inline int is_enabled_region(u32_t index)
 {
+	/* Lock IRQs to ensure RNR value is correct when reading RASR. */
+	unsigned int key;
+	u32_t rasr;
+
+	key = irq_lock();
 	MPU->RNR = index;
-	return (MPU->RASR & MPU_RASR_ENABLE_Msk) ? 1 : 0;
+	rasr = MPU->RASR;
+	irq_unlock(key);
+
+	return (rasr & MPU_RASR_ENABLE_Msk) ? 1 : 0;
 }
 
 /* Only a single bit is set for all user accessible permissions.
@@ -169,8 +179,16 @@ static inline int is_enabled_region(u32_t index)
  */
 static inline u32_t get_region_ap(u32_t r_index)
 {
+	/* Lock IRQs to ensure RNR value is correct when reading RASR. */
+	unsigned int key;
+	u32_t rasr;
+
+	key = irq_lock();
 	MPU->RNR = r_index;
-	return (MPU->RASR & MPU_RASR_AP_Msk) >> MPU_RASR_AP_Pos;
+	rasr = MPU->RASR;
+	irq_unlock(key);
+
+	return (rasr & MPU_RASR_AP_Msk) >> MPU_RASR_AP_Pos;
 }
 
 /**
@@ -184,14 +202,29 @@ static inline int is_in_region(u32_t r_index, u32_t start, u32_t size)
 	u32_t r_addr_start;
 	u32_t r_size_lshift;
 	u32_t r_addr_end;
+	u32_t end;
 
+	/* Lock IRQs to ensure RNR value is correct when reading RBAR, RASR. */
+	unsigned int key;
+	u32_t rbar, rasr;
+
+	key = irq_lock();
 	MPU->RNR = r_index;
-	r_addr_start = MPU->RBAR & MPU_RBAR_ADDR_Msk;
-	r_size_lshift = ((MPU->RASR & MPU_RASR_SIZE_Msk) >>
+	rbar = MPU->RBAR;
+	rasr = MPU->RASR;
+	irq_unlock(key);
+
+	r_addr_start = rbar & MPU_RBAR_ADDR_Msk;
+	r_size_lshift = ((rasr & MPU_RASR_SIZE_Msk) >>
 			MPU_RASR_SIZE_Pos) + 1;
 	r_addr_end = r_addr_start + (1UL << r_size_lshift) - 1;
 
-	if (start >= r_addr_start && (start + size - 1) <= r_addr_end) {
+	size = size == 0 ? 0 : size - 1;
+	if (u32_add_overflow(start, size, &end)) {
+		return 0;
+	}
+
+	if ((start >= r_addr_start) && (end <= r_addr_end)) {
 		return 1;
 	}
 
@@ -252,41 +285,9 @@ static inline int mpu_buffer_validate(void *addr, size_t size, int write)
 static int mpu_configure_region(const u8_t index,
 	const struct k_mem_partition *new_region);
 
-/* This internal function programs a set of given MPU regions
- * over a background memory area, optionally performing a
- * sanity check of the memory regions to be programmed.
- */
 static int mpu_configure_regions(const struct k_mem_partition
 	*regions[], u8_t regions_num, u8_t start_reg_index,
-	bool do_sanity_check)
-{
-	int i;
-	int reg_index = start_reg_index;
-
-	for (i = 0; i < regions_num; i++) {
-		if (regions[i]->size == 0U) {
-			continue;
-		}
-		/* Non-empty region. */
-
-		if (do_sanity_check &&
-				(!mpu_partition_is_valid(regions[i]))) {
-			LOG_ERR("Partition %u: sanity check failed.", i);
-			return -EINVAL;
-		}
-
-		reg_index = mpu_configure_region(reg_index, regions[i]);
-
-		if (reg_index == -EINVAL) {
-			return reg_index;
-		}
-
-		/* Increment number of programmed MPU indices. */
-		reg_index++;
-	}
-
-	return reg_index;
-}
+	bool do_sanity_check);
 
 /* This internal function programs the static MPU regions.
  *
@@ -348,4 +349,4 @@ static int mpu_configure_dynamic_mpu_regions(const struct k_mem_partition
 	return mpu_reg_index;
 }
 
-#endif	/* ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_ */
+#endif	/* ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_ */

arch/arm/core/aarch32/cortex_m/mpu/arm_mpu_v8_internal.h

@@ -5,10 +5,10 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_
-#define ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_
+#ifndef ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_
+#define ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_
 
-#include <cmse.h>
+#include <aarch32/cortex_m/cmse.h>
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
 #include <logging/log.h>
 
@@ -318,11 +318,20 @@ static int region_allocate_and_init(const u8_t index,
 static int mpu_configure_region(const u8_t index,
 	const struct k_mem_partition *new_region);
 
+#if !defined(CONFIG_MPU_GAP_FILLING)
+static int mpu_configure_regions(const struct k_mem_partition
+	*regions[], u8_t regions_num, u8_t start_reg_index,
+	bool do_sanity_check);
+#endif
+
 /* This internal function programs a set of given MPU regions
  * over a background memory area, optionally performing a
  * sanity check of the memory regions to be programmed.
+ *
+ * The function performs a full partition of the background memory
+ * area, effectively, leaving no space in this area uncovered by MPU.
  */
-static int mpu_configure_regions(const struct k_mem_partition
+static int mpu_configure_regions_and_partition(const struct k_mem_partition
 	*regions[], u8_t regions_num, u8_t start_reg_index,
 	bool do_sanity_check)
 {
@@ -472,7 +481,7 @@ static int mpu_configure_static_mpu_regions(const struct k_mem_partition
 	ARG_UNUSED(background_area_base);
 	ARG_UNUSED(background_area_end);
 
-	mpu_reg_index = mpu_configure_regions(static_regions,
+	mpu_reg_index = mpu_configure_regions_and_partition(static_regions,
 		regions_num, mpu_reg_index, true);
 
 	static_regions_num = mpu_reg_index;
@@ -539,6 +548,7 @@ static int mpu_configure_dynamic_mpu_regions(const struct k_mem_partition
 		ARM_MPU_ClrRegion(i);
 	}
 
+#if defined(CONFIG_MPU_GAP_FILLING)
 	/* Reset MPU regions inside which dynamic memory regions may
 	 * be programmed.
 	 */
@@ -551,11 +561,26 @@ static int mpu_configure_dynamic_mpu_regions(const struct k_mem_partition
 	 * forming a full partition of the background area, specified by the
 	 * given boundaries.
 	 */
+	mpu_reg_index = mpu_configure_regions_and_partition(dynamic_regions,
+		regions_num, mpu_reg_index, true);
+#else
 
+	/* We are going to skip the full partition of the background areas.
+	 * So we can disable MPU regions inside which dynamic memroy regions
+	 * may be programmed.
+	 */
+	for (int i = 0; i < MPU_DYNAMIC_REGION_AREAS_NUM; i++) {
+		ARM_MPU_ClrRegion(dyn_reg_info[i].index);
+	}
+
+	/* The dynamic regions are now programmed on top of
+	 * existing SRAM region configuration.
+	 */
 	mpu_reg_index = mpu_configure_regions(dynamic_regions,
 		regions_num, mpu_reg_index, true);
 
+#endif /* CONFIG_MPU_GAP_FILLING */
 	return mpu_reg_index;
 }
 
-#endif	/* ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_ */
+#endif	/* ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_ */

arch/arm/core/aarch32/cortex_m/mpu/nxp_mpu.c

@@ -9,8 +9,8 @@
 #include <kernel.h>
 #include <soc.h>
 #include "arm_core_mpu_dev.h"
-#include <arch/arm/cortex_m/mpu/arm_core_mpu.h>
 #include <sys/__assert.h>
+#include <sys/math_extras.h>
 #include <linker/linker-defs.h>
 
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
@@ -429,11 +429,17 @@ static inline int is_in_region(u32_t r_index, u32_t start, u32_t size)
 {
 	u32_t r_addr_start;
 	u32_t r_addr_end;
+	u32_t end;
 
 	r_addr_start = SYSMPU->WORD[r_index][0];
 	r_addr_end = SYSMPU->WORD[r_index][1];
 
-	if (start >= r_addr_start && (start + size - 1) <= r_addr_end) {
+	size = size == 0 ? 0 : size - 1;
+	if (u32_add_overflow(start, size, &end)) {
+		return 0;
+	}
+
+	if ((start >= r_addr_start) && (end <= r_addr_end)) {
 		return 1;
 	}
 

arch/arm/core/aarch32/cortex_m/relay_vector_table.ld

@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2019 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+KEEP(*(.vector_relay_table))
+KEEP(*(".vector_relay_table.*"))
+KEEP(*(.vector_relay_handler))
+KEEP(*(".vector_relay_handler.*"))

arch/arm/core/aarch32/cortex_m/reset.S

@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2013-2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Reset handler
+ *
+ * Reset handler that prepares the system for running C code.
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <arch/cpu.h>
+#include "vector_table.h"
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(z_arm_reset)
+GTEXT(memset)
+GDATA(_interrupt_stack)
+#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
+GTEXT(z_platform_init)
+#endif
+
+/**
+ *
+ * @brief Reset vector
+ *
+ * Ran when the system comes out of reset. The processor is in thread mode with
+ * privileged level. At this point, the main stack pointer (MSP) is already
+ * pointing to a valid area in SRAM.
+ *
+ * Locking interrupts prevents anything but NMIs and hard faults from
+ * interrupting the CPU. A default NMI handler is already in place in the
+ * vector table, and the boot code should not generate hard fault, or we're in
+ * deep trouble.
+ *
+ * We want to use the process stack pointer (PSP) instead of the MSP, since the
+ * MSP is to be set up to point to the one-and-only interrupt stack during
+ * later boot. That would not be possible if in use for running C code.
+ *
+ * When these steps are completed, jump to z_arm_prep_c(), which will finish
+ * setting up the system for running C code.
+ *
+ * @return N/A
+ */
+
+SECTION_SUBSEC_FUNC(TEXT,_reset_section,z_arm_reset)
+
+/*
+ * The entry point is located at the z_arm_reset symbol, which
+ * is fetched by a XIP image playing the role of a bootloader, which jumps to
+ * it, not through the reset vector mechanism. Such bootloaders might want to
+ * search for a __start symbol instead, so create that alias here.
+ */
+SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
+
+#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
+    bl z_platform_init
+#endif
+
+    /* lock interrupts: will get unlocked when switch to main task */
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+    cpsid i
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
+    msr BASEPRI, r0
+#else
+#error Unknown ARM architecture
+#endif
+
+#ifdef CONFIG_WDOG_INIT
+    /* board-specific watchdog initialization is necessary */
+    bl z_arm_watchdog_init
+#endif
+
+#ifdef CONFIG_INIT_STACKS
+    ldr r0, =_interrupt_stack
+    ldr r1, =0xaa
+    ldr r2, =CONFIG_ISR_STACK_SIZE
+    bl memset
+#endif
+
+    /*
+     * Set PSP and use it to boot without using MSP, so that it
+     * gets set to _interrupt_stack during initialization.
+     */
+    ldr r0, =_interrupt_stack
+    ldr r1, =CONFIG_ISR_STACK_SIZE
+    adds r0, r0, r1
+    msr PSP, r0
+    mrs r0, CONTROL
+    movs r1, #2
+    orrs r0, r1 /* CONTROL_SPSEL_Msk */
+    msr CONTROL, r0
+    /*
+     * When changing the stack pointer, software must use an ISB instruction
+     * immediately after the MSR instruction. This ensures that instructions
+     * after the ISB instruction execute using the new stack pointer.
+     */
+    isb
+
+    /*
+     * 'bl' jumps the furthest of the branch instructions that are
+     * supported on all platforms. So it is used when jumping to z_arm_prep_c
+     * (even though we do not intend to return).
+     */
+    bl z_arm_prep_c

arch/arm/core/aarch32/cortex_m/scb.c

@@ -17,7 +17,7 @@
 #include <kernel.h>
 #include <arch/cpu.h>
 #include <sys/util.h>
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 
 /**
  *

arch/arm/core/aarch32/cortex_m/thread_abort.c

@@ -17,7 +17,6 @@
  */
 
 #include <kernel.h>
-#include <kernel_structs.h>
 #include <toolchain.h>
 #include <linker/sections.h>
 #include <ksched.h>

arch/arm/core/aarch32/cortex_m/tz/CMakeLists.txt

@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# '-mcmse' enables the generation of code for the Secure state of the ARMv8-M
+# Security Extensions. This option is required when building a Secure firmware.
+zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE -mcmse)
+
+if(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)
+
+  # --out-implib and --cmse-implib instruct the linker to produce
+  # an import library that consists of a relocatable file containing
+  # only a symbol table with the entry veneers. The library may be used
+  # when building a Non-Secure image which shall have access to Secure
+  # Entry functions.
+  zephyr_ld_options(
+    ${LINKERFLAGPREFIX},--out-implib=${CMAKE_BINARY_DIR}/${CONFIG_ARM_ENTRY_VENEERS_LIB_NAME}
+  )
+
+  zephyr_ld_options(
+    ${LINKERFLAGPREFIX},--cmse-implib
+  )
+
+  # Indicate that the entry veneers library file is created during linking of this firmware.
+  set_property(
+    GLOBAL APPEND PROPERTY
+    extra_post_build_byproducts
+    ${CMAKE_BINARY_DIR}/${CONFIG_ARM_ENTRY_VENEERS_LIB_NAME}
+    )
+
+  zephyr_linker_sources(SECTIONS SORT_KEY z_end secure_entry_functions.ld)
+endif()
+
+# Link the entry veneers library file with the Non-Secure Firmware that needs it.
+zephyr_link_libraries_ifdef(CONFIG_ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS
+  ${CMAKE_BINARY_DIR}/${CONFIG_ARM_ENTRY_VENEERS_LIB_NAME}
+  )
+
+if(CONFIG_ARM_SECURE_FIRMWARE)
+  zephyr_library()
+
+  zephyr_library_sources(arm_core_tz.c)
+endif()

arch/arm/core/aarch32/cortex_m/tz/Kconfig

@@ -0,0 +1,11 @@
+# ARM TrustZone-M core configuration options
+
+# Copyright (c) 2018 Nordic Semiconductor ASA.
+# SPDX-License-Identifier: Apache-2.0
+
+config ARM_TRUSTZONE_M
+	bool "ARM TrustZone-M support"
+	depends on CPU_HAS_TEE
+	depends on ARMV8_M_SE
+	help
+	  Platform has support for ARM TrustZone-M.

arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c

@@ -4,9 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <arch/arm/cortex_m/cmsis.h>
-#include <cortex_m/tz.h>
-#include <cortex_m/exc.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
+#include <aarch32/cortex_m/tz.h>
+#include <aarch32/cortex_m/exc.h>
 
 static void configure_nonsecure_vtor_offset(u32_t vtor_ns)
 {

arch/arm/core/aarch32/cortex_m/tz/secure_entry_functions.ld

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0
+	#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)
+#elif defined(CONFIG_CPU_HAS_NRF_IDAU)
+	/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. */
+	#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))
+#else
+	#define NSC_ALIGN . = ALIGN(4)
+#endif
+
+#ifdef CONFIG_CPU_HAS_NRF_IDAU
+	#define NSC_ALIGN_END . = ALIGN(0x8000)
+#else
+	#define NSC_ALIGN_END . = ALIGN(4)
+#endif
+
+SECTION_PROLOGUE(.gnu.sgstubs,,)
+{
+	NSC_ALIGN;
+	__sg_start = .;
+	/* No input section necessary, since the Secure Entry Veneers are
+	   automatically placed after the .gnu.sgstubs output section. */
+} GROUP_LINK_IN(ROMABLE_REGION)
+__sg_end = .;
+__sg_size = __sg_end - __sg_start;
+NSC_ALIGN_END;
+__nsc_size = . - __sg_start;
+
+#ifdef CONFIG_CPU_HAS_NRF_IDAU
+	ASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))
+			 == (0x8000 - (__sg_start % 0x8000))
+		&& (0x8000 - (__sg_start % 0x8000)) >= 32
+		&& (0x8000 - (__sg_start % 0x8000)) <= 4096,
+		"The Non-Secure Callable region size must be a power of 2 \
+between 32 and 4096 bytes.")
+#endif

arch/arm/core/aarch32/cortex_m/vector_table.S

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2013-2015 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Populated vector table in ROM
+ *
+ * Vector table at the beginning of the image for starting system. The reset
+ * vector is the system entry point, ie. the first instruction executed.
+ *
+ * The table is populated with all the system exception handlers. The NMI vector
+ * must be populated with a valid handler since it can happen at any time. The
+ * rest should not be triggered until the kernel is ready to handle them.
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include "vector_table.h"
+
+_ASM_FILE_PROLOGUE
+
+GDATA(z_main_stack)
+
+SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
+
+    /*
+     * setting the _very_ early boot on the main stack allows to use memset
+     * on the interrupt stack when CONFIG_INIT_STACKS is enabled before
+     * switching to the interrupt stack for the rest of the early boot
+     */
+    .word z_main_stack + CONFIG_MAIN_STACK_SIZE
+
+    .word z_arm_reset
+    .word z_arm_nmi
+
+    .word z_arm_hard_fault
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+    .word z_arm_reserved
+    .word z_arm_reserved
+    .word z_arm_reserved
+    .word z_arm_reserved
+    .word z_arm_reserved
+    .word z_arm_reserved
+    .word z_arm_reserved
+    .word z_arm_svc
+    .word z_arm_reserved
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+    .word z_arm_mpu_fault
+    .word z_arm_bus_fault
+    .word z_arm_usage_fault
+#if defined(CONFIG_ARM_SECURE_FIRMWARE)
+    .word z_arm_secure_fault
+#else
+    .word z_arm_reserved
+#endif /* CONFIG_ARM_SECURE_FIRMWARE */
+    .word z_arm_reserved
+    .word z_arm_reserved
+    .word z_arm_reserved
+    .word z_arm_svc
+    .word z_arm_debug_monitor
+#else
+#error Unknown ARM architecture
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+    .word z_arm_reserved
+    .word z_arm_pendsv
+#if defined(CONFIG_SYS_CLOCK_EXISTS)
+    .word z_clock_isr
+#else
+    .word z_arm_reserved
+#endif
+

arch/arm/core/aarch32/cortex_m/vector_table.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2013-2015 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Definitions for the boot vector table
+ *
+ *
+ * Definitions for the boot vector table.
+ *
+ * System exception handler names all have the same format:
+ *
+ *   __<exception name with underscores>
+ *
+ * No other symbol has the same format, so they are easy to spot.
+ */
+
+#ifndef ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_VECTOR_TABLE_H_
+#define ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_VECTOR_TABLE_H_
+
+#ifdef _ASMLANGUAGE
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <sys/util.h>
+
+GTEXT(__start)
+GTEXT(_vector_table)
+
+GTEXT(z_arm_reset)
+GTEXT(z_arm_nmi)
+GTEXT(z_arm_hard_fault)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+GTEXT(z_arm_svc)
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+GTEXT(z_arm_mpu_fault)
+GTEXT(z_arm_bus_fault)
+GTEXT(z_arm_usage_fault)
+#if defined(CONFIG_ARM_SECURE_FIRMWARE)
+GTEXT(z_arm_secure_fault)
+#endif /* CONFIG_ARM_SECURE_FIRMWARE */
+GTEXT(z_arm_svc)
+GTEXT(z_arm_debug_monitor)
+#else
+#error Unknown ARM architecture
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+GTEXT(z_arm_pendsv)
+GTEXT(z_arm_reserved)
+
+GTEXT(z_arm_prep_c)
+GTEXT(_isr_wrapper)
+
+#else /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void *_vector_table[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_VECTOR_TABLE_H_ */

arch/arm/core/aarch32/cortex_r/Kconfig

@@ -0,0 +1,87 @@
+# ARM Cortex-R platform configuration options
+
+# Copyright (c) 2018 Marvell
+# Copyright (c) 2018 Lexmark International, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# NOTE: We have the specific core implementations first and outside of the
+# if CPU_CORTEX_R block so that SoCs can select which core they are using
+# without having to select all the options related to that core.  Everything
+# else is captured inside the if CPU_CORTEX_R block so they are not exposed
+# if one selects a different ARM Cortex Family (Cortex-A or Cortex-M)
+
+
+config CPU_CORTEX_R4
+	bool
+	select CPU_CORTEX_R
+	select ARMV7_R
+	select ARMV7_R_FP if CPU_HAS_FPU
+	help
+	  This option signifies the use of a Cortex-R4 CPU
+
+config CPU_CORTEX_R5
+	bool
+	select CPU_CORTEX_R
+	select ARMV7_R
+	select ARMV7_R_FP if CPU_HAS_FPU
+	help
+	  This option signifies the use of a Cortex-R5 CPU
+
+if CPU_CORTEX_R
+
+config ARMV7_R
+	bool
+	select ATOMIC_OPERATIONS_BUILTIN
+	select ISA_ARM
+	help
+	  This option signifies the use of an ARMv7-R processor
+	  implementation.
+
+	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
+	  The Armv7-R architecture implements a traditional Arm architecture with
+	  multiple modes and supports a Protected Memory System Architecture
+	  (PMSA) based on a Memory Protection Unit (MPU). It supports the Arm (32)
+	  and Thumb (T32) instruction sets.
+
+config ARMV7_R_FP
+	bool
+	depends on ARMV7_R
+	help
+	  This option signifies the use of an ARMv7-R processor
+	  implementation supporting the Floating-Point Extension.
+
+config ARMV7_EXCEPTION_STACK_SIZE
+	int "Undefined Instruction and Abort stack size (in bytes)"
+	default 256
+	help
+	  This option specifies the size of the stack used by the undefined
+	  instruction and data abort exception handlers.
+
+config ARMV7_FIQ_STACK_SIZE
+	int "FIQ stack size (in bytes)"
+	default 256
+	help
+	  This option specifies the size of the stack used by the FIQ handler.
+
+config ARMV7_SVC_STACK_SIZE
+	int "SVC stack size (in bytes)"
+	default 512
+	help
+	  This option specifies the size of the stack used by the SVC handler.
+
+config ARMV7_SYS_STACK_SIZE
+	int "SYS stack size (in bytes)"
+	default 1024
+	help
+	  This option specifies the size of the stack used by the system mode.
+
+config RUNTIME_NMI
+	default y
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+endif # CPU_CORTEX_R

arch/arm/core/aarch32/cortex_r/fault.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2018 Lexmark International, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <kernel_internal.h>
+#include <kernel_structs.h>
+
+/**
+ *
+ * @brief Fault handler
+ *
+ * This routine is called when fatal error conditions are detected by hardware
+ * and is responsible only for reporting the error. Once reported, it then
+ * invokes the user provided routine _SysFatalErrorHandler() which is
+ * responsible for implementing the error handling policy.
+ *
+ * This is a stub for more exception handling code to be added later.
+ */
+void z_arm_fault(z_arch_esf_t *esf, u32_t exc_return)
+{
+	z_arm_fatal_error(K_ERR_CPU_EXCEPTION, esf);
+}
+
+void z_arm_fault_init(void)
+{
+}

arch/arm/core/aarch32/cortex_r/reboot.c

@@ -11,7 +11,7 @@
 
 #include <kernel.h>
 #include <arch/cpu.h>
-#include <misc/util.h>
+#include <sys/util.h>
 
 /**
  *

arch/arm/core/aarch32/cortex_r/reset.S

@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2013-2014 Wind River Systems, Inc.
+ * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Reset handler
+ *
+ * Reset handler that prepares the system for running C code.
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <arch/cpu.h>
+#include <offsets_short.h>
+#include "vector_table.h"
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(z_arm_reset)
+GDATA(_interrupt_stack)
+GDATA(z_arm_svc_stack)
+GDATA(z_arm_sys_stack)
+GDATA(z_arm_fiq_stack)
+GDATA(z_arm_abort_stack)
+GDATA(z_arm_undef_stack)
+#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
+GTEXT(z_platform_init)
+#endif
+
+/**
+ *
+ * @brief Reset vector
+ *
+ * Ran when the system comes out of reset. The processor is in Supervisor mode
+ * and interrupts are disabled. The processor architectural registers are in
+ * an indeterminate state.
+ *
+ * When these steps are completed, jump to z_arm_prep_c(), which will finish
+ * setting up the system for running C code.
+ *
+ * @return N/A
+ */
+SECTION_SUBSEC_FUNC(TEXT, _reset_section, z_arm_reset)
+SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)
+
+#if defined(CONFIG_CPU_HAS_DCLS)
+    /*
+     * Initialise CPU registers to a defined state if the processor is
+     * configured as Dual-redundant Core Lock-step (DCLS). This is required
+     * for state convergence of the two parallel executing cores.
+     */
+
+    /* Common and SVC mode registers */
+    mov r0,  #0
+    mov r1,  #0
+    mov r2,  #0
+    mov r3,  #0
+    mov r4,  #0
+    mov r5,  #0
+    mov r6,  #0
+    mov r7,  #0
+    mov r8,  #0
+    mov r9,  #0
+    mov r10, #0
+    mov r11, #0
+    mov r12, #0
+    mov r13, #0         /* r13_svc */
+    mov r14, #0         /* r14_svc */
+    mrs r0,  cpsr
+    msr spsr_cxsf, r0   /* spsr_svc */
+
+    /* FIQ mode registers */
+    cps #MODE_FIQ
+    mov r8,  #0         /* r8_fiq */
+    mov r9,  #0         /* r9_fiq */
+    mov r10, #0         /* r10_fiq */
+    mov r11, #0         /* r11_fiq */
+    mov r12, #0         /* r12_fiq */
+    mov r13, #0         /* r13_fiq */
+    mov r14, #0         /* r14_fiq */
+    mrs r0,  cpsr
+    msr spsr_cxsf, r0   /* spsr_fiq */
+
+    /* IRQ mode registers */
+    cps #MODE_IRQ
+    mov r13, #0         /* r13_irq */
+    mov r14, #0         /* r14_irq */
+    mrs r0,  cpsr
+    msr spsr_cxsf, r0   /* spsr_irq */
+
+    /* ABT mode registers */
+    cps #MODE_ABT
+    mov r13, #0         /* r13_abt */
+    mov r14, #0         /* r14_abt */
+    mrs r0,  cpsr
+    msr spsr_cxsf, r0   /* spsr_abt */
+
+    /* UND mode registers */
+    cps #MODE_UND
+    mov r13, #0         /* r13_und */
+    mov r14, #0         /* r14_und */
+    mrs r0,  cpsr
+    msr spsr_cxsf, r0   /* spsr_und */
+
+    /* SYS mode registers */
+    cps #MODE_SYS
+    mov r13, #0         /* r13_sys */
+    mov r14, #0         /* r14_sys */
+
+#if defined(CONFIG_FLOAT)
+    /*
+     * Initialise FPU registers to a defined state.
+     */
+
+    /* Allow VFP coprocessor access */
+    mrc p15, 0, r0, c1, c0, 2
+    orr r0, r0, #(CPACR_CP10(CPACR_FA) | CPACR_CP11(CPACR_FA))
+    mcr p15, 0, r0, c1, c0, 2
+
+    /* Enable VFP */
+    mov  r0, #FPEXC_EN
+    fmxr fpexc, r0
+
+    /* Initialise VFP registers */
+    fmdrr d0,  r1, r1
+    fmdrr d1,  r1, r1
+    fmdrr d2,  r1, r1
+    fmdrr d3,  r1, r1
+    fmdrr d4,  r1, r1
+    fmdrr d5,  r1, r1
+    fmdrr d6,  r1, r1
+    fmdrr d7,  r1, r1
+    fmdrr d8,  r1, r1
+    fmdrr d9,  r1, r1
+    fmdrr d10, r1, r1
+    fmdrr d11, r1, r1
+    fmdrr d12, r1, r1
+    fmdrr d13, r1, r1
+    fmdrr d14, r1, r1
+    fmdrr d15, r1, r1
+#endif /* CONFIG_FLOAT */
+
+#endif /* CONFIG_CPU_HAS_DCLS */
+
+    /*
+     * Configure stack.
+     */
+
+    /* FIQ mode stack */
+    msr CPSR_c, #(MODE_FIQ | I_BIT | F_BIT)
+    ldr sp, =(z_arm_fiq_stack + CONFIG_ARMV7_FIQ_STACK_SIZE)
+
+    /* IRQ mode stack */
+    msr CPSR_c, #(MODE_IRQ | I_BIT | F_BIT)
+    ldr sp, =(_interrupt_stack + CONFIG_ISR_STACK_SIZE)
+
+    /* ABT mode stack */
+    msr CPSR_c, #(MODE_ABT | I_BIT | F_BIT)
+    ldr sp, =(z_arm_abort_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE)
+
+    /* UND mode stack */
+    msr CPSR_c, #(MODE_UND | I_BIT | F_BIT)
+    ldr sp, =(z_arm_undef_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE)
+
+    /* SVC mode stack */
+    msr CPSR_c, #(MODE_SVC | I_BIT | F_BIT)
+    ldr sp, =(z_arm_svc_stack + CONFIG_ARMV7_SVC_STACK_SIZE)
+
+    /* SYS mode stack */
+    msr CPSR_c, #(MODE_SYS | I_BIT | F_BIT)
+    ldr sp, =(z_arm_sys_stack + CONFIG_ARMV7_SYS_STACK_SIZE)
+
+#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
+    /* Execute platform-specific initialisation if applicable */
+    bl z_platform_init
+#endif
+
+#if defined(CONFIG_WDOG_INIT)
+    /* board-specific watchdog initialization is necessary */
+    bl z_arm_watchdog_init
+#endif
+
+    b z_arm_prep_c

arch/arm/core/aarch32/cortex_r/stacks.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018 Lexmark International, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <aarch32/cortex_r/stack.h>
+#include <string.h>
+
+K_THREAD_STACK_DEFINE(z_arm_fiq_stack,   CONFIG_ARMV7_FIQ_STACK_SIZE);
+K_THREAD_STACK_DEFINE(z_arm_abort_stack, CONFIG_ARMV7_EXCEPTION_STACK_SIZE);
+K_THREAD_STACK_DEFINE(z_arm_undef_stack, CONFIG_ARMV7_EXCEPTION_STACK_SIZE);
+K_THREAD_STACK_DEFINE(z_arm_svc_stack,   CONFIG_ARMV7_SVC_STACK_SIZE);
+K_THREAD_STACK_DEFINE(z_arm_sys_stack,   CONFIG_ARMV7_SYS_STACK_SIZE);
+
+#if defined(CONFIG_INIT_STACKS)
+void z_arm_init_stacks(void)
+{
+	memset(z_arm_fiq_stack, 0xAA, CONFIG_ARMV7_FIQ_STACK_SIZE);
+	memset(z_arm_svc_stack, 0xAA, CONFIG_ARMV7_SVC_STACK_SIZE);
+	memset(z_arm_abort_stack, 0xAA, CONFIG_ARMV7_EXCEPTION_STACK_SIZE);
+	memset(z_arm_undef_stack, 0xAA, CONFIG_ARMV7_EXCEPTION_STACK_SIZE);
+	memset(&_interrupt_stack, 0xAA, CONFIG_ISR_STACK_SIZE);
+}
+#endif

arch/arm/core/aarch32/cortex_r/vector_table.S

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2018 Marvell
+ * Copyright (c) 2018 Lexmark International, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Populated vector table in ROM
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include "vector_table.h"
+
+_ASM_FILE_PROLOGUE
+
+SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
+	ldr pc, =z_arm_reset             /*                   offset 0 */
+	ldr pc, =z_arm_undef_instruction /* undef instruction offset 4 */
+	ldr pc, =z_arm_svc               /* svc               offset 8 */
+	ldr pc, =z_arm_prefetch_abort    /* prefetch abort offset  0xc */
+	ldr pc, =z_arm_data_abort        /* data abort     offset 0x10 */
+	nop				 /*                offset 0x14 */
+	ldr pc, =_isr_wrapper		 /* IRQ            offset 0x18 */
+	ldr pc, =z_arm_nmi               /* FIQ            offset 0x1c */

arch/arm/core/aarch32/cortex_r/vector_table.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018 Marvell
+ * Copyright (c) 2018 Lexmark International, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Definitions for the boot vector table
+ *
+ *
+ * Definitions for the boot vector table.
+ *
+ * System exception handler names all have the same format:
+ *
+ *   __<exception name with underscores>
+ *
+ * No other symbol has the same format, so they are easy to spot.
+ */
+
+#ifndef _VECTOR_TABLE__H_
+#define _VECTOR_TABLE__H_
+
+#ifdef _ASMLANGUAGE
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <sys/util.h>
+
+GTEXT(__start)
+GTEXT(_vector_table)
+
+GTEXT(z_arm_nmi)
+GTEXT(z_arm_undef_instruction)
+GTEXT(z_arm_svc)
+GTEXT(z_arm_prefetch_abort)
+GTEXT(z_arm_data_abort)
+
+GTEXT(z_arm_pendsv)
+GTEXT(z_arm_reserved)
+
+GTEXT(z_arm_prep_c)
+GTEXT(_isr_wrapper)
+
+#else /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void *_vector_table[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* _VECTOR_TABLE__H_ */

arch/arm/core/aarch32/cpu_idle.S

@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2013-2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief ARM Cortex-M and Cortex-R power management
+ *
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(z_arm_cpu_idle_init)
+GTEXT(arch_cpu_idle)
+GTEXT(arch_cpu_atomic_idle)
+
+#if defined(CONFIG_CPU_CORTEX_M)
+#define _SCB_SCR 0xE000ED10
+
+#define _SCB_SCR_SEVONPEND (1 << 4)
+#define _SCB_SCR_SLEEPDEEP (1 << 2)
+#define _SCB_SCR_SLEEPONEXIT (1 << 1)
+#define _SCR_INIT_BITS _SCB_SCR_SEVONPEND
+#endif
+
+/**
+ *
+ * @brief Initialization of CPU idle
+ *
+ * Only called by arch_kernel_init(). Sets SEVONPEND bit once for the system's
+ * duration.
+ *
+ * @return N/A
+ *
+ * C function prototype:
+ *
+ * void z_arm_cpu_idle_init(void);
+ */
+
+SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
+#if defined(CONFIG_CPU_CORTEX_M)
+	ldr r1, =_SCB_SCR
+	movs.n r2, #_SCR_INIT_BITS
+	str r2, [r1]
+#endif
+	bx lr
+
+SECTION_FUNC(TEXT, arch_cpu_idle)
+#ifdef CONFIG_TRACING
+	push {r0, lr}
+	bl    sys_trace_idle
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+	pop {r0, r1}
+        mov lr, r1
+#else
+	pop {r0, lr}
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+#endif /* CONFIG_TRACING */
+
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
+	|| defined(CONFIG_ARMV7_R)
+	cpsie i
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+	/* clear BASEPRI so wfi is awakened by incoming interrupts */
+	eors.n r0, r0
+	msr BASEPRI, r0
+#else
+#error Unknown ARM architecture
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+
+	wfi
+
+	bx lr
+
+SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
+#ifdef CONFIG_TRACING
+	push {r0, lr}
+	bl    sys_trace_idle
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+        pop {r0, r1}
+        mov lr, r1
+#else
+	pop {r0, lr}
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+#endif /* CONFIG_TRACING */
+
+	/*
+	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
+	 * incoming interrupts but the CPU will not service them right away.
+	 */
+	cpsid i
+
+	/*
+	 * No need to set SEVONPEND, it's set once in z_CpuIdleInit() and never
+	 * touched again.
+	 */
+
+	/* r0: interrupt mask from caller */
+
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
+	|| defined(CONFIG_ARMV7_R)
+	/* No BASEPRI, call wfe directly (SEVONPEND set in z_CpuIdleInit()) */
+	wfe
+
+	cmp r0, #0
+	bne _irq_disabled
+	cpsie i
+_irq_disabled:
+
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+	/* r1: zero, for setting BASEPRI (needs a register) */
+	eors.n r1, r1
+
+	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
+	msr BASEPRI, r1
+
+	wfe
+
+	msr BASEPRI, r0
+	cpsie i
+#else
+#error Unknown ARM architecture
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+	bx lr

arch/arm/core/aarch32/exc_exit.S

@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2013-2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief ARM Cortex-M and Cortex-R exception/interrupt exit API
+ *
+ *
+ * Provides functions for performing kernel handling when exiting exceptions or
+ * interrupts that are installed directly in the vector table (i.e. that are not
+ * wrapped around by _isr_wrapper()).
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <offsets_short.h>
+#include <arch/cpu.h>
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(z_arm_exc_exit)
+GTEXT(z_arm_int_exit)
+GDATA(_kernel)
+#if defined(CONFIG_CPU_CORTEX_R)
+GTEXT(z_arm_pendsv)
+#endif
+
+/**
+ *
+ * @brief Kernel housekeeping when exiting interrupt handler installed
+ *            directly in vector table
+ *
+ * Kernel allows installing interrupt handlers (ISRs) directly into the vector
+ * table to get the lowest interrupt latency possible. This allows the ISR to
+ * be invoked directly without going through a software interrupt table.
+ * However, upon exiting the ISR, some kernel work must still be performed,
+ * namely possible context switching. While ISRs connected in the software
+ * interrupt table do this automatically via a wrapper, ISRs connected directly
+ * in the vector table must invoke z_arm_int_exit() as the *very last* action
+ * before returning.
+ *
+ * e.g.
+ *
+ * void myISR(void)
+ *     {
+ *     printk("in %s\n", __FUNCTION__);
+ *     doStuff();
+ *     z_arm_int_exit();
+ *     }
+ *
+ * @return N/A
+ */
+
+SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_int_exit)
+
+/* z_arm_int_exit falls through to z_arm_exc_exit (they are aliases of each
+ * other)
+ */
+
+/**
+ *
+ * @brief Kernel housekeeping when exiting exception handler installed
+ *            directly in vector table
+ *
+ * See z_arm_int_exit().
+ *
+ * @return N/A
+ */
+
+SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)
+#if defined(CONFIG_CPU_CORTEX_R)
+    /* r0 contains the caller mode */
+    push {r0, lr}
+#endif
+
+#ifdef CONFIG_PREEMPT_ENABLED
+    ldr r0, =_kernel
+
+    ldr r1, [r0, #_kernel_offset_to_current]
+
+    ldr r0, [r0, #_kernel_offset_to_ready_q_cache]
+    cmp r0, r1
+    beq _EXIT_EXC
+
+#if defined(CONFIG_CPU_CORTEX_M)
+    /* context switch required, pend the PendSV exception */
+    ldr r1, =_SCS_ICSR
+    ldr r2, =_SCS_ICSR_PENDSV
+    str r2, [r1]
+#elif defined(CONFIG_CPU_CORTEX_R)
+    bl z_arm_pendsv
+#endif
+
+_ExcExitWithGdbStub:
+
+_EXIT_EXC:
+#endif /* CONFIG_PREEMPT_ENABLED */
+
+#ifdef CONFIG_STACK_SENTINEL
+#if defined(CONFIG_CPU_CORTEX_M)
+    push {r0, lr}
+    bl z_check_stack_sentinel
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+    pop {r0, r1}
+    mov lr, r1
+#else
+    pop {r0, lr}
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+#else
+    bl z_check_stack_sentinel
+#endif /* CONFIG_CPU_CORTEX_M */
+#endif /* CONFIG_STACK_SENTINEL */
+
+#if defined(CONFIG_CPU_CORTEX_M)
+    bx lr
+#elif defined(CONFIG_CPU_CORTEX_R)
+    /* Restore the caller mode to r0 */
+    pop {r0, lr}
+
+    /*
+     * Restore r0-r3, r12 and lr stored into the process stack by the mode
+     * entry function. These registers are saved by _isr_wrapper for IRQ mode
+     * and z_arm_svc for SVC mode.
+     *
+     * r0-r3 are either the values from the thread before it was switched out
+     * or they are the args to _new_thread for a new thread.
+     */
+    push {r4, r5}
+
+    cmp r0, #RET_FROM_SVC
+    cps #MODE_SYS
+    ldmia sp!, {r0-r5}
+    beq _svc_exit
+
+    cps #MODE_IRQ
+    b _exc_exit
+
+_svc_exit:
+    cps #MODE_SVC
+
+_exc_exit:
+    mov r12, r4
+    mov lr, r5
+    pop {r4, r5}
+    movs pc, lr
+#endif

arch/arm/core/aarch32/fatal.c

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Kernel fatal error handler for ARM Cortex-M and Cortex-R
+ *
+ * This module provides the z_arm_fatal_error() routine for ARM Cortex-M
+ * and Cortex-R CPUs.
+ */
+
+#include <kernel.h>
+#include <logging/log.h>
+LOG_MODULE_DECLARE(os);
+
+static void esf_dump(const z_arch_esf_t *esf)
+{
+	LOG_ERR("r0/a1:  0x%08x  r1/a2:  0x%08x  r2/a3:  0x%08x",
+		esf->basic.a1, esf->basic.a2, esf->basic.a3);
+	LOG_ERR("r3/a4:  0x%08x r12/ip:  0x%08x r14/lr:  0x%08x",
+		esf->basic.a4, esf->basic.ip, esf->basic.lr);
+	LOG_ERR(" xpsr:  0x%08x", esf->basic.xpsr);
+#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+	for (int i = 0; i < 16; i += 4) {
+		LOG_ERR("s[%2d]:  0x%08x  s[%2d]:  0x%08x"
+			"  s[%2d]:  0x%08x  s[%2d]:  0x%08x",
+			i, (u32_t)esf->s[i],
+			i + 1, (u32_t)esf->s[i + 1],
+			i + 2, (u32_t)esf->s[i + 2],
+			i + 3, (u32_t)esf->s[i + 3]);
+	}
+	LOG_ERR("fpscr:  0x%08x", esf->fpscr);
+#endif
+	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
+		esf->basic.pc);
+}
+
+void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
+{
+
+	if (esf != NULL) {
+		esf_dump(esf);
+	}
+	z_fatal_error(reason, esf);
+}
+
+/**
+ * @brief Handle a software-generated fatal exception
+ * (e.g. kernel oops, panic, etc.).
+ *
+ * Notes:
+ * - the function is invoked in SVC Handler
+ * - if triggered from nPRIV mode, only oops and stack fail error reasons
+ *   may be propagated to the fault handling process.
+ * - We expect the supplied exception stack frame to always be a valid
+ *   frame. That is because, if the ESF cannot be stacked during an SVC,
+ *   a processor fault (e.g. stacking error) will be generated, and the
+ *   fault handler will executed insted of the SVC.
+ *
+ * @param esf exception frame
+ */
+void z_do_kernel_oops(const z_arch_esf_t *esf)
+{
+	/* Stacked R0 holds the exception reason. */
+	unsigned int reason = esf->basic.r0;
+
+#if defined(CONFIG_USERSPACE)
+	if ((__get_CONTROL() & CONTROL_nPRIV_Msk) == CONTROL_nPRIV_Msk) {
+		/*
+		 * Exception triggered from nPRIV mode.
+		 *
+		 * User mode is only allowed to induce oopses and stack check
+		 * failures via software-triggered system fatal exceptions.
+		 */
+		if (!((esf->basic.r0 == K_ERR_KERNEL_OOPS) ||
+			(esf->basic.r0 == K_ERR_STACK_CHK_FAIL))) {
+
+			reason = K_ERR_KERNEL_OOPS;
+		}
+	}
+
+#endif /* CONFIG_USERSPACE */
+	z_arm_fatal_error(reason, esf);
+}
+
+FUNC_NORETURN void arch_syscall_oops(void *ssf_ptr)
+{
+	u32_t *ssf_contents = ssf_ptr;
+	z_arch_esf_t oops_esf = { 0 };
+
+	/* TODO: Copy the rest of the register set out of ssf_ptr */
+	oops_esf.basic.pc = ssf_contents[3];
+
+	z_arm_fatal_error(K_ERR_KERNEL_OOPS, &oops_esf);
+	CODE_UNREACHABLE;
+}

arch/arm/core/aarch32/fault_s.S

@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2013-2014 Wind River Systems, Inc.
+ * Copyright (c) 2017-2019 Nordic Semiconductor ASA.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Fault handlers for ARM Cortex-M and Cortex-R
+ *
+ * Fault handlers for ARM Cortex-M and Cortex-R processors.
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(z_arm_fault)
+
+GTEXT(z_arm_hard_fault)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+/* HardFault is used for all fault conditions on ARMv6-M. */
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+GTEXT(z_arm_mpu_fault)
+GTEXT(z_arm_bus_fault)
+GTEXT(z_arm_usage_fault)
+#if defined(CONFIG_ARM_SECURE_FIRMWARE)
+GTEXT(z_arm_secure_fault)
+#endif /* CONFIG_ARM_SECURE_FIRMWARE*/
+GTEXT(z_arm_debug_monitor)
+#elif defined(CONFIG_ARMV7_R)
+GTEXT(z_arm_undef_instruction)
+GTEXT(z_arm_prefetch_abort)
+GTEXT(z_arm_data_abort)
+#else
+#error Unknown ARM architecture
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+GTEXT(z_arm_reserved)
+
+/**
+ *
+ * @brief Fault handler installed in the fault and reserved vectors
+ *
+ * Entry point for the HardFault, MemManageFault, BusFault, UsageFault,
+ * SecureFault, Debug Monitor, and reserved exceptions.
+ *
+ * For Cortex-M: the function supplies the values of
+ * - the MSP
+ * - the PSP
+ * - the EXC_RETURN value
+ * as parameters to the z_arm_fault() C function that will perform the
+ * rest of the fault handling (i.e. z_arm_fault(MSP, PSP, EXC_RETURN)).
+ *
+ * For Cortex-R: the function simply invokes z_arm_fault() with currently
+ * unused arguments.
+ *
+ * Provides these symbols:
+ *
+ *   z_arm_hard_fault
+ *   z_arm_mpu_fault
+ *   z_arm_bus_fault
+ *   z_arm_usage_fault
+ *   z_arm_secure_fault
+ *   z_arm_debug_monitor
+ *   z_arm_reserved
+ */
+
+SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_hard_fault)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+/* HardFault is used for all fault conditions on ARMv6-M. */
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_mpu_fault)
+SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_bus_fault)
+SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_usage_fault)
+#if defined(CONFIG_ARM_SECURE_FIRMWARE)
+SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_secure_fault)
+#endif /* CONFIG_ARM_SECURE_FIRMWARE */
+SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_debug_monitor)
+#elif defined(CONFIG_ARMV7_R)
+SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_undef_instruction)
+SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_prefetch_abort)
+SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_data_abort)
+#else
+#error Unknown ARM architecture
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_reserved)
+
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || \
+	defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+	mrs r0, MSP
+	mrs r1, PSP
+	mov r2, lr /* EXC_RETURN */
+
+	push {r0, lr}
+#elif defined(CONFIG_ARMV7_R)
+	/*
+	 * Pass null for the esf to z_arm_fault for now. A future PR will add
+	 * better exception debug for Cortex-R that subsumes what esf
+	 * provides.
+	 */
+	mov r0, #0
+#else
+#error Unknown ARM architecture
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE || CONFIG_ARMv7_M_ARMV8_M_MAINLINE */
+
+	bl z_arm_fault
+
+#if defined(CONFIG_CPU_CORTEX_M)
+	pop {r0, pc}
+#elif defined(CONFIG_CPU_CORTEX_R)
+	pop {r0, lr}
+	subs pc, lr, #8
+#endif
+
+	.end

arch/arm/core/aarch32/irq_manage.c

@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2013-2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief ARM Cortex-M and Cortex-R interrupt management
+ *
+ *
+ * Interrupt management: enabling/disabling and dynamic ISR
+ * connecting/replacing.  SW_ISR_TABLE_DYNAMIC has to be enabled for
+ * connecting ISRs at runtime.
+ */
+
+#include <kernel.h>
+#include <arch/cpu.h>
+#if defined(CONFIG_CPU_CORTEX_M)
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
+#elif defined(CONFIG_CPU_CORTEX_R)
+#include <device.h>
+#include <irq_nextlevel.h>
+#endif
+#include <sys/__assert.h>
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <sw_isr_table.h>
+#include <irq.h>
+#include <tracing/tracing.h>
+
+extern void z_arm_reserved(void);
+
+#if defined(CONFIG_CPU_CORTEX_M)
+#define NUM_IRQS_PER_REG 32
+#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
+#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
+
+void arch_irq_enable(unsigned int irq)
+{
+	NVIC_EnableIRQ((IRQn_Type)irq);
+}
+
+void arch_irq_disable(unsigned int irq)
+{
+	NVIC_DisableIRQ((IRQn_Type)irq);
+}
+
+int arch_irq_is_enabled(unsigned int irq)
+{
+	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
+}
+
+/**
+ * @internal
+ *
+ * @brief Set an interrupt's priority
+ *
+ * The priority is verified if ASSERT_ON is enabled. The maximum number
+ * of priority levels is a little complex, as there are some hardware
+ * priority levels which are reserved.
+ *
+ * @return N/A
+ */
+void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
+{
+	/* The kernel may reserve some of the highest priority levels.
+	 * So we offset the requested priority level with the number
+	 * of priority levels reserved by the kernel.
+	 */
+
+#if defined(CONFIG_ZERO_LATENCY_IRQS)
+	/* If we have zero latency interrupts, those interrupts will
+	 * run at a priority level which is not masked by irq_lock().
+	 * Our policy is to express priority levels with special properties
+	 * via flags
+	 */
+	if (flags & IRQ_ZERO_LATENCY) {
+		prio = _EXC_ZERO_LATENCY_IRQS_PRIO;
+	} else {
+		prio += _IRQ_PRIO_OFFSET;
+	}
+#else
+	ARG_UNUSED(flags);
+	prio += _IRQ_PRIO_OFFSET;
+#endif
+	/* The last priority level is also used by PendSV exception, but
+	 * allow other interrupts to use the same level, even if it ends up
+	 * affecting performance (can still be useful on systems with a
+	 * reduced set of priorities, like Cortex-M0/M0+).
+	 */
+	__ASSERT(prio <= (BIT(DT_NUM_IRQ_PRIO_BITS) - 1),
+		 "invalid priority %d! values must be less than %lu\n",
+		 prio - _IRQ_PRIO_OFFSET,
+		 BIT(DT_NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
+	NVIC_SetPriority((IRQn_Type)irq, prio);
+}
+
+#elif defined(CONFIG_CPU_CORTEX_R)
+void arch_irq_enable(unsigned int irq)
+{
+	struct device *dev = _sw_isr_table[0].arg;
+
+	irq_enable_next_level(dev, (irq >> 8) - 1);
+}
+
+void arch_irq_disable(unsigned int irq)
+{
+	struct device *dev = _sw_isr_table[0].arg;
+
+	irq_disable_next_level(dev, (irq >> 8) - 1);
+}
+
+int arch_irq_is_enabled(unsigned int irq)
+{
+	struct device *dev = _sw_isr_table[0].arg;
+
+	return irq_is_enabled_next_level(dev);
+}
+
+/**
+ * @internal
+ *
+ * @brief Set an interrupt's priority
+ *
+ * The priority is verified if ASSERT_ON is enabled. The maximum number
+ * of priority levels is a little complex, as there are some hardware
+ * priority levels which are reserved: three for various types of exceptions,
+ * and possibly one additional to support zero latency interrupts.
+ *
+ * @return N/A
+ */
+void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
+{
+	struct device *dev = _sw_isr_table[0].arg;
+
+	if (irq == 0)
+		return;
+
+	irq_set_priority_next_level(dev, (irq >> 8) - 1, prio, flags);
+}
+
+#endif
+
+/**
+ *
+ * @brief Spurious interrupt handler
+ *
+ * Installed in all dynamic interrupt slots at boot time. Throws an error if
+ * called.
+ *
+ * See z_arm_reserved().
+ *
+ * @return N/A
+ */
+void z_irq_spurious(void *unused)
+{
+	ARG_UNUSED(unused);
+	z_arm_reserved();
+}
+
+#ifdef CONFIG_SYS_POWER_MANAGEMENT
+void _arch_isr_direct_pm(void)
+{
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
+	|| defined(CONFIG_ARMV7_R)
+	unsigned int key;
+
+	/* irq_lock() does what we wan for this CPU */
+	key = irq_lock();
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+	/* Lock all interrupts. irq_lock() will on this CPU only disable those
+	 * lower than BASEPRI, which is not what we want. See comments in
+	 * arch/arm/core/aarch32/isr_wrapper.S
+	 */
+	__asm__ volatile("cpsid i" : : : "memory");
+#else
+#error Unknown ARM architecture
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+
+	if (_kernel.idle) {
+		s32_t idle_val = _kernel.idle;
+
+		_kernel.idle = 0;
+		z_sys_power_save_idle_exit(idle_val);
+	}
+
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
+	|| defined(CONFIG_ARMV7_R)
+	irq_unlock(key);
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+	__asm__ volatile("cpsie i" : : : "memory");
+#else
+#error Unknown ARM architecture
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+
+}
+#endif
+
+#if defined(CONFIG_ARM_SECURE_FIRMWARE)
+/**
+ *
+ * @brief Set the target security state for the given IRQ
+ *
+ * Function sets the security state (Secure or Non-Secure) targeted
+ * by the given irq. It requires ARMv8-M MCU.
+ * It is only compiled if ARM_SECURE_FIRMWARE is defined.
+ * It should only be called while in Secure state, otherwise, a write attempt
+ * to NVIC.ITNS register is write-ignored(WI), as the ITNS register is not
+ * banked between security states and, therefore, has no Non-Secure instance.
+ *
+ * It shall assert if the operation is not performed successfully.
+ *
+ * @param irq IRQ line
+ * @param secure_state 1 if target state is Secure, 0 otherwise.
+ *
+ * @return N/A
+ */
+void irq_target_state_set(unsigned int irq, int secure_state)
+{
+	if (secure_state) {
+		/* Set target to Secure */
+		if (NVIC_ClearTargetState(irq) != 0) {
+			__ASSERT(0, "NVIC SetTargetState error");
+		}
+	} else {
+		/* Set target state to Non-Secure */
+		if (NVIC_SetTargetState(irq) != 1) {
+			__ASSERT(0, "NVIC SetTargetState error");
+		}
+	}
+}
+
+/**
+ *
+ * @brief Determine whether the given IRQ targets the Secure state
+ *
+ * Function determines whether the given irq targets the Secure state
+ * or not (i.e. targets the Non-Secure state). It requires ARMv8-M MCU.
+ * It is only compiled if ARM_SECURE_FIRMWARE is defined.
+ * It should only be called while in Secure state, otherwise, a read attempt
+ * to NVIC.ITNS register is read-as-zero(RAZ), as the ITNS register is not
+ * banked between security states and, therefore, has no Non-Secure instance.
+ *
+ * @param irq IRQ line
+ *
+ * @return 1 if target state is Secure, 0 otherwise.
+ */
+int irq_target_state_is_secure(unsigned int irq)
+{
+	return NVIC_GetTargetState(irq) == 0;
+}
+
+#endif /* CONFIG_ARM_SECURE_FIRMWARE */
+
+#ifdef CONFIG_DYNAMIC_INTERRUPTS
+int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
+			     void (*routine)(void *parameter), void *parameter,
+			     u32_t flags)
+{
+	z_isr_install(irq, routine, parameter);
+	z_arm_irq_priority_set(irq, priority, flags);
+	return irq;
+}
+
+#ifdef CONFIG_DYNAMIC_DIRECT_INTERRUPTS
+static inline void z_arm_irq_dynamic_direct_isr_dispatch(void)
+{
+	u32_t irq = __get_IPSR() - 16;
+
+	if (irq < IRQ_TABLE_SIZE) {
+		struct _isr_table_entry *isr_entry = &_sw_isr_table[irq];
+
+		isr_entry->isr(isr_entry->arg);
+	}
+}
+
+ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_reschedule)
+{
+	z_arm_irq_dynamic_direct_isr_dispatch();
+
+	return 1;
+}
+
+ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_no_reschedule)
+{
+	z_arm_irq_dynamic_direct_isr_dispatch();
+
+	return 0;
+}
+
+#endif /* CONFIG_DYNAMIC_DIRECT_INTERRUPTS */
+
+#endif /* CONFIG_DYNAMIC_INTERRUPTS */

arch/arm/core/aarch32/irq_offload.c

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2015 Intel corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file Software interrupts utility code - ARM implementation
+ */
+
+#include <kernel.h>
+#include <irq_offload.h>
+
+volatile irq_offload_routine_t offload_routine;
+static void *offload_param;
+
+/* Called by z_arm_svc */
+void z_irq_do_offload(void)
+{
+	offload_routine(offload_param);
+}
+
+void arch_irq_offload(irq_offload_routine_t routine, void *parameter)
+{
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && defined(CONFIG_ASSERT)
+	/* ARMv6-M/ARMv8-M Baseline HardFault if you make a SVC call with
+	 * interrupts locked.
+	 */
+	unsigned int key;
+
+	__asm__ volatile("mrs %0, PRIMASK;" : "=r" (key) : : "memory");
+	__ASSERT(key == 0U, "irq_offload called with interrupts locked\n");
+#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE && CONFIG_ASSERT */
+
+	k_sched_lock();
+	offload_routine = routine;
+	offload_param = parameter;
+
+	__asm__ volatile ("svc %[id]"
+			  :
+			  : [id] "i" (_SVC_CALL_IRQ_OFFLOAD)
+			  : "memory");
+
+	offload_routine = NULL;
+	k_sched_unlock();
+}