release: Zephyr 2.2.0

Bump version to 2.2.0 final.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>

.checkpatch.conf

@@ -1,4 +1,3 @@
---mailback
 --emacs
 --summary-file
 --show-types

.editorconfig

@@ -9,6 +9,7 @@ charset = utf-8
 end_of_line = lf
 insert_final_newline = true
 trim_trailing_whitespace = true
+max_line_length = 80
 
 # C
 [*.{c,h}]

.github/license_config.yml

@@ -0,0 +1,16 @@
+license:
+  main: apache-2.0
+  report_missing: true
+  category: Permissive
+copyright:
+  check: true
+exclude:
+  extensions:
+    - yml
+    - yaml
+    - html
+    - rst
+    - conf
+    - cfg
+  langs:
+    - HTML

.github/workflows/doc-build.yml

@@ -0,0 +1,65 @@
+# Copyright (c) 2020 Linaro Limited.
+# SPDX-License-Identifier: Apache-2.0
+
+name: Documentation GitHub Workflow
+
+on: [pull_request]
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+
+    steps:
+    - name: Update PATH for west
+      run: |
+        echo "::add-path::$HOME/.local/bin"
+
+    - name: checkout
+      uses: actions/checkout@v2
+
+    - name: install-pkgs
+      run: |
+        sudo apt-get install -y ninja-build doxygen
+
+    - name: cache-pip
+      uses: actions/cache@v1
+      with:
+        path: ~/.cache/pip
+        key: ${{ runner.os }}-doc-pip
+
+    - name: install-pip
+      run: |
+        pip3 install setuptools
+        pip3 install 'breathe>=4.9.1' 'docutils>=0.14' \
+                     'sphinx>=1.7.5' sphinx_rtd_theme sphinx-tabs \
+                     sphinxcontrib-svg2pdfconverter 'west>=0.6.2'
+        pip3 install pyelftools
+
+    - name: west setup
+      run: |
+        west init -l . || true
+
+    - name: build-docs
+      run: |
+        source zephyr-env.sh
+        make htmldocs
+        tar cvf htmldocs.tar --directory=./doc/_build html
+
+    - name: upload-build
+      uses: actions/upload-artifact@master
+      continue-on-error: True
+      with:
+        name: htmldocs.tar
+        path: htmldocs.tar
+
+    - name: check-warns
+      run: |
+        if [ -s doc/_build/doc.warnings ]; then
+           docwarn=$(cat doc/_build/doc.warnings)
+           docwarn="${docwarn//'%'/'%25'}"
+           docwarn="${docwarn//$'\n'/'%0A'}"
+           docwarn="${docwarn//$'\r'/'%0D'}"
+           # We treat doc warnings as errors
+           echo "::error file=doc.warnings::$docwarn"
+           exit 1
+        fi

.github/workflows/doc-publish.yml

@@ -0,0 +1,112 @@
+# Copyright (c) 2020 Linaro Limited.
+# SPDX-License-Identifier: Apache-2.0
+
+name: Doc build for Release or Daily
+
+# Either a daily based on schedule/cron or only on tag push
+on:
+  schedule:
+    - cron:  '50 22 * * *'
+  push:
+    tags:
+    - '*'
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+
+    steps:
+    - name: Update PATH for west
+      run: |
+        echo "::add-path::$HOME/.local/bin"
+
+    - name: Determine tag
+      id: tag
+      run: |
+        # We expect to get here either due to a schedule event in which
+        # case we are doing a daily build of the docs, or because a new
+        # tag was pushed, in which case we are building docs for a release
+        if [ ${GITHUB_EVENT_NAME} == "schedule" ]; then
+           echo ::set-output name=TYPE::daily;
+           echo ::set-output name=RELEASE::latest;
+        elif [ ${GITHUB_EVENT_NAME} == "push" ]; then
+           # If push due to a tag GITHUB_REF will look like refs/tags/TAG-FOO
+           # chop of 'refs/tags' so RELEASE=TAG-FOO
+           echo ::set-output name=TYPE::release;
+           echo ::set-output name=RELEASE::${GITHUB_REF/refs\/tags\//};
+        else
+           exit 1
+        fi
+
+    - name: Configure AWS Credentials
+      uses: aws-actions/configure-aws-credentials@v1
+      with:
+        aws-access-key-id: ${{ secrets.AWS_ACCESS_KEY_ID }}
+        aws-secret-access-key: ${{ secrets.AWS_SECRET_ACCESS_KEY }}
+        aws-region: us-east-1
+
+    - name: checkout
+      uses: actions/checkout@v2
+
+    - name: install-pkgs
+      run: |
+        sudo apt-get install -y ninja-build doxygen
+
+    - name: cache-pip
+      uses: actions/cache@v1
+      with:
+        path: ~/.cache/pip
+        key: ${{ runner.os }}-doc-pip
+
+    - name: install-pip
+      run: |
+        pip3 install setuptools
+        pip3 install 'breathe>=4.9.1' 'docutils>=0.14' \
+                     'sphinx>=1.7.5' sphinx_rtd_theme sphinx-tabs \
+                     sphinxcontrib-svg2pdfconverter 'west>=0.6.2'
+        pip3 install pyelftools
+
+    - name: west setup
+      run: |
+        west init -l . || true
+
+    - name: build-docs
+      env:
+        DOC_TAG: ${{ steps.tag.outputs.TYPE }}
+      run: |
+        source zephyr-env.sh
+        make DOC_TAG=${DOC_TAG} htmldocs
+
+    - name: check-warns
+      run: |
+        if [ -s doc/_build/doc.warnings ]; then
+           docwarn=$(cat doc/_build/doc.warnings)
+           docwarn="${docwarn//'%'/'%25'}"
+           docwarn="${docwarn//$'\n'/'%0A'}"
+           docwarn="${docwarn//$'\r'/'%0D'}"
+           # We treat doc warnings as errors
+           echo "::error file=doc.warnings::$docwarn"
+           exit 1
+        fi
+
+    - name: Upload to AWS S3
+      env:
+        RELEASE: ${{ steps.tag.outputs.RELEASE }}
+      run: |
+        echo "DOC_RELEASE=[$RELEASE]"
+        if [ "$RELEASE" == "latest" ]; then
+           export
+           echo "publish latest docs"
+           aws s3 sync  --quiet doc/_build/html s3://docs.zephyrproject.org/latest --delete
+           echo "success sync of latest docs"
+        else
+           DOC_RELEASE=${RELEASE}.0
+           echo "publish release docs: ${DOC_RELEASE}"
+           aws s3 sync  --quiet doc/_build/html s3://docs.zephyrproject.org/${DOC_RELEASE}
+           echo "success sync of rel docs"
+        fi
+        if [ -d doc/_build/doxygen/html ]; then
+           echo "publish doxygen"
+           aws s3 sync  --quiet doc/_build/doxygen/html s3://docs.zephyrproject.org/apidoc/${RELEASE} --delete
+           echo "success publish of doxygen"
+        fi

.github/workflows/license_check.yml

@@ -0,0 +1,32 @@
+name: Scancode
+
+on: [pull_request]
+
+jobs:
+  scancode_job:
+    runs-on: ubuntu-latest
+    name: Scan code for licenses
+    steps:
+    - name: Checkout the code
+      uses: actions/checkout@v1
+    - name: Scan the code
+      id: scancode
+      uses: zephyrproject-rtos/action_scancode@v3
+      with:
+        directory-to-scan: 'scan/'
+    - name: Artifact Upload
+      uses: actions/upload-artifact@v1
+      with:
+        name: scancode
+        path: ./artifacts
+
+    - name: Verify
+      run: |
+        if [ -s ./artifacts/report.txt ]; then
+          report=$(cat ./artifacts/report.txt)
+          report="${report//'%'/'%25'}"
+          report="${report//$'\n'/'%0A'}"
+          report="${report//$'\r'/'%0D'}"
+          echo "::error file=./artifacts/report.txt::$report"
+          exit 1
+        fi

.github/workflows/west_cmds.yml

@@ -0,0 +1,65 @@
+# Copyright (c) 2020 Linaro Limited.
+# SPDX-License-Identifier: Apache-2.0
+
+name: Zephyr West Command Tests
+
+on:
+  push:
+    paths:
+    - 'scripts/west-commands.yml'
+    - 'scripts/west_commands/**'
+  pull_request:
+    paths:
+    - 'scripts/west-commands.yml'
+    - 'scripts/west_commands/**'
+
+jobs:
+  build:
+    runs-on: ${{ matrix.os }}
+    strategy:
+      matrix:
+        python-version: [3.6, 3.7, 3.8]
+        os: [ubuntu-latest, macos-latest, windows-latest]
+    steps:
+    - name: checkout
+      uses: actions/checkout@v2
+    - name: Set up Python ${{ matrix.python-version }}
+      uses: actions/setup-python@v1
+      with:
+        python-version: ${{ matrix.python-version }}
+    - name: cache-pip-linux
+      if: startsWith(runner.os, 'Linux')
+      uses: actions/cache@v1
+      with:
+        path: ~/.cache/pip
+        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
+        restore-keys: |
+          ${{ runner.os }}-pip-${{ matrix.python-version }}
+    - name: cache-pip-mac
+      if: startsWith(runner.os, 'macOS')
+      uses: actions/cache@v1
+      with:
+        path: ~/Library/Caches/pip
+        # Trailing '-' was just to get a different cache name
+        key: ${{ runner.os }}-pip-${{ matrix.python-version }}-
+        restore-keys: |
+          ${{ runner.os }}-pip-${{ matrix.python-version }}-
+    - name: cache-pip-win
+      if: startsWith(runner.os, 'Windows')
+      uses: actions/cache@v1
+      with:
+        path: ~\AppData\Local\pip\Cache
+        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
+        restore-keys: |
+          ${{ runner.os }}-pip-${{ matrix.python-version }}
+    - name: install pytest
+      run: |
+        pip3 install pytest west pyelftools
+    - name: run pytest-win
+      if: runner.os == 'Windows'
+      run: |
+        cmd /C "set PYTHONPATH=.\scripts\west_commands && pytest ./scripts/west_commands/tests/"
+    - name: run pytest-mac-linux
+      if: runner.os != 'Windows'
+      run: |
+        PYTHONPATH=./scripts/west_commands pytest ./scripts/west_commands/tests/

.known-issues/doc/bluetooth.conf

@@ -48,3 +48,21 @@
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
 ^.*bt_mesh_model.__unnamed__.*
 ^[- \t]*\^
+#
+# Bluetooth mesh pub struct definition
+#
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]bluetooth[/\\]mesh[/\\]access.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_mesh_model_pub.*
+^[- \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_mesh_model_pub.*
+^[- \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_mesh_model_pub.*
+^[- \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_mesh_model_pub.*
+^[- \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_mesh_model_pub.*
+^[- \t]*\^

.known-issues/doc/duplicate.conf

@@ -1,6 +1,6 @@
 #
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]file_system[/\\]index.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration.
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]file_system[/\\]index.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)
 #
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]dma.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration.
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]dma.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)
 #
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]sensor.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration.
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]sensor.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)

.known-issues/doc/networking.conf

@@ -67,4 +67,4 @@
 #
 # stray duplicate definition warnings
 #
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]networking[/\\]net_if.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration.
+^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]networking[/\\]net_if.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)

.shippable.yml

@@ -4,7 +4,7 @@ compiler: gcc
 
 env:
     global:
-        - ZEPHYR_SDK_INSTALL_DIR=/opt/sdk/zephyr-sdk-0.10.3
+        - ZEPHYR_SDK_INSTALL_DIR=/opt/sdk/zephyr-sdk-0.11.2
         - ZEPHYR_TOOLCHAIN_VARIANT=zephyr
         - MATRIX_BUILDS="5"
     matrix:
@@ -20,7 +20,7 @@ build:
         - ${SHIPPABLE_BUILD_DIR}/ccache
     pre_ci_boot:
         image_name: zephyrprojectrtos/ci
-        image_tag: v0.9.1
+        image_tag: v0.11.4
         pull: true
         options: "-e HOME=/home/buildslave --privileged=true --tty --net=bridge --user buildslave"
 

CMakeLists.txt

@@ -50,7 +50,6 @@ set(ZEPHYR_FINAL_EXECUTABLE    zephyr_final)
 
 # Set some phony targets to collect dependencies
 set(OFFSETS_H_TARGET           offsets_h)
-set(SYSCALL_MACROS_H_TARGET    syscall_macros_h_target)
 set(SYSCALL_LIST_H_TARGET      syscall_list_h_target)
 set(DRIVER_VALIDATION_H_TARGET driver_validation_h_target)
 set(KOBJ_TYPES_H_TARGET        kobj_types_h_target)
@@ -74,7 +73,6 @@ zephyr_library_named(zephyr)
 
 zephyr_include_directories(
   include
-  include/drivers
   ${PROJECT_BINARY_DIR}/include/generated
   ${USERINCLUDE}
   ${STDINCLUDE}
@@ -144,6 +142,13 @@ else()
   assert(0 "Unreachable code. Expected optimization level to have been chosen. See Kconfig.zephyr")
 endif()
 
+if(NOT CONFIG_ARCH_IS_SET)
+  message(WARNING "\
+None of the CONFIG_<arch> (e.g. CONFIG_X86) symbols are set. \
+Select one of them from the SOC_SERIES_* symbol or, lacking that, from the \
+SOC_* symbol.")
+endif()
+
 # Apply the final optimization flag(s)
 zephyr_compile_options(${OPTIMIZATION_FLAG})
 
@@ -403,11 +408,11 @@ set_ifndef(  DTS_BOARD_FIXUP_FILE                                   ${BOARD_DIR}
 set_ifndef(    DTS_SOC_FIXUP_FILE                 ${SOC_DIR}/${ARCH}/${SOC_PATH}/dts_fixup.h)
 set(           DTS_APP_FIXUP_FILE                      ${APPLICATION_SOURCE_DIR}/dts_fixup.h)
 
-set_ifndef(DTS_CAT_OF_FIXUP_FILES ${ZEPHYR_BINARY_DIR}/include/generated/generated_dts_board_fixups.h)
+set_ifndef(DTS_CAT_OF_FIXUP_FILES ${ZEPHYR_BINARY_DIR}/include/generated/devicetree_fixups.h)
 
 # Concatenate the fixups into a single header file for easy
 # #include'ing
-file(WRITE ${DTS_CAT_OF_FIXUP_FILES} "/* May only be included by generated_dts_board.h */\n\n")
+file(WRITE ${DTS_CAT_OF_FIXUP_FILES} "/* May only be included by devicetree.h */\n\n")
 foreach(fixup_file
     ${DTS_BOARD_FIXUP_FILE}
     ${DTS_SOC_FIXUP_FILE}
@@ -458,6 +463,7 @@ add_subdirectory(drivers)
 if(EXISTS ${CMAKE_BINARY_DIR}/zephyr_modules.txt)
 	file(STRINGS ${CMAKE_BINARY_DIR}/zephyr_modules.txt ZEPHYR_MODULES_TXT
 		ENCODING UTF-8)
+  set(module_names)
 
   foreach(module ${ZEPHYR_MODULES_TXT})
     # Match "<name>":"<path>" for each line of file, each corresponding to
@@ -465,30 +471,27 @@ if(EXISTS ${CMAKE_BINARY_DIR}/zephyr_modules.txt)
     # lazy regexes (it supports greedy only).
     string(REGEX REPLACE "\"(.*)\":\".*\"" "\\1" module_name ${module})
     string(REGEX REPLACE "\".*\":\"(.*)\"" "\\1" module_path ${module})
+
+    list(APPEND module_names ${module_name})
+
+    string(TOUPPER ${module_name} MODULE_NAME_UPPER)
+    set(ZEPHYR_${MODULE_NAME_UPPER}_MODULE_DIR ${module_path})
+  endforeach()
+
+  foreach(module_name ${module_names})
     # Note the second, binary_dir parameter requires the added
     # subdirectory to have its own, local cmake target(s). If not then
     # this binary_dir is created but stays empty. Object files land in
     # the main binary dir instead.
     # https://cmake.org/pipermail/cmake/2019-June/069547.html
-    set(ZEPHYR_CURRENT_MODULE_DIR ${module_path})
-    add_subdirectory(${module_path} ${CMAKE_BINARY_DIR}/modules/${module_name})
+    string(TOUPPER ${module_name} MODULE_NAME_UPPER)
+    set(ZEPHYR_CURRENT_MODULE_DIR ${ZEPHYR_${MODULE_NAME_UPPER}_MODULE_DIR})
+    add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR} ${CMAKE_BINARY_DIR}/modules/${module_name})
   endforeach()
   # Done processing modules, clear ZEPHYR_CURRENT_MODULE_DIR.
   set(ZEPHYR_CURRENT_MODULE_DIR)
 endif()
 
-set(syscall_macros_h ${ZEPHYR_BINARY_DIR}/include/generated/syscall_macros.h)
-
-add_custom_target(${SYSCALL_MACROS_H_TARGET} DEPENDS ${syscall_macros_h})
-add_custom_command(                          OUTPUT  ${syscall_macros_h}
-  COMMAND
-  ${PYTHON_EXECUTABLE}
-  ${ZEPHYR_BASE}/scripts/gen_syscall_header.py
-  > ${syscall_macros_h}
-  DEPENDS ${ZEPHYR_BASE}/scripts/gen_syscall_header.py
-  )
-
-
 set(syscall_list_h ${CMAKE_CURRENT_BINARY_DIR}/include/generated/syscall_list.h)
 set(syscalls_json  ${CMAKE_CURRENT_BINARY_DIR}/misc/generated/syscalls.json)
 
@@ -564,12 +567,21 @@ else()
   set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${syscalls_subdirs_txt})
 endif()
 
-# SYSCALL_INCLUDE_DIRECTORY will include the directories that needs to be
-# searched for syscall declarations if CONFIG_APPLICATION_DEFINED_SYSCALL is set
+# syscall declarations are searched for in the SYSCALL_INCLUDE_DIRS
 if(CONFIG_APPLICATION_DEFINED_SYSCALL)
-  set(SYSCALL_INCLUDE_DIRECTORY --include ${APPLICATION_SOURCE_DIR})
+  list(APPEND SYSCALL_INCLUDE_DIRS ${APPLICATION_SOURCE_DIR})
 endif()
 
+if(CONFIG_ZTEST)
+  list(APPEND SYSCALL_INCLUDE_DIRS ${ZEPHYR_BASE}/subsys/testsuite/ztest/include)
+endif()
+
+foreach(d ${SYSCALL_INCLUDE_DIRS})
+  list(APPEND parse_syscalls_include_args
+    --include ${d}
+    )
+endforeach()
+
 add_custom_command(
   OUTPUT
   ${syscalls_json}
@@ -577,7 +589,7 @@ add_custom_command(
   ${PYTHON_EXECUTABLE}
   ${ZEPHYR_BASE}/scripts/parse_syscalls.py
    --include          ${ZEPHYR_BASE}/include        # Read files from this dir
-  ${SYSCALL_INCLUDE_DIRECTORY}
+  ${parse_syscalls_include_args}                    # Read files from these dirs also
   --json-file        ${syscalls_json}              # Write this file
   DEPENDS ${syscalls_subdirs_trigger} ${PARSE_SYSCALLS_HEADER_DEPENDS}
   )
@@ -621,6 +633,14 @@ add_custom_target(${DRIVER_VALIDATION_H_TARGET} DEPENDS ${DRV_VALIDATION})
 include($ENV{ZEPHYR_BASE}/cmake/kobj.cmake)
 gen_kobj(KOBJ_INCLUDE_PATH)
 
+# Add a pseudo-target that is up-to-date when all generated headers
+# are up-to-date.
+
+add_custom_target(zephyr_generated_headers)
+add_dependencies(zephyr_generated_headers
+  offsets_h
+  )
+
 # Generate offsets.c.obj from offsets.c
 # Generate offsets.h     from offsets.c.obj
 
@@ -637,7 +657,6 @@ target_include_directories(${OFFSETS_LIB} PRIVATE
 target_link_libraries(${OFFSETS_LIB} zephyr_interface)
 add_dependencies(     ${OFFSETS_LIB}
   ${SYSCALL_LIST_H_TARGET}
-  ${SYSCALL_MACROS_H_TARGET}
   ${DRIVER_VALIDATION_H_TARGET}
   ${KOBJ_TYPES_H_TARGET}
   )
@@ -664,7 +683,7 @@ get_property(ZEPHYR_LIBS_PROPERTY GLOBAL PROPERTY ZEPHYR_LIBS)
 
 foreach(zephyr_lib ${ZEPHYR_LIBS_PROPERTY})
   # TODO: Could this become an INTERFACE property of zephyr_interface?
-  add_dependencies(${zephyr_lib} ${OFFSETS_H_TARGET})
+  add_dependencies(${zephyr_lib} zephyr_generated_headers)
 endforeach()
 
 get_property(OUTPUT_FORMAT        GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT)
@@ -679,7 +698,7 @@ configure_linker_script(
   ${PRIV_STACK_DEP}
   ${APP_SMEM_ALIGNED_DEP}
   ${CODE_RELOCATION_DEP}
-  ${OFFSETS_H_TARGET}
+  zephyr_generated_headers
   )
 
 add_custom_target(
@@ -793,6 +812,10 @@ if(CONFIG_ARM AND CONFIG_USERSPACE)
     )
   add_custom_target(priv_stacks DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${PRIV_STACKS})
 
+  if(${GPERF} STREQUAL GPERF-NOTFOUND)
+    message(FATAL_ERROR "Unable to find gperf")
+  endif()
+
   # Use gperf to generate C code (PRIV_STACKS_OUTPUT_SRC_PRE) which implements a
   # perfect hashtable based on PRIV_STACKS
   add_custom_command(
@@ -1060,9 +1083,6 @@ if(CONFIG_USERSPACE)
   if(CONFIG_NEWLIB_LIBC_NANO)
     set(NEWLIB_PART -l libc_nano.a z_libc_partition)
   endif()
-  if(CONFIG_MBEDTLS)
-    set(MBEDTLS_PART -l lib..__modules__crypto__mbedtls.a k_mbedtls_partition)
-  endif()
 
   add_custom_command(
     OUTPUT ${APP_SMEM_UNALIGNED_LD}
@@ -1070,7 +1090,7 @@ if(CONFIG_USERSPACE)
     ${ZEPHYR_BASE}/scripts/gen_app_partitions.py
     -d ${OBJ_FILE_DIR}
     -o ${APP_SMEM_UNALIGNED_LD}
-    ${NEWLIB_PART} ${MBEDTLS_PART}
+    ${NEWLIB_PART}
     $<TARGET_PROPERTY:zephyr_property_target,COMPILE_OPTIONS>
     $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
     DEPENDS
@@ -1087,7 +1107,7 @@ if(CONFIG_USERSPACE)
     ${CODE_RELOCATION_DEP}
     ${APP_SMEM_UNALIGNED_DEP}
     ${APP_SMEM_UNALIGNED_LD}
-    ${OFFSETS_H_TARGET}
+    zephyr_generated_headers
     )
 
   add_custom_target(
@@ -1121,7 +1141,7 @@ if(CONFIG_USERSPACE)
     ${ZEPHYR_BASE}/scripts/gen_app_partitions.py
     -e $<TARGET_FILE:app_smem_unaligned_prebuilt>
     -o ${APP_SMEM_ALIGNED_LD}
-    ${NEWLIB_PART} ${MBEDTLS_PART}
+    ${NEWLIB_PART}
     $<TARGET_PROPERTY:zephyr_property_target,COMPILE_OPTIONS>
     $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
     DEPENDS
@@ -1141,7 +1161,7 @@ if(CONFIG_USERSPACE AND CONFIG_ARM)
     ${CODE_RELOCATION_DEP}
     ${APP_SMEM_ALIGNED_DEP}
     ${APP_SMEM_ALIGNED_LD}
-    ${OFFSETS_H_TARGET}
+    zephyr_generated_headers
     )
 
   add_custom_target(
@@ -1199,7 +1219,7 @@ else()
     ${PRIV_STACK_DEP}
     ${CODE_RELOCATION_DEP}
     ${ZEPHYR_PREBUILT_EXECUTABLE}
-    ${OFFSETS_H_TARGET}
+    zephyr_generated_headers
     )
 
   set(LINKER_PASS_FINAL_SCRIPT_TARGET linker_pass_final_script_target)
@@ -1481,6 +1501,8 @@ if(HEX_FILES_TO_MERGE)
 
   add_custom_target(mergehex ALL DEPENDS ${MERGED_HEX_NAME})
   list(APPEND FLASH_DEPS mergehex)
+
+  message(VERBOSE "Merging hex files: ${HEX_FILES_TO_MERGE}")
 endif()
 
 if(EMU_PLATFORM)
@@ -1499,21 +1521,28 @@ add_subdirectory(cmake/flash)
 add_subdirectory(cmake/usage)
 add_subdirectory(cmake/reports)
 
+add_subdirectory_ifdef(
+  CONFIG_MAKEFILE_EXPORTS
+  cmake/makefile_exports
+  )
+
 if(NOT CONFIG_TEST)
 if(CONFIG_ASSERT AND (NOT CONFIG_FORCE_NO_ASSERT))
-  message(WARNING "
-      ------------------------------------------------------------
-      --- WARNING:  __ASSERT() statements are globally ENABLED ---
-      --- The kernel will run more slowly and use more memory  ---
-      ------------------------------------------------------------"
-  )
+  message(WARNING "__ASSERT() statements are globally ENABLED")
 endif()
 endif()
 
-if(CONFIG_BOARD_DEPRECATED)
+if(CONFIG_BOARD_DEPRECATED_RELEASE)
   message(WARNING "
       WARNING:  The board '${BOARD}' is deprecated and will be
-      removed in version ${CONFIG_BOARD_DEPRECATED}"
+      removed in version ${CONFIG_BOARD_DEPRECATED_RELEASE}"
+  )
+endif()
+
+if(CONFIG_SOC_DEPRECATED_RELEASE)
+  message(WARNING "
+      WARNING:  The SoC '${SOC_NAME}' is deprecated and will be
+      removed in version ${CONFIG_SOC_DEPRECATED_RELEASE}"
   )
 endif()
 
@@ -1526,7 +1555,7 @@ set(build_types None Debug Release RelWithDebInfo MinSizeRel)
 if((CMAKE_BUILD_TYPE IN_LIST build_types) AND (NOT NO_BUILD_TYPE_WARNING))
   string(TOUPPER ${CMAKE_BUILD_TYPE} CMAKE_BUILD_TYPE_uppercase)
 
-  if(NOT (${OPTIMIZATION_FLAG} IN_LIST ${CMAKE_C_FLAGS_${CMAKE_BUILD_TYPE_uppercase}}))
+  if(NOT (${OPTIMIZATION_FLAG} IN_LIST CMAKE_C_FLAGS_${CMAKE_BUILD_TYPE_uppercase}))
     message(WARNING "
       The CMake build type was set to '${CMAKE_BUILD_TYPE}', but the optimization flag was set to '${OPTIMIZATION_FLAG}'.
       This may be intentional and the warning can be turned off by setting the CMake variable 'NO_BUILD_TYPE_WARNING'"

CODEOWNERS

@@ -5,35 +5,44 @@
 # Order is important; for each modified file, the last matching
 # pattern takes the most precedence.
 # That is, with the last pattern being
-# *.rst                                     @dbkinder
-# if only .rst files are being modified, only dbkinder is
+# *.rst                                     @nashif
+# if only .rst files are being modified, only nashif is
 # automatically requested for review, but you can manually
 # add others as needed.
 
 # Do not use wildcard on all source yet
 # *                                        @galak @nashif
 
-/.known-issues/                           @inakypg @nashif
+/.known-issues/                           @nashif
+/.github/				  @nashif
+/.github/workflows/                       @galak @nashif
 /arch/arc/                                @vonhust @ruuddw
 /arch/arm/                                @MaureenHelm @galak @ioannisg
-/arch/arm/core/cortex_m/cmse/             @ioannisg
-/arch/arm/include/cortex_m/cmse.h         @ioannisg
-/arch/arm/core/cortex_r/                  @MaureenHelm @galak @ioannisg @bbolen
+/arch/arm/core/aarch32/cortex_m/cmse/     @ioannisg
+/arch/arm/core/aarch64/                   @carlocaione
+/arch/arm/include/aarch32/cortex_m/cmse.h @ioannisg
+/arch/arm/include/aarch64/                @carlocaione
+/arch/arm/core/aarch32/cortex_r/          @MaureenHelm @galak @ioannisg @bbolen @stephanosio
 /arch/common/                             @andrewboie @ioannisg @andyross
 /soc/arc/snps_*/                          @vonhust @ruuddw
 /soc/nios2/                               @nashif @wentongwu
 /soc/arm/                                 @MaureenHelm @galak @ioannisg
 /soc/arm/arm/mps2/                        @fvincenzo
 /soc/arm/atmel_sam/sam3x/                 @ioannisg
+/soc/arm/atmel_sam/sam4e/                 @nandojve
 /soc/arm/atmel_sam/sam4s/                 @fallrisk
+/soc/arm/atmel_sam/samv71/                @nandojve
+/soc/arm/bcm*/                            @sbranden
 /soc/arm/nxp*/                            @MaureenHelm
 /soc/arm/nordic_nrf/                      @ioannisg
+/soc/arm/qemu_cortex_a53/                 @carlocaione
 /soc/arm/st_stm32/                        @erwango
 /soc/arm/st_stm32/stm32f4/                @rsalveti @idlethread
-/soc/arm/st_stm32/stm32mp1/               @arnop2
+/soc/arm/st_stm32/stm32mp1/               @arnopo
 /soc/arm/ti_simplelink/cc13x2_cc26x2/     @bwitherspoon
 /soc/arm/ti_simplelink/cc32xx/            @vanti
 /soc/arm/ti_simplelink/msp432p4xx/        @Mani-Sadhasivam
+/soc/arm/xilinx_zynqmp/                   @stephanosio
 /soc/xtensa/intel_s1000/                  @sathishkuttan @dcpleung
 /arch/x86/                                @andrewboie
 /arch/nios2/                              @andrewboie @wentongwu
@@ -62,6 +71,7 @@
 /boards/arm/disco_l475_iot1/              @erwango
 /boards/arm/frdm*/                        @MaureenHelm
 /boards/arm/frdm*/doc/                    @MaureenHelm @MeganHansen
+/boards/arm/google_*/                     @jackrosenthal
 /boards/arm/hexiwear*/                    @MaureenHelm
 /boards/arm/hexiwear*/doc/                @MaureenHelm @MeganHansen
 /boards/arm/lpcxpresso*/                  @MaureenHelm
@@ -73,8 +83,12 @@
 /boards/arm/nrf*/                         @carlescufi @lemrey @ioannisg
 /boards/arm/nucleo*/                      @erwango
 /boards/arm/nucleo_f401re/                @rsalveti @idlethread
+/boards/arm/qemu_cortex_a53/              @carlocaione
+/boards/arm/qemu_cortex_r*/               @stephanosio
 /boards/arm/qemu_cortex_m*/               @ioannisg
+/boards/arm/sam4e_xpro/                   @nandojve
 /boards/arm/sam4s_xplained/               @fallrisk
+/boards/arm/sam_v71_xult/                 @nandojve
 /boards/arm/v2m_beetle/                   @fvincenzo
 /boards/arm/olimexino_stm32/              @ydamigos
 /boards/arm/sensortile_box/               @avisconti
@@ -104,6 +118,9 @@
 /doc/scripts/                             @carlescufi
 /doc/guides/bluetooth/                    @joerchan @jhedberg @Vudentz
 /doc/reference/bluetooth/                 @joerchan @jhedberg @Vudentz
+/doc/reference/kernel/other/resource_mgmt.rst @pabigot
+/doc/reference/networking/can*            @alexanderwachter
+/drivers/debug/                           @nashif
 /drivers/*/*cc13xx_cc26xx*                @bwitherspoon
 /drivers/*/*mcux*                         @MaureenHelm
 /drivers/*/*stm32*                        @erwango
@@ -118,39 +135,50 @@
 /drivers/counter/counter_cmos.c           @andrewboie
 /drivers/display/                         @vanwinkeljan
 /drivers/display/display_framebuf.c       @andrewboie
+/drivers/dma/*dw*                         @tbursztyka
 /drivers/dma/*sam0*                       @Sizurka
 /drivers/dma/dma_stm32*                   @cybertale
 /drivers/eeprom/                          @henrikbrixandersen
+/drivers/eeprom/eeprom_stm32.c            @KwonTae-young
 /drivers/entropy/*rv32m1*                 @MaureenHelm
 /drivers/espi/                            @albertofloyd @franciscomunoz @scottwcpg
 /drivers/ps2/                             @albertofloyd @franciscomunoz @scottwcpg
 /drivers/kscan/                           @albertofloyd @franciscomunoz @scottwcpg
 /drivers/ethernet/                        @jukkar @tbursztyka @pfalcon
+/drivers/entropy/*litex*                  @mateusz-holenko @kgugala @pgielda
 /drivers/flash/                           @nashif @nvlsianpu
-/drivers/flash/*native_posix*             @vanwinkeljan @aescolar
 /drivers/flash/*nrf*                      @nvlsianpu
 /drivers/flash/*spi_nor*                  @pabigot
 /drivers/flash/*stm32*                    @superna9999
 /drivers/gpio/                            @mnkp @pabigot
 /drivers/gpio/*ht16k33*                   @henrikbrixandersen
-/drivers/gpio/*stm32*                     @rsalveti @idlethread
+/drivers/gpio/*lmp90xxx*                  @henrikbrixandersen
+/drivers/gpio/*stm32*                     @erwango
+/drivers/gpio/*sx1509b*                   @pabigot
+/drivers/gpio/*litex*                     @mateusz-holenko @kgugala @pgielda
 /drivers/hwinfo/                          @alexanderwachter
+/drivers/i2c/*litex*                      @mateusz-holenko @kgugala @pgielda
 /drivers/i2s/i2s_ll_stm32*                @avisconti
+/drivers/i2c/i2c_shell.c                  @nashif
 /drivers/ieee802154/                      @jukkar @tbursztyka
+/drivers/ieee802154/ieee802154_rf2xx*     @jukkar @tbursztyka @nandojve
 /drivers/interrupt_controller/            @andrewboie
+/drivers/interrupt_controller/intc_gic.c  @stephanosio
+/drivers/*/intc_vexriscv_litex.c          @mateusz-holenko @kgugala @pgielda
 /drivers/ipm/ipm_mhu*                     @karl-zh
 /drivers/ipm/Kconfig.nrfx                 @masz-nordic @ioannisg
 /drivers/ipm/Kconfig.nrfx_ipc_channel     @masz-nordic @ioannisg
 /drivers/ipm/ipm_nrfx_ipc.c               @masz-nordic @ioannisg
 /drivers/ipm/ipm_nrfx_ipc.h               @masz-nordic @ioannisg
-/drivers/ipm/ipm_stm32_ipcc.c             @arnop2
-/drivers/*/vexriscv_litex.c               @mateusz-holenko @kgugala @pgielda
+/drivers/ipm/ipm_stm32_ipcc.c             @arnopo
 /drivers/led/                             @Mani-Sadhasivam
 /drivers/led_strip/                       @mbolivar
+/drivers/lora/                            @Mani-Sadhasivam
 /drivers/modem/                           @mike-scott
 /drivers/pcie/                            @andrewboie
 /drivers/pinmux/stm32/                    @rsalveti @idlethread
 /drivers/pinmux/*hsdk*                    @iriszzw
+/drivers/pwm/*litex*                      @mateusz-holenko @kgugala @pgielda
 /drivers/sensor/                          @MaureenHelm
 /drivers/sensor/ams_iAQcore/              @alexanderwachter
 /drivers/sensor/ens210/                   @alexanderwachter
@@ -169,11 +197,13 @@
 /drivers/serial/uart_xlnx_ps.c            @wjliang
 /drivers/net/                             @jukkar @tbursztyka
 /drivers/ptp_clock/                       @jukkar
+/drivers/pwm/*rv32m1*                     @henrikbrixandersen
 /drivers/pwm/pwm_shell.c                  @henrikbrixandersen
 /drivers/spi/                             @tbursztyka
 /drivers/spi/spi_ll_stm32.*               @superna9999
 /drivers/spi/spi_rv32m1_lpspi*            @karstenkoenig
 /drivers/timer/apic_timer.c               @andrewboie
+/drivers/timer/arm_arch_timer.c           @carlocaione
 /drivers/timer/cortex_m_systick.c         @ioannisg
 /drivers/timer/altera_avalon_timer_hal.c  @wentongwu
 /drivers/timer/riscv_machine_timer.c      @nategraff-sifive @kgugala @pgielda
@@ -187,12 +217,18 @@
 /drivers/i2c/i2c_rv32m1_lpi2c*            @henrikbrixandersen
 /drivers/i2c/*sam0*                       @Sizurka
 /drivers/i2c/i2c_dw*                      @dcpleung
-/drivers/*/*xec*                     @franciscomunoz @albertofloyd @scottwcpg
+/drivers/*/*xec*                          @franciscomunoz @albertofloyd @scottwcpg
+/drivers/watchdog/*gecko*                 @oanerer
+/drivers/watchdog/wdt_handlers.c          @andrewboie
 /drivers/wifi/                            @jukkar @tbursztyka @pfalcon
 /drivers/wifi/eswifi/                     @loicpoulain
 /dts/arc/                                 @vonhust @ruuddw @iriszzw
+/dts/arm/atmel/sam4e*                     @nandojve
 /dts/arm/atmel/samr21.dtsi                @benpicco
 /dts/arm/atmel/sam*5*.dtsi                @benpicco
+/dts/arm/atmel/samv71*                    @nandojve
+/dts/arm/broadcom/                        @sbranden
+/dts/arm/qemu-virt/                       @carlocaione
 /dts/arm/st/                              @erwango
 /dts/arm/ti/cc13?2*                       @bwitherspoon
 /dts/arm/ti/cc26?2*                       @bwitherspoon
@@ -200,13 +236,19 @@
 /dts/arm/nordic/                          @ioannisg @carlescufi
 /dts/arm/nxp/                             @MaureenHelm
 /dts/arm/microchip/                       @franciscomunoz @albertofloyd @scottwcpg
+/dts/arm/silabs/efm32gg11b*               @oanerer
+/dts/arm/silabs/efm32_jg_pg*              @chrta
+/dts/arm/silabs/efm32jg12b*               @chrta
+/dts/arm/silabs/efm32pg12b*               @chrta
 /dts/riscv/microsemi-miv.dtsi             @galak
 /dts/riscv/rv32m1*                        @MaureenHelm
 /dts/riscv/riscv32-fe310.dtsi             @nategraff-sifive
 /dts/riscv/riscv32-litex-vexriscv.dtsi    @mateusz-holenko @kgugala @pgielda
-/dts/arm/armv7-r.dtsi                     @bbolen
-/dts/arm/xilinx/                          @bbolen
+/dts/arm/armv7-r.dtsi                     @bbolen @stephanosio
+/dts/arm/armv8-a.dtsi                     @carlocaione
+/dts/arm/xilinx/                          @bbolen @stephanosio
 /dts/xtensa/xtensa.dtsi                   @ydamigos
+/dts/xtensa/intel/                        @dcpleung
 /dts/bindings/                            @galak
 /dts/bindings/can/                        @alexanderwachter
 /dts/bindings/iio/adc/st*stm32-adc.yaml   @cybertale
@@ -234,18 +276,22 @@
 /include/drivers/flash.h                  @nashif @carlescufi @galak @MaureenHelm @nvlsianpu
 /include/drivers/led/ht16k33.h            @henrikbrixandersen
 /include/drivers/interrupt_controller/    @andrewboie
+/include/drivers/interrupt_controller/gic.h @stephanosio
 /include/drivers/pcie/                    @andrewboie
 /include/drivers/hwinfo.h                 @alexanderwachter
 /include/drivers/led.h                    @Mani-Sadhasivam
 /include/drivers/led_strip.h              @mbolivar
 /include/drivers/sensor.h                 @MaureenHelm
 /include/drivers/spi.h                    @tbursztyka
+/include/drivers/lora.h                   @Mani-Sadhasivam
 /include/app_memory/                      @andrewboie
 /include/arch/arc/                        @vonhust @ruuddw
 /include/arch/arc/arch.h                  @andrewboie
 /include/arch/arc/v2/irq.h                @andrewboie
-/include/arch/arm/                        @MaureenHelm @galak @ioannisg
-/include/arch/arm/irq.h                   @andrewboie
+/include/arch/arm/aarch32/                @MaureenHelm @galak @ioannisg
+/include/arch/arm/aarch32/cortex_r/       @stephanosio
+/include/arch/arm/aarch64/                @carlocaione
+/include/arch/arm/aarch32/irq.h           @andrewboie
 /include/arch/nios2/                      @andrewboie
 /include/arch/nios2/arch.h                @andrewboie
 /include/arch/posix/                      @aescolar
@@ -256,6 +302,9 @@
 /include/sys/atomic.h                     @andrewboie @andyross
 /include/bluetooth/                       @joerchan @jhedberg @Vudentz
 /include/cache.h                          @andrewboie @andyross
+/include/canbus/                          @alexanderwachter
+/include/tracing/                         @wentongwu @nashif
+/include/debug/                           @nashif
 /include/device.h                         @wentongwu @nashif
 /include/display/                         @vanwinkeljan
 /include/dt-bindings/clock/kinetis_mcg.h  @henrikbrixandersen
@@ -272,7 +321,6 @@
 /include/linker/app_smem*.ld              @andrewboie
 /include/linker/                          @andrewboie @andyross
 /include/logging/                         @nordic-krch
-/include/misc/                            @andrewboie @andyross
 /include/net/                             @jukkar @tbursztyka @pfalcon
 /include/net/buf.h                        @jukkar @jhedberg @tbursztyka @pfalcon
 /include/posix/                           @pfalcon
@@ -304,8 +352,9 @@
 /samples/boards/intel_s1000_crb/          @sathishkuttan @dcpleung @nashif
 /samples/display/                         @vanwinkeljan
 /samples/drivers/CAN/                     @alexanderwachter
+/samples/drivers/display/                 @vanwinkeljan
 /samples/drivers/ht16k33/                 @henrikbrixandersen
-/samples/gui/                             @vanwinkeljan
+/samples/drivers/lora/                    @Mani-Sadhasivam
 /samples/net/                             @jukkar @tbursztyka @pfalcon
 /samples/net/dns_resolve/                 @jukkar @tbursztyka @pfalcon
 /samples/net/lwm2m_client/                @mike-scott
@@ -319,6 +368,7 @@
 /samples/subsys/shell/                    @jakub-uC @nordic-krch
 /samples/subsys/usb/                      @jfischer-phytec-iot @finikorg
 /samples/subsys/power/                    @wentongwu @pabigot
+/samples/userspace/                       @andrewboie
 /scripts/coccicheck                       @himanshujha199640 @JuliaLawall
 /scripts/coccinelle/                      @himanshujha199640 @JuliaLawall
 /scripts/kconfig/                         @ulfalizer
@@ -331,10 +381,11 @@
 /arch/x86/gen_idt.py                      @andrewboie
 /scripts/gen_kobject_list.py              @andrewboie
 /scripts/gen_priv_stacks.py               @andrewboie @agross-oss @ioannisg
-/scripts/gen_syscall_header.py            @andrewboie
 /scripts/gen_syscalls.py                  @andrewboie
+/scripts/net/                             @jukkar @pfl
 /scripts/process_gperf.py                 @andrewboie
 /scripts/gen_relocate_app.py              @wentongwu
+/scripts/tracing/                         @wentongwu
 /scripts/sanity_chk/                      @nashif
 /scripts/sanitycheck                      @nashif
 /scripts/series-push-hook.sh              @erwango
@@ -345,9 +396,11 @@
 /subsys/bluetooth/                        @joerchan @jhedberg @Vudentz
 /subsys/bluetooth/controller/             @carlescufi @cvinayak @thoh-ot
 /subsys/bluetooth/mesh/                   @jhedberg @trond-snekvik @joerchan @Vudentz
+/subsys/canbus/                           @alexanderwachter
 /subsys/cpp/                              @pabigot @vanwinkeljan
 /subsys/debug/                            @nashif
-/subsys/debug/asan.c                      @vanwinkeljan @aescolar
+/subsys/tracing/                          @nashif @wentongwu
+/subsys/debug/asan_hacks.c                @vanwinkeljan @aescolar
 /subsys/disk/disk_access_spi_sdhc.c       @JunYangNXP
 /subsys/disk/disk_access_sdhc.h           @JunYangNXP
 /subsys/disk/disk_access_usdhc.c          @JunYangNXP
@@ -365,7 +418,7 @@
 /subsys/net/lib/                          @jukkar @tbursztyka @pfalcon
 /subsys/net/lib/dns/                      @jukkar @tbursztyka @pfalcon
 /subsys/net/lib/lwm2m/                    @mike-scott
-/subsys/net/lib/config/                   @jukkar @tbursztyka
+/subsys/net/lib/config/                   @jukkar @tbursztyka @pfalcon
 /subsys/net/lib/mqtt/                     @jukkar @tbursztyka @rlubos
 /subsys/net/lib/openthread/               @rlubos
 /subsys/net/lib/coap/                     @rveerama1
@@ -386,11 +439,13 @@
 /tests/boards/native_posix/               @aescolar
 /tests/boards/intel_s1000_crb/            @dcpleung @sathishkuttan
 /tests/bluetooth/                         @joerchan @jhedberg @Vudentz
+/tests/bluetooth/bsim_bt/                 @joerchan @jhedberg @Vudentz @aescolar
 /tests/posix/                             @pfalcon
 /tests/crypto/                            @ceolin
 /tests/crypto/mbedtls/                    @nashif @ceolin
 /tests/drivers/can/                       @alexanderwachter
 /tests/drivers/flash_simulator/           @nvlsianpu
+/tests/drivers/gpio/                      @mnkp @pabigot
 /tests/drivers/hwinfo/                    @alexanderwachter
 /tests/drivers/spi/                       @tbursztyka
 /tests/drivers/uart/uart_async_api/       @Mierunski
@@ -407,5 +462,5 @@
 /tests/subsys/settings/                   @nvlsianpu
 /tests/subsys/shell/                      @jakub-uC @nordic-krch
 # Get all docs reviewed
-*.rst                                     @dbkinder
-*posix*.rst                               @dbkinder @aescolar
+*.rst                                     @nashif
+*posix*.rst                               @aescolar

Kconfig.zephyr

@@ -11,37 +11,30 @@ source "modules/Kconfig"
 
 endmenu
 
-# Include these first so that any properties (e.g. defaults) below can be
-# overridden in *.defconfig files (by defining symbols in multiple locations).
-# After merging all the symbol definitions, Kconfig picks the first property
-# (e.g. the first default) with a satisfied condition.
+# Include Kconfig.defconfig files first so that they can override defaults and
+# other symbol/choice properties by adding extra symbol/choice definitions.
+# After merging all definitions for a symbol/choice, Kconfig picks the first
+# property (e.g. the first default) with a satisfied condition.
 #
-# Board defaults should be parsed before SoC defaults, because boards usually
-# overrides SoC values.
+# Shield defaults should have precedence over board defaults, which should have
+# precedence over SoC defaults, so include them in that order.
 #
-# Note: $ARCH and $BOARD_DIR might be glob patterns.
+# $ARCH and $BOARD_DIR will be glob patterns when building documentation.
+source "boards/shields/*/Kconfig.defconfig"
 source "$(BOARD_DIR)/Kconfig.defconfig"
-
 source "$(SOC_DIR)/$(ARCH)/*/Kconfig.defconfig"
 
 source "boards/Kconfig"
-
 source "$(SOC_DIR)/Kconfig"
-
 source "arch/Kconfig"
-
 source "kernel/Kconfig"
-
 source "dts/Kconfig"
-
 source "drivers/Kconfig"
-
 source "lib/Kconfig"
-
 source "subsys/Kconfig"
-
 source "ext/Kconfig"
 
+osource "$(TOOLCHAIN_KCONFIG_DIR)/Kconfig"
 
 menu "Build and Link Features"
 
@@ -85,20 +78,24 @@ config HAS_FLASH_LOAD_OFFSET
 	  This option is selected by targets having a FLASH_LOAD_OFFSET
 	  and FLASH_LOAD_SIZE.
 
-config USE_CODE_PARTITION
-	bool "link into code-partition"
-	depends on HAS_FLASH_LOAD_OFFSET
+if HAS_FLASH_LOAD_OFFSET
+
+config USE_DT_CODE_PARTITION
+	bool "Link application into /chosen/zephyr,code-partition from devicetree"
 	help
-	  When selected application will be linked into chosen code-partition.
+	  When enabled, the application will be linked into the flash partition
+	  selected by the zephyr,code-partition property in /chosen in devicetree.
+	  When this is disabled, the flash load offset and size can be set manually
+	  below.
 
 # Workaround for not being able to have commas in macro arguments
 DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
 
 config FLASH_LOAD_OFFSET
-	hex "Kernel load offset"
-	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_CODE_PARTITION
+	# Only user-configurable when USE_DT_CODE_PARTITION is disabled
+	hex "Kernel load offset" if !USE_DT_CODE_PARTITION
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_DT_CODE_PARTITION
 	default 0
-	depends on HAS_FLASH_LOAD_OFFSET
 	help
 	  This option specifies the byte offset from the beginning of flash that
 	  the kernel should be loaded into. Changing this value from zero will
@@ -108,10 +105,10 @@ config FLASH_LOAD_OFFSET
 	  If unsure, leave at the default value 0.
 
 config FLASH_LOAD_SIZE
-	hex "Kernel load size"
-	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_CODE_PARTITION
+	# Only user-configurable when USE_DT_CODE_PARTITION is disabled
+	hex "Kernel load size" if !USE_DT_CODE_PARTITION
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_DT_CODE_PARTITION
 	default 0
-	depends on HAS_FLASH_LOAD_OFFSET
 	help
 	  If non-zero, this option specifies the size, in bytes, of the flash
 	  area that the Zephyr image will be allowed to occupy.  If zero, the
@@ -120,6 +117,8 @@ config FLASH_LOAD_SIZE
 
 	  If unsure, leave at the default value 0.
 
+endif # HAS_FLASH_LOAD_OFFSET
+
 config TEXT_SECTION_OFFSET
 	hex
 	prompt "TEXT section offset" if !BOOTLOADER_MCUBOOT
@@ -248,6 +247,28 @@ config COMPILER_OPT
 
 endmenu
 
+choice
+	prompt "Error checking behavior for CHECK macro"
+	default RUNTIME_ERROR_CHECKS
+
+config ASSERT_ON_ERRORS
+	bool "Assert on all errors"
+	help
+	  Assert on errors covered with the CHECK macro.
+
+config NO_RUNTIME_CHECKS
+	bool "No runtime error checks"
+	help
+	  Do not do any runtime checks or asserts when using the CHECK macro.
+
+config RUNTIME_ERROR_CHECKS
+	bool "Enable runtime error checks"
+	help
+	  Always perform runtime checks covered with the CHECK macro. This
+	  option is the default and the only option used during testing.
+
+endchoice
+
 menu "Build Options"
 
 config KERNEL_BIN_NAME
@@ -309,7 +330,6 @@ config BUILD_OUTPUT_S19
 
 config BUILD_NO_GAP_FILL
 	bool "Don't fill gaps in generated hex/bin/s19 files."
-	depends on BUILD_OUTPUT_HEX || BUILD_OUTPUT_BIN || BUILD_OUTPUT_S19
 
 config BUILD_OUTPUT_STRIPPED
 	bool "Build a stripped binary"
@@ -323,6 +343,12 @@ config APPLICATION_DEFINED_SYSCALL
 	  Scan additional folders inside application source folder
 	  for application defined syscalls.
 
+config MAKEFILE_EXPORTS
+	bool "Generate build metadata files named Makefile.exports"
+	help
+	  Generates a file with build information that can be read by
+	  third party Makefile-based build systems.
+
 endmenu
 endmenu
 
@@ -351,7 +377,7 @@ config BOOTLOADER_SRAM_SIZE
 
 config BOOTLOADER_MCUBOOT
 	bool "MCUboot bootloader support"
-	select USE_CODE_PARTITION
+	select USE_DT_CODE_PARTITION
 	help
 	  This option signifies that the target uses MCUboot as a bootloader,
 	  or in other words that the image is to be chain-loaded by MCUboot.
@@ -363,8 +389,6 @@ config BOOTLOADER_MCUBOOT
 	      for the MCUboot image header
 	    * Activating SW_VECTOR_RELAY on Cortex-M0 (or Armv8-M baseline)
 	      targets with no built-in vector relocation mechanisms
-	    * Including dts/common/mcuboot.overlay when building the Device
-	      Tree in order to place and link the image at the slot0 offset
 
 config BOOTLOADER_ESP_IDF
 	bool "ESP-IDF bootloader support"
@@ -408,7 +432,6 @@ config MISRA_SANE
 
 endmenu
 
-
 menu "Compatibility"
 
 config COMPAT_INCLUDES

README.rst

@@ -1,4 +1,3 @@
-
 .. raw:: html
 
    <a href="https://www.zephyrproject.org">

VERSION

@@ -1,5 +1,5 @@
 VERSION_MAJOR = 2
-VERSION_MINOR = 1
+VERSION_MINOR = 2
 PATCHLEVEL = 0
 VERSION_TWEAK = 0
 EXTRAVERSION =

arch/Kconfig

@@ -11,49 +11,75 @@
 # Note: $ARCH might be a glob pattern
 source "$(ARCH_DIR)/$(ARCH)/Kconfig"
 
-choice ARCH_CHOICE
-	prompt "Architecture"
-	default X86
+# Architecture symbols
+#
+# Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
+# by SOC_*.
 
 config ARC
-	bool "ARC architecture"
+	bool
+	select ARCH_IS_SET
 	select HAS_DTS
+	help
+	  ARC architecture
 
 config ARM
-	bool "ARM architecture"
+	bool
+	select ARCH_IS_SET
 	select HAS_DTS
+	help
+	  ARM architecture
 
 config X86
-	bool "x86 architecture"
+	bool
+	select ARCH_IS_SET
 	select ATOMIC_OPERATIONS_BUILTIN
 	select HAS_DTS
+	help
+	  x86 architecture
 
 config NIOS2
-	bool "Nios II Gen 2 architecture"
+	bool
+	select ARCH_IS_SET
 	select ATOMIC_OPERATIONS_C
 	select HAS_DTS
+	help
+	  Nios II Gen 2 architecture
 
 config RISCV
-	bool "RISCV architecture"
+	bool
+	select ARCH_IS_SET
 	select HAS_DTS
+	help
+	  RISCV architecture
 
 config XTENSA
-	bool "Xtensa architecture"
+	bool
+	select ARCH_IS_SET
 	select HAS_DTS
 	select USE_SWITCH
 	select USE_SWITCH_SUPPORTED
+	select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
+	help
+	  Xtensa architecture
 
 config ARCH_POSIX
-	bool "POSIX (native) architecture"
+	bool
+	select ARCH_IS_SET
 	select ATOMIC_OPERATIONS_BUILTIN
 	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
 	select ARCH_HAS_CUSTOM_BUSY_WAIT
 	select ARCH_HAS_THREAD_ABORT
 	select NATIVE_APPLICATION
 	select HAS_COVERAGE_SUPPORT
+	help
+	  POSIX (native) architecture
 
-endchoice
-
+config ARCH_IS_SET
+	bool
+	help
+	  Helper symbol to detect SoCs forgetting to select one of the arch
+	  symbols above. See the top-level CMakeLists.txt.
 
 menu "General Architecture Options"
 
@@ -84,8 +110,6 @@ config 64BIT
 	  soc/**/Kconfig, or boards/**/Kconfig and the user should generally
 	  avoid modifying it.
 
-if ARC || ARM || NIOS2 || X86
-
 # Workaround for not being able to have commas in macro arguments
 DT_CHOSEN_Z_SRAM := zephyr,sram
 
@@ -93,17 +117,19 @@ config SRAM_SIZE
 	int "SRAM Size in kB"
 	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K)
 	help
-	  This option specifies the size of the SRAM in kB.  It is normally set by
-	  the board's defconfig file and the user should generally avoid modifying
-	  it via the menu configuration.
+	  The SRAM size in kB. The default value comes from /chosen/zephyr,sram in
+	  devicetree. The user should generally avoid changing it via menuconfig or
+	  in configuration files.
 
 config SRAM_BASE_ADDRESS
 	hex "SRAM Base Address"
 	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))
 	help
-	  This option specifies the base address of the SRAM on the board.  It is
-	  normally set by the board's defconfig file and the user should generally
-	  avoid modifying it via the menu configuration.
+	  The SRAM base address. The default value comes from from
+	  /chosen/zephyr,sram in devicetree. The user should generally avoid
+	  changing it via menuconfig or in configuration files.
+
+if ARC || ARM || NIOS2 || X86
 
 # Workaround for not being able to have commas in macro arguments
 DT_CHOSEN_Z_FLASH := zephyr,flash
@@ -171,6 +197,7 @@ config HW_STACK_PROTECTION
 config USERSPACE
 	bool "User mode threads"
 	depends on ARCH_HAS_USERSPACE
+	depends on RUNTIME_ERROR_CHECKS
 	help
 	  When enabled, threads may be created or dropped down to user mode,
 	  which has significantly restricted permissions and must interact
@@ -216,6 +243,14 @@ config STACK_GROWS_UP
 	  Select this option if the architecture has upward growing thread
 	  stacks. This is not common.
 
+config NO_UNUSED_STACK_INSPECTION
+	bool
+	help
+	  Selected if the architecture will generate a fault if unused stack
+	  memory is examined, which is the region between the current stack
+	  pointer and the deepest available address in the current stack
+	  region.
+
 config MAX_THREAD_BYTES
 	int "Bytes to use when tracking object thread permissions"
 	default 2
@@ -239,22 +274,17 @@ config DYNAMIC_OBJECTS
 	  API call, or when the number of references to that object drops to
 	  zero.
 
-if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
-
 config NOCACHE_MEMORY
 	bool "Support for uncached memory"
+	depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT
 	help
 	  Add a "nocache" read-write memory section that is configured to
 	  not be cached. This memory section can be used to perform DMA
 	  transfers when cache coherence issues are not optimal or can not
 	  be solved using cache maintenance operations.
 
-endif # ARCH_HAS_NOCACHE_MEMORY_SUPPORT
-
 menu "Interrupt Configuration"
-#
-# Interrupt related configs
-#
+
 config DYNAMIC_INTERRUPTS
 	bool "Enable installation of IRQs at runtime"
 	help
@@ -313,7 +343,6 @@ config GEN_IRQ_START_VECTOR
 	  This is a hidden option which needs to be set per architecture and
 	  left alone.
 
-
 config IRQ_OFFLOAD
 	bool "Enable IRQ offload"
 	depends on TEST
@@ -329,6 +358,7 @@ endmenu
 #
 # Architecture Capabilities
 #
+
 config ARCH_HAS_TRUSTED_EXECUTION
 	bool
 
@@ -361,57 +391,51 @@ config ARCH_HAS_THREAD_ABORT
 # Hidden PM feature configs which are to be selected by
 # individual SoC.
 #
+
 config HAS_SYS_POWER_STATE_SLEEP_1
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_SLEEP_1
 	  configuration option.
 
 config HAS_SYS_POWER_STATE_SLEEP_2
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_SLEEP_2
 	  configuration option.
 
 config HAS_SYS_POWER_STATE_SLEEP_3
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_SLEEP_3
 	  configuration option.
 
 config HAS_SYS_POWER_STATE_DEEP_SLEEP_1
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_1
 	  configuration option.
 
 config HAS_SYS_POWER_STATE_DEEP_SLEEP_2
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_2
 	  configuration option.
 
 config HAS_SYS_POWER_STATE_DEEP_SLEEP_3
-	# Hidden
 	bool
 	help
 	  This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_3
 	  configuration option.
 
 config BOOTLOADER_CONTEXT_RESTORE_SUPPORTED
-	# Hidden
 	bool
 	help
 	  This option signifies that the target has options of bootloaders
 	  that support context restore upon resume from deep sleep
 
-
-# End hidden CPU family configs
+#
+# Hidden CPU family configs
 #
 
 config CPU_HAS_TEE
@@ -421,6 +445,12 @@ config CPU_HAS_TEE
 	  Execution Environment (e.g. when it has a security attribution
 	  unit).
 
+config CPU_HAS_DCLS
+	bool
+	help
+	  This option is enabled when the processor hardware is configured in
+	  Dual-redundant Core Lock-step (DCLS) topology.
+
 config CPU_HAS_FPU
 	bool
 	help
@@ -487,20 +517,13 @@ menuconfig FLOAT
 	  Disabling this option means that any thread that uses a
 	  floating point register will get a fatal exception.
 
-if FLOAT
-
 config FP_SHARING
 	bool "Floating point register sharing"
+	depends on FLOAT
 	help
 	  This option allows multiple threads to use the floating point
 	  registers.
 
-endif # FLOAT
-
-#
-# End hidden PM feature configs
-#
-
 config ARCH
 	string
 	help

arch/arc/Kconfig

@@ -117,7 +117,6 @@ config ARC_FIRQ
 config ARC_FIRQ_STACK
 	bool "Enable separate firq stack"
 	depends on ARC_FIRQ && RGF_NUM_BANKS > 1
-	default n
 	help
 	  Use separate stack for FIRQ handing. When the fast irq is also a direct
 	  irq, this will get the minimal interrupt latency.
@@ -129,7 +128,7 @@ config ARC_FIRQ_STACK_SIZE
 	help
 	  The size of firq stack.
 
-config 	ARC_HAS_STACK_CHECKING
+config ARC_HAS_STACK_CHECKING
 	bool "ARC has STACK_CHECKING"
 	default y
 	help
@@ -146,6 +145,7 @@ config ARC_CONNECT
 
 config ARC_STACK_CHECKING
 	bool
+	select NO_UNUSED_STACK_INSPECTION
 	help
 	  Use ARC STACK_CHECKING to do stack protection
 
@@ -167,7 +167,6 @@ config ARC_STACK_PROTECTION
 
 config ARC_USE_UNALIGNED_MEM_ACCESS
 	bool "Enable unaligned access in HW"
-	default n if CPU_ARCEM
 	default y if CPU_ARCHS
 	depends on (CPU_ARCEM && !ARC_HAS_SECURE) || CPU_ARCHS
 	help
@@ -235,8 +234,7 @@ config SJLI_TABLE_SIZE
 	  sjli instruction.
 
 config ARC_SECURE_FIRMWARE
-	prompt "Generate Secure Firmware"
-	bool
+	bool "Generate Secure Firmware"
 	depends on ARC_HAS_SECURE
 	default y if TRUSTED_EXECUTION_SECURE
 	help
@@ -252,8 +250,7 @@ config ARC_SECURE_FIRMWARE
 	  and normal resources of the ARC processors.
 
 config ARC_NORMAL_FIRMWARE
-	prompt "Generate Normal Firmware"
-	bool
+	bool "Generate Normal Firmware"
 	depends on !ARC_SECURE_FIRMWARE
 	depends on ARC_HAS_SECURE
 	default y if TRUSTED_EXECUTION_NONSECURE

arch/arc/core/CMakeLists.txt

@@ -30,3 +30,5 @@ zephyr_library_sources_ifdef(CONFIG_ARC_CONNECT arc_smp.c)
 
 add_subdirectory_ifdef(CONFIG_ARC_CORE_MPU mpu)
 add_subdirectory_ifdef(CONFIG_ARC_SECURE_FIRMWARE secureshield)
+
+zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)

arch/arc/core/arc_smp.c

@@ -24,7 +24,7 @@
 #define ARCV2_ICI_IRQ_PRIORITY 1
 
 volatile struct {
-	void (*fn)(int, void*);
+	arch_cpustart_t fn;
 	void *arg;
 } arc_cpu_init[CONFIG_MP_NUM_CPUS];
 
@@ -46,7 +46,7 @@ volatile _cpu_t *_curr_cpu[CONFIG_MP_NUM_CPUS];
 
 /* Called from Zephyr initialization */
 void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
-		    void (*fn)(int, void *), void *arg)
+		    arch_cpustart_t fn, void *arg)
 {
 	_curr_cpu[cpu_num] = &(_kernel.cpus[cpu_num]);
 	arc_cpu_init[cpu_num].fn = fn;
@@ -69,7 +69,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
 /* the C entry of slave cores */
 void z_arc_slave_start(int cpu_num)
 {
-	void (*fn)(int, void*);
+	arch_cpustart_t fn;
 
 #ifdef CONFIG_SMP
 	z_icache_setup();
@@ -82,7 +82,7 @@ void z_arc_slave_start(int cpu_num)
 	/* call the function set by arch_start_cpu */
 	fn = arc_cpu_init[cpu_num].fn;
 
-	fn(cpu_num, arc_cpu_init[cpu_num].arg);
+	fn(arc_cpu_init[cpu_num].arg);
 }
 
 #ifdef CONFIG_SMP
@@ -119,7 +119,7 @@ u64_t z_arc_smp_switch_in_isr(void)
 		_current_cpu->swap_ok = 0;
 		((struct k_thread *)new_thread)->base.cpu =
 				arch_curr_cpu()->id;
-		_current = (struct k_thread *) new_thread;
+		_current_cpu->current = (struct k_thread *) new_thread;
 		ret = new_thread | ((u64_t)(old_thread) << 32);
 	}
 

arch/arc/core/fast_irq.S

@@ -155,8 +155,6 @@ SECTION_FUNC(TEXT, _firq_exit)
 	bl z_check_stack_sentinel
 #endif
 
-#ifdef CONFIG_PREEMPT_ENABLED
-
 #ifdef CONFIG_SMP
 	bl z_arc_smp_switch_in_isr
 	/* r0 points to new thread, r1 points to old thread */
@@ -171,8 +169,6 @@ SECTION_FUNC(TEXT, _firq_exit)
 #endif
 	/* fall to no rescheduling */
 
-#endif /* CONFIG_PREEMPT_ENABLED */
-
 .balign 4
 _firq_no_reschedule:
 	pop sp
@@ -186,8 +182,6 @@ _firq_no_reschedule:
 #endif
 	rtie
 
-#ifdef CONFIG_PREEMPT_ENABLED
-
 .balign 4
 _firq_reschedule:
 	pop sp
@@ -207,12 +201,36 @@ _firq_reschedule:
 	 * point, so when switching back to register bank 0, it will contain the
 	 * registers from the interrupted thread.
 	 */
-
+#if defined(CONFIG_USERSPACE)
+/* when USERSPACE is configured, here need to consider the case where firq comes
+ * out in user mode, according to ARCv2 ISA and nsim, the following micro ops
+ * will be executed:
+ *	sp<-reg bank1'sp
+ *      switch between sp and _ARC_V2_USER_SP
+ * then:
+ *      sp is the sp of kernel stack of interrupted thread
+ *      _ARC_V2_USER_SP is reg bank1'sp
+ *      the sp of user stack of interrupted thread is reg bank0'sp
+ * if firq comes out in kernel mode, the following micro ops will be executed:
+ *      sp<-reg bank'sp
+ * so, sw needs to do necessary handling to set up the correct sp
+ */
+	lr r0, [_ARC_V2_AUX_IRQ_ACT]
+	bbit0 r0, 31, _firq_from_kernel
+	aex sp, [_ARC_V2_USER_SP]
+	lr r0, [_ARC_V2_STATUS32]
+	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
+	kflag r0
+	aex sp, [_ARC_V2_USER_SP]
+	b _firq_create_irq_stack_frame
+_firq_from_kernel:
+#endif
 	/* chose register bank #0 */
 	lr r0, [_ARC_V2_STATUS32]
 	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
 	kflag r0
 
+_firq_create_irq_stack_frame:
 	/* we're back on the outgoing thread's stack */
 	_create_irq_stack_frame
 
@@ -225,6 +243,7 @@ _firq_reschedule:
 	st_s r0, [sp, ___isf_t_status32_OFFSET]
 
 	st ilink, [sp, ___isf_t_pc_OFFSET] /* ilink into pc */
+
 #ifdef CONFIG_SMP
 /*
  * load r0, r1 from irq stack
@@ -235,6 +254,16 @@ _firq_reschedule:
 #endif
 #endif
 
+#if defined(CONFIG_USERSPACE)
+/*
+ * need to remember the user/kernel status of interrupted thread, will be
+ * restored when thread switched back
+ */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	and r3, r3, 0x80000000
+	push_s r3
+#endif
+
 #ifdef CONFIG_SMP
 	mov_s r2, r1
 #else
@@ -300,6 +329,16 @@ _firq_return_from_coop:
 _firq_return_from_rirq:
 _firq_return_from_firq:
 
+#if defined(CONFIG_USERSPACE)
+/*
+ * need to recover the user/kernel status of interrupted thread
+ */
+	pop_s r3
+	lr r2, [_ARC_V2_AUX_IRQ_ACT]
+	or r2, r2, r3
+	sr r2, [_ARC_V2_AUX_IRQ_ACT]
+#endif
+
 	_pop_irq_stack_frame
 
 	ld ilink, [sp, -4] /* status32 into ilink */
@@ -308,5 +347,3 @@ _firq_return_from_firq:
 
 	/* LP registers are already restored, just switch back to bank 0 */
 	rtie
-
-#endif /* CONFIG_PREEMPT_ENABLED */

arch/arc/core/fault_s.S

@@ -114,7 +114,6 @@ _exc_return:
  * exception comes out,  thread context?irq_context?nest irq context?
  */
 
-#ifdef CONFIG_PREEMPT_ENABLED
 #ifdef CONFIG_SMP
 	bl z_arc_smp_switch_in_isr
 	breq r0, 0, _exc_return_from_exc
@@ -187,7 +186,6 @@ _exc_return:
 
 	/* Assumption: r2 has current thread */
 	b _rirq_common_interrupt_swap
-#endif
 
 _exc_return_from_exc:
 	ld_s r0, [sp, ___isf_t_pc_OFFSET]
@@ -208,7 +206,7 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	/* do sys_call */
 	mov_s ilink, K_SYSCALL_LIMIT
 	cmp r6, ilink
-	blt valid_syscall_id
+	blo valid_syscall_id
 
 	mov_s r0, r6
 	mov_s r6, K_SYSCALL_BAD
@@ -277,83 +275,6 @@ exc_nest_handle:
 
 	_dec_int_nest_counter r0, r1
 
-	lr  r0, [_ARC_V2_AUX_IRQ_ACT]
-	and r0, r0, 0xffff
-	cmp r0, 0
-	bne _exc_return_from_exc
-
-#ifdef CONFIG_PREEMPT_ENABLED
-#ifdef CONFIG_SMP
-	bl z_arc_smp_switch_in_isr
-	breq r0, 0, _exc_return_from_irqoffload_trap
-	mov_s r2, r1
-
-	_save_callee_saved_regs
-
-	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
-	mov_s r2, r0
-#else
-	mov_s r1, _kernel
-	ld_s r2, [r1, _kernel_offset_to_current]
-
-	/* check if the current thread needs to be rescheduled */
-	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
-	breq r0, r2, _exc_return_from_irqoffload_trap
-#endif
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	/*
-	 * sync up the ERSEC_STAT.ERM and SEC_STAT.IRM.
-	 * use a fake interrupt return to simulate an exception turn.
-	 * ERM and IRM record which mode the cpu should return, 1: secure
-	 * 0: normal
-	 */
-	lr r3,[_ARC_V2_ERSEC_STAT]
-	btst r3, 31
-	bset.nz r3, r3, _ARC_V2_SEC_STAT_IRM_BIT
-	bclr.z r3, r3, _ARC_V2_SEC_STAT_IRM_BIT
-	sflag r3
-	/* save  _ARC_V2_SEC_STAT */
-	and r3, r3, 0xff
-	push_s r3
-#endif
-
-	_save_callee_saved_regs
-
-	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
-	/* note: Ok to use _CAUSE_RIRQ since everything is saved */
-
-	mov_s r2, r0
-#ifndef CONFIG_SMP
-	st_s r2, [r1, _kernel_offset_to_current]
-#endif
-	/* clear AE bit to forget this was an exception */
-	lr r3, [_ARC_V2_STATUS32]
-	and r3,r3,(~_ARC_V2_STATUS32_AE)
-	kflag r3
-	/* pretend lowest priority interrupt happened to use common handler */
-	lr r3, [_ARC_V2_AUX_IRQ_ACT]
-
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	or r3, r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
-#else
-	or r3, r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
-#endif
-
-#ifdef CONFIG_ARC_NORMAL_FIRMWARE
-	push_s r2
-	mov_s r0, _ARC_V2_AUX_IRQ_ACT
-	mov_s r1, r3
-	mov_s r6, ARC_S_CALL_AUX_WRITE
-	sjli SJLI_CALL_ARC_SECURE
-	pop_s r2
-#else
-	sr r3, [_ARC_V2_AUX_IRQ_ACT]
-#endif
-	/* Assumption: r2 has current thread */
-	b _rirq_common_interrupt_swap
-#endif
-
-_exc_return_from_irqoffload_trap:
 	_pop_irq_stack_frame
 	rtie
 #endif /* CONFIG_IRQ_OFFLOAD */

arch/arc/core/irq_offload.c

@@ -22,9 +22,7 @@ void z_irq_do_offload(void)
 
 void arch_irq_offload(irq_offload_routine_t routine, void *parameter)
 {
-	unsigned int key;
 
-	key = irq_lock();
 	offload_routine = routine;
 	offload_param = parameter;
 
@@ -32,6 +30,4 @@ void arch_irq_offload(irq_offload_routine_t routine, void *parameter)
 		:
 		: [id] "i"(_TRAP_S_SCALL_IRQ_OFFLOAD) : );
 
-	irq_unlock(key);
 }
-

arch/arc/core/isr_wrapper.S

@@ -246,18 +246,6 @@ rirq_path:
 
 #if defined(CONFIG_TRACING)
 GTEXT(sys_trace_isr_enter)
-
-.macro log_interrupt_k_event
-	clri r0 /* do not interrupt event logger operations */
-	push_s r0
-	push_s blink
-	jl sys_trace_isr_enter
-	pop_s blink
-	pop_s r0
-	seti r0
-.endm
-#else
-	#define log_interrupt_k_event
 #endif
 
 #if defined(CONFIG_SYS_POWER_MANAGEMENT)
@@ -303,7 +291,6 @@ SECTION_FUNC(TEXT, _isr_demux)
 	/* cannot be done before this point because we must be able to run C */
 	/* r0 is available to be stomped here, and exit_tickless_idle uses it */
 	exit_tickless_idle
-	log_interrupt_k_event
 
 	lr r0, [_ARC_V2_ICAUSE]
 	/* handle software triggered interrupt */

arch/arc/core/mpu/arc_mpu_v3_internal.h

@@ -656,7 +656,7 @@ int arc_core_mpu_get_max_domain_partition_regions(void)
 int arc_core_mpu_buffer_validate(void *addr, size_t size, int write)
 {
 	int r_index;
-
+	int key = arch_irq_lock();
 
 	/*
 	 * For ARC MPU v3, overlapping is not supported.
@@ -667,13 +667,17 @@ int arc_core_mpu_buffer_validate(void *addr, size_t size, int write)
 	/*  match and the area is in one region */
 	if (r_index >= 0 && r_index == _mpu_probe((u32_t)addr + (size - 1))) {
 		if (_is_user_accessible_region(r_index, write)) {
-			return 0;
+			r_index = 0;
 		} else {
-			return -EPERM;
+			r_index = -EPERM;
 		}
+	} else {
+		r_index = -EPERM;
 	}
 
-	return -EPERM;
+	arch_irq_unlock(key);
+
+	return r_index;
 }
 #endif /* CONFIG_USERSPACE */
 

arch/arc/core/regular_irq.S

@@ -266,8 +266,6 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	bl z_check_stack_sentinel
 #endif
 
-#ifdef CONFIG_PREEMPT_ENABLED
-
 #ifdef CONFIG_SMP
 	bl z_arc_smp_switch_in_isr
 	/* r0 points to new thread, r1 points to old thread */
@@ -303,6 +301,15 @@ _rirq_reschedule:
 	lr r3, [_ARC_V2_SEC_STAT]
 	push_s r3
 #endif
+
+#if defined(CONFIG_USERSPACE)
+/*
+ * need to remember the user/kernel status of interrupted thread
+ */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	and r3, r3, 0x80000000
+	push_s r3
+#endif
 	/* _save_callee_saved_regs expects outgoing thread in r2 */
 	_save_callee_saved_regs
 
@@ -395,11 +402,18 @@ _rirq_return_from_coop:
 	/* rtie will pop the rest from the stack */
 	rtie
 
-#endif /* CONFIG_PREEMPT_ENABLED */
-
 .balign 4
 _rirq_return_from_firq:
 _rirq_return_from_rirq:
+#if defined(CONFIG_USERSPACE)
+/*
+ * need to recover the user/kernel status of interrupted thread
+ */
+	pop_s r3
+	lr r2, [_ARC_V2_AUX_IRQ_ACT]
+	or r2, r2, r3
+	sr r2, [_ARC_V2_AUX_IRQ_ACT]
+#endif
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	/* here need to recover SEC_STAT.IRM bit */
 	pop_s r3

arch/arc/core/switch.S

@@ -162,6 +162,16 @@ return_loc:
 _switch_return_from_rirq:
 _switch_return_from_firq:
 
+#if defined(CONFIG_USERSPACE)
+/*
+ * need to recover the user/kernel status of interrupted thread
+ */
+	pop_s r3
+	lr r2, [_ARC_V2_AUX_IRQ_ACT]
+	or r2, r2, r3
+	sr r2, [_ARC_V2_AUX_IRQ_ACT]
+#endif
+
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	/* here need to recover SEC_STAT.IRM bit */
 	pop_s r3

arch/arc/core/vector_table.c

@@ -64,4 +64,3 @@ struct vector_table _VectorTable Z_GENERIC_SECTION(.exc_vector_table) = {
 	0,
 	0
 };
-

arch/arc/core/vector_table.ld

@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2019 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* when !XIP, .text is in RAM, and vector table must be at its very start */
+
+KEEP(*(.exc_vector_table))
+KEEP(*(".exc_vector_table.*"))
+KEEP(*(IRQ_VECTOR_TABLE))

arch/arm/CMakeLists.txt

@@ -1,26 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
-set(ARCH_FOR_cortex-m0        armv6s-m        )
-set(ARCH_FOR_cortex-m0plus    armv6s-m        )
-set(ARCH_FOR_cortex-m3        armv7-m         )
-set(ARCH_FOR_cortex-m4        armv7e-m        )
-set(ARCH_FOR_cortex-m23       armv8-m.base    )
-set(ARCH_FOR_cortex-m33       armv8-m.main+dsp)
-set(ARCH_FOR_cortex-m33+nodsp armv8-m.main    )
-set(ARCH_FOR_cortex-r4        armv7-r         )
-
-if(ARCH_FOR_${GCC_M_CPU})
-    set(ARCH_FLAG -march=${ARCH_FOR_${GCC_M_CPU}})
+if(CONFIG_ARM64)
+  include(aarch64.cmake)
+else()
+  include(aarch32.cmake)
 endif()
-
-zephyr_compile_options(
-  -mabi=aapcs
-  ${ARCH_FLAG}
-  )
-
-zephyr_ld_options(
-  -mabi=aapcs
-  ${ARCH_FLAG}
-  )
-
-add_subdirectory(core)

arch/arm/Kconfig

@@ -6,9 +6,14 @@
 menu "ARM Options"
 	depends on ARM
 
-source "arch/arm/core/Kconfig"
+rsource "core/aarch32/Kconfig"
+rsource "core/aarch64/Kconfig"
 
 config ARCH
 	default "arm"
 
+config ARM64
+	bool
+	select 64BIT
+
 endmenu

arch/arm/aarch32.cmake

@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(ARCH_FOR_cortex-m0        armv6s-m        )
+set(ARCH_FOR_cortex-m0plus    armv6s-m        )
+set(ARCH_FOR_cortex-m3        armv7-m         )
+set(ARCH_FOR_cortex-m4        armv7e-m        )
+set(ARCH_FOR_cortex-m23       armv8-m.base    )
+set(ARCH_FOR_cortex-m33       armv8-m.main+dsp)
+set(ARCH_FOR_cortex-m33+nodsp armv8-m.main    )
+set(ARCH_FOR_cortex-r4        armv7-r         )
+
+if(ARCH_FOR_${GCC_M_CPU})
+    set(ARCH_FLAG -march=${ARCH_FOR_${GCC_M_CPU}})
+endif()
+
+zephyr_compile_options(
+  -mabi=aapcs
+  ${ARCH_FLAG}
+  )
+
+zephyr_ld_options(
+  -mabi=aapcs
+  ${ARCH_FLAG}
+  )
+
+set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-little${ARCH}) # BFD format
+
+add_subdirectory(core/aarch32)

arch/arm/aarch64.cmake

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf64-littleaarch64) # BFD format
+
+add_subdirectory(core/aarch64)

arch/arm/core/aarch32/CMakeLists.txt

@@ -33,3 +33,5 @@ add_subdirectory_ifdef(CONFIG_ARM_SECURE_FIRMWARE cortex_m/tz)
 add_subdirectory_ifdef(CONFIG_ARM_NONSECURE_FIRMWARE cortex_m/tz)
 
 add_subdirectory_ifdef(CONFIG_CPU_CORTEX_R cortex_r)
+
+zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)

arch/arm/core/aarch32/Kconfig

@@ -3,6 +3,8 @@
 # Copyright (c) 2015 Wind River Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
+if !ARM64
+
 config CPU_CORTEX
 	bool
 	help
@@ -28,6 +30,7 @@ config CPU_CORTEX_M
 config CPU_CORTEX_R
 	bool
 	select CPU_CORTEX
+	select HAS_CMSIS_CORE
 	select HAS_FLASH_LOAD_OFFSET
 	help
 	  This option signifies the use of a CPU of the Cortex-R family.
@@ -246,9 +249,6 @@ config ARM_ENTRY_VENEERS_LIB_NAME
 
 endmenu
 
-menu "Architecture Floating Point Options"
-depends on CPU_HAS_FPU
-
 choice
 	prompt "Floating point ABI"
 	default FP_HARDABI
@@ -269,11 +269,11 @@ config FP_SOFTABI
 
 endchoice
 
-endmenu
+rsource "cortex_m/Kconfig"
+rsource "cortex_r/Kconfig"
 
-source "arch/arm/core/cortex_m/Kconfig"
-source "arch/arm/core/cortex_r/Kconfig"
+rsource "cortex_m/mpu/Kconfig"
 
-source "arch/arm/core/cortex_m/mpu/Kconfig"
+rsource "cortex_m/tz/Kconfig"
 
-source "arch/arm/core/cortex_m/tz/Kconfig"
+endif # !ARM64

arch/arm/core/aarch32/cortex_m/CMakeLists.txt

@@ -11,6 +11,12 @@ zephyr_library_sources(
   thread_abort.c
   )
 
+zephyr_linker_sources_ifdef(CONFIG_SW_VECTOR_RELAY
+  ROM_START
+  SORT_KEY 0x0relay_vectors
+  relay_vector_table.ld
+  )
+
 zephyr_linker_sources_ifdef(CONFIG_SW_VECTOR_RELAY
   RAM_SECTIONS
   vt_pointer_section.ld

arch/arm/core/aarch32/cortex_m/Kconfig

@@ -70,6 +70,17 @@ config CPU_CORTEX_M_HAS_SYSTICK
 	help
 	  This option is enabled when the CPU implements the SysTick timer.
 
+config CPU_CORTEX_M_HAS_DWT
+	bool
+	depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS
+	help
+	  This option signifies that the CPU implements the Data Watchpoint and
+	  Trace (DWT) unit specified by the ARMv7-M and above.
+
+	  While ARMv6-M does define a "DWT" unit, this is significantly different
+	  from the DWT specified by the ARMv7-M and above in terms of both feature
+	  set and register mappings.
+
 config CPU_CORTEX_M_HAS_BASEPRI
 	bool
 	depends on ARMV7_M_ARMV8_M_MAINLINE
@@ -243,6 +254,17 @@ config ZERO_LATENCY_IRQS
 	  higher priority than the rest of the kernel they cannot use any
 	  kernel functionality.
 
+config DYNAMIC_DIRECT_INTERRUPTS
+	bool "Enable support for dynamic direct interrupts"
+	depends on DYNAMIC_INTERRUPTS
+	help
+	  Direct interrupts are designed for performance-critical interrupt
+	  handling and do not go through all of the common interrupt handling
+	  code. This option enables the installation of interrupt service
+	  routines for direct interrupts at runtime.
+	  Note: this requires enabling support for dynamic interrupts in the
+	  kernel.
+
 config SW_VECTOR_RELAY
 	bool "Enable Software Vector Relay"
 	default y if BOOTLOADER_MCUBOOT

arch/arm/core/aarch32/cortex_m/cmse/arm_core_cmse.c

@@ -5,7 +5,7 @@
  */
 
 #include <zephyr.h>
-#include <cortex_m/cmse.h>
+#include <aarch32/cortex_m/cmse.h>
 
 int arm_cmse_mpu_region_get(u32_t addr)
 {

arch/arm/core/aarch32/cortex_m/irq_init.c

@@ -11,7 +11,7 @@
  */
 
 #include <arch/cpu.h>
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 
 /**
  *

arch/arm/core/aarch32/cortex_m/mpu/Kconfig

@@ -16,7 +16,7 @@ config ARM_MPU
 	  MCU implements Memory Protection Unit.
 
 	  Notes:
-	  The ARMv6-M and ARMv8-M MPU architecture requires a power-of-two
+	  The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
 	  alignment of MPU region base address and size.
 
 	  The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
@@ -60,10 +60,9 @@ config MPU_STACK_GUARD
 	help
 	  Enable Thread Stack Guards via MPU
 
-if MPU_STACK_GUARD
-
 config MPU_STACK_GUARD_MIN_SIZE_FLOAT
 	int
+	depends on MPU_STACK_GUARD
 	depends on FP_SHARING
 	default 128
 	help
@@ -75,8 +74,6 @@ config MPU_STACK_GUARD_MIN_SIZE_FLOAT
 	  is only stacked in sharing FP registers mode, therefore, the
 	  option is applicable only when FP_SHARING is selected.
 
-endif # MPU_STACK_GUARD
-
 config MPU_ALLOW_FLASH_WRITE
 	bool "Add MPU access to write to flash"
 	help
@@ -84,7 +81,6 @@ config MPU_ALLOW_FLASH_WRITE
 
 config CUSTOM_SECTION_ALIGN
 	bool "Custom Section Align"
-	depends on ARM_MPU
 	help
 	  MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT(ARMv7-M) sometimes cause memory
 	  wasting in linker scripts defined memory sections. Use this symbol

arch/arm/core/aarch32/cortex_m/mpu/arm_core_mpu_dev.h

@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_
-#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_
+#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_
 
 #include <zephyr/types.h>
 
@@ -268,4 +268,4 @@ int arm_core_mpu_buffer_validate(void *addr, size_t size, int write);
 }
 #endif
 
-#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_MPU_ARM_CORE_MPU_DEV_H_ */

arch/arm/core/aarch32/cortex_m/mpu/arm_mpu_v7_internal.h

@@ -5,10 +5,12 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_
-#define ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_
+#ifndef ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_
+#define ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_
 
 
+#include <sys/math_extras.h>
+
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
 #include <logging/log.h>
 
@@ -151,8 +153,16 @@ static inline u32_t mpu_region_get_size(u32_t index)
  */
 static inline int is_enabled_region(u32_t index)
 {
+	/* Lock IRQs to ensure RNR value is correct when reading RASR. */
+	unsigned int key;
+	u32_t rasr;
+
+	key = irq_lock();
 	MPU->RNR = index;
-	return (MPU->RASR & MPU_RASR_ENABLE_Msk) ? 1 : 0;
+	rasr = MPU->RASR;
+	irq_unlock(key);
+
+	return (rasr & MPU_RASR_ENABLE_Msk) ? 1 : 0;
 }
 
 /* Only a single bit is set for all user accessible permissions.
@@ -169,8 +179,16 @@ static inline int is_enabled_region(u32_t index)
  */
 static inline u32_t get_region_ap(u32_t r_index)
 {
+	/* Lock IRQs to ensure RNR value is correct when reading RASR. */
+	unsigned int key;
+	u32_t rasr;
+
+	key = irq_lock();
 	MPU->RNR = r_index;
-	return (MPU->RASR & MPU_RASR_AP_Msk) >> MPU_RASR_AP_Pos;
+	rasr = MPU->RASR;
+	irq_unlock(key);
+
+	return (rasr & MPU_RASR_AP_Msk) >> MPU_RASR_AP_Pos;
 }
 
 /**
@@ -184,14 +202,29 @@ static inline int is_in_region(u32_t r_index, u32_t start, u32_t size)
 	u32_t r_addr_start;
 	u32_t r_size_lshift;
 	u32_t r_addr_end;
+	u32_t end;
 
+	/* Lock IRQs to ensure RNR value is correct when reading RBAR, RASR. */
+	unsigned int key;
+	u32_t rbar, rasr;
+
+	key = irq_lock();
 	MPU->RNR = r_index;
-	r_addr_start = MPU->RBAR & MPU_RBAR_ADDR_Msk;
-	r_size_lshift = ((MPU->RASR & MPU_RASR_SIZE_Msk) >>
+	rbar = MPU->RBAR;
+	rasr = MPU->RASR;
+	irq_unlock(key);
+
+	r_addr_start = rbar & MPU_RBAR_ADDR_Msk;
+	r_size_lshift = ((rasr & MPU_RASR_SIZE_Msk) >>
 			MPU_RASR_SIZE_Pos) + 1;
 	r_addr_end = r_addr_start + (1UL << r_size_lshift) - 1;
 
-	if (start >= r_addr_start && (start + size - 1) <= r_addr_end) {
+	size = size == 0 ? 0 : size - 1;
+	if (u32_add_overflow(start, size, &end)) {
+		return 0;
+	}
+
+	if ((start >= r_addr_start) && (end <= r_addr_end)) {
 		return 1;
 	}
 
@@ -316,4 +349,4 @@ static int mpu_configure_dynamic_mpu_regions(const struct k_mem_partition
 	return mpu_reg_index;
 }
 
-#endif	/* ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_ */
+#endif	/* ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V7_INTERNAL_H_ */

arch/arm/core/aarch32/cortex_m/mpu/arm_mpu_v8_internal.h

@@ -5,10 +5,10 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_
-#define ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_
+#ifndef ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_
+#define ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_
 
-#include <cmse.h>
+#include <aarch32/cortex_m/cmse.h>
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
 #include <logging/log.h>
 
@@ -583,4 +583,4 @@ static int mpu_configure_dynamic_mpu_regions(const struct k_mem_partition
 	return mpu_reg_index;
 }
 
-#endif	/* ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_ */
+#endif	/* ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_ */

arch/arm/core/aarch32/cortex_m/mpu/nxp_mpu.c

@@ -10,6 +10,7 @@
 #include <soc.h>
 #include "arm_core_mpu_dev.h"
 #include <sys/__assert.h>
+#include <sys/math_extras.h>
 #include <linker/linker-defs.h>
 
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
@@ -428,11 +429,17 @@ static inline int is_in_region(u32_t r_index, u32_t start, u32_t size)
 {
 	u32_t r_addr_start;
 	u32_t r_addr_end;
+	u32_t end;
 
 	r_addr_start = SYSMPU->WORD[r_index][0];
 	r_addr_end = SYSMPU->WORD[r_index][1];
 
-	if (start >= r_addr_start && (start + size - 1) <= r_addr_end) {
+	size = size == 0 ? 0 : size - 1;
+	if (u32_add_overflow(start, size, &end)) {
+		return 0;
+	}
+
+	if ((start >= r_addr_start) && (end <= r_addr_end)) {
 		return 1;
 	}
 

arch/arm/core/aarch32/cortex_m/relay_vector_table.ld

@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2019 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+KEEP(*(.vector_relay_table))
+KEEP(*(".vector_relay_table.*"))
+KEEP(*(.vector_relay_handler))
+KEEP(*(".vector_relay_handler.*"))

arch/arm/core/aarch32/cortex_m/scb.c

@@ -17,7 +17,7 @@
 #include <kernel.h>
 #include <arch/cpu.h>
 #include <sys/util.h>
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 
 /**
  *

arch/arm/core/aarch32/cortex_m/tz/CMakeLists.txt

@@ -25,6 +25,8 @@ if(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)
     extra_post_build_byproducts
     ${CMAKE_BINARY_DIR}/${CONFIG_ARM_ENTRY_VENEERS_LIB_NAME}
     )
+
+  zephyr_linker_sources(SECTIONS SORT_KEY z_end secure_entry_functions.ld)
 endif()
 
 # Link the entry veneers library file with the Non-Secure Firmware that needs it.

arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c

@@ -4,9 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <arch/arm/cortex_m/cmsis.h>
-#include <cortex_m/tz.h>
-#include <cortex_m/exc.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
+#include <aarch32/cortex_m/tz.h>
+#include <aarch32/cortex_m/exc.h>
 
 static void configure_nonsecure_vtor_offset(u32_t vtor_ns)
 {

arch/arm/core/aarch32/cortex_m/tz/secure_entry_functions.ld

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0
+	#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)
+#elif defined(CONFIG_CPU_HAS_NRF_IDAU)
+	/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. */
+	#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))
+#else
+	#define NSC_ALIGN . = ALIGN(4)
+#endif
+
+#ifdef CONFIG_CPU_HAS_NRF_IDAU
+	#define NSC_ALIGN_END . = ALIGN(0x8000)
+#else
+	#define NSC_ALIGN_END . = ALIGN(4)
+#endif
+
+SECTION_PROLOGUE(.gnu.sgstubs,,)
+{
+	NSC_ALIGN;
+	__sg_start = .;
+	/* No input section necessary, since the Secure Entry Veneers are
+	   automatically placed after the .gnu.sgstubs output section. */
+} GROUP_LINK_IN(ROMABLE_REGION)
+__sg_end = .;
+__sg_size = __sg_end - __sg_start;
+NSC_ALIGN_END;
+__nsc_size = . - __sg_start;
+
+#ifdef CONFIG_CPU_HAS_NRF_IDAU
+	ASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))
+			 == (0x8000 - (__sg_start % 0x8000))
+		&& (0x8000 - (__sg_start % 0x8000)) >= 32
+		&& (0x8000 - (__sg_start % 0x8000)) <= 4096,
+		"The Non-Secure Callable region size must be a power of 2 \
+between 32 and 4096 bytes.")
+#endif

arch/arm/core/aarch32/cortex_m/vector_table.h

@@ -18,8 +18,8 @@
  * No other symbol has the same format, so they are easy to spot.
  */
 
-#ifndef ZEPHYR_ARCH_ARM_CORE_CORTEX_M_VECTOR_TABLE_H_
-#define ZEPHYR_ARCH_ARM_CORE_CORTEX_M_VECTOR_TABLE_H_
+#ifndef ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_VECTOR_TABLE_H_
+#define ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_VECTOR_TABLE_H_
 
 #ifdef _ASMLANGUAGE
 
@@ -67,4 +67,4 @@ extern void *_vector_table[];
 
 #endif /* _ASMLANGUAGE */
 
-#endif /* ZEPHYR_ARCH_ARM_CORE_CORTEX_M_VECTOR_TABLE_H_ */
+#endif /* ZEPHYR_ARCH_ARM_CORE_AARCH32_CORTEX_M_VECTOR_TABLE_H_ */

arch/arm/core/aarch32/cortex_r/Kconfig

@@ -75,8 +75,6 @@ config ARMV7_SYS_STACK_SIZE
 	help
 	  This option specifies the size of the stack used by the system mode.
 
-if CPU_CORTEX_R
-
 config RUNTIME_NMI
 	default y
 
@@ -87,5 +85,3 @@ config GEN_IRQ_VECTOR_TABLE
 	default n
 
 endif # CPU_CORTEX_R
-
-endif # CPU_CORTEX_R

arch/arm/core/aarch32/cortex_r/reboot.c

@@ -11,7 +11,7 @@
 
 #include <kernel.h>
 #include <arch/cpu.h>
-#include <misc/util.h>
+#include <sys/util.h>
 
 /**
  *

arch/arm/core/aarch32/cortex_r/reset.S

@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2013-2014 Wind River Systems, Inc.
+ * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Reset handler
+ *
+ * Reset handler that prepares the system for running C code.
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <arch/cpu.h>
+#include <offsets_short.h>
+#include "vector_table.h"
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(z_arm_reset)
+GDATA(_interrupt_stack)
+GDATA(z_arm_svc_stack)
+GDATA(z_arm_sys_stack)
+GDATA(z_arm_fiq_stack)
+GDATA(z_arm_abort_stack)
+GDATA(z_arm_undef_stack)
+#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
+GTEXT(z_platform_init)
+#endif
+
+/**
+ *
+ * @brief Reset vector
+ *
+ * Ran when the system comes out of reset. The processor is in Supervisor mode
+ * and interrupts are disabled. The processor architectural registers are in
+ * an indeterminate state.
+ *
+ * When these steps are completed, jump to z_arm_prep_c(), which will finish
+ * setting up the system for running C code.
+ *
+ * @return N/A
+ */
+SECTION_SUBSEC_FUNC(TEXT, _reset_section, z_arm_reset)
+SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)
+
+#if defined(CONFIG_CPU_HAS_DCLS)
+    /*
+     * Initialise CPU registers to a defined state if the processor is
+     * configured as Dual-redundant Core Lock-step (DCLS). This is required
+     * for state convergence of the two parallel executing cores.
+     */
+
+    /* Common and SVC mode registers */
+    mov r0,  #0
+    mov r1,  #0
+    mov r2,  #0
+    mov r3,  #0
+    mov r4,  #0
+    mov r5,  #0
+    mov r6,  #0
+    mov r7,  #0
+    mov r8,  #0
+    mov r9,  #0
+    mov r10, #0
+    mov r11, #0
+    mov r12, #0
+    mov r13, #0         /* r13_svc */
+    mov r14, #0         /* r14_svc */
+    mrs r0,  cpsr
+    msr spsr_cxsf, r0   /* spsr_svc */
+
+    /* FIQ mode registers */
+    cps #MODE_FIQ
+    mov r8,  #0         /* r8_fiq */
+    mov r9,  #0         /* r9_fiq */
+    mov r10, #0         /* r10_fiq */
+    mov r11, #0         /* r11_fiq */
+    mov r12, #0         /* r12_fiq */
+    mov r13, #0         /* r13_fiq */
+    mov r14, #0         /* r14_fiq */
+    mrs r0,  cpsr
+    msr spsr_cxsf, r0   /* spsr_fiq */
+
+    /* IRQ mode registers */
+    cps #MODE_IRQ
+    mov r13, #0         /* r13_irq */
+    mov r14, #0         /* r14_irq */
+    mrs r0,  cpsr
+    msr spsr_cxsf, r0   /* spsr_irq */
+
+    /* ABT mode registers */
+    cps #MODE_ABT
+    mov r13, #0         /* r13_abt */
+    mov r14, #0         /* r14_abt */
+    mrs r0,  cpsr
+    msr spsr_cxsf, r0   /* spsr_abt */
+
+    /* UND mode registers */
+    cps #MODE_UND
+    mov r13, #0         /* r13_und */
+    mov r14, #0         /* r14_und */
+    mrs r0,  cpsr
+    msr spsr_cxsf, r0   /* spsr_und */
+
+    /* SYS mode registers */
+    cps #MODE_SYS
+    mov r13, #0         /* r13_sys */
+    mov r14, #0         /* r14_sys */
+
+#if defined(CONFIG_FLOAT)
+    /*
+     * Initialise FPU registers to a defined state.
+     */
+
+    /* Allow VFP coprocessor access */
+    mrc p15, 0, r0, c1, c0, 2
+    orr r0, r0, #(CPACR_CP10(CPACR_FA) | CPACR_CP11(CPACR_FA))
+    mcr p15, 0, r0, c1, c0, 2
+
+    /* Enable VFP */
+    mov  r0, #FPEXC_EN
+    fmxr fpexc, r0
+
+    /* Initialise VFP registers */
+    fmdrr d0,  r1, r1
+    fmdrr d1,  r1, r1
+    fmdrr d2,  r1, r1
+    fmdrr d3,  r1, r1
+    fmdrr d4,  r1, r1
+    fmdrr d5,  r1, r1
+    fmdrr d6,  r1, r1
+    fmdrr d7,  r1, r1
+    fmdrr d8,  r1, r1
+    fmdrr d9,  r1, r1
+    fmdrr d10, r1, r1
+    fmdrr d11, r1, r1
+    fmdrr d12, r1, r1
+    fmdrr d13, r1, r1
+    fmdrr d14, r1, r1
+    fmdrr d15, r1, r1
+#endif /* CONFIG_FLOAT */
+
+#endif /* CONFIG_CPU_HAS_DCLS */
+
+    /*
+     * Configure stack.
+     */
+
+    /* FIQ mode stack */
+    msr CPSR_c, #(MODE_FIQ | I_BIT | F_BIT)
+    ldr sp, =(z_arm_fiq_stack + CONFIG_ARMV7_FIQ_STACK_SIZE)
+
+    /* IRQ mode stack */
+    msr CPSR_c, #(MODE_IRQ | I_BIT | F_BIT)
+    ldr sp, =(_interrupt_stack + CONFIG_ISR_STACK_SIZE)
+
+    /* ABT mode stack */
+    msr CPSR_c, #(MODE_ABT | I_BIT | F_BIT)
+    ldr sp, =(z_arm_abort_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE)
+
+    /* UND mode stack */
+    msr CPSR_c, #(MODE_UND | I_BIT | F_BIT)
+    ldr sp, =(z_arm_undef_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE)
+
+    /* SVC mode stack */
+    msr CPSR_c, #(MODE_SVC | I_BIT | F_BIT)
+    ldr sp, =(z_arm_svc_stack + CONFIG_ARMV7_SVC_STACK_SIZE)
+
+    /* SYS mode stack */
+    msr CPSR_c, #(MODE_SYS | I_BIT | F_BIT)
+    ldr sp, =(z_arm_sys_stack + CONFIG_ARMV7_SYS_STACK_SIZE)
+
+#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
+    /* Execute platform-specific initialisation if applicable */
+    bl z_platform_init
+#endif
+
+#if defined(CONFIG_WDOG_INIT)
+    /* board-specific watchdog initialization is necessary */
+    bl z_arm_watchdog_init
+#endif
+
+    b z_arm_prep_c

arch/arm/core/aarch32/cortex_r/stacks.c

@@ -5,7 +5,7 @@
  */
 
 #include <kernel.h>
-#include <cortex_r/stack.h>
+#include <aarch32/cortex_r/stack.h>
 #include <string.h>
 
 K_THREAD_STACK_DEFINE(z_arm_fiq_stack,   CONFIG_ARMV7_FIQ_STACK_SIZE);

arch/arm/core/aarch32/cortex_r/vector_table.h

@@ -26,7 +26,7 @@
 
 #include <toolchain.h>
 #include <linker/sections.h>
-#include <misc/util.h>
+#include <sys/util.h>
 
 GTEXT(__start)
 GTEXT(_vector_table)

arch/arm/core/aarch32/irq_manage.c

@@ -17,7 +17,7 @@
 #include <kernel.h>
 #include <arch/cpu.h>
 #if defined(CONFIG_CPU_CORTEX_M)
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 #elif defined(CONFIG_CPU_CORTEX_R)
 #include <device.h>
 #include <irq_nextlevel.h>
@@ -27,7 +27,7 @@
 #include <linker/sections.h>
 #include <sw_isr_table.h>
 #include <irq.h>
-#include <debug/tracing.h>
+#include <tracing/tracing.h>
 
 extern void z_arm_reserved(void);
 
@@ -171,7 +171,7 @@ void _arch_isr_direct_pm(void)
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	/* Lock all interrupts. irq_lock() will on this CPU only disable those
 	 * lower than BASEPRI, which is not what we want. See comments in
-	 * arch/arm/core/isr_wrapper.S
+	 * arch/arm/core/aarch32/isr_wrapper.S
 	 */
 	__asm__ volatile("cpsid i" : : : "memory");
 #else
@@ -262,4 +262,33 @@ int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
 	z_arm_irq_priority_set(irq, priority, flags);
 	return irq;
 }
+
+#ifdef CONFIG_DYNAMIC_DIRECT_INTERRUPTS
+static inline void z_arm_irq_dynamic_direct_isr_dispatch(void)
+{
+	u32_t irq = __get_IPSR() - 16;
+
+	if (irq < IRQ_TABLE_SIZE) {
+		struct _isr_table_entry *isr_entry = &_sw_isr_table[irq];
+
+		isr_entry->isr(isr_entry->arg);
+	}
+}
+
+ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_reschedule)
+{
+	z_arm_irq_dynamic_direct_isr_dispatch();
+
+	return 1;
+}
+
+ISR_DIRECT_DECLARE(z_arm_irq_direct_dynamic_dispatch_no_reschedule)
+{
+	z_arm_irq_dynamic_direct_isr_dispatch();
+
+	return 0;
+}
+
+#endif /* CONFIG_DYNAMIC_DIRECT_INTERRUPTS */
+
 #endif /* CONFIG_DYNAMIC_INTERRUPTS */

arch/arm/core/aarch32/isr_wrapper.S

@@ -64,7 +64,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
 	bl read_timer_start_of_isr
 #endif
 
-#ifdef CONFIG_TRACING
+#ifdef CONFIG_TRACING_ISR
 	bl sys_trace_isr_enter
 #endif
 
@@ -77,7 +77,15 @@ SECTION_FUNC(TEXT, _isr_wrapper)
 	 * state is not interrupted.  In each case, z_sys_power_save_idle_exit
 	 * is called with interrupts disabled.
 	 */
+
+     /*
+      * FIXME: Remove the Cortex-M conditional compilation checks for `cpsid i`
+      *        and `cpsie i` after the Cortex-R port is updated to support
+      *        interrupt nesting.  For more details, refer to the issue #21758.
+      */
+#if defined(CONFIG_CPU_CORTEX_M)
 	cpsid i  /* PRIMASK = 1 */
+#endif
 
 	/* is this a wakeup from idle ? */
 	ldr r2, =_kernel
@@ -110,9 +118,12 @@ _idle_state_cleared:
 #error Unknown ARM architecture
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 
+#if defined(CONFIG_CPU_CORTEX_M)
 	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
 #endif
 
+#endif /* CONFIG_SYS_POWER_MANAGEMENT */
+
 #if defined(CONFIG_CPU_CORTEX_M)
 	mrs r0, IPSR	/* get exception number */
 #endif
@@ -151,7 +162,7 @@ _idle_state_cleared:
 #endif /* CONFIG_EXECUTION_BENCHMARKING */
 	blx r3		/* call ISR */
 
-#ifdef CONFIG_TRACING
+#ifdef CONFIG_TRACING_ISR
 	bl sys_trace_isr_exit
 #endif
 

arch/arm/core/aarch32/prep_c.c

@@ -21,7 +21,7 @@
 #include <linker/linker-defs.h>
 
 #if defined(CONFIG_ARMV7_R)
-#include <cortex_r/stack.h>
+#include <aarch32/cortex_r/stack.h>
 #endif
 
 #if defined(__GNUC__)
@@ -76,11 +76,18 @@ void __weak relocate_vector_table(void)
 
 #endif /* CONFIG_CPU_CORTEX_M_HAS_VTOR */
 
-#ifdef CONFIG_FLOAT
-static inline void enable_floating_point(void)
+#if defined(CONFIG_CPU_HAS_FPU)
+static inline void z_arm_floating_point_init(void)
 {
 	/*
-	 * Upon reset, the Co-Processor Access Control Register is 0x00000000.
+	 * Upon reset, the Co-Processor Access Control Register is, normally,
+	 * 0x00000000. However, it might be left un-cleared by firmware running
+	 * before Zephyr boot.
+	 */
+	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
+
+#if defined(CONFIG_FLOAT)
+	/*
 	 * Enable CP10 and CP11 Co-Processors to enable access to floating
 	 * point registers.
 	 */
@@ -135,12 +142,23 @@ static inline void enable_floating_point(void)
 	 * will be activated (FPCA bit on the CONTROL register) in the presence
 	 * of floating point instructions.
 	 */
-}
-#else
-static inline void enable_floating_point(void)
-{
-}
+
+#endif /* CONFIG_FLOAT */
+
+	/*
+	 * Upon reset, the CONTROL.FPCA bit is, normally, cleared. However,
+	 * it might be left un-cleared by firmware running before Zephyr boot.
+	 * We must clear this bit to prevent errors in exception unstacking.
+	 *
+	 * Note:
+	 * In Sharing FP Registers mode CONTROL.FPCA is cleared before switching
+	 * to main, so it may be skipped here (saving few boot cycles).
+	 */
+#if !defined(CONFIG_FLOAT) || !defined(CONFIG_FP_SHARING)
+	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
 #endif
+}
+#endif /* CONFIG_CPU_HAS_FPU */
 
 extern FUNC_NORETURN void z_cstart(void);
 /**
@@ -154,7 +172,9 @@ extern FUNC_NORETURN void z_cstart(void);
 void z_arm_prep_c(void)
 {
 	relocate_vector_table();
-	enable_floating_point();
+#if defined(CONFIG_CPU_HAS_FPU)
+	z_arm_floating_point_init();
+#endif
 	z_bss_zero();
 	z_data_copy();
 #if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)

arch/arm/core/aarch32/swap_helper.S

@@ -198,7 +198,7 @@ out_fp_endif:
     cpsie i
 _thread_irq_disabled:
 
-#if defined(CONFIG_ARM_MPU)
+#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
     /* Re-program dynamic memory map */
     push {r2,lr}
     mov r0, r2
@@ -278,7 +278,7 @@ in_fp_endif:
     isb
 #endif
 
-#if defined (CONFIG_ARM_MPU)
+#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
     /* Re-program dynamic memory map */
     push {r2,lr}
     mov r0, r2 /* _current thread */
@@ -322,12 +322,6 @@ _thread_irq_disabled:
 #error Unknown ARM architecture
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 
-#ifdef CONFIG_BUILTIN_STACK_GUARD
-    /* clear stack pointer limit before setting the PSP */
-    mov r0, #0
-    msr PSPLIM, r0
-#endif /* CONFIG_BUILTIN_STACK_GUARD */
-
 #if defined(CONFIG_CPU_CORTEX_M)
     msr PSP, ip
 #endif
@@ -514,7 +508,10 @@ _do_syscall:
     ldr ip, =K_SYSCALL_LIMIT
     cmp r6, ip
 #endif
-    blt valid_syscall_id
+    /* The supplied syscall_id must be lower than the limit
+     * (Requires unsigned integer comparison)
+     */
+    blo valid_syscall_id
 
     /* bad syscall id.  Set arg1 to bad id and set call_id to SYSCALL_BAD */
     str r6, [r0]
@@ -555,6 +552,16 @@ valid_syscall_id:
      */
     isb
 
+#if defined(CONFIG_BUILTIN_STACK_GUARD)
+    /* Thread is now in privileged mode; after returning from SCVall it
+     * will use the default (user) stack before switching to the privileged
+     * stack to execute the system call. We need to protect the user stack
+     * against stack overflows until this stack transition.
+     */
+    ldr r1, [r0, #_thread_offset_to_stack_info_start]    /* stack_info.start */
+    msr PSPLIM, r1
+#endif /* CONFIG_BUILTIN_STACK_GUARD */
+
     /* return from SVC to the modified LR - z_arm_do_syscall */
     bx lr
 #endif /* CONFIG_USERSPACE */

arch/arm/core/aarch32/thread.c

@@ -170,11 +170,11 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
 	 * buffer area accordingly.
 	 */
 #if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
-	 _current->arch.priv_stack_start +=
+	_current->arch.priv_stack_start +=
 		(_current->base.user_options & K_FP_REGS) ?
 		MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE;
 #else
-	 _current->arch.priv_stack_start += MPU_GUARD_ALIGN_AND_SIZE;
+	_current->arch.priv_stack_start += MPU_GUARD_ALIGN_AND_SIZE;
 #endif /* CONFIG_FLOAT && CONFIG_FP_SHARING */
 #endif /* CONFIG_MPU_STACK_GUARD */
 
@@ -205,11 +205,20 @@ void configure_builtin_stack_guard(struct k_thread *thread)
 		 * User threads executing in user mode do not require a stack
 		 * limit protection.
 		 */
+		__set_PSPLIM(0);
 		return;
 	}
-	u32_t guard_start = thread->arch.priv_stack_start ?
-			    (u32_t)thread->arch.priv_stack_start :
-			    (u32_t)thread->stack_obj;
+	/* Only configure PSPLIM to guard the privileged stack area, if
+	 * the thread is currently using it, otherwise guard the default
+	 * thread stack. Note that the conditional check relies on the
+	 * thread privileged stack being allocated in higher memory area
+	 * than the default thread stack (ensured by design).
+	 */
+	u32_t guard_start =
+		((thread->arch.priv_stack_start) &&
+			(__get_PSP() >= thread->arch.priv_stack_start)) ?
+		(u32_t)thread->arch.priv_stack_start :
+		(u32_t)thread->stack_obj;
 
 	__ASSERT(thread->stack_info.start == ((u32_t)thread->stack_obj),
 		"stack_info.start does not point to the start of the"
@@ -404,7 +413,7 @@ void arch_switch_to_main_thread(struct k_thread *main_thread,
 
 	/* the ready queue cache already contains the main thread */
 
-#ifdef CONFIG_ARM_MPU
+#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
 	/*
 	 * If stack protection is enabled, make sure to set it
 	 * before jumping to thread entry function

arch/arm/core/aarch32/userspace.S

@@ -12,6 +12,8 @@
 #include <offsets_short.h>
 #include <syscall.h>
 
+#include <arch/arm/aarch32/exc.h>
+
 _ASM_FILE_PROLOGUE
 
 GTEXT(z_arm_userspace_enter)
@@ -41,12 +43,6 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter)
     /* move user_entry to lr */
     mov lr, r0
 
-#if defined(CONFIG_BUILTIN_STACK_GUARD)
-    /* clear stack pointer limit before setting the PSP */
-    mov r0, #0
-    msr PSPLIM, r0
-#endif
-
     /* prepare to set stack to privileged stack */
     ldr r0, =_kernel
     ldr r0, [r0, #_kernel_offset_to_current]
@@ -71,10 +67,23 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter)
      */
     mov ip, sp
 
-    /* set stack to privileged stack */
+    /* set stack to privileged stack
+     *
+     * Note [applies only when CONFIG_BUILTIN_STACK_GUARD is enabled]:
+     * modifying PSP via MSR instruction is not subject to stack limit
+     * checking, so we do not need to clear PSPLIM before setting PSP.
+     * The operation is safe since, by design, the privileged stack is
+     * located in memory higher than the default (user) thread stack.
+     */
     msr PSP, r0
 
 #if defined(CONFIG_BUILTIN_STACK_GUARD)
+    /* At this point the privileged stack is not yet protected by PSPLIM.
+     * Since we have just switched to the top of the privileged stack, we
+     * are safe, as long as the stack can accommodate the maximum exception
+     * stack frame.
+     */
+
     /* set stack pointer limit to the start of the priv stack */
     ldr r0, =_kernel
     ldr r0, [r0, #_kernel_offset_to_current]
@@ -148,12 +157,6 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter)
     /* r0 contains user stack start, ip contains user stack size */
     add r0, r0, ip   /* calculate top of stack */
 
-#if defined(CONFIG_BUILTIN_STACK_GUARD)
-    /* clear stack limit (stack protection not required in user mode) */
-    mov r3, #0
-    msr PSPLIM, r3
-#endif
-
     /* pop remaining arguments from stack before switching stacks */
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
     /* Use r4 to pop lr, then restore r4 */
@@ -165,9 +168,51 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter)
     pop {r1,r2,r3,lr}
 #endif
 
+#if defined(CONFIG_BUILTIN_STACK_GUARD)
+    /*
+     * Guard the default (user) stack until thread drops privileges.
+     *
+     * Notes:
+     * PSPLIM is configured *before* PSP switches to the default (user) stack.
+     * This is safe, since the user stack is located, by design, in a lower
+     * memory area compared to the privileged stack.
+     *
+     * However, we need to prevent a context-switch to occur, because that
+     * would re-configure PSPLIM to guard the privileged stack; we enforce
+     * a PendSV locking for this purporse.
+     *
+     * Between PSPLIM update and PSP switch, the privileged stack will be
+     * left un-guarded; this is safe, as long as the privileged stack is
+     * large enough to accommodate a maximum exception stack frame.
+     */
+
+    /* Temporarily store current IRQ locking status in ip */
+    mrs ip, BASEPRI
+    push {r0, ip}
+
+    /* Lock PendSV while reprogramming PSP and PSPLIM */
+    mov r0, #_EXC_PENDSV_PRIO_MASK
+    msr BASEPRI, r0
+    isb
+
+    /* Set PSPLIM to guard the thread's user stack. */
+    ldr r0, =_kernel
+    ldr r0, [r0, #_kernel_offset_to_current]
+    ldr r0, [r0, #_thread_offset_to_stack_info_start]
+    msr PSPLIM, r0
+
+    pop {r0, ip}
+#endif
+
     /* set stack to user stack */
     msr PSP, r0
 
+#if defined(CONFIG_BUILTIN_STACK_GUARD)
+    /* Restore interrupt lock status */
+    msr BASEPRI, ip
+    isb
+#endif
+
     /* restore r0 */
     mov r0, lr
 
@@ -250,21 +295,19 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter)
  */
 SECTION_FUNC(TEXT, z_arm_do_syscall)
 
-    /* The function is executing in privileged mode. This implies that we
+    /* Note [when using MPU-based stack guarding]:
+     * The function is executing in privileged mode. This implies that we
      * shall not be allowed to use the thread's default unprivileged stack,
      * (i.e push to or pop from it), to avoid a possible stack corruption.
      *
-     * Rationale: since we execute in PRIV mode and no MPU guard or PSPLIM
-     * register is guarding the end of the default stack, we won't be able
+     * Rationale: since we execute in PRIV mode and no MPU guard
+     * is guarding the end of the default stack, we won't be able
      * to detect any stack overflows.
+     *
+     * Note [when using built-in stack limit checking on ARMv8-M]:
+     * At this point PSPLIM is already configured to guard the default (user)
+     * stack, so pushing to the default thread's stack is safe.
      */
-
-#if defined(CONFIG_BUILTIN_STACK_GUARD)
-    /* clear stack pointer limit before setting the PSP */
-    mov ip, #0
-    msr PSPLIM, ip
-#endif
-
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
     /* save current stack pointer (user stack) */
     mov ip, sp
@@ -289,6 +332,7 @@ SECTION_FUNC(TEXT, z_arm_do_syscall)
     pop {r0, r1}
 
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+
     /* setup privileged stack */
     ldr ip, =_kernel
     ldr ip, [ip, #_kernel_offset_to_current]
@@ -304,6 +348,14 @@ SECTION_FUNC(TEXT, z_arm_do_syscall)
     /* switch to privileged stack */
     msr PSP, ip
 
+    /* Note (applies when using stack limit checking):
+     * We do not need to lock IRQs after switching PSP to the privileged stack;
+     * PSPLIM is guarding the default (user) stack, which, by design, is
+     * located at *lower* memory area. Since we switch to the top of the
+     * privileged stack we are safe, as long as the stack can accommodate
+     * the maximum exception stack frame.
+     */
+
 #if defined(CONFIG_BUILTIN_STACK_GUARD)
     /* Set stack pointer limit (needed in privileged mode) */
     ldr ip, =_kernel
@@ -391,9 +443,37 @@ dispatch_syscall:
     ldr lr, [sp,#12]
 #endif
 
+
 #if defined(CONFIG_BUILTIN_STACK_GUARD)
-    /* clear stack limit (stack protection not required in user mode) */
-    mov r3, #0
+    /*
+     * Guard the default (user) stack until thread drops privileges.
+     *
+     * Notes:
+     * PSPLIM is configured *before* PSP switches to the default (user) stack.
+     * This is safe, since the user stack is located, by design, in a lower
+     * memory area compared to the privileged stack.
+     *
+     * However, we need to prevent a context-switch to occur, because that
+     * would re-configure PSPLIM to guard the privileged stack; we enforce
+     * a PendSV locking for this purporse.
+     *
+     * Between PSPLIM update and PSP switch, the privileged stack will be
+     * left un-guarded; this is safe, as long as the privileged stack is
+     * large enough to accommodate a maximum exception stack frame.
+     */
+
+    /* Temporarily store current IRQ locking status in r2 */
+    mrs r2, BASEPRI
+
+    /* Lock PendSV while reprogramming PSP and PSPLIM */
+    mov r3, #_EXC_PENDSV_PRIO_MASK
+    msr BASEPRI, r3
+    isb
+
+    /* Set PSPLIM to guard the thread's user stack. */
+    ldr r3, =_kernel
+    ldr r3, [r3, #_kernel_offset_to_current]
+    ldr r3, [r3, #_thread_offset_to_stack_info_start]    /* stack_info.start */
     msr PSPLIM, r3
 #endif
 
@@ -412,6 +492,12 @@ dispatch_syscall:
     msr PSP, ip
 #endif
 
+#if defined(CONFIG_BUILTIN_STACK_GUARD)
+    /* Restore interrupt lock status */
+    msr BASEPRI, r2
+    isb
+#endif
+
     push {r0, r1}
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
     push {r2, r3}
@@ -546,4 +632,3 @@ z_arm_user_string_nlen_fixup:
 
     add	sp, #12
     pop	{r4, r5, pc}
-

arch/arm/core/aarch32/vector_table.ld

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2019 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+_vector_start = .;
+KEEP(*(.exc_vector_table))
+KEEP(*(".exc_vector_table.*"))
+
+KEEP(*(IRQ_VECTOR_TABLE))
+
+KEEP(*(.vectors))
+
+_vector_end = .;
+
+KEEP(*(.openocd_dbg))
+KEEP(*(".openocd_dbg.*"))

arch/arm/core/aarch64/CMakeLists.txt

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+if (CONFIG_COVERAGE)
+  toolchain_cc_coverage()
+endif ()
+
+zephyr_library_sources(
+  cpu_idle.S
+  fatal.c
+  irq_manage.c
+  prep_c.c
+  reset.S
+  swap.c
+  swap_helper.S
+  thread.c
+  vector_table.S
+)
+
+zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
+zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
+zephyr_library_sources_ifdef(CONFIG_ARM_MMU arm_mmu.c)

arch/arm/core/aarch64/Kconfig

@@ -0,0 +1,174 @@
+# ARM64 core configuration options
+
+# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if ARM64
+
+config CPU_CORTEX
+	bool
+	help
+	  This option signifies the use of a CPU of the Cortex family.
+
+config CPU_CORTEX_A
+	bool
+	select CPU_CORTEX
+	select HAS_FLASH_LOAD_OFFSET
+	help
+	  This option signifies the use of a CPU of the Cortex-A family.
+
+config CPU_CORTEX_A53
+	bool
+	select CPU_CORTEX_A
+	select ARMV8_A
+	help
+	  This option signifies the use of a Cortex-A53 CPU
+
+config SWITCH_TO_EL1
+	bool "Switch to EL1 at boot"
+	default y
+	help
+	  This option indicates that we want to switch to EL1 at boot. Only
+	  switching to EL1 from EL3 is supported.
+
+config NUM_IRQS
+	int
+
+config MAIN_STACK_SIZE
+	default 4096
+
+config IDLE_STACK_SIZE
+	default 4096
+
+config ISR_STACK_SIZE
+	default 4096
+
+config TEST_EXTRA_STACKSIZE
+	default 2048
+
+config SYSTEM_WORKQUEUE_STACK_SIZE
+	default 4096
+
+config OFFLOAD_WORKQUEUE_STACK_SIZE
+	default 4096
+
+config CMSIS_THREAD_MAX_STACK_SIZE
+	default 4096
+
+config CMSIS_V2_THREAD_MAX_STACK_SIZE
+	default 4096
+
+config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE
+	default 4096
+
+config IPM_CONSOLE_STACK_SIZE
+	default 2048
+
+if CPU_CORTEX_A
+
+config ARMV8_A
+	bool
+	select ATOMIC_OPERATIONS_BUILTIN
+	help
+	  This option signifies the use of an ARMv8-A processor
+	  implementation.
+
+	  From https://developer.arm.com/products/architecture/cpu-architecture/a-profile:
+	  The Armv8-A architecture introduces the ability to use 64-bit and
+	  32-bit Execution states, known as AArch64 and AArch32 respectively.
+	  The AArch64 Execution state supports the A64 instruction set, holds
+	  addresses in 64-bit registers and allows instructions in the base
+	  instruction set to use 64-bit registers for their processing. The AArch32
+	  Execution state is a 32-bit Execution state that preserves backwards
+	  compatibility with the Armv7-A architecture and enhances that profile
+	  so that it can support some features included in the AArch64 state.
+	  It supports the T32 and A32 instruction sets.
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+config ARM_MMU
+	bool "ARM MMU Support"
+	default y
+	help
+	  Memory Management Unit support.
+
+if ARM_MMU
+
+config MAX_XLAT_TABLES
+	int "Maximum numbers of translation tables"
+	default 7
+	help
+	  This option specifies the maximum numbers of translation tables
+	  excluding the base translation table. Based on this, translation
+	  tables are allocated at compile time and used at runtime as needed.
+	  If the runtime need exceeds preallocated numbers of translation
+	  tables, it will result in assert. Number of translation tables
+	  required is decided based on how many discrete memory regions
+	  (both normal and device memory) are present on given platform and
+	  how much granularity is required while assigning attributes
+	  to these memory regions.
+
+choice
+	prompt "Virtual address space size"
+	default ARM64_VA_BITS_32
+	help
+	  Allows choosing one of multiple possible virtual address
+	  space sizes. The level of translation table is determined by
+	  a combination of page size and virtual address space size.
+
+config ARM64_VA_BITS_32
+	bool "32-bit"
+
+config ARM64_VA_BITS_36
+	bool "36-bit"
+
+config ARM64_VA_BITS_42
+	bool "42-bit"
+
+config ARM64_VA_BITS_48
+	bool "48-bit"
+endchoice
+
+config ARM64_VA_BITS
+	int
+	default 32 if ARM64_VA_BITS_32
+	default 36 if ARM64_VA_BITS_36
+	default 42 if ARM64_VA_BITS_42
+	default 48 if ARM64_VA_BITS_48
+
+choice
+	prompt "Physical address space size"
+	default ARM64_PA_BITS_32
+	help
+	  Choose the maximum physical address range that the kernel will
+	  support.
+
+config ARM64_PA_BITS_32
+	bool "32-bit"
+
+config ARM64_PA_BITS_36
+	bool "36-bit"
+
+config ARM64_PA_BITS_42
+	bool "42-bit"
+
+config ARM64_PA_BITS_48
+	bool "48-bit"
+endchoice
+
+config ARM64_PA_BITS
+	int
+	default 32 if ARM64_PA_BITS_32
+	default 36 if ARM64_PA_BITS_36
+	default 42 if ARM64_PA_BITS_42
+	default 48 if ARM64_PA_BITS_48
+
+endif #ARM_MMU
+
+endif # CPU_CORTEX_A
+
+endif # ARM64

arch/arm/core/aarch64/arm_mmu.c

@@ -0,0 +1,470 @@
+/*
+ * Copyright 2019 Broadcom
+ * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+#include <kernel.h>
+#include <arch/arm/aarch64/cpu.h>
+#include <arch/arm/aarch64/arm_mmu.h>
+#include <linker/linker-defs.h>
+#include <sys/util.h>
+
+/* Set below flag to get debug prints */
+#define MMU_DEBUG_PRINTS	0
+/* To get prints from MMU driver, it has to initialized after console driver */
+#define MMU_DEBUG_PRIORITY	70
+
+#if MMU_DEBUG_PRINTS
+/* To dump page table entries while filling them, set DUMP_PTE macro */
+#define DUMP_PTE		0
+#define MMU_DEBUG(fmt, ...)	printk(fmt, ##__VA_ARGS__)
+#else
+#define MMU_DEBUG(...)
+#endif
+
+/* We support only 4kB translation granule */
+#define PAGE_SIZE_SHIFT		12U
+#define PAGE_SIZE		(1U << PAGE_SIZE_SHIFT)
+#define XLAT_TABLE_SIZE_SHIFT   PAGE_SIZE_SHIFT /* Size of one complete table */
+#define XLAT_TABLE_SIZE		(1U << XLAT_TABLE_SIZE_SHIFT)
+
+#define XLAT_TABLE_ENTRY_SIZE_SHIFT	3U /* Each table entry is 8 bytes */
+#define XLAT_TABLE_LEVEL_MAX	3U
+
+#define XLAT_TABLE_ENTRIES_SHIFT \
+			(XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT)
+#define XLAT_TABLE_ENTRIES	(1U << XLAT_TABLE_ENTRIES_SHIFT)
+
+/* Address size covered by each entry at given translation table level */
+#define L3_XLAT_VA_SIZE_SHIFT	PAGE_SIZE_SHIFT
+#define L2_XLAT_VA_SIZE_SHIFT	\
+			(L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L1_XLAT_VA_SIZE_SHIFT	\
+			(L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L0_XLAT_VA_SIZE_SHIFT	\
+			(L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+
+#define LEVEL_TO_VA_SIZE_SHIFT(level) \
+				(PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \
+				(XLAT_TABLE_LEVEL_MAX - (level))))
+
+/* Virtual Address Index within given translation table level */
+#define XLAT_TABLE_VA_IDX(va_addr, level) \
+	((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1))
+
+/*
+ * Calculate the initial translation table level from CONFIG_ARM64_VA_BITS
+ * For a 4 KB page size,
+ * (va_bits <= 21)	 - base level 3
+ * (22 <= va_bits <= 30) - base level 2
+ * (31 <= va_bits <= 39) - base level 1
+ * (40 <= va_bits <= 48) - base level 0
+ */
+#define GET_XLAT_TABLE_BASE_LEVEL(va_bits)	\
+	((va_bits > L0_XLAT_VA_SIZE_SHIFT)	\
+	? 0U					\
+	: (va_bits > L1_XLAT_VA_SIZE_SHIFT)	\
+	? 1U					\
+	: (va_bits > L2_XLAT_VA_SIZE_SHIFT)	\
+	? 2U : 3U)
+
+#define XLAT_TABLE_BASE_LEVEL	GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS)
+
+#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits)	\
+	(1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL)))
+
+#define NUM_BASE_LEVEL_ENTRIES	GET_NUM_BASE_LEVEL_ENTRIES(CONFIG_ARM64_VA_BITS)
+
+#if DUMP_PTE
+#define L0_SPACE ""
+#define L1_SPACE "  "
+#define L2_SPACE "    "
+#define L3_SPACE "      "
+#define XLAT_TABLE_LEVEL_SPACE(level)		\
+	(((level) == 0) ? L0_SPACE :		\
+	((level) == 1) ? L1_SPACE :		\
+	((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+static u64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES]
+		__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(u64_t));
+
+static u64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
+		__aligned(XLAT_TABLE_ENTRIES * sizeof(u64_t));
+
+/* Translation table control register settings */
+static u64_t get_tcr(int el)
+{
+	u64_t tcr;
+	u64_t pa_bits = CONFIG_ARM64_PA_BITS;
+	u64_t va_bits = CONFIG_ARM64_VA_BITS;
+	u64_t tcr_ps_bits;
+
+	switch (pa_bits) {
+	case 48:
+		tcr_ps_bits = TCR_PS_BITS_256TB;
+		break;
+	case 44:
+		tcr_ps_bits = TCR_PS_BITS_16TB;
+		break;
+	case 42:
+		tcr_ps_bits = TCR_PS_BITS_4TB;
+		break;
+	case 40:
+		tcr_ps_bits = TCR_PS_BITS_1TB;
+		break;
+	case 36:
+		tcr_ps_bits = TCR_PS_BITS_64GB;
+		break;
+	default:
+		tcr_ps_bits = TCR_PS_BITS_4GB;
+		break;
+	}
+
+	if (el == 1) {
+		tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
+		/*
+		 * TCR_EL1.EPD1: Disable translation table walk for addresses
+		 * that are translated using TTBR1_EL1.
+		 */
+		tcr |= TCR_EPD1_DISABLE;
+	} else
+		tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT);
+
+	tcr |= TCR_T0SZ(va_bits);
+	/*
+	 * Translation table walk is cacheable, inner/outer WBWA and
+	 * inner shareable
+	 */
+	tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+
+	return tcr;
+}
+
+static int pte_desc_type(u64_t *pte)
+{
+	return *pte & PTE_DESC_TYPE_MASK;
+}
+
+static u64_t *calculate_pte_index(u64_t addr, int level)
+{
+	int base_level = XLAT_TABLE_BASE_LEVEL;
+	u64_t *pte;
+	u64_t idx;
+	unsigned int i;
+
+	/* Walk through all translation tables to find pte index */
+	pte = (u64_t *)base_xlat_table;
+	for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++) {
+		idx = XLAT_TABLE_VA_IDX(addr, i);
+		pte += idx;
+
+		/* Found pte index */
+		if (i == level)
+			return pte;
+		/* if PTE is not table desc, can't traverse */
+		if (pte_desc_type(pte) != PTE_TABLE_DESC)
+			return NULL;
+		/* Move to the next translation table level */
+		pte = (u64_t *)(*pte & 0x0000fffffffff000ULL);
+	}
+
+	return NULL;
+}
+
+static void set_pte_table_desc(u64_t *pte, u64_t *table, unsigned int level)
+{
+#if DUMP_PTE
+	MMU_DEBUG("%s", XLAT_TABLE_LEVEL_SPACE(level));
+	MMU_DEBUG("%p: [Table] %p\n", pte, table);
+#endif
+	/* Point pte to new table */
+	*pte = PTE_TABLE_DESC | (u64_t)table;
+}
+
+static void set_pte_block_desc(u64_t *pte, u64_t addr_pa,
+			       unsigned int attrs, unsigned int level)
+{
+	u64_t desc = addr_pa;
+	unsigned int mem_type;
+
+	desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC;
+
+	/* NS bit for security memory access from secure state */
+	desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0;
+
+	/* AP bits for Data access permission */
+	desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO;
+
+	/* the access flag */
+	desc |= PTE_BLOCK_DESC_AF;
+
+	/* memory attribute index field */
+	mem_type = MT_TYPE(attrs);
+	desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type);
+
+	switch (mem_type) {
+	case MT_DEVICE_nGnRnE:
+	case MT_DEVICE_nGnRE:
+	case MT_DEVICE_GRE:
+		/* Access to Device memory and non-cacheable memory are coherent
+		 * for all observers in the system and are treated as
+		 * Outer shareable, so, for these 2 types of memory,
+		 * it is not strictly needed to set shareability field
+		 */
+		desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+		/* Map device memory as execute-never */
+		desc |= PTE_BLOCK_DESC_PXN;
+		desc |= PTE_BLOCK_DESC_UXN;
+		break;
+	case MT_NORMAL_NC:
+	case MT_NORMAL:
+		/* Make Normal RW memory as execute never */
+		if ((attrs & MT_RW) || (attrs & MT_EXECUTE_NEVER))
+			desc |= PTE_BLOCK_DESC_PXN;
+		if (mem_type == MT_NORMAL)
+			desc |= PTE_BLOCK_DESC_INNER_SHARE;
+		else
+			desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+	}
+
+#if DUMP_PTE
+	MMU_DEBUG("%s", XLAT_TABLE_LEVEL_SPACE(level));
+	MMU_DEBUG("%p: ", pte);
+	MMU_DEBUG((mem_type == MT_NORMAL) ? "MEM" :
+		  ((mem_type == MT_NORMAL_NC) ? "NC" : "DEV"));
+	MMU_DEBUG((attrs & MT_RW) ? "-RW" : "-RO");
+	MMU_DEBUG((attrs & MT_NS) ? "-NS" : "-S");
+	MMU_DEBUG((attrs & MT_EXECUTE_NEVER) ? "-XN" : "-EXEC");
+	MMU_DEBUG("\n");
+#endif
+
+	*pte = desc;
+}
+
+/* Returns a new reallocated table */
+static u64_t *new_prealloc_table(void)
+{
+	static unsigned int table_idx;
+
+	__ASSERT(table_idx < CONFIG_MAX_XLAT_TABLES,
+		"Enough xlat tables not allocated");
+
+	return (u64_t *)(xlat_tables[table_idx++]);
+}
+
+/* Splits a block into table with entries spanning the old block */
+static void split_pte_block_desc(u64_t *pte, int level)
+{
+	u64_t old_block_desc = *pte;
+	u64_t *new_table;
+	unsigned int i = 0;
+	/* get address size shift bits for next level */
+	int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1);
+
+	MMU_DEBUG("Splitting existing PTE %p(L%d)\n", pte, level);
+
+	new_table = new_prealloc_table();
+
+	for (i = 0; i < XLAT_TABLE_ENTRIES; i++) {
+		new_table[i] = old_block_desc | (i << levelshift);
+
+		if ((level + 1) == 3)
+			new_table[i] |= PTE_PAGE_DESC;
+	}
+
+	/* Overwrite existing PTE set the new table into effect */
+	set_pte_table_desc(pte, new_table, level);
+}
+
+/* Create/Populate translation table(s) for given region */
+static void init_xlat_tables(const struct arm_mmu_region *region)
+{
+	u64_t *pte;
+	u64_t virt = region->base_va;
+	u64_t phys = region->base_pa;
+	u64_t size = region->size;
+	u64_t attrs = region->attrs;
+	u64_t level_size;
+	u64_t *new_table;
+	unsigned int level = XLAT_TABLE_BASE_LEVEL;
+
+	MMU_DEBUG("mmap: virt %llx phys %llx size %llx\n", virt, phys, size);
+	/* check minimum alignment requirement for given mmap region */
+	__ASSERT(((virt & (PAGE_SIZE - 1)) == 0) &&
+		 ((size & (PAGE_SIZE - 1)) == 0),
+		 "address/size are not page aligned\n");
+
+	while (size) {
+		__ASSERT(level <= XLAT_TABLE_LEVEL_MAX,
+			 "max translation table level exceeded\n");
+
+		/* Locate PTE for given virtual address and page table level */
+		pte = calculate_pte_index(virt, level);
+		__ASSERT(pte != NULL, "pte not found\n");
+
+		level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level);
+
+		if (size >= level_size && !(virt & (level_size - 1))) {
+			/* Given range fits into level size,
+			 * create block/page descriptor
+			 */
+			set_pte_block_desc(pte, phys, attrs, level);
+			virt += level_size;
+			phys += level_size;
+			size -= level_size;
+			/* Range is mapped, start again for next range */
+			level = XLAT_TABLE_BASE_LEVEL;
+		} else if (pte_desc_type(pte) == PTE_INVALID_DESC) {
+			/* Range doesn't fit, create subtable */
+			new_table = new_prealloc_table();
+			set_pte_table_desc(pte, new_table, level);
+			level++;
+		} else if (pte_desc_type(pte) == PTE_BLOCK_DESC) {
+			split_pte_block_desc(pte, level);
+			level++;
+		} else if (pte_desc_type(pte) == PTE_TABLE_DESC)
+			level++;
+	}
+}
+
+/* zephyr execution regions with appropriate attributes */
+static const struct arm_mmu_region mmu_zephyr_regions[] = {
+
+	/* Mark text segment cacheable,read only and executable */
+	MMU_REGION_FLAT_ENTRY("zephyr_code",
+			      (uintptr_t)_image_text_start,
+			      (uintptr_t)_image_text_size,
+			      MT_CODE | MT_SECURE),
+
+	/* Mark rodata segment cacheable, read only and execute-never */
+	MMU_REGION_FLAT_ENTRY("zephyr_rodata",
+			      (uintptr_t)_image_rodata_start,
+			      (uintptr_t)_image_rodata_size,
+			      MT_RODATA | MT_SECURE),
+
+	/* Mark rest of the zephyr execution regions (data, bss, noinit, etc.)
+	 * cacheable, read-write
+	 * Note: read-write region is marked execute-ever internally
+	 */
+	MMU_REGION_FLAT_ENTRY("zephyr_data",
+			      (uintptr_t)__kernel_ram_start,
+			      (uintptr_t)__kernel_ram_size,
+			      MT_NORMAL | MT_RW | MT_SECURE),
+};
+
+static void setup_page_tables(void)
+{
+	unsigned int index;
+	const struct arm_mmu_region *region;
+	u64_t max_va = 0, max_pa = 0;
+
+	for (index = 0; index < mmu_config.num_regions; index++) {
+		region = &mmu_config.mmu_regions[index];
+		max_va = MAX(max_va, region->base_va + region->size);
+		max_pa = MAX(max_pa, region->base_pa + region->size);
+	}
+
+	__ASSERT(max_va <= (1ULL << CONFIG_ARM64_VA_BITS),
+		 "Maximum VA not supported\n");
+	__ASSERT(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS),
+		 "Maximum PA not supported\n");
+
+	/* create translation tables for user provided platform regions */
+	for (index = 0; index < mmu_config.num_regions; index++) {
+		region = &mmu_config.mmu_regions[index];
+		if (region->size || region->attrs)
+			init_xlat_tables(region);
+	}
+
+	/* setup translation table for zephyr execution regions */
+	for (index = 0; index < ARRAY_SIZE(mmu_zephyr_regions); index++) {
+		region = &mmu_zephyr_regions[index];
+		if (region->size || region->attrs)
+			init_xlat_tables(region);
+	}
+}
+
+static void enable_mmu_el1(unsigned int flags)
+{
+	ARG_UNUSED(flags);
+	u64_t val;
+
+	/* Set MAIR, TCR and TBBR registers */
+	__asm__ volatile("msr mair_el1, %0"
+			:
+			: "r" (MEMORY_ATTRIBUTES)
+			: "memory", "cc");
+	__asm__ volatile("msr tcr_el1, %0"
+			:
+			: "r" (get_tcr(1))
+			: "memory", "cc");
+	__asm__ volatile("msr ttbr0_el1, %0"
+			:
+			: "r" ((u64_t)base_xlat_table)
+			: "memory", "cc");
+
+	/* Ensure these changes are seen before MMU is enabled */
+	__ISB();
+
+	/* Enable the MMU and data cache */
+	__asm__ volatile("mrs %0, sctlr_el1" : "=r" (val));
+	__asm__ volatile("msr sctlr_el1, %0"
+			:
+			: "r" (val | SCTLR_M_BIT | SCTLR_C_BIT)
+			: "memory", "cc");
+
+	/* Ensure the MMU enable takes effect immediately */
+	__ISB();
+
+	MMU_DEBUG("MMU enabled with dcache\n");
+}
+
+/* ARM MMU Driver Initial Setup */
+
+/*
+ * @brief MMU default configuration
+ *
+ * This function provides the default configuration mechanism for the Memory
+ * Management Unit (MMU).
+ */
+static int arm_mmu_init(struct device *arg)
+{
+	u64_t val;
+	unsigned int idx, flags = 0;
+
+	/* Current MMU code supports only EL1 */
+	__asm__ volatile("mrs %0, CurrentEL" : "=r" (val));
+
+	__ASSERT(GET_EL(val) == MODE_EL1,
+		 "Exception level not EL1, MMU not enabled!\n");
+
+	/* Ensure that MMU is already not enabled */
+	__asm__ volatile("mrs %0, sctlr_el1" : "=r" (val));
+	__ASSERT((val & SCTLR_M_BIT) == 0, "MMU is already enabled\n");
+
+	MMU_DEBUG("xlat tables:\n");
+	MMU_DEBUG("base table(L%d): %p, %d entries\n", XLAT_TABLE_BASE_LEVEL,
+			(u64_t *)base_xlat_table, NUM_BASE_LEVEL_ENTRIES);
+	for (idx = 0; idx < CONFIG_MAX_XLAT_TABLES; idx++)
+		MMU_DEBUG("%d: %p\n", idx, (u64_t *)(xlat_tables + idx));
+
+	setup_page_tables();
+
+	/* currently only EL1 is supported */
+	enable_mmu_el1(flags);
+
+	return 0;
+}
+
+SYS_INIT(arm_mmu_init, PRE_KERNEL_1,
+#if MMU_DEBUG_PRINTS
+	 MMU_DEBUG_PRIORITY
+#else
+	 CONFIG_KERNEL_INIT_PRIORITY_DEVICE
+#endif
+);

arch/arm/core/aarch64/cpu_idle.S

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief ARM64 Cortex-A power management
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <arch/cpu.h>
+
+GTEXT(arch_cpu_idle)
+SECTION_FUNC(TEXT, arch_cpu_idle)
+#ifdef CONFIG_TRACING
+	stp	xzr, x30, [sp, #-16]!
+	bl	sys_trace_idle
+	ldp	xzr, x30, [sp], #16
+#endif
+	dsb	sy
+	wfi
+	msr	daifclr, #(DAIFSET_IRQ)
+	ret
+
+GTEXT(arch_cpu_atomic_idle)
+SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
+#ifdef CONFIG_TRACING
+	stp	xzr, x30, [sp, #-16]!
+	bl	sys_trace_idle
+	ldp	xzr, x30, [sp], #16
+#endif
+	msr	daifset, #(DAIFSET_IRQ)
+	isb
+	wfe
+	tst	x0, #(DAIF_IRQ)
+	beq	_irq_disabled
+	msr	daifclr, #(DAIFSET_IRQ)
+_irq_disabled:
+	ret

arch/arm/core/aarch64/fatal.c

@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Kernel fatal error handler for ARM64 Cortex-A
+ *
+ * This module provides the z_arm64_fatal_error() routine for ARM64 Cortex-A
+ * CPUs
+ */
+
+#include <kernel.h>
+#include <logging/log.h>
+
+LOG_MODULE_DECLARE(os);
+
+static void print_EC_cause(u64_t esr)
+{
+	u32_t EC = (u32_t)esr >> 26;
+
+	switch (EC) {
+	case 0b000000:
+		LOG_ERR("Unknown reason");
+		break;
+	case 0b000001:
+		LOG_ERR("Trapped WFI or WFE instruction execution");
+		break;
+	case 0b000011:
+		LOG_ERR("Trapped MCR or MRC access with (coproc==0b1111) that "
+			"is not reported using EC 0b000000");
+		break;
+	case 0b000100:
+		LOG_ERR("Trapped MCRR or MRRC access with (coproc==0b1111) "
+			"that is not reported using EC 0b000000");
+		break;
+	case 0b000101:
+		LOG_ERR("Trapped MCR or MRC access with (coproc==0b1110)");
+		break;
+	case 0b000110:
+		LOG_ERR("Trapped LDC or STC access");
+		break;
+	case 0b000111:
+		LOG_ERR("Trapped access to SVE, Advanced SIMD, or "
+			"floating-point functionality");
+		break;
+	case 0b001100:
+		LOG_ERR("Trapped MRRC access with (coproc==0b1110)");
+		break;
+	case 0b001101:
+		LOG_ERR("Branch Target Exception");
+		break;
+	case 0b001110:
+		LOG_ERR("Illegal Execution state");
+		break;
+	case 0b010001:
+		LOG_ERR("SVC instruction execution in AArch32 state");
+		break;
+	case 0b011000:
+		LOG_ERR("Trapped MSR, MRS or System instruction execution in "
+			"AArch64 state, that is not reported using EC "
+			"0b000000, 0b000001 or 0b000111");
+		break;
+	case 0b011001:
+		LOG_ERR("Trapped access to SVE functionality");
+		break;
+	case 0b100000:
+		LOG_ERR("Instruction Abort from a lower Exception level, that "
+			"might be using AArch32 or AArch64");
+		break;
+	case 0b100001:
+		LOG_ERR("Instruction Abort taken without a change in Exception "
+			"level.");
+		break;
+	case 0b100010:
+		LOG_ERR("PC alignment fault exception.");
+		break;
+	case 0b100100:
+		LOG_ERR("Data Abort from a lower Exception level, that might "
+			"be using AArch32 or AArch64");
+		break;
+	case 0b100101:
+		LOG_ERR("Data Abort taken without a change in Exception level");
+		break;
+	case 0b100110:
+		LOG_ERR("SP alignment fault exception");
+		break;
+	case 0b101000:
+		LOG_ERR("Trapped floating-point exception taken from AArch32 "
+			"state");
+		break;
+	case 0b101100:
+		LOG_ERR("Trapped floating-point exception taken from AArch64 "
+			"state.");
+		break;
+	case 0b101111:
+		LOG_ERR("SError interrupt");
+		break;
+	case 0b110000:
+		LOG_ERR("Breakpoint exception from a lower Exception level, "
+			"that might be using AArch32 or AArch64");
+		break;
+	case 0b110001:
+		LOG_ERR("Breakpoint exception taken without a change in "
+			"Exception level");
+		break;
+	case 0b110010:
+		LOG_ERR("Software Step exception from a lower Exception level, "
+			"that might be using AArch32 or AArch64");
+		break;
+	case 0b110011:
+		LOG_ERR("Software Step exception taken without a change in "
+			"Exception level");
+		break;
+	case 0b110100:
+		LOG_ERR("Watchpoint exception from a lower Exception level, "
+			"that might be using AArch32 or AArch64");
+		break;
+	case 0b110101:
+		LOG_ERR("Watchpoint exception taken without a change in "
+			"Exception level.");
+		break;
+	case 0b111000:
+		LOG_ERR("BKPT instruction execution in AArch32 state");
+		break;
+	case 0b111100:
+		LOG_ERR("BRK instruction execution in AArch64 state.");
+		break;
+	}
+}
+
+static void esf_dump(const z_arch_esf_t *esf)
+{
+	LOG_ERR("x1:  %-8llx  x0:  %llx",
+		esf->basic.regs[18], esf->basic.regs[19]);
+	LOG_ERR("x2:  %-8llx  x3:  %llx",
+		esf->basic.regs[16], esf->basic.regs[17]);
+	LOG_ERR("x4:  %-8llx  x5:  %llx",
+		esf->basic.regs[14], esf->basic.regs[15]);
+	LOG_ERR("x6:  %-8llx  x7:  %llx",
+		esf->basic.regs[12], esf->basic.regs[13]);
+	LOG_ERR("x8:  %-8llx  x9:  %llx",
+		esf->basic.regs[10], esf->basic.regs[11]);
+	LOG_ERR("x10: %-8llx  x11: %llx",
+		esf->basic.regs[8], esf->basic.regs[9]);
+	LOG_ERR("x12: %-8llx  x13: %llx",
+		esf->basic.regs[6], esf->basic.regs[7]);
+	LOG_ERR("x14: %-8llx  x15: %llx",
+		esf->basic.regs[4], esf->basic.regs[5]);
+	LOG_ERR("x16: %-8llx  x17: %llx",
+		esf->basic.regs[2], esf->basic.regs[3]);
+	LOG_ERR("x18: %-8llx  x30: %llx",
+		esf->basic.regs[0], esf->basic.regs[1]);
+}
+
+void z_arm64_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
+{
+	u64_t el, esr, elr, far;
+
+	if (reason != K_ERR_SPURIOUS_IRQ) {
+		__asm__ volatile("mrs %0, CurrentEL" : "=r" (el));
+
+		switch (GET_EL(el)) {
+		case MODE_EL1:
+			__asm__ volatile("mrs %0, esr_el1" : "=r" (esr));
+			__asm__ volatile("mrs %0, far_el1" : "=r" (far));
+			__asm__ volatile("mrs %0, elr_el1" : "=r" (elr));
+			break;
+		case MODE_EL2:
+			__asm__ volatile("mrs %0, esr_el2" : "=r" (esr));
+			__asm__ volatile("mrs %0, far_el2" : "=r" (far));
+			__asm__ volatile("mrs %0, elr_el2" : "=r" (elr));
+			break;
+		case MODE_EL3:
+			__asm__ volatile("mrs %0, esr_el3" : "=r" (esr));
+			__asm__ volatile("mrs %0, far_el3" : "=r" (far));
+			__asm__ volatile("mrs %0, elr_el3" : "=r" (elr));
+			break;
+		default:
+			/* Just to keep the compiler happy */
+			esr = elr = far = 0;
+			break;
+		}
+
+		if (GET_EL(el) != MODE_EL0) {
+			LOG_ERR("ESR_ELn: %llx", esr);
+			LOG_ERR("FAR_ELn: %llx", far);
+			LOG_ERR("ELR_ELn: %llx", elr);
+
+			print_EC_cause(esr);
+		}
+
+	}
+
+	if (esf != NULL) {
+		esf_dump(esf);
+	}
+	z_fatal_error(reason, esf);
+
+	CODE_UNREACHABLE;
+}

arch/arm/core/aarch64/irq_manage.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief ARM64 Cortex-A interrupt management
+ */
+
+#include <kernel.h>
+#include <arch/cpu.h>
+#include <device.h>
+#include <tracing/tracing.h>
+#include <irq.h>
+#include <irq_nextlevel.h>
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <sw_isr_table.h>
+
+void z_arm64_fatal_error(unsigned int reason, const z_arch_esf_t *esf);
+
+void arch_irq_enable(unsigned int irq)
+{
+	struct device *dev = _sw_isr_table[0].arg;
+
+	irq_enable_next_level(dev, (irq >> 8) - 1);
+}
+
+void arch_irq_disable(unsigned int irq)
+{
+	struct device *dev = _sw_isr_table[0].arg;
+
+	irq_disable_next_level(dev, (irq >> 8) - 1);
+}
+
+int arch_irq_is_enabled(unsigned int irq)
+{
+	struct device *dev = _sw_isr_table[0].arg;
+
+	return irq_is_enabled_next_level(dev);
+}
+
+void z_arm64_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
+{
+	struct device *dev = _sw_isr_table[0].arg;
+
+	if (irq == 0)
+		return;
+
+	irq_set_priority_next_level(dev, (irq >> 8) - 1, prio, flags);
+}
+
+void z_irq_spurious(void *unused)
+{
+	ARG_UNUSED(unused);
+
+	z_arm64_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
+}

arch/arm/core/aarch64/irq_offload.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Software interrupts utility code - ARM64 implementation
+ */
+
+#include <kernel.h>
+#include <irq_offload.h>
+#include <aarch64/exc.h>
+
+volatile irq_offload_routine_t offload_routine;
+static void *offload_param;
+
+void z_irq_do_offload(void)
+{
+	offload_routine(offload_param);
+}
+
+void arch_irq_offload(irq_offload_routine_t routine, void *parameter)
+{
+	k_sched_lock();
+	offload_routine = routine;
+	offload_param = parameter;
+
+	z_arm64_offload();
+
+	offload_routine = NULL;
+	k_sched_unlock();
+}

arch/arm/core/aarch64/isr_wrapper.S

@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief ARM64 Cortex-A ISRs wrapper
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <offsets_short.h>
+#include <arch/cpu.h>
+#include <sw_isr_table.h>
+
+GDATA(_sw_isr_table)
+
+/**
+ * @brief Wrapper around ISRs when inserted in software ISR table
+ *
+ * When inserted in the vector table, _isr_wrapper() demuxes the ISR table
+ * using the running interrupt number as the index, and invokes the registered
+ * ISR with its corresponding argument. When returning from the ISR, it
+ * determines if a context switch needs to happen.
+ *
+ * @return N/A
+ */
+
+GTEXT(_isr_wrapper)
+SECTION_FUNC(TEXT, _isr_wrapper)
+	/*
+	 * Save x0-x18 (and x30) on the process stack because they can be
+	 * clobbered by the ISR and/or context switch.
+	 *
+	 * Two things can happen:
+	 *
+	 * - No context-switch: in this case x19-x28 are callee-saved register
+	 *   so we can be sure they are not going to be clobbered by ISR.
+	 * - Context-switch: the callee-saved registers are saved by
+	 *   z_arm64_pendsv() in the kernel structure.
+	 */
+	stp	x0, x1, [sp, #-16]!
+	stp	x2, x3, [sp, #-16]!
+	stp	x4, x5, [sp, #-16]!
+	stp	x6, x7, [sp, #-16]!
+	stp	x8, x9, [sp, #-16]!
+	stp	x10, x11, [sp, #-16]!
+	stp	x12, x13, [sp, #-16]!
+	stp	x14, x15, [sp, #-16]!
+	stp	x16, x17, [sp, #-16]!
+	stp	x18, x30, [sp, #-16]!
+
+	/* ++(_kernel->nested) to be checked by arch_is_in_isr() */
+	ldr	x1, =_kernel
+	ldr	x2, [x1, #_kernel_offset_to_nested]
+	add	x2, x2, #1
+	str	x2, [x1, #_kernel_offset_to_nested]
+
+#ifdef CONFIG_TRACING
+	bl	sys_trace_isr_enter
+#endif
+
+	/* Cortex-A has one IRQ line so the main handler will be at offset 0 */
+	ldr	x1, =_sw_isr_table
+	ldp	x0, x3, [x1] /* arg in x0, ISR in x3 */
+	blr	x3
+
+#ifdef CONFIG_TRACING
+	bl	sys_trace_isr_exit
+#endif
+
+	/* --(_kernel->nested) */
+	ldr	x1, =_kernel
+	ldr	x2, [x1, #_kernel_offset_to_nested]
+	sub	x2, x2, #1
+	str	x2, [x1, #_kernel_offset_to_nested]
+
+	/* Check if we need to context switch */
+	ldr	x2, [x1, #_kernel_offset_to_current]
+	ldr	x3, [x1, #_kernel_offset_to_ready_q_cache]
+	cmp	x2, x3
+	beq	exit
+
+	/* Switch thread */
+	bl	z_arm64_pendsv
+
+	/* We return here in two cases:
+	 *
+	 * - The ISR was taken and no context switch was performed.
+	 * - A context-switch was performed during the ISR in the past and now
+	 *   the thread has been switched in again and we return here from the
+	 *   ret in z_arm64_pendsv() because x30 was saved and restored.
+	 */
+exit:
+#ifdef CONFIG_STACK_SENTINEL
+	bl	z_check_stack_sentinel
+#endif
+	b	z_arm64_exit_exc
+

arch/arm/core/aarch64/macro.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _MACRO_H_
+#define _MACRO_H_
+
+#ifdef _ASMLANGUAGE
+
+.macro	switch_el, xreg, el3_label, el2_label, el1_label
+	mrs	\xreg, CurrentEL
+	cmp	\xreg, 0xc
+	beq	\el3_label
+	cmp	\xreg, 0x8
+	beq	\el2_label
+	cmp	\xreg, 0x4
+	beq	\el1_label
+.endm
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* _MACRO_H_ */

arch/arm/core/aarch64/prep_c.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Full C support initialization
+ *
+ * Initialization of full C support: zero the .bss and call z_cstart().
+ *
+ * Stack is available in this module, but not the global data/bss until their
+ * initialization is performed.
+ */
+
+#include <kernel_internal.h>
+
+extern FUNC_NORETURN void z_cstart(void);
+/**
+ *
+ * @brief Prepare to and run C code
+ *
+ * This routine prepares for the execution of and runs C code.
+ *
+ * @return N/A
+ */
+void z_arm64_prep_c(void)
+{
+	z_bss_zero();
+	z_cstart();
+
+	CODE_UNREACHABLE;
+}

arch/arm/core/aarch64/reset.S

@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Reset handler
+ *
+ * Reset handler that prepares the system for running C code.
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <arch/cpu.h>
+#include "vector_table.h"
+#include "macro.h"
+
+/**
+ *
+ * @brief Reset vector
+ *
+ * Ran when the system comes out of reset. The processor is in thread mode with
+ * privileged level. At this point, neither SP_EL0 nor SP_ELx point to a valid
+ * area in SRAM.
+ *
+ * When these steps are completed, jump to z_arm64_prep_c(), which will finish
+ * setting up the system for running C code.
+ *
+ * @return N/A
+ */
+GTEXT(__reset)
+SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset)
+
+/*
+ * The entry point is located at the __reset symbol, which is fetched by a XIP
+ * image playing the role of a bootloader, which jumps to it, not through the
+ * reset vector mechanism. Such bootloaders might want to search for a __start
+ * symbol instead, so create that alias here.
+ */
+GTEXT(__start)
+SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
+
+#ifdef CONFIG_SWITCH_TO_EL1
+	switch_el x1, 3f, 2f, 1f
+3:
+	/* Disable MMU and async exceptions routing to EL1 */
+	msr	sctlr_el1, xzr
+
+	/* Disable EA/IRQ/FIQ routing to EL3 and set EL1 to AArch64 */
+	mov	x0, xzr
+	orr	x0, x0, #(SCR_EL3_RW)
+	msr	scr_el3, x0
+
+	/* On eret return to EL1 with DAIF masked */
+	mov	x0, xzr
+	orr	x0, x0, #(DAIF_MASK)
+	orr	x0, x0, #(SPSR_EL3_TO_EL1)
+	orr	x0, x0, #(SPSR_EL3_h)
+	msr	spsr_el3, x0
+
+	adr	x0, 1f
+	msr	elr_el3, x0
+	eret
+2:
+	/* Boot from EL2 not supported */
+	bl	.
+1:
+#endif
+	/* Setup vector table */
+	adr	x0, _vector_table
+
+	switch_el x1, 3f, 2f, 1f
+3:
+	/* Initialize VBAR */
+	msr	vbar_el3, x0
+
+	/* SError, IRQ and FIQ routing enablement in EL3 */
+	mrs	x0, scr_el3
+	orr	x0, x0, #(SCR_EL3_IRQ | SCR_EL3_FIQ | SCR_EL3_EA)
+	msr	scr_el3, x0
+
+	/* Disable access trapping in EL3 for NEON/FP */
+	msr	cptr_el3, xzr
+
+	/*
+	 * Enable the instruction cache, stack pointer and data access
+	 * alignment checks and disable speculative loads.
+	 */
+	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
+	mrs	x0, sctlr_el3
+	orr	x0, x0, x1
+	msr	sctlr_el3, x0
+	b	0f
+2:
+	/* Initialize VBAR */
+	msr	vbar_el2, x0
+
+	/* SError, IRQ and FIQ routing enablement in EL2 */
+	mrs	x0, hcr_el2
+	orr	x0, x0, #(HCR_EL2_FMO | HCR_EL2_IMO | HCR_EL2_AMO)
+	msr	hcr_el2, x0
+
+	/* Disable access trapping in EL2 for NEON/FP */
+	msr	cptr_el2, xzr
+
+	/*
+	 * Enable the instruction cache, stack pointer and data access
+	 * alignment checks and disable speculative loads.
+	 */
+	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
+	mrs	x0, sctlr_el2
+	orr	x0, x0, x1
+	msr	sctlr_el2, x0
+	b	0f
+1:
+	/* Initialize VBAR */
+	msr	vbar_el1, x0
+
+	/* Disable access trapping in EL1 for NEON/FP */
+	mov	x1, #(CPACR_EL1_FPEN_NOTRAP)
+	msr	cpacr_el1, x1
+
+	/*
+	 * Enable the instruction cache, stack pointer and data access
+	 * alignment checks and disable speculative loads.
+	 */
+	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
+	mrs	x0, sctlr_el1
+	orr	x0, x0, x1
+	msr	sctlr_el1, x0
+0:
+	isb
+
+	/* Enable the SError interrupt */
+	msr	daifclr, #(DAIFSET_ABT)
+
+	/* Switch to SP_ELn and setup the stack */
+	msr	spsel, #1
+	ldr	x0, =(_interrupt_stack)
+	add	x0, x0, #(CONFIG_ISR_STACK_SIZE)
+	mov	sp, x0
+
+	bl	z_arm64_prep_c

arch/arm/core/aarch64/swap.c

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <kernel_internal.h>
+
+extern const int _k_neg_eagain;
+
+int arch_swap(unsigned int key)
+{
+	_current->arch.swap_return_value = _k_neg_eagain;
+
+	z_arm64_call_svc();
+	irq_unlock(key);
+
+	/* Context switch is performed here. Returning implies the
+	 * thread has been context-switched-in again.
+	 */
+	return _current->arch.swap_return_value;
+}

arch/arm/core/aarch64/swap_helper.S

@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Thread context switching for ARM64 Cortex-A
+ *
+ * This module implements the routines necessary for thread context switching
+ * on ARM64 Cortex-A.
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <offsets_short.h>
+#include <arch/cpu.h>
+#include <syscall.h>
+#include "macro.h"
+
+GDATA(_kernel)
+GDATA(_k_neg_eagain)
+
+/**
+ * @brief PendSV exception handler, handling context switches
+ *
+ * The PendSV exception is the only execution context in the system that can
+ * perform context switching. When an execution context finds out it has to
+ * switch contexts, it pends the PendSV exception.
+ *
+ * When PendSV is pended, the decision that a context switch must happen has
+ * already been taken. In other words, when z_arm64_pendsv() runs, we *know* we
+ * have to swap *something*.
+ *
+ * For Cortex-A, PendSV exception is not supported by the architecture and this
+ * function is directly called either by _isr_wrapper() in case of preemption,
+ * or z_arm64_svc() in case of cooperative switching.
+ */
+GTEXT(z_arm64_pendsv)
+SECTION_FUNC(TEXT, z_arm64_pendsv)
+#ifdef CONFIG_TRACING
+	stp	xzr, x30, [sp, #-16]!
+	bl	sys_trace_thread_switched_in
+	ldp	xzr, x30, [sp], #16
+#endif
+	/* load _kernel into x1 and current k_thread into x2 */
+	ldr	x1, =_kernel
+	ldr	x2, [x1, #_kernel_offset_to_current]
+
+	/* addr of callee-saved regs in thread in x0 */
+	ldr	x0, =_thread_offset_to_callee_saved
+	add	x0, x0, x2
+
+	/* Store rest of process context including x30, SPSR_ELn and ELR_ELn */
+	stp	x19, x20, [x0], #16
+	stp	x21, x22, [x0], #16
+	stp	x23, x24, [x0], #16
+	stp	x25, x26, [x0], #16
+	stp	x27, x28, [x0], #16
+	stp	x29, x30, [x0], #16
+
+	switch_el x3, 3f, 2f, 1f
+3:
+	mrs	x4, spsr_el3
+	mrs	x5, elr_el3
+	b	0f
+2:
+	mrs	x4, spsr_el2
+	mrs	x5, elr_el2
+	b	0f
+1:
+	mrs	x4, spsr_el1
+	mrs	x5, elr_el1
+0:
+	stp	x4, x5, [x0], #16
+
+	/* Save the current SP */
+	mov	x6, sp
+	str	x6, [x0]
+
+	/* fetch the thread to run from the ready queue cache */
+	ldr	x2, [x1, #_kernel_offset_to_ready_q_cache]
+	str	x2, [x1, #_kernel_offset_to_current]
+
+	/* load _kernel into x1 and current k_thread into x2 */
+	ldr	x1, =_kernel
+	ldr	x2, [x1, #_kernel_offset_to_current]
+
+	/* addr of callee-saved regs in thread in x0 */
+	ldr	x0, =_thread_offset_to_callee_saved
+	add	x0, x0, x2
+
+	/* Restore x19-x29 plus x30, SPSR_ELn and ELR_ELn */
+	ldp	x19, x20, [x0], #16
+	ldp	x21, x22, [x0], #16
+	ldp	x23, x24, [x0], #16
+	ldp	x25, x26, [x0], #16
+	ldp	x27, x28, [x0], #16
+	ldp	x29, x30, [x0], #16
+
+	ldp	x4, x5, [x0], #16
+
+	switch_el x3, 3f, 2f, 1f
+3:
+	msr	spsr_el3, x4
+	msr	elr_el3, x5
+	b	0f
+2:
+	msr	spsr_el2, x4
+	msr	elr_el2, x5
+	b	0f
+1:
+	msr	spsr_el1, x4
+	msr	elr_el1, x5
+0:
+	ldr	x6, [x0]
+	mov	sp, x6
+
+#ifdef CONFIG_TRACING
+	stp	xzr, x30, [sp, #-16]!
+	bl	sys_trace_thread_switched_out
+	ldp	xzr, x30, [sp], #16
+#endif
+
+	/* We restored x30 from the process stack. There are three possible
+	 * cases:
+	 *
+	 * - We return to z_arm64_svc() when swappin in a thread that was
+	 *   swapped out by z_arm64_svc() before jumping into
+	 *   z_arm64_exit_exc()
+	 * - We return to _isr_wrapper() when swappin in a thread that was
+	 *   swapped out by _isr_wrapper() before jumping into
+	 *   z_arm64_exit_exc()
+	 * - We return (jump) into z_thread_entry_wrapper() for new threads
+	 * (see thread.c)
+	 */
+	ret
+
+/**
+ *
+ * @brief Entry wrapper for new threads
+ *
+ * @return N/A
+ */
+
+GTEXT(z_thread_entry_wrapper)
+SECTION_FUNC(TEXT, z_thread_entry_wrapper)
+	/*
+	 * z_thread_entry_wrapper is called for every new thread upon the return
+	 * of arch_swap() or ISR. Its address, as well as its input function
+	 * arguments thread_entry_t, void *, void *, void * are restored from
+	 * the thread stack (see thread.c).
+	 * In this case, thread_entry_t, * void *, void * and void * are stored
+	 * in registers x0, x1, x2 and x3. These registers are used as arguments
+	 * to function z_thread_entry.
+	 */
+	ldp	x0, x1, [sp], #16
+	ldp	x2, x3, [sp], #16
+
+	/* ELR_ELn was set in thread.c to z_thread_entry() */
+	eret
+
+/**
+ *
+ * @brief Service call handler
+ *
+ * The service call (SVC) is used in the following occasions:
+ * - Cooperative context switching
+ * - IRQ offloading
+ *
+ * @return N/A
+ */
+GTEXT(z_arm64_svc)
+SECTION_FUNC(TEXT, z_arm64_svc)
+	/*
+	 * Save the volatile registers and x30 on the process stack. This is
+	 * needed if the thread is switched out.
+	 */
+	stp	x0, x1, [sp, #-16]!
+	stp	x2, x3, [sp, #-16]!
+	stp	x4, x5, [sp, #-16]!
+	stp	x6, x7, [sp, #-16]!
+	stp	x8, x9, [sp, #-16]!
+	stp	x10, x11, [sp, #-16]!
+	stp	x12, x13, [sp, #-16]!
+	stp	x14, x15, [sp, #-16]!
+	stp	x16, x17, [sp, #-16]!
+	stp	x18, x30, [sp, #-16]!
+
+	switch_el x3, 3f, 2f, 1f
+3:
+	mrs	x0, esr_el3
+	b	0f
+2:
+	mrs	x0, esr_el2
+	b	0f
+1:
+	mrs	x0, esr_el1
+0:
+	lsr	x1, x0, #26
+
+	cmp	x1, #0x15 /* 0x15 = SVC */
+	bne	inv
+
+	/* Demux the SVC call */
+	and	x2, x0, #0xff
+	cmp	x2, #_SVC_CALL_CONTEXT_SWITCH
+	beq	context_switch
+
+#ifdef CONFIG_IRQ_OFFLOAD
+	cmp	x2, #_SVC_CALL_IRQ_OFFLOAD
+	beq	offload
+	b	inv
+offload:
+	/* ++(_kernel->nested) to be checked by arch_is_in_isr() */
+	ldr	x1, =_kernel
+	ldr	x2, [x1, #_kernel_offset_to_nested]
+	add	x2, x2, #1
+	str	x2, [x1, #_kernel_offset_to_nested]
+
+	bl	z_irq_do_offload
+
+	/* --(_kernel->nested) */
+	ldr	x1, =_kernel
+	ldr	x2, [x1, #_kernel_offset_to_nested]
+	sub	x2, x2, #1
+	str	x2, [x1, #_kernel_offset_to_nested]
+	b	exit
+#endif
+	b	inv
+
+context_switch:
+	bl	z_arm64_pendsv
+
+exit:
+	b	z_arm64_exit_exc
+
+inv:
+	mov	x1, sp
+	mov	x0, #0 /* K_ERR_CPU_EXCEPTION */
+	b	z_arm64_fatal_error
+
+
+/**
+ * @brief Restore volatile registers and x30
+ *
+ * This is the common exit point for z_arm64_pendsv() and _isr_wrapper(). We
+ * restore the registers saved on the process stack including X30. The return
+ * address used by eret (in ELR_ELn) is either restored by z_arm64_pendsv() if
+ * a context-switch happened or not touched at all by the ISR if there was no
+ * context-switch.
+ *
+ * @return N/A
+ */
+
+GTEXT(z_arm64_exit_exc)
+SECTION_FUNC(TEXT, z_arm64_exit_exc)
+	/*
+	 * In x30 we can have:
+	 *
+	 * - The address of irq_unlock() in swap.c when swapping in a thread
+	 *   that was cooperatively swapped out (used by ret in
+	 *   z_arm64_call_svc())
+	 * - A previos generic value if the thread that we are swapping in was
+	 *   swapped out preemptively by the ISR.
+	 */
+	ldp	x18, x30, [sp], #16
+	ldp	x16, x17, [sp], #16
+	ldp	x14, x15, [sp], #16
+	ldp	x12, x13, [sp], #16
+	ldp	x10, x11, [sp], #16
+	ldp	x8, x9, [sp], #16
+	ldp	x6, x7, [sp], #16
+	ldp	x4, x5, [sp], #16
+	ldp	x2, x3, [sp], #16
+	ldp	x0, x1, [sp], #16
+
+	/*
+	 * In general in the  ELR_ELn register we can find:
+	 *
+	 * - The address of ret in z_arm64_call_svc() in case of arch_swap()
+	 *   (see swap.c)
+	 * - The address of the next instruction at the time of the IRQ when the
+	 *   thread was switched out.
+	 * - The address of z_thread_entry() for new threads (see thread.c).
+	 */
+	eret
+
+GTEXT(z_arm64_call_svc)
+SECTION_FUNC(TEXT, z_arm64_call_svc)
+	svc	#_SVC_CALL_CONTEXT_SWITCH
+	ret
+
+#ifdef CONFIG_IRQ_OFFLOAD
+GTEXT(z_arm64_offload)
+SECTION_FUNC(TEXT, z_arm64_offload)
+	svc	#_SVC_CALL_IRQ_OFFLOAD
+	ret
+#endif
+

arch/arm/core/aarch64/thread.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief New thread creation for ARM64 Cortex-A
+ *
+ * Core thread related primitives for the ARM64 Cortex-A
+ */
+
+#include <kernel.h>
+#include <ksched.h>
+#include <wait_q.h>
+#include <arch/cpu.h>
+
+/**
+ *
+ * @brief Initialize a new thread from its stack space
+ *
+ * The control structure (thread) is put at the lower address of the stack. An
+ * initial context, to be "restored" by z_arm64_pendsv(), is put at the other
+ * end of the stack, and thus reusable by the stack when not needed anymore.
+ *
+ * <options> is currently unused.
+ *
+ * @param stack      pointer to the aligned stack memory
+ * @param stackSize  size of the available stack memory in bytes
+ * @param pEntry the entry point
+ * @param parameter1 entry point to the first param
+ * @param parameter2 entry point to the second param
+ * @param parameter3 entry point to the third param
+ * @param priority   thread priority
+ * @param options    thread options: K_ESSENTIAL, K_FP_REGS
+ *
+ * @return N/A
+ */
+
+void z_thread_entry_wrapper(k_thread_entry_t k, void *p1, void *p2, void *p3);
+
+void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
+		     size_t stackSize, k_thread_entry_t pEntry,
+		     void *parameter1, void *parameter2, void *parameter3,
+		     int priority, unsigned int options)
+{
+	char *pStackMem = Z_THREAD_STACK_BUFFER(stack);
+	char *stackEnd;
+	struct __esf *pInitCtx;
+
+	stackEnd = pStackMem + stackSize;
+
+	z_new_thread_init(thread, pStackMem, stackSize, priority, options);
+
+	pInitCtx = (struct __esf *)(STACK_ROUND_DOWN(stackEnd -
+				    sizeof(struct __basic_sf)));
+
+	pInitCtx->basic.regs[0] = (u64_t)pEntry;
+	pInitCtx->basic.regs[1] = (u64_t)parameter1;
+	pInitCtx->basic.regs[2] = (u64_t)parameter2;
+	pInitCtx->basic.regs[3] = (u64_t)parameter3;
+
+	/*
+	 * We are saving:
+	 *
+	 * - SP: to pop out pEntry and parameters when going through
+	 *   z_thread_entry_wrapper().
+	 * - x30: to be used by ret in z_arm64_pendsv() when the new task is
+	 *   first scheduled.
+	 * - ELR_EL1: to be used by eret in z_thread_entry_wrapper() to return
+	 *   to z_thread_entry() with pEntry in x0 and the parameters already
+	 *   in place in x1, x2, x3.
+	 * - SPSR_EL1: to enable IRQs (we are masking debug exceptions, SError
+	 *   interrupts and FIQs).
+	 */
+
+	thread->callee_saved.sp = (u64_t)pInitCtx;
+	thread->callee_saved.x30 = (u64_t)z_thread_entry_wrapper;
+	thread->callee_saved.elr = (u64_t)z_thread_entry;
+	thread->callee_saved.spsr = SPSR_MODE_EL1H | DAIF_FIQ;
+}

arch/arm/core/aarch64/vector_table.S

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Populated vector table
+ */
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include "vector_table.h"
+
+/*
+ * Four types of exceptions:
+ * - synchronous: aborts from MMU, SP/CP alignment checking, unallocated
+ *   instructions, SVCs/SMCs/HVCs, ...)
+ * - IRQ: group 1 (normal) interrupts
+ * - FIQ: group 0 or secure interrupts
+ * - SError: fatal system errors
+ *
+ * Four different contexts:
+ * - from same exception level, when using the SP_EL0 stack pointer
+ * - from same exception level, when using the SP_ELx stack pointer
+ * - from lower exception level, when this is AArch64
+ * - from lower exception level, when this is AArch32
+ *
+ * +------------------+------------------+-------------------------+
+ * |     Address      |  Exception type  |       Description       |
+ * +------------------+------------------+-------------------------+
+ * | VBAR_ELn + 0x000 | Synchronous      | Current EL with SP0     |
+ * |          + 0x080 | IRQ / vIRQ       |                         |
+ * |          + 0x100 | FIQ / vFIQ       |                         |
+ * |          + 0x180 | SError / vSError |                         |
+ * +------------------+------------------+-------------------------+
+ * |          + 0x200 | Synchronous      | Current EL with SPx     |
+ * |          + 0x280 | IRQ / vIRQ       |                         |
+ * |          + 0x300 | FIQ / vFIQ       |                         |
+ * |          + 0x380 | SError / vSError |                         |
+ * +------------------+------------------+-------------------------+
+ * |          + 0x400 | Synchronous      | Lower EL using  AArch64 |
+ * |          + 0x480 | IRQ / vIRQ       |                         |
+ * |          + 0x500 | FIQ / vFIQ       |                         |
+ * |          + 0x580 | SError / vSError |                         |
+ * +------------------+------------------+-------------------------+
+ * |          + 0x600 | Synchronous      | Lower EL using AArch64  |
+ * |          + 0x680 | IRQ / vIRQ       |                         |
+ * |          + 0x700 | FIQ / vFIQ       |                         |
+ * |          + 0x780 | SError / vSError |                         |
+ * +------------------+------------------+-------------------------+
+ */
+
+	/* The whole table must be 2K aligned */
+	.align 11
+SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
+
+	/* Current EL with SP0 / Synchronous */
+	.align 7
+	b	.
+
+	/* Current EL with SP0 / IRQ */
+	.align 7
+	b	.
+
+	/* Current EL with SP0 / FIQ */
+	.align 7
+	b 	.
+
+	/* Current EL with SP0 / SError */
+	.align 7
+	b	.
+
+	/* Current EL with SPx / Synchronous */
+	.align 7
+	b	z_arm64_svc
+
+	/* Current EL with SPx / IRQ */
+	.align 7
+	b	_isr_wrapper
+
+	/* Current EL with SPx / FIQ */
+	.align 7
+	b	.
+
+	/* Current EL with SPx / SError */
+	.align 7
+	stp	x0, x1, [sp, #-16]!
+	stp	x2, x3, [sp, #-16]!
+	stp	x4, x5, [sp, #-16]!
+	stp	x6, x7, [sp, #-16]!
+	stp	x8, x9, [sp, #-16]!
+	stp	x10, x11, [sp, #-16]!
+	stp	x12, x13, [sp, #-16]!
+	stp	x14, x15, [sp, #-16]!
+	stp	x16, x17, [sp, #-16]!
+	stp	x18, x30, [sp, #-16]!
+
+	mov	x1, sp
+	mov	x0, #0 /* K_ERR_CPU_EXCEPTION */
+
+	b	z_arm64_fatal_error
+