Zephyr 1.6.0

Change-Id: Iccecc12218132ff1eae209d2dd17edaf71b94d5a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.checkpatch.conf

@@ -1,20 +1,22 @@
+--mailback
+--no-tree
 --emacs
 --summary-file
 --show-types
 --max-line-length=80
 --min-conf-desc-length=1
---typedefsfile=scripts/checkpatch/typedefsfile
 
 --ignore BRACES
 --ignore PRINTK_WITHOUT_KERN_LEVEL
 --ignore SPLIT_STRING
 --ignore VOLATILE
 --ignore CONFIG_EXPERIMENTAL
+--ignore PREFER_KERNEL_TYPES
 --ignore AVOID_EXTERNS
 --ignore NETWORKING_BLOCK_COMMENT_STYLE
 --ignore DATE_TIME
 --ignore MINMAX
 --ignore CONST_STRUCT
 --ignore FILE_PATH_CHANGES
---ignore SPDX_LICENSE_TAG
 --exclude ext
+--exclude net/ip/contiki

.clang-format

@@ -1,145 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# clang-format configuration file. Intended for clang-format >= 4.
-#
-# For more information, see:
-#
-#   Documentation/process/clang-format.rst
-#   https://clang.llvm.org/docs/ClangFormat.html
-#   https://clang.llvm.org/docs/ClangFormatStyleOptions.html
-#
----
-AccessModifierOffset: -4
-AlignAfterOpenBracket: Align
-AlignConsecutiveAssignments: false
-AlignConsecutiveDeclarations: false
-#AlignEscapedNewlines: Left # Unknown to clang-format-4.0
-AlignOperands: true
-AlignTrailingComments: false
-AllowAllParametersOfDeclarationOnNextLine: false
-AllowShortBlocksOnASingleLine: false
-AllowShortCaseLabelsOnASingleLine: false
-AllowShortFunctionsOnASingleLine: None
-AllowShortIfStatementsOnASingleLine: false
-AllowShortLoopsOnASingleLine: false
-AlwaysBreakAfterDefinitionReturnType: None
-AlwaysBreakAfterReturnType: None
-AlwaysBreakBeforeMultilineStrings: false
-AlwaysBreakTemplateDeclarations: false
-BinPackArguments: true
-BinPackParameters: true
-BraceWrapping:
-  AfterClass: false
-  AfterControlStatement: false
-  AfterEnum: false
-  AfterFunction: true
-  AfterNamespace: true
-  AfterObjCDeclaration: false
-  AfterStruct: false
-  AfterUnion: false
-  #AfterExternBlock: false # Unknown to clang-format-5.0
-  BeforeCatch: false
-  BeforeElse: false
-  IndentBraces: false
-  #SplitEmptyFunction: true # Unknown to clang-format-4.0
-  #SplitEmptyRecord: true # Unknown to clang-format-4.0
-  #SplitEmptyNamespace: true # Unknown to clang-format-4.0
-BreakBeforeBinaryOperators: None
-BreakBeforeBraces: Custom
-#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0
-BreakBeforeTernaryOperators: false
-BreakConstructorInitializersBeforeComma: false
-#BreakConstructorInitializers: BeforeComma # Unknown to clang-format-4.0
-BreakAfterJavaFieldAnnotations: false
-BreakStringLiterals: false
-ColumnLimit: 80
-CommentPragmas: '^ IWYU pragma:'
-#CompactNamespaces: false # Unknown to clang-format-4.0
-ConstructorInitializerAllOnOneLineOrOnePerLine: false
-ConstructorInitializerIndentWidth: 8
-ContinuationIndentWidth: 8
-Cpp11BracedListStyle: false
-DerivePointerAlignment: false
-DisableFormat: false
-ExperimentalAutoDetectBinPacking: false
-#FixNamespaceComments: false # Unknown to clang-format-4.0
-
-# Taken from:
-#   git grep -h '^#define [^[:space:]]*FOR_EACH[^[:space:]]*(' include/ \
-#   | sed "s,^#define \([^[:space:]]*FOR_EACH[^[:space:]]*\)(.*$,  - '\1'," \
-#   | sort | uniq
-ForEachMacros:
-  - 'FOR_EACH'
-  - 'FOR_EACH_FIXED_ARG'
-  - 'RB_FOR_EACH'
-  - 'RB_FOR_EACH_CONTAINER'
-  - 'SYS_DLIST_FOR_EACH_CONTAINER'
-  - 'SYS_DLIST_FOR_EACH_CONTAINER_SAFE'
-  - 'SYS_DLIST_FOR_EACH_NODE'
-  - 'SYS_DLIST_FOR_EACH_NODE_SAFE'
-  - 'SYS_SFLIST_FOR_EACH_CONTAINER'
-  - 'SYS_SFLIST_FOR_EACH_CONTAINER_SAFE'
-  - 'SYS_SFLIST_FOR_EACH_NODE'
-  - 'SYS_SFLIST_FOR_EACH_NODE_SAFE'
-  - 'SYS_SLIST_FOR_EACH_CONTAINER'
-  - 'SYS_SLIST_FOR_EACH_CONTAINER_SAFE'
-  - 'SYS_SLIST_FOR_EACH_NODE'
-  - 'SYS_SLIST_FOR_EACH_NODE_SAFE'
-  - 'Z_GENLIST_FOR_EACH_CONTAINER'
-  - 'Z_GENLIST_FOR_EACH_CONTAINER_SAFE'
-  - 'Z_GENLIST_FOR_EACH_NODE'
-  - 'Z_GENLIST_FOR_EACH_NODE_SAFE'
-  - '_WAIT_Q_FOR_EACH'
-
-#IncludeBlocks: Preserve # Unknown to clang-format-5.0
-IncludeCategories:
-  - Regex: '.*'
-    Priority: 1
-IncludeIsMainRegex: '(Test)?$'
-IndentCaseLabels: false
-#IndentPPDirectives: None # Unknown to clang-format-5.0
-IndentWidth: 8
-IndentWrappedFunctionNames: false
-JavaScriptQuotes: Leave
-JavaScriptWrapImports: true
-KeepEmptyLinesAtTheStartOfBlocks: false
-MacroBlockBegin: ''
-MacroBlockEnd: ''
-MaxEmptyLinesToKeep: 1
-NamespaceIndentation: Inner
-#ObjCBinPackProtocolList: Auto # Unknown to clang-format-5.0
-ObjCBlockIndentWidth: 8
-ObjCSpaceAfterProperty: true
-ObjCSpaceBeforeProtocolList: true
-
-# Taken from git's rules
-#PenaltyBreakAssignment: 10 # Unknown to clang-format-4.0
-PenaltyBreakBeforeFirstCallParameter: 30
-PenaltyBreakComment: 10
-PenaltyBreakFirstLessLess: 0
-PenaltyBreakString: 10
-PenaltyExcessCharacter: 100
-PenaltyReturnTypeOnItsOwnLine: 60
-
-PointerAlignment: Right
-ReflowComments: false
-SortIncludes: false
-#SortUsingDeclarations: false # Unknown to clang-format-4.0
-SpaceAfterCStyleCast: false
-SpaceAfterTemplateKeyword: true
-SpaceBeforeAssignmentOperators: true
-#SpaceBeforeCtorInitializerColon: true # Unknown to clang-format-5.0
-#SpaceBeforeInheritanceColon: true # Unknown to clang-format-5.0
-SpaceBeforeParens: ControlStatements
-#SpaceBeforeRangeBasedForLoopColon: true # Unknown to clang-format-5.0
-SpaceInEmptyParentheses: false
-SpacesBeforeTrailingComments: 1
-SpacesInAngles: false
-SpacesInContainerLiterals: false
-SpacesInCStyleCastParentheses: false
-SpacesInParentheses: false
-SpacesInSquareBrackets: false
-Standard: Cpp03
-TabWidth: 8
-UseTab: Always
-...

.codecov.yml

@@ -1,31 +0,0 @@
-codecov:
-  notify:
-    require_ci_to_pass: yes
-
-coverage:
-  precision: 2
-  round: down
-  range: "70...100"
-
-  status:
-    project: yes
-    patch: yes
-    changes: no
-
-#ignore:
-#  - "tests/**/*"
-#  - "samples/**/*"
-#  - "ext/hal/**/*"
-
-parsers:
-  gcov:
-    branch_detection:
-      conditional: yes
-      loop: yes
-      method: no
-      macro: no
-
-comment:
-  layout: "reach, diff, flags, files, footer"
-  behavior: default
-  require_changes: no

.editorconfig

@@ -1,67 +0,0 @@
-# EditorConfig: https://editorconfig.org/
-
-# top-most EditorConfig file
-root = true
-
-# All (Defaults)
-[*]
-charset = utf-8
-end_of_line = lf
-insert_final_newline = true
-trim_trailing_whitespace = true
-max_line_length = 80
-
-# Assembly
-[*.S]
-indent_style = tab
-indent_size = 8
-
-# C
-[*.{c,h}]
-indent_style = tab
-indent_size = 8
-
-# Python
-[*.py]
-indent_style = space
-indent_size = 4
-
-# Perl
-[*.pl]
-indent_style = tab
-indent_size = 8
-
-# YAML
-[*.{yml,yaml}]
-indent_style = space
-indent_size = 2
-
-# Shell Script
-[*.sh]
-indent_style = space
-indent_size = 4
-
-# Windows Command Script
-[*.cmd]
-end_of_line = crlf
-indent_style = tab
-indent_size = 8
-
-# Valgrind Suppression File
-[*.supp]
-indent_style = space
-indent_size = 3
-
-# CMake
-[{CMakeLists.txt,*.cmake}]
-indent_style = space
-indent_size = 2
-
-# Makefile
-[Makefile]
-indent_style = tab
-
-# Device tree
-[*.{dts,dtsi,overlay}]
-indent_style = tab
-indent_size = 8

.gitattributes

@@ -3,7 +3,3 @@
 .gitattributes export-ignore
 .gitignore export-ignore
 .mailmap export-ignore
-
-# Tell linguist that generated test pattern files should not be included in the
-# language statistics.
-*.pat linguist-generated=true

.github/ISSUE_TEMPLATE/bug_report.md

@@ -1,39 +0,0 @@
----
-name: Bug report
-about: Create a report to help us improve Zephyr
-title: ''
-labels: bug
-assignees: ''
-
----
-
-**Describe the bug**
-A clear and concise description of what the bug is.
-What have you tried to diagnose or workaround this issue?
-
-**To Reproduce**
-Steps to reproduce the behavior:
-1. mkdir build; cd build
-2. cmake -DBOARD=board\_xyz
-3. make
-4. See error
-
-**Expected behavior**
-A clear and concise description of what you expected to happen.
-
-**Impact**
-What impact does this issue have on your progress (e.g., annoyance, showstopper)
-
-**Screenshots or console output**
-If applicable, add a screenshot (drag-and-drop an image), or console logs
-(cut-and-paste text and put a code fence (\`\`\`) before and after, to help
-explain the issue.
-
-**Environment (please complete the following information):**
- - OS: (e.g. Linux, MacOS, Windows)
- - Toolchain (e.g Zephyr SDK, ...)
- - Commit SHA or Version used
-
-
-**Additional context**
-Add any other context about the problem here.

.github/ISSUE_TEMPLATE/enhancement.md

@@ -1,20 +0,0 @@
----
-name: Enhancement
-about: Suggest enhancements to existing features
-title: ''
-labels: Enhancement
-assignees: ''
-
----
-
-**Is your enhancement proposal related to a problem? Please describe.**
-A clear and concise description of what the problem is.
-
-**Describe the solution you'd like**
-A clear and concise description of what you want to happen.
-
-**Describe alternatives you've considered**
-A clear and concise description of any alternative solutions or features you've considered.
-
-**Additional context**
-Add any other context or graphics (drag-and-drop an image) about the feature request here.

.github/ISSUE_TEMPLATE/feature_request.md

@@ -1,20 +0,0 @@
----
-name: Feature request
-about: Suggest an idea for this project
-title: ''
-labels: feature request
-assignees: ''
-
----
-
-**Is your feature request related to a problem? Please describe.**
-A clear and concise description of what the problem is.
-
-**Describe the solution you'd like**
-A clear and concise description of what you want to happen.
-
-**Describe alternatives you've considered**
-A clear and concise description of any alternative solutions or features you've considered.
-
-**Additional context**
-Add any other context or graphics (drag-and-drop an image) about the feature request here.

.github/ISSUE_TEMPLATE/rfc---proposal.md

@@ -1,51 +0,0 @@
----
-name: RFC / Proposal
-about: Submit an RFC / Proposal
-title: ''
-labels: RFC
-assignees: ''
-
----
-
-## Introduction
-
-This section targets end users, TSC members, maintainers and anyone else that might
-need a quick explanation of your proposed change.
-
-### Problem description
-
-Why do we want this change and what problem are we trying to address?
-
-### Proposed change
-
-A brief summary of the proposed change - the 10,000 ft view on what it will
-change once this change is implemented.
-
-## Detailed RFC
-
-In this section of the document the target audience is the dev team. Upon
-reading this section each engineer should have a rather clear picture of what
-needs to be done in order to implement the described feature.
-
-### Proposed change (Detailed)
-
-This section is freeform - you should describe your change in as much detail
-as possible. Please also ensure to include any context or background info here.
-For example, do we have existing components which can be reused or altered.
-
-By reading this section, each team member should be able to know what exactly
-you're planning to change and how.
-
-### Dependencies
-
-Highlight how the change may affect the rest of the project (new components,
-modifications in other areas), or other teams/projects.
-
-### Concerns and Unresolved Questions
-
-List any concerns, unknowns, and generally unresolved questions etc.
-
-## Alternatives
-
-List any alternatives considered, and the reasons for choosing this option
-over them.

.github/license_config.yml

@@ -1,16 +0,0 @@
-license:
-  main: apache-2.0
-  report_missing: true
-  category: Permissive
-copyright:
-  check: true
-exclude:
-  extensions:
-    - yml
-    - yaml
-    - html
-    - rst
-    - conf
-    - cfg
-  langs:
-    - HTML

.github/workflows/doc-build.yml

@@ -1,65 +0,0 @@
-# Copyright (c) 2020 Linaro Limited.
-# SPDX-License-Identifier: Apache-2.0
-
-name: Documentation GitHub Workflow
-
-on: [pull_request]
-
-jobs:
-  build:
-    runs-on: ubuntu-latest
-
-    steps:
-    - name: Update PATH for west
-      run: |
-        echo "::add-path::$HOME/.local/bin"
-
-    - name: checkout
-      uses: actions/checkout@v2
-
-    - name: install-pkgs
-      run: |
-        sudo apt-get install -y ninja-build doxygen
-
-    - name: cache-pip
-      uses: actions/cache@v1
-      with:
-        path: ~/.cache/pip
-        key: ${{ runner.os }}-doc-pip
-
-    - name: install-pip
-      run: |
-        pip3 install setuptools
-        pip3 install 'breathe>=4.9.1,<4.15.0' 'docutils>=0.14' \
-                     'sphinx>=1.7.5,<3.0' sphinx_rtd_theme sphinx-tabs \
-                     sphinxcontrib-svg2pdfconverter 'west>=0.6.2'
-        pip3 install pyelftools canopen progress
-
-    - name: west setup
-      run: |
-        west init -l . || true
-
-    - name: build-docs
-      run: |
-        source zephyr-env.sh
-        make htmldocs
-        tar cvf htmldocs.tar --directory=./doc/_build html
-
-    - name: upload-build
-      uses: actions/upload-artifact@master
-      continue-on-error: True
-      with:
-        name: htmldocs.tar
-        path: htmldocs.tar
-
-    - name: check-warns
-      run: |
-        if [ -s doc/_build/doc.warnings ]; then
-           docwarn=$(cat doc/_build/doc.warnings)
-           docwarn="${docwarn//'%'/'%25'}"
-           docwarn="${docwarn//$'\n'/'%0A'}"
-           docwarn="${docwarn//$'\r'/'%0D'}"
-           # We treat doc warnings as errors
-           echo "::error file=doc.warnings::$docwarn"
-           exit 1
-        fi

.github/workflows/doc-publish.yml

@@ -1,112 +0,0 @@
-# Copyright (c) 2020 Linaro Limited.
-# SPDX-License-Identifier: Apache-2.0
-
-name: Doc build for Release or Daily
-
-# Either a daily based on schedule/cron or only on tag push
-on:
-  schedule:
-    - cron:  '50 22 * * *'
-  push:
-    tags:
-    - '*'
-
-jobs:
-  build:
-    runs-on: ubuntu-latest
-
-    steps:
-    - name: Update PATH for west
-      run: |
-        echo "::add-path::$HOME/.local/bin"
-
-    - name: Determine tag
-      id: tag
-      run: |
-        # We expect to get here either due to a schedule event in which
-        # case we are doing a daily build of the docs, or because a new
-        # tag was pushed, in which case we are building docs for a release
-        if [ ${GITHUB_EVENT_NAME} == "schedule" ]; then
-           echo ::set-output name=TYPE::daily;
-           echo ::set-output name=RELEASE::latest;
-        elif [ ${GITHUB_EVENT_NAME} == "push" ]; then
-           # If push due to a tag GITHUB_REF will look like refs/tags/TAG-FOO
-           # chop of 'refs/tags' so RELEASE=TAG-FOO
-           echo ::set-output name=TYPE::release;
-           echo ::set-output name=RELEASE::${GITHUB_REF/refs\/tags\//};
-        else
-           exit 1
-        fi
-
-    - name: Configure AWS Credentials
-      uses: aws-actions/configure-aws-credentials@v1
-      with:
-        aws-access-key-id: ${{ secrets.AWS_ACCESS_KEY_ID }}
-        aws-secret-access-key: ${{ secrets.AWS_SECRET_ACCESS_KEY }}
-        aws-region: us-east-1
-
-    - name: checkout
-      uses: actions/checkout@v2
-
-    - name: install-pkgs
-      run: |
-        sudo apt-get install -y ninja-build doxygen
-
-    - name: cache-pip
-      uses: actions/cache@v1
-      with:
-        path: ~/.cache/pip
-        key: ${{ runner.os }}-doc-pip
-
-    - name: install-pip
-      run: |
-        pip3 install setuptools
-        pip3 install 'breathe>=4.9.1,<4.15.0' 'docutils>=0.14' \
-                     'sphinx>=1.7.5,<3.0' sphinx_rtd_theme sphinx-tabs \
-                     sphinxcontrib-svg2pdfconverter 'west>=0.6.2'
-        pip3 install pyelftools
-
-    - name: west setup
-      run: |
-        west init -l . || true
-
-    - name: build-docs
-      env:
-        DOC_TAG: ${{ steps.tag.outputs.TYPE }}
-      run: |
-        source zephyr-env.sh
-        make DOC_TAG=${DOC_TAG} htmldocs
-
-    - name: check-warns
-      run: |
-        if [ -s doc/_build/doc.warnings ]; then
-           docwarn=$(cat doc/_build/doc.warnings)
-           docwarn="${docwarn//'%'/'%25'}"
-           docwarn="${docwarn//$'\n'/'%0A'}"
-           docwarn="${docwarn//$'\r'/'%0D'}"
-           # We treat doc warnings as errors
-           echo "::error file=doc.warnings::$docwarn"
-           exit 1
-        fi
-
-    - name: Upload to AWS S3
-      env:
-        RELEASE: ${{ steps.tag.outputs.RELEASE }}
-      run: |
-        echo "DOC_RELEASE=[$RELEASE]"
-        if [ "$RELEASE" == "latest" ]; then
-           export
-           echo "publish latest docs"
-           aws s3 sync  --quiet doc/_build/html s3://docs.zephyrproject.org/latest --delete
-           echo "success sync of latest docs"
-        else
-           DOC_RELEASE=${RELEASE}.0
-           echo "publish release docs: ${DOC_RELEASE}"
-           aws s3 sync  --quiet doc/_build/html s3://docs.zephyrproject.org/${DOC_RELEASE}
-           echo "success sync of rel docs"
-        fi
-        if [ -d doc/_build/doxygen/html ]; then
-           echo "publish doxygen"
-           aws s3 sync  --quiet doc/_build/doxygen/html s3://docs.zephyrproject.org/apidoc/${RELEASE} --delete
-           echo "success publish of doxygen"
-        fi

.github/workflows/license_check.yml

@@ -1,32 +0,0 @@
-name: Scancode
-
-on: [pull_request]
-
-jobs:
-  scancode_job:
-    runs-on: ubuntu-latest
-    name: Scan code for licenses
-    steps:
-    - name: Checkout the code
-      uses: actions/checkout@v1
-    - name: Scan the code
-      id: scancode
-      uses: zephyrproject-rtos/action_scancode@v3
-      with:
-        directory-to-scan: 'scan/'
-    - name: Artifact Upload
-      uses: actions/upload-artifact@v1
-      with:
-        name: scancode
-        path: ./artifacts
-
-    - name: Verify
-      run: |
-        if [ -s ./artifacts/report.txt ]; then
-          report=$(cat ./artifacts/report.txt)
-          report="${report//'%'/'%25'}"
-          report="${report//$'\n'/'%0A'}"
-          report="${report//$'\r'/'%0D'}"
-          echo "::error file=./artifacts/report.txt::$report"
-          exit 1
-        fi

.github/workflows/west_cmds.yml

@@ -1,65 +0,0 @@
-# Copyright (c) 2020 Linaro Limited.
-# SPDX-License-Identifier: Apache-2.0
-
-name: Zephyr West Command Tests
-
-on:
-  push:
-    paths:
-    - 'scripts/west-commands.yml'
-    - 'scripts/west_commands/**'
-  pull_request:
-    paths:
-    - 'scripts/west-commands.yml'
-    - 'scripts/west_commands/**'
-
-jobs:
-  build:
-    runs-on: ${{ matrix.os }}
-    strategy:
-      matrix:
-        python-version: [3.6, 3.7, 3.8]
-        os: [ubuntu-latest, macos-latest, windows-latest]
-    steps:
-    - name: checkout
-      uses: actions/checkout@v2
-    - name: Set up Python ${{ matrix.python-version }}
-      uses: actions/setup-python@v1
-      with:
-        python-version: ${{ matrix.python-version }}
-    - name: cache-pip-linux
-      if: startsWith(runner.os, 'Linux')
-      uses: actions/cache@v1
-      with:
-        path: ~/.cache/pip
-        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
-        restore-keys: |
-          ${{ runner.os }}-pip-${{ matrix.python-version }}
-    - name: cache-pip-mac
-      if: startsWith(runner.os, 'macOS')
-      uses: actions/cache@v1
-      with:
-        path: ~/Library/Caches/pip
-        # Trailing '-' was just to get a different cache name
-        key: ${{ runner.os }}-pip-${{ matrix.python-version }}-
-        restore-keys: |
-          ${{ runner.os }}-pip-${{ matrix.python-version }}-
-    - name: cache-pip-win
-      if: startsWith(runner.os, 'Windows')
-      uses: actions/cache@v1
-      with:
-        path: ~\AppData\Local\pip\Cache
-        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
-        restore-keys: |
-          ${{ runner.os }}-pip-${{ matrix.python-version }}
-    - name: install pytest
-      run: |
-        pip3 install pytest west pyelftools canopen progress
-    - name: run pytest-win
-      if: runner.os == 'Windows'
-      run: |
-        cmd /C "set PYTHONPATH=.\scripts\west_commands && pytest ./scripts/west_commands/tests/"
-    - name: run pytest-mac-linux
-      if: runner.os != 'Windows'
-      run: |
-        PYTHONPATH=./scripts/west_commands pytest ./scripts/west_commands/tests/

.gitignore

@@ -7,46 +7,24 @@
 *.swp
 *.swo
 *~
-build*/
-!doc/guides/build
-!tests/drivers/build_all
 cscope.*
 .dir
-
-/*.patch
-
-# The .cache directory will be used to cache toolchain capabilities if
-# no suitable out-of-tree directory is found.
-.cache
-
 outdir
 outdir-*
 scripts/basic/fixdep
 scripts/gen_idt/gen_idt
+scripts/gen_offset_header/gen_offset_header
+scripts/kconfig/conf
+scripts/kconfig/mconf
+scripts/kconfig/zconf.hash.c
+scripts/kconfig/zconf.lex.c
+scripts/kconfig/zconf.tab.c
 doc/_build
-doc/doxygen
 doc/xml
 doc/html
-doc/boards
-doc/samples
 doc/latex
-doc/themes/zephyr-docs-theme
-sanity-out*
-bsim_bt_out
+sanity-out/
 scripts/grub
-doc/reference/kconfig/*.rst
-doc/doc.warnings
-.*project
-.settings
-.envrc
-.vscode
-hide-defaults-note
-
-# Tag files
-GPATH
-GRTAGS
-GTAGS
-TAGS
+doc/reference/kconfig/CONFIG_*
+doc/reference/kconfig/index.rst
 tags
-
-.idea

.gitlint

@@ -1,57 +0,0 @@
-# All these sections are optional, edit this file as you like.
-[general]
-ignore=title-trailing-punctuation, T3, title-max-length, T1, body-hard-tab, B3, B1
-# verbosity should be a value between 1 and 3, the commandline -v flags take precedence over this
-verbosity = 3
-# By default gitlint will ignore merge commits. Set to 'false' to disable.
-ignore-merge-commits=true
-# Enable debug mode (prints more output). Disabled by default
-debug = false
-
-# Set the extra-path where gitlint will search for user defined rules
-# See http://jorisroovers.github.io/gitlint/user_defined_rules for details
-extra-path=scripts/gitlint
-
-[title-max-length-no-revert]
-line-length=75
-
-[body-min-line-count]
-min-line-count=1
-
-[body-max-line-count]
-max-line-count=200
-
-[title-starts-with-subsystem]
-regex = ^(?!subsys:)(([^:]+):)(\s([^:]+):)*\s(.+)$
-
-[title-must-not-contain-word]
-# Comma-separated list of words that should not occur in the title. Matching is case
-# insensitive. It's fine if the keyword occurs as part of a larger word (so "WIPING"
-# will not cause a violation, but "WIP: my title" will.
-words=wip
-
-[title-match-regex]
-# python like regex (https://docs.python.org/2/library/re.html) that the
-# commit-msg title must be matched to.
-# Note that the regex can contradict with other rules if not used correctly
-# (e.g. title-must-not-contain-word).
-#regex=^US[0-9]*
-
-[max-line-length-with-exceptions]
-# B1 = body-max-line-length
-line-length=72
-
-[body-min-length]
-min-length=3
-
-[body-is-missing]
-# Whether to ignore this rule on merge commits (which typically only have a title)
-# default = True
-ignore-merge-commits=false
-
-[body-changed-file-mention]
-# List of files that need to be explicitly mentioned in the body when they are changed
-# This is useful for when developers often erroneously edit certain files or git submodules.
-# By specifying this rule, developers can only change the file when they explicitly reference
-# it in the commit message.
-#files=gitlint/rules.py,README.md

.gitreview

@@ -0,0 +1,4 @@
+[gerrit]
+host=gerrit.zephyrproject.org
+port=29418
+project=zephyr.git

.known-issues/doc/bluetooth.conf

@@ -3,7 +3,7 @@
 #
 # FIXME: all these should match the relative filename
 #
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
 ^[ \t]*$
 ^[ \t]*\^$
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
@@ -15,7 +15,7 @@
 #
 # bt_gatt_discover_params unnamed struct definition
 #
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
@@ -27,7 +27,7 @@
 #
 # Bluetooth GATT unnamed struct definition
 #
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
@@ -36,33 +36,3 @@
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
 ^.*bt_gatt_read_params.__unnamed__.*
 ^[- \t]*\^
-#
-# Bluetooth mesh unnamed struct definition
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*bt_mesh_model.__unnamed__.*
-^[- \t]*\^
-#
-# Bluetooth mesh pub struct definition
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]bluetooth[/\\]mesh[/\\]access.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*bt_mesh_model_pub.*
-^[- \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*bt_mesh_model_pub.*
-^[- \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*bt_mesh_model_pub.*
-^[- \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*bt_mesh_model_pub.*
-^[- \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*bt_mesh_model_pub.*
-^[- \t]*\^

.known-issues/doc/crypto.conf

@@ -1,25 +0,0 @@
-#
-# crypto unnamed struct definition
-#doc/reference/crypto/index.rst
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]crypto[/\\]index.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*cipher_ctx.mode_params.*
-^[- \t]*\^
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]crypto[/\\]index.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*cipher_ctx.key.*
-^[- \t]*\^

.known-issues/doc/display.conf

@@ -1,15 +0,0 @@
-#
-# Display
-#
-#
-# include
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]display_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*mb_image.__unnamed__
-^[- \t]*\^

.known-issues/doc/duplicate.conf

@@ -1,6 +0,0 @@
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]file_system[/\\]index.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]dma.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]sensor.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)

.known-issues/doc/header_footer.conf

@@ -0,0 +1,18 @@
+#
+# KERNELVERSION not being defined in local builds, kill that warning,
+# can ignore it
+#
+^.*/Kconfig.zephyr:[0-9]+: warning: The symbol KERNELVERSION references the non-existent environment variable KERNELVERSION.*
+#
+# Documentation generation, early message
+#
+^cd .* && doxygen doc/doxygen.config
+^srctree=.* SRCARCH=\w+ python scripts/genrest/genrest.py .*$
+# This cuts the sphinx build line; has to be separate because in the
+# middle, we have removed the KERNELVERSION one and a full regex won't match
+^sphinx-build -t \w+ -b html -d [-._/\w]+  -q \. .*
+#
+# Documentation generation, footer message
+#
+^[ \t]*
+^Build finished. The HTML pages are in [-._/\w]+

.known-issues/doc/misc.conf

@@ -1,15 +0,0 @@
-#
-# Display
-#
-#
-# include
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]misc_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*json_obj_descr.__unnamed__
-^[- \t]*\^

.known-issues/doc/networking.conf

@@ -1,70 +0,0 @@
-#
-# Networking
-#
-#
-# include/net/net_ip.h warnings
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*in[_6]+addr.in[46]_u
-^[- \t]*\^
-#
-# include/net/net_mgmt.h
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*net_mgmt_event_callback.__unnamed__
-^[- \t]*\^
-#
-# include/net/buf.h
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*net_buf.__unnamed__
-^[- \t]*\^
-#
-# include/net/ieee802154.h
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*ieee802154_req_params.__unnamed__
-^[- \t]*\^
-#
-# include/net/net_context.h
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]networking[/\\]net_context.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*net_context.options
-^[- \t]*\^
-#
-# include/net/net_stats.h
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]networking[/\\]net_stats.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*net_stats_tc.[a-z]+
-^[- \t]*\^
-#
-# stray duplicate definition warnings
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]networking[/\\]net_if.rst):(?P<lineno>[0-9]+): WARNING: Duplicate declaration(.*)

.known-issues/doc/sensor.conf

@@ -0,0 +1,12 @@
+#
+# Sensor value unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*sensor_value.__unnamed__.*
+^[- \t]*\^

.known-issues/doc/uart.conf

@@ -1,7 +1,7 @@
 #
 # UART unnamed struct definition
-#doc/api/peripherals/uart.rst
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]uart.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+#
+^(?P<filename>[-._/\w]+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
 ^[ \t]*
 ^[ \t]*\^
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
@@ -13,19 +13,3 @@
 ^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
 ^.*uart_device_config.__unnamed__.*
 ^[- \t]*\^
-#
-^(?P<filename>([\-:\\/\w\.])+[/\\]doc[/\\]reference[/\\]peripherals[/\\]uart.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
-^[ \t]*
-^[ \t]*\^
-^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
-^.*uart_event.data
-^[- \t]*\^

.mailmap

@@ -18,15 +18,3 @@ Keren Siman-Tov <keren.siman-tov@intel.com> <keren.siman-tov@intel.com>
 Naga Raja Rao Tulasi <tulasi.r@tcs.com> <tulasi.r@tcs.com>
 Felipe Neves <ryukokki.felipe@gmail.com> <ryukokki.felipe@gmail.com>
 Amir Kaplan <amir.kaplan@intel.com> <amir.kaplan@intel.com>
-Anas Nashif <anas.nashif@intel.com> <anas.nashif@intel.com>
-Ruud Derwig <Ruud.Derwig@synopsys.com> <Ruud.Derwig@synopsys.com>
-Flavio Arieta Netto <flavio@exati.com.br>
-Nishikant Nayak <nishikantax.nayak@intel.com>
-Justin Watson <jwatson5@gmail.com>
-Johann Fischer <j.fischer@phytec.de>
-Jun Li <jun.r.li@intel.com>
-Xiaorui Hu <xiaorui.hu@linaro.org>
-Yannis Damigos <giannis.damigos@gmail.com> <ydamigos@iccs.gr>
-Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no> <vinayak.kariappa.chettimada@nordicsemi.no> <vich@nordicsemi.no> <vinayak.kariappa@gmail.com>
-Sean Nyekjaer <sean@geanix.com> <sean.nyekjaer@prevas.dk>
-Sean Nyekjaer <sean@geanix.com> <sean@nyekjaer.dk>

.shippable.yml

@@ -1,75 +0,0 @@
-language: c
-
-compiler: gcc
-
-env:
-    global:
-        - ZEPHYR_SDK_INSTALL_DIR=/opt/sdk/zephyr-sdk-0.11.3
-        - ZEPHYR_TOOLCHAIN_VARIANT=zephyr
-        - MATRIX_BUILDS="5"
-    matrix:
-        - MATRIX_BUILD="1"
-        - MATRIX_BUILD="2"
-        - MATRIX_BUILD="3"
-        - MATRIX_BUILD="4"
-        - MATRIX_BUILD="5"
-
-build:
-    cache: false
-    cache_dir_list:
-        - ${SHIPPABLE_BUILD_DIR}/ccache
-    pre_ci_boot:
-        image_name: zephyrprojectrtos/ci
-        image_tag: v0.11.8
-        pull: true
-        options: "-e HOME=/home/buildslave --privileged=true --tty --net=bridge --user buildslave"
-
-    ci:
-      - export CCACHE_DIR=${SHIPPABLE_BUILD_DIR}/ccache/.ccache
-      - >
-        if [ "$IS_PULL_REQUEST" = "true" ]; then
-          ./scripts/ci/run_ci.sh -c -b ${PULL_REQUEST_BASE_BRANCH} -r origin -m ${MATRIX_BUILD} -M ${MATRIX_BUILDS} -p ${PULL_REQUEST};
-        else
-          ./scripts/ci/run_ci.sh -c -b ${BRANCH} -r origin -m ${MATRIX_BUILD} -M ${MATRIX_BUILDS};
-        fi;
-      - ccache -s
-    on_failure:
-      - >
-        if [ "$IS_PULL_REQUEST" = "true" ]; then
-          ./scripts/ci/run_ci.sh -f -b ${PULL_REQUEST_BASE_BRANCH} -r origin -m ${MATRIX_BUILD} -M ${MATRIX_BUILDS} -p ${PULL_REQUEST};
-        else
-          ./scripts/ci/run_ci.sh -f -b ${BRANCH} -r origin -m ${MATRIX_BUILD} -M ${MATRIX_BUILDS};
-        fi;
-    on_success:
-      - >
-        if [ "$IS_PULL_REQUEST" = "true" ]; then
-          ./scripts/ci/run_ci.sh -s -b ${PULL_REQUEST_BASE_BRANCH} -r origin -m ${MATRIX_BUILD} -M ${MATRIX_BUILDS} -p ${PULL_REQUEST};
-        else
-          ./scripts/ci/run_ci.sh -s -b ${BRANCH} -r origin -m ${MATRIX_BUILD} -M ${MATRIX_BUILDS};
-        fi;
-branches:
-  only:
-    - master
-    - v*-branch
-    - topic-*
-integrations:
-  notifications:
-    - integrationName: slack_integration
-      type: slack
-      recipients:
-        - "#ci"
-      branches:
-        only:
-          - master
-      on_success: never
-      on_failure: never
-    - integrationName: email
-      type: email
-      recipients:
-        - builds@zephyrproject.org
-      branches:
-        only:
-          - master
-      on_success: never
-      on_failure: always
-      on_pull_request: never

.uncrustify.cfg

@@ -1,80 +0,0 @@
-indent_with_tabs    = 2     # 1=indent to level only, 2=indent with tabs
-input_tab_size      = 8     # original tab size
-output_tab_size     = 8     # new tab size
-indent_columns      = output_tab_size
-indent_label        = 1     # pos: absolute col, neg: relative column
-indent_switch_case  = 0     # number
-
-#
-# inter-symbol newlines
-#
-
-nl_enum_brace       = remove    # "enum {" vs "enum \n {"
-nl_union_brace      = remove    # "union {" vs "union \n {"
-nl_struct_brace     = remove    # "struct {" vs "struct \n {"
-nl_do_brace         = remove    # "do {" vs "do \n {"
-nl_if_brace         = remove    # "if () {" vs "if () \n {"
-nl_for_brace        = remove    # "for () {" vs "for () \n {"
-nl_else_brace       = remove    # "else {" vs "else \n {"
-nl_while_brace      = remove    # "while () {" vs "while () \n {"
-nl_switch_brace     = remove    # "switch () {" vs "switch () \n {"
-nl_brace_while      = remove    # "} while" vs "} \n while" - cuddle while
-nl_brace_else       = remove    # "} \n else" vs "} else"
-nl_func_var_def_blk = 1
-nl_fcall_brace      = remove    # "list_for_each() {" vs "list_for_each()\n{"
-nl_fdef_brace       = add       # "int foo() {" vs "int foo()\n{"
-
-#
-# Source code modifications
-#
-
-mod_paren_on_return = ignore    # "return 1;" vs "return (1);"
-mod_full_brace_if   = add       # "if() { } else { }" vs "if() else"
-
-#
-# inter-character spacing options
-#
-
-sp_sizeof_paren     = remove    # "sizeof (int)" vs "sizeof(int)"
-sp_before_sparen    = force     # "if (" vs "if("
-sp_after_sparen     = force     # "if () {" vs "if (){"
-sp_inside_braces    = add       # "{ 1 }" vs "{1}"
-sp_inside_braces_struct = add   # "{ 1 }" vs "{1}"
-sp_inside_braces_enum   = add   # "{ 1 }" vs "{1}"
-sp_assign           = add
-sp_arith            = add
-sp_bool             = add
-sp_compare          = add
-sp_assign           = add
-sp_after_comma      = add
-sp_func_def_paren   = remove    # "int foo (){" vs "int foo(){"
-sp_func_call_paren  = remove    # "foo (" vs "foo("
-sp_func_proto_paren = remove    # "int foo ();" vs "int foo();"
-sp_inside_fparen    = remove    # "func( arg )" vs "func(arg)"
-sp_else_brace       = add       # ignore/add/remove/force
-sp_before_ptr_star  = add       # ignore/add/remove/force
-sp_after_ptr_star   = remove    # ignore/add/remove/force
-sp_between_ptr_star = remove    # ignore/add/remove/force
-sp_inside_paren     = remove    # remove spaces inside parens
-sp_paren_paren      = remove    # remove spaces between nested parens
-sp_inside_sparen    = remove    # remove spaces inside parens for if, while and the like
-sp_brace_else       = add       # ignore/add/remove/force
-sp_before_nl_cont   = ignore
-sp_cmt_cpp_start    = add
-sp_brace_typedef    = add       # }typedefd_name -> } typedefd_name
-
-cmt_sp_after_star_cont          = 1
-#
-# Aligning stuff
-#
-
-align_with_tabs     = FALSE     # use tabs to align
-align_on_tabstop    = TRUE      # align on tabstops
-align_enum_equ_span = 4         # '=' in enum definition
-align_struct_init_span  = 0     # align stuff in a structure init '= { }'
-align_right_cmt_span    = 3
-align_nl_cont	    = TRUE
-
-
-
-sp_pp_concat                              = ignore      # ignore/add/remove/force

CODEOWNERS

@@ -1,508 +0,0 @@
-# CODEOWNERS for autoreview assigning in github
-
-# https://help.github.com/en/articles/about-code-owners#codeowners-syntax
-
-# Order is important; for each modified file, the last matching
-# pattern takes the most precedence.
-# That is, with the last pattern being
-# *.rst                                     @nashif
-# if only .rst files are being modified, only nashif is
-# automatically requested for review, but you can manually
-# add others as needed.
-
-# Do not use wildcard on all source yet
-# *                                        @galak @nashif
-
-/.known-issues/                           @nashif
-/.github/				  @nashif
-/.github/workflows/                       @galak @nashif
-/arch/arc/                                @vonhust @ruuddw
-/arch/arm/                                @MaureenHelm @galak @ioannisg
-/arch/arm/core/aarch32/cortex_m/cmse/     @ioannisg
-/arch/arm/core/aarch64/                   @carlocaione
-/arch/arm/include/aarch32/cortex_m/cmse.h @ioannisg
-/arch/arm/include/aarch64/                @carlocaione
-/arch/arm/core/aarch32/cortex_a_r/        @MaureenHelm @galak @ioannisg @bbolen @stephanosio
-/arch/common/                             @andrewboie @ioannisg @andyross
-/soc/arc/snps_*/                          @vonhust @ruuddw
-/soc/nios2/                               @nashif @wentongwu
-/soc/arm/                                 @MaureenHelm @galak @ioannisg
-/soc/arm/arm/mps2/                        @fvincenzo
-/soc/arm/atmel_sam/sam3x/                 @ioannisg
-/soc/arm/atmel_sam/sam4e/                 @nandojve
-/soc/arm/atmel_sam/sam4s/                 @fallrisk
-/soc/arm/atmel_sam/same70/                @nandojve
-/soc/arm/atmel_sam/samv71/                @nandojve
-/soc/arm/bcm*/                            @sbranden
-/soc/arm/infineon_xmc/                    @parthitce
-/soc/arm/nxp*/                            @MaureenHelm
-/soc/arm/nordic_nrf/                      @ioannisg
-/soc/arm/qemu_cortex_a53/                 @carlocaione
-/soc/arm/st_stm32/                        @erwango
-/soc/arm/st_stm32/stm32f4/                @idlethread
-/soc/arm/st_stm32/stm32mp1/               @arnopo
-/soc/arm/ti_simplelink/cc13x2_cc26x2/     @bwitherspoon
-/soc/arm/ti_simplelink/cc32xx/            @vanti
-/soc/arm/ti_simplelink/msp432p4xx/        @Mani-Sadhasivam
-/soc/arm/xilinx_zynqmp/                   @stephanosio
-/soc/xtensa/intel_s1000/                  @sathishkuttan @dcpleung
-/arch/x86/                                @andrewboie
-/arch/nios2/                              @andrewboie @wentongwu
-/arch/posix/                              @aescolar @daor-oti
-/arch/riscv/                              @kgugala @pgielda @nategraff-sifive
-/soc/posix/                               @aescolar @daor-oti
-/soc/riscv/                               @kgugala @pgielda @nategraff-sifive
-/soc/riscv/openisa*/                      @MaureenHelm
-/soc/x86/                                 @andrewboie
-/arch/xtensa/                             @andrewboie @dcpleung @andyross
-/soc/xtensa/                              @andrewboie @dcpleung @andyross
-/boards/arc/                              @vonhust @ruuddw
-/boards/arm/                              @MaureenHelm @galak
-/boards/arm/96b_argonkey/                 @avisconti
-/boards/arm/96b_avenger96/                @Mani-Sadhasivam
-/boards/arm/96b_carbon/                   @idlethread
-/boards/arm/96b_meerkat96/                @Mani-Sadhasivam
-/boards/arm/96b_nitrogen/                 @idlethread
-/boards/arm/96b_neonkey/                  @Mani-Sadhasivam
-/boards/arm/96b_stm32_sensor_mez/         @Mani-Sadhasivam
-/boards/arm/96b_wistrio/                  @Mani-Sadhasivam
-/boards/arm/arduino_due/                  @ioannisg
-/boards/arm/cc1352r1_launchxl/            @bwitherspoon
-/boards/arm/cc26x2r1_launchxl/            @bwitherspoon
-/boards/arm/cc3220sf_launchxl/            @vanti
-/boards/arm/disco_l475_iot1/              @erwango
-/boards/arm/frdm*/                        @MaureenHelm
-/boards/arm/frdm*/doc/                    @MaureenHelm @MeganHansen
-/boards/arm/google_*/                     @jackrosenthal
-/boards/arm/hexiwear*/                    @MaureenHelm
-/boards/arm/hexiwear*/doc/                @MaureenHelm @MeganHansen
-/boards/arm/ip_k66f/                      @parthitce
-/boards/arm/lpcxpresso*/                  @MaureenHelm
-/boards/arm/lpcxpresso*/doc/              @MaureenHelm @MeganHansen
-/boards/arm/mimxrt*/                      @MaureenHelm
-/boards/arm/mimxrt*/doc/                  @MaureenHelm @MeganHansen
-/boards/arm/mps2_an385/                   @fvincenzo
-/boards/arm/msp_exp432p401r_launchxl/     @Mani-Sadhasivam
-/boards/arm/nrf*/                         @carlescufi @lemrey @ioannisg
-/boards/arm/nucleo*/                      @erwango
-/boards/arm/nucleo_f401re/                @idlethread
-/boards/arm/qemu_cortex_a53/              @carlocaione
-/boards/arm/qemu_cortex_r*/               @stephanosio
-/boards/arm/qemu_cortex_m*/               @ioannisg
-/boards/arm/xmc45_relax_kit/              @parthitce
-/boards/arm/sam4e_xpro/                   @nandojve
-/boards/arm/sam4s_xplained/               @fallrisk
-/boards/arm/sam_e70_xplained/             @nandojve
-/boards/arm/sam_v71_xult/                 @nandojve
-/boards/arm/v2m_beetle/                   @fvincenzo
-/boards/arm/olimexino_stm32/              @ydamigos
-/boards/arm/sensortile_box/               @avisconti
-/boards/arm/steval_fcu001v1/              @Navin-Sankar
-/boards/arm/stm32l1_disco/                @karlp
-/boards/arm/stm32*_disco/                 @erwango
-/boards/arm/stm32f3_disco/                @ydamigos
-/boards/arm/stm32*_eval/                  @erwango
-/boards/common/                           @mbolivar-nordic
-/boards/deprecated.cmake                  @tejlmand
-/boards/nios2/                            @wentongwu
-/boards/nios2/altera_max10/               @wentongwu
-/boards/arm/stm32_min_dev/                @cbsiddharth
-/boards/posix/                            @aescolar @daor-oti
-/boards/posix/nrf52_bsim/                 @aescolar @wopu-ot
-/boards/riscv/                            @kgugala @pgielda @nategraff-sifive
-/boards/riscv/rv32m1_vega/                @MaureenHelm
-/boards/shields/                          @erwango
-/boards/x86/                              @andrewboie @nashif
-/boards/xtensa/                           @nashif @dcpleung
-/boards/xtensa/intel_s1000_crb/           @sathishkuttan @dcpleung
-/boards/xtensa/odroid_go/                 @ydamigos
-# All cmake related files
-/cmake/                                   @tejlmand @nashif
-/CMakeLists.txt                           @tejlmand @nashif
-/doc/                                     @dbkinder
-/doc/guides/coccinelle.rst                @himanshujha199640 @JuliaLawall
-/doc/CMakeLists.txt                       @carlescufi
-/doc/scripts/                             @carlescufi
-/doc/guides/bluetooth/                    @joerchan @jhedberg @Vudentz
-/doc/guides/dts/                          @galak @mbolivar-nordic
-/doc/reference/bluetooth/                 @joerchan @jhedberg @Vudentz
-/doc/reference/devicetree/                @galak @mbolivar-nordic
-/doc/reference/resource_management/       @pabigot
-/doc/reference/networking/can*            @alexanderwachter
-/drivers/debug/                           @nashif
-/drivers/*/*cc13xx_cc26xx*                @bwitherspoon
-/drivers/*/*mcux*                         @MaureenHelm
-/drivers/*/*stm32*                        @erwango
-/drivers/*/*native_posix*                 @aescolar @daor-oti
-/drivers/adc/                             @anangl
-/drivers/adc/adc_stm32.c                  @cybertale
-/drivers/bluetooth/                       @joerchan @jhedberg @Vudentz
-/drivers/can/                             @alexanderwachter
-/drivers/can/*mcp2515*                    @karstenkoenig
-/drivers/clock_control/*nrf*              @nordic-krch
-/drivers/counter/                         @nordic-krch
-/drivers/console/semihost_console.c       @luozhongyao
-/drivers/counter/counter_cmos.c           @andrewboie
-/drivers/counter/maxim_ds3231.c           @pabigot
-/drivers/crypto/*nrf_ecb*                 @maciekfabia @anangl
-/drivers/console/*mux*                    @jukkar
-/drivers/display/                         @vanwinkeljan
-/drivers/display/display_framebuf.c       @andrewboie
-/drivers/dac/                             @martinjaeger
-/drivers/dma/*dw*                         @tbursztyka
-/drivers/dma/*sam0*                       @Sizurka
-/drivers/dma/dma_stm32*                   @cybertale
-/drivers/eeprom/                          @henrikbrixandersen
-/drivers/eeprom/eeprom_stm32.c            @KwonTae-young
-/drivers/entropy/*rv32m1*                 @MaureenHelm
-/drivers/entropy/*gecko*                  @chrta
-/drivers/espi/                            @albertofloyd @franciscomunoz @scottwcpg
-/drivers/ps2/                             @albertofloyd @franciscomunoz @scottwcpg
-/drivers/kscan/                           @albertofloyd @franciscomunoz @scottwcpg
-/drivers/peci/                            @albertofloyd @franciscomunoz @scottwcpg
-/drivers/ethernet/                        @jukkar @tbursztyka @pfalcon
-/drivers/entropy/*litex*                  @mateusz-holenko @kgugala @pgielda
-/drivers/flash/                           @nashif @nvlsianpu
-/drivers/flash/*nrf*                      @nvlsianpu
-/drivers/flash/*spi_nor*                  @pabigot
-/drivers/flash/*stm32*                    @superna9999
-/drivers/gpio/                            @mnkp @pabigot
-/drivers/gpio/*ht16k33*                   @henrikbrixandersen
-/drivers/gpio/*lmp90xxx*                  @henrikbrixandersen
-/drivers/gpio/*stm32*                     @erwango
-/drivers/gpio/*sx1509b*                   @pabigot
-/drivers/gpio/*litex*                     @mateusz-holenko @kgugala @pgielda
-/drivers/hwinfo/                          @alexanderwachter
-/drivers/i2c/*litex*                      @mateusz-holenko @kgugala @pgielda
-/drivers/i2s/i2s_ll_stm32*                @avisconti
-/drivers/i2c/i2c_shell.c                  @nashif
-/drivers/ieee802154/                      @jukkar @tbursztyka
-/drivers/ieee802154/ieee802154_rf2xx*     @jukkar @tbursztyka @nandojve
-/drivers/interrupt_controller/            @andrewboie
-/drivers/interrupt_controller/intc_gic.c  @stephanosio
-/drivers/*/intc_vexriscv_litex.c          @mateusz-holenko @kgugala @pgielda
-/drivers/ipm/ipm_mhu*                     @karl-zh
-/drivers/ipm/Kconfig.nrfx                 @masz-nordic @ioannisg
-/drivers/ipm/Kconfig.nrfx_ipc_channel     @masz-nordic @ioannisg
-/drivers/ipm/ipm_cavs_idc*                @dcpleung
-/drivers/ipm/ipm_nrfx_ipc.c               @masz-nordic @ioannisg
-/drivers/ipm/ipm_nrfx_ipc.h               @masz-nordic @ioannisg
-/drivers/ipm/ipm_stm32_ipcc.c             @arnopo
-/drivers/led/                             @Mani-Sadhasivam
-/drivers/led_strip/                       @mbolivar-nordic
-/drivers/lora/                            @Mani-Sadhasivam
-/drivers/modem/                           @mike-scott
-/drivers/pcie/                            @andrewboie
-/drivers/pinmux/stm32/                    @idlethread
-/drivers/pinmux/*hsdk*                    @iriszzw
-/drivers/pwm/*litex*                      @mateusz-holenko @kgugala @pgielda
-/drivers/sensor/                          @MaureenHelm
-/drivers/sensor/ams_iAQcore/              @alexanderwachter
-/drivers/sensor/ens210/                   @alexanderwachter
-/drivers/sensor/hts*/                     @avisconti
-/drivers/sensor/lis*/                     @avisconti
-/drivers/sensor/lps*/                     @avisconti
-/drivers/sensor/lsm*/                     @avisconti
-/drivers/sensor/st*/                      @avisconti
-/drivers/serial/uart_altera_jtag_hal.c    @wentongwu
-/drivers/serial/*ns16550*                 @andrewboie
-/drivers/serial/*nrfx*                    @Mierunski @anangl
-/drivers/serial/Kconfig.litex             @mateusz-holenko @kgugala @pgielda
-/drivers/serial/uart_liteuart.c           @mateusz-holenko @kgugala @pgielda
-/drivers/serial/Kconfig.rtt               @carlescufi @pkral78
-/drivers/serial/uart_rtt.c                @carlescufi @pkral78
-/drivers/serial/Kconfig.xlnx              @wjliang
-/drivers/serial/uart_xlnx_ps.c            @wjliang
-/drivers/serial/*xmc4xxx*                 @parthitce
-/drivers/net/                             @jukkar @tbursztyka
-/drivers/ptp_clock/                       @jukkar
-/drivers/pwm/*rv32m1*                     @henrikbrixandersen
-/drivers/pwm/pwm_shell.c                  @henrikbrixandersen
-/drivers/spi/                             @tbursztyka
-/drivers/spi/spi_ll_stm32.*               @superna9999
-/drivers/spi/spi_rv32m1_lpspi*            @karstenkoenig
-/drivers/timer/apic_timer.c               @andrewboie
-/drivers/timer/arm_arch_timer.c           @carlocaione
-/drivers/timer/cortex_m_systick.c         @ioannisg
-/drivers/timer/altera_avalon_timer_hal.c  @wentongwu
-/drivers/timer/riscv_machine_timer.c      @nategraff-sifive @kgugala @pgielda
-/drivers/timer/litex_timer.c              @mateusz-holenko @kgugala @pgielda
-/drivers/timer/xlnx_psttc_timer*          @wjliang @stephanosio
-/drivers/timer/cc13x2_cc26x2_rtc_timer.c  @vanti
-/drivers/timer/cavs_timer.c               @dcpleung
-/drivers/usb/                             @jfischer-phytec-iot @finikorg
-/drivers/usb/device/usb_dc_stm32.c        @ydamigos @loicpoulain
-/drivers/video/                           @loicpoulain
-/drivers/i2c/i2c_ll_stm32*                @ldts @ydamigos
-/drivers/i2c/i2c_rv32m1_lpi2c*            @henrikbrixandersen
-/drivers/i2c/*sam0*                       @Sizurka
-/drivers/i2c/i2c_dw*                      @dcpleung
-/drivers/*/*xec*                          @franciscomunoz @albertofloyd @scottwcpg
-/drivers/watchdog/*gecko*                 @oanerer
-/drivers/watchdog/wdt_handlers.c          @andrewboie
-/drivers/wifi/                            @jukkar @tbursztyka @pfalcon
-/drivers/wifi/eswifi/                     @loicpoulain
-/dts/arc/                                 @vonhust @ruuddw @iriszzw
-/dts/arm/atmel/sam4e*                     @nandojve
-/dts/arm/atmel/samr21.dtsi                @benpicco
-/dts/arm/atmel/sam*5*.dtsi                @benpicco
-/dts/arm/atmel/same70*                    @nandojve
-/dts/arm/atmel/samv71*                    @nandojve
-/dts/arm/atmel/                           @galak
-/dts/arm/broadcom/                        @sbranden
-/dts/arm/infineon/                        @parthitce
-/dts/arm/qemu-virt/                       @carlocaione
-/dts/arm/st/                              @erwango
-/dts/arm/ti/cc13?2*                       @bwitherspoon
-/dts/arm/ti/cc26?2*                       @bwitherspoon
-/dts/arm/ti/cc3235*                       @vanti
-/dts/arm/nordic/                          @ioannisg @carlescufi
-/dts/arm/nxp/                             @MaureenHelm
-/dts/arm/microchip/                       @franciscomunoz @albertofloyd @scottwcpg
-/dts/arm/silabs/efm32gg11b*               @oanerer
-/dts/arm/silabs/efm32_jg_pg*              @chrta
-/dts/arm/silabs/efr32bg13p*               @mnkp
-/dts/arm/silabs/efm32jg12b*               @chrta
-/dts/arm/silabs/efm32pg12b*               @chrta
-/dts/riscv/microsemi-miv.dtsi             @galak
-/dts/riscv/rv32m1*                        @MaureenHelm
-/dts/riscv/riscv32-fe310.dtsi             @nategraff-sifive
-/dts/riscv/riscv32-litex-vexriscv.dtsi    @mateusz-holenko @kgugala @pgielda
-/dts/arm/armv7-r.dtsi                     @bbolen @stephanosio
-/dts/arm/armv8-a.dtsi                     @carlocaione
-/dts/arm/xilinx/                          @bbolen @stephanosio
-/dts/xtensa/xtensa.dtsi                   @ydamigos
-/dts/xtensa/intel/                        @dcpleung
-/dts/bindings/                            @galak
-/dts/bindings/can/                        @alexanderwachter
-/dts/bindings/iio/adc/st*stm32-adc.yaml   @cybertale
-/dts/bindings/serial/ns16550.yaml         @andrewboie
-/dts/bindings/*/nordic*                   @anangl
-/dts/bindings/*/nxp*                      @MaureenHelm
-/dts/bindings/*/openisa*                  @MaureenHelm
-/dts/bindings/*/st*                       @erwango
-/dts/bindings/sensor/ams*                 @alexanderwachter
-/dts/bindings/*/sifive*                   @mateusz-holenko @kgugala @pgielda @nategraff-sifive
-/dts/bindings/*/litex*                    @mateusz-holenko @kgugala @pgielda
-/dts/bindings/*/vexriscv*                 @mateusz-holenko @kgugala @pgielda
-/dts/posix/                               @aescolar @vanwinkeljan @daor-oti
-/dts/bindings/sensor/*bme680*             @BoschSensortec
-/dts/bindings/sensor/st*                  @avisconti
-/include/                                 @nashif @carlescufi @galak @MaureenHelm
-/include/drivers/adc.h                    @anangl
-/include/drivers/can.h                    @alexanderwachter
-/include/drivers/counter.h                @nordic-krch
-/include/drivers/dac.h                    @martinjaeger
-/include/drivers/display.h                @vanwinkeljan
-/include/drivers/espi.h                   @albertofloyd @franciscomunoz @scottwcpg
-/include/drivers/bluetooth/               @joerchan @jhedberg @Vudentz
-/include/drivers/flash.h                  @nashif @carlescufi @galak @MaureenHelm @nvlsianpu
-/include/drivers/led/ht16k33.h            @henrikbrixandersen
-/include/drivers/interrupt_controller/    @andrewboie
-/include/drivers/interrupt_controller/gic.h @stephanosio
-/include/drivers/pcie/                    @andrewboie
-/include/drivers/hwinfo.h                 @alexanderwachter
-/include/drivers/led.h                    @Mani-Sadhasivam
-/include/drivers/led_strip.h              @mbolivar-nordic
-/include/drivers/sensor.h                 @MaureenHelm
-/include/drivers/spi.h                    @tbursztyka
-/include/drivers/lora.h                   @Mani-Sadhasivam
-/include/drivers/peci.h                   @albertofloyd @franciscomunoz @scottwcpg
-/include/app_memory/                      @andrewboie
-/include/arch/arc/                        @vonhust @ruuddw
-/include/arch/arc/arch.h                  @andrewboie
-/include/arch/arc/v2/irq.h                @andrewboie
-/include/arch/arm/aarch32/                @MaureenHelm @galak @ioannisg
-/include/arch/arm/aarch32/cortex_a_r/     @stephanosio
-/include/arch/arm/aarch64/                @carlocaione
-/include/arch/arm/aarch32/irq.h           @andrewboie
-/include/arch/nios2/                      @andrewboie
-/include/arch/nios2/arch.h                @andrewboie
-/include/arch/posix/                      @aescolar @daor-oti
-/include/arch/riscv/                      @nategraff-sifive @kgugala @pgielda
-/include/arch/x86/                        @andrewboie @wentongwu
-/include/arch/common/                     @andrewboie @andyross @nashif
-/include/arch/xtensa/                     @andrewboie
-/include/sys/atomic.h                     @andrewboie @andyross
-/include/bluetooth/                       @joerchan @jhedberg @Vudentz
-/include/cache.h                          @andrewboie @andyross
-/include/canbus/                          @alexanderwachter
-/include/tracing/                         @wentongwu @nashif
-/include/debug/                           @nashif
-/include/device.h                         @wentongwu @nashif
-/include/devicetree.h                     @galak
-/include/display/                         @vanwinkeljan
-/include/dt-bindings/clock/kinetis_mcg.h  @henrikbrixandersen
-/include/dt-bindings/clock/kinetis_scg.h  @henrikbrixandersen
-/include/dt-bindings/dma/stm32_dma.h      @cybertale
-/include/dt-bindings/pcie/                @andrewboie
-/include/dt-bindings/usb/usb.h            @galak @finikorg
-/include/fs/                              @nashif @wentongwu
-/include/init.h                           @andrewboie @andyross
-/include/irq.h                            @andrewboie @andyross
-/include/irq_offload.h                    @andrewboie @andyross
-/include/kernel.h                         @andrewboie @andyross
-/include/kernel_version.h                 @andrewboie @andyross
-/include/linker/app_smem*.ld              @andrewboie
-/include/linker/                          @andrewboie @andyross
-/include/logging/                         @nordic-krch
-/include/net/                             @jukkar @tbursztyka @pfalcon
-/include/net/buf.h                        @jukkar @jhedberg @tbursztyka @pfalcon
-/include/posix/                           @pfalcon
-/include/power/power.h                    @wentongwu @nashif
-/include/ptp_clock.h                      @jukkar
-/include/shared_irq.h                     @andrewboie @andyross
-/include/shell/                           @jakub-uC @nordic-krch
-/include/sw_isr_table.h                   @andrewboie @andyross
-/include/sys_clock.h                      @andrewboie @andyross
-/include/sys/sys_io.h                     @andrewboie @andyross
-/include/toolchain.h                      @andrewboie @andyross @nashif
-/include/toolchain/                       @andrewboie @andyross
-/include/zephyr.h                         @andrewboie @andyross
-/kernel/                                  @andrewboie @andyross
-/lib/fnmatch/                             @carlescufi
-/lib/gui/                                 @vanwinkeljan
-/lib/open-amp/                            @arnopo
-/lib/os/                                  @andrewboie @andyross
-/lib/posix/                               @pfalcon
-/lib/cmsis_rtos_v2/                       @nashif
-/lib/cmsis_rtos_v1/                       @nashif
-/lib/libc/                                @nashif @andrewboie
-/modules/                                 @nashif
-/kernel/device.c                          @andrewboie @andyross @nashif
-/kernel/idle.c                            @andrewboie @andyross @nashif
-/samples/                                 @nashif
-/samples/basic/minimal/                   @carlescufi
-/samples/basic/servo_motor/boards/*microbit* @jhe
-/lib/updatehub/                           @nandojve @otavio
-/samples/bluetooth/                       @jhedberg @Vudentz @joerchan
-/samples/boards/intel_s1000_crb/          @sathishkuttan @dcpleung @nashif
-/samples/display/                         @vanwinkeljan
-/samples/drivers/can/                     @alexanderwachter
-/samples/drivers/display/                 @vanwinkeljan
-/samples/drivers/ht16k33/                 @henrikbrixandersen
-/samples/drivers/lora/                    @Mani-Sadhasivam
-/samples/drivers/counter/maxim_ds3231/    @pabigot
-/samples/net/                             @jukkar @tbursztyka @pfalcon
-/samples/net/dns_resolve/                 @jukkar @tbursztyka @pfalcon
-/samples/net/lwm2m_client/                @rlubos
-/samples/net/mqtt_publisher/              @jukkar @tbursztyka
-/samples/net/sockets/coap_*/              @rveerama1
-/samples/net/sockets/                     @jukkar @tbursztyka @pfalcon
-/samples/net/updatehub/                   @nandojve @otavio
-/samples/sensor/                          @MaureenHelm
-/samples/shields/                         @avisconti
-/samples/subsys/logging/                  @nordic-krch @jakub-uC
-/samples/subsys/shell/                    @jakub-uC @nordic-krch
-/samples/subsys/mgmt/mcumgr/smp_svr/      @aunsbjerg @nvlsianpu
-/samples/subsys/usb/                      @jfischer-phytec-iot @finikorg
-/samples/subsys/power/                    @wentongwu @pabigot
-/samples/userspace/                       @andrewboie
-/scripts/coccicheck                       @himanshujha199640 @JuliaLawall
-/scripts/coccinelle/                      @himanshujha199640 @JuliaLawall
-/scripts/kconfig/                         @ulfalizer
-/scripts/sanity_chk/expr_parser.py        @nashif
-/scripts/gen_app_partitions.py            @andrewboie
-/scripts/dts/                             @ulfalizer @galak
-/scripts/release/                         @nashif
-/scripts/ci/                              @nashif
-/arch/x86/gen_gdt.py                      @andrewboie
-/arch/x86/gen_idt.py                      @andrewboie
-/scripts/gen_kobject_list.py              @andrewboie
-/scripts/gen_syscalls.py                  @andrewboie
-/scripts/net/                             @jukkar @pfl
-/scripts/process_gperf.py                 @andrewboie
-/scripts/gen_relocate_app.py              @wentongwu
-/scripts/requirements*.txt                @mbolivar @galak @nashif
-/scripts/tests/sanitycheck/               @aasthagr
-/scripts/tracing/                         @wentongwu
-/scripts/sanity_chk/                      @nashif
-/scripts/sanitycheck                      @nashif
-/scripts/series-push-hook.sh              @erwango
-/scripts/west_commands/                   @mbolivar-nordic
-/scripts/west-commands.yml                @mbolivar-nordic
-/scripts/zephyr_module.py                 @tejlmand
-/scripts/user_wordsize.py                 @cfriedt
-/scripts/valgrind.supp                    @aescolar @daor-oti
-/share/zephyr-package/                    @tejlmand
-/share/zephyrunittest-package/            @tejlmand
-/subsys/bluetooth/                        @joerchan @jhedberg @Vudentz
-/subsys/bluetooth/controller/             @carlescufi @cvinayak @thoh-ot
-/subsys/bluetooth/mesh/                   @jhedberg @trond-snekvik @joerchan @Vudentz
-/subsys/canbus/                           @alexanderwachter
-/subsys/cpp/                              @pabigot @vanwinkeljan
-/subsys/debug/                            @nashif
-/subsys/dfu/                              @nvlsianpu
-/subsys/tracing/                          @nashif @wentongwu
-/subsys/debug/asan_hacks.c                @vanwinkeljan @aescolar @daor-oti
-/subsys/disk/disk_access_spi_sdhc.c       @JunYangNXP
-/subsys/disk/disk_access_sdhc.h           @JunYangNXP
-/subsys/disk/disk_access_usdhc.c          @JunYangNXP
-/subsys/disk/disk_access_stm32_sdmmc.c    @anthonybrandon
-/subsys/fb/                               @jfischer-phytec-iot
-/subsys/fs/                               @nashif
-/subsys/fs/fcb/                           @nvlsianpu
-/subsys/fs/fuse_fs_access.c               @vanwinkeljan
-/subsys/fs/littlefs_fs.c                  @pabigot
-/subsys/fs/nvs/                           @Laczen
-/subsys/logging/                          @nordic-krch
-/subsys/logging/log_backend_net.c         @nordic-krch @jukkar
-/subsys/mgmt/                             @carlescufi @nvlsianpu
-/subsys/mgmt/smp_udp.c                    @aunsbjerg
-/subsys/net/buf.c                         @jukkar @jhedberg @tbursztyka @pfalcon
-/subsys/net/ip/                           @jukkar @tbursztyka @pfalcon
-/subsys/net/lib/                          @jukkar @tbursztyka @pfalcon
-/subsys/net/lib/dns/                      @jukkar @tbursztyka @pfalcon
-/subsys/net/lib/lwm2m/                    @rlubos
-/subsys/net/lib/config/                   @jukkar @tbursztyka @pfalcon
-/subsys/net/lib/mqtt/                     @jukkar @tbursztyka @rlubos
-/subsys/net/lib/coap/                     @rveerama1
-/subsys/net/lib/sockets/socketpair.c      @cfriedt
-/subsys/net/lib/sockets/                  @jukkar @tbursztyka @pfalcon
-/subsys/net/lib/tls_credentials/          @rlubos
-/subsys/net/l2/                           @jukkar @tbursztyka
-/subsys/net/l2/canbus/                    @alexanderwachter @jukkar
-/subsys/net/*/openthread/                 @rlubos
-/subsys/power/                            @wentongwu @pabigot
-/subsys/random/                           @dleach02
-/subsys/settings/                         @nvlsianpu
-/subsys/shell/                            @jakub-uC @nordic-krch
-/subsys/storage/                          @nvlsianpu
-/subsys/testsuite/                        @nashif
-/subsys/usb/                              @jfischer-phytec-iot @finikorg
-/tests/                                   @nashif
-/tests/application_development/libcxx/    @pabigot
-/tests/arch/arm/                          @ioannisg @stephanosio
-/tests/benchmarks/cmsis_dsp/              @stephanosio
-/tests/boards/native_posix/               @aescolar @daor-oti
-/tests/boards/intel_s1000_crb/            @dcpleung @sathishkuttan
-/tests/bluetooth/                         @joerchan @jhedberg @Vudentz
-/tests/bluetooth/bsim_bt/                 @joerchan @jhedberg @Vudentz @aescolar @wopu-ot
-/tests/posix/                             @pfalcon
-/tests/crypto/                            @ceolin
-/tests/crypto/mbedtls/                    @nashif @ceolin
-/tests/drivers/can/                       @alexanderwachter
-/tests/drivers/counter/                   @nordic-krch
-/tests/drivers/counter/maxim_ds3231_api/  @pabigot
-/tests/drivers/flash_simulator/           @nvlsianpu
-/tests/drivers/gpio/                      @mnkp @pabigot
-/tests/drivers/hwinfo/                    @alexanderwachter
-/tests/drivers/spi/                       @tbursztyka
-/tests/drivers/uart/uart_async_api/       @Mierunski
-/tests/kernel/                            @andrewboie @andyross @nashif
-/tests/lib/                               @nashif
-/tests/lib/cmsis_dsp/                     @stephanosio
-/tests/net/                               @jukkar @tbursztyka @pfalcon
-/tests/net/buf/                           @jukkar @jhedberg @tbursztyka @pfalcon
-/tests/net/lib/                           @jukkar @tbursztyka @pfalcon
-/tests/net/lib/http_header_fields/        @jukkar @tbursztyka
-/tests/net/lib/mqtt_packet/               @jukkar @tbursztyka
-/tests/net/lib/coap/                      @rveerama1
-/tests/net/socket/socketpair/             @cfriedt
-/tests/net/socket/                        @jukkar @tbursztyka @pfalcon
-/tests/subsys/fs/                         @nashif @wentongwu
-/tests/subsys/settings/                   @nvlsianpu
-/tests/subsys/shell/                      @jakub-uC @nordic-krch
-# Get all docs reviewed
-*.rst                                     @nashif
-*posix*.rst                               @aescolar @daor-oti

CODE_OF_CONDUCT.md

@@ -1,78 +0,0 @@
-# Contributor Covenant Code of Conduct
-
-## Our Pledge
-
-In the interest of fostering an open and welcoming environment, we as
-contributors and maintainers pledge to making participation in our project and
-our community a harassment-free experience for everyone, regardless of age, body
-size, disability, ethnicity, sex characteristics, gender identity and expression,
-level of experience, education, socio-economic status, nationality, personal
-appearance, race, religion, or sexual identity and orientation.
-
-## Our Standards
-
-Examples of behavior that contributes to creating a positive environment
-include:
-
-* Using welcoming and inclusive language
-* Being respectful of differing viewpoints and experiences
-* Gracefully accepting constructive criticism
-* Focusing on what is best for the community
-* Showing empathy towards other community members
-
-Examples of unacceptable behavior by participants include:
-
-* The use of sexualized language or imagery and unwelcome sexual attention or
- advances
-* Trolling, insulting/derogatory comments, and personal or political attacks
-* Public or private harassment
-* Publishing others' private information, such as a physical or electronic
- address, without explicit permission
-* Other conduct which could reasonably be considered inappropriate in a
- professional setting
-
-## Our Responsibilities
-
-Project maintainers are responsible for clarifying the standards of acceptable
-behavior and are expected to take appropriate and fair corrective action in
-response to any instances of unacceptable behavior.
-
-Project maintainers have the right and responsibility to remove, edit, or
-reject comments, commits, code, wiki edits, issues, and other contributions
-that are not aligned to this Code of Conduct, or to ban temporarily or
-permanently any contributor for other behaviors that they deem inappropriate,
-threatening, offensive, or harmful.
-
-## Scope
-
-This Code of Conduct applies both within project spaces and in public spaces
-when an individual is representing the project or its community. Examples of
-representing a project or community include using an official project e-mail
-address, posting via an official social media account, or acting as an appointed
-representative at an online or offline event. Representation of a project may be
-further defined and clarified by project maintainers.
-
-## Enforcement
-
-Instances of abusive, harassing, or otherwise unacceptable behavior may be
-reported by contacting the project team at conduct@zephyrproject.org.
-Reports will be received by Kate Stewart (Linux Foundation) and Amy Occhialino
-(Intel). All complaints will be reviewed and investigated, and will result in a
-response that is deemed necessary and appropriate to the circumstances. The
-project team is obligated to maintain confidentiality with regard to the
-reporter of an incident.  Further details of specific enforcement policies may
-be posted separately.
-
-Project maintainers who do not follow or enforce the Code of Conduct in good
-faith may face temporary or permanent repercussions as determined by other
-members of the project's leadership.
-
-## Attribution
-
-This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4,
-available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html
-
-[homepage]: https://www.contributor-covenant.org
-
-For answers to common questions about this code of conduct, see
-https://www.contributor-covenant.org/faq

CONTRIBUTING.rst

@@ -1,39 +0,0 @@
-Contribution Guidelines
-#######################
-
-As an open-source project, we welcome and encourage the community to submit
-patches directly to the project.  In our collaborative open source environment,
-standards and methods for submitting changes help reduce the chaos that can result
-from an active development community.
-
-This document briefly summarizes the full `Contribution
-Guidelines <http://docs.zephyrproject.org/latest/contribute/index.html>`_
-documentation.
-
-* Zephyr uses the permissive open source `Apache 2.0 license`_
-  that allows you to freely use, modify, distribute and sell your own products
-  that include Apache 2.0 licensed software.
-
-* There are some imported or reused components of the Zephyr project that
-  use other licensing and are clearly identified.
-
-* The Developer Certificate of Origin (DCO) process is followed to
-  ensure developers are following licensing criteria for their
-  contributions, and documented with a ``Signed-off-by`` line in commits.
-
-* Zephyr development workflow is supported on Linux, macOS, and Windows,
-  (with a few exceptions).
-
-* Source code for the project is maintained in the GitHub repo:
-  https://github.com/zephyrproject-rtos/zephyr
-
-* Issue and feature tracking is done using GitHub issues in this repo.
-
-* A Continuous Integration (CI) system runs on every Pull Request (PR)
-  to verify several aspects of the PR including Git commit formatting,
-  Coding Style, sanity checks builds, and documentation builds.
-
-* The `Zephyr devel mailing list`_ is a great place to engage with the
-  community, ask questions, discuss issues, and help each other.
-
-.. _Zephyr devel mailing list: https://lists.zephyrproject.org/g/devel

Kbuild

@@ -0,0 +1,123 @@
+# vim: filetype=make
+
+ifneq ("$(wildcard $(MDEF_FILE))","")
+MDEF_FILE_PATH=$(strip $(MDEF_FILE))
+else
+ifneq ($(MDEF_FILE),)
+MDEF_FILE_PATH=$(strip $(PROJECT_BASE)/$(MDEF_FILE))
+endif
+endif
+
+ifeq (${CONFIG_NUM_COMMAND_PACKETS},)
+CONFIG_NUM_COMMAND_PACKETS=0
+endif
+ifeq (${CONFIG_NUM_TIMER_PACKETS},)
+CONFIG_NUM_TIMER_PACKETS=0
+endif
+ifeq (${CONFIG_NUM_TASK_PRIORITIES},)
+CONFIG_NUM_TASK_PRIORITIES=$(CONFIG_NUM_PREEMPT_PRIORITIES)
+endif
+
+ifeq ($(ARCH),x86)
+TASKGROUP_SSE="  TASKGROUP SSE"
+endif
+
+define filechk_prj.mdef
+	(echo "% WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY!"; \
+	echo; \
+	echo "% CONFIG NUM_COMMAND_PACKETS NUM_TIMER_PACKETS NUM_TASK_PRIORITIES"; \
+	echo "% ============================================================="; \
+	echo "  CONFIG ${CONFIG_NUM_COMMAND_PACKETS}             ${CONFIG_NUM_TIMER_PACKETS}               ${CONFIG_NUM_TASK_PRIORITIES}"; \
+	echo; \
+	echo "% TASKGROUP NAME";\
+	echo "% ==============";\
+	echo "  TASKGROUP EXE";\
+	echo "  TASKGROUP SYS";\
+	echo "  TASKGROUP FPU_LEGACY";\
+	echo $(TASKGROUP_SSE);\
+	echo; \
+	if test -e "$(MDEF_FILE_PATH)"; then \
+		cat $(MDEF_FILE_PATH); \
+	fi;)
+endef
+
+misc/generated/sysgen/prj.mdef:	$(MDEF_FILE_PATH) \
+				include/config/auto.conf FORCE
+	$(call filechk,prj.mdef)
+
+sysgen_cmd=$(strip \
+	$(PYTHON) $(srctree)/scripts/sysgen \
+	-i $(CURDIR)/misc/generated/sysgen/prj.mdef \
+	-o $(CURDIR)/misc/generated/sysgen/ \
+)
+
+misc/generated/sysgen/kernel_main.c: misc/generated/sysgen/prj.mdef \
+				     $(srctree)/scripts/sysgen
+	$(Q)$(sysgen_cmd)
+
+define filechk_configs.c
+	(echo "/* file is auto-generated, do not modify ! */"; \
+	echo; \
+	echo "#include <toolchain.h>"; \
+	echo; \
+	echo "GEN_ABS_SYM_BEGIN (_ConfigAbsSyms)"; \
+	echo; \
+	cat $(CURDIR)/include/generated/autoconf.h | sed \
+	's/".*"/1/' | awk  \
+	'/#define/{printf "GEN_ABSOLUTE_SYM(%s, %s);\n", $$2, $$3}'; \
+	echo; \
+	echo "GEN_ABS_SYM_END";)
+endef
+
+misc/generated/configs.c: include/config/auto.conf FORCE
+	$(call filechk,configs.c)
+
+targets := misc/generated/configs.c
+targets += include/generated/offsets.h
+
+
+always := misc/generated/configs.c
+always += include/generated/offsets.h
+
+ifeq ($(CONFIG_MDEF),y)
+targets += misc/generated/sysgen/kernel_main.c
+always += misc/generated/sysgen/kernel_main.c
+endif
+
+define rule_cc_o_c_1
+	$(call echo-cmd,cc_o_c_1) $(cmd_cc_o_c_1);
+endef
+
+OFFSETS_INCLUDE = $(strip \
+		-include $(CURDIR)/include/generated/autoconf.h \
+		-I $(srctree)/include \
+		-I $(CURDIR)/include/generated \
+		-I $(srctree)/kernel/unified/include \
+		$(OFFSETS_INCLUDE_KERNEL_LOCATION) \
+		-I $(srctree)/lib/libc/minimal/include \
+		-I $(srctree)/arch/${ARCH}/include )
+
+cmd_cc_o_c_1 = $(CC) $(KBUILD_CFLAGS) $(OFFSETS_INCLUDE) -c -o $@ $<
+
+arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c $(KCONFIG_CONFIG)
+	$(Q)mkdir -p $(dir $@)
+	$(call if_changed,cc_o_c_1)
+
+
+define offsetchk
+	$(Q)set -e;                             \
+	$(kecho) '  CHK     $@';                \
+	mkdir -p $(dir $@);                     \
+	$(GENOFFSET_H) -i $(1) -o $@.tmp;       \
+	if [ -r $@ ] && cmp -s $@ $@.tmp; then  \
+	rm -f $@.tmp;                           \
+	else                                    \
+	$(kecho) '  UPD     $@';                \
+	mv -f $@.tmp $@;                        \
+	fi
+endef
+
+include/generated/offsets.h: arch/$(ARCH)/core/offsets/offsets.o \
+					include/config/auto.conf FORCE
+	$(call offsetchk,arch/$(ARCH)/core/offsets/offsets.o)
+

Kconfig

@@ -1,8 +1,20 @@
-# General configuration options
+# Kconfig - general configuration options
 
+#
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
-# SPDX-License-Identifier: Apache-2.0
-
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
 mainmenu "Zephyr Kernel Configuration"
 
 source "Kconfig.zephyr"

Kconfig.zephyr

@@ -1,458 +1,49 @@
-# General configuration options
+# Kconfig - general configuration options
 
+#
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # Copyright (c) 2016 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-menu "Modules"
-
-source "$(CMAKE_BINARY_DIR)/Kconfig.modules"
-source "modules/Kconfig"
-
-endmenu
-
-# Include Kconfig.defconfig files first so that they can override defaults and
-# other symbol/choice properties by adding extra symbol/choice definitions.
-# After merging all definitions for a symbol/choice, Kconfig picks the first
-# property (e.g. the first default) with a satisfied condition.
 #
-# Shield defaults should have precedence over board defaults, which should have
-# precedence over SoC defaults, so include them in that order.
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
 #
-# $ARCH and $BOARD_DIR will be glob patterns when building documentation.
-source "boards/shields/*/Kconfig.defconfig"
-source "$(BOARD_DIR)/Kconfig.defconfig"
-source "$(SOC_DIR)/$(ARCH)/*/Kconfig.defconfig"
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+config KERNELVERSION
+	string
+	option env="KERNELVERSION"
 
-source "boards/Kconfig"
-source "$(SOC_DIR)/Kconfig"
 source "arch/Kconfig"
+
 source "kernel/Kconfig"
-source "dts/Kconfig"
+
 source "drivers/Kconfig"
+
+source "net/Kconfig"
+
+source "misc/Kconfig"
+
 source "lib/Kconfig"
+
 source "subsys/Kconfig"
 
-osource "$(TOOLCHAIN_KCONFIG_DIR)/Kconfig"
-
-menu "Build and Link Features"
-
-menu "Linker Options"
-
-choice
-	prompt "Linker Orphan Section Handling"
-	default LINKER_ORPHAN_SECTION_WARN
-
-config LINKER_ORPHAN_SECTION_PLACE
-	bool "Place"
-	help
-	  Linker puts orphan sections in place without warnings
-	  or errors.
-
-config LINKER_ORPHAN_SECTION_WARN
-	bool "Warn"
-	help
-	  Linker places the orphan sections in output and issues
-	  warning about those sections.
-
-config LINKER_ORPHAN_SECTION_ERROR
-	bool "Error"
-	help
-	  Linker exits with error when an orphan section is found.
-
-endchoice
-
-config CODE_DATA_RELOCATION
-	bool "Relocate code/data sections"
-	depends on ARM
-	help
-	  When selected this will relocate .text, data and .bss sections from
-	  the specified files and places it in the required memory region. The
-	  files should be specified in the CMakeList.txt file with
-	  a cmake API zephyr_code_relocate().
-
-config HAS_FLASH_LOAD_OFFSET
-	bool
-	help
-	  This option is selected by targets having a FLASH_LOAD_OFFSET
-	  and FLASH_LOAD_SIZE.
-
-if HAS_FLASH_LOAD_OFFSET
-
-config USE_DT_CODE_PARTITION
-	bool "Link application into /chosen/zephyr,code-partition from devicetree"
-	help
-	  When enabled, the application will be linked into the flash partition
-	  selected by the zephyr,code-partition property in /chosen in devicetree.
-	  When this is disabled, the flash load offset and size can be set manually
-	  below.
-
-# Workaround for not being able to have commas in macro arguments
-DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
-
-config FLASH_LOAD_OFFSET
-	# Only user-configurable when USE_DT_CODE_PARTITION is disabled
-	hex "Kernel load offset" if !USE_DT_CODE_PARTITION
-	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_DT_CODE_PARTITION
-	default 0
-	help
-	  This option specifies the byte offset from the beginning of flash that
-	  the kernel should be loaded into. Changing this value from zero will
-	  affect the Zephyr image's link, and will decrease the total amount of
-	  flash available for use by application code.
-
-	  If unsure, leave at the default value 0.
-
-config FLASH_LOAD_SIZE
-	# Only user-configurable when USE_DT_CODE_PARTITION is disabled
-	hex "Kernel load size" if !USE_DT_CODE_PARTITION
-	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_DT_CODE_PARTITION
-	default 0
-	help
-	  If non-zero, this option specifies the size, in bytes, of the flash
-	  area that the Zephyr image will be allowed to occupy.  If zero, the
-	  image will be able to occupy from the FLASH_LOAD_OFFSET to the end of
-	  the device.
-
-	  If unsure, leave at the default value 0.
-
-endif # HAS_FLASH_LOAD_OFFSET
-
-config TEXT_SECTION_OFFSET
-	hex
-	prompt "TEXT section offset" if !BOOTLOADER_MCUBOOT
-	default 0x200 if BOOTLOADER_MCUBOOT
-	default 0
-	help
-	  If the application is built for chain-loading by a bootloader this
-	  variable is required to be set to value that leaves sufficient
-	  space between the beginning of the image and the start of the .text
-	  section to store an image header or any other metadata.
-	  In the particular case of the MCUboot bootloader this reserves enough
-	  space to store the image header, which should also meet vector table
-	  alignment requirements on most ARM targets, although some targets
-	  may require smaller or larger values.
-
-config HAVE_CUSTOM_LINKER_SCRIPT
-	bool "Custom linker scripts provided"
-	help
-	  Set this option if you have a custom linker script which needed to
-	  be define in CUSTOM_LINKER_SCRIPT.
-
-config CUSTOM_LINKER_SCRIPT
-	string "Path to custom linker script"
-	depends on HAVE_CUSTOM_LINKER_SCRIPT
-	help
-	  Path to the linker script to be used instead of the one define by the
-	  board.
-
-	  The linker script must be based on a version provided by Zephyr since
-	  the kernel can expect a certain layout/certain regions.
-
-	  This is useful when an application needs to add sections into the
-	  linker script and avoid having to change the script provided by
-	  Zephyr.
-
-config CUSTOM_RODATA_LD
-	bool "(DEPRECATED) Include custom-rodata.ld"
-	help
-	  Note: This is deprecated, use Cmake function zephyr_linker_sources() instead.
-	  Include a customized linker script fragment for inserting additional
-	  data and linker directives into the rodata section.
-
-config CUSTOM_RWDATA_LD
-	bool "(DEPRECATED) Include custom-rwdata.ld"
-	help
-	  Note: This is deprecated, use Cmake function zephyr_linker_sources() instead.
-	  Include a customized linker script fragment for inserting additional
-	  data and linker directives into the data section.
-
-config CUSTOM_SECTIONS_LD
-	bool "(DEPRECATED) Include custom-sections.ld"
-	help
-	  Note: This is deprecated, use Cmake function zephyr_linker_sources() instead.
-	  Include a customized linker script fragment for inserting additional
-	  arbitrary sections.
-
-config KERNEL_ENTRY
-	string "Kernel entry symbol"
-	default "__start"
-	help
-	  Code entry symbol, to be set at linking phase.
-
-config LINKER_SORT_BY_ALIGNMENT
-	bool "Sort input sections by alignment"
-	default y
-	help
-	  This turns on the linker flag to sort sections by alignment
-	  in decreasing size of symbols. This helps to minimize
-	  padding between symbols.
-
-endmenu
-
-menu "Compiler Options"
-
-config NATIVE_APPLICATION
-	bool "Build as a native host application"
-	help
-	  Build as a native application that can run on the host and using
-	  resources and libraries provided by the host.
-
-choice
-	prompt "Optimization level"
-	default NO_OPTIMIZATIONS    if COVERAGE
-	default DEBUG_OPTIMIZATIONS if DEBUG
-	default SIZE_OPTIMIZATIONS
-	help
-	  Note that these flags shall only control the compiler
-	  optimization level, and that no extra debug code shall be
-	  conditionally compiled based on them.
-
-config SIZE_OPTIMIZATIONS
-	bool "Optimize for size"
-	help
-	  Compiler optimizations will be set to -Os independently of other
-	  options.
-
-config SPEED_OPTIMIZATIONS
-	bool "Optimize for speed"
-	help
-	  Compiler optimizations will be set to -O2 independently of other
-	  options.
-
-config DEBUG_OPTIMIZATIONS
-	bool "Optimize debugging experience"
-	help
-	  Compiler optimizations will be set to -Og independently of other
-	  options.
-
-config NO_OPTIMIZATIONS
-	bool "Optimize nothing"
-	help
-	  Compiler optimizations will be set to -O0 independently of other
-	  options.
-
-endchoice
-
-config COMPILER_OPT
-	string "Custom compiler options"
-	help
-	  This option is a free-form string that is passed to the compiler
-	  when building all parts of a project (i.e. kernel).
-	  The compiler options specified by this string supplement the
-	  predefined set of compiler supplied by the build system,
-	  and can be used to change compiler optimization, warning and error
-	  messages, and so on.
-
-endmenu
-
-choice
-	prompt "Error checking behavior for CHECK macro"
-	default RUNTIME_ERROR_CHECKS
-
-config ASSERT_ON_ERRORS
-	bool "Assert on all errors"
-	help
-	  Assert on errors covered with the CHECK macro.
-
-config NO_RUNTIME_CHECKS
-	bool "No runtime error checks"
-	help
-	  Do not do any runtime checks or asserts when using the CHECK macro.
-
-config RUNTIME_ERROR_CHECKS
-	bool "Enable runtime error checks"
-	help
-	  Always perform runtime checks covered with the CHECK macro. This
-	  option is the default and the only option used during testing.
-
-endchoice
-
-menu "Build Options"
-
-config KERNEL_BIN_NAME
-	string "The kernel binary name"
-	default "zephyr"
-	help
-	  This option sets the name of the generated kernel binary.
-
-config OUTPUT_STAT
-	bool "Create a statistics file"
-	default y
-	help
-	  Create a stat file using readelf -e <elf>
-
-config OUTPUT_DISASSEMBLY
-	bool "Create a disassembly file"
-	default y
-	help
-	  Create an .lst file with the assembly listing of the firmware.
-
-config OUTPUT_DISASSEMBLE_ALL
-	bool "Disassemble all sections with source. Fill zeros."
-	default n
-	depends on OUTPUT_DISASSEMBLY
-	help
-	  The .lst file will contain complete disassembly of the firmware
-	  not just those expected to contain instructions including zeros
-
-config OUTPUT_PRINT_MEMORY_USAGE
-	bool "Print memory usage to stdout"
-	default y
-	help
-	  If the toolchain supports it, this option will pass
-	  --print-memory-region to the linker when it is doing it's first
-	  linker pass. Note that the memory regions are symbolic concepts
-	  defined by the linker scripts and do not necessarily map
-	  directly to the real physical address space. Take also note that
-	  some platforms do two passes of the linker so the results do not
-	  match exactly to the final elf file. See also rom_report,
-	  ram_report and
-	  https://sourceware.org/binutils/docs/ld/MEMORY.html
-
-config BUILD_OUTPUT_HEX
-	bool "Build a binary in HEX format"
-	help
-	  Build a binary in HEX format. This will build a zephyr.hex file need
-	  by some platforms.
-
-config BUILD_OUTPUT_BIN
-	bool "Build a binary in BIN format"
-	default y
-	help
-	  Build a binary in BIN format. This will build a zephyr.bin file need
-	  by some platforms.
-
-config BUILD_OUTPUT_EXE
-	bool "Build a binary in ELF format with .exe extension"
-	help
-	  Build a binary in ELF format that can run in the host system. This
-	  will build a zephyr.exe file.
-
-config BUILD_OUTPUT_S19
-	bool "Build a binary in S19 format"
-	help
-	  Build a binary in S19 format. This will build a zephyr.s19 file need
-	  by some platforms.
-
-config BUILD_NO_GAP_FILL
-	bool "Don't fill gaps in generated hex/bin/s19 files."
-
-config BUILD_OUTPUT_STRIPPED
-	bool "Build a stripped binary"
-	help
-	  Build a stripped binary. This will build a zephyr.stripped file need
-	  by some platforms.
-
-config APPLICATION_DEFINED_SYSCALL
-	bool "Scan application folder for any syscall definition"
-	help
-	  Scan additional folders inside application source folder
-	  for application defined syscalls.
-
-config MAKEFILE_EXPORTS
-	bool "Generate build metadata files named Makefile.exports"
-	help
-	  Generates a file with build information that can be read by
-	  third party Makefile-based build systems.
-
-config LEGACY_DEVICETREE_MACROS
-	bool "Allow use of legacy devicetree macros"
-	help
-	  Allows use of legacy devicetree macros which were used in
-	  Zephyr 2.2 and previous versions, rather than the devicetree.h
-	  API introduced during the Zephyr 2.3 development cycle.
-
-endmenu
-endmenu
-
-
-menu "Boot Options"
-
-config IS_BOOTLOADER
-	bool "Act as a bootloader"
-	depends on XIP
-	depends on ARM
-	help
-	  This option indicates that Zephyr will act as a bootloader to execute
-	  a separate Zephyr image payload.
-
-config BOOTLOADER_SRAM_SIZE
-	int "SRAM reserved for bootloader"
-	default 16
-	depends on !XIP || IS_BOOTLOADER
-	depends on ARM || XTENSA
-	help
-	  This option specifies the amount of SRAM (measure in kB) reserved for
-	  a bootloader image, when either:
-	  - the Zephyr image itself is to act as the bootloader, or
-	  - Zephyr is a !XIP image, which implicitly assumes existence of a
-	  bootloader that loads the Zephyr !XIP image onto SRAM.
-
-config BOOTLOADER_MCUBOOT
-	bool "MCUboot bootloader support"
-	select USE_DT_CODE_PARTITION
-	help
-	  This option signifies that the target uses MCUboot as a bootloader,
-	  or in other words that the image is to be chain-loaded by MCUboot.
-	  This sets several required build system and Device Tree options in
-	  order for the image generated to be bootable using the MCUboot open
-	  source bootloader. Currently this includes:
-
-	    * Setting TEXT_SECTION_OFFSET to a default value that allows space
-	      for the MCUboot image header
-	    * Activating SW_VECTOR_RELAY on Cortex-M0 (or Armv8-M baseline)
-	      targets with no built-in vector relocation mechanisms
-
-config BOOTLOADER_ESP_IDF
-	bool "ESP-IDF bootloader support"
-	depends on SOC_ESP32
-	help
-	  This option will trigger the compilation of the ESP-IDF bootloader
-	  inside the build folder.
-	  At flash time, the bootloader will be flashed with the zephyr image
-
-config BOOTLOADER_KEXEC
-	bool "Boot using Linux kexec() system call"
-	depends on X86
-	help
-	  This option signifies that Linux boots the kernel using kexec system call
-	  and utility. This method is used to boot the kernel over the network.
-
-config BOOTLOADER_CONTEXT_RESTORE
-	bool "Boot loader has context restore support"
-	default y
-	depends on SYS_POWER_DEEP_SLEEP_STATES && BOOTLOADER_CONTEXT_RESTORE_SUPPORTED
-	help
-	  This option signifies that the target has a bootloader
-	  that restores CPU context upon resuming from deep sleep
-	  power state.
-
-config REBOOT
-	bool "Reboot functionality"
-	select SYSTEM_CLOCK_DISABLE
-	help
-	  Enable the sys_reboot() API. Enabling this can drag in other subsystems
-	  needed to perform a "safe" reboot (e.g. SYSTEM_CLOCK_DISABLE, to stop the
-	  system clock before issuing a reset).
-
-config MISRA_SANE
-	bool "MISRA standards compliance features"
-	help
-	  Causes the source code to build in "MISRA" mode, which
-	  disallows some otherwise-permitted features of the C
-	  standard for safety reasons.  Specifically variable length
-	  arrays are not permitted (and gcc will enforce this).
-
-endmenu
-
-menu "Compatibility"
-
-config COMPAT_INCLUDES
-	bool "Suppress warnings when using header shims"
-	default y
-	help
-	  Suppress any warnings from the pre-processor when including
-	  deprecated header files.
-
-endmenu
+source "ext/Kconfig"
+
+source "tests/Kconfig"
+
+#
+# The following are for Kconfig files for default values only.
+# These should be parsed at the end.
+#
+# Board defaults should be parsed after SoC defaults
+# because board usually overrides SoC values.
+#
+source "arch/*/soc/*/Kconfig.defconfig"
+source "boards/*/*/Kconfig.defconfig"

LICENSING.rst

@@ -0,0 +1,66 @@
+.. _zephyr_licensing:
+
+Licensing of Zephyr Project components
+######################################
+
+The Zephyr kernel tree imports or reuses packages, scripts and other
+files that are not covered by the :download:`Apache License
+<../LICENSE>`. In some places there is no LICENSE file or way to put
+a LICENSE file there, so we describe the licensing in this document.
+
+
+- *kconfig* and *kbuild*
+
+  *Origin:* Linux Kernel
+  *Licensing:* *GPLv2*
+
+- *scripts/{checkpatch.pl,checkstack.pl,get_maintainers.pl,spelling.txt}*
+
+  *Origin:* Linux Kernel
+  *Licensing:* *GPLv2*
+
+- *ext/fs/fat/*
+
+  *Origin:* FatFs is a file system based on the FAT file system specification.  This is
+  provided by ELM Chan http://elm-chan.org/fsw/ff/00index_e.html
+
+  *Licensing*:
+
+    Copyright (C) 2016, ChaN, all right reserved.
+
+    FatFs module is an open source software. Redistribution and use of FatFs in
+    source and binary forms, with or without modification, are permitted provided
+    that the following condition is met:
+
+    1. Redistributions of source code must retain the above copyright notice,
+       this condition and the following disclaimer.
+
+    This software is provided by the copyright holder and contributors "AS IS"
+    and any warranties related to this software are DISCLAIMED.
+    The copyright owner or contributors be NOT LIABLE for any damages caused
+    by use of this software.
+
+- *ext/hal/cmsis/*
+
+  *Origin:* https://github.com/ARM-software/CMSIS.git
+
+  *Licensing*: :download:`CMSIS_END_USER_LICENCE_AGREEMENT <../ext/hal/cmsis/CMSIS_END_USER_LICENCE_AGREEMENT.pdf>`
+
+- *ext/hal/ksdk/*
+
+  *Origin:* http://kex.nxp.com
+
+  *Licensing*: 3-clause BSD (see :download:`source
+  <../ext/hal/ksdk/drivers/fsl_rtc.h>`)
+
+- *ext/hal/nordic/*
+
+  *Origin:*
+
+  *Licensing*: 3-clause BSD (see :download:`source <../ext/hal/nordic/mdk/nrf51.h>`)
+
+- *ext/hal/qmsi/*
+
+  *Origin:* https://github.com/quark-mcu/qmsi/releases
+
+  *Licensing*: 3-clause BSD (see :download:`source <../ext/hal/qmsi/include/qm_common.h>`)

MAINTAINERS

@@ -0,0 +1,458 @@
+Originally from the Linux Kernel.
+# Licensed under the terms of the GNU GPL License version 2
+
+Descriptions of section entries:
+
+	P: Person (obsolete)
+	M: Mail patches to: FullName <address@domain>
+	R: Designated reviewer: FullName <address@domain>
+	   These reviewers should be CCed on patches.
+	L: Mailing list that is relevant to this area
+	W: Web-page with status/info
+	Q: Patchwork web based patch tracking system site
+	T: SCM tree type and location.
+	   Type is one of: git, hg, quilt, stgit, topgit
+	S: Status, one of the following:
+	   Supported:	Someone is actually paid to look after this.
+	   Maintained:	Someone actually looks after it.
+	   Odd Fixes:	It has a maintainer but they don't have time to do
+			much other than throw the odd patch in. See below..
+	   Orphan:	No current maintainer [but maybe you could take the
+			role as you write your new code].
+	   Obsolete:	Old code. Something tagged obsolete generally means
+			it has been replaced by a better system and you
+			should be using that.
+	F: Files and directories with wildcard patterns.
+	   A trailing slash includes all files and subdirectory files.
+	   F:	drivers/net/	all files in and below drivers/net
+	   F:	drivers/net/*	all files in drivers/net, but not below
+	   F:	*/net/*		all files in "any top level directory"/net
+	   One pattern per line.  Multiple F: lines acceptable.
+	N: Files and directories with regex patterns.
+	   N:	[^a-z]tegra	all files whose path contains the word tegra
+	   One pattern per line.  Multiple N: lines acceptable.
+	   scripts/get_maintainer.pl has different behavior for files that
+	   match F: pattern and matches of N: patterns.  By default,
+	   get_maintainer will not look at git log history when an F: pattern
+	   match occurs.  When an N: match occurs, git log history is used
+	   to also notify the people that have git commit signatures.
+	X: Files and directories that are NOT maintained, same rules as F:
+	   Files exclusions are tested before file matches.
+	   Can be useful for excluding a specific subdirectory, for instance:
+	   F:	net/
+	   X:	net/ipv6/
+	   matches all files in and below net excluding net/ipv6/
+	K: Keyword perl extended regex pattern to match content in a
+	   patch or file.  For instance:
+	   K: of_get_profile
+	      matches patches or files that contain "of_get_profile"
+	   K: \b(printk|pr_(info|err))\b
+	      matches patches or files that contain one or more of the words
+	      printk, pr_info or pr_err
+	   One regex pattern per line.  Multiple K: lines acceptable.
+
+Note: For the hard of thinking, this list is meant to remain in alphabetical
+order. If you could add yourselves to it in alphabetical order that would be
+so much easier [Ed]
+
+Maintainers List (try to look for most precise areas first)
+
+		-----------------------------------
+
+ARC ARCHITECTURE
+M:	Ruud Derwig <Ruud.Derwig@synopsys.com>
+M:	Chuck Jordan <Chuck.Jordan@synopsys.com>
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+S:	Supported
+F:	arch/arc/
+F:	include/arch/arc/
+F:	boards/arc/
+
+ARM ARCHITECTURE
+M:	Maureen Helm <maureen.helm@nxp.com>
+M:	Kumar Gala <kumar.gala@linaro.org>
+S:	Supported
+F:	arch/arm/
+F:	include/arch/arm/
+F:	boards/arm/
+
+ARM CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD (CMSIS)
+M:	Maureen Helm <maureen.helm@nxp.com>
+M:	Kumar Gala <kumar.gala@linaro.org>
+S:	Supported
+F:	ext/hal/cmsis/
+
+BOARDS/ARC - ARDUINO 101 SSS
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/arc/arduino_101_sss/
+
+BOARDS/ARC - EM Starterkit
+M:	Chuck Jordan <Chuck.Jordan@synopsys.com>
+S:	Supported
+F:	boards/arc/em_starterkit/
+
+BOARDS/ARC - QUARK SE C1000 SS Devboard
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/arc/quark_se_c1000_ss_devboard/
+
+BOARDS/ARM - 96Boards CARBON
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	boards/arm/96b_carbon/
+
+BOARDS/ARM - 96Boards NITROGEN
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+S:	Supported
+F:	boards/arm/96b_nitrogen/
+
+BOARDS/ARM - ARDUINO 101 BLE
+M:	Johan Hedberg <johan.hedberg@intel.com>
+S:	Supported
+F:	boards/arm/arduino_101_ble/
+
+BOARDS/ARM - CC3200 LAUNCHXL
+M:      Gil Pitney <gil.pitney@linaro.org>
+S:      Supported
+F:      boards/arm/cc3200_launchxl/
+
+BOARDS/ARM - NXP FRDM-K64F
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	boards/arm/frdm_k64f/
+
+BOARDS/ARM - NXP Hexiwear
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	boards/arm/hexiwear_k64/
+
+BOARDS/ARM - NORDIC NRF51 REDBEAR BLENANO
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	boards/arm/nrf51_blenano/
+
+BOARDS/ARM - NORDIC NRF52 PCA10040
+M:	Carles Cufi <carles.cufi@nordicsemi.no>
+S:	Supported
+F:	boards/arm/nrf52_pca10040/
+
+BOARDS/ARM - NUCLEO-64 F401RE Devboard
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	boards/arm/nucleo_f401re/
+
+BOARDS/ARM - ARM LTD V2M Beetle
+M:	Vincenzo Frascino <vincenzo.frascino@linaro.org>
+S:	Supported
+F:	boards/arm/v2m_beetle/
+
+BOARDS/NIOS2 - ALTERA MAX10
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	boards/nios2/altera_max10/
+
+BOARDS/X86 - ARDUINO 101
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/arduino_101/
+
+BOARDS/X86 - Galileo
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/galileo/
+
+BOARDS/X86 - QUARK D2000 Devboard
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/quark_d2000/
+
+BOARDS/X86 - QUARK SE C1000 Devboard
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/quark_se_c1000/
+
+BLUETOOTH
+M:	Johan Hedberg <johan.hedberg@intel.com>
+M:	Luiz Augusto von Dentz <luiz.dentz@gmail.com>
+M:	Szymon Janc <szymon.janc@gmail.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/bluetooth/bluetooth.html
+F:	subsys/bluetooth/
+F:	include/bluetooth/
+F:	drivers/bluetooth/
+F:	samples/bluetooth/
+F:	tests/bluetooth/
+F:	doc/subsystems/bluetooth/
+
+BLUETOOTH CONTROLLER
+M:	Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
+M:	Carles Cufi <carles.cufi@nordicsemi.no>
+S:	Supported
+F:	subsys/bluetooth/controller/
+
+CC3200 SDK
+M:      Gil Pitney <gil.pitney@linaro.org>
+S:      Supported
+F:      ext/hal/cc3200sdk/
+
+CC32XX SOC - TI SIMPLELINK
+M:      Gil Pitney <gil.pitney@linaro.org>
+S:      Supported
+F:      arch/arm/soc/ti_simplelink/
+
+DOCUMENTATION
+M:	Kinder, David <david.b.kinder@intel.com>
+M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
+S:	Supported
+F:	doc/
+
+FILE SYSTEM
+M:	Ramesh Thomas <ramesh.thomas@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	ext/fs/
+F:	subsys/fs/
+F:	include/fs/
+F:	include/fs.h
+F:	samples/fs/
+
+FLASH DRIVER
+M:	Baohong Liu <baohong.liu@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	drivers/flash/
+
+INTERRUPTS
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	drivers/interrupt_controller/
+F:	arch/arc/core/
+F:	arch/arm/core/
+F:	arch/nios2/core/
+F:	arch/x86/core/
+F:	include/irq.h
+F:	include/arch/x86/arch.h
+F:	include/arch/arm/cortex_m/irq.h
+F:	include/arch/nios2/arch.h
+F:	include/arch/arc/arch.h
+F:	include/arch/arc/v2/irq.h
+F:	include/drivers/loapic.h
+F:	include/drivers/ioapic.h
+F:	include/drivers/mvic.h
+
+KERNEL CORE
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+M:	Allan Stephens <allan.stephens@windriver.com>
+S:	Supported
+F:	kernel/
+F:	include/nanokernel.h
+F:	include/microkernel.h
+F:	include/microkernel/
+F:	include/misc/
+F:	include/toolchain/
+F:	include/atomic.h
+F:	include/cache.h
+F:	include/init.h
+F:	include/irq.h
+F:	include/irq_offload.h
+F:	include/kernel_version.h
+F:	include/linker-defs.h
+F:	include/linker-tool-gcc.h
+F:	include/linker-tool.h
+F:	include/section_tags.h
+F:	include/sections.h
+F:	include/shared_irq.h
+F:	include/sw_isr_table.h
+F:	include/sys_clock.h
+F:	include/sys_io.h
+F:	include/toolchain.h
+F:	include/zephyr.h
+
+KINETIS SOFTWARE DEVELOPMENT KIT (KSDK)
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	ext/hal/ksdk/
+
+KNOWN ISSUES
+M:	Anas Nashif <anas.nashif@intel.com>
+M:	Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+M:	Javier B Perez <javier.b.perez.hernandez@intel.com>
+F:	.known-issues/
+
+
+MAINTAINERS
+M:	Javier B Perez <javier.b.perez.hernandez@intel.com>
+M:	Anas Nashif <anas.nashif@intel.com>
+M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
+S:	Supported
+F:	MAINTAINERS
+
+MBEDTLS
+M:	Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
+M:	Jithu Joseph <jithu.joseph@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	ext/lib/crypto/mbedtls/
+F:	samples/net/mbedtls_sslclient/
+F:	tests/crypto/test_mbedtls/
+
+NETWORKING
+M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/networking/networking.html
+F:	net/ip/
+F:	include/net/
+F:	samples/net/
+F:	tests/net/
+
+NETWORK APPLICATIONS
+M:	Flavio Santes <flavio.santes@intel.com>
+S:	Supported
+F:	samples/net/dns_client/
+F:	samples/net/nats_clients/
+F:	samples/net/paho_mqtt_clients/
+
+NETWORK BUFFERS
+M:	Johan Hedberg <johan.hedberg@intel.com>
+M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/networking/buffers.html
+F:	net/buf.c
+F:	include/net/buf.h
+F:	tests/net/buf/
+
+NIOS II
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	arch/nios2/
+F:	include/arch/nios2/
+F:	drivers/serial/uart_altera_jtag.c
+F:	drivers/timer/altera_avalon_timer.c
+F:	tests/kernel/test_intmath/
+F:	boards/nios2/
+
+NORDIC MDK
+M:	Carles Cufi <carles.cufi@nordicsemi.no>
+S:	Supported
+F:	ext/hal/nordic/mdk/
+
+POWER MANAGEMENT
+M:	Ramesh Thomas <ramesh.thomas@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	arch/x86/core/crt0.S
+F:	include/device.h
+F:	include/init.h
+F:	include/power.h
+F:	kernel/microkernel/k_idle.c
+F:	kernel/nanokernel/device.c
+F:	samples/power/
+
+QMSI
+M:	Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	ext/hal/qmsi/
+
+QMSI DRIVERS
+M:	Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
+M:	Baohong Liu <baohong.liu@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	drivers/*/*qmsi*
+F:	drivers/*/*/*qmsi*
+
+QUARK D2000 SOC
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	arch/x86/soc/intel_quark/quark_d2000/
+
+QUARK SE C1000 SOC
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	arch/x86/soc/intel_quark/quark_se_c1000/
+
+QUARK X1000 SOC
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	arch/x86/soc/intel_quark/quark_x1000/
+
+RELEASE NOTES
+M:      Anas Nashif <anas.nashif@intel.com>
+M:	Javier B Perez <javier.b.perez.hernandez@intel.com>
+M:	Kinder, David <david.b.kinder@intel.com>
+S:	Supported
+F:	release-notes.rst
+
+SANITYCHECK
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	scripts/sanitycheck
+F:	scripts/expr_parser.py
+F:	scripts/sanity_chk/
+
+SENSOR DRIVERS
+M:	Bogdan Davidoaia <bogdan.m.davidoaia@intel.com>
+M:	Laurentiu Palcu <laurentiu.palcu@intel.com>
+M:	Murtaza Alexandru <alexandru.murtaza@intel.com>
+M:	Vlad Dogaru <vlad.dogaru@intel.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/sensor.html
+F:	include/sensor.h
+F:	drivers/sensor/
+F:	samples/sensor/
+
+STM32CUBE SDK
+M:	Erwan Gouriou <erwan.gouriou@linaro.org>
+S:	Supported
+F:	ext/hal/st/stm32cube/
+
+STM32F4X SoC FAMILY and DRIVERS
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	arch/arm/soc/st_stm32/stm32f4/
+F:	drivers/pinmux/stm32/
+F:	drivers/gpio/*stm32*
+F:	drivers/clock_control/*stm32f4*
+
+TINYCRYPT
+M:	Constanza Heath <constanza.m.heath@intel.com>
+M:	Flavio Santes <flavio.santes@intel.com>
+S:	Supported
+F:	ext/lib/crypto/tinycrypt/
+F:	tests/crypto/
+
+USB
+M:	Jithu Joseph <jithu.joseph@intel.com>
+S:	Supported
+F:	subsys/usb
+F:	drivers/usb
+F:	samples/usb
+
+X86 ARCH
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+M:	Allan Stephens <allan.stephens@windriver.com>
+S:	Supported
+F:	arch/x86/
+F:	include/arch/x86/
+F:	boards/x86/
+
+ZOAP
+M:	Vinicius Costa Gomes <vinicius.gomes@intel.com>
+S:	Supported
+F:	lib/iot/zoap/
+F:	samples/net/zoap_client/
+F:	samples/net/zoap_server/
+F:	tests/net/zoap/
+
+THE REST
+M:	Anas Nashif <anas.nashif@intel.com>
+M:	Kumar Gala <kumar.gala@linaro.org>
+L:	devel@lists.zephyrproject.com
+T:	git https://gerrit.zephyrproject.org/r/a/zephyr
+S:	Buried alive in reporters
+F:	*
+F:	*/

Makefile.inc

@@ -0,0 +1,149 @@
+# vim: filetype=make
+#
+
+UNAME := $(shell uname)
+ifeq (MINGW, $(findstring MINGW, $(UNAME)))
+DQUOTE = '
+# '
+PROJECT_BASE ?= $(shell sh -c "pwd -W")
+else
+DQUOTE = "
+# "
+PROJECT_BASE ?= $(CURDIR)
+endif
+
+ifdef BOARD
+KBUILD_DEFCONFIG_PATH=$(wildcard $(ZEPHYR_BASE)/boards/*/*/$(BOARD)_defconfig)
+ifeq ($(KBUILD_DEFCONFIG_PATH),)
+$(error Board $(BOARD) not found!)
+endif
+else
+$(error BOARD is not defined!)
+endif
+
+# Choose a default output directory if one wasn't supplied.  Note that
+# PRISTINE_O depends on whether this is default or not.  If building
+# in-tree, we want to remove the whole outdir and not just the BOARD
+# specified (thus "pristine").  Out of tree, we can obviously remove
+# only what we were told to build.
+ifndef O
+PRISTINE_O = outdir
+O = $(PROJECT_BASE)/outdir/$(BOARD)
+else
+PRISTINE_O = $(O)
+endif
+
+# Turn O into an absolute path; we call the main Kbuild with $(MAKE) -C
+# which changes the working directory, relative paths don't work right.
+# Need to create the directory first to make realpath happy
+
+ifneq ($(MAKECMDGOALS),help)
+$(shell mkdir -p $(O))
+override O := $(realpath $(O))
+endif
+
+export ARCH MDEF_FILE QEMU_EXTRA_FLAGS PROJECT_BASE
+
+override CONF_FILE := $(strip $(subst $(DQUOTE),,$(CONF_FILE)))
+
+SOURCE_DIR ?= $(PROJECT_BASE)/src/
+override SOURCE_DIR := $(realpath $(SOURCE_DIR))
+override SOURCE_DIR := $(subst \,/,$(SOURCE_DIR))
+override SOURCE_DIR_PARENT := $(patsubst %, %/.., $(SOURCE_DIR))
+override SOURCE_DIR_PARENT := $(abspath $(SOURCE_DIR_PARENT))
+override SOURCE_DIR_PARENT := $(subst \,/,$(SOURCE_DIR_PARENT))
+export SOURCE_DIR SOURCE_DIR_PARENT
+
+ifeq ("$(origin V)", "command line")
+  KBUILD_VERBOSE = $(V)
+endif
+ifndef KBUILD_VERBOSE
+  KBUILD_VERBOSE = 0
+endif
+
+ifeq ($(KBUILD_VERBOSE),1)
+  Q =
+  S =
+else
+  Q = @
+  S = -s
+endif
+
+export CFLAGS
+
+zephyrmake	= +$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) \
+			PROJECT=$(PROJECT_BASE) SOURCE_DIR=$(DQUOTE)$(SOURCE_DIR)$(DQUOTE) $(2)
+
+BOARDCONFIG = $(O)/.board_$(BOARD)
+
+DOTCONFIG = $(O)/.config
+
+all: $(DOTCONFIG)
+	$(Q)$(call zephyrmake,$(O),$@)
+
+ifeq ($(findstring qemu_,$(BOARD)),)
+qemu:
+	@echo "Emulation not available for this platform"
+qemugdb: qemu
+else
+qemu: $(DOTCONFIG)
+	$(Q)$(call zephyrmake,$(O),$@)
+qemugdb: $(DOTCONFIG)
+	$(Q)$(call zephyrmake,$(O),$@)
+endif
+
+debug:	$(DOTCONFIG)
+	$(Q)$(call zephyrmake,$(O),$@)
+
+flash: $(DOTCONFIG)
+	$(Q)$(call zephyrmake,$(O),$@)
+
+ifeq ($(MAKECMDGOALS),debugserver)
+ARCH = $(notdir $(subst /$(BOARD),,$(wildcard $(ZEPHYR_BASE)/boards/*/$(BOARD))))
+-include $(ZEPHYR_BASE)/boards/$(ARCH)/$(BOARD)/Makefile.board
+-include $(ZEPHYR_BASE)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
+BOARD_NAME = $(BOARD)
+export BOARD_NAME
+endif
+debugserver: FORCE
+	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/support/$(FLASH_SCRIPT) debugserver
+
+
+initconfig outputexports: $(DOTCONFIG)
+
+$(BOARDCONFIG):
+	@rm -f $(O)/.board_*
+	@touch $@
+
+
+ram_report: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
+rom_report: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
+menuconfig: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
+help:
+	$(Q)$(MAKE) -s -C $(ZEPHYR_BASE) $@
+
+# Catch all
+%:
+	$(Q)$(call zephyrmake,$(O),$@)
+
+KERNEL_CONFIG = $(ZEPHYR_BASE)/kernel/configs/unified.config
+
+$(DOTCONFIG): $(BOARDCONFIG) $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
+	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/kconfig/merge_config.sh \
+		-q -m -O $(O) $(KBUILD_DEFCONFIG_PATH) $(KERNEL_CONFIG) $(CONF_FILE) \
+			      $(wildcard $(O)/*.conf)
+	$(Q)$(MAKE) $(S) -C $(ZEPHYR_BASE) O=$(O) PROJECT=$(PROJECT_BASE) oldnoconfig
+
+pristine:
+	$(Q)rm -rf $(PRISTINE_O)
+
+PHONY += FORCE initconfig
+FORCE:
+
+.PHONY: $(PHONY)

README.rst

@@ -1,86 +0,0 @@
-.. raw:: html
-
-   <a href="https://www.zephyrproject.org">
-     <p align="center">
-       <img src="doc/images/Zephyr-Project.png">
-     </p>
-   </a>
-
-   <a href="https://bestpractices.coreinfrastructure.org/projects/74"><img
-   src="https://bestpractices.coreinfrastructure.org/projects/74/badge"></a>
-   <img
-   src="https://api.shippable.com/projects/58ffb2b8baa5e307002e1d79/badge?branch=master">
-
-
-The Zephyr Project is a scalable real-time operating system (RTOS) supporting
-multiple hardware architectures, optimized for resource constrained devices,
-and built with security in mind.
-
-The Zephyr OS is based on a small-footprint kernel designed for use on
-resource-constrained systems: from simple embedded environmental sensors and
-LED wearables to sophisticated smart watches and IoT wireless gateways.
-
-The Zephyr kernel supports multiple architectures, including ARM Cortex-M,
-Intel x86, ARC, Nios II, Tensilica Xtensa, and RISC-V, and a large number of
-`supported boards`_.
-
-.. below included in doc/introduction/introduction.rst
-
-.. start_include_here
-
-Getting Started
-***************
-
-Welcome to Zephyr! See the `Introduction to Zephyr`_ for a high-level overview,
-and the documentation's `Getting Started Guide`_ to start developing.
-
-Community Support
-*****************
-
-Community support is provided via mailing lists and Slack; see the Resources
-below for details.
-
-.. _project-resources:
-
-Resources
-*********
-
-Here's a quick summary of resources to help you find your way around:
-
-* **Help**: `Asking for Help Tips`_
-* **Documentation**: http://docs.zephyrproject.org (`Getting Started Guide`_)
-* **Source Code**: https://github.com/zephyrproject-rtos/zephyr is the main
-  repository; https://elixir.bootlin.com/zephyr/latest/source contains a
-  searchable index
-* **Releases**: https://github.com/zephyrproject-rtos/zephyr/releases
-* **Samples and example code**: see `Sample and Demo Code Examples`_
-* **Mailing Lists**: users@lists.zephyrproject.org and
-  devel@lists.zephyrproject.org are the main user and developer mailing lists,
-  respectively. You can join the developer's list and search its archives at
-  `Zephyr Development mailing list`_. The other `Zephyr mailing list
-  subgroups`_ have their own archives and sign-up pages.
-* **Nightly CI Build Status**: https://lists.zephyrproject.org/g/builds
-  The builds@lists.zephyrproject.org mailing list archives the CI
-  (shippable) nightly build results.
-* **Chat**: Zephyr's Slack workspace is https://zephyrproject.slack.com.  Use
-  this `Slack Invite`_ to register.
-* **Contributing**: see the `Contribution Guide`_
-* **Wiki**: `Zephyr GitHub wiki`_
-* **Issues**: https://github.com/zephyrproject-rtos/zephyr/issues
-* **Security Issues**: Email vulnerabilities@zephyrproject.org to report
-  security issues; also see our `Security`_ documentation. Security issues are
-  tracked separately at https://zephyrprojectsec.atlassian.net.
-* **Zephyr Project Website**: https://zephyrproject.org
-
-.. _Slack Invite: https://tinyurl.com/y5glwylp
-.. _supported boards: http://docs.zephyrproject.org/latest/boards/index.html
-.. _Zephyr Documentation: http://docs.zephyrproject.org
-.. _Introduction to Zephyr: http://docs.zephyrproject.org/latest/introduction/index.html
-.. _Getting Started Guide: http://docs.zephyrproject.org/latest/getting_started/index.html
-.. _Contribution Guide: http://docs.zephyrproject.org/latest/contribute/index.html
-.. _Zephyr GitHub wiki: https://github.com/zephyrproject-rtos/zephyr/wiki
-.. _Zephyr Development mailing list: https://lists.zephyrproject.org/g/devel
-.. _Zephyr mailing list subgroups: https://lists.zephyrproject.org/g/main/subgroups
-.. _Sample and Demo Code Examples: http://docs.zephyrproject.org/latest/samples/index.html
-.. _Security: http://docs.zephyrproject.org/latest/security/index.html
-.. _Asking for Help Tips: https://docs.zephyrproject.org/latest/guides/getting-help.html

VERSION

@@ -1,5 +0,0 @@
-VERSION_MAJOR = 2
-VERSION_MINOR = 3
-PATCHLEVEL = 0
-VERSION_TWEAK = 0
-EXTRAVERSION =

arch/CMakeLists.txt

@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-add_definitions(-D__ZEPHYR_SUPERVISOR__)
-
-include_directories(
-  ${ZEPHYR_BASE}/kernel/include
-  ${ZEPHYR_BASE}/arch/${ARCH}/include
-  )
-
-add_subdirectory(common)
-add_subdirectory(${ARCH_DIR}/${ARCH} arch/${ARCH})

arch/Kconfig

@@ -1,590 +1,112 @@
-# General architecture configuration options
+# Kconfig - general architecture configuration options
 
+#
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # Copyright (c) 2015 Intel Corporation
-# Copyright (c) 2016 Cadence Design Systems, Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-# Include these first so that any properties (e.g. defaults) below can be
-# overridden (by defining symbols in multiple locations)
-
-# Note: $ARCH might be a glob pattern
-source "$(ARCH_DIR)/$(ARCH)/Kconfig"
-
-# Architecture symbols
 #
-# Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
-# by SOC_*.
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+
+choice
+	prompt "Architecture"
+	default X86
 
 config ARC
-	bool
-	select ARCH_IS_SET
-	select HAS_DTS
-	help
-	  ARC architecture
+	bool "ARC architecture"
 
 config ARM
-	bool
-	select ARCH_IS_SET
-	select HAS_DTS
-	# FIXME: current state of the code for all ARM requires this, but
-	# is really only necessary for Cortex-M with ARM MPU!
-	select GEN_PRIV_STACKS
-	help
-	  ARM architecture
+	bool "ARM architecture"
 
 config X86
-	bool
-	select ARCH_IS_SET
+	bool "x86 architecture"
+	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
 	select ATOMIC_OPERATIONS_BUILTIN
-	select HAS_DTS
-	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN if !X86_64
-	help
-	  x86 architecture
 
 config NIOS2
-	bool
-	select ARCH_IS_SET
+	bool "Nios II Gen 2 architecture"
 	select ATOMIC_OPERATIONS_C
-	select HAS_DTS
-	help
-	  Nios II Gen 2 architecture
 
-config RISCV
-	bool
-	select ARCH_IS_SET
-	select HAS_DTS
-	help
-	  RISCV architecture
-
-config XTENSA
-	bool
-	select ARCH_IS_SET
-	select HAS_DTS
-	select USE_SWITCH
-	select USE_SWITCH_SUPPORTED
-	help
-	  Xtensa architecture
-
-config ARCH_POSIX
-	bool
-	select ARCH_IS_SET
-	select HAS_DTS
-	select ATOMIC_OPERATIONS_BUILTIN
-	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
-	select ARCH_HAS_CUSTOM_BUSY_WAIT
-	select ARCH_HAS_THREAD_ABORT
-	select NATIVE_APPLICATION
-	select HAS_COVERAGE_SUPPORT
-	help
-	  POSIX (native) architecture
-
-config ARCH_IS_SET
-	bool
-	help
-	  Helper symbol to detect SoCs forgetting to select one of the arch
-	  symbols above. See the top-level CMakeLists.txt.
-
-menu "General Architecture Options"
-
-module = ARCH
-module-str = arch
-source "subsys/logging/Kconfig.template.log_config"
-
-module = MPU
-module-str = mpu
-source "subsys/logging/Kconfig.template.log_config"
-
-config BIG_ENDIAN
-	bool
-	help
-	  This option tells the build system that the target system is big-endian.
-	  Little-endian architecture is the default and should leave this option
-	  unselected.  This option is selected by arch/$ARCH/Kconfig,
-	  soc/**/Kconfig, or boards/**/Kconfig and the user should generally avoid
-	  modifying it.  The option is used to select linker script OUTPUT_FORMAT
-	  and command line option for gen_isr_tables.py.
-
-config 64BIT
-	bool
-	help
-	  This option tells the build system that the target system is
-	  using a 64-bit address space, meaning that pointer and long types
-	  are 64 bits wide. This option is selected by arch/$ARCH/Kconfig,
-	  soc/**/Kconfig, or boards/**/Kconfig and the user should generally
-	  avoid modifying it.
-
-# Workaround for not being able to have commas in macro arguments
-DT_CHOSEN_Z_SRAM := zephyr,sram
-
-config SRAM_SIZE
-	int "SRAM Size in kB"
-	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K)
-	help
-	  The SRAM size in kB. The default value comes from /chosen/zephyr,sram in
-	  devicetree. The user should generally avoid changing it via menuconfig or
-	  in configuration files.
-
-config SRAM_BASE_ADDRESS
-	hex "SRAM Base Address"
-	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))
-	help
-	  The SRAM base address. The default value comes from from
-	  /chosen/zephyr,sram in devicetree. The user should generally avoid
-	  changing it via menuconfig or in configuration files.
-
-if ARC || ARM || NIOS2 || X86
-
-# Workaround for not being able to have commas in macro arguments
-DT_CHOSEN_Z_FLASH := zephyr,flash
-
-config FLASH_SIZE
-	int "Flash Size in kB"
-	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && ARM) || !ARM
-	help
-	  This option specifies the size of the flash in kB.  It is normally set by
-	  the board's defconfig file and the user should generally avoid modifying
-	  it via the menu configuration.
-
-config FLASH_BASE_ADDRESS
-	hex "Flash Base Address"
-	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && ARM) || !ARM
-	help
-	  This option specifies the base address of the flash on the board. It is
-	  normally set by the board's defconfig file and the user should generally
-	  avoid modifying it via the menu configuration.
-
-endif # ARM || ARC || NIOS2 || X86
-
-if ARCH_HAS_TRUSTED_EXECUTION
-
-config TRUSTED_EXECUTION_SECURE
-	bool "Trusted Execution: Secure firmware image"
-	help
-	  Select this option to enable building a Secure firmware
-	  image for a platform that supports Trusted Execution. A
-	  Secure firmware image will execute in Secure state. It may
-	  allow the CPU to execute in Non-Secure (Normal) state.
-	  Therefore, a Secure firmware image shall be able to
-	  configure security attributions of CPU resources (memory
-	  areas, peripherals, interrupts, etc.) as well as to handle
-	  faults, related to security violations. It may optionally
-	  allow certain functions to be called from the Non-Secure
-	  (Normal) domain.
-
-config TRUSTED_EXECUTION_NONSECURE
-	depends on !TRUSTED_EXECUTION_SECURE
-	bool "Trusted Execution: Non-Secure firmware image"
-	help
-	  Select this option to enable building a Non-Secure
-	  firmware image for a platform that supports Trusted
-	  Execution. A Non-Secure firmware image will execute
-	  in Non-Secure (Normal) state. Therefore, it shall not
-	  access CPU resources (memory areas, peripherals,
-	  interrupts etc.) belonging to the Secure domain.
-
-endif # ARCH_HAS_TRUSTED_EXECUTION
-
-config HW_STACK_PROTECTION
-	bool "Hardware Stack Protection"
-	depends on ARCH_HAS_STACK_PROTECTION
-	help
-	  Select this option to enable hardware-based platform features to
-	  catch stack overflows when the system is running in privileged
-	  mode. If CONFIG_USERSPACE is not enabled, the system is always
-	  running in privileged mode.
-
-	  Note that this does not necessarily prevent corruption and assertions
-	  about the overall system state when a fault is triggered cannot be
-	  made.
-
-config USERSPACE
-	bool "User mode threads"
-	depends on ARCH_HAS_USERSPACE
-	depends on RUNTIME_ERROR_CHECKS
-	help
-	  When enabled, threads may be created or dropped down to user mode,
-	  which has significantly restricted permissions and must interact
-	  with the kernel via system calls. See Zephyr documentation for more
-	  details	about this feature.
-
-	  If a user thread overflows its stack, this will be caught and the
-	  kernel itself will be shielded from harm. Enabling this option
-	  may or may not catch stack overflows when the system is in
-	  privileged mode or handling a system call; to ensure these are always
-	  caught, enable CONFIG_HW_STACK_PROTECTION.
-
-config PRIVILEGED_STACK_SIZE
-	int "Size of privileged stack"
-	default 1024
-	depends on ARCH_HAS_USERSPACE
-	help
-	  This option sets the privileged stack region size that will be used
-	  in addition to the user mode thread stack.  During normal execution,
-	  this region will be inaccessible from user mode.  During system calls,
-	  this region will be utilized by the system call. This value must be
-	  a multiple of the minimum stack alignment.
-
-config KOBJECT_TEXT_AREA
-	int "Size if kobject text area"
-	default 512 if COVERAGE_GCOV
-	default 512 if NO_OPTIMIZATIONS
-	default 256
-	depends on ARCH_HAS_USERSPACE
-	help
-	  Size of kernel object text area. Used in linker script.
-
-config GEN_PRIV_STACKS
-	bool
-	help
-	  Selected if the architecture requires that privilege elevation stacks
-	  be allocated in a separate memory area. This is typical of arches
-	  whose MPUs require regions to be power-of-two aligned/sized.
-
-	  FIXME: This should be removed and replaced with checks against
-	  CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT, but both ARM and ARC
-	  changes will be necessary for this.
-
-config STACK_GROWS_UP
-	bool "Stack grows towards higher memory addresses"
-	help
-	  Select this option if the architecture has upward growing thread
-	  stacks. This is not common.
-
-config NO_UNUSED_STACK_INSPECTION
-	bool
-	help
-	  Selected if the architecture will generate a fault if unused stack
-	  memory is examined, which is the region between the current stack
-	  pointer and the deepest available address in the current stack
-	  region.
-
-config MAX_THREAD_BYTES
-	int "Bytes to use when tracking object thread permissions"
-	default 2
-	depends on USERSPACE
-	help
-	  Every kernel object will have an associated bitfield to store
-	  thread permissions for that object. This controls the size of the
-	  bitfield (in bytes) and imposes a limit on how many threads can
-	  be created in the system.
-
-config DYNAMIC_OBJECTS
-	bool "Allow kernel objects to be allocated at runtime"
-	depends on USERSPACE
-	help
-	  Enabling this option allows for kernel objects to be requested from
-	  the calling thread's resource pool, at a slight cost in performance
-	  due to the supplemental run-time tables required to validate such
-	  objects.
-
-	  Objects allocated in this way can be freed with a supervisor-only
-	  API call, or when the number of references to that object drops to
-	  zero.
-
-config NOCACHE_MEMORY
-	bool "Support for uncached memory"
-	depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT
-	help
-	  Add a "nocache" read-write memory section that is configured to
-	  not be cached. This memory section can be used to perform DMA
-	  transfers when cache coherence issues are not optimal or can not
-	  be solved using cache maintenance operations.
-
-menu "Interrupt Configuration"
-
-config DYNAMIC_INTERRUPTS
-	bool "Enable installation of IRQs at runtime"
-	help
-	  Enable installation of interrupts at runtime, which will move some
-	  interrupt-related data structures to RAM instead of ROM, and
-	  on some architectures increase code size.
-
-config GEN_ISR_TABLES
-	bool "Use generated IRQ tables"
-	help
-	  This option controls whether a platform uses the gen_isr_tables
-	  script to generate its interrupt tables. This mechanism will create
-	  an appropriate hardware vector table and/or software IRQ table.
-
-config GEN_IRQ_VECTOR_TABLE
-	bool "Generate an interrupt vector table"
-	default y
-	depends on GEN_ISR_TABLES
-	help
-	  This option controls whether a platform using gen_isr_tables
-	  needs an interrupt vector table created. Only disable this if the
-	  platform does not use a vector table at all, or requires the vector
-	  table to be in a format that is not an array of function pointers
-	  indexed by IRQ line. In the latter case, the vector table must be
-	  supplied by the application or architecture code.
-
-config GEN_SW_ISR_TABLE
-	bool "Generate a software ISR table"
-	default y
-	depends on GEN_ISR_TABLES
-	help
-	  This option controls whether a platform using gen_isr_tables
-	  needs a software ISR table table created. This is an array of struct
-	  _isr_table_entry containing the interrupt service routine and supplied
-	  parameter.
-
-config ARCH_SW_ISR_TABLE_ALIGN
-	int "Alignment size of a software ISR table"
-	default 0
-	depends on GEN_SW_ISR_TABLE
-	help
-	  This option controls alignment size of generated
-	  _sw_isr_table.  Some architecture needs a software ISR table
-	  to be aligned to architecture specific size.  The default
-	  size is 0 for no alignment.
-
-config GEN_IRQ_START_VECTOR
-	int
-	default 0
-	depends on GEN_ISR_TABLES
-	help
-	  On some architectures, part of the vector table may be reserved for
-	  system exceptions and is declared separately from the tables
-	  created by gen_isr_tables.py. When creating these tables, this value
-	  will be subtracted from CONFIG_NUM_IRQS to properly size them.
-	  This is a hidden option which needs to be set per architecture and
-	  left alone.
-
-config IRQ_OFFLOAD
-	bool "Enable IRQ offload"
-	depends on TEST
-	help
-	  Enable irq_offload() API which allows functions to be synchronously
-	  run in interrupt context. Only useful for test cases that need
-	  to validate the correctness of kernel objects in IRQ context.
-
-endmenu # Interrupt configuration
-
-endmenu
-
-#
-# Architecture Capabilities
-#
-
-config ARCH_HAS_TRUSTED_EXECUTION
-	bool
-
-config ARCH_HAS_STACK_PROTECTION
-	bool
-
-config ARCH_HAS_USERSPACE
-	bool
-
-config ARCH_HAS_EXECUTABLE_PAGE_BIT
-	bool
-
-config ARCH_HAS_NOCACHE_MEMORY_SUPPORT
-	bool
-
-config ARCH_HAS_RAMFUNC_SUPPORT
-	bool
-
-config ARCH_HAS_NESTED_EXCEPTION_DETECTION
-	bool
-
-#
-# Other architecture related options
-#
-
-config ARCH_HAS_THREAD_ABORT
-	bool
+endchoice
 
 #
 # Hidden PM feature configs which are to be selected by
 # individual SoC.
 #
-
-config HAS_SYS_POWER_STATE_SLEEP_1
+config SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	# Hidden
 	bool
+	default n
 	help
-	  This option signifies that the target supports the SYS_POWER_STATE_SLEEP_1
-	  configuration option.
+	This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
+	configuration option.
 
-config HAS_SYS_POWER_STATE_SLEEP_2
+config SYS_POWER_DEEP_SLEEP_SUPPORTED
+	# Hidden
 	bool
+	default n
 	help
-	  This option signifies that the target supports the SYS_POWER_STATE_SLEEP_2
-	  configuration option.
-
-config HAS_SYS_POWER_STATE_SLEEP_3
-	bool
-	help
-	  This option signifies that the target supports the SYS_POWER_STATE_SLEEP_3
-	  configuration option.
-
-config HAS_SYS_POWER_STATE_DEEP_SLEEP_1
-	bool
-	help
-	  This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_1
-	  configuration option.
-
-config HAS_SYS_POWER_STATE_DEEP_SLEEP_2
-	bool
-	help
-	  This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_2
-	  configuration option.
-
-config HAS_SYS_POWER_STATE_DEEP_SLEEP_3
-	bool
-	help
-	  This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_3
-	  configuration option.
+	This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
+	configuration option.
 
 config BOOTLOADER_CONTEXT_RESTORE_SUPPORTED
+	# Hidden
 	bool
+	default n
 	help
-	  This option signifies that the target has options of bootloaders
-	  that support context restore upon resume from deep sleep
+	This option signifies that the target has options of bootloaders
+	that support context restore upon resume from deep sleep
 
 #
-# Hidden CPU family configs
+# End hidden PM feature configs
 #
 
-config CPU_HAS_TEE
-	bool
-	help
-	  This option is enabled when the CPU has support for Trusted
-	  Execution Environment (e.g. when it has a security attribution
-	  unit).
-
-config CPU_HAS_DCLS
-	bool
-	help
-	  This option is enabled when the processor hardware is configured in
-	  Dual-redundant Core Lock-step (DCLS) topology.
-
-config CPU_HAS_FPU
-	bool
-	help
-	  This option is enabled when the CPU has hardware floating point
-	  unit.
-
-config CPU_HAS_FPU_DOUBLE_PRECISION
-	bool
-	select CPU_HAS_FPU
-	help
-	  When enabled, this indicates that the CPU has a double floating point
-	  precision unit.
-
-config CPU_HAS_MPU
-	bool
-	help
-	  This option is enabled when the CPU has a Memory Protection Unit (MPU).
-
-config MEMORY_PROTECTION
-	bool
-	help
-	  This option is enabled when Memory Protection features are supported.
-	  Memory protection support is currently available on ARC, ARM, and x86
-	  architectures.
-
-config MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
-	bool
-	help
-	  This option is enabled when the MPU requires a power of two alignment
-	  and size for MPU regions.
-
-config MPU_REQUIRES_NON_OVERLAPPING_REGIONS
-	bool
-	help
-	  This option is enabled when the MPU requires the active (i.e. enabled)
-	  MPU regions to be non-overlapping with each other.
-
-config MPU_GAP_FILLING
-	bool "Force MPU to be filling in background memory regions"
-	depends on MPU_REQUIRES_NON_OVERLAPPING_REGIONS
-	default y if !USERSPACE
-	help
-	  This Kconfig option instructs the MPU driver to enforce
-	  a full kernel SRAM partitioning, when it programs the
-	  dynamic MPU regions (user thread stack, PRIV stack guard
-	  and application memory domains) during context-switch. We
-	  allow this to be a configurable option, in order to be able
-	  to switch the option off and have an increased number of MPU
-	  regions available for application memory domain programming.
-
-	  Notes:
-	  An increased number of MPU regions should only be required,
-	  when building with USERSPACE support. As a result, when we
-	  build without USERSPACE support, gap filling should always
-	  be required.
-
-	  When the option is switched off, access to memory areas not
-	  covered by explicit MPU regions is restricted to privileged
-	  code on an ARCH-specific basis. Refer to ARCH-specific
-	  documentation for more information on how this option is
-	  used.
-
-menu "Floating Point Options"
-
-config FPU
-	bool "Enable floating point unit (FPU)"
-	depends on CPU_HAS_FPU
-	depends on ARC || ARM || RISCV || X86
-	help
-	  This option enables the hardware Floating Point Unit (FPU), in order to
-	  support using the floating point registers and instructions.
-
-	  When this option is enabled, by default, threads may use the floating
-	  point registers only in an exclusive manner, and this usually means that
-	  only one thread may perform floating point operations.
-
-	  If it is necessary for multiple threads to perform concurrent floating
-	  point operations, the "FPU register sharing" option must be enabled to
-	  preserve the floating point registers across context switches.
-
-	  Note that this option cannot be selected for the platforms that do not
-	  include a hardware floating point unit; the floating point support for
-	  those platforms is dependent on the availability of the toolchain-
-	  provided software floating point library.
-
-config FPU_SHARING
-	bool "FPU register sharing"
-	depends on FPU
-	help
-	  This option enables preservation of the hardware floating point registers
-	  across context switches to allow multiple threads to perform concurrent
-	  floating point operations.
-
-endmenu
-
 config ARCH
 	string
 	help
-	  System architecture string.
+	System architecture string.
 
 config SOC
 	string
 	help
-	  SoC name which can be found under soc/<arch>/<soc name>.
-	  This option holds the directory name used by the build system to locate
-	  the correct linker and header files for the SoC.
+	SoC name which can be found under arch/<arch>/soc/<soc name>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files for the SoC. This option will go away
+	once all SoCs are using family/series structure.
 
 config SOC_SERIES
 	string
 	help
-	  SoC series name which can be found under soc/<arch>/<family>/<series>.
-	  This option holds the directory name used by the build system to locate
-	  the correct linker and header files.
+	SoC series name which can be found under arch/<arch>/soc/<family>/<series>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
 
 config SOC_FAMILY
 	string
 	help
-	  SoC family name which can be found under soc/<arch>/<family>.
-	  This option holds the directory name used by the build system to locate
-	  the correct linker and header files.
+	SoC family name which can be found under arch/<arch>/soc/<family>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
 
 config BOARD
 	string
 	help
-	  This option holds the name of the board and is used to locate the files
-	  related to the board in the source tree (under boards/).
-	  The Board is the first location where we search for a linker.ld file,
-	  if not found we look for the linker file in
-	  soc/<arch>/<family>/<series>
+	This option holds the name of the board and is used to located the files
+	related to the board in the source tree (under boards/).
+	The Board is the first location where we search for a linker.ld file,
+	if not found we look for the linker file in
+	arch/<arch>/soc/<family>/<series>
+
+source "arch/*/Kconfig"
+
+source "boards/Kconfig"

arch/Makefile

@@ -0,0 +1 @@
+obj-y += $(ARCH)/

arch/arc/CMakeLists.txt

@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-# Enable debug support in mdb
-# Dwarf version 2 can be recognized by mdb
-# The default dwarf version in gdb is not recognized by mdb
-zephyr_cc_option(-g3 -gdwarf-2)
-
-# Without this (poorly named) option, compiler may generate undefined
-# references to abort().
-# See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63691
-zephyr_cc_option(-fno-delete-null-pointer-checks)
-
-zephyr_cc_option_ifdef(CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS -munaligned-access)
-
-add_subdirectory(core)

arch/arc/Kbuild

@@ -0,0 +1,6 @@
+subdir-ccflags-y +=-I$(srctree)/include/drivers
+subdir-ccflags-y +=-I$(srctree)/drivers
+subdir-asflags-y += $(subdir-ccflags-y)
+
+obj-y += soc/$(SOC_PATH)/
+obj-y += core/

arch/arc/Kconfig

@@ -1,7 +1,28 @@
-# ARC options
+# ARC EM4 options
+
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+choice
+	prompt "ARC SoC Selection"
+	depends on ARC
+
+	source "arch/arc/soc/*/Kconfig.soc"
+endchoice
 
-# Copyright (c) 2014, 2019 Wind River Systems, Inc.
-# SPDX-License-Identifier: Apache-2.0
 
 menu "ARC Options"
 	depends on ARC
@@ -9,70 +30,53 @@ menu "ARC Options"
 config ARCH
 	default "arc"
 
-choice
-	prompt "ARC core family"
-	default CPU_ARCEM
+config ARCH_DEFCONFIG
+	string
+	default "arch/arc/defconfig"
 
-config CPU_ARCEM
-	bool "ARC EM cores"
+menu "ARC EM4 processor options"
+
+config	CPU_ARCEM4
+	bool
+	default y
 	select CPU_ARCV2
 	select ATOMIC_OPERATIONS_C
 	help
-	  This option signifies the use of an ARC EM CPU
+	This option signifies the use of an ARC EM4 CPU
 
-config CPU_ARCHS
-	bool "ARC HS cores"
-	select CPU_ARCV2
-	select ATOMIC_OPERATIONS_BUILTIN
-	help
-	  This option signifies the use of an ARC HS CPU
-
-endchoice
-
-config CPU_EM4
-	bool
-	help
-	  If y, the SoC uses an ARC EM4 CPU
-
-config CPU_EM4_DMIPS
-	bool
-	help
-	  If y, the SoC uses an ARC EM4 DMIPS CPU
-
-config CPU_EM4_FPUS
-	bool
-	help
-	  If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision
-	  floating-point extension
-
-config CPU_EM4_FPUDA
-	bool
-	help
-	  If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision
-	  floating-point and double assist instructions
-
-config CPU_EM6
-	bool
-	help
-	  If y, the SoC uses an ARC EM6 CPU
-
-config FP_FPU_DA
-	bool
+endmenu
 
 menu "ARCv2 Family Options"
 
-config CPU_ARCV2
+config	CPU_ARCV2
 	bool
-	select ARCH_HAS_STACK_PROTECTION if ARC_HAS_STACK_CHECKING || ARC_MPU
-	select ARCH_HAS_USERSPACE if ARC_MPU
-	select USE_SWITCH
-	select USE_SWITCH_SUPPORTED
 	default y
+	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
 	help
 	  This option signifies the use of a CPU of the ARCv2 family.
 
-config NUM_IRQ_PRIO_LEVELS
-	int "Number of supported interrupt priority levels"
+config NSIM
+	prompt "Running on the MetaWare nSIM simulator"
+	bool
+	default n
+	help
+	  For running on nSIM simulator.
+
+	  a) Uses non-XIP to run in RAM.
+	  b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
+	     a pc_size of 16 (default).
+
+config	DATA_ENDIANNESS_LITTLE
+	bool
+	default y
+	help
+	  This is driven by the processor implementation, since it is fixed in
+	  hardware. The BSP should set this value to 'n' if the data is
+	  implemented as big endian.
+
+config	NUM_IRQ_PRIO_LEVELS
+	int
+	prompt "Number of supported interrupt priority levels"
 	range 1 16
 	help
 	  Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
@@ -80,8 +84,9 @@ config NUM_IRQ_PRIO_LEVELS
 
 	  The BSP must provide a valid default for proper operation.
 
-config NUM_IRQS
-	int "Upper limit of interrupt numbers/IDs used"
+config	NUM_IRQS
+	int
+	prompt "Upper limit of interrupt numbers/IDs used"
 	range 17 256
 	help
 	  Interrupts available will be 0 to NUM_IRQS-1.
@@ -91,244 +96,216 @@ config NUM_IRQS
 	  The BSP must provide a valid default. This drives the size of the
 	  vector table.
 
-config RGF_NUM_BANKS
-	int "Number of General Purpose Register Banks"
+config	RGF_NUM_BANKS
+	int
+	prompt "Number of General Purpose Register Banks"
 	depends on CPU_ARCV2
 	range 1 2
 	default 2
 	help
-	  The ARC CPU can be configured to have more than one register
-	  bank. If fast interrupts are supported (FIRQ), the 2nd
-	  register bank, in the set, will be used by FIRQ interrupts.
-	  If fast interrupts are supported but there is only 1
-	  register bank, the fast interrupt handler must save
-	  and restore general purpose registers.
+	The ARC CPU can be configured to have more than one register
+	bank. If fast interrupts are supported (FIRQ), the 2nd
+	register bank, in the set, will be used by FIRQ interrupts.
+	If fast interrupts are supported but there is only 1
+	register bank, the fast interrupt handler must save
+	and restore general purpose regsiters.
 
-config ARC_FIRQ
-	bool "FIRQ enable"
-	default y
-	help
-	  Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts
-	  with highest priority, status32 and pc will be saved in aux regs,
-	  other regs will be saved according to the number of register bank;
-	  If FIRQ is disabled, the handle of interrupts with highest priority
-	  will be same with other interrupts.
-
-config ARC_FIRQ_STACK
-	bool "Enable separate firq stack"
-	depends on ARC_FIRQ && RGF_NUM_BANKS > 1
-	help
-	  Use separate stack for FIRQ handing. When the fast irq is also a direct
-	  irq, this will get the minimal interrupt latency.
-
-config ARC_FIRQ_STACK_SIZE
-	int "FIRQ stack size"
-	depends on ARC_FIRQ_STACK
+config	FIRQ_STACK_SIZE
+	int
+	prompt "Size of stack for FIRQs (in bytes)"
+	depends on CPU_ARCV2
 	default 1024
 	help
-	  The size of firq stack.
+	  FIRQs and regular IRQs have different stacks so that a FIRQ can start
+	  running without doing stack switching in software.
 
-config ARC_HAS_STACK_CHECKING
-	bool "ARC has STACK_CHECKING"
-	default y
+config	ARC_STACK_CHECKING
+	bool "Enable Stack Checking"
+	depends on CPU_ARCV2
+	default n
 	help
-	  ARC is configured with STACK_CHECKING which is a mechanism for
-	  checking stack accesses and raising an exception when a stack
-	  overflow or underflow is detected.
+	  ARCV2 has a special feature allowing to check stack overflows. This
+	  enables code that allows using this debug feature
 
-config ARC_CONNECT
-	bool "ARC has ARC connect"
-	select SCHED_IPI_SUPPORTED
-	help
-	  ARC is configured with ARC CONNECT which is a hardware for connecting
-	  multi cores.
-
-config ARC_STACK_CHECKING
-	bool
-	select NO_UNUSED_STACK_INSPECTION
-	help
-	  Use ARC STACK_CHECKING to do stack protection
-
-config ARC_STACK_PROTECTION
-	bool
-	default y if HW_STACK_PROTECTION
-	select ARC_STACK_CHECKING if ARC_HAS_STACK_CHECKING
-	select MPU_STACK_GUARD if (!ARC_STACK_CHECKING && ARC_MPU && ARC_MPU_VER !=2)
-	select THREAD_STACK_INFO
-	help
-	  This option enables either:
-	  - The ARC stack checking, or
-	  - the MPU-based stack guard
-	  to cause a system fatal error
-	  if the bounds of the current process stack are overflowed.
-	  The two stack guard options are mutually exclusive. The
-	  selection of the ARC stack checking is
-	  prioritized over the MPU-based stack guard.
-
-config ARC_USE_UNALIGNED_MEM_ACCESS
-	bool "Enable unaligned access in HW"
-	default y if CPU_ARCHS
-	depends on (CPU_ARCEM && !ARC_HAS_SECURE) || CPU_ARCHS
-	help
-	  ARC EM cores w/o secure shield 2+2 mode support might be configured
-	  to support unaligned memory access which is then disabled by default.
-	  Enable unaligned access in hardware and make software to use it.
-
-config FAULT_DUMP
-	int "Fault dump level"
+config	FAULT_DUMP
+	int
+	prompt "Fault dump level"
 	default 2
 	range 0 2
 	help
-	  Different levels for display information when a fault occurs.
+	Different levels for display information when a fault occurs.
 
-	  2: The default. Display specific and verbose information. Consumes
+	2: The default. Display specific and verbose information. Consumes
 		the most memory (long strings).
 
-	  1: Display general and short information. Consumes less memory
+	1: Display general and short information. Consumes less memory
 		(short strings).
 
-	  0: Off.
+	0: Off.
 
-config XIP
-	default y if !UART_NSIM
+config IRQ_OFFLOAD
+	bool "Enable IRQ offload"
+	default n
+	help
+	Enable irq_offload() API which allows functions to be synchronously
+	run in interrupt context. Uses one entry in the	IDT.  Mainly useful
+	for test cases.
 
-config GEN_ISR_TABLES
+config	XIP
+	default n if NSIM
 	default y
 
-config GEN_IRQ_START_VECTOR
-	default 16
-
 config HARVARD
-	bool "Harvard Architecture"
+	prompt "Harvard Architecture"
+	bool
+	default n
 	help
 	  The ARC CPU can be configured to have two busses;
 	  one for instruction fetching and another that serves as a data bus.
 
-config CODE_DENSITY
-	bool "Code Density Option"
+config ICCM_SIZE
+	int "ICCM Size in kB"
 	help
-	  Enable code density option to get better code density
+	This option specifies the size of the ICCM in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
 
-config ARC_HAS_ACCL_REGS
-	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
-	default y if FPU
+config ICCM_BASE_ADDRESS
+	hex "ICCM Base Address"
 	help
-	  Depending on the configuration, CPU can contain accumulator reg-pair
-	  (also referred to as r58:r59). These can also be used by gcc as GPR so
-	  kernel needs to save/restore per process
+	This option specifies the base address of the ICCM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
 
-config ARC_HAS_SECURE
-	bool "ARC has SecureShield"
-	select CPU_HAS_TEE
-	select ARCH_HAS_TRUSTED_EXECUTION
+config DCCM_SIZE
+	int "DCCM Size in kB"
 	help
-	  This option is enabled when ARC core supports secure mode
+	This option specifies the size of the DCCM in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
 
-config SJLI_TABLE_SIZE
-	int "SJLI table size"
-	depends on ARC_SECURE_FIRMWARE
-	default 8
+config DCCM_BASE_ADDRESS
+	hex "DCCM Base Address"
 	help
-	  The size of sjli (Secure Jump and Link Indexed) table. The
-	  code in normal mode call secure services in secure mode through
-	  sjli instruction.
+	This option specifies the base address of the DCCM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
 
-config ARC_SECURE_FIRMWARE
-	bool "Generate Secure Firmware"
-	depends on ARC_HAS_SECURE
-	default y if TRUSTED_EXECUTION_SECURE
+config SRAM_SIZE
+	int "SRAM Size in kB"
 	help
-	  This option indicates that we are building a Zephyr image that
-	  is intended to execute in secure mode. The option is only
-	  applicable to ARC processors that implement the SecureShield.
+	This option specifies the size of the SRAM in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
 
-	  This option enables Zephyr to include code that executes in
-	  secure mode, as well as to exclude code that is designed to
-	  execute only in normal mode.
-
-	  Code executing in secure mode has access to both the secure
-	  and normal resources of the ARC processors.
-
-config ARC_NORMAL_FIRMWARE
-	bool "Generate Normal Firmware"
-	depends on !ARC_SECURE_FIRMWARE
-	depends on ARC_HAS_SECURE
-	default y if TRUSTED_EXECUTION_NONSECURE
+config SRAM_BASE_ADDRESS
+	hex "SRAM Base Address"
 	help
-	  This option indicates that we are building a Zephyr image that
-	  is intended to execute in normal mode. Execution of this
-	  image is triggered by secure firmware that executes in secure
-	  mode. The option is only applicable to ARC processors that
-	  implement the SecureShield.
+	This option specifies the base address of the SRAM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
 
-	  This option enables Zephyr to include code that executes in
-	  normal mode only, as well as to exclude code that is
-	  designed to execute only in secure mode.
-
-	  Code executing in normal mode has no access to secure
-	  resources of the ARC processors, and, therefore, it shall avoid
-	  accessing them.
-
-menu "ARC MPU Options"
-depends on CPU_HAS_MPU
-
-config ARC_MPU_ENABLE
-	bool "Enable MPU"
-	select ARC_MPU
+config FLASH_SIZE
+	int "Flash Size in kB"
 	help
-	  Enable MPU
+	This option specifies the size of the flash in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
 
-source "arch/arc/core/mpu/Kconfig"
+config FLASH_BASE_ADDRESS
+	hex "Flash Base Address"
+	help
+	This option specifies the base address of the flash on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
 
-endmenu
+config SW_ISR_TABLE
+	bool
+	prompt "Enable software interrupt handler table"
+	default y
+	help
+	  Enable an interrupt handler table implemented in software. This
+	  table, unlike ISRs connected directly in the vector table, allow
+	  a parameter to be passed to the interrupt handlers. Also, invoking
+	  the exeception/interrupt exit stub is automatically done.
+
+config IRQ_VECTOR_TABLE_CUSTOM
+	bool
+	prompt "Projects provide a custom static IRQ part of vector table"
+	depends on !SW_ISR_TABLE
+	default n
+	help
+	  Projects, not the BSP, provide the IRQ part of the vector table.
+
+	  This is the table of interrupt handlers with the best potential
+	  performance, but is the less flexible.
+
+	  The ISRs are installed directly in the vector table, thus are
+	  directly called by the CPU when an interrupt is taken. This adds
+	  the least overhead when handling an interrupt.
+
+	  Downsides:
+
+	  - ISRs cannot have a parameter
+	  - ISRs cannot be connected at runtime
+	  - ISRs must notify the kernel manually by invoking _ExcExit() when
+	    then are about to return.
+
+config	IRQ_VECTOR_TABLE_BSP
+	bool
+	# omit prompt to signify a "hidden" option
+	depends on SW_ISR_TABLE || !IRQ_VECTOR_TABLE_CUSTOM
+	default y
+	help
+	  Not user-selectable, helps build system logic.
+
+config ARCH_HAS_TASK_ABORT
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
+
+config ARCH_HAS_NANO_FIBER_ABORT
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
 
 config CACHE_LINE_SIZE_DETECT
-	bool "Detect d-cache line size at runtime"
+	bool
+	prompt "Detect d-cache line size at runtime"
+	default n
 	help
-	  This option enables querying the d-cache build register for finding
-	  the d-cache line size at the expense of taking more memory and code
-	  and a slightly increased boot time.
+	This option enables querying the d-cache build register for finding
+	the d-cache line size at the expense of taking more memory and code
+	and a slightly increased boot time.
 
-	  If the CPU's d-cache line size is known in advance, disable this
-	  option and manually enter the value for CACHE_LINE_SIZE.
+	If the CPU's d-cache line size is known in advance, disable this
+	option and manually enter the value for CACHE_LINE_SIZE.
 
 config CACHE_LINE_SIZE
-	int "Cache line size" if !CACHE_LINE_SIZE_DETECT
+	int
+	prompt "Cache line size" if !CACHE_LINE_SIZE_DETECT
 	default 32
 	help
-	  Size in bytes of a CPU d-cache line.
+	Size in bytes of a CPU d-cache line.
 
-	  Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
+	Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
 
 config ARCH_CACHE_FLUSH_DETECT
 	bool
+	default n
 
 config CACHE_FLUSHING
-	bool "Enable d-cache flushing mechanism"
-	help
-	  This links in the sys_cache_flush() function, which provides a
-	  way to flush multiple lines of the d-cache.
-	  If the d-cache is present, set this to y.
-	  If the d-cache is NOT present, set this to n.
-
-config ARC_EXCEPTION_STACK_SIZE
-	int "ARC exception handling stack size"
-	default 768
-	help
-	  Size in bytes of exception handling stack which is at the top of
-	  interrupt stack to get smaller memory footprint because exception
-	  is not frequent. To reduce the impact on interrupt handling,
-	  especially nested interrupt, it cannot be too large.
-
-endmenu
-
-config ARC_EXCEPTION_DEBUG
-	bool "Unhandled exception debugging information"
+	bool
 	default n
-	depends on PRINTK || LOG
+	prompt "Enable d-cache flushing mechanism"
 	help
-	  Print human-readable information about exception vectors, cause codes,
-	  and parameters, at a cost of code/data size for the human-readable
-	  strings.
+	This links in the sys_cache_flush() function, which provides a
+	way to flush multiple lines of the d-cache.
+	If the d-cache is present, set this to y.
+	If the d-cache is NOT present, set this to n.
+
+endmenu
+
+source "arch/arc/soc/*/Kconfig"
 
 endmenu

arch/arc/Makefile

@@ -0,0 +1,15 @@
+cflags-y += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
+cflags-$(CONFIG_ARC_STACK_CHECKING) = $(call cc-option,-fomit-frame-pointer)
+cflags-$(CONFIG_LTO) = $(call cc-option,-flto,)
+
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
+
+KBUILD_CFLAGS += $(cflags-y)
+KBUILD_CXXFLAGS += $(cflags-y)
+
+soc-cxxflags ?= $(soc-cflags)
+soc-aflags ?= $(soc-cflags)
+KBUILD_CFLAGS += $(soc-cflags)
+KBUILD_CXXFLAGS += $(soc-cxxflags)
+KBUILD_AFLAGS += $(soc-aflags)
+

arch/arc/core/CMakeLists.txt

@@ -1,34 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library()
-
-zephyr_library_sources(
-  thread.c
-  thread_entry_wrapper.S
-  cpu_idle.S
-  fatal.c
-  fault.c
-  fault_s.S
-  irq_manage.c
-  timestamp.c
-  isr_wrapper.S
-  regular_irq.S
-  switch.S
-  prep_c.c
-  reset.S
-  vector_table.c
-  )
-
-zephyr_library_sources_ifdef(CONFIG_CACHE_FLUSHING cache.c)
-zephyr_library_sources_ifdef(CONFIG_ARC_FIRQ fast_irq.S)
-
-zephyr_library_sources_if_kconfig(irq_offload.c)
-
-zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
-zephyr_library_sources_ifdef(CONFIG_ARC_CONNECT arc_connect.c)
-zephyr_library_sources_ifdef(CONFIG_ARC_CONNECT arc_smp.c)
-
-add_subdirectory_ifdef(CONFIG_ARC_CORE_MPU mpu)
-add_subdirectory_ifdef(CONFIG_ARC_SECURE_FIRMWARE secureshield)
-
-zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)

arch/arc/core/Makefile

@@ -0,0 +1,20 @@
+ccflags-y += -I$(srctree)/kernel/unified/include
+ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
+
+obj-y += thread.o thread_entry_wrapper.o \
+	cpu_idle.o  fast_irq.o  fatal.o  fault.o  \
+	fault_s.o  irq_manage.o cache.o  \
+	isr_wrapper.o  regular_irq.o  swap_macros.h  swap.o \
+	sys_fatal_error_handler.o
+
+obj-y += prep_c.o \
+         reset.o \
+         vector_table.o
+
+obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
+
+# Some ARC cores like the EM4 lack the atomic LLOCK/SCOND and
+# can't use these.
+obj-$(CONFIG_ATOMIC_OPERATIONS_CUSTOM) += atomic.o
+obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
+obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o

arch/arc/core/arc_connect.c

@@ -1,449 +0,0 @@
-/*
- * Copyright (c) 2019 Synopsys.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief ARCv2 ARC CONNECT driver
- *
- */
-
-#include <kernel.h>
-#include <arch/cpu.h>
-#include <spinlock.h>
-
-
-static struct k_spinlock arc_connect_spinlock;
-
-#define LOCKED(lck) for (k_spinlock_key_t __i = {},			\
-					  __key = k_spin_lock(lck);	\
-			!__i.key;					\
-			k_spin_unlock(lck, __key), __i.key = 1)
-
-
-/* Generate an inter-core interrupt to the target core */
-void z_arc_connect_ici_generate(u32_t core)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_INTRPT_GENERATE_IRQ, core);
-	}
-}
-
-/* Acknowledge the inter-core interrupt raised by core */
-void z_arc_connect_ici_ack(u32_t core)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_INTRPT_GENERATE_ACK, core);
-	}
-}
-
-/* Read inter-core interrupt status */
-u32_t z_arc_connect_ici_read_status(u32_t core)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_INTRPT_READ_STATUS, core);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/* Check the source of inter-core interrupt */
-u32_t z_arc_connect_ici_check_src(void)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_INTRPT_CHECK_SOURCE, 0);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/* Clear the inter-core interrupt */
-void z_arc_connect_ici_clear(void)
-{
-	u32_t cpu, c;
-
-	LOCKED(&arc_connect_spinlock) {
-
-		z_arc_connect_cmd(ARC_CONNECT_CMD_INTRPT_CHECK_SOURCE, 0);
-		cpu = z_arc_connect_cmd_readback(); /* 1,2,4,8... */
-	/*
-	 * In rare case, multiple concurrent ICIs sent to same target can
-	 * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpu can be
-	 * "vectored" (multiple bits sets) as opposed to typical single bit
-	 */
-		while (cpu) {
-			c = find_lsb_set(cpu) - 1;
-			z_arc_connect_cmd(
-				ARC_CONNECT_CMD_INTRPT_GENERATE_ACK, c);
-			cpu &= ~(1U << c);
-		}
-	}
-}
-
-/* Reset the cores in core_mask */
-void z_arc_connect_debug_reset(u32_t core_mask)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_DEBUG_RESET,
-			0, core_mask);
-	}
-}
-
-/* Halt the cores in core_mask */
-void z_arc_connect_debug_halt(u32_t core_mask)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_DEBUG_HALT,
-			0, core_mask);
-	}
-}
-
-/* Run the cores in core_mask */
-void z_arc_connect_debug_run(u32_t core_mask)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_DEBUG_RUN,
-			0, core_mask);
-	}
-}
-
-/* Set core mask */
-void z_arc_connect_debug_mask_set(u32_t core_mask, u32_t mask)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_DEBUG_SET_MASK,
-			mask, core_mask);
-	}
-}
-
-/* Read core mask */
-u32_t z_arc_connect_debug_mask_read(u32_t core_mask)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_DEBUG_READ_MASK,
-			0, core_mask);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/*
- * Select cores that should be halted if the core issuing the command is halted
- */
-void z_arc_connect_debug_select_set(u32_t core_mask)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_DEBUG_SET_SELECT,
-			0, core_mask);
-	}
-}
-
-/* Read the select value */
-u32_t z_arc_connect_debug_select_read(void)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_DEBUG_READ_SELECT, 0);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/* Read the status, halt or run of all cores in the system */
-u32_t z_arc_connect_debug_en_read(void)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_DEBUG_READ_EN, 0);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/* Read the last command sent */
-u32_t z_arc_connect_debug_cmd_read(void)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_DEBUG_READ_CMD, 0);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/* Read the value of internal MCD_CORE register */
-u32_t z_arc_connect_debug_core_read(void)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_DEBUG_READ_CORE, 0);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/* Clear global free running counter */
-void z_arc_connect_gfrc_clear(void)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_GFRC_CLEAR, 0);
-	}
-}
-
-/* Read total 64 bits of global free running counter */
-u64_t z_arc_connect_gfrc_read(void)
-{
-	u32_t low;
-	u32_t high;
-	u32_t key;
-
-	/*
-	 * each core has its own arc connect interface, i.e.,
-	 * CMD/READBACK. So several concurrent commands to ARC
-	 * connect are of if they are trying to access different
-	 * sub-components. For GFRC, HW allows simultaneously accessing to
-	 * counters. So an irq lock is enough.
-	 */
-	key = arch_irq_lock();
-
-	z_arc_connect_cmd(ARC_CONNECT_CMD_GFRC_READ_LO, 0);
-	low = z_arc_connect_cmd_readback();
-
-	z_arc_connect_cmd(ARC_CONNECT_CMD_GFRC_READ_HI, 0);
-	high = z_arc_connect_cmd_readback();
-
-	arch_irq_unlock(key);
-
-	return (((u64_t)high) << 32) | low;
-}
-
-/* Enable global free running counter */
-void z_arc_connect_gfrc_enable(void)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_GFRC_ENABLE, 0);
-	}
-}
-
-/* Disable global free running counter */
-void z_arc_connect_gfrc_disable(void)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_GFRC_DISABLE, 0);
-	}
-}
-
-/* Disable global free running counter */
-void z_arc_connect_gfrc_core_set(u32_t core_mask)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_GFRC_SET_CORE,
-			0, core_mask);
-	}
-}
-
-/* Set the relevant cores to halt global free running counter */
-u32_t z_arc_connect_gfrc_halt_read(void)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_GFRC_READ_HALT, 0);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/* Read the internal CORE register */
-u32_t z_arc_connect_gfrc_core_read(void)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_GFRC_READ_CORE, 0);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/* Enable interrupt distribute unit */
-void z_arc_connect_idu_enable(void)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_IDU_ENABLE, 0);
-	}
-}
-
-/* Disable interrupt distribute unit */
-void z_arc_connect_idu_disable(void)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_IDU_DISABLE, 0);
-	}
-}
-
-/* Read enable status of interrupt distribute unit */
-u32_t z_arc_connect_idu_read_enable(void)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_IDU_READ_ENABLE, 0);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/*
- * Set the triggering mode and distribution mode for the specified common
- * interrupt
- */
-void z_arc_connect_idu_set_mode(u32_t irq_num,
-	u16_t trigger_mode, u16_t distri_mode)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_IDU_SET_MODE,
-			irq_num, (distri_mode | (trigger_mode << 4)));
-	}
-}
-
-/* Read the internal MODE register of the specified common interrupt */
-u32_t z_arc_connect_idu_read_mode(u32_t irq_num)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_IDU_READ_MODE, irq_num);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/*
- * Set the target cores to receive the specified common interrupt
- * when it is triggered
- */
-void z_arc_connect_idu_set_dest(u32_t irq_num, u32_t core_mask)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_IDU_SET_DEST,
-			irq_num, core_mask);
-	}
-}
-
-/* Read the internal DEST register of the specified common interrupt */
-u32_t z_arc_connect_idu_read_dest(u32_t irq_num)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_IDU_READ_DEST, irq_num);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/* Assert the specified common interrupt */
-void z_arc_connect_idu_gen_cirq(u32_t irq_num)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_IDU_GEN_CIRQ, irq_num);
-	}
-}
-
-/* Acknowledge the specified common interrupt */
-void z_arc_connect_idu_ack_cirq(u32_t irq_num)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_IDU_ACK_CIRQ, irq_num);
-	}
-}
-
-/* Read the internal STATUS register of the specified common interrupt */
-u32_t z_arc_connect_idu_check_status(u32_t irq_num)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_IDU_CHECK_STATUS, irq_num);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/* Read the internal SOURCE register of the specified common interrupt */
-u32_t z_arc_connect_idu_check_source(u32_t irq_num)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_IDU_CHECK_SOURCE, irq_num);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/* Mask or unmask the specified common interrupt */
-void z_arc_connect_idu_set_mask(u32_t irq_num, u32_t mask)
-{
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_IDU_SET_MASK,
-			irq_num, mask);
-	}
-}
-
-/* Read the internal MASK register of the specified common interrupt */
-u32_t z_arc_connect_idu_read_mask(u32_t irq_num)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_IDU_READ_MASK, irq_num);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-}
-
-/*
- * Check if it is the first-acknowledging core to the common interrupt
- * if IDU is programmed in the first-acknowledged mode
- */
-u32_t z_arc_connect_idu_check_first(u32_t irq_num)
-{
-	u32_t ret = 0;
-
-	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd(ARC_CONNECT_CMD_IDU_CHECK_FIRST, irq_num);
-		ret = z_arc_connect_cmd_readback();
-	}
-
-	return ret;
-
-}

arch/arc/core/arc_smp.c

@@ -1,151 +0,0 @@
-/*
- * Copyright (c) 2019 Synopsys.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief codes required for ARC multicore and Zephyr smp support
- *
- */
-#include <device.h>
-#include <kernel.h>
-#include <kernel_structs.h>
-#include <ksched.h>
-#include <soc.h>
-#include <init.h>
-
-
-#ifndef IRQ_ICI
-#define IRQ_ICI 19
-#endif
-
-#define ARCV2_ICI_IRQ_PRIORITY 1
-
-volatile struct {
-	arch_cpustart_t fn;
-	void *arg;
-} arc_cpu_init[CONFIG_MP_NUM_CPUS];
-
-/*
- * arc_cpu_wake_flag is used to sync up master core and slave cores
- * Slave core will spin for arc_cpu_wake_flag until master core sets
- * it to the core id of slave core. Then, slave core clears it to notify
- * master core that it's waken
- *
- */
-volatile u32_t arc_cpu_wake_flag;
-
-volatile char *arc_cpu_sp;
-/*
- * _curr_cpu is used to record the struct of _cpu_t of each cpu.
- * for efficient usage in assembly
- */
-volatile _cpu_t *_curr_cpu[CONFIG_MP_NUM_CPUS];
-
-/* Called from Zephyr initialization */
-void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
-		    arch_cpustart_t fn, void *arg)
-{
-	_curr_cpu[cpu_num] = &(_kernel.cpus[cpu_num]);
-	arc_cpu_init[cpu_num].fn = fn;
-	arc_cpu_init[cpu_num].arg = arg;
-
-	/* set the initial sp of target sp through arc_cpu_sp
-	 * arc_cpu_wake_flag will protect arc_cpu_sp that
-	 * only one slave cpu can read it per time
-	 */
-	arc_cpu_sp = Z_THREAD_STACK_BUFFER(stack) + sz;
-
-	arc_cpu_wake_flag = cpu_num;
-
-	/* wait slave cpu to start */
-	while (arc_cpu_wake_flag != 0) {
-		;
-	}
-}
-
-/* the C entry of slave cores */
-void z_arc_slave_start(int cpu_num)
-{
-	arch_cpustart_t fn;
-
-#ifdef CONFIG_SMP
-	z_icache_setup();
-	z_irq_setup();
-
-	z_arc_connect_ici_clear();
-	z_irq_priority_set(IRQ_ICI, ARCV2_ICI_IRQ_PRIORITY, 0);
-	irq_enable(IRQ_ICI);
-#endif
-	/* call the function set by arch_start_cpu */
-	fn = arc_cpu_init[cpu_num].fn;
-
-	fn(arc_cpu_init[cpu_num].arg);
-}
-
-#ifdef CONFIG_SMP
-
-static void sched_ipi_handler(void *unused)
-{
-	ARG_UNUSED(unused);
-
-	z_arc_connect_ici_clear();
-	z_sched_ipi();
-}
-
-/* arch implementation of sched_ipi */
-void arch_sched_ipi(void)
-{
-	u32_t i;
-
-	/* broadcast sched_ipi request to other cores
-	 * if the target is current core, hardware will ignore it
-	 */
-	for (i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
-		z_arc_connect_ici_generate(i);
-	}
-}
-
-static int arc_smp_init(struct device *dev)
-{
-	ARG_UNUSED(dev);
-	struct arc_connect_bcr bcr;
-
-	/* necessary master core init */
-	_curr_cpu[0] = &(_kernel.cpus[0]);
-
-	bcr.val = z_arc_v2_aux_reg_read(_ARC_V2_CONNECT_BCR);
-
-	if (bcr.ipi) {
-	/* register ici interrupt, just need master core to register once */
-		z_arc_connect_ici_clear();
-		IRQ_CONNECT(IRQ_ICI, ARCV2_ICI_IRQ_PRIORITY,
-		    sched_ipi_handler, NULL, 0);
-
-		irq_enable(IRQ_ICI);
-	} else {
-		__ASSERT(0,
-			"ARC connect has no inter-core interrupt\n");
-		return -ENODEV;
-	}
-
-	if (bcr.gfrc) {
-		/* global free running count init */
-		z_arc_connect_gfrc_enable();
-
-		/* when all cores halt, gfrc halt */
-		z_arc_connect_gfrc_core_set((1 << CONFIG_MP_NUM_CPUS) - 1);
-		z_arc_connect_gfrc_clear();
-	} else {
-		__ASSERT(0,
-			"ARC connect has no global free running counter\n");
-		return -ENODEV;
-	}
-
-	return 0;
-}
-
-SYS_INIT(arc_smp_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-#endif

arch/arc/core/atomic.S

@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief ARC atomic operations library
+ *
+ * This library provides routines to perform a number of atomic operations
+ * on a memory location: add, subtract, increment, decrement, bitwise OR,
+ * bitwise NOR, bitwise AND, bitwise NAND, set, clear and compare-and-swap.
+ *
+ * This requires the processor to support LLOCK and SCOND instructions,
+ * where they are not supported on ARC EM family processors.
+ */
+
+#define _ASMLANGUAGE
+
+#include <toolchain.h>
+#include <sections.h>
+
+/* exports */
+
+GTEXT(atomic_set)
+GTEXT(atomic_get)
+GTEXT(atomic_add)
+GTEXT(atomic_nand)
+GTEXT(atomic_and)
+GTEXT(atomic_or)
+GTEXT(atomic_xor)
+GTEXT(atomic_clear)
+GTEXT(atomic_dec)
+GTEXT(atomic_inc)
+GTEXT(atomic_sub)
+GTEXT(atomic_cas)
+
+	.section .TEXT._Atomic, "ax"
+	.balign  2
+
+/**
+ *
+ * @brief Atomically clear a memory location
+ *
+ * This routine atomically clears the contents of <target> and returns the old
+ * value that was in <target>.
+ *
+ * This routine can be used from both task and interrupt level.
+ *
+ * @return Contents of <target> before the atomic operation
+ *
+ * ERRNO: N/A
+ *
+ * atomic_val_t atomic_clear
+ *    (
+ *    atomic_t *target	/@ memory location to clear @/
+ *    )
+ */
+
+SECTION_SUBSEC_FUNC(TEXT, atomic_clear_set, atomic_clear)
+	mov_s r1, 0
+	/* fall through into atomic_set */
+
+/**
+ *
+ * @brief Atomically set a memory location
+ *
+ * This routine atomically sets the contents of <target> to <value> and returns
+ * the old value that was in <target>.
+ *
+ * This routine can be used from both task and interrupt level.
+ *
+ * @return Contents of <target> before the atomic operation
+ *
+ * ERRNO: N/A
+ *
+ * atomic_val_t atomic_set
+ *    (
+ *    atomic_t *target,	/@ memory location to set @/
+ *    atomic_val_t value	/@ set with this value @/
+ *    )
+ *
+ */
+
+SECTION_SUBSEC_FUNC(TEXT, atomic_clear_set, atomic_set)
+
+	ex r1, [r0]		/* swap new value with old value */
+
+	j_s.d [blink]
+	mov_s r0, r1		/* return old value */
+
+/**
+ *
+ * @brief Get the value of a shared memory atomically
+ *
+ * This routine atomically retrieves the value in *target
+ *
+ * atomic_val_t atomic_get
+ *     (
+ *     atomic_t *target    /@ address of atom to be retrieved @/
+ *     )
+ *
+ * RETURN: value read from address target.
+ *
+ */
+
+SECTION_FUNC(TEXT, atomic_get)
+	ld_s r0, [r0, 0]
+	j_s [blink]
+
+/**
+ *
+ * @brief Atomically increment a memory location
+ *
+ * This routine atomically increments the value in <target>.  The operation is
+ * done using unsigned integer arithmetic.  Various CPU architectures may impose
+ * restrictions with regards to the alignment and cache attributes of the
+ * atomic_t type.
+ *
+ * This routine can be used from both task and interrupt level.
+ *
+ * @return Contents of <target> before the atomic operation
+ *
+ * ERRNO: N/A
+ *
+ * atomic_val_t atomic_inc
+ *    (
+ *    atomic_t *target,	/@ memory location to increment @/
+ *    )
+ *
+ */
+
+SECTION_SUBSEC_FUNC(TEXT, atomic_inc_add, atomic_inc)
+	mov_s r1, 1
+	/* fall through into atomic_add */
+
+/**
+ *
+ * @brief Atomically add a value to a memory location
+ *
+ * This routine atomically adds the contents of <target> and <value>, placing
+ * the result in <target>. The operation is done using signed integer arithmetic.
+ * Various CPU architectures may impose restrictions with regards to the
+ * alignment and cache attributes of the atomic_t type.
+ *
+ * This routine can be used from both task and interrupt level.
+ *
+ * @return Contents of <target> before the atomic operation
+ *
+ * ERRNO: N/A
+ *
+ * atomic_val_t atomic_add
+ *    (
+ *    atomic_t *target,	/@ memory location to add to @/
+ *    atomic_val_t value	/@ value to add @/
+ *    )
+ */
+
+SECTION_SUBSEC_FUNC(TEXT, atomic_inc_add, atomic_add)
+
+	llock r2, [r0]	/* load old value and mark exclusive access */
+	add_s r3, r1, r2
+	scond r3, [r0]	/* try to store new value */
+
+	/* STATUS32.Z = 1 if successful */
+
+	bne_s atomic_add  /* if store is not successful, retry */
+
+	j_s.d [blink]
+	mov_s r0, r2		/* return old value */
+
+/**
+ *
+ * @brief Atomically decrement a memory location
+ *
+ * This routine atomically decrements the value in <target>.  The operation is
+ * done using unsigned integer arithmetic.  Various CPU architectures may impose
+ * restrictions with regards to the alignment and cache attributes of the
+ * atomic_t type.
+ *
+ * This routine can be used from both task and interrupt level.
+ *
+ * @return Contents of <target> before the atomic operation
+ *
+ * ERRNO: N/A
+ *
+ * atomic_val_t atomic_dec
+ *    (
+ *    atomic_t *target,	/@ memory location to decrement @/
+ *    )
+ *
+ */
+
+SECTION_SUBSEC_FUNC(TEXT, atomic_dec_sub, atomic_dec)
+	mov_s r1, 1
+	/* fall through into atomic_sub */
+
+/**
+ *
+ * @brief Atomically subtract a value from a memory location
+ *
+ * This routine atomically subtracts <value> from the contents of <target>,
+ * placing the result in <target>.  The operation is done using signed integer
+ * arithmetic. Various CPU architectures may impose restrictions with regards to
+ * the alignment and cache attributes of the atomic_t type.
+ *
+ * This routine can be used from both task and interrupt level.
+ *
+ * @return Contents of <target> before the atomic operation
+ *
+ * ERRNO: N/A
+ *
+ * atomic_val_t atomic_sub
+ *    (
+ *    atomic_t *target,	/@ memory location to subtract from @/
+ *    atomic_val_t value	/@ value to subtract @/
+ *    )
+ *
+ */
+
+SECTION_SUBSEC_FUNC(TEXT, atomic_dec_sub, atomic_sub)
+
+	llock r2, [r0]	/* load old value and mark exclusive access */
+	sub r3, r2, r1
+	scond r3, [r0]	/* try to store new value */
+
+	/* STATUS32.Z = 1 if successful */
+
+	bne_s atomic_sub  /* if store is not successful, retry */
+
+	j_s.d [blink]
+	mov_s r0, r2		/* return old value */
+
+/**
+ *
+ * @brief Atomically perform a bitwise NAND on a memory location
+ *
+ * This routine atomically performs a bitwise NAND operation of the contents of
+ * <target> and <value>, placing the result in <target>.
+ * Various CPU architectures may impose restrictions with regards to the
+ * alignment and cache attributes of the atomic_t type.
+ *
+ * This routine can be used from both task and interrupt level.
+ *
+ * @return Contents of <target> before the atomic operation
+ *
+ * ERRNO: N/A
+ *
+ * atomic_val_t atomic_nand
+ *    (
+ *    atomic_t *target,	/@ memory location to NAND @/
+ *    atomic_val_t value	/@ NAND with this value @/
+ *    )
+ *
+ */
+
+SECTION_FUNC(TEXT, atomic_nand)
+
+	llock r2, [r0]	/* load old value and mark exclusive access */
+	and r3, r1, r2
+	not r3, r3
+	scond r3, [r0]	/* try to store new value */
+
+	/* STATUS32.Z = 1 if successful */
+
+	bne_s atomic_nand  /* if store is not successful, retry */
+
+	j_s.d [blink]
+	mov_s r0, r2		/* return old value */
+
+/**
+ *
+ * @brief Atomically perform a bitwise AND on a memory location
+ *
+ * This routine atomically performs a bitwise AND operation of the contents of
+ * <target> and <value>, placing the result in <target>.
+ * Various CPU architectures may impose restrictions with regards to the
+ * alignment and cache attributes of the atomic_t type.
+ *
+ * This routine can be used from both task and interrupt level.
+ *
+ * @return Contents of <target> before the atomic operation
+ *
+ * ERRNO: N/A
+ *
+ * atomic_val_t atomic_and
+ *    (
+ *    atomic_t *target,	/@ memory location to AND @/
+ *    atomic_val_t value	/@ AND with this value @/
+ *    )
+ *
+ */
+
+SECTION_FUNC(TEXT, atomic_and)
+
+	llock r2, [r0]	/* load old value and mark exclusive access */
+	and r3, r1, r2
+	scond r3, [r0]	/* try to store new value */
+
+	/* STATUS32.Z = 1 if successful */
+
+	bne_s atomic_and  /* if store is not successful, retry */
+
+	j_s.d [blink]
+	mov_s r0, r2		/* return old value */
+
+/**
+ *
+ * @brief Atomically perform a bitwise OR on memory location
+ *
+ * This routine atomically performs a bitwise OR operation of the contents of
+ * <target> and <value>, placing the result in <target>.
+ * Various CPU architectures may impose restrictions with regards to the
+ * alignment and cache attributes of the atomic_t type.
+ *
+ * This routine can be used from both task and interrupt level.
+ *
+ * @return Contents of <target> before the atomic operation
+ *
+ * ERRNO: N/A
+ *
+ * atomic_val_t atomic_or
+ *    (
+ *    atomic_t *target,	/@ memory location to OR @/
+ *    atomic_val_t value	/@ OR with this value @/
+ *    )
+ *
+ */
+
+SECTION_FUNC(TEXT, atomic_or)
+
+	llock r2, [r0]	/* load old value and mark exclusive access */
+	or r3, r1, r2
+	scond r3, [r0]	/* try to store new value */
+
+	/* STATUS32.Z = 1 if successful */
+
+	bne_s atomic_or  /* if store is not successful, retry */
+
+	j_s.d [blink]
+	mov_s r0, r2		/* return old value */
+
+/**
+ *
+ * @brief Atomically perform a bitwise XOR on a memory location
+ *
+ * This routine atomically performs a bitwise XOR operation of the contents of
+ * <target> and <value>, placing the result in <target>.
+ * Various CPU architectures may impose restrictions with regards to the
+ * alignment and cache attributes of the atomic_t type.
+ *
+ * This routine can be used from both task and interrupt level.
+ *
+ * @return Contents of <target> before the atomic operation
+ *
+ * ERRNO: N/A
+ *
+ * atomic_val_t atomic_xor
+ *    (
+ *    atomic_t *target,	/@ memory location to XOR @/
+ *    atomic_val_t value	/@ XOR with this value @/
+ *    )
+ *
+ */
+
+SECTION_FUNC(TEXT, atomic_xor)
+
+	llock r2, [r0]	/* load old value and mark exclusive access */
+	xor r3, r1, r2
+	scond r3, [r0]	/* try to store new value */
+
+	/* STATUS32.Z = 1 if successful */
+
+	bne_s atomic_xor  /* if store is not successful, retry */
+
+	j_s.d [blink]
+	mov_s r0, r2		/* return old value */
+
+/**
+ *
+ * @brief Atomically compare-and-swap the contents of a memory location
+ *
+ * This routine performs an atomic compare-and-swap. testing that the contents of
+ * <target> contains <oldValue>, and if it does, setting the value of <target>
+ * to <newValue>. Various CPU architectures may impose restrictions with regards
+ * to the alignment and cache attributes of the atomic_t type.
+ *
+ * This routine can be used from both task and interrupt level.
+ *
+ * @return 1 if the swap is actually executed, 0 otherwise.
+ *
+ * ERRNO: N/A
+ *
+ * int atomic_cas
+ *    (
+ *    atomic_t *target,	    /@ memory location to compare-and-swap @/
+ *    atomic_val_t oldValue,	/@ compare to this value @/
+ *    atomic_val_t newValue,	/@ swap with this value @/
+ *    )
+ *
+ */
+
+SECTION_FUNC(TEXT, atomic_cas)
+
+	llock r3, [r0]	/* load old value and mark exclusive access */
+	cmp_s r1, r3
+
+	bne_s nanoAtomicCas_fail
+
+	scond r2, [r0]	/* try to store new value */
+
+	/* STATUS32.Z = 1 if successful */
+
+	bne_s atomic_cas  /* if store is not successful, retry */
+
+	j_s.d [blink]
+	mov_s r0, 1		/* return TRUE */
+
+	/* failed comparison */
+nanoAtomicCas_fail:
+	scond r1, [r0]	/* write old value to clear the access lock */
+	j_s.d [blink]
+	mov_s r0, 0	/* return FALSE */

arch/arc/core/cache.c

@@ -3,7 +3,17 @@
 /*
  * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -13,17 +23,18 @@
  * This module contains functions for manipulation of the d-cache.
  */
 
-#include <kernel.h>
+#include <nanokernel.h>
 #include <arch/cpu.h>
-#include <sys/util.h>
+#include <misc/util.h>
 #include <toolchain.h>
 #include <cache.h>
-#include <linker/linker-defs.h>
+#include <linker-defs.h>
 #include <arch/arc/v2/aux_regs.h>
-#include <kernel_internal.h>
-#include <sys/__assert.h>
+#include <nano_internal.h>
+#include <misc/__assert.h>
 #include <init.h>
-#include <stdbool.h>
+
+#if defined(CONFIG_CACHE_FLUSHING)
 
 #if (CONFIG_CACHE_LINE_SIZE == 0) && !defined(CONFIG_CACHE_LINE_SIZE_DETECT)
 #error Cannot use this implementation with a cache line size of 0
@@ -47,19 +58,19 @@
 #define DC_CTRL_OP_SUCCEEDED         0x4  /* d-cache operation succeeded */
 
 
-static bool dcache_available(void)
+static int dcache_available(void)
 {
-	unsigned long val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+	unsigned long val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
 
 	val &= 0xff; /* extract version */
-	return (val == 0) ? false : true;
+	return (val == 0)?0:1;
 }
 
-static void dcache_dc_ctrl(u32_t dcache_en_mask)
+static void dcache_dc_ctrl(uint32_t dcache_en_mask)
 {
-	if (dcache_available()) {
-		z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, dcache_en_mask);
-	}
+	if (!dcache_available())
+		return;
+	_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, dcache_en_mask);
 }
 
 static void dcache_enable(void)
@@ -84,36 +95,35 @@ static void dcache_enable(void)
  *
  * @return N/A
  */
-static void dcache_flush_mlines(u32_t start_addr, u32_t size)
+static void dcache_flush_mlines(uint32_t start_addr, uint32_t size)
 {
-	u32_t end_addr;
+	uint32_t end_addr;
 	unsigned int key;
 
-	if (!dcache_available() || (size == 0U)) {
+	if (!dcache_available() || (size == 0)) {
 		return;
 	}
 
 	end_addr = start_addr + size - 1;
-	start_addr &= (u32_t)(~(DCACHE_LINE_SIZE - 1));
+	start_addr &= (uint32_t)(~(DCACHE_LINE_SIZE - 1));
 
-	key = arch_irq_lock(); /* --enter critical section-- */
+	key = irq_lock(); /* --enter critical section-- */
 
 	do {
-		z_arc_v2_aux_reg_write(_ARC_V2_DC_FLDL, start_addr);
+		_arc_v2_aux_reg_write(_ARC_V2_DC_FLDL, start_addr);
 		__asm__ volatile("nop_s");
 		__asm__ volatile("nop_s");
 		__asm__ volatile("nop_s");
 		/* wait for flush completion */
 		do {
-			if ((z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) &
-			     DC_CTRL_FLUSH_STATUS) == 0) {
+			if ((_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) &
+				DC_CTRL_FLUSH_STATUS) == 0)
 				break;
-			}
 		} while (1);
 		start_addr += DCACHE_LINE_SIZE;
 	} while (start_addr <= end_addr);
 
-	arch_irq_unlock(key); /* --exit critical section-- */
+	irq_unlock(key); /* --exit critical section-- */
 
 }
 
@@ -137,7 +147,7 @@ static void dcache_flush_mlines(u32_t start_addr, u32_t size)
 
 void sys_cache_flush(vaddr_t start_addr, size_t size)
 {
-	dcache_flush_mlines((u32_t)start_addr, (u32_t)size);
+	dcache_flush_mlines((uint32_t)start_addr, (uint32_t)size);
 }
 
 
@@ -145,12 +155,12 @@ void sys_cache_flush(vaddr_t start_addr, size_t size)
 size_t sys_cache_line_size;
 static void init_dcache_line_size(void)
 {
-	u32_t val;
+	uint32_t val;
 
-	val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
-	__ASSERT((val&0xff) != 0U, "d-cache is not present");
+	val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+	__ASSERT((val&0xff) != 0, "d-cache is not present");
 	val = ((val>>16) & 0xf) + 1;
-	val *= 16U;
+	val *= 16;
 	sys_cache_line_size = (size_t) val;
 }
 #endif
@@ -169,3 +179,6 @@ static int init_dcache(struct device *unused)
 }
 
 SYS_INIT(init_dcache, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_CACHE_FLUSHING */
+

arch/arc/core/cpu_idle.S

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -11,18 +21,19 @@
  * CPU power management routines.
  */
 
+#define _ASMLANGUAGE
+
 #include <kernel_structs.h>
 #include <offsets_short.h>
 #include <toolchain.h>
-#include <linker/sections.h>
+#include <sections.h>
 #include <arch/cpu.h>
 
-GTEXT(arch_cpu_idle)
-GTEXT(arch_cpu_atomic_idle)
-GDATA(z_arc_cpu_sleep_mode)
+GTEXT(nano_cpu_idle)
+GTEXT(nano_cpu_atomic_idle)
+GDATA(nano_cpu_sleep_mode)
 
-SECTION_VAR(BSS, z_arc_cpu_sleep_mode)
-	.balign 4
+SECTION_VAR(BSS, nano_cpu_sleep_mode)
 	.word 0
 
 /*
@@ -33,30 +44,17 @@ SECTION_VAR(BSS, z_arc_cpu_sleep_mode)
  * void nanCpuIdle(void)
  */
 
-SECTION_FUNC(TEXT, arch_cpu_idle)
+SECTION_FUNC(TEXT, nano_cpu_idle)
 
-#ifdef CONFIG_TRACING
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
 	push_s blink
-	jl    sys_trace_idle
+	jl    _sys_k_event_logger_enter_sleep
 	pop_s blink
 #endif
 
-	ld r1, [z_arc_cpu_sleep_mode]
+	ld r1, [nano_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
-/*
- * It's found that (in nsim_hs_smp), when cpu
- * is sleeping, no response to inter-processor interrupt
- * although it's pending and interrupts are enabled.
- * (Here fire SNPS JIRA issue P10019563-41294 to trace)
- * here is a workround
- */
-#if defined(CONFIG_SOC_NSIM) && defined(CONFIG_SMP)
-	seti r1
-_z_arc_idle_loop:
-	b _z_arc_idle_loop
-#else
 	sleep r1
-#endif
 	j_s [blink]
 	nop
 
@@ -65,17 +63,17 @@ _z_arc_idle_loop:
  *
  * This function exits with interrupts restored to <key>.
  *
- * void arch_cpu_atomic_idle(unsigned int key)
+ * void nano_cpu_atomic_idle(unsigned int key)
  */
-SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
+SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
 
-#ifdef CONFIG_TRACING
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
 	push_s blink
-	jl    sys_trace_idle
+	jl    _sys_k_event_logger_enter_sleep
 	pop_s blink
 #endif
 
-	ld r1, [z_arc_cpu_sleep_mode]
+	ld r1, [nano_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
 	j_s.d [blink]

arch/arc/core/fast_irq.S

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -13,15 +23,35 @@
  * See isr_wrapper.S for details.
  */
 
+#define _ASMLANGUAGE
+
 #include <kernel_structs.h>
 #include <offsets_short.h>
 #include <toolchain.h>
-#include <linker/sections.h>
 #include <arch/cpu.h>
-#include <swap_macros.h>
+#include "swap_macros.h"
 
 GTEXT(_firq_enter)
 GTEXT(_firq_exit)
+GTEXT(_firq_stack_setup)
+
+#if CONFIG_RGF_NUM_BANKS != 1
+GDATA(_firq_stack)
+GTEXT(_is_next_thread_current)
+
+SECTION_VAR(NOINIT, _firq_stack)
+	.space CONFIG_FIRQ_STACK_SIZE
+#else
+GDATA(saved_r0)
+#endif
+
+.macro _firq_return
+#if CONFIG_RGF_NUM_BANKS == 1
+	b _firq_no_reschedule
+#else
+	rtie
+#endif
+.endm
 
 /**
  *
@@ -46,27 +76,24 @@ GTEXT(_firq_exit)
  */
 
 SECTION_FUNC(TEXT, _firq_enter)
+
 /*
  * ATTENTION:
  * If CONFIG_RGF_NUM_BANKS>1, firq uses a 2nd register bank so GPRs do
  * not need to be saved.
  * If CONFIG_RGF_NUM_BANKS==1, firq must use the stack to save registers.
- * This has already been done by _isr_wrapper.
+ * This has already been done by _isr_enter.
  */
+
 #ifdef CONFIG_ARC_STACK_CHECKING
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	lr r2, [_ARC_V2_SEC_STAT]
-	bclr r2, r2, _ARC_V2_SEC_STAT_SSC_BIT
-	sflag r2
-#else
 	/* disable stack checking */
 	lr r2, [_ARC_V2_STATUS32]
 	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
 	kflag r2
 #endif
-#endif
 
 #if CONFIG_RGF_NUM_BANKS != 1
+#ifndef CONFIG_FIRQ_NO_LPCC
 	/*
 	 * Save LP_START/LP_COUNT/LP_END because called handler might use.
 	 * Save these in callee saved registers to avoid using memory.
@@ -76,60 +103,10 @@ SECTION_FUNC(TEXT, _firq_enter)
 	lr r24, [_ARC_V2_LP_START]
 	lr r25, [_ARC_V2_LP_END]
 #endif
-
-	/* check whether irq stack is used */
-	_check_and_inc_int_nest_counter r0, r1
-
-	bne.d firq_nest
-	mov_s r0, sp
-
-	_get_curr_cpu_irq_stack sp
-#if CONFIG_RGF_NUM_BANKS != 1
-	b firq_nest_1
-firq_nest:
-	/*
-	 * because firq and rirq share the same interrupt stack,
-	 * switch back to original register bank to get correct sp.
-	 * to get better firq latency, an approach is to prepare
-	 * separate interrupt stack for firq and do not do thread
-	 * switch in firq.
-	 */
-	lr r1, [_ARC_V2_STATUS32]
-	and r1, r1, ~_ARC_V2_STATUS32_RB(7)
-	kflag r1
-
-	/* here use _ARC_V2_USER_SP and ilink to exchange sp
-	 * save original value of _ARC_V2_USER_SP and ilink into
-	 * the stack of interrupted context first, then restore them later
-	 */
-	push ilink
-	PUSHAX ilink, _ARC_V2_USER_SP
-
-	/* sp here is the sp of interrupted context */
-	sr sp, [_ARC_V2_USER_SP]
-	/* here, bank 0 sp must go back to the value before push and
-	 * PUSHAX as we will switch to bank1, the pop and POPAX later will
-	 * change bank1's sp, not bank0's sp
-	 */
-	add sp, sp, 8
-
-	/* switch back to banked reg, only ilink can be used */
-	lr ilink, [_ARC_V2_STATUS32]
-	or ilink, ilink, _ARC_V2_STATUS32_RB(1)
-	kflag ilink
-	lr sp, [_ARC_V2_USER_SP]
-
-	POPAX ilink, _ARC_V2_USER_SP
-	pop ilink
-firq_nest_1:
-#else
-firq_nest:
 #endif
-	push_s r0
+
 	j @_isr_demux
 
-
-
 /**
  *
  * @brief Work to be done exiting a FIRQ
@@ -140,90 +117,113 @@ firq_nest:
 SECTION_FUNC(TEXT, _firq_exit)
 
 #if CONFIG_RGF_NUM_BANKS != 1
+#ifndef CONFIG_FIRQ_NO_LPCC
 	/* restore lp_count, lp_start, lp_end from r23-r25 */
 	mov lp_count,r23
 	sr r24, [_ARC_V2_LP_START]
 	sr r25, [_ARC_V2_LP_END]
 #endif
-	_dec_int_nest_counter r0, r1
+#endif
 
-	_check_nest_int_by_irq_act r0, r1
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
 
-	jne _firq_no_switch
+#if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
+	/* check if we're a nested interrupt: if so, let the interrupted
+	 * interrupt handle the reschedule */
 
-	/* sp is struct k_thread **old of z_arc_switch_in_isr
-	 * which is a wrapper of z_get_next_switch_handle.
-	 * r0 contains the 1st thread in ready queue. if
-	 * it equals _current(r2) ,then do swap, or no swap.
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+
+	/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
+	 * AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is not 1, it
+	 * means that another bit is set so an interrupt was interrupted.
 	 */
-	_get_next_switch_handle
 
-	/* restore interrupted context' sp */
-	pop sp
+	breq r3, 1, _firq_check_for_swap
 
-	cmp r0, r2
-	bne _firq_switch
-
-	/* fall to no switch */
+	_firq_return
+#endif
 
 .balign 4
-_firq_no_switch:
+_firq_check_for_swap:
+	/* coop thread ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_prio]
+	brlt r0, 0, _firq_no_reschedule
+
+	/* scheduler locked ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_sched_locked]
+	brgt r0, 0, _firq_no_reschedule
+
+	/* check if the current thread needs to be rescheduled */
+	push_s r2
+	push_s r1
+	push_s blink
+	jl _is_next_thread_current
+	pop_s blink
+	pop_s r1
+	pop_s r2
+#if CONFIG_RGF_NUM_BANKS != 1
+#ifndef CONFIG_FIRQ_NO_LPCC
+	/*
+	 * restore lp_count, lp_start, lp_end from r23-r25 in case
+	 * _is_next_thread_current() routine used them
+	 */
+	mov lp_count,r23
+	sr r24, [_ARC_V2_LP_START]
+	sr r25, [_ARC_V2_LP_END]
+#endif
+#endif
+	breq r0, 0, _firq_reschedule
+	/* fall to no rescheduling */
+
+.balign 4
+_firq_no_reschedule:
 	/*
 	 * Keeping this code block close to those that use it allows using brxx
 	 * instruction instead of a pair of cmp and bxx
 	 */
 #if CONFIG_RGF_NUM_BANKS == 1
-	_pop_irq_stack_frame
+	add sp,sp,4 /* don't need r0 from stack */
+	pop_s r1
+	pop_s r2
+	pop_s r3
+	pop r4
+	pop r5
+	pop r6
+	pop r7
+	pop r8
+	pop r9
+	pop r10
+	pop r11
+	pop_s r12
+	pop_s r13
+	pop_s blink
+	pop_s r0
+	sr r0, [_ARC_V2_LP_END]
+	pop_s r0
+	sr r0, [_ARC_V2_LP_START]
+	pop_s r0
+	mov lp_count,r0
+	ld r0,[saved_r0]
+	add sp,sp,8 /* don't need ilink & status32_po from stack */
 #endif
 	rtie
 
 .balign 4
-_firq_switch:
+_firq_reschedule:
 
 #if CONFIG_RGF_NUM_BANKS != 1
-/*
- * save r0, r2 in irq stack for a while, as they will be changed by register
- * bank switch
- */
-	_get_curr_cpu_irq_stack r1
-	st r0, [r1, -4]
-	st r2, [r1, -8]
-
 	/*
 	 * We know there is no interrupted interrupt of lower priority at this
 	 * point, so when switching back to register bank 0, it will contain the
 	 * registers from the interrupted thread.
 	 */
-#if defined(CONFIG_USERSPACE)
-/* when USERSPACE is configured, here need to consider the case where firq comes
- * out in user mode, according to ARCv2 ISA and nsim, the following micro ops
- * will be executed:
- *	sp<-reg bank1'sp
- *      switch between sp and _ARC_V2_USER_SP
- * then:
- *      sp is the sp of kernel stack of interrupted thread
- *      _ARC_V2_USER_SP is reg bank1'sp
- *      the sp of user stack of interrupted thread is reg bank0'sp
- * if firq comes out in kernel mode, the following micro ops will be executed:
- *      sp<-reg bank'sp
- * so, sw needs to do necessary handling to set up the correct sp
- */
-	lr r0, [_ARC_V2_AUX_IRQ_ACT]
-	bbit0 r0, 31, _firq_from_kernel
-	aex sp, [_ARC_V2_USER_SP]
-	lr r0, [_ARC_V2_STATUS32]
-	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
-	kflag r0
-	aex sp, [_ARC_V2_USER_SP]
-	b _firq_create_irq_stack_frame
-_firq_from_kernel:
-#endif
+
 	/* chose register bank #0 */
 	lr r0, [_ARC_V2_STATUS32]
 	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
 	kflag r0
 
-_firq_create_irq_stack_frame:
 	/* we're back on the outgoing thread's stack */
 	_create_irq_stack_frame
 
@@ -236,49 +236,79 @@ _firq_create_irq_stack_frame:
 	st_s r0, [sp, ___isf_t_status32_OFFSET]
 
 	st ilink, [sp, ___isf_t_pc_OFFSET] /* ilink into pc */
-/*
- * load r0, r2 from irq stack
- */
-	_get_curr_cpu_irq_stack r1
-	ld r0, [r1, -4]
-	ld r2, [r1, -8]
 #endif
-	/* r2 is old thread */
-	_irq_store_old_thread_callee_regs
+
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+
+	_save_callee_saved_regs
 
 	st _CAUSE_FIRQ, [r2, _thread_offset_to_relinquish_cause]
 
-	/* mov new thread (r0) to r2 */
+	/*
+	 * Save needed registers to callee saved ones. It is faster than
+	 * pushing them to stack. It is possible to do since program has
+	 * just saved them and the calling routine will save them in turn
+	 * if it uses them.
+	 */
+	mov_s r13, blink
+	mov_s r14, r1
+	jl _get_next_ready_thread
+	mov_s blink, r13
+	mov_s r1, r14
+	mov_s r2, r0
+	st_s r2, [r1, _kernel_offset_to_current]
 
-	mov r2, r0
-	_load_new_thread_callee_regs
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* Use stack top and down registers from restored context */
+	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
+	sr r3, [_ARC_V2_KSTACK_TOP]
+	ld_s r3, [r2, _thread_offset_to_stack_top]
+	sr r3, [_ARC_V2_KSTACK_BASE]
+#endif
+	/*
+	 * _load_callee_saved_regs expects incoming thread in r2.
+	 * _load_callee_saved_regs restores the stack pointer.
+	 */
+	_load_callee_saved_regs
 
-	breq r3, _CAUSE_RIRQ, _firq_switch_from_rirq
-	nop_s
-	breq r3, _CAUSE_FIRQ, _firq_switch_from_firq
-	nop_s
+	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
+
+	breq r3, _CAUSE_RIRQ, _firq_return_from_rirq
+	nop
+	breq r3, _CAUSE_FIRQ, _firq_return_from_firq
+	nop
 
 	/* fall through */
 
 .balign 4
-_firq_switch_from_coop:
+_firq_return_from_coop:
 
-	_set_misc_regs_irq_switch_from_coop
+	ld_s r3, [r2, _thread_offset_to_intlock_key]
+	st  0, [r2, _thread_offset_to_intlock_key]
 
 	/* pc into ilink */
 	pop_s r0
-	mov_s ilink, r0
+	mov ilink, r0
 
 	pop_s r0 /* status32 into r0 */
+	/*
+	 * There are only two interrupt lock states: locked and unlocked. When
+	 * entering _Swap(), they are always locked, so the IE bit is unset in
+	 * status32. If the incoming thread had them locked recursively, it
+	 * means that the IE bit should stay unset. The only time the bit
+	 * has to change is if they were not locked recursively.
+	 */
+	and.f r3, r3, (1 << 4)
+	or.nz r0, r0, _ARC_V2_STATUS32_IE
 	sr r0, [_ARC_V2_STATUS32_P0]
 
+	ld_s r0, [r2, _thread_offset_to_return_value]
 	rtie
 
 .balign 4
-_firq_switch_from_rirq:
-_firq_switch_from_firq:
-
-	_set_misc_regs_irq_switch_from_irq
+_firq_return_from_rirq:
+_firq_return_from_firq:
 
 	_pop_irq_stack_frame
 
@@ -288,3 +318,33 @@ _firq_switch_from_firq:
 
 	/* LP registers are already restored, just switch back to bank 0 */
 	rtie
+
+
+/**
+ *
+ * @brief Install the FIRQ stack in register bank 1 if CONFIG_RGF_NUM_BANK!=1
+ *
+ * @return N/A
+ */
+
+SECTION_FUNC(TEXT, _firq_stack_setup)
+
+#if CONFIG_RGF_NUM_BANKS != 1
+	lr r0, [_ARC_V2_STATUS32]
+	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
+	or r0, r0, _ARC_V2_STATUS32_RB(1)
+	kflag r0
+
+	mov sp, _firq_stack
+	add sp, sp, CONFIG_FIRQ_STACK_SIZE
+
+	/*
+	 * We have to reload r0 here, because it is bank1 r0 which contains
+	 * garbage, not bank0 r0 containing the previous value of status32.
+	 */
+	lr r0, [_ARC_V2_STATUS32]
+	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
+	kflag r0
+#endif
+
+	j_s [blink]

arch/arc/core/fatal.c

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -12,33 +22,74 @@
  * ARCv2 CPUs.
  */
 
-#include <kernel.h>
+#include <kernel_structs.h>
 #include <offsets_short.h>
+#include <toolchain.h>
 #include <arch/cpu.h>
-#include <logging/log.h>
-LOG_MODULE_DECLARE(os);
 
-void z_arc_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
+#ifdef CONFIG_PRINTK
+#include <misc/printk.h>
+#define PR_EXC(...) printk(__VA_ARGS__)
+#else
+#define PR_EXC(...)
+#endif /* CONFIG_PRINTK */
+
+const NANO_ESF _default_esf = {
+	0xdeaddead, /* placeholder */
+};
+
+/**
+ *
+ * @brief Nanokernel fatal error handler
+ *
+ * This routine is called when fatal error conditions are detected by software
+ * and is responsible only for reporting the error. Once reported, it then
+ * invokes the user provided routine _SysFatalErrorHandler() which is
+ * responsible for implementing the error handling policy.
+ *
+ * The caller is expected to always provide a usable ESF. In the event that the
+ * fatal error does not have a hardware generated ESF, the caller should either
+ * create its own or use a pointer to the global default ESF <_default_esf>.
+ *
+ * @return This function does not return.
+ */
+FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
+							const NANO_ESF *pEsf)
 {
-	if (reason == K_ERR_CPU_EXCEPTION) {
-		LOG_ERR("Faulting instruction address = 0x%lx",
-			z_arc_v2_aux_reg_read(_ARC_V2_ERET));
+	switch (reason) {
+	case _NANO_ERR_INVALID_TASK_EXIT:
+		PR_EXC("***** Invalid Exit Software Error! *****\n");
+		break;
+
+#if defined(CONFIG_STACK_CANARIES)
+	case _NANO_ERR_STACK_CHK_FAIL:
+		PR_EXC("***** Stack Check Fail! *****\n");
+		break;
+#endif
+
+	case _NANO_ERR_ALLOCATION_FAIL:
+		PR_EXC("**** Kernel Allocation Failure! ****\n");
+		break;
+
+	default:
+		PR_EXC("**** Unknown Fatal Error %d! ****\n", reason);
+		break;
 	}
+	PR_EXC("Current thread ID = %p\n"
+	       "Faulting instruction address = 0x%lx\n",
+	       k_current_get(),
+	       _arc_v2_aux_reg_read(_ARC_V2_ERET));
 
-	z_fatal_error(reason, esf);
-}
-
-FUNC_NORETURN void arch_syscall_oops(void *ssf_ptr)
-{
-	z_arc_fatal_error(K_ERR_KERNEL_OOPS, ssf_ptr);
-	CODE_UNREACHABLE;
-}
-
-FUNC_NORETURN void arch_system_halt(unsigned int reason)
-{
-	ARG_UNUSED(reason);
-
-	__asm__("brk");
-
-	CODE_UNREACHABLE;
+	/*
+	 * Now that the error has been reported, call the user implemented
+	 * policy
+	 * to respond to the error.  The decisions as to what responses are
+	 * appropriate to the various errors are something the customer must
+	 * decide.
+	 */
+
+	_SysFatalErrorHandler(reason, pEsf);
+
+	for (;;)
+		;
 }

arch/arc/core/fault.c

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -12,423 +22,70 @@
  */
 
 #include <toolchain.h>
-#include <linker/sections.h>
+#include <sections.h>
 #include <inttypes.h>
 
-#include <kernel.h>
-#include <kernel_internal.h>
+#include <nanokernel.h>
 #include <kernel_structs.h>
-#include <exc_handle.h>
-#include <logging/log.h>
-LOG_MODULE_DECLARE(os);
 
-#ifdef CONFIG_USERSPACE
-Z_EXC_DECLARE(z_arc_user_string_nlen);
-
-static const struct z_exc_handle exceptions[] = {
-	Z_EXC_HANDLE(z_arc_user_string_nlen)
-};
-#endif
-
-#if defined(CONFIG_MPU_STACK_GUARD)
-
-#define IS_MPU_GUARD_VIOLATION(guard_start, fault_addr, stack_ptr) \
-	((fault_addr >= guard_start) && \
-	(fault_addr < (guard_start + STACK_GUARD_SIZE)) && \
-	(stack_ptr <= (guard_start + STACK_GUARD_SIZE)))
-
-/**
- * @brief Assess occurrence of current thread's stack corruption
- *
- * This function performs an assessment whether a memory fault (on a
- * given memory address) is the result of stack memory corruption of
- * the current thread.
- *
- * Thread stack corruption for supervisor threads or user threads in
- * privilege mode (when User Space is supported) is reported upon an
- * attempt to access the stack guard area (if MPU Stack Guard feature
- * is supported). Additionally the current thread stack pointer
- * must be pointing inside or below the guard area.
- *
- * Thread stack corruption for user threads in user mode is reported,
- * if the current stack pointer is pointing below the start of the current
- * thread's stack.
- *
- * Notes:
- * - we assume a fully descending stack,
- * - we assume a stacking error has occurred,
- * - the function shall be called when handling MPU privilege violation
- *
- * If stack corruption is detected, the function returns the lowest
- * allowed address where the Stack Pointer can safely point to, to
- * prevent from errors when un-stacking the corrupted stack frame
- * upon exception return.
- *
- * @param fault_addr memory address on which memory access violation
- *                   has been reported.
- * @param sp stack pointer when exception comes out
- *
- * @return The lowest allowed stack frame pointer, if error is a
- *         thread stack corruption, otherwise return 0.
- */
-static u32_t z_check_thread_stack_fail(const u32_t fault_addr, u32_t sp)
-{
-	const struct k_thread *thread = _current;
-
-	if (!thread) {
-		return 0;
-	}
-#if defined(CONFIG_USERSPACE)
-	if (thread->arch.priv_stack_start) {
-		/* User thread */
-		if (z_arc_v2_aux_reg_read(_ARC_V2_ERSTATUS)
-			& _ARC_V2_STATUS32_U) {
-			/* Thread's user stack corruption */
-#ifdef CONFIG_ARC_HAS_SECURE
-			sp = z_arc_v2_aux_reg_read(_ARC_V2_SEC_U_SP);
+#ifdef CONFIG_PRINTK
+#include <misc/printk.h>
+#define PR_EXC(...) printk(__VA_ARGS__)
 #else
-			sp = z_arc_v2_aux_reg_read(_ARC_V2_USER_SP);
-#endif
-			if (sp <= (u32_t)thread->stack_obj) {
-				return (u32_t)thread->stack_obj;
-			}
-		} else {
-			/* User thread in privilege mode */
-			if (IS_MPU_GUARD_VIOLATION(
-			thread->arch.priv_stack_start - STACK_GUARD_SIZE,
-			fault_addr, sp)) {
-				/* Thread's privilege stack corruption */
-				return thread->arch.priv_stack_start;
-			}
-		}
-	} else {
-		/* Supervisor thread */
-		if (IS_MPU_GUARD_VIOLATION((u32_t)thread->stack_obj,
-			fault_addr, sp)) {
-			/* Supervisor thread stack corruption */
-			return (u32_t)thread->stack_obj + STACK_GUARD_SIZE;
-		}
-	}
-#else /* CONFIG_USERSPACE */
-	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start,
-			fault_addr, sp)) {
-		/* Thread stack corruption */
-		return thread->stack_info.start + STACK_GUARD_SIZE;
-	}
-#endif /* CONFIG_USERSPACE */
-
-	return 0;
-}
+#define PR_EXC(...)
+#endif /* CONFIG_PRINTK */
 
+#if (CONFIG_FAULT_DUMP > 0)
+#define FAULT_DUMP(esf, fault) _FaultDump(esf, fault)
+#else
+#define FAULT_DUMP(esf, fault) \
+	do {                   \
+		(void) esf;    \
+		(void) fault;  \
+	} while ((0))
 #endif
 
-#ifdef CONFIG_ARC_EXCEPTION_DEBUG
-/* For EV_ProtV, the numbering/semantics of the parameter are consistent across
- * several codes, although not all combination will be reported.
+#if (CONFIG_FAULT_DUMP > 0)
+/*
+ * @brief Dump information regarding fault (FAULT_DUMP > 0)
  *
- * These codes and parameters do not have associated* names in
- * the technical manual, just switch on the values in Table 6-5
+ * Dump information regarding the fault when CONFIG_FAULT_DUMP is set to 1
+ * (short form).
+ *
+ * @return N/A
  */
-static const char *get_protv_access_err(u32_t parameter)
+void _FaultDump(const NANO_ESF *esf, int fault)
 {
-	switch (parameter) {
-	case 0x1:
-		return "code protection scheme";
-	case 0x2:
-		return "stack checking scheme";
-	case 0x4:
-		return "MPU";
-	case 0x8:
-		return "MMU";
-	case 0x10:
-		return "NVM";
-	case 0x24:
-		return "Secure MPU";
-	case 0x44:
-		return "Secure MPU with SID mismatch";
-	default:
-		return "unknown";
-	}
-}
+	ARG_UNUSED(esf);
+#ifdef CONFIG_PRINTK
+	uint32_t exc_addr = _arc_v2_aux_reg_read(_ARC_V2_EFA);
+	uint32_t ecr = _arc_v2_aux_reg_read(_ARC_V2_ECR);
 
-static void dump_protv_exception(u32_t cause, u32_t parameter)
-{
-	switch (cause) {
-	case 0x0:
-		LOG_ERR("Instruction fetch violation (%s)",
-			get_protv_access_err(parameter));
-		break;
-	case 0x1:
-		LOG_ERR("Memory read protection violation (%s)",
-			get_protv_access_err(parameter));
-		break;
-	case 0x2:
-		LOG_ERR("Memory write protection violation (%s)",
-			get_protv_access_err(parameter));
-		break;
-	case 0x3:
-		LOG_ERR("Memory read-modify-write violation (%s)",
-			get_protv_access_err(parameter));
-		break;
-	case 0x10:
-		LOG_ERR("Normal vector table in secure memory");
-		break;
-	case 0x11:
-		LOG_ERR("NS handler code located in S memory");
-		break;
-	case 0x12:
-		LOG_ERR("NSC Table Range Violation");
-		break;
-	default:
-		LOG_ERR("unknown");
-		break;
-	}
+	PR_EXC("Exception vector: 0x%" PRIx32 ", cause code: 0x%" PRIx32
+	       ", parameter 0x%" PRIx32 "\n",
+	       _ARC_V2_ECR_VECTOR(ecr),
+	       _ARC_V2_ECR_CODE(ecr),
+	       _ARC_V2_ECR_PARAMETER(ecr));
+	PR_EXC("Address 0x%" PRIx32 "\n", exc_addr);
+#endif
 }
-
-static void dump_machine_check_exception(u32_t cause, u32_t parameter)
-{
-	switch (cause) {
-	case 0x0:
-		LOG_ERR("double fault");
-		break;
-	case 0x1:
-		LOG_ERR("overlapping TLB entries");
-		break;
-	case 0x2:
-		LOG_ERR("fatal TLB error");
-		break;
-	case 0x3:
-		LOG_ERR("fatal cache error");
-		break;
-	case 0x4:
-		LOG_ERR("internal memory error on instruction fetch");
-		break;
-	case 0x5:
-		LOG_ERR("internal memory error on data fetch");
-		break;
-	case 0x6:
-		LOG_ERR("illegal overlapping MPU entries");
-		if (parameter == 0x1) {
-			LOG_ERR(" - jump and branch target");
-		}
-		break;
-	case 0x10:
-		LOG_ERR("secure vector table not located in secure memory");
-		break;
-	case 0x11:
-		LOG_ERR("NSC jump table not located in secure memory");
-		break;
-	case 0x12:
-		LOG_ERR("secure handler code not located in secure memory");
-		break;
-	case 0x13:
-		LOG_ERR("NSC target address not located in secure memory");
-		break;
-	case 0x80:
-		LOG_ERR("uncorrectable ECC or parity error in vector memory");
-		break;
-	default:
-		LOG_ERR("unknown");
-		break;
-	}
-}
-
-static void dump_privilege_exception(u32_t cause, u32_t parameter)
-{
-	switch (cause) {
-	case 0x0:
-		LOG_ERR("Privilege violation");
-		break;
-	case 0x1:
-		LOG_ERR("disabled extension");
-		break;
-	case 0x2:
-		LOG_ERR("action point hit");
-		break;
-	case 0x10:
-		switch (parameter) {
-		case 0x1:
-			LOG_ERR("N to S return using incorrect return mechanism");
-			break;
-		case 0x2:
-			LOG_ERR("N to S return with incorrect operating mode");
-			break;
-		case 0x3:
-			LOG_ERR("IRQ/exception return fetch from wrong mode");
-			break;
-		case 0x4:
-			LOG_ERR("attempt to halt secure processor in NS mode");
-			break;
-		case 0x20:
-			LOG_ERR("attempt to access secure resource from normal mode");
-			break;
-		case 0x40:
-			LOG_ERR("SID violation on resource access (APEX/UAUX/key NVM)");
-			break;
-		default:
-			LOG_ERR("unknown");
-			break;
-		}
-		break;
-	case 0x13:
-		switch (parameter) {
-		case 0x20:
-			LOG_ERR("attempt to access secure APEX feature from NS mode");
-			break;
-		case 0x40:
-			LOG_ERR("SID violation on access to APEX feature");
-			break;
-		default:
-			LOG_ERR("unknown");
-			break;
-		}
-		break;
-	default:
-		LOG_ERR("unknown");
-		break;
-	}
-}
-
-static void dump_exception_info(u32_t vector, u32_t cause, u32_t parameter)
-{
-	if (vector >= 0x10 && vector <= 0xFF) {
-		LOG_ERR("interrupt %u", vector);
-		return;
-	}
-
-	/* Names are exactly as they appear in Designware ARCv2 ISA
-	 * Programmer's reference manual for easy searching
-	 */
-	switch (vector) {
-	case ARC_EV_RESET:
-		LOG_ERR("Reset");
-		break;
-	case ARC_EV_MEM_ERROR:
-		LOG_ERR("Memory Error");
-		break;
-	case ARC_EV_INS_ERROR:
-		LOG_ERR("Instruction Error");
-		break;
-	case ARC_EV_MACHINE_CHECK:
-		LOG_ERR("EV_MachineCheck");
-		dump_machine_check_exception(cause, parameter);
-		break;
-	case ARC_EV_TLB_MISS_I:
-		LOG_ERR("EV_TLBMissI");
-		break;
-	case ARC_EV_TLB_MISS_D:
-		LOG_ERR("EV_TLBMissD");
-		break;
-	case ARC_EV_PROT_V:
-		LOG_ERR("EV_ProtV");
-		dump_protv_exception(cause, parameter);
-		break;
-	case ARC_EV_PRIVILEGE_V:
-		LOG_ERR("EV_PrivilegeV");
-		dump_privilege_exception(cause, parameter);
-		break;
-	case ARC_EV_SWI:
-		LOG_ERR("EV_SWI");
-		break;
-	case ARC_EV_TRAP:
-		LOG_ERR("EV_Trap");
-		break;
-	case ARC_EV_EXTENSION:
-		LOG_ERR("EV_Extension");
-		break;
-	case ARC_EV_DIV_ZERO:
-		LOG_ERR("EV_DivZero");
-		break;
-	case ARC_EV_DC_ERROR:
-		LOG_ERR("EV_DCError");
-		break;
-	case ARC_EV_MISALIGNED:
-		LOG_ERR("EV_Misaligned");
-		break;
-	case ARC_EV_VEC_UNIT:
-		LOG_ERR("EV_VecUnit");
-		break;
-	default:
-		LOG_ERR("unknown");
-		break;
-	}
-}
-#endif /* CONFIG_ARC_EXCEPTION_DEBUG */
+#endif /* CONFIG_FAULT_DUMP */
 
 /*
  * @brief Fault handler
  *
  * This routine is called when fatal error conditions are detected by hardware
  * and is responsible only for reporting the error. Once reported, it then
- * invokes the user provided routine k_sys_fatal_error_handler() which is
+ * invokes the user provided routine _SysFatalErrorHandler() which is
  * responsible for implementing the error handling policy.
+ *
+ * @return This function does not return.
  */
-void _Fault(z_arch_esf_t *esf, u32_t old_sp)
+void _Fault(void)
 {
-	u32_t vector, cause, parameter;
-	u32_t exc_addr = z_arc_v2_aux_reg_read(_ARC_V2_EFA);
-	u32_t ecr = z_arc_v2_aux_reg_read(_ARC_V2_ECR);
+	uint32_t ecr = _arc_v2_aux_reg_read(_ARC_V2_ECR);
 
-#ifdef CONFIG_USERSPACE
-	for (int i = 0; i < ARRAY_SIZE(exceptions); i++) {
-		u32_t start = (u32_t)exceptions[i].start;
-		u32_t end = (u32_t)exceptions[i].end;
+	FAULT_DUMP(&_default_esf, ecr);
 
-		if (esf->pc >= start && esf->pc < end) {
-			esf->pc = (u32_t)(exceptions[i].fixup);
-			return;
-		}
-	}
-#endif
-
-	vector = Z_ARC_V2_ECR_VECTOR(ecr);
-	cause =  Z_ARC_V2_ECR_CODE(ecr);
-	parameter = Z_ARC_V2_ECR_PARAMETER(ecr);
-
-	/* exception raised by kernel */
-	if (vector == ARC_EV_TRAP && parameter == _TRAP_S_CALL_RUNTIME_EXCEPT) {
-		/*
-		 * in user mode software-triggered system fatal exceptions only allow
-		 * K_ERR_KERNEL_OOPS and K_ERR_STACK_CHK_FAIL
-		 */
-#ifdef CONFIG_USERSPACE
-		if ((esf->status32 & _ARC_V2_STATUS32_U) &&
-			esf->r0 != K_ERR_STACK_CHK_FAIL) {
-			esf->r0 = K_ERR_KERNEL_OOPS;
-		}
-#endif
-
-		z_arc_fatal_error(esf->r0, esf);
-		return;
-	}
-
-	LOG_ERR("***** Exception vector: 0x%x, cause code: 0x%x, parameter 0x%x",
-		vector, cause, parameter);
-	LOG_ERR("Address 0x%x", exc_addr);
-#ifdef CONFIG_ARC_EXCEPTION_DEBUG
-	dump_exception_info(vector, cause, parameter);
-#endif
-
-#ifdef CONFIG_ARC_STACK_CHECKING
-	/* Vector 6 = EV_ProV. Regardless of cause, parameter 2 means stack
-	 * check violation
-	 * stack check and mpu violation can come out together, then
-	 * parameter = 0x2 | [0x4 | 0x8 | 0x1]
-	 */
-	if (vector == ARC_EV_PROT_V && parameter & 0x2) {
-		z_arc_fatal_error(K_ERR_STACK_CHK_FAIL, esf);
-		return;
-	}
-#endif
-
-#ifdef CONFIG_MPU_STACK_GUARD
-	if (vector == ARC_EV_PROT_V && ((parameter == 0x4) ||
-					(parameter == 0x24))) {
-		if (z_check_thread_stack_fail(exc_addr, old_sp)) {
-			z_arc_fatal_error(K_ERR_STACK_CHK_FAIL, esf);
-			return;
-		}
-	}
-#endif
-	z_arc_fatal_error(K_ERR_CPU_EXCEPTION, esf);
+	_SysFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, &_default_esf);
 }

arch/arc/core/fault_s.S

@@ -1,8 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
- * Copyright (c) 2018 Synopsys.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -12,13 +21,15 @@
  * Fault handlers for ARCv2 processors.
  */
 
+#define _ASMLANGUAGE
+
 #include <toolchain.h>
-#include <linker/sections.h>
+#include <sections.h>
 #include <arch/cpu.h>
-#include <swap_macros.h>
-#include <syscall.h>
+#include "swap_macros.h"
 
 GTEXT(_Fault)
+
 GTEXT(__reset)
 GTEXT(__memory_error)
 GTEXT(__instruction_error)
@@ -33,31 +44,17 @@ GTEXT(__ev_extension)
 GTEXT(__ev_div_zero)
 GTEXT(__ev_dc_error)
 GTEXT(__ev_maligned)
-#ifdef CONFIG_IRQ_OFFLOAD
-GTEXT(z_irq_do_offload);
-#endif
 
-.macro _save_exc_regs_into_stack
-#ifdef CONFIG_ARC_HAS_SECURE
-	/* ERSEC_STAT is IOW/RAZ in normal mode */
-	lr r0,[_ARC_V2_ERSEC_STAT]
-	st_s r0, [sp, ___isf_t_sec_stat_OFFSET]
-#endif
-	lr r0,[_ARC_V2_ERET]
-	st_s r0, [sp, ___isf_t_pc_OFFSET]
-	lr r0,[_ARC_V2_ERSTATUS]
-	st_s r0, [sp, ___isf_t_status32_OFFSET]
-.endm
+SECTION_VAR(BSS, saved_stack_pointer)
+	.word 0
 
-/*
- * The exception handling will use top part of interrupt stack to
- * get smaller memory footprint, because exception is not frequent.
- * To reduce the impact on interrupt handling, especially nested interrupt
- * the top part of interrupt stack cannot be too large, so add a check
- * here
- */
-#if CONFIG_ARC_EXCEPTION_STACK_SIZE > (CONFIG_ISR_STACK_SIZE >> 1)
-#error "interrupt stack size is too small"
+#if CONFIG_RGF_NUM_BANKS == 1
+GDATA(_exception_stack)
+SECTION_VAR(NOINIT, _exception_stack)
+	.space 512
+/* note: QUARK_SE_C1000_SS can't afford 512B */
+#else
+GDATA(_firq_stack)
 #endif
 
 /*
@@ -72,196 +69,153 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_tlb_miss_d)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_prot_v)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_privilege_v)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_swi)
+#ifndef CONFIG_IRQ_OFFLOAD
+SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
+#endif
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_extension)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_div_zero)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_dc_error)
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 
-_exc_entry:
 	/*
-	 * re-use the top part of interrupt stack as exception
-	 * stack. If this top part is used by interrupt handling,
-	 * and exception is raised, then here it's guaranteed that
-	 * exception handling has necessary stack to use
-	 */
-	mov_s ilink, sp
-	_get_curr_cpu_irq_stack sp
-	sub sp, sp, (CONFIG_ISR_STACK_SIZE - CONFIG_ARC_EXCEPTION_STACK_SIZE)
-
-	/*
-	 * save caller saved registers
-	 * this stack frame is set up in exception stack,
-	 * not in the original sp (thread stack or interrupt stack).
-	 * Because the exception may be raised by stack checking or
-	 * mpu protect violation related to stack. If this stack frame
-	 * is setup in original sp, double exception may be raised during
-	 * _create_irq_stack_frame, which is unrecoverable.
-	 */
-	_create_irq_stack_frame
-
-	_save_exc_regs_into_stack
-
-	/* sp is parameter of _Fault */
-	mov_s r0, sp
-	/* ilink is the thread's original sp */
-	mov_s r1, ilink
-	jl _Fault
-
-_exc_return:
-/* the exception cause must be fixed in exception handler when exception returns
- * directly, or exception will be repeated.
- *
- * If thread switch is raised in exception handler, the context of old thread will
- * not be saved, i.e., it cannot be recovered, because we don't know where the
- * exception comes out,  thread context?irq_context?nest irq context?
- */
-
-	_get_next_switch_handle
-
-	breq r0, r2, _exc_return_from_exc
-
-	mov_s r2, r0
-
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	/*
-	 * sync up the ERSEC_STAT.ERM and SEC_STAT.IRM.
-	 * use a fake interrupt return to simulate an exception turn.
-	 * ERM and IRM record which mode the cpu should return, 1: secure
-	 * 0: normal
-	 */
-	lr r3,[_ARC_V2_ERSEC_STAT]
-	btst r3, 31
-	bset.nz r3, r3, _ARC_V2_SEC_STAT_IRM_BIT
-	bclr.z r3, r3, _ARC_V2_SEC_STAT_IRM_BIT
-	sflag r3
-#endif
-	/* clear AE bit to forget this was an exception, and go to
-	 * register bank0 (if exception is raised in firq with 2 reg
-	 * banks, then we may be bank1)
-	 */
-#if defined(CONFIG_ARC_FIRQ) && CONFIG_RGF_NUM_BANKS != 1
-	/* save r2 in ilink because of the possible following reg
-	 * bank switch
-	 */
-	mov_s ilink, r2
-#endif
-	lr r3, [_ARC_V2_STATUS32]
-	and r3,r3,(~(_ARC_V2_STATUS32_AE | _ARC_V2_STATUS32_RB(7)))
-	kflag r3
-	/* pretend lowest priority interrupt happened to use common handler
-	 * if exception is raised in irq, i.e., _ARC_V2_AUX_IRQ_ACT !=0,
-	 * ignore irq handling, we cannot return to irq handling which may
-	 * raise exception again. The ignored interrupts will be re-triggered
-	 * if not cleared, or re-triggered by interrupt sources, or just missed
+	 * Before invoking exception handler, the kernel switches to an exception
+	 * stack, to save the faulting thread's registers.
+	 * The exception is fatal and all the kernel can do is just print
+	 * a diagnostic message and halt.
 	 */
 
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	mov_s r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
-#else
-	mov_s r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
-#endif
-
-#ifdef CONFIG_ARC_NORMAL_FIRMWARE
+#ifdef CONFIG_ARC_STACK_CHECKING
 	push_s r2
-	mov_s r0, _ARC_V2_AUX_IRQ_ACT
-	mov_s r1, r3
-	mov_s r6, ARC_S_CALL_AUX_WRITE
-	sjli SJLI_CALL_ARC_SECURE
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
 	pop_s r2
+#endif
+
+	st sp, [saved_stack_pointer]
+#if CONFIG_RGF_NUM_BANKS == 1
+	mov_s sp, _exception_stack
+	add sp, sp, 512
 #else
-	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+	mov_s sp, _firq_stack
+	add sp, sp, CONFIG_FIRQ_STACK_SIZE
 #endif
 
-#if defined(CONFIG_ARC_FIRQ) && CONFIG_RGF_NUM_BANKS != 1
-	mov r2, ilink
-#endif
-
-	/* Assumption: r2 has next thread */
-	b _rirq_newthread_switch
-
-_exc_return_from_exc:
-	/* exception handler may change return address.
-	 * reload it
-	 */
-	ld_s r0, [sp, ___isf_t_pc_OFFSET]
-	sr r0, [_ARC_V2_ERET]
-
-	_pop_irq_stack_frame
-	mov_s sp, ilink
-	rtie
-
-/* separated entry for trap which may be used by irq_offload, USERPSACE */
-SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
-	/* get the id of trap_s */
-	lr ilink, [_ARC_V2_ECR]
-	and ilink, ilink, 0x3f
-#ifdef CONFIG_USERSPACE
-	cmp ilink, _TRAP_S_CALL_SYSTEM_CALL
-	bne _do_non_syscall_trap
-	/* do sys_call */
-	mov_s ilink, K_SYSCALL_LIMIT
-	cmp r6, ilink
-	blo valid_syscall_id
-
-	mov_s r0, r6
-	mov_s r6, K_SYSCALL_BAD
-
-valid_syscall_id:
-	/* create a sys call frame
-	 * caller regs (r0 - 12) are saved in _create_irq_stack_frame
-	 * ok to use them later
-	 */
-	_create_irq_stack_frame
-
-	_save_exc_regs_into_stack
-
-	/* exc return and do sys call in kernel mode,
-	 * so need to clear U bit, r0 is already loaded
-	 * with ERSTATUS in _save_exc_regs_into_stack
-	 */
-
-	bclr r0, r0, _ARC_V2_STATUS32_U_BIT
-	sr r0, [_ARC_V2_ERSTATUS]
-
-	mov_s r0, _arc_do_syscall
-	sr r0, [_ARC_V2_ERET]
-
-	rtie
-
-_do_non_syscall_trap:
-#endif /* CONFIG_USERSPACE */
-#ifdef CONFIG_IRQ_OFFLOAD
-	/*
-	 * IRQ_OFFLOAD is to simulate interrupt handling through exception,
-	 * so its entry is different with normal exception handling, it is
-	 * handled in isr stack
-	 */
-	cmp ilink, _TRAP_S_SCALL_IRQ_OFFLOAD
-	bne _exc_entry
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
-	_save_exc_regs_into_stack
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, ___isf_t_status32_OFFSET]
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
 
-	/* check whether irq stack is used */
-	_check_and_inc_int_nest_counter r0, r1
-
-	bne.d exc_nest_handle
-	mov_s r0, sp
-
-	_get_curr_cpu_irq_stack sp
-exc_nest_handle:
-	push_s r0
-
-	jl z_irq_do_offload
-
-	pop sp
-
-	_dec_int_nest_counter r0, r1
+	jl _Fault
 
+	/* if _Fault returns, restore the registers */
 	_pop_irq_stack_frame
 
-	/* ERSTATUS, ERET are not changed, so ok to rtie */
+	/* now restore the stack */
+	ld sp,[saved_stack_pointer]
 	rtie
+
+#ifdef CONFIG_IRQ_OFFLOAD
+GTEXT(_irq_do_offload);
+
+SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
+	/*
+	 * Before invoking exception handler, the kernel switches to an exception
+	 * stack to save the faulting thread's registers.
+	 * The exception is fatal and all the kernel can do is just print
+	 * a diagnostic message and halt.
+	 */
+
+#ifdef CONFIG_ARC_STACK_CHECKING
+	push_s r2
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+	pop_s r2
+#endif
+
+	/* save caller saved registers */
+	_create_irq_stack_frame
+
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, ___isf_t_status32_OFFSET]
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
+
+	jl _irq_do_offload
+
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+	/* check if we're a nested interrupt: if so, let the
+	 * interrupted interrupt handle the reschedule
+	 */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
+	 * AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is 0, it
+	 * means trap was taken from outside an interrupt handler.
+	 * But if it was inside, let that handler do the swap.
+	 */
+	breq r3, 0, _trap_check_for_swap
+_trap_return:
+	_pop_irq_stack_frame
+	rtie
+
+.balign 4
+_trap_check_for_swap:
+	/* coop thread ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_prio]
+	brlt r0, 0, _trap_return
+
+	/* scheduler locked ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_sched_locked]
+	brgt r0, 0, _trap_return
+
+	/* check if the current thread needs to be rescheduled */
+	push_s r2
+	push_s r1
+	push_s blink
+	jl _is_next_thread_current
+	pop_s blink
+	pop_s r1
+	pop_s r2
+	brne r0, 0, _trap_return
+
+	_save_callee_saved_regs
+
+	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
+	/* note: Ok to use _CAUSE_RIRQ since everything is saved */
+
+	/*
+	 * Save needed registers to callee saved ones. It is faster than
+	 * pushing registers to stack. It is possible to do since program has
+	 * just saved them and the calling routine will save them in turn
+	 * if it uses them.
+	 */
+	mov_s r13, blink
+	mov_s r14, r0
+	mov_s r15, r1
+	jl _get_next_ready_thread
+	mov_s r2, r0
+	mov_s r1, r15
+	mov_s r0, r14
+	mov_s blink, r13
+	st_s r2, [r1, _kernel_offset_to_current]
+
+	/* clear AE bit to forget this was an exception */
+	lr r3, [_ARC_V2_STATUS32]
+	and r3,r3,(~_ARC_V2_STATUS32_AE)
+	kflag r3
+	/* pretend lowest priority interrupt happened to use common handler */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1)) /* use lowest */
+	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+
+	/* Assumption: r2 has current thread */
+	b _rirq_common_interrupt_swap
+
 #endif /* CONFIG_IRQ_OFFLOAD */
-	b _exc_entry

arch/arc/core/irq_manage.c

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -17,71 +27,13 @@
  * number from 16 to last IRQ number on the platform.
  */
 
-#include <kernel.h>
+#include <nanokernel.h>
 #include <arch/cpu.h>
-#include <sys/__assert.h>
+#include <misc/__assert.h>
 #include <toolchain.h>
-#include <linker/sections.h>
+#include <sections.h>
 #include <sw_isr_table.h>
 #include <irq.h>
-#include <sys/printk.h>
-
-
-/*
- * storage space for the interrupt stack of fast_irq
- */
-#if defined(CONFIG_ARC_FIRQ_STACK)
-#if defined(CONFIG_SMP)
-K_THREAD_STACK_ARRAY_DEFINE(_firq_interrupt_stack, CONFIG_MP_NUM_CPUS,
-			    CONFIG_ARC_FIRQ_STACK_SIZE);
-#else
-K_THREAD_STACK_DEFINE(_firq_interrupt_stack, CONFIG_ARC_FIRQ_STACK_SIZE);
-#endif
-
-/*
- * @brief Set the stack pointer for firq handling
- *
- * @return N/A
- */
-void z_arc_firq_stack_set(void)
-{
-#ifdef CONFIG_SMP
-	char *firq_sp = Z_THREAD_STACK_BUFFER(
-		  _firq_interrupt_stack[z_arc_v2_core_id()]) +
-		  CONFIG_ARC_FIRQ_STACK_SIZE;
-#else
-	char *firq_sp = Z_THREAD_STACK_BUFFER(_firq_interrupt_stack) +
-		  CONFIG_ARC_FIRQ_STACK_SIZE;
-#endif
-
-/* the z_arc_firq_stack_set must be called when irq diasbled, as
- * it can be called not only in the init phase but also other places
- */
-	unsigned int key = arch_irq_lock();
-
-	__asm__ volatile (
-/* only ilink will not be banked, so use ilink as channel
- * between 2 banks
- */
-	"mov ilink, %0		\n\t"
-	"lr %0, [%1]		\n\t"
-	"or %0, %0, %2		\n\t"
-	"kflag %0		\n\t"
-	"mov sp, ilink		\n\t"
-/* switch back to bank0, use ilink to avoid the pollution of
- * bank1's gp regs.
- */
-	"lr ilink, [%1]		\n\t"
-	"and ilink, ilink, %3	\n\t"
-	"kflag ilink		\n\t"
-	:
-	: "r"(firq_sp), "i"(_ARC_V2_STATUS32),
-	  "i"(_ARC_V2_STATUS32_RB(1)),
-	  "i"(~_ARC_V2_STATUS32_RB(7))
-	);
-	arch_irq_unlock(key);
-}
-#endif
 
 /*
  * @brief Enable an interrupt line
@@ -93,9 +45,12 @@ void z_arc_firq_stack_set(void)
  * @return N/A
  */
 
-void arch_irq_enable(unsigned int irq)
+void _arch_irq_enable(unsigned int irq)
 {
-	z_arc_v2_irq_unit_int_enable(irq);
+	int key = irq_lock();
+
+	_arc_v2_irq_unit_int_enable(irq);
+	irq_unlock(key);
 }
 
 /*
@@ -107,20 +62,12 @@ void arch_irq_enable(unsigned int irq)
  * @return N/A
  */
 
-void arch_irq_disable(unsigned int irq)
+void _arch_irq_disable(unsigned int irq)
 {
-	z_arc_v2_irq_unit_int_disable(irq);
-}
+	int key = irq_lock();
 
-/**
- * @brief Return IRQ enable state
- *
- * @param irq IRQ line
- * @return interrupt enable state, true or false
- */
-int arch_irq_is_enabled(unsigned int irq)
-{
-	return z_arc_v2_irq_unit_int_enabled(irq);
+	_arc_v2_irq_unit_int_disable(irq);
+	irq_unlock(key);
 }
 
 /*
@@ -137,23 +84,16 @@ int arch_irq_is_enabled(unsigned int irq)
  * @return N/A
  */
 
-void z_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
+void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
 	ARG_UNUSED(flags);
 
+	int key = irq_lock();
+
 	__ASSERT(prio < CONFIG_NUM_IRQ_PRIO_LEVELS,
 		 "invalid priority %d for irq %d", prio, irq);
-/* 0 -> CONFIG_NUM_IRQ_PRIO_LEVELS allocted to secure world
- * left prio levels allocated to normal world
- */
-#if defined(CONFIG_ARC_SECURE_FIRMWARE)
-	prio = prio < ARC_N_IRQ_START_LEVEL ?
-		prio : (ARC_N_IRQ_START_LEVEL - 1);
-#elif defined(CONFIG_ARC_NORMAL_FIRMWARE)
-	prio = prio < ARC_N_IRQ_START_LEVEL ?
-		 ARC_N_IRQ_START_LEVEL : prio;
-#endif
-	z_arc_v2_irq_unit_prio_set(irq, prio);
+	_arc_v2_irq_unit_prio_set(irq, prio);
+	irq_unlock(key);
 }
 
 /*
@@ -165,19 +105,12 @@ void z_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
  * @return N/A
  */
 
-void z_irq_spurious(void *unused)
+#include <misc/printk.h>
+void _irq_spurious(void *unused)
 {
 	ARG_UNUSED(unused);
-	z_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
+	printk("_irq_spurious(). Spinning...\n");
+	for (;;)
+		;
 }
 
-#ifdef CONFIG_DYNAMIC_INTERRUPTS
-int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
-			     void (*routine)(void *parameter), void *parameter,
-			     u32_t flags)
-{
-	z_isr_install(irq, routine, parameter);
-	z_irq_priority_set(irq, priority, flags);
-	return irq;
-}
-#endif /* CONFIG_DYNAMIC_INTERRUPTS */

arch/arc/core/irq_offload.c

@@ -1,33 +1,45 @@
 /*
  * Copyright (c) 2015 Intel corporation
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
  * @file Software interrupts utility code - ARC implementation
  */
 
-#include <kernel.h>
+#include <nanokernel.h>
 #include <irq_offload.h>
 
 static irq_offload_routine_t offload_routine;
 static void *offload_param;
 
 /* Called by trap_s exception handler */
-void z_irq_do_offload(void)
+void _irq_do_offload(void)
 {
 	offload_routine(offload_param);
 }
 
-void arch_irq_offload(irq_offload_routine_t routine, void *parameter)
+void irq_offload(irq_offload_routine_t routine, void *parameter)
 {
+	int key;
 
+	key = irq_lock();
 	offload_routine = routine;
 	offload_param = parameter;
 
-	__asm__ volatile ("trap_s %[id]"
-		:
-		: [id] "i"(_TRAP_S_SCALL_IRQ_OFFLOAD) : );
+	__asm__ volatile ("trap_s 0");
 
+	irq_unlock(key);
 }
+

arch/arc/core/irq_vector_table.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief IRQ part of vector table for Quark SE Sensor Subsystem
+ *
+ * This file contains the IRQ part of the vector table. It is meant to be used
+ * for one of two cases:
+ *
+ * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
+ * binds _IsrWrapper() to all the IRQ entries in the vector table.
+ *
+ * b) When the BSP is written so that device ISRs are installed directly in the
+ * vector table, they are enumerated here.
+ *
+ */
+
+#include <toolchain.h>
+#include <sections.h>
+
+extern void _isr_enter(void);
+typedef void (*vth)(void); /* Vector Table Handler */
+
+#if defined(CONFIG_SW_ISR_TABLE)
+
+vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS - 16] = {
+	[0 ...(CONFIG_NUM_IRQS - 17)] = _isr_enter
+};
+
+#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
+
+extern void _SpuriousIRQ(void);
+
+/* placeholders: fill with real ISRs */
+
+vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS - 16] = {
+	[0 ...(CONFIG_NUM_IRQS - 17)] = _SpuriousIRQ
+};
+
+#endif /* CONFIG_SW_ISR_TABLE */

arch/arc/core/isr_wrapper.S

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -13,19 +23,27 @@
  * a parameter.
  */
 
+#define _ASMLANGUAGE
+
 #include <offsets_short.h>
 #include <toolchain.h>
-#include <linker/sections.h>
+#include <sections.h>
 #include <sw_isr_table.h>
 #include <kernel_structs.h>
 #include <arch/cpu.h>
-#include <swap_macros.h>
 
-GTEXT(_isr_wrapper)
+GTEXT(_isr_enter)
 GTEXT(_isr_demux)
 
+#if CONFIG_RGF_NUM_BANKS == 1
+GDATA(saved_r0)
+
+SECTION_VAR(BSS, saved_r0)
+        .word 0
+#endif
+
 #if defined(CONFIG_SYS_POWER_MANAGEMENT)
-GTEXT(z_sys_power_save_idle_exit)
+GTEXT(_sys_power_save_idle_exit)
 #endif
 
 /*
@@ -34,39 +52,48 @@ _rirq_enter/_firq_enter: they are jump points.
 
 The flow is the following:
 
-ISR -> _isr_wrapper -- + -> _rirq_enter -> _isr_demux -> ISR -> _rirq_exit
-			 |
-			 + -> _firq_enter -> _isr_demux -> ISR -> _firq_exit
+ISR -> _isr_enter -- + -> _rirq_enter -> _isr_demux -> ISR -> _rirq_exit
+                     |
+                     + -> _firq_enter -> _isr_demux -> ISR -> _firq_exit
 
 Context switch explanation:
 
 The context switch code is spread in these files:
 
-	isr_wrapper.s, switch.s, swap_macros.h, fast_irq.s, regular_irq.s
+  isr_wrapper.s, swap.s, swap_macros.s, fast_irq.s, regular_irq.s
 
 IRQ stack frame layout:
 
-	high address
+  high address
 
-	status32
-		pc
-	lp_count
-	lp_start
-	lp_end
-	blink
-	 r13
-	 ...
-	sp ->    r0
+           status32
+              pc
+           lp_count
+           lp_start
+            lp_end
+            blink
+             r13
+             ...
+    sp ->    r0
 
-	low address
+  low address
+
+Registers not taken into account in the current implementation.
+          jli_base
+          ldi_base
+          ei_base
+          accl
+          acch
 
 The context switch code adopts this standard so that it is easier to follow:
 
-	- r2 contains _kernel.current ASAP, and the incoming thread when we
-		transition from outgoing thread to incoming thread
+  - r1 contains _kernel ASAP and is not overwritten over the lifespan of
+    the functions.
+  - r2 contains _kernel.current ASAP, and the incoming thread when we
+    transition from outgoing thread to incoming thread
 
 Not loading _kernel into r0 allows loading _kernel without stomping on
-the parameter in r0 in arch_switch().
+the parameter in r0 in _Swap().
 
 
 ARCv2 processors have two kinds of interrupts: fast (FIRQ) and regular. The
@@ -92,55 +119,53 @@ registers (to avoid stack accesses). It is possible to register a FIRQ
 handler that operates outside of the kernel, but care must be taken to only
 use instructions that only use the banked registers.
 
-The kernel is able to handle transitions to and from FIRQ, RIRQ and threads.
-The contexts are saved 'lazily': the minimum amount of work is
+The kernel is able to handle transitions to and from FIRQ, RIRQ and threads
+(fibers/task). The contexts are saved 'lazily': the minimum amount of work is
 done upfront, and the rest is done when needed:
 
 o RIRQ
 
-	All needed registers to run C code in the ISR are saved automatically
-	on the outgoing thread's stack: loop, status32, pc, and the caller-
-	saved GPRs. That stack frame layout is pre-determined. If returning
-	to a thread, the stack is popped and no registers have to be saved by
-	the kernel. If a context switch is required, the callee-saved GPRs
-	are then saved in the thread's stack.
+  All needed regisers to run C code in the ISR are saved automatically
+  on the outgoing thread's stack: loop, status32, pc, and the caller-
+  saved GPRs. That stack frame layout is pre-determined. If returning
+  to a fiber, the stack is popped and no registers have to be saved by
+  the kernel. If a context switch is required, the callee-saved GPRs
+  are then saved in the thread control structure (TCS).
 
 o FIRQ
 
-	First, a FIRQ can be interrupting a lower-priority RIRQ: if this is
-	the case, the FIRQ does not take a scheduling decision and leaves it
-	the RIRQ to handle. This limits the amount of code that has to run at
-	interrupt-level.
+  First, a FIRQ can be interrupting a lower-priority RIRQ: if this is the case,
+  the FIRQ does not take a scheduling decision and leaves it the RIRQ to
+  handle. This limits the amount of code that has to run at interrupt-level.
 
-	CONFIG_RGF_NUM_BANKS==1 case:
-	Registers are saved on the stack frame just as they are for RIRQ.
-	Context switch can happen just as it does in the RIRQ case, however,
-	if the FIRQ interrupted a RIRQ, the FIRQ will return from interrupt
-	and let the RIRQ do the context switch. At entry, one register is
-	needed in order to have code to save other registers. r0 is saved
-	first in the stack and restored later
+  CONFIG_RGF_NUM_BANKS==1 case:
+  Registers are saved on the stack frame just as they are for RIRQ.
+  Context switch can happen just as it does in the RIRQ case, however,
+  if the FIRQ interrupted a RIRQ, the FIRQ will return from interrupt and
+  let the RIRQ do the context switch.  At entry, one register is needed in order
+  to have code to save other registers. r0 is saved first in a global called
+  saved_r0.
 
-	CONFIG_RGF_NUM_BANKS!=1 case:
-	During early initialization, the sp in the 2nd register bank is made to
-	refer to _firq_stack. This allows for the FIRQ handler to use its own
-	stack. GPRs are banked, loop registers are saved in unused callee saved
-	regs upon interrupt entry. If returning to a thread, loop registers are
-	restored and the CPU switches back to bank 0 for the GPRs. If a context
-	switch is needed, at this point only are all the registers saved.
-	First, a  stack frame with the same layout as the automatic RIRQ one is
-	created and then the callee-saved GPRs are saved in the stack.
-	status32_p0 and ilink are saved in this case, not status32 and pc.
-	To create the stack frame, the FIRQ handling code must first go back to
-	using bank0 of registers, since that is where the registers containing
-	the exiting thread are saved. Care must be taken not to touch any
-	register before saving them: the only one usable at that point is the
-	stack pointer.
+  CONFIG_RGF_NUM_BANKS!=1 case:
+  During early initialization, the sp in the 2nd register bank is made to
+  refer to _firq_stack. This allows for the FIRQ handler to use its own stack.
+  GPRs are banked, loop registers are saved in unused callee saved regs upon
+  interrupt entry. If returning to a fiber, loop registers are restored and the
+  CPU switches back to bank 0 for the GPRs. If a context switch is
+  needed, at this point only are all the registers saved. First, a
+  stack frame with the same layout as the automatic RIRQ one is created
+  and then the callee-saved GPRs are saved in the TCS. status32_p0 and
+  ilink are saved in this case, not status32 and pc.
+  To create the stack frame, the FIRQ handling code must first go back to using
+  bank0 of registers, since that is where the registers containing the exiting
+  thread are saved. Care must be taken not to touch any register before saving
+  them: the only one usable at that point is the stack pointer.
 
 o coop
 
-	When a coop context switch is done, the callee-saved registers are
-	saved in the stack. The other GPRs do not need to be saved, since the
-	compiler has already placed them on the stack.
+  When a coop context switch is done, the callee-saved registers are
+  saved in the TCS. The other GPRs do not need to be saved, since the
+  compiler has already placed them on the stack.
 
 For restoring the contexts, there are six cases. In all cases, the
 callee-saved registers of the incoming thread have to be restored. Then, there
@@ -148,87 +173,102 @@ are specifics for each case:
 
 From coop:
 
-	o to coop
+  o to coop
 
-		Do a normal function call return.
+    Restore interrupt lock level and do a normal function call return.
 
-	o to any irq
+  o to any irq
 
-	The incoming interrupted thread has an IRQ stack frame containing the
-	caller-saved registers that has to be popped. status32 has to be
-	restored, then we jump to the interrupted instruction.
+    The incoming interrupted thread has an IRQ stack frame containing the
+    caller-saved registers that has to be popped. status32 has to be restored,
+    then we jump to the interrupted instruction.
 
 From FIRQ:
 
-	When CONFIG_RGF_NUM_BANKS==1, context switch is done as it is for RIRQ.
-	When CONFIG_RGF_NUM_BANKS!=1, the processor is put back to using bank0,
-	not bank1 anymore, because it had to save the outgoing context from
-	bank0, and now has to load the incoming one into bank0.
+  When CONFIG_RGF_NUM_BANKS==1, context switch is done as it is for RIRQ.
+  When CONFIG_RGF_NUM_BANKS!=1, the processor is put back to using bank0,
+  not bank1 anymore, because it had to save the outgoing context from bank0,
+  and now has to load the incoming one
+  into bank0.
 
-	o to coop
+  o to coop
 
-	The address of the returning instruction from arch_switch() is loaded
-	in ilink and the saved status32 in status32_p0.
+    The address of the returning instruction from _Swap() is loaded in ilink and
+    the saved status32 in status32_p0, taking care to adjust the interrupt lock
+    state desired in status32_p0. The return value is put in r0.
 
-	o to any irq
+  o to any irq
 
-	The IRQ has saved the caller-saved registers in a stack frame, which
-	must be popped, and status32 and pc loaded in status32_p0 and ilink.
+    The IRQ has saved the caller-saved registers in a stack frame, which must be
+    popped, and statu32 and pc loaded in status32_p0 and ilink.
 
 From RIRQ:
 
-	o to coop
+  o to coop
 
-	The interrupt return mechanism in the processor expects a stack frame,
-	but the outgoing context did not create one. A fake one is created
-	here, with only the relevant values filled in: pc, status32.
+    The interrupt return mechanism in the processor expects a stack frame, but
+    the outgoing context did not create one. A fake one is created here, with
+    only the relevant values filled in: pc, status32 and the return value in r0.
 
-	There is a discrepancy between the ABI from the ARCv2 docs,
-	including the way the processor pushes GPRs in pairs in the IRQ stack
-	frame, and the ABI GCC uses. r13 should be a callee-saved register,
-	but GCC treats it as caller-saved. This means that the processor pushes
-	it in the stack frame along with r12, but the compiler does not save it
-	before entering a function. So, it is saved as part of the callee-saved
-	registers, and restored there, but the processor restores it _a second
-	time_ when popping the IRQ stack frame. Thus, the correct value must
-	also be put in the fake stack frame when returning to a thread that
-	context switched out cooperatively.
+    There is a discrepancy between the ABI from the ARCv2 docs, including the
+    way the processor pushes GPRs in pairs in the IRQ stack frame, and the ABI
+    GCC uses. r13 should be a callee-saved register, but GCC treats it as
+    caller-saved. This means that the processor pushes it in the stack frame
+    along with r12, but the compiler does not save it before entering a
+    function. So, it is saved as part of the callee-saved registers, and
+    restored there, but the processor restores it _a second time_ when popping
+    the IRQ stack frame. Thus, the correct value must also be put in the fake
+    stack frame when returning to a thread that context switched out
+    cooperatively.
 
-	o to any irq
+  o to any irq
 
-	Both types of IRQs already have an IRQ stack frame: simply return from
-	interrupt.
+    Both types of IRQs already have an IRQ stack frame: simply return from
+    interrupt.
  */
 
-SECTION_FUNC(TEXT, _isr_wrapper)
-#if defined(CONFIG_ARC_FIRQ)
+SECTION_FUNC(TEXT, _isr_enter)
 #if CONFIG_RGF_NUM_BANKS == 1
-/* free r0 here, use r0 to check whether irq is firq.
- * for rirq,  as sp will not change and r0 already saved, this action
- * in fact is an action like nop.
- * for firq,  r0 will be restored later
- */
-	st_s r0, [sp]
+	st r0,[saved_r0]
 #endif
 	lr r0, [_ARC_V2_AUX_IRQ_ACT]
 	ffs r0, r0
 	cmp r0, 0
 #if CONFIG_RGF_NUM_BANKS == 1
 	bnz rirq_path
-	ld_s r0, [sp]
 	/* 1-register bank FIRQ handling must save registers on stack */
-	_create_irq_stack_frame
-	lr r0, [_ARC_V2_STATUS32_P0]
-	st_s r0, [sp, ___isf_t_status32_OFFSET]
-	lr r0, [_ARC_V2_ERET]
-	st_s r0, [sp, ___isf_t_pc_OFFSET]
-
-	mov_s r3, _firq_exit
-	mov_s r2, _firq_enter
+	lr r0,[_ARC_V2_STATUS32_P0]
+	push_s r0
+	mov r0,ilink
+	push_s r0
+	mov r0,lp_count
+	push_s r0
+	lr r0, [_ARC_V2_LP_START]
+	push_s r0
+	lr r0, [_ARC_V2_LP_END]
+	push_s r0
+	push_s blink
+	push_s r13
+	push_s r12
+	push r11
+	push r10
+	push r9
+	push r8
+	push r7
+	push r6
+	push r5
+	push r4
+	push_s r3
+	push_s r2
+	push_s r1
+	ld r0,[saved_r0]
+	push_s r0
+	mov r3, _firq_exit
+	mov r2, _firq_enter
 	j_s [r2]
 rirq_path:
-	mov_s r3, _rirq_exit
-	mov_s r2, _rirq_enter
+	mov r3, _rirq_exit
+	mov r2, _rirq_enter
 	j_s [r2]
 #else
 	mov.z r3, _firq_exit
@@ -237,25 +277,55 @@ rirq_path:
 	mov.nz r2, _rirq_enter
 	j_s [r2]
 #endif
+
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+GTEXT(_sys_k_event_logger_exit_sleep)
+
+.macro log_sleep_k_event
+	clri r0 /* do not interrupt event logger operations */
+	push_s r0
+	push_s blink
+	jl _sys_k_event_logger_exit_sleep
+	pop_s blink
+	pop_s r0
+	seti r0
+.endm
 #else
-	mov_s r3, _rirq_exit
-	mov_s r2, _rirq_enter
-	j_s [r2]
+	#define log_sleep_k_event
+#endif
+#if defined(CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT)
+GTEXT(_sys_k_event_logger_interrupt)
+
+.macro log_interrupt_k_event
+	clri r0 /* do not interrupt event logger operations */
+	push_s r0
+	push_s blink
+	jl _sys_k_event_logger_interrupt
+	pop_s blink
+	pop_s r0
+	seti r0
+.endm
+#else
+	#define log_interrupt_k_event
 #endif
 
 #if defined(CONFIG_SYS_POWER_MANAGEMENT)
 .macro exit_tickless_idle
 	clri r0 /* do not interrupt exiting tickless idle operations */
+	push_s r1
+	push_s r0
 	mov_s r1, _kernel
 	ld_s r0, [r1, _kernel_offset_to_idle] /* requested idle duration */
 	breq r0, 0, _skip_sys_power_save_idle_exit
 
 	st 0, [r1, _kernel_offset_to_idle] /* zero idle duration */
 	push_s blink
-	jl z_sys_power_save_idle_exit
+	jl _sys_power_save_idle_exit
 	pop_s blink
 
 _skip_sys_power_save_idle_exit:
+	pop_s r0
+	pop_s r1
 	seti r0
 .endm
 #else
@@ -266,63 +336,23 @@ _skip_sys_power_save_idle_exit:
 SECTION_FUNC(TEXT, _isr_demux)
 	push_s r3
 
-/* according to ARCv2 ISA, r25, r30, r58, r59 are caller-saved
- * scratch registers, possibly used by interrupt handlers
- */
-	push r25
-	push r30
-#ifdef CONFIG_ARC_HAS_ACCL_REGS
-	push r58
-	push r59
-#endif
-
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	bl read_timer_start_of_isr
-#endif
-
-#if defined(CONFIG_TRACING)
-	bl sys_trace_isr_enter
-#endif
 	/* cannot be done before this point because we must be able to run C */
 	/* r0 is available to be stomped here, and exit_tickless_idle uses it */
 	exit_tickless_idle
+	log_interrupt_k_event
+	log_sleep_k_event
 
 	lr r0, [_ARC_V2_ICAUSE]
-	/* handle software triggered interrupt */
-	lr r3, [_ARC_V2_AUX_IRQ_HINT]
-	brne r3, r0, irq_hint_handled
-	sr 0, [_ARC_V2_AUX_IRQ_HINT]
-irq_hint_handled:
-
 	sub r0, r0, 16
 
-	mov_s r1, _sw_isr_table
+	mov r1, _sw_isr_table
 	add3 r0, r1, r0   /* table entries are 8-bytes wide */
 
 	ld_s r1, [r0, 4] /* ISR into r1 */
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	push_s r0
-	push_s r1
-	bl read_timer_end_of_isr
-	pop_s r1
-	pop_s r0
-#endif
 	jl_s.d [r1]
 	ld_s r0, [r0] /* delay slot: ISR parameter into r0  */
 
-#ifdef CONFIG_TRACING_ISR
-	bl sys_trace_isr_exit
-#endif
-
-#ifdef CONFIG_ARC_HAS_ACCL_REGS
-	pop r59
-	pop r58
-#endif
-
-	pop r30
-	pop r25
-
 	/* back from ISR, jump to exit stub */
 	pop_s r3
 	j_s [r3]
-	nop_s
+	nop

arch/arc/core/mpu/CMakeLists.txt

@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library()
-
-zephyr_library_sources_if_kconfig(arc_core_mpu.c)
-zephyr_library_sources_if_kconfig(arc_mpu.c)

arch/arc/core/mpu/Kconfig

@@ -1,37 +0,0 @@
-# Memory Protection Unit (MPU) configuration options
-
-# Copyright (c) 2017 Synopsys
-# SPDX-License-Identifier: Apache-2.0
-
-config ARC_MPU_VER
-	int "ARC MPU version"
-	range 2 4
-	default 2
-	help
-	  ARC MPU has several versions. For MPU v2, the minimum region is 2048 bytes;
-	  For MPU v3, the minimum region is 32 bytes
-
-config ARC_CORE_MPU
-	bool "ARC Core MPU functionalities"
-	help
-	  ARC core MPU functionalities
-
-config MPU_STACK_GUARD
-	bool "Thread Stack Guards"
-	depends on ARC_CORE_MPU && ARC_MPU_VER !=2
-	help
-	  Enable thread stack guards via MPU. ARC supports built-in stack protection.
-	  If your core supports that, it is preferred over MPU stack guard.
-	  For ARC_MPU_VER == 2, it requires 2048 extra bytes and a strong start address
-	  alignment, this will bring big waste of memory, so no support for it.
-
-config ARC_MPU
-	bool "ARC MPU Support"
-	select ARC_CORE_MPU
-	select THREAD_STACK_INFO
-	select MEMORY_PROTECTION
-	select GEN_PRIV_STACKS if ARC_MPU_VER = 2
-	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if ARC_MPU_VER = 2
-	select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if ARC_MPU_VER = 3
-	help
-	  Target has ARC MPU (currently only works for EMSK 2.2/2.3 ARCEM7D)

arch/arc/core/mpu/arc_core_mpu.c

@@ -1,101 +0,0 @@
-/*
- * Copyright (c) 2017 Synopsys.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <device.h>
-#include <init.h>
-#include <kernel.h>
-#include <soc.h>
-#include <arch/arc/v2/mpu/arc_core_mpu.h>
-#include <kernel_structs.h>
-
-/*
- * @brief Configure MPU for the thread
- *
- * This function configures per thread memory map reprogramming the MPU.
- *
- * @param thread thread info data structure.
- */
-void configure_mpu_thread(struct k_thread *thread)
-{
-	arc_core_mpu_disable();
-	arc_core_mpu_configure_thread(thread);
-	arc_core_mpu_enable();
-}
-
-#if defined(CONFIG_USERSPACE)
-
-int arch_mem_domain_max_partitions_get(void)
-{
-	return arc_core_mpu_get_max_domain_partition_regions();
-}
-
-/*
- * Reset MPU region for a single memory partition
- */
-void arch_mem_domain_partition_remove(struct k_mem_domain *domain,
-				      u32_t partition_id)
-{
-	if (_current->mem_domain_info.mem_domain != domain) {
-		return;
-	}
-
-	arc_core_mpu_disable();
-	arc_core_mpu_remove_mem_partition(domain, partition_id);
-	arc_core_mpu_enable();
-}
-
-/*
- * Configure MPU memory domain
- */
-void arch_mem_domain_thread_add(struct k_thread *thread)
-{
-	if (_current != thread) {
-		return;
-	}
-
-	arc_core_mpu_disable();
-	arc_core_mpu_configure_mem_domain(thread);
-	arc_core_mpu_enable();
-}
-
-/*
- * Destroy MPU regions for the mem domain
- */
-void arch_mem_domain_destroy(struct k_mem_domain *domain)
-{
-	if (_current->mem_domain_info.mem_domain != domain) {
-		return;
-	}
-
-	arc_core_mpu_disable();
-	arc_core_mpu_remove_mem_domain(domain);
-	arc_core_mpu_enable();
-}
-
-void arch_mem_domain_partition_add(struct k_mem_domain *domain,
-				   u32_t partition_id)
-{
-	/* No-op on this architecture */
-}
-
-void arch_mem_domain_thread_remove(struct k_thread *thread)
-{
-	if (_current != thread) {
-		return;
-	}
-
-	arch_mem_domain_destroy(thread->mem_domain_info.mem_domain);
-}
-
-/*
- * Validate the given buffer is user accessible or not
- */
-int arch_buffer_validate(void *addr, size_t size, int write)
-{
-	return arc_core_mpu_buffer_validate(addr, size, write);
-}
-
-#endif

arch/arc/core/mpu/arc_mpu.c

@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2019 Synopsys.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <device.h>
-#include <init.h>
-#include <kernel.h>
-#include <soc.h>
-#include <arch/arc/v2/aux_regs.h>
-#include <arch/arc/v2/mpu/arc_mpu.h>
-#include <arch/arc/v2/mpu/arc_core_mpu.h>
-#include <linker/linker-defs.h>
-
-#define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
-#include <logging/log.h>
-LOG_MODULE_REGISTER(mpu);
-
-/**
- * @brief Get the number of supported MPU regions
- *
- */
-static inline u8_t get_num_regions(void)
-{
-	u32_t num = z_arc_v2_aux_reg_read(_ARC_V2_MPU_BUILD);
-
-	num = (num & 0xFF00U) >> 8U;
-
-	return (u8_t)num;
-}
-
-/**
- * This internal function is utilized by the MPU driver to parse the intent
- * type (i.e. THREAD_STACK_REGION) and return the correct parameter set.
- */
-static inline u32_t get_region_attr_by_type(u32_t type)
-{
-	switch (type) {
-	case THREAD_STACK_USER_REGION:
-		return REGION_RAM_ATTR;
-	case THREAD_STACK_REGION:
-		return AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR;
-	case THREAD_APP_DATA_REGION:
-		return REGION_RAM_ATTR;
-	case THREAD_STACK_GUARD_REGION:
-		/* no Write and Execute to guard region */
-		return AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR;
-	default:
-		/* unknown type */
-		return 0;
-	}
-}
-
-#if CONFIG_ARC_MPU_VER == 2
-#include "arc_mpu_v2_internal.h"
-#elif CONFIG_ARC_MPU_VER == 3
-#include "arc_mpu_v3_internal.h"
-#endif

arch/arc/core/mpu/arc_mpu_v2_internal.h

@@ -1,433 +0,0 @@
-/*
- * Copyright (c) 2019 Synopsys.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V2_INTERNAL_H_
-#define ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V2_INTERNAL_H_
-
-#define AUX_MPU_RDB_VALID_MASK (0x1)
-#define AUX_MPU_EN_ENABLE   (0x40000000)
-#define AUX_MPU_EN_DISABLE  (0xBFFFFFFF)
-
-#define AUX_MPU_RDP_REGION_SIZE(bits) \
-	(((bits - 1) & 0x3) | (((bits - 1) & 0x1C) << 7))
-
-#define AUX_MPU_RDP_ATTR_MASK (0x1FC)
-#define AUX_MPU_RDP_SIZE_MASK (0xE03)
-
-#define _ARC_V2_MPU_EN   (0x409)
-#define _ARC_V2_MPU_RDB0 (0x422)
-#define _ARC_V2_MPU_RDP0 (0x423)
-
-/* For MPU version 2, the minimum protection region size is 2048 bytes */
-#define ARC_FEATURE_MPU_ALIGNMENT_BITS 11
-
-/**
- * This internal function initializes a MPU region
- */
-static inline void _region_init(u32_t index, u32_t region_addr, u32_t size,
-				u32_t region_attr)
-{
-	u8_t bits = find_msb_set(size) - 1;
-
-	index = index * 2U;
-
-	if (bits < ARC_FEATURE_MPU_ALIGNMENT_BITS) {
-		bits = ARC_FEATURE_MPU_ALIGNMENT_BITS;
-	}
-
-	if ((1 << bits) < size) {
-		bits++;
-	}
-
-	if (size > 0) {
-		region_attr &= ~(AUX_MPU_RDP_SIZE_MASK);
-		region_attr |= AUX_MPU_RDP_REGION_SIZE(bits);
-		region_addr |= AUX_MPU_RDB_VALID_MASK;
-	} else {
-		region_addr = 0U;
-	}
-
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_RDP0 + index, region_attr);
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_RDB0 + index, region_addr);
-}
-
-/**
- * This internal function is utilized by the MPU driver to parse the intent
- * type (i.e. THREAD_STACK_REGION) and return the correct region index.
- */
-static inline int get_region_index_by_type(u32_t type)
-{
-	/*
-	 * The new MPU regions are allocated per type after the statically
-	 * configured regions. The type is one-indexed rather than
-	 * zero-indexed.
-	 *
-	 * For ARC MPU v2, the smaller index has higher priority, so the
-	 * index is allocated in reverse order. Static regions start from
-	 * the biggest index, then thread related regions.
-	 *
-	 */
-	switch (type) {
-	case THREAD_STACK_USER_REGION:
-		return get_num_regions() - mpu_config.num_regions
-		       - THREAD_STACK_REGION;
-	case THREAD_STACK_REGION:
-	case THREAD_APP_DATA_REGION:
-	case THREAD_DOMAIN_PARTITION_REGION:
-		/*
-		 * Start domain partition region from stack guard region
-		 * since stack guard is not supported.
-		 */
-		return get_num_regions() - mpu_config.num_regions - type + 1;
-	default:
-		__ASSERT(0, "Unsupported type");
-		return -EINVAL;
-	}
-}
-
-/**
- * This internal function checks if region is enabled or not
- */
-static inline bool _is_enabled_region(u32_t r_index)
-{
-	return ((z_arc_v2_aux_reg_read(_ARC_V2_MPU_RDB0 + r_index * 2U)
-		 & AUX_MPU_RDB_VALID_MASK) == AUX_MPU_RDB_VALID_MASK);
-}
-
-/**
- * This internal function check if the given buffer in in the region
- */
-static inline bool _is_in_region(u32_t r_index, u32_t start, u32_t size)
-{
-	u32_t r_addr_start;
-	u32_t r_addr_end;
-	u32_t r_size_lshift;
-
-	r_addr_start = z_arc_v2_aux_reg_read(_ARC_V2_MPU_RDB0 + r_index * 2U)
-		       & (~AUX_MPU_RDB_VALID_MASK);
-	r_size_lshift = z_arc_v2_aux_reg_read(_ARC_V2_MPU_RDP0 + r_index * 2U)
-			& AUX_MPU_RDP_SIZE_MASK;
-	r_size_lshift = (r_size_lshift & 0x3) | ((r_size_lshift >> 7) & 0x1C);
-	r_addr_end = r_addr_start  + (1 << (r_size_lshift + 1));
-
-	if (start >= r_addr_start && (start + size) <= r_addr_end) {
-		return 1;
-	}
-
-	return 0;
-}
-
-/**
- * This internal function check if the region is user accessible or not
- */
-static inline bool _is_user_accessible_region(u32_t r_index, int write)
-{
-	u32_t r_ap;
-
-	r_ap = z_arc_v2_aux_reg_read(_ARC_V2_MPU_RDP0 + r_index * 2U);
-
-	r_ap &= AUX_MPU_RDP_ATTR_MASK;
-
-	if (write) {
-		return ((r_ap & (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW)) ==
-			(AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW));
-	}
-
-	return ((r_ap & (AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR)) ==
-		(AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR));
-}
-
-/**
- * @brief configure the base address and size for an MPU region
- *
- * @param type MPU region type
- * @param base base address in RAM
- * @param size size of the region
- */
-static inline int _mpu_configure(u8_t type, u32_t base, u32_t size)
-{
-	s32_t region_index =  get_region_index_by_type(type);
-	u32_t region_attr = get_region_attr_by_type(type);
-
-	LOG_DBG("Region info: 0x%x 0x%x", base, size);
-
-	if (region_attr == 0U || region_index < 0) {
-		return -EINVAL;
-	}
-
-	/*
-	 * For ARC MPU v2, MPU regions can be overlapped, smaller
-	 * region index has higher priority.
-	 */
-	_region_init(region_index, base, size, region_attr);
-
-	return 0;
-}
-
-/* ARC Core MPU Driver API Implementation for ARC MPUv2 */
-
-/**
- * @brief enable the MPU
- */
-void arc_core_mpu_enable(void)
-{
-	/* Enable MPU */
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN,
-		z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) | AUX_MPU_EN_ENABLE);
-}
-
-/**
- * @brief disable the MPU
- */
-void arc_core_mpu_disable(void)
-{
-	/* Disable MPU */
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN,
-		z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) & AUX_MPU_EN_DISABLE);
-}
-
-/**
- * @brief configure the thread's MPU regions
- *
- * @param thread the target thread
- */
-void arc_core_mpu_configure_thread(struct k_thread *thread)
-{
-#if defined(CONFIG_USERSPACE)
-	/* configure stack region of user thread */
-	if (thread->base.user_options & K_USER) {
-		LOG_DBG("configure user thread %p's stack", thread);
-		if (_mpu_configure(THREAD_STACK_USER_REGION,
-		(u32_t)thread->stack_obj, thread->stack_info.size) < 0) {
-			LOG_ERR("user thread %p's stack failed", thread);
-			return;
-		}
-	}
-
-	LOG_DBG("configure thread %p's domain", thread);
-	arc_core_mpu_configure_mem_domain(thread);
-#endif
-}
-
-
-/**
- * @brief configure the default region
- *
- * @param region_attr region attribute of default region
- */
-void arc_core_mpu_default(u32_t region_attr)
-{
-	u32_t val =  z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) &
-		    (~AUX_MPU_RDP_ATTR_MASK);
-
-	region_attr &= AUX_MPU_RDP_ATTR_MASK;
-
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, region_attr | val);
-}
-
-/**
- * @brief configure the MPU region
- *
- * @param index   MPU region index
- * @param base    base address
- * @param region_attr region attribute
- */
-int arc_core_mpu_region(u32_t index, u32_t base, u32_t size,
-			 u32_t region_attr)
-{
-	if (index >= get_num_regions()) {
-		return -EINVAL;
-	}
-
-	region_attr &= AUX_MPU_RDP_ATTR_MASK;
-
-	_region_init(index, base, size, region_attr);
-
-	return 0;
-}
-
-#if defined(CONFIG_USERSPACE)
-
-/**
- * @brief configure MPU regions for the memory partitions of the memory domain
- *
- * @param thread the thread which has memory domain
- */
-void arc_core_mpu_configure_mem_domain(struct k_thread *thread)
-{
-	int region_index =
-		get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
-	u32_t num_partitions;
-	struct k_mem_partition *pparts;
-	struct k_mem_domain *mem_domain = NULL;
-
-	if (thread) {
-		mem_domain = thread->mem_domain_info.mem_domain;
-	}
-
-	if (mem_domain) {
-		LOG_DBG("configure domain: %p", mem_domain);
-		num_partitions = mem_domain->num_partitions;
-		pparts = mem_domain->partitions;
-	} else {
-		LOG_DBG("disable domain partition regions");
-		num_partitions = 0U;
-		pparts = NULL;
-	}
-
-	for (; region_index >= 0; region_index--) {
-		if (num_partitions) {
-			LOG_DBG("set region 0x%x 0x%lx 0x%x",
-				region_index, pparts->start, pparts->size);
-			_region_init(region_index, pparts->start,
-			 pparts->size, pparts->attr);
-			num_partitions--;
-		} else {
-			/* clear the left mpu entries */
-			_region_init(region_index, 0, 0, 0);
-		}
-		pparts++;
-	}
-}
-
-/**
- * @brief remove MPU regions for the memory partitions of the memory domain
- *
- * @param mem_domain the target memory domain
- */
-void arc_core_mpu_remove_mem_domain(struct k_mem_domain *mem_domain)
-{
-	ARG_UNUSED(mem_domain);
-
-	int region_index =
-		get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
-
-	for (; region_index >= 0; region_index--) {
-		_region_init(region_index, 0, 0, 0);
-	}
-}
-
-/**
- * @brief reset MPU region for a single memory partition
- *
- * @param domain  the target memory domain
- * @param partition_id  memory partition id
- */
-void arc_core_mpu_remove_mem_partition(struct k_mem_domain *domain,
-			u32_t part_id)
-{
-	ARG_UNUSED(domain);
-
-	int region_index =
-		get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
-
-	LOG_DBG("disable region 0x%x", region_index + part_id);
-	/* Disable region */
-	_region_init(region_index + part_id, 0, 0, 0);
-}
-
-/**
- * @brief get the maximum number of free regions for memory domain partitions
- */
-int arc_core_mpu_get_max_domain_partition_regions(void)
-{
-	return get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION) + 1;
-}
-
-/**
- * @brief validate the given buffer is user accessible or not
- */
-int arc_core_mpu_buffer_validate(void *addr, size_t size, int write)
-{
-	int r_index;
-
-	/*
-	 * For ARC MPU v2, smaller region number takes priority.
-	 * we can stop the iteration immediately once we find the
-	 * matched region that grants permission or denies access.
-	 *
-	 */
-	for (r_index = 0; r_index < get_num_regions(); r_index++) {
-		if (!_is_enabled_region(r_index) ||
-		    !_is_in_region(r_index, (u32_t)addr, size)) {
-			continue;
-		}
-
-		if (_is_user_accessible_region(r_index, write)) {
-			return 0;
-		} else {
-			return -EPERM;
-		}
-	}
-
-	return -EPERM;
-}
-#endif /* CONFIG_USERSPACE */
-
-/* ARC MPU Driver Initial Setup */
-/*
- * @brief MPU default initialization and configuration
- *
- * This function provides the default configuration mechanism for the Memory
- * Protection Unit (MPU).
- */
-static int arc_mpu_init(struct device *arg)
-{
-	ARG_UNUSED(arg);
-
-	u32_t num_regions;
-	u32_t i;
-
-	num_regions = get_num_regions();
-
-	/* ARC MPU supports up to 16 Regions */
-	if (mpu_config.num_regions > num_regions) {
-		__ASSERT(0,
-		"Request to configure: %u regions (supported: %u)\n",
-		mpu_config.num_regions, num_regions);
-		return -EINVAL;
-	}
-
-	/* Disable MPU */
-	arc_core_mpu_disable();
-
-	int r_index;
-	/*
-	 * the MPU regions are filled in the reverse order.
-	 * According to ARCv2 ISA, the MPU region with smaller
-	 * index has higher priority. The static background MPU
-	 * regions in mpu_config will be in the bottom. Then
-	 * the special type regions will be above.
-	 *
-	 */
-	r_index = num_regions - mpu_config.num_regions;
-
-	/* clear all the regions first */
-	for (i = 0U; i < r_index; i++) {
-		_region_init(i, 0, 0, 0);
-	}
-
-	/* configure the static regions */
-	for (i = 0U; i < mpu_config.num_regions; i++) {
-		_region_init(r_index,
-			     mpu_config.mpu_regions[i].base,
-			     mpu_config.mpu_regions[i].size,
-			     mpu_config.mpu_regions[i].attr);
-		r_index++;
-	}
-
-	/* default region: no read, write and execute */
-	arc_core_mpu_default(0);
-
-	/* Enable MPU */
-	arc_core_mpu_enable();
-
-	return 0;
-}
-
-SYS_INIT(arc_mpu_init, PRE_KERNEL_1,
-	 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
-#endif /* ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V2_INTERNAL_H_ */

arch/arc/core/mpu/arc_mpu_v3_internal.h

@@ -1,918 +0,0 @@
-/*
- * Copyright (c) 2019 Synopsys.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V3_INTERNAL_H_
-#define ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V3_INTERNAL_H_
-
-#define AUX_MPU_RPER_SID1       0x10000
-/* valid mask: SID1+secure+valid */
-#define AUX_MPU_RPER_VALID_MASK ((0x1) | AUX_MPU_RPER_SID1 | AUX_MPU_ATTR_S)
-
-#define AUX_MPU_RPER_ATTR_MASK (0x1FF)
-
-#define _ARC_V2_MPU_EN   (0x409)
-
-/* aux regs added in MPU version 3 */
-#define _ARC_V2_MPU_INDEX       (0x448) /* MPU index */
-#define _ARC_V2_MPU_RSTART      (0x449) /* MPU region start address */
-#define _ARC_V2_MPU_REND        (0x44A) /* MPU region end address */
-#define _ARC_V2_MPU_RPER        (0x44B) /* MPU region permission register */
-#define _ARC_V2_MPU_PROBE       (0x44C) /* MPU probe register */
-
-
-/* For MPU version 3, the minimum protection region size is 32 bytes */
-#define ARC_FEATURE_MPU_ALIGNMENT_BITS 5
-
-#define CALC_REGION_END_ADDR(start, size) \
-	(start + size - (1 << ARC_FEATURE_MPU_ALIGNMENT_BITS))
-
-/* ARC MPU version 3 does not support mpu region overlap in hardware
- * so if we want to allocate MPU region dynamically, e.g. thread stack,
- * memory domain from a background region, a dynamic region splitting
- * approach is designed. pls see comments in
- *          _dynamic_region_allocate_and_init
- * But this approach has an impact on performance of thread switch.
- * As a trade off, we can use the default mpu region as the background region
- * to avoid the dynamic region splitting. This will give more privilege to
- * codes in kernel mode which can access the memory region not covered by
- * explicit mpu entry. Considering  memory protection is mainly used to
- * isolate malicious codes in user mode, it makes sense to get better
- * thread switch performance through default mpu region.
- * CONFIG_MPU_GAP_FILLING is used to turn this on/off.
- *
- */
-#if defined(CONFIG_MPU_GAP_FILLING)
-
-#if defined(CONFIG_USERSPACE) && defined(CONFIG_MPU_STACK_GUARD)
-/* 1 for stack guard , 1 for user thread, 1 for split */
-#define MPU_REGION_NUM_FOR_THREAD 3
-#elif defined(CONFIG_USERSPACE) || defined(CONFIG_MPU_STACK_GUARD)
-/* 1 for stack guard or user thread stack , 1 for split */
-#define MPU_REGION_NUM_FOR_THREAD 2
-#else
-#define MPU_REGION_NUM_FOR_THREAD 0
-#endif
-
-#define MPU_DYNAMIC_REGION_AREAS_NUM 2
-
-/**
- * @brief internal structure holding information of
- * memory areas where dynamic MPU programming is allowed.
- */
-struct dynamic_region_info {
-	u8_t index;
-	u32_t base;
-	u32_t size;
-	u32_t attr;
-};
-
-static u8_t dynamic_regions_num;
-static u8_t dynamic_region_index;
-
-/**
- * Global array, holding the MPU region index of
- * the memory region inside which dynamic memory
- * regions may be configured.
- */
-static struct dynamic_region_info dyn_reg_info[MPU_DYNAMIC_REGION_AREAS_NUM];
-#endif /* CONFIG_MPU_GAP_FILLING */
-
-static u8_t static_regions_num;
-
-#ifdef CONFIG_ARC_NORMAL_FIRMWARE
-/* \todo through secure service to access mpu */
-static inline void _region_init(u32_t index, u32_t region_addr, u32_t size,
-				u32_t region_attr)
-{
-}
-
-static inline void _region_set_attr(u32_t index, u32_t attr)
-{
-
-}
-
-static inline u32_t _region_get_attr(u32_t index)
-{
-	return 0;
-}
-
-static inline u32_t _region_get_start(u32_t index)
-{
-	return 0;
-}
-
-static inline void _region_set_start(u32_t index, u32_t start)
-{
-
-}
-
-static inline u32_t _region_get_end(u32_t index)
-{
-	return 0;
-}
-
-static inline void _region_set_end(u32_t index, u32_t end)
-{
-}
-
-/**
- * This internal function probes the given addr's MPU index.if not
- * in MPU, returns error
- */
-static inline int _mpu_probe(u32_t addr)
-{
-	return -EINVAL;
-}
-
-/**
- * This internal function checks if MPU region is enabled or not
- */
-static inline bool _is_enabled_region(u32_t r_index)
-{
-	return false;
-}
-
-/**
- * This internal function check if the region is user accessible or not
- */
-static inline bool _is_user_accessible_region(u32_t r_index, int write)
-{
-	return false;
-}
-#else /* CONFIG_ARC_NORMAL_FIRMWARE */
-/* the following functions are prepared for SECURE_FRIMWARE */
-static inline void _region_init(u32_t index, u32_t region_addr, u32_t size,
-				u32_t region_attr)
-{
-	if (size < (1 << ARC_FEATURE_MPU_ALIGNMENT_BITS)) {
-		size = (1 << ARC_FEATURE_MPU_ALIGNMENT_BITS);
-	}
-
-	if (region_attr) {
-		region_attr &= AUX_MPU_RPER_ATTR_MASK;
-		region_attr |=  AUX_MPU_RPER_VALID_MASK;
-	}
-
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, index);
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_RSTART, region_addr);
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_REND,
-			CALC_REGION_END_ADDR(region_addr, size));
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_RPER, region_attr);
-}
-
-static inline void _region_set_attr(u32_t index, u32_t attr)
-{
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, index);
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_RPER, attr |
-				 AUX_MPU_RPER_VALID_MASK);
-}
-
-static inline u32_t _region_get_attr(u32_t index)
-{
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, index);
-
-	return z_arc_v2_aux_reg_read(_ARC_V2_MPU_RPER);
-}
-
-static inline u32_t _region_get_start(u32_t index)
-{
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, index);
-
-	return z_arc_v2_aux_reg_read(_ARC_V2_MPU_RSTART);
-}
-
-static inline void _region_set_start(u32_t index, u32_t start)
-{
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, index);
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_RSTART, start);
-}
-
-static inline u32_t _region_get_end(u32_t index)
-{
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, index);
-
-	return z_arc_v2_aux_reg_read(_ARC_V2_MPU_REND) +
-		(1 << ARC_FEATURE_MPU_ALIGNMENT_BITS);
-}
-
-static inline void _region_set_end(u32_t index, u32_t end)
-{
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, index);
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_REND, end -
-		(1 << ARC_FEATURE_MPU_ALIGNMENT_BITS));
-}
-
-/**
- * This internal function probes the given addr's MPU index.if not
- * in MPU, returns error
- */
-static inline int _mpu_probe(u32_t addr)
-{
-	u32_t val;
-
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_PROBE, addr);
-	val = z_arc_v2_aux_reg_read(_ARC_V2_MPU_INDEX);
-
-	/* if no match or multiple regions match, return error */
-	if (val & 0xC0000000) {
-		return -EINVAL;
-	} else {
-		return val;
-	}
-}
-
-/**
- * This internal function checks if MPU region is enabled or not
- */
-static inline bool _is_enabled_region(u32_t r_index)
-{
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, r_index);
-	return ((z_arc_v2_aux_reg_read(_ARC_V2_MPU_RPER) &
-		 AUX_MPU_RPER_VALID_MASK) == AUX_MPU_RPER_VALID_MASK);
-}
-
-/**
- * This internal function check if the region is user accessible or not
- */
-static inline bool _is_user_accessible_region(u32_t r_index, int write)
-{
-	u32_t r_ap;
-
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_INDEX, r_index);
-	r_ap = z_arc_v2_aux_reg_read(_ARC_V2_MPU_RPER);
-	r_ap &= AUX_MPU_RPER_ATTR_MASK;
-
-	if (write) {
-		return ((r_ap & (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW)) ==
-			(AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW));
-	}
-
-	return ((r_ap & (AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR)) ==
-		(AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR));
-}
-
-#endif /* CONFIG_ARC_NORMAL_FIRMWARE */
-
-/**
- * This internal function checks the area given by (start, size)
- * and returns the index if the area match one MPU entry
- */
-static inline int _get_region_index(u32_t start, u32_t size)
-{
-	int index = _mpu_probe(start);
-
-	if (index > 0 && index == _mpu_probe(start + size - 1)) {
-		return index;
-	}
-
-	return -EINVAL;
-}
-
-#if defined(CONFIG_MPU_GAP_FILLING)
-/**
- * This internal function allocates a dynamic MPU region and returns
- * the index or error
- */
-static inline int _dynamic_region_allocate_index(void)
-{
-	if (dynamic_region_index >= get_num_regions()) {
-		LOG_ERR("no enough mpu entries %d", dynamic_region_index);
-		return -EINVAL;
-	}
-
-	return dynamic_region_index++;
-}
-
-/* @brief allocate and init a dynamic MPU region
- *
- * This internal function performs the allocation and initialization of
- * a dynamic MPU region
- *
- * @param base region base
- * @param size region size
- * @param attr region attribute
- * @return  <0 failure, >0  allocated dynamic region index
- */
-static int _dynamic_region_allocate_and_init(u32_t base, u32_t size,
-	 u32_t attr)
-{
-	int u_region_index = _get_region_index(base, size);
-	int region_index;
-
-	LOG_DBG("Region info: base 0x%x size 0x%x attr 0x%x", base, size, attr);
-
-	if (u_region_index == -EINVAL) {
-		/* no underlying region */
-
-		region_index = _dynamic_region_allocate_index();
-
-		if (region_index > 0) {
-		/* a new region */
-			_region_init(region_index, base, size, attr);
-		}
-
-		return region_index;
-	}
-
-	/*
-	 * The new memory region is to be placed inside the underlying
-	 * region, possibly splitting the underlying region into two.
-	 */
-
-	u32_t u_region_start = _region_get_start(u_region_index);
-	u32_t u_region_end = _region_get_end(u_region_index);
-	u32_t u_region_attr = _region_get_attr(u_region_index);
-	u32_t end = base + size;
-
-
-	if ((base == u_region_start) && (end == u_region_end)) {
-		/* The new region overlaps entirely with the
-		 * underlying region. In this case we simply
-		 * update the partition attributes of the
-		 * underlying region with those of the new
-		 * region.
-		 */
-		_region_init(u_region_index, base, size, attr);
-		region_index = u_region_index;
-	} else if (base == u_region_start) {
-		/* The new region starts exactly at the start of the
-		 * underlying region; the start of the underlying
-		 * region needs to be set to the end of the new region.
-		 */
-		_region_set_start(u_region_index, base + size);
-		_region_set_attr(u_region_index, u_region_attr);
-
-		region_index = _dynamic_region_allocate_index();
-
-		if (region_index > 0) {
-			_region_init(region_index, base, size, attr);
-		}
-
-	} else if (end == u_region_end) {
-		/* The new region ends exactly at the end of the
-		 * underlying region; the end of the underlying
-		 * region needs to be set to the start of the
-		 * new region.
-		 */
-		_region_set_end(u_region_index, base);
-		_region_set_attr(u_region_index, u_region_attr);
-
-		region_index = _dynamic_region_allocate_index();
-
-		if (region_index > 0) {
-			_region_init(region_index, base, size, attr);
-		}
-
-	} else {
-		/* The new region lies strictly inside the
-		 * underlying region, which needs to split
-		 * into two regions.
-		 */
-
-		_region_set_end(u_region_index, base);
-		_region_set_attr(u_region_index, u_region_attr);
-
-		region_index = _dynamic_region_allocate_index();
-
-		if (region_index > 0) {
-			_region_init(region_index, base, size, attr);
-
-			region_index = _dynamic_region_allocate_index();
-
-			if (region_index > 0) {
-				_region_init(region_index, base + size,
-				 u_region_end - end, u_region_attr);
-			}
-		}
-	}
-
-	return region_index;
-}
-
-/* @brief reset the dynamic MPU regions
- *
- * This internal function performs the reset of dynamic MPU regions
- */
-static void _mpu_reset_dynamic_regions(void)
-{
-	u32_t i;
-	u32_t num_regions = get_num_regions();
-
-	for (i = static_regions_num; i < num_regions; i++) {
-		_region_init(i, 0, 0, 0);
-	}
-
-	for (i = 0U; i < dynamic_regions_num; i++) {
-		_region_init(
-			dyn_reg_info[i].index,
-			dyn_reg_info[i].base,
-			dyn_reg_info[i].size,
-			dyn_reg_info[i].attr);
-	}
-
-	/* dynamic regions are after static regions */
-	dynamic_region_index = static_regions_num;
-}
-
-/**
- * @brief configure the base address and size for an MPU region
- *
- * @param   type    MPU region type
- * @param   base    base address in RAM
- * @param   size    size of the region
- */
-static inline int _mpu_configure(u8_t type, u32_t base, u32_t size)
-{
-	u32_t region_attr = get_region_attr_by_type(type);
-
-	return _dynamic_region_allocate_and_init(base, size, region_attr);
-}
-#else
-/**
- * This internal function is utilized by the MPU driver to parse the intent
- * type (i.e. THREAD_STACK_REGION) and return the correct region index.
- */
-static inline int get_region_index_by_type(u32_t type)
-{
-	/*
-	 * The new MPU regions are allocated per type after the statically
-	 * configured regions. The type is one-indexed rather than
-	 * zero-indexed.
-	 *
-	 * For ARC MPU v2, the smaller index has higher priority, so the
-	 * index is allocated in reverse order. Static regions start from
-	 * the biggest index, then thread related regions.
-	 *
-	 */
-	switch (type) {
-	case THREAD_STACK_USER_REGION:
-		return static_regions_num + THREAD_STACK_REGION;
-	case THREAD_STACK_REGION:
-	case THREAD_APP_DATA_REGION:
-	case THREAD_STACK_GUARD_REGION:
-		return static_regions_num + type;
-	case THREAD_DOMAIN_PARTITION_REGION:
-#if defined(CONFIG_MPU_STACK_GUARD)
-		return static_regions_num + type;
-#else
-		/*
-		 * Start domain partition region from stack guard region
-		 * since stack guard is not enabled.
-		 */
-		return static_regions_num + type - 1;
-#endif
-	default:
-		__ASSERT(0, "Unsupported type");
-		return -EINVAL;
-	}
-}
-
-/**
- * @brief configure the base address and size for an MPU region
- *
- * @param   type    MPU region type
- * @param   base    base address in RAM
- * @param   size    size of the region
- */
-static inline int _mpu_configure(u8_t type, u32_t base, u32_t size)
-{
-	int region_index =  get_region_index_by_type(type);
-	u32_t region_attr = get_region_attr_by_type(type);
-
-	LOG_DBG("Region info: 0x%x 0x%x", base, size);
-
-	if (region_attr == 0U || region_index < 0) {
-		return -EINVAL;
-	}
-
-	_region_init(region_index, base, size, region_attr);
-
-	return 0;
-}
-#endif
-
-/* ARC Core MPU Driver API Implementation for ARC MPUv3 */
-
-/**
- * @brief enable the MPU
- */
-void arc_core_mpu_enable(void)
-{
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-/* the default region:
- * secure:0x8000, SID:0x10000, KW:0x100 KR:0x80
- */
-#define MPU_ENABLE_ATTR	0x18180
-#else
-#define MPU_ENABLE_ATTR	0
-#endif
-	arc_core_mpu_default(MPU_ENABLE_ATTR);
-}
-
-/**
- * @brief disable the MPU
- */
-void arc_core_mpu_disable(void)
-{
-	/* MPU is always enabled, use default region to
-	 * simulate MPU disable
-	 */
-	arc_core_mpu_default(REGION_ALL_ATTR | AUX_MPU_ATTR_S |
-				AUX_MPU_RPER_SID1);
-}
-
-/**
- * @brief configure the thread's mpu regions
- *
- * @param thread the target thread
- */
-void arc_core_mpu_configure_thread(struct k_thread *thread)
-{
-#if defined(CONFIG_MPU_GAP_FILLING)
-/* the mpu entries of ARC MPUv3 are divided into 2 parts:
- * static entries: global mpu entries, not changed in context switch
- * dynamic entries: MPU entries changed in context switch and
- * memory domain configure, including:
- *    MPU entries for user thread stack
- *    MPU entries for stack guard
- *    MPU entries for mem domain
- *    MPU entries for other thread specific regions
- * before configuring thread specific mpu entries, need to reset dynamic
- * entries
- */
-	_mpu_reset_dynamic_regions();
-#endif
-#if defined(CONFIG_MPU_STACK_GUARD)
-#if defined(CONFIG_USERSPACE)
-	if ((thread->base.user_options & K_USER) != 0U) {
-		/* the areas before and after the user stack of thread is
-		 * kernel only. These area can be used as stack guard.
-		 * -----------------------
-		 * |  kernel only area   |
-		 * |---------------------|
-		 * |  user stack         |
-		 * |---------------------|
-		 * |privilege stack guard|
-		 * |---------------------|
-		 * |  privilege stack    |
-		 * -----------------------
-		 */
-		if (_mpu_configure(THREAD_STACK_GUARD_REGION,
-			thread->arch.priv_stack_start - STACK_GUARD_SIZE,
-			STACK_GUARD_SIZE) < 0) {
-			LOG_ERR("thread %p's stack guard failed", thread);
-			return;
-		}
-	} else {
-		if (_mpu_configure(THREAD_STACK_GUARD_REGION,
-			thread->stack_info.start - STACK_GUARD_SIZE,
-			STACK_GUARD_SIZE) < 0) {
-			LOG_ERR("thread %p's stack guard failed", thread);
-			return;
-		}
-	}
-#else
-	if (_mpu_configure(THREAD_STACK_GUARD_REGION,
-		thread->stack_info.start - STACK_GUARD_SIZE,
-		STACK_GUARD_SIZE) < 0) {
-		LOG_ERR("thread %p's stack guard failed", thread);
-		return;
-	}
-#endif
-#endif
-
-#if defined(CONFIG_USERSPACE)
-	/* configure stack region of user thread */
-	if (thread->base.user_options & K_USER) {
-		LOG_DBG("configure user thread %p's stack", thread);
-		if (_mpu_configure(THREAD_STACK_USER_REGION,
-		(u32_t)thread->stack_obj, thread->stack_info.size) < 0) {
-			LOG_ERR("thread %p's stack failed", thread);
-			return;
-		}
-	}
-
-#if defined(CONFIG_MPU_GAP_FILLING)
-	u32_t num_partitions;
-	struct k_mem_partition *pparts;
-	struct k_mem_domain *mem_domain = thread->mem_domain_info.mem_domain;
-
-	/* configure thread's memory domain */
-	if (mem_domain) {
-		LOG_DBG("configure thread %p's domain: %p",
-		 thread, mem_domain);
-		num_partitions = mem_domain->num_partitions;
-		pparts = mem_domain->partitions;
-	} else {
-		num_partitions = 0U;
-		pparts = NULL;
-	}
-
-	for (u32_t i = 0; i < num_partitions; i++) {
-		if (pparts->size) {
-			if (_dynamic_region_allocate_and_init(pparts->start,
-				pparts->size, pparts->attr) < 0) {
-				LOG_ERR(
-				"thread %p's mem region: %p failed",
-				 thread, pparts);
-				return;
-			}
-		}
-		pparts++;
-	}
-#else
-	arc_core_mpu_configure_mem_domain(thread);
-#endif
-#endif
-}
-
-/**
- * @brief configure the default region
- *
- * @param region_attr region attribute of default region
- */
-void arc_core_mpu_default(u32_t region_attr)
-{
-#ifdef CONFIG_ARC_NORMAL_FIRMWARE
-/* \todo through secure service to access mpu */
-#else
-	z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, region_attr);
-#endif
-}
-
-/**
- * @brief configure the MPU region
- *
- * @param index MPU region index
- * @param base  base address
- * @param size  region size
- * @param region_attr region attribute
- */
-int arc_core_mpu_region(u32_t index, u32_t base, u32_t size,
-			 u32_t region_attr)
-{
-	if (index >= get_num_regions()) {
-		return -EINVAL;
-	}
-
-	region_attr &= AUX_MPU_RPER_ATTR_MASK;
-
-	_region_init(index, base, size, region_attr);
-
-	return 0;
-}
-
-#if defined(CONFIG_USERSPACE)
-/**
- * @brief configure MPU regions for the memory partitions of the memory domain
- *
- * @param thread the thread which has memory domain
- */
-#if defined(CONFIG_MPU_GAP_FILLING)
-void arc_core_mpu_configure_mem_domain(struct k_thread *thread)
-{
-	arc_core_mpu_configure_thread(thread);
-}
-#else
-void arc_core_mpu_configure_mem_domain(struct k_thread *thread)
-{
-	u32_t region_index;
-	u32_t num_partitions;
-	u32_t num_regions;
-	struct k_mem_partition *pparts;
-	struct k_mem_domain *mem_domain = NULL;
-
-	if (thread) {
-		mem_domain = thread->mem_domain_info.mem_domain;
-	}
-
-	if (mem_domain) {
-		LOG_DBG("configure domain: %p", mem_domain);
-		num_partitions = mem_domain->num_partitions;
-		pparts = mem_domain->partitions;
-	} else {
-		LOG_DBG("disable domain partition regions");
-		num_partitions = 0U;
-		pparts = NULL;
-	}
-
-	num_regions = get_num_regions();
-	region_index = get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION);
-
-	while (num_partitions && region_index < num_regions) {
-		if (pparts->size > 0) {
-			LOG_DBG("set region 0x%x 0x%lx 0x%x",
-				region_index, pparts->start, pparts->size);
-			_region_init(region_index, pparts->start,
-				     pparts->size, pparts->attr);
-			region_index++;
-		}
-		pparts++;
-		num_partitions--;
-	}
-
-	while (region_index < num_regions) {
-		/* clear the left mpu entries */
-		_region_init(region_index, 0, 0, 0);
-		region_index++;
-	}
-}
-#endif
-
-/**
- * @brief remove MPU regions for the memory partitions of the memory domain
- *
- * @param mem_domain the target memory domain
- */
-void arc_core_mpu_remove_mem_domain(struct k_mem_domain *mem_domain)
-{
-	u32_t num_partitions;
-	struct k_mem_partition *pparts;
-	int index;
-
-	if (mem_domain) {
-		LOG_DBG("configure domain: %p", mem_domain);
-		num_partitions = mem_domain->num_partitions;
-		pparts = mem_domain->partitions;
-	} else {
-		LOG_DBG("disable domain partition regions");
-		num_partitions = 0U;
-		pparts = NULL;
-	}
-
-	for (u32_t i = 0; i < num_partitions; i++) {
-		if (pparts->size) {
-			index = _get_region_index(pparts->start,
-			 pparts->size);
-			if (index > 0) {
-#if defined(CONFIG_MPU_GAP_FILLING)
-				_region_set_attr(index,
-				REGION_KERNEL_RAM_ATTR);
-#else
-				_region_init(index, 0, 0, 0);
-#endif
-			}
-		}
-		pparts++;
-	}
-}
-
-/**
- * @brief reset MPU region for a single memory partition
- *
- * @param partition_id  memory partition id
- */
-void arc_core_mpu_remove_mem_partition(struct k_mem_domain *domain,
-			u32_t partition_id)
-{
-	struct k_mem_partition *partition = &domain->partitions[partition_id];
-
-	int region_index = _get_region_index(partition->start,
-			 partition->size);
-
-	if (region_index < 0) {
-		return;
-	}
-
-	LOG_DBG("remove region 0x%x", region_index);
-#if defined(CONFIG_MPU_GAP_FILLING)
-	_region_set_attr(region_index, REGION_KERNEL_RAM_ATTR);
-#else
-	_region_init(region_index, 0, 0, 0);
-#endif
-}
-
-/**
- * @brief get the maximum number of free regions for memory domain partitions
- */
-int arc_core_mpu_get_max_domain_partition_regions(void)
-{
-#if defined(CONFIG_MPU_GAP_FILLING)
-	/* consider the worst case: each partition requires split */
-	return (get_num_regions() - MPU_REGION_NUM_FOR_THREAD) / 2;
-#else
-	return get_num_regions() -
-	       get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION) - 1;
-#endif
-}
-
-/**
- * @brief validate the given buffer is user accessible or not
- */
-int arc_core_mpu_buffer_validate(void *addr, size_t size, int write)
-{
-	int r_index;
-	int key = arch_irq_lock();
-
-	/*
-	 * For ARC MPU v3, overlapping is not supported.
-	 * we can stop the iteration immediately once we find the
-	 * matched region that grants permission or denies access.
-	 */
-	r_index = _mpu_probe((u32_t)addr);
-	/*  match and the area is in one region */
-	if (r_index >= 0 && r_index == _mpu_probe((u32_t)addr + (size - 1))) {
-		if (_is_user_accessible_region(r_index, write)) {
-			r_index = 0;
-		} else {
-			r_index = -EPERM;
-		}
-	} else {
-		r_index = -EPERM;
-	}
-
-	arch_irq_unlock(key);
-
-	return r_index;
-}
-#endif /* CONFIG_USERSPACE */
-
-/* ARC MPU Driver Initial Setup */
-/*
- * @brief MPU default initialization and configuration
- *
- * This function provides the default configuration mechanism for the Memory
- * Protection Unit (MPU).
- */
-static int arc_mpu_init(struct device *arg)
-{
-	ARG_UNUSED(arg);
-	u32_t num_regions;
-	u32_t i;
-
-	num_regions = get_num_regions();
-
-	/* ARC MPU supports up to 16 Regions */
-	if (mpu_config.num_regions > num_regions) {
-		__ASSERT(0,
-		"Request to configure: %u regions (supported: %u)\n",
-		mpu_config.num_regions, num_regions);
-		return -EINVAL;
-	}
-
-	static_regions_num = 0;
-
-	/* Disable MPU */
-	arc_core_mpu_disable();
-
-	for (i = 0U; i < mpu_config.num_regions; i++) {
-		/* skip empty region */
-		if (mpu_config.mpu_regions[i].size == 0) {
-			continue;
-		}
-#if defined(CONFIG_MPU_GAP_FILLING)
-		_region_init(static_regions_num,
-			     mpu_config.mpu_regions[i].base,
-			     mpu_config.mpu_regions[i].size,
-			     mpu_config.mpu_regions[i].attr);
-
-		/* record the static region which can be split */
-		if (mpu_config.mpu_regions[i].attr & REGION_DYNAMIC) {
-			if (dynamic_regions_num >=
-			MPU_DYNAMIC_REGION_AREAS_NUM) {
-				LOG_ERR("not enough dynamic regions %d",
-				 dynamic_regions_num);
-				return -EINVAL;
-			}
-
-			dyn_reg_info[dynamic_regions_num].index = i;
-			dyn_reg_info[dynamic_regions_num].base =
-				mpu_config.mpu_regions[i].base;
-			dyn_reg_info[dynamic_regions_num].size =
-				mpu_config.mpu_regions[i].size;
-			dyn_reg_info[dynamic_regions_num].attr =
-				mpu_config.mpu_regions[i].attr;
-
-			dynamic_regions_num++;
-		}
-		static_regions_num++;
-#else
-		/* dynamic region will be covered by default mpu setting
-		 * no need to configure
-		 */
-		if (!(mpu_config.mpu_regions[i].attr & REGION_DYNAMIC)) {
-			_region_init(static_regions_num,
-			     mpu_config.mpu_regions[i].base,
-			     mpu_config.mpu_regions[i].size,
-			     mpu_config.mpu_regions[i].attr);
-			static_regions_num++;
-		}
-#endif
-	}
-
-	for (i = static_regions_num; i < num_regions; i++) {
-		_region_init(i, 0, 0, 0);
-	}
-
-	/* Enable MPU */
-	arc_core_mpu_enable();
-
-	return 0;
-}
-
-SYS_INIT(arc_mpu_init, PRE_KERNEL_1,
-	 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
-#endif /* ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V3_INTERNAL_H_ */

arch/arc/core/offsets/offsets.c

@@ -1,19 +1,30 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
  * @file
- * @brief ARCv2 kernel structure member offset definition file
+ * @brief ARCv2 nano kernel structure member offset definition file
  *
  * This module is responsible for the generation of the absolute symbols whose
- * value represents the member offsets for various ARCv2 kernel structures.
+ * value represents the member offsets for various ARCv2 nanokernel
+ * structures.
  *
  * All of the absolute symbols defined by this module will be present in the
- * final kernel ELF image (due to the linker's reference to the _OffsetAbsSyms
- * symbol).
+ * final microkernel or nanokernel ELF image (due to the linker's reference to
+ * the _OffsetAbsSyms symbol).
  *
  * INTERNAL
  * It is NOT necessary to define the offset for every member of a structure.
@@ -22,25 +33,16 @@
  * completeness.
  */
 
-#include <kernel.h>
-#include <kernel_arch_data.h>
 #include <gen_offset.h>
+#include <kernel_structs.h>
 #include <kernel_offsets.h>
 
+GEN_OFFSET_SYM(_thread_arch_t, intlock_key);
 GEN_OFFSET_SYM(_thread_arch_t, relinquish_cause);
+GEN_OFFSET_SYM(_thread_arch_t, return_value);
 #ifdef CONFIG_ARC_STACK_CHECKING
-GEN_OFFSET_SYM(_thread_arch_t, k_stack_base);
-GEN_OFFSET_SYM(_thread_arch_t, k_stack_top);
-#ifdef CONFIG_USERSPACE
-GEN_OFFSET_SYM(_thread_arch_t, u_stack_base);
-GEN_OFFSET_SYM(_thread_arch_t, u_stack_top);
+GEN_OFFSET_SYM(_thread_arch_t, stack_top);
 #endif
-#endif
-
-#ifdef CONFIG_USERSPACE
-GEN_OFFSET_SYM(_thread_arch_t, priv_stack_start);
-#endif
-
 
 /* ARCv2-specific IRQ stack frame structure member offsets */
 GEN_OFFSET_SYM(_isf_t, r0);
@@ -61,15 +63,7 @@ GEN_OFFSET_SYM(_isf_t, blink);
 GEN_OFFSET_SYM(_isf_t, lp_end);
 GEN_OFFSET_SYM(_isf_t, lp_start);
 GEN_OFFSET_SYM(_isf_t, lp_count);
-#ifdef CONFIG_CODE_DENSITY
-GEN_OFFSET_SYM(_isf_t, ei_base);
-GEN_OFFSET_SYM(_isf_t, ldi_base);
-GEN_OFFSET_SYM(_isf_t, jli_base);
-#endif
 GEN_OFFSET_SYM(_isf_t, pc);
-#ifdef CONFIG_ARC_HAS_SECURE
-GEN_OFFSET_SYM(_isf_t, sec_stat);
-#endif
 GEN_OFFSET_SYM(_isf_t, status32);
 GEN_ABSOLUTE_SYM(___isf_t_SIZEOF, sizeof(_isf_t));
 
@@ -91,30 +85,7 @@ GEN_OFFSET_SYM(_callee_saved_stack_t, r24);
 GEN_OFFSET_SYM(_callee_saved_stack_t, r25);
 GEN_OFFSET_SYM(_callee_saved_stack_t, r26);
 GEN_OFFSET_SYM(_callee_saved_stack_t, fp);
-#ifdef CONFIG_USERSPACE
-#ifdef CONFIG_ARC_HAS_SECURE
-GEN_OFFSET_SYM(_callee_saved_stack_t, kernel_sp);
-GEN_OFFSET_SYM(_callee_saved_stack_t, user_sp);
-#else
-GEN_OFFSET_SYM(_callee_saved_stack_t, user_sp);
-#endif
-#endif
 GEN_OFFSET_SYM(_callee_saved_stack_t, r30);
-#ifdef CONFIG_ARC_HAS_ACCL_REGS
-GEN_OFFSET_SYM(_callee_saved_stack_t, r58);
-GEN_OFFSET_SYM(_callee_saved_stack_t, r59);
-#endif
-#ifdef CONFIG_FPU_SHARING
-GEN_OFFSET_SYM(_callee_saved_stack_t, fpu_status);
-GEN_OFFSET_SYM(_callee_saved_stack_t, fpu_ctrl);
-#ifdef CONFIG_FP_FPU_DA
-GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp2h);
-GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp2l);
-GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp1h);
-GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp1l);
-#endif
-
-#endif
 GEN_ABSOLUTE_SYM(___callee_saved_stack_t_SIZEOF, sizeof(_callee_saved_stack_t));
 
 GEN_ABSOLUTE_SYM(_K_THREAD_NO_FLOAT_SIZEOF, sizeof(struct k_thread));

arch/arc/core/prep_c.c

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -10,22 +20,20 @@
  *
  *
  * Initialization of full C support: zero the .bss, copy the .data if XIP,
- * call z_cstart().
+ * call _Cstart().
  *
  * Stack is available in this module, but not the global data/bss until their
  * initialization is performed.
  */
 
-#include <zephyr/types.h>
+#include <stdint.h>
 #include <toolchain.h>
-#include <linker/linker-defs.h>
+#include <linker-defs.h>
 #include <arch/arc/v2/aux_regs.h>
 #include <kernel_structs.h>
-#include <kernel_internal.h>
+#include <nano_internal.h>
 
 
-/* XXX - keep for future use in full-featured cache APIs */
-#if 0
 /**
  *
  * @brief Disable the i-cache if present
@@ -40,14 +48,14 @@ static void disable_icache(void)
 {
 	unsigned int val;
 
-	val = z_arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
+	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
 	val &= 0xff; /* version field */
 	if (val == 0) {
 		return; /* skip if i-cache is not present */
 	}
-	z_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0);
+	_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0);
 	__asm__ __volatile__ ("nop");
-	z_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1);
+	_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1);
 }
 
 /**
@@ -64,16 +72,44 @@ static void invalidate_dcache(void)
 {
 	unsigned int val;
 
-	val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+	val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
 	val &= 0xff; /* version field */
 	if (val == 0) {
 		return; /* skip if d-cache is not present */
 	}
-	z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
+	_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
 }
-#endif
 
-extern FUNC_NORETURN void z_cstart(void);
+
+/**
+ *
+ * @brief Adjust the vector table base
+ *
+ * Set the vector table base if the value found in the
+ * _ARC_V2_IRQ_VECT_BASE auxiliary register is different from the
+ * _VectorTable known by software. It is important to do this very early
+ * so that exception vectors can be handled.
+ *
+ * @return N/A
+ */
+
+static void adjust_vector_table_base(void)
+{
+	extern struct vector_table _VectorTable;
+	unsigned int vbr;
+	/* if the compiled-in vector table is different
+	 * from the base address known by the ARC CPU,
+	 * set the vector base to the compiled-in address.
+	 */
+	vbr = _arc_v2_aux_reg_read(_ARC_V2_IRQ_VECT_BASE);
+	vbr &= 0xfffffc00;
+	if (vbr != (unsigned int)&_VectorTable) {
+		_arc_v2_aux_reg_write(_ARC_V2_IRQ_VECT_BASE,
+					(unsigned int)&_VectorTable);
+	}
+}
+
+extern FUNC_NORETURN void _Cstart(void);
 /**
  *
  * @brief Prepare to and run C code
@@ -85,9 +121,11 @@ extern FUNC_NORETURN void z_cstart(void);
 
 void _PrepC(void)
 {
-	z_icache_setup();
-	z_bss_zero();
-	z_data_copy();
-	z_cstart();
+	disable_icache();
+	invalidate_dcache();
+	adjust_vector_table_base();
+	_bss_zero();
+	_data_copy();
+	_Cstart();
 	CODE_UNREACHABLE;
 }

arch/arc/core/regular_irq.S

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -14,179 +24,37 @@
  * See isr_wrapper.S for details.
  */
 
+#define _ASMLANGUAGE
+
 #include <kernel_structs.h>
 #include <offsets_short.h>
 #include <toolchain.h>
-#include <linker/sections.h>
 #include <arch/cpu.h>
-#include <swap_macros.h>
+#include "swap_macros.h"
 
 GTEXT(_rirq_enter)
 GTEXT(_rirq_exit)
-GTEXT(_rirq_newthread_switch)
+GTEXT(_rirq_common_interrupt_swap)
+GTEXT(_is_next_thread_current)
 
+#if 0 /* TODO: when FIRQ is not present, all would be regular */
+#define NUM_REGULAR_IRQ_PRIO_LEVELS CONFIG_NUM_IRQ_PRIO_LEVELS
+#else
+#define NUM_REGULAR_IRQ_PRIO_LEVELS (CONFIG_NUM_IRQ_PRIO_LEVELS-1)
+#endif
+/* note: the above define assumes that prio 0 IRQ is for FIRQ, and
+ * that all others are regular interrupts.
+ * TODO: Revist this if FIRQ becomes configurable.
+ */
+
+#if NUM_REGULAR_IRQ_PRIO_LEVELS > 1
+#error "nested regular interrupts are not supported."
 /*
+ * Nesting of Regularing interrupts is not yet supported.
+ * Set CONFIG_NUM_IRQ_PRIO_LEVELS to 2 even if SOC supports more.
+ */
+#endif
 
-===========================================================
- RETURN FROM INTERRUPT TO COOPERATIVE THREAD
-===========================================================
-
-That's a special case because:
- 1. We return from IRQ handler to a cooperative thread
- 2. During IRQ handling context switch did happen
- 3. Returning to a thread which previously gave control
-    to another thread because of:
-     - Calling k_sleep()
-     - Explicitly yielding
-     - Bumping into locked sync primitive etc
-
-What (3) means is before passing control to another thread our thread
-in question:
- a. Stashed all precious caller-saved registers on its stack
- b. Pushed return address to the top of the stack as well
-
-That's how thread's stack looks like right before jumping to another thread:
------------------------------>8---------------------------------
-PRE-CONTEXT-SWITCH STACK
-
-  lower_addr, let's say: 0x1000
-
-         --------------------------------------
-  SP ->  | Return address; PC (Program Counter), in fact value taken from
-         | BLINK register in arch_switch()
-         --------------------------------------
-         | STATUS32 value, we explicitly save it here for later usage, read-on
-         --------------------------------------
-         | Caller-saved registers: some of R0-R12
-         --------------------------------------
-         |...
-         |...
-
-  higher_addr, let's say: 0x2000
------------------------------>8---------------------------------
-
-When context gets switched the kernel saves callee-saved registers in the
-thread's stack right on top of pre-switch contents so that's what we have:
------------------------------>8---------------------------------
-POST-CONTEXT-SWITCH STACK
-
-  lower_addr, let's say: 0x1000
-
-         --------------------------------------
-SP ->    | Callee-saved registers: see struct _callee_saved_stack{}
-         |  |- R13
-         |  |- R14
-         |  | ...
-         |  \- FP
-         |   ...
-         --------------------------------------
-         | Return address; PC (Program Counter)
-         --------------------------------------
-         | STATUS32 value
-         --------------------------------------
-         | Caller-saved registers: some of R0-R12
-         --------------------------------------
-         |...
-         |...
-
-  higher_addr, let's say: 0x2000
------------------------------>8---------------------------------
-
-So how do we return in such a complex scenario.
-
-First we restore callee-saved regs with help of _load_callee_saved_regs().
-Now we're back to PRE-CONTEXT-SWITCH STACK (see above).
-
-Logically our next step is to load return address from the top of the stack
-and jump to that address to continue execution of the desired thread, but
-we're still in interrupt handling mode and the only way to return to normal
-execution mode is to execute "rtie" instruction. And here we need to deal
-with peculiarities of return from IRQ on ARCv2 cores.
-
-Instead of simple jump to a return address stored in the tip of thread's stack
-(with subsequent interrupt enable) ARCv2 core additionally automatically
-restores some registers from stack. Most important ones are
-PC ("Program Counter") which holds address of the next instruction to execute
-and STATUS32 which holds imortant flags including global interrupt enable,
-zero, carry etc.
-
-To make things worse depending on ARC core configuration and run-time setup
-of certain features different set of registers will be restored.
-
-Typically those same registers are automatically saved on stack on entry to
-an interrupt, but remember we're returning to the thread which was
-not interrupted by interrupt and so on its stack there're no automatically
-saved registers, still inevitably on RTIE execution register restoration
-will happen. So if we do nothing special we'll end-up with that:
------------------------------>8---------------------------------
-  lower_addr, let's say: 0x1000
-
-         --------------------------------------
-    #    | Return address; PC (Program Counter)
-    |    --------------------------------------
-    |    | STATUS32 value
-    |    --------------------------------------
-    |
- sizeof(_irq_stack_frame)
-    |
-    |    | Caller-saved registers: R0-R12
-    V    --------------------------------------
-         |...
-  SP ->  | < Some data on thread's stack>
-         |...
-
-  higher_addr, let's say: 0x2000
------------------------------>8---------------------------------
-
-I.e. we'll go much deeper down the stack over needed return address, read
-some value from unexpected location in stack and will try to jump there.
-Nobody knows were we end-up then.
-
-To work-around that problem we need to mimic existance of IRQ stack frame
-of which we really only need return address obviously to return where we
-need to. For that we just shift SP so that it points sizeof(_irq_stack_frame)
-above like that:
------------------------------>8---------------------------------
-  lower_addr, let's say: 0x1000
-
-  SP ->  |
-    A    | < Some unrelated data >
-    |    |
-    |
- sizeof(_irq_stack_frame)
-    |
-    |    --------------------------------------
-    |    | Return address; PC (Program Counter)
-    |    --------------------------------------
-    #    | STATUS32 value
-         --------------------------------------
-         | Caller-saved registers: R0-R12
-         --------------------------------------
-         |...
-         | < Some data on thread's stack>
-         |...
-
-  higher_addr, let's say: 0x2000
------------------------------>8---------------------------------
-
-Indeed R0-R13 "restored" from IRQ stack frame will contain garbage but
-it makes no difference because we're returning to execution of code as if
-we're returning from yet another function call and so we will restore
-all needed registers from the stack.
-
-One other important remark here is R13.
-
-CPU hardware automatically save/restore registers in pairs and since we
-wanted to save/restore R12 in IRQ stack frame as a caller-saved register we
-just happen to do that for R13 as well. But given compiler treats it as
-a callee-saved register we save/restore it separately in _callee_saved_stack
-structure. And when we restore callee-saved registers from stack we among
-other registers recover R13. But later on return from IRQ with RTIE
-instruction, R13 will be "restored" again from fake IRQ stack frame and
-if we don't copy correct R13 value to fake IRQ stack frame R13 value
-will be corrupted.
-
-*/
 
 /**
  *
@@ -203,26 +71,20 @@ will be corrupted.
 
 SECTION_FUNC(TEXT, _rirq_enter)
 
-/* the ISR will be handled in separate interrupt stack,
- * so stack checking must be diabled, or exception will
- * be caused
- */
-	_disable_stack_checking r2
-	clri
-
-	/* check whether irq stack is used, if
-	 * not switch to isr stack
-	 */
-	_check_and_inc_int_nest_counter r0, r1
-
-	bne.d rirq_nest
-	mov_s r0, sp
-
-	_get_curr_cpu_irq_stack sp
-rirq_nest:
-	push_s r0
-
-	seti
+	mov r1, _kernel
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+#endif
+	ld_s r2, [r1, _kernel_offset_to_current]
+#if NUM_REGULAR_IRQ_PRIO_LEVELS == 1
+	st sp, [r2, _thread_offset_to_sp]
+	ld sp, [r1, _kernel_offset_to_irq_stack]
+#else
+#error regular irq nesting is not implemented
+#endif
 	j _isr_demux
 
 
@@ -234,72 +96,142 @@ rirq_nest:
  */
 
 SECTION_FUNC(TEXT, _rirq_exit)
+
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+
+	/*
+	 * Lock interrupts to ensure kernel queues do not change from this
+	 * point on until return from interrupt.
+	 */
+
 	clri
 
-	pop sp
+#if NUM_REGULAR_IRQ_PRIO_LEVELS > 1
+	/* check if we're a nested interrupt: if so, let the interrupted interrupt
+	 * handle the reschedule */
 
-	_dec_int_nest_counter r0, r1
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	ffs r0, r3
 
-	_check_nest_int_by_irq_act r0, r1
+	asl r0, 1, r0
 
-	jne _rirq_no_switch
-
-	/* sp is struct k_thread **old of z_arc_switch_in_isr
-	 * which is a wrapper of z_get_next_switch_handle.
-	 * r0 contains the 1st thread in ready queue. if
-	 * it equals _current(r2) ,then do swap, or no swap.
+	/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
+	 * AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is greater
+	 * than FFS(AUX_IRQ_ACT), it means that another bit is set so an
+	 * interrupt was interrupted.
 	 */
-	_get_next_switch_handle
 
-	cmp r0, r2
-	beq _rirq_no_switch
-
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	/* here need to remember SEC_STAT.IRM bit */
-	lr r3, [_ARC_V2_SEC_STAT]
-	push_s r3
+	cmp r0, r3
+	brgt _rirq_return_from_rirq
+	ld sp, [r2, _thread_offset_to_sp]
 #endif
 
-	/* r2 is old thread */
-	_irq_store_old_thread_callee_regs
+	/*
+	 * Both (a)reschedule and (b)non-reschedule cases need to load the current
+	 * thread's stack, but don't have to use it until the decision is taken:
+	 * load the delay slots with the 'load stack pointer' instruction.
+	 *
+	 * a) needs to load it to save outgoing context.
+	 * b) needs to load it to restore the interrupted context.
+	 */
+
+	/* coop thread ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_prio]
+	cmp_s r0, 0
+	blt.d _rirq_no_reschedule
+	ld sp, [r2, _thread_offset_to_sp]
+
+	/* scheduler locked ? do not schedule */
+	ld_s r0, [r2, _thread_offset_to_sched_locked]
+	brgt.d r0, 0,  _rirq_no_reschedule
+	ld sp, [r2, _thread_offset_to_sp]
+
+	/* check if the current thread needs to be rescheduled */
+	push_s r2
+	push_s r1
+	push_s blink
+	jl _is_next_thread_current
+	pop_s blink
+	pop_s r1
+	pop_s r2
+	brne.d r0, 0, _rirq_no_reschedule
+	ld sp, [r2, _thread_offset_to_sp]
+
+	/*
+	 * Get the next scheduled thread. On _get_next_ready_thread
+	 * return it is stored in r0.
+	 */
+	push_s r2
+	push_s r1
+	push_s blink
+	jl _get_next_ready_thread
+	pop_s blink
+	pop_s r1
+	pop_s r2
+
+.balign 4
+_rirq_reschedule:
+
+	/* _save_callee_saved_regs expects outgoing thread in r2 */
+	_save_callee_saved_regs
 
 	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
 
-	/* mov new thread (r0) to r2 */
+	/* incoming thread is in r0: it becomes the new 'current' */
 	mov r2, r0
+	st_s r2, [r1, _kernel_offset_to_current]
 
-/* _rirq_newthread_switch required by exception handling */
 .balign 4
-_rirq_newthread_switch:
+_rirq_common_interrupt_swap:
+	/* r2 contains pointer to new thread */
 
-	_load_new_thread_callee_regs
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* Use stack top and down registers from restored context */
+	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
+	sr r3, [_ARC_V2_KSTACK_TOP]
+	ld_s r3, [r2, _thread_offset_to_stack_top]
+	sr r3, [_ARC_V2_KSTACK_BASE]
+#endif
+	/*
+	 * _load_callee_saved_regs expects incoming thread in r2.
+	 * _load_callee_saved_regs restores the stack pointer.
+	 */
+	_load_callee_saved_regs
 
-	breq r3, _CAUSE_RIRQ, _rirq_switch_from_rirq
-	nop_s
-	breq r3, _CAUSE_FIRQ, _rirq_switch_from_firq
-	nop_s
+	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
+
+	breq r3, _CAUSE_RIRQ, _rirq_return_from_rirq
+	nop
+	breq r3, _CAUSE_FIRQ, _rirq_return_from_firq
+	nop
 
 	/* fall through */
 
 .balign 4
-_rirq_switch_from_coop:
+_rirq_return_from_coop:
 
-	/* for a cooperative switch, it's not in irq, so
-	 * need to set some regs for irq return
-	 */
-	_set_misc_regs_irq_switch_from_coop
+	/* status32 and pc (blink) are already on the stack in the right order */
 
-	/*
-	 * See verbose explanation of
-	 * RETURN FROM INTERRUPT TO COOPERATIVE THREAD above
-	 */
+	/* update status32.ie (explanation in firq_exit:_firq_return_from_coop) */
+	ld_s r0, [sp, 4]
+	ld_s r3, [r2, _thread_offset_to_intlock_key]
+	st  0, [r2, _thread_offset_to_intlock_key]
+	cmp r3, 0
+	or.ne r0, r0, _ARC_V2_STATUS32_IE
+	st_s r0, [sp, 4]
 
 	/* carve fake stack */
-	sub sp, sp, ___isf_t_pc_OFFSET
 
+	/*
+	 * a) status32/pc are already on the stack
+	 * b) a real value will be pushed in r0
+	 */
+	sub sp, sp, (___isf_t_SIZEOF - 12)
 
-	/* reset zero-overhead loops */
-	st 0, [sp, ___isf_t_lp_end_OFFSET]
+	/* push return value on stack */
+	ld_s r0, [r2, _thread_offset_to_return_value]
+	push_s r0
 
 	/*
 	 * r13 is part of both the callee and caller-saved register sets because
@@ -309,15 +241,19 @@ _rirq_switch_from_coop:
 	 */
 	st_s r13, [sp, ___isf_t_r13_OFFSET]
 
-	/* stack now has the IRQ stack frame layout, pointing to sp */
-	/* rtie will pop the rest from the stack */
-	rtie
+	/* stack now has the IRQ stack frame layout, pointing to r0 */
+
+	/* fall through to rtie instruction */
 
 .balign 4
-_rirq_switch_from_firq:
-_rirq_switch_from_rirq:
+_rirq_return_from_firq:
+_rirq_return_from_rirq:
 
-	_set_misc_regs_irq_switch_from_irq
+	/* rtie will pop the rest from the stack */
+
+	/* fall through to rtie instruction */
+
+.balign 4
+_rirq_no_reschedule:
 
-_rirq_no_switch:
 	rtie

arch/arc/core/reset.S

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -11,20 +21,34 @@
  * Reset handler that prepares the system for running C code.
  */
 
-#include <toolchain.h>
-#include <linker/sections.h>
-#include <arch/cpu.h>
-#include <swap_macros.h>
+#define _ASMLANGUAGE
 
-GDATA(z_interrupt_stacks)
-GDATA(z_main_stack)
-GDATA(_VectorTable)
+// #include <board.h>
+#include <toolchain.h>
+#include <sections.h>
+#include <arch/cpu.h>
+
+GDATA(_interrupt_stack)
+GDATA(_firq_stack)
+GDATA(_main_stack)
 
 /* use one of the available interrupt stacks during init */
 
+/* FIRQ only ? */
+#if CONFIG_NUM_IRQ_PRIO_LEVELS == 1
 
-#define INIT_STACK z_interrupt_stacks
-#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
+	/* FIRQ, but uses _interrupt_stack ? */
+	#if CONFIG_RGF_NUM_BANKS == 1
+		#define INIT_STACK _interrupt_stack
+		#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
+	#else
+		#define INIT_STACK _firq_stack
+		#define INIT_STACK_SIZE CONFIG_FIRQ_STACK_SIZE
+	#endif
+#else
+	#define INIT_STACK _interrupt_stack
+	#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
+#endif
 
 GTEXT(__reset)
 GTEXT(__start)
@@ -45,114 +69,9 @@ GTEXT(__start)
 
 SECTION_FUNC(TEXT,__reset)
 SECTION_FUNC(TEXT,__start)
-	/* lock interrupts: will get unlocked when switch to main task
-	 * also make sure the processor in the correct status
-	 */
-	mov_s r0, 0
-	kflag r0
 
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	sflag r0
-#endif
-
-#if defined(CONFIG_BOOT_TIME_MEASUREMENT) && defined(CONFIG_ARCV2_TIMER)
-	/*
-	 * ARCV2 timer (timer0) is a free run timer, let it start to count
-	 * here.
-	 */
-	mov_s r0, 0xffffffff
-	sr r0, [_ARC_V2_TMR0_LIMIT]
-	mov_s r0, 0
-	sr r0, [_ARC_V2_TMR0_COUNT]
-#endif
-	/* interrupt related init */
-#ifndef CONFIG_ARC_NORMAL_FIRMWARE
-	/* IRQ_ACT and IRQ_CTRL should be initialized and set in secure mode */
-	sr r0, [_ARC_V2_AUX_IRQ_ACT]
-	sr r0, [_ARC_V2_AUX_IRQ_CTRL]
-#endif
-	sr r0, [_ARC_V2_AUX_IRQ_HINT]
-
-	/* set the vector table base early,
-	 * so that exception vectors can be handled.
-	 */
-	mov_s r0, _VectorTable
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	sr r0, [_ARC_V2_IRQ_VECT_BASE_S]
-#else
-	sr r0, [_ARC_V2_IRQ_VECT_BASE]
-#endif
-
-#if defined(CONFIG_USERSPACE)
-	lr r0, [_ARC_V2_STATUS32]
-	bset r0, r0, _ARC_V2_STATUS32_US_BIT
-	kflag r0
-#endif
-
-#ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
-	lr r0, [_ARC_V2_STATUS32]
-	bset r0, r0, _ARC_V2_STATUS32_AD_BIT
-	kflag r0
-#endif
-
-	mov_s r1, 1
-
-invalidate_and_disable_icache:
-
-	lr r0, [_ARC_V2_I_CACHE_BUILD]
-	and.f r0, r0, 0xff
-	bz.nd invalidate_dcache
-
-	mov_s r2, 0
-	sr r2, [_ARC_V2_IC_IVIC]
-	/* writing to IC_IVIC needs 3 NOPs */
-	nop_s
-	nop_s
-	nop_s
-	sr r1, [_ARC_V2_IC_CTRL]
-
-invalidate_dcache:
-
-	lr r3, [_ARC_V2_D_CACHE_BUILD]
-	and.f r3, r3, 0xff
-	bz.nd done_cache_invalidate
-
-	sr r1, [_ARC_V2_DC_IVDC]
-
-done_cache_invalidate:
-
-#if defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES) && \
-	!defined(CONFIG_BOOTLOADER_CONTEXT_RESTORE)
-        jl @_sys_resume_from_deep_sleep
-#endif
-
-#if defined(CONFIG_SMP) || CONFIG_MP_NUM_CPUS  > 1
-	_get_cpu_id r0
-	breq r0, 0, _master_core_startup
-
-/*
- * Non-masters wait for master core (core 0) to boot enough
- */
-_slave_core_wait:
-#if CONFIG_MP_NUM_CPUS == 1
-	kflag	1
-#endif
-	ld r1, [arc_cpu_wake_flag]
-	brne r0, r1, _slave_core_wait
-
-	ld sp, [arc_cpu_sp]
-	/* signal master core that slave core runs */
-	st 0, [arc_cpu_wake_flag]
-
-#if defined(CONFIG_ARC_FIRQ_STACK)
-	push r0
-	jl z_arc_firq_stack_set
-	pop r0
-#endif
-	j z_arc_slave_start
-
-_master_core_startup:
-#endif
+	/* lock interrupts: will get unlocked when switch to main task */
+	clri
 
 #ifdef CONFIG_INIT_STACKS
 	/*
@@ -160,21 +79,24 @@ _master_core_startup:
 	 * FIRQ stack when CONFIG_INIT_STACKS is enabled before switching to
 	 * one of them for the rest of the early boot
 	 */
-	mov_s sp, z_main_stack
+	mov sp, _main_stack
 	add sp, sp, CONFIG_MAIN_STACK_SIZE
 
-	mov_s r0, z_interrupt_stacks
+	mov_s r0, _interrupt_stack
 	mov_s r1, 0xaa
 	mov_s r2, CONFIG_ISR_STACK_SIZE
 	jl memset
 
-#endif /* CONFIG_INIT_STACKS */
-
-	mov_s sp, INIT_STACK
-	add sp, sp, INIT_STACK_SIZE
-
-#if defined(CONFIG_ARC_FIRQ_STACK)
-	jl z_arc_firq_stack_set
+#if CONFIG_RGF_NUM_BANKS != 1
+	mov_s r0, _firq_stack
+	mov_s r1, 0xaa
+	mov_s r2, CONFIG_FIRQ_STACK_SIZE
+	jl memset
 #endif
 
+#endif /* CONFIG_INIT_STACKS */
+
+	mov sp, INIT_STACK
+	add sp, sp, INIT_STACK_SIZE
+
 	j @_PrepC

arch/arc/core/secureshield/CMakeLists.txt

@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library()
-
-zephyr_library_sources(
-  arc_sjli.c
-  arc_secure.S
-  secure_sys_services.c
-  )

arch/arc/core/secureshield/arc_secure.S

@@ -1,122 +0,0 @@
-/*
- * Copyright (c) 2018 Synopsys.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <toolchain.h>
-#include <linker/sections.h>
-#include <arch/cpu.h>
-
-.macro clear_scratch_regs
-	mov r1, 0
-	mov r2, 0
-	mov r3, 0
-	mov r4, 0
-	mov r5, 0
-	mov r6, 0
-	mov r7, 0
-	mov r8, 0
-	mov r9, 0
-	mov r10, 0
-	mov r11, 0
-	mov r12, 0
-.endm
-
-.macro clear_callee_regs
-	mov r25, 0
-	mov r24, 0
-	mov r23, 0
-	mov r22, 0
-	mov r21, 0
-	mov r20, 0
-	mov r19, 0
-	mov r18, 0
-	mov r17, 0
-	mov r16, 0
-
-	mov r15, 0
-	mov r14, 0
-	mov r13, 0
-.endm
-
-GTEXT(arc_go_to_normal)
-GTEXT(_arc_do_secure_call)
-GDATA(arc_s_call_table)
-
-
-SECTION_FUNC(TEXT, _arc_do_secure_call)
-	/* r0-r5: arg1-arg6, r6 is call id */
-	/* the call id should be checked */
-	/* disable normal interrupt happened when processor in secure mode ? */
-	/* seti (0x30 | (ARC_N_IRQ_START_LEVEL-1)) */
-	breq r6, ARC_S_CALL_CLRI, _s_clri
-	breq r6, ARC_S_CALL_SETI, _s_seti
-	push_s blink
-	mov	blink, arc_s_call_table
-	ld.as r6, [blink, r6]
-
-	jl	[r6]
-
-	/*
-	 * no need to clear callee regs, as they will be saved and restored
-	 * automatically
-	 */
-	clear_scratch_regs
-
-	mov r29, 0
-	mov r30, 0
-
-
-_arc_do_secure_call_exit:
-	pop_s blink
-
-	j [blink]
-	/* enable normal interrupt */
-	/*
-	 * j.d [blink]
-	 * seti (0x30 | (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
-	 */
-
-_s_clri:
-	lr r0, [_ARC_V2_STATUS32]
-	and r0, r0, 0x1e
-	asr r0, r0
-	or r0, r0, 0x30
-	mov r6, (0x30 | (ARC_N_IRQ_START_LEVEL-1))
-
-	j.d [blink]
-	seti r6
-
-_s_seti:
-	btst r0, 4
-	jnz __seti_0
-	mov r0, (CONFIG_NUM_IRQ_PRIO_LEVELS - 1)
-	lr r6, [_ARC_V2_STATUS32]
-	and r6, r6, 0x1e
-	asr r6, r6
-	cmp r0, r6
-	mov.hs r0, r6
-__seti_0:
-	and r0, r0, 0xf
-	brhs r0, ARC_N_IRQ_START_LEVEL, __seti_1
-	mov r0, ARC_N_IRQ_START_LEVEL
-__seti_1:
-	or r0, r0, 0x30
-
-	j.d [blink]
-	seti r0
-
-
-SECTION_FUNC(TEXT, arc_go_to_normal)
-	clear_callee_regs
-	clear_scratch_regs
-
-	mov fp, 0
-	mov r29, 0
-	mov r30, 0
-	mov blink, 0
-
-	jl [r0]
-	/* should not come here */
-	kflag 1
-

arch/arc/core/secureshield/arc_sjli.c

@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <device.h>
-#include <kernel.h>
-#include <errno.h>
-#include <zephyr/types.h>
-#include <init.h>
-#include <toolchain.h>
-
-#include <arch/arc/v2/secureshield/arc_secure.h>
-
-static void _default_sjli_entry(void);
-/*
- * sjli vector table must be in instruction space
- * \todo: how to let user to install customized sjli entry easily, e.g.
- *  through macros or with the help of compiler?
- */
-const static u32_t _sjli_vector_table[CONFIG_SJLI_TABLE_SIZE] = {
-	[0] = (u32_t)_arc_do_secure_call,
-	[1 ... (CONFIG_SJLI_TABLE_SIZE - 1)] = (u32_t)_default_sjli_entry,
-};
-
-/*
- * @brief default entry of sjli call
- *
- */
-static void _default_sjli_entry(void)
-{
-	printk("default sjli entry\n");
-}
-
-/*
- * @brief initializaiton of sjli related functions
- *
- */
-static void sjli_table_init(void)
-{
-	/* install SJLI table */
-	z_arc_v2_aux_reg_write(_ARC_V2_NSC_TABLE_BASE, _sjli_vector_table);
-	z_arc_v2_aux_reg_write(_ARC_V2_NSC_TABLE_TOP,
-		(_sjli_vector_table + CONFIG_SJLI_TABLE_SIZE));
-}
-
-/*
- * @brief initializaiton of secureshield related functions.
- */
-static int arc_secureshield_init(struct device *arg)
-{
-	sjli_table_init();
-
-	/* set nic bit to enable seti/clri and
-	 * sleep/wevt in normal mode.
-	 * If not set, direct call of seti/clri etc. will raise exception.
-	 * Then, these seti/clri instructions should be replaced with secure
-	 * secure services (sjli call)
-	 *
-	 */
-	__asm__ volatile("sflag  0x20");
-
-	return 0;
-}
-
-SYS_INIT(arc_secureshield_init, PRE_KERNEL_1,
-		CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/core/secureshield/secure_sys_services.c

@@ -1,89 +0,0 @@
-/*
- * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <errno.h>
-#include <kernel.h>
-#include <arch/cpu.h>
-#include <zephyr/types.h>
-#include <soc.h>
-#include <toolchain.h>
-
-#include <arch/arc/v2/secureshield/arc_secure.h>
-
-#define IRQ_PRIO_MASK (0xffff << ARC_N_IRQ_START_LEVEL)
-/*
- * @brief read secure auxiliary regs on behalf of normal mode
- *
- * @param aux_reg  address of aux reg
- *
- * Some aux regs require secure privilege, this function implements
- * an secure service to access secure aux regs. Check should be done
- * to decide whether the access is valid.
- */
-static s32_t arc_s_aux_read(u32_t aux_reg)
-{
-	return -1;
-}
-
-/*
- * @brief write secure auxiliary regs on behalf of normal mode
- *
- * @param aux_reg address of aux reg
- * @param val, the val to write
- *
- *  Some aux regs require secure privilege, this function implements
- * an secure service to access secure aux regs. Check should be done
- * to decide whether the access is valid.
- */
-static s32_t arc_s_aux_write(u32_t aux_reg, u32_t val)
-{
-	if (aux_reg == _ARC_V2_AUX_IRQ_ACT) {
-		/* 0 -> CONFIG_NUM_IRQ_PRIO_LEVELS allocated to secure world
-		 * left prio levels allocated to normal world
-		 */
-		val &= IRQ_PRIO_MASK;
-		z_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_ACT, val |
-		(z_arc_v2_aux_reg_read(_ARC_V2_AUX_IRQ_ACT) &
-			(~IRQ_PRIO_MASK)));
-
-		return  0;
-	}
-
-	return -1;
-}
-
-/*
- * @brief allocate interrupt for normal world
- *
- * @param intno, the interrupt to be allocated to normal world
- *
- * By default, most interrupts are configured to be secure in initialization.
- * If normal world wants to use an interrupt, through this secure service to
- * apply one. Necessary check should be done to decide whether the apply is
- * valid
- */
-static s32_t arc_s_irq_alloc(u32_t intno)
-{
-	z_arc_v2_irq_uinit_secure_set(intno, 0);
-	return 0;
-}
-
-
-/*
- * \todo, to access MPU from normal mode, secure mpu service should be
- * created. In the secure mpu service, the parameters should be checked
- * (e.g., not overwrite the mpu regions for secure world)that operations
- * are valid
- */
-
-
-/*
- * \todo, how to add secure service easily
- */
-const _arc_s_call_handler_t arc_s_call_table[ARC_S_CALL_LIMIT] = {
-	[ARC_S_CALL_AUX_READ] = (_arc_s_call_handler_t)arc_s_aux_read,
-	[ARC_S_CALL_AUX_WRITE] = (_arc_s_call_handler_t)arc_s_aux_write,
-	[ARC_S_CALL_IRQ_ALLOC] = (_arc_s_call_handler_t)arc_s_irq_alloc,
-};

arch/arc/core/sw_isr_table.S

@@ -0,0 +1,64 @@
+/* sw_isr_table.S - ISR table for static ISR declarations for ARC */
+
+/*
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define _ASMLANGUAGE
+
+#include <toolchain.h>
+#include <sections.h>
+#include <arch/cpu.h>
+
+/*
+ * enable preprocessor features, such
+ * as %expr - evaluate the expression and use it as a string
+ */
+.altmacro
+
+/*
+ * Define an ISR table entry
+ * Define symbol as weak and give the section .gnu.linkonce
+ * prefix. This allows linker overload the symbol and the
+ * whole section by the one defined by a device driver
+ */
+.macro _isr_table_entry_declare index
+	WDATA(_isr_irq\index)
+	.section .gnu.linkonce.isr_irq\index
+	_isr_irq\index: .word 0xABAD1DEA, _irq_spurious
+.endm
+
+/*
+ * Declare the ISR table
+ */
+.macro _isr_table_declare from, to
+	counter = \from
+	.rept (\to - \from)
+		_isr_table_entry_declare %counter
+		counter = counter + 1
+	.endr
+.endm
+
+GTEXT(_irq_spurious)
+GDATA(_sw_isr_table)
+
+.section .isr_irq16
+.align
+_sw_isr_table:
+
+/*In ARC architecture, IRQ 0-15 are reserved for the system and are not
+assignable by the user, for that reason the isr table linker section
+start at IRQ 16*/
+_isr_table_declare 16 CONFIG_NUM_IRQS

arch/arc/core/swap.S

@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2014-2015 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Thread context switching
+ *
+ * This module implements the routines necessary for thread context switching
+ * on ARCv2 CPUs.
+ *
+ * See isr_wrapper.S for details.
+ */
+
+#define _ASMLANGUAGE
+
+#include <kernel_structs.h>
+#include <offsets_short.h>
+#include <toolchain.h>
+#include <arch/cpu.h>
+#include <v2/irq.h>
+#include "swap_macros.h"
+
+GTEXT(_Swap)
+GTEXT(_get_next_ready_thread)
+GDATA(_k_neg_eagain)
+GDATA(_kernel)
+
+/**
+ *
+ * @brief Initiate a cooperative context switch
+ *
+ * The _Swap() routine is invoked by various nanokernel services to effect
+ * a cooperative context switch.  Prior to invoking _Swap(), the caller
+ * disables interrupts via nanoCpuIntLock() and the return 'key' is passed as a
+ * parameter to _Swap(). The key is in fact the value stored in the register
+ * operand of a CLRI instruction.
+ *
+ * It stores the intlock key parameter into current->intlock_key.
+
+ * Given that _Swap() is called to effect a cooperative context switch,
+ * the caller-saved integer registers are saved on the stack by the function
+ * call preamble to _Swap(). This creates a custom stack frame that will be
+ * popped when returning from _Swap(), but is not suitable for handling a return
+ * from an exception. Thus, the fact that the thread is pending because of a
+ * cooperative call to _Swap() has to be recorded via the _CAUSE_COOP code in
+ * the relinquish_cause of the thread's k_thread structure. The
+ * _IrqExit()/_FirqExit() code will take care of doing the right thing to
+ * restore the thread status.
+ *
+ * When _Swap() is invoked, we know the decision to perform a context switch or
+ * not has already been taken and a context switch must happen.
+ *
+ * @return may contain a return value setup by a call to fiberRtnValueSet()
+ *
+ * C function prototype:
+ *
+ * unsigned int _Swap (unsigned int key);
+ *
+ */
+
+SECTION_FUNC(TEXT, _Swap)
+
+	/* interrupts are locked, interrupt key is in r0 */
+
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+
+	/* save intlock key */
+	st_s r0, [r2, _thread_offset_to_intlock_key]
+	st _CAUSE_COOP, [r2, _thread_offset_to_relinquish_cause]
+
+	/*
+         * Carve space for the return value. Setting it to a defafult of
+         * -EAGAIN eliminates the need for the timeout code to set it.
+         * If another value is ever needed, it can be modified with
+         * fiberRtnValueSet().
+         */
+	ld r3, [_k_neg_eagain]
+	st_s r3, [r2, _thread_offset_to_return_value]
+
+	/*
+	 * Save status32 and blink on the stack before the callee-saved registers.
+	 * This is the same layout as the start of an IRQ stack frame.
+	 */
+	lr r3, [_ARC_V2_STATUS32]
+	push_s r3
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* disable stack checking during swap */
+	bclr r3, r3, _ARC_V2_STATUS32_SC_BIT
+	kflag r3
+#endif
+	push_s blink
+
+	_save_callee_saved_regs
+
+	/* find out incoming thread (fiber or task) */
+
+	/*
+	 * Save needed registers to callee saved ones. It is faster than
+	 * pushing them to stack. It is possible to do since program has
+	 * just saved them and the calling routine will save them in turn
+	 * if it uses them.
+	 */
+	mov_s r13, blink
+	mov_s r14, r0
+	mov_s r15, r1
+	jl _get_next_ready_thread
+	mov_s r2, r0
+	mov_s r1, r15
+	mov_s r0, r14
+	mov_s blink, r13
+
+	/* entering here, r2 contains the new current thread */
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* Use stack top and down registers from restored context */
+	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
+	sr r3, [_ARC_V2_KSTACK_TOP]
+	ld_s r3, [r2, _thread_offset_to_stack_top]
+	sr r3, [_ARC_V2_KSTACK_BASE]
+#endif
+	/* XXX - can be moved to delay slot of _CAUSE_RIRQ ? */
+	st_s r2, [r1, _kernel_offset_to_current]
+
+	_load_callee_saved_regs
+
+	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
+
+	breq r3, _CAUSE_RIRQ, _swap_return_from_rirq
+	nop
+	breq r3, _CAUSE_FIRQ, _swap_return_from_firq
+	nop
+
+	/* fall through to _swap_return_from_coop */
+
+.balign 4
+_swap_return_from_coop:
+
+	ld_s r1, [r2, _thread_offset_to_intlock_key]
+	st  0, [r2, _thread_offset_to_intlock_key]
+	ld_s r0, [r2, _thread_offset_to_return_value]
+
+	lr ilink, [_ARC_V2_STATUS32]
+	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
+
+	pop_s blink /* pc into blink */
+	pop_s r3    /* status32 into r3 */
+	kflag r3    /* write status32 */
+
+	j_s.d [blink] /* always execute delay slot */
+	seti r1       /* delay slot */
+
+
+.balign 4
+_swap_return_from_rirq:
+_swap_return_from_firq:
+
+	lr r3, [_ARC_V2_STATUS32]
+	bbit1 r3, _ARC_V2_STATUS32_AE_BIT, _return_from_exc_irq
+
+	/* pretend interrupt happened to use rtie instruction */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	brne r3,0,_swap_already_in_irq
+
+	or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1)) /* use lowest */
+	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+
+_swap_already_in_irq:
+	rtie
+
+.balign 4
+_return_from_exc_irq:
+	_pop_irq_stack_frame
+	sub_s sp, sp, 8
+
+_return_from_exc:
+
+	/* put the return address to eret */
+	ld ilink, [sp] /* pc into ilink */
+	sr ilink, [_ARC_V2_ERET]
+
+	/* put status32 into estatus */
+	ld ilink, [sp, 4] /* status32 into ilink */
+	sr ilink, [_ARC_V2_ERSTATUS]
+	add_s sp, sp, 8
+	rtie

arch/arc/core/swap_macros.h

@@ -0,0 +1,171 @@
+/* swap_macros.h - helper macros for context switch */
+
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _SWAP_MACROS__H_
+#define _SWAP_MACROS__H_
+
+#include <kernel_structs.h>
+#include <offsets_short.h>
+#include <toolchain.h>
+#include <arch/cpu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef _ASMLANGUAGE
+
+/* entering this macro, current is in r2 */
+.macro _save_callee_saved_regs
+
+	sub_s sp, sp, ___callee_saved_stack_t_SIZEOF
+
+	/* save regs on stack */
+	st_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
+	st_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
+	st_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
+	st r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
+	st r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
+	st r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
+	st r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
+	st r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
+	st r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
+	st r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
+	st r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
+	st r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
+	st r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
+	st r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
+	st fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
+	st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
+
+	/* save stack pointer in struct tcs */
+	st sp, [r2, _thread_offset_to_sp]
+.endm
+
+/* entering this macro, current is in r2 */
+.macro _load_callee_saved_regs
+	/* restore stack pointer from struct tcs */
+	ld sp, [r2, _thread_offset_to_sp]
+
+	ld_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
+	ld_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
+	ld_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
+	ld r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
+	ld r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
+	ld r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
+	ld r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
+	ld r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
+	ld r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
+	ld r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
+	ld r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
+	ld r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
+	ld r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
+	ld r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
+	ld fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
+	ld r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
+
+	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
+
+.endm
+
+/*
+ * Must be called with interrupts locked or in P0.
+ * Upon exit, sp will be pointing to the stack frame.
+ */
+.macro _create_irq_stack_frame
+
+	sub_s sp, sp, ___isf_t_SIZEOF
+
+	st blink, [sp, ___isf_t_blink_OFFSET]
+
+	/* store these right away so we can use them if needed */
+
+	st_s r13, [sp, ___isf_t_r13_OFFSET]
+	st_s r12, [sp, ___isf_t_r12_OFFSET]
+	st   r11, [sp, ___isf_t_r11_OFFSET]
+	st   r10, [sp, ___isf_t_r10_OFFSET]
+	st   r9,  [sp, ___isf_t_r9_OFFSET]
+	st   r8,  [sp, ___isf_t_r8_OFFSET]
+	st   r7,  [sp, ___isf_t_r7_OFFSET]
+	st   r6,  [sp, ___isf_t_r6_OFFSET]
+	st   r5,  [sp, ___isf_t_r5_OFFSET]
+	st   r4,  [sp, ___isf_t_r4_OFFSET]
+	st_s r3,  [sp, ___isf_t_r3_OFFSET]
+	st_s r2,  [sp, ___isf_t_r2_OFFSET]
+	st_s r1,  [sp, ___isf_t_r1_OFFSET]
+	st_s r0,  [sp, ___isf_t_r0_OFFSET]
+
+	mov r0, lp_count
+	st_s r0, [sp, ___isf_t_lp_count_OFFSET]
+	lr r1, [_ARC_V2_LP_START]
+	lr r0, [_ARC_V2_LP_END]
+	st_s r1, [sp, ___isf_t_lp_start_OFFSET]
+	st_s r0, [sp, ___isf_t_lp_end_OFFSET]
+
+.endm
+
+/*
+ * Must be called with interrupts locked or in P0.
+ * sp must be pointing the to stack frame.
+ */
+.macro _pop_irq_stack_frame
+
+	ld blink, [sp, ___isf_t_blink_OFFSET]
+
+	ld_s r0, [sp, ___isf_t_lp_count_OFFSET]
+	mov lp_count, r0
+	ld_s r1, [sp, ___isf_t_lp_start_OFFSET]
+	ld_s r0, [sp, ___isf_t_lp_end_OFFSET]
+	sr r1, [_ARC_V2_LP_START]
+	sr r0, [_ARC_V2_LP_END]
+
+	ld_s r13, [sp, ___isf_t_r13_OFFSET]
+	ld_s r12, [sp, ___isf_t_r12_OFFSET]
+	ld   r11, [sp, ___isf_t_r11_OFFSET]
+	ld   r10, [sp, ___isf_t_r10_OFFSET]
+	ld   r9,  [sp, ___isf_t_r9_OFFSET]
+	ld   r8,  [sp, ___isf_t_r8_OFFSET]
+	ld   r7,  [sp, ___isf_t_r7_OFFSET]
+	ld   r6,  [sp, ___isf_t_r6_OFFSET]
+	ld   r5,  [sp, ___isf_t_r5_OFFSET]
+	ld   r4,  [sp, ___isf_t_r4_OFFSET]
+	ld_s r3,  [sp, ___isf_t_r3_OFFSET]
+	ld_s r2,  [sp, ___isf_t_r2_OFFSET]
+	ld_s r1,  [sp, ___isf_t_r1_OFFSET]
+	ld_s r0,  [sp, ___isf_t_r0_OFFSET]
+
+	/*
+	 * All gprs have been reloaded, the only one that is still usable is
+	 * ilink.
+	 *
+	 * The pc and status32 values will still be on the stack. We cannot
+	 * pop them yet because the callers of _pop_irq_stack_frame must reload
+	 * status32 differently depending on the execution context they are running
+	 * in (_Swap(), firq or exception).
+	 */
+	add_s sp, sp, ___isf_t_SIZEOF
+
+.endm
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*  _SWAP_MACROS__H_ */

arch/arc/core/switch.S

@@ -1,164 +0,0 @@
-/*
- * Copyright (c) 2019 Synopsys.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Thread context switching
- *
- * This module implements the routines necessary for thread context switching
- * on ARCv2 CPUs.
- *
- * See isr_wrapper.S for details.
- */
-
-#include <kernel_structs.h>
-#include <offsets_short.h>
-#include <toolchain.h>
-#include <linker/sections.h>
-#include <arch/cpu.h>
-#include <v2/irq.h>
-#include <swap_macros.h>
-
-GTEXT(arch_switch)
-
-/**
- *
- * @brief Initiate a cooperative context switch
- *
- * The arch_switch routine is invoked by various kernel services to effect
- * a cooperative context switch. Prior to invoking arch_switch, the caller
- * disables interrupts via irq_lock()
-
- * Given that arch_switch() is called to effect a cooperative context switch,
- * the caller-saved integer registers are saved on the stack by the function
- * call preamble to arch_switch. This creates a custom stack frame that will
- * be popped when returning from arch_switch, but is not suitable for handling
- * a return from an exception. Thus, the fact that the thread is pending because
- * of a cooperative call to arch_switch() has to be recorded via the
- * _CAUSE_COOP code in the relinquish_cause of the thread's k_thread structure.
- * The _rirq_exit()/_firq_exit() code will take care of doing the right thing
- * to restore the thread status.
- *
- * When arch_switch() is invoked, we know the decision to perform a context
- * switch or not has already been taken and a context switch must happen.
- *
- *
- * C function prototype:
- *
- * void arch_switch(void *switch_to, void **switched_from);
- *
- */
-
-SECTION_FUNC(TEXT, arch_switch)
-
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	push_s r0
-	push_s r1
-	push_s blink
-
-	bl read_timer_start_of_swap
-
-	pop_s blink
-	pop_s r1
-	pop_s r0
-#endif
-	/*
-	 * r0 = new_thread->switch_handle = switch_to thread,
-	 * r1 = &old_thread->switch_handle
-	 * get old_thread from r1
-	 */
-
-	sub r2, r1, ___thread_t_switch_handle_OFFSET
-
-
-	st _CAUSE_COOP, [r2, _thread_offset_to_relinquish_cause]
-
-	/*
-	 * Save status32 and blink on the stack before the callee-saved registers.
-	 * This is the same layout as the start of an IRQ stack frame.
-	 */
-	lr r3, [_ARC_V2_STATUS32]
-	push_s r3
-
-#ifdef CONFIG_ARC_HAS_SECURE
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	lr r3, [_ARC_V2_SEC_STAT]
-#else
-	mov_s r3, 0
-#endif
-	push_s r3
-#endif
-
-	push_s blink
-
-	_store_old_thread_callee_regs
-
-/* disable stack checking here, as sp will be changed to target
- * thread'sp
- */
-	_disable_stack_checking r3
-
-	mov_s r2, r0
-
-	_load_new_thread_callee_regs
-
-	breq r3, _CAUSE_RIRQ, _switch_return_from_rirq
-	nop_s
-	breq r3, _CAUSE_FIRQ, _switch_return_from_firq
-	nop_s
-
-	/* fall through to _switch_return_from_coop */
-
-.balign 4
-_switch_return_from_coop:
-
-	pop_s blink /* pc into blink */
-#ifdef CONFIG_ARC_HAS_SECURE
-	pop_s r3    /* pop SEC_STAT */
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	sflag r3
-#endif
-#endif
-	pop_s r3    /* status32 into r3 */
-	kflag r3    /* write status32 */
-
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	push_s blink
-
-	bl read_timer_end_of_swap
-
-	pop_s blink
-#endif /* CONFIG_EXECUTION_BENCHMARKING */
-	j_s [blink]
-
-
-.balign 4
-_switch_return_from_rirq:
-_switch_return_from_firq:
-
-	_set_misc_regs_irq_switch_from_irq
-
-	/* use lowest interrupt priority to simulate
-	 * a interrupt return to load left regs of new
-	 * thread
-	 */
-
-	lr r3, [_ARC_V2_AUX_IRQ_ACT]
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	or r3, r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
-#else
-	or r3, r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
-#endif
-
-#ifdef CONFIG_ARC_NORMAL_FIRMWARE
-	mov_s r0, _ARC_V2_AUX_IRQ_ACT
-	mov_s r1, r3
-	mov_s r6, ARC_S_CALL_AUX_WRITE
-	sjli SJLI_CALL_ARC_SECURE
-#else
-	sr r3, [_ARC_V2_AUX_IRQ_ACT]
-#endif
-	rtie

arch/arc/core/sys_fatal_error_handler.c

@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief ARCv2 system fatal error handler
+ *
+ * This module provides the _SysFatalErrorHandler() routine for ARCv2 BSPs.
+ */
+
+#include <nanokernel.h>
+#include <toolchain.h>
+#include <sections.h>
+#include <kernel_structs.h>
+#include <misc/printk.h>
+
+/**
+ *
+ * @brief Fatal error handler
+ *
+ * This routine implements the corrective action to be taken when the system
+ * detects a fatal error.
+ *
+ * This sample implementation attempts to abort the current thread and allow
+ * the system to continue executing, which may permit the system to continue
+ * functioning with degraded capabilities.
+ *
+ * System designers may wish to enhance or substitute this sample
+ * implementation to take other actions, such as logging error (or debug)
+ * information to a persistent repository and/or rebooting the system.
+ *
+ * @param reason the fatal error reason
+ * @param pEsf pointer to exception stack frame
+ *
+ * @return N/A
+ */
+FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
+					 const NANO_ESF *pEsf)
+{
+	ARG_UNUSED(reason);
+	ARG_UNUSED(pEsf);
+
+	if (k_is_in_isr() || _is_thread_essential()) {
+		printk("Fatal fault in %s! Spinning...\n",
+		       k_is_in_isr() ? "ISR" : "essential thread");
+		for (;;)
+			; /* spin forever */
+	}
+	printk("Fatal fault in thread! Aborting.\n");
+	k_thread_abort(_current);
+
+	CODE_UNREACHABLE;
+}

arch/arc/core/thread.c

@@ -1,38 +1,64 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
  * @file
  * @brief New thread creation for ARCv2
  *
- * Core thread related primitives for the ARCv2 processor architecture.
+ * Core nanokernel fiber related primitives for the ARCv2 processor
+ * architecture.
  */
 
-#include <kernel.h>
-#include <ksched.h>
+#include <nanokernel.h>
+#include <toolchain.h>
+#include <kernel_structs.h>
 #include <offsets_short.h>
 #include <wait_q.h>
-
-#ifdef CONFIG_USERSPACE
-#include <arch/arc/v2/mpu/arc_core_mpu.h>
-#endif
-
+#ifdef CONFIG_INIT_STACKS
+#include <string.h>
+#endif /* CONFIG_INIT_STACKS */
 /*  initial stack frame */
 struct init_stack_frame {
-	u32_t pc;
-#ifdef CONFIG_ARC_HAS_SECURE
-	u32_t sec_stat;
-#endif
-	u32_t status32;
-	u32_t r3;
-	u32_t r2;
-	u32_t r1;
-	u32_t r0;
+	uint32_t pc;
+	uint32_t status32;
+	uint32_t r3;
+	uint32_t r2;
+	uint32_t r1;
+	uint32_t r0;
 };
 
+#if defined(CONFIG_THREAD_MONITOR)
+/*
+ * Add a thread to the kernel's list of active threads.
+ */
+static ALWAYS_INLINE void thread_monitor_init(struct k_thread *thread)
+{
+	unsigned int key;
+
+	key = irq_lock();
+	thread->next_thread = _kernel.threads;
+	_kernel.threads = thread;
+	irq_unlock(key);
+}
+#else
+#define thread_monitor_init(thread) \
+	do {/* do nothing */     \
+	} while ((0))
+#endif /* CONFIG_THREAD_MONITOR */
+
 /*
  * @brief Initialize a new thread from its stack space
  *
@@ -42,7 +68,7 @@ struct init_stack_frame {
  * needed anymore.
  *
  * The initial context is a basic stack frame that contains arguments for
- * z_thread_entry() return address, that points at z_thread_entry()
+ * _thread_entry() return address, that points at _thread_entry()
  * and status register.
  *
  * <options> is currently unused.
@@ -58,241 +84,78 @@ struct init_stack_frame {
  *
  * @return N/A
  */
-void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
-		     size_t stackSize, k_thread_entry_t pEntry,
-		     void *parameter1, void *parameter2, void *parameter3,
-		     int priority, unsigned int options)
+void _new_thread(char *pStackMem, size_t stackSize,
+		 _thread_entry_t pEntry,
+		 void *parameter1, void *parameter2, void *parameter3,
+		 int priority, unsigned options)
 {
-	char *pStackMem = Z_THREAD_STACK_BUFFER(stack);
+	_ASSERT_VALID_PRIO(priority, pEntry);
 
-	char *stackEnd;
-	char *priv_stack_end;
+	char *stackEnd = pStackMem + stackSize;
 	struct init_stack_frame *pInitCtx;
 
-#ifdef CONFIG_USERSPACE
+	struct k_thread *thread = (struct k_thread *) pStackMem;
 
-	size_t stackAdjSize;
-	size_t offset = 0;
-
-
-	stackAdjSize = Z_ARC_MPU_SIZE_ALIGN(stackSize);
-
-	stackEnd = pStackMem + stackAdjSize;
-
-#ifdef CONFIG_STACK_POINTER_RANDOM
-	offset = stackAdjSize - stackSize;
+#ifdef CONFIG_INIT_STACKS
+	memset(pStackMem, 0xaa, stackSize);
 #endif
 
-	if (options & K_USER) {
-#ifdef CONFIG_GEN_PRIV_STACKS
-		thread->arch.priv_stack_start =
-			(u32_t)z_priv_stack_find(thread->stack_obj);
+	/* carve the thread entry struct from the "base" of the stack */
+
+	pInitCtx = (struct init_stack_frame *)(STACK_ROUND_DOWN(stackEnd) -
+				       sizeof(struct init_stack_frame));
+
+	pInitCtx->pc = ((uint32_t)_thread_entry_wrapper);
+	pInitCtx->r0 = (uint32_t)pEntry;
+	pInitCtx->r1 = (uint32_t)parameter1;
+	pInitCtx->r2 = (uint32_t)parameter2;
+	pInitCtx->r3 = (uint32_t)parameter3;
+	/*
+	 * For now set the interrupt priority to 15
+	 * we can leave interrupt enable flag set to 0 as
+	 * seti instruction in the end of the _Swap() will
+	 * enable the interrupts based on intlock_key
+	 * value.
+	 */
+#ifdef CONFIG_ARC_STACK_CHECKING
+	pInitCtx->status32 = _ARC_V2_STATUS32_SC | _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
+	thread->arch.stack_top = (uint32_t) stackEnd;
 #else
-		thread->arch.priv_stack_start =
-			(u32_t)(stackEnd + STACK_GUARD_SIZE);
+	pInitCtx->status32 = _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
 #endif
 
-		priv_stack_end = (char *)Z_STACK_PTR_ALIGN(
-				thread->arch.priv_stack_start +
-				CONFIG_PRIVILEGED_STACK_SIZE);
+	_init_thread_base(&thread->base, priority, K_PRESTART, options);
 
-		/* reserve 4 bytes for the start of user sp */
-		priv_stack_end -= 4;
-		(*(u32_t *)priv_stack_end) = Z_STACK_PTR_ALIGN(
-			(u32_t)stackEnd - offset);
+	/* static threads overwrite them afterwards with real values */
+	thread->init_data = NULL;
+	thread->fn_abort = NULL;
 
-#ifdef CONFIG_THREAD_USERSPACE_LOCAL_DATA
-		/* reserve stack space for the userspace local data struct */
-		thread->userspace_local_data =
-			(struct _thread_userspace_local_data *)
-			Z_STACK_PTR_ALIGN(stackEnd -
-			sizeof(*thread->userspace_local_data) - offset);
-		/* update the start of user sp */
-		(*(u32_t *)priv_stack_end) =
-			(u32_t) thread->userspace_local_data;
+#ifdef CONFIG_THREAD_CUSTOM_DATA
+	/* Initialize custom data field (value is opaque to kernel) */
+
+	thread->custom_data = NULL;
 #endif
 
-	} else {
-		pStackMem += STACK_GUARD_SIZE;
-		stackEnd += STACK_GUARD_SIZE;
-
-		thread->arch.priv_stack_start = 0;
-
-#ifdef CONFIG_THREAD_USERSPACE_LOCAL_DATA
-		/* reserve stack space for the userspace local data struct */
-		priv_stack_end = (char *)Z_STACK_PTR_ALIGN(stackEnd
-			- sizeof(*thread->userspace_local_data) - offset);
-		thread->userspace_local_data =
-			(struct _thread_userspace_local_data *)priv_stack_end;
-#else
-		priv_stack_end = (char *)Z_STACK_PTR_ALIGN(stackEnd - offset);
+#ifdef CONFIG_THREAD_MONITOR
+	/*
+	 * In debug mode thread->entry give direct access to the thread entry
+	 * and the corresponding parameters.
+	 */
+	thread->entry = (struct __thread_entry *)(pInitCtx);
 #endif
-	}
-
-	z_new_thread_init(thread, pStackMem, stackAdjSize);
-
-	/* carve the thread entry struct from the "base" of
-		the privileged stack */
-	pInitCtx = (struct init_stack_frame *)(
-		priv_stack_end - sizeof(struct init_stack_frame));
-
-	/* fill init context */
-	pInitCtx->status32 = 0U;
-	if (options & K_USER) {
-		pInitCtx->pc = ((u32_t)z_user_thread_entry_wrapper);
-	} else {
-		pInitCtx->pc = ((u32_t)z_thread_entry_wrapper);
-	}
 
 	/*
-	 * enable US bit, US is read as zero in user mode. This will allow use
-	 * mode sleep instructions, and it enables a form of denial-of-service
-	 * attack by putting the processor in sleep mode, but since interrupt
-	 * level/mask can't be set from user space that's not worse than
-	 * executing a loop without yielding.
+	 * intlock_key is constructed based on ARCv2 ISA Programmer's
+	 * Reference Manual CLRI instruction description:
+	 * dst[31:6] dst[5] dst[4]       dst[3:0]
+	 *    26'd0    1    STATUS32.IE  STATUS32.E[3:0]
 	 */
-	pInitCtx->status32 |= _ARC_V2_STATUS32_US;
-#else /* For no USERSPACE feature */
-	pStackMem += STACK_GUARD_SIZE;
-	stackEnd = pStackMem + stackSize;
-
-	z_new_thread_init(thread, pStackMem, stackSize);
-
-	priv_stack_end = stackEnd;
-
-	pInitCtx = (struct init_stack_frame *)(
-		Z_STACK_PTR_ALIGN(priv_stack_end) -
-		sizeof(struct init_stack_frame));
-
-	pInitCtx->status32 = 0U;
-	pInitCtx->pc = ((u32_t)z_thread_entry_wrapper);
-#endif
-
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	pInitCtx->sec_stat = z_arc_v2_aux_reg_read(_ARC_V2_SEC_STAT);
-#endif
-
-	pInitCtx->r0 = (u32_t)pEntry;
-	pInitCtx->r1 = (u32_t)parameter1;
-	pInitCtx->r2 = (u32_t)parameter2;
-	pInitCtx->r3 = (u32_t)parameter3;
-
-/* stack check configuration */
-#ifdef CONFIG_ARC_STACK_CHECKING
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	pInitCtx->sec_stat |= _ARC_V2_SEC_STAT_SSC;
-#else
-	pInitCtx->status32 |= _ARC_V2_STATUS32_SC;
-#endif
-#ifdef CONFIG_USERSPACE
-	if (options & K_USER) {
-		thread->arch.u_stack_top = (u32_t)pStackMem;
-		thread->arch.u_stack_base = (u32_t)stackEnd;
-		thread->arch.k_stack_top =
-			 (u32_t)(thread->arch.priv_stack_start);
-		thread->arch.k_stack_base = (u32_t)
-		(thread->arch.priv_stack_start + CONFIG_PRIVILEGED_STACK_SIZE);
-	} else {
-		thread->arch.k_stack_top = (u32_t)pStackMem;
-		thread->arch.k_stack_base = (u32_t)stackEnd;
-		thread->arch.u_stack_top = 0;
-		thread->arch.u_stack_base = 0;
-	}
-#else
-	thread->arch.k_stack_top = (u32_t) pStackMem;
-	thread->arch.k_stack_base = (u32_t) stackEnd;
-#endif
-#endif
-
-#ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
-	pInitCtx->status32 |= _ARC_V2_STATUS32_AD;
-#endif
-
-	thread->switch_handle = thread;
+	thread->arch.intlock_key = 0x3F;
 	thread->arch.relinquish_cause = _CAUSE_COOP;
 	thread->callee_saved.sp =
-		(u32_t)pInitCtx - ___callee_saved_stack_t_SIZEOF;
+		(uint32_t)pInitCtx - ___callee_saved_stack_t_SIZEOF;
 
 	/* initial values in all other regs/k_thread entries are irrelevant */
+
+	thread_monitor_init(thread);
 }
-
-void *z_arch_get_next_switch_handle(struct k_thread **old_thread)
-{
-	*old_thread =  _current;
-
-	return z_get_next_switch_handle(*old_thread);
-}
-
-#ifdef CONFIG_USERSPACE
-
-FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
-					void *p1, void *p2, void *p3)
-{
-
-
-	_current->stack_info.start = (u32_t)_current->stack_obj;
-#ifdef CONFIG_GEN_PRIV_STACKS
-	_current->arch.priv_stack_start =
-			(u32_t)z_priv_stack_find(_current->stack_obj);
-#else
-	_current->arch.priv_stack_start =
-			(u32_t)(_current->stack_info.start +
-				_current->stack_info.size + STACK_GUARD_SIZE);
-#endif
-
-
-#ifdef CONFIG_ARC_STACK_CHECKING
-	_current->arch.k_stack_top = _current->arch.priv_stack_start;
-	_current->arch.k_stack_base = _current->arch.priv_stack_start +
-				CONFIG_PRIVILEGED_STACK_SIZE;
-	_current->arch.u_stack_top = _current->stack_info.start;
-	_current->arch.u_stack_base = _current->stack_info.start +
-				_current->stack_info.size;
-#endif
-
-	/* possible optimizaiton: no need to load mem domain anymore */
-	/* need to lock cpu here ? */
-	configure_mpu_thread(_current);
-
-	z_arc_userspace_enter(user_entry, p1, p2, p3,
-			      (u32_t)_current->stack_obj,
-			      _current->stack_info.size, _current);
-	CODE_UNREACHABLE;
-}
-
-#endif
-
-#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
-int arch_float_disable(struct k_thread *thread)
-{
-	unsigned int key;
-
-	/* Ensure a preemptive context switch does not occur */
-
-	key = irq_lock();
-
-	/* Disable all floating point capabilities for the thread */
-	thread->base.user_options &= ~K_FP_REGS;
-
-	irq_unlock(key);
-
-	return 0;
-}
-
-
-int arch_float_enable(struct k_thread *thread)
-{
-	unsigned int key;
-
-	/* Ensure a preemptive context switch does not occur */
-
-	key = irq_lock();
-
-	/* Enable all floating point capabilities for the thread */
-	thread->base.user_options |= K_FP_REGS;
-
-	irq_unlock(key);
-
-	return 0;
-}
-#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */

arch/arc/core/thread_entry_wrapper.S

@@ -1,38 +1,48 @@
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
  * @file
- * @brief Wrapper for z_thread_entry
+ * @brief Wrapper for _thread_entry
  *
- * Wrapper for z_thread_entry routine when called from the initial context.
+ * Wrapper for _thread_entry routine when called from the initial context.
  */
 
-#include <toolchain.h>
-#include <linker/sections.h>
-#include <v2/irq.h>
+#define _ASMLANGUAGE
 
-GTEXT(z_thread_entry_wrapper)
-GTEXT(z_thread_entry_wrapper1)
+#include <toolchain.h>
+#include <sections.h>
+
+GTEXT(_thread_entry_wrapper)
+GTEXT(_thread_entry)
 
 /*
- * @brief Wrapper for z_thread_entry
+ * @brief Wrapper for _thread_entry
  *
- * The routine pops parameters for the z_thread_entry from stack frame, prepared
- * by the arch_new_thread() routine.
+ * The routine pops parameters for the _thread_entry from stack frame, prepared
+ * by the _new_thread() routine.
  *
  * @return N/A
  */
 
-SECTION_FUNC(TEXT, z_thread_entry_wrapper)
-	seti _ARC_V2_INIT_IRQ_LOCK_KEY
-z_thread_entry_wrapper1:
+SECTION_FUNC(TEXT, _thread_entry_wrapper)
+
 	pop_s r3
 	pop_s r2
 	pop_s r1
 	pop_s r0
-	j z_thread_entry
+	j _thread_entry
 	nop

arch/arc/core/timestamp.c

@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2017 Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Time Stamp API for ARCv2
- *
- * Provide 64-bit time stamp API
- */
-
-#include <kernel.h>
-#include <toolchain.h>
-#include <kernel_structs.h>
-
-/*
- * @brief Read 64-bit timestamp value
- *
- * This function returns a 64-bit bit time stamp value that is clocked
- * at the same frequency as the CPU.
- *
- * @return 64-bit time stamp value
- */
-u64_t z_tsc_read(void)
-{
-	unsigned int key;
-	u64_t t;
-	u32_t count;
-
-	key = arch_irq_lock();
-	t = (u64_t)z_tick_get();
-	count = z_arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT);
-	arch_irq_unlock(key);
-	t *= k_ticks_to_cyc_floor64(1);
-	t += (u64_t)count;
-	return t;
-}

arch/arc/core/userspace.S

@@ -1,294 +0,0 @@
-/*
- * Copyright (c) 2018 Synopsys.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <offsets_short.h>
-#include <toolchain.h>
-#include <linker/sections.h>
-#include <kernel_structs.h>
-#include <arch/cpu.h>
-#include <syscall.h>
-#include <swap_macros.h>
-#include <v2/irq.h>
-
-.macro clear_scratch_regs
-	mov_s r1, 0
-	mov_s r2, 0
-	mov_s r3, 0
-	mov_s r4, 0
-	mov_s r5, 0
-	mov_s r6, 0
-	mov_s r7, 0
-	mov_s r8, 0
-	mov_s r9, 0
-	mov_s r10, 0
-	mov_s r11, 0
-	mov_s r12, 0
-.endm
-
-.macro clear_callee_regs
-	mov_s r25, 0
-	mov_s r24, 0
-	mov_s r23, 0
-	mov_s r22, 0
-	mov_s r21, 0
-	mov_s r20, 0
-	mov_s r19, 0
-	mov_s r18, 0
-	mov_s r17, 0
-	mov_s r16, 0
-
-	mov_s r15, 0
-	mov_s r14, 0
-	mov_s r13, 0
-.endm
-
-GTEXT(z_arc_userspace_enter)
-GTEXT(_arc_do_syscall)
-GTEXT(z_user_thread_entry_wrapper)
-GTEXT(arch_user_string_nlen)
-GTEXT(z_arc_user_string_nlen_fault_start)
-GTEXT(z_arc_user_string_nlen_fault_end)
-GTEXT(z_arc_user_string_nlen_fixup)
-/*
- * @brief Wrapper for z_thread_entry in the case of user thread
- * The init parameters are in privileged stack
- *
- * @return N/A
- */
-SECTION_FUNC(TEXT, z_user_thread_entry_wrapper)
-	seti _ARC_V2_INIT_IRQ_LOCK_KEY
-	pop_s r3
-	pop_s r2
-	pop_s r1
-	pop_s r0
-/* the start of user sp is in r5 */
-	pop r5
-/* start of privilege stack in blink */
-	mov_s blink, sp
-
-	st.aw r0, [r5, -4]
-	st.aw r1, [r5, -4]
-	st.aw r2, [r5, -4]
-	st.aw r3, [r5, -4]
-
-/*
- * when CONFIG_INIT_STACKS is enable, stack will be initialized
- * in z_new_thread_init.
- */
-	j _arc_go_to_user_space
-
-/**
- *
- * User space entry function
- *
- * This function is the entry point to user mode from privileged execution.
- * The conversion is one way, and threads which transition to user mode do
- * not transition back later, unless they are doing system calls.
- *
- */
-SECTION_FUNC(TEXT, z_arc_userspace_enter)
-	/*
-	 * In ARCv2, the U bit can only be set through exception return
-	 */
-	/* disable stack checking as the stack should be initialized */
-	_disable_stack_checking blink
-
-	/* the end of user stack in r5 */
-	add r5, r4, r5
-	/* get start of privilege stack, r6 points to current thread */
-	ld blink, [r6, _thread_offset_to_priv_stack_start]
-	add blink, blink, CONFIG_PRIVILEGED_STACK_SIZE
-
-	mov_s sp, r5
-
-	push_s r0
-	push_s r1
-	push_s r2
-	push_s r3
-
-	mov r5, sp /* skip r0, r1, r2, r3 */
-
-/* to avoid the leakage of kernel info, the thread stack needs to be
- * re-initialized
- */
-#ifdef CONFIG_INIT_STACKS
-	mov_s r0, 0xaaaaaaaa
-#else
-	mov_s r0, 0x0
-#endif
-_clear_user_stack:
-	st.ab r0, [r4, 4]
-	cmp r4, r5
-	jlt _clear_user_stack
-
-/* reload the stack checking regs as the original kernel stack
- * becomes user stack
- */
-#ifdef CONFIG_ARC_STACK_CHECKING
-/* current thread in r6, SMP case is also considered */
-	mov r2, r6
-
-	_load_stack_check_regs
-
-	_enable_stack_checking r0
-#endif
-
-/* the following codes are used to switch from kernel mode
- * to user mode by fake exception, because U bit can only be set
- * by exception
- */
-_arc_go_to_user_space:
-	lr r0, [_ARC_V2_STATUS32]
-	bset r0, r0, _ARC_V2_STATUS32_U_BIT
-
-	mov_s r1, z_thread_entry_wrapper1
-
-	sr r0, [_ARC_V2_ERSTATUS]
-	sr r1, [_ARC_V2_ERET]
-
-	/* fake exception return */
-	lr r0, [_ARC_V2_STATUS32]
-	bset r0, r0, _ARC_V2_STATUS32_AE_BIT
-	kflag r0
-
-/* when exception returns from kernel to user, sp and _ARC_V2_USER_SP
- * /_ARC_V2_SECU_SP will be switched
- */
-#if defined(CONFIG_ARC_HAS_SECURE) && defined(CONFIG_ARC_SECURE_FIRMWARE)
-	lr r0, [_ARC_V2_SEC_STAT]
-	/* the mode returns from exception return is secure mode */
-	bset r0, r0, 31
-	sr r0, [_ARC_V2_ERSEC_STAT]
-	sr r5, [_ARC_V2_SEC_U_SP]
-#else
-	sr r5, [_ARC_V2_USER_SP]
-#endif
-	mov_s sp, blink
-
-	mov_s r0, 0
-
-	clear_callee_regs
-
-	clear_scratch_regs
-
-	mov_s fp, 0
-	mov_s r29, 0
-	mov_s r30, 0
-	mov_s blink, 0
-
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	bl read_timer_end_of_userspace_enter
-#endif
-
-	rtie
-
-/**
- *
- * Userspace system call function
- *
- * This function is used to do system calls from unprivileged code.  This
- * function is responsible for the following:
- * 1) Dispatching the system call
- * 2) Restoring stack and calling back to the caller of the system call
- *
- */
-SECTION_FUNC(TEXT, _arc_do_syscall)
-	/*
-	 * r0-r5: arg1-arg6, r6 is call id which is already checked in
-	 * trap_s handler, r7 is the system call stack frame pointer
-	 * need to recover r0, r1, r2 because they will be modified in
-	 * _create_irq_stack_frame. If a specific syscall frame (different
-	 * with irq stack frame) is defined, the cover of r0, r1, r2 can be
-	 * optimized.
-	 */
-	ld_s r0, [sp, ___isf_t_r0_OFFSET]
-	ld_s r1, [sp, ___isf_t_r1_OFFSET]
-	ld_s r2, [sp, ___isf_t_r2_OFFSET]
-
-	mov r7, sp
-
-	mov_s blink, _k_syscall_table
-	ld.as r6, [blink, r6]
-
-	jl [r6]
-
-	/* save return value */
-	st_s r0, [sp, ___isf_t_r0_OFFSET]
-
-	mov_s r29, 0
-	mov_s r30, 0
-
-	/* through fake exception return, go back to the caller */
-	lr r0, [_ARC_V2_STATUS32]
-	bset r0, r0, _ARC_V2_STATUS32_AE_BIT
-	kflag r0
-
-
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	ld_s r0, [sp, ___isf_t_sec_stat_OFFSET]
-	sr r0,[_ARC_V2_ERSEC_STAT]
-#endif
-	ld_s r0, [sp, ___isf_t_status32_OFFSET]
-	sr r0,[_ARC_V2_ERSTATUS]
-
-	ld_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
-	sr r0,[_ARC_V2_ERET]
-
-	_pop_irq_stack_frame
-
-	rtie
-
-/*
- * size_t arch_user_string_nlen(const char *s, size_t maxsize, int *err_arg)
- */
-SECTION_FUNC(TEXT, arch_user_string_nlen)
-	/* int err; */
-	sub_s sp,sp,0x4
-
-	/* Initial error value (-1 failure), store at [sp,0] */
-	mov_s r3, -1
-	st_s r3, [sp, 0]
-
-	/* Loop setup.
-	 * r12 (position locator) = s - 1
-	 * r0 (length counter return value)) = 0
-	 * lp_count = maxsize + 1
-	 * */
-	sub r12, r0, 0x1
-	mov_s r0, 0
-	add_s r1, r1, 1
-	mov lp_count, r1
-
-strlen_loop:
-z_arc_user_string_nlen_fault_start:
-	/* is the byte at ++r12 a NULL? if so, we're done. Might fault! */
-	ldb.aw r1, [r12, 1]
-
-z_arc_user_string_nlen_fault_end:
-	brne_s r1, 0, not_null
-
-strlen_done:
-	/* Success, set err to 0 */
-	mov_s r1, 0
-	st_s r1, [sp, 0]
-
-z_arc_user_string_nlen_fixup:
-	/* *err_arg = err; Pop stack and return */
-	ld_s r1, [sp, 0]
-	add_s sp, sp, 4
-	j_s.d [blink]
-	st_s r1, [r2, 0]
-
-not_null:
-	/* check if we've hit the maximum, if so we're done. */
-	brne.d.nt lp_count, 0x1, inc_len
-	sub lp_count, lp_count, 0x1
-	b_s strlen_done
-
-inc_len:
-	/* increment length measurement, loop again */
-	add_s r0, r0, 1
-	b_s strlen_loop

arch/arc/core/vector_table.c

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -23,44 +33,45 @@
  * swapped.
  */
 
-#include <zephyr/types.h>
+#include <stdint.h>
 #include <toolchain.h>
 #include "vector_table.h"
 
 struct vector_table {
-	u32_t reset;
-	u32_t memory_error;
-	u32_t instruction_error;
-	u32_t ev_machine_check;
-	u32_t ev_tlb_miss_i;
-	u32_t ev_tlb_miss_d;
-	u32_t ev_prot_v;
-	u32_t ev_privilege_v;
-	u32_t ev_swi;
-	u32_t ev_trap;
-	u32_t ev_extension;
-	u32_t ev_div_zero;
-	u32_t ev_dc_error;
-	u32_t ev_maligned;
-	u32_t unused_1;
-	u32_t unused_2;
+	uint32_t reset;
+	uint32_t memory_error;
+	uint32_t instruction_error;
+	uint32_t ev_machine_check;
+	uint32_t ev_tlb_miss_i;
+	uint32_t ev_tlb_miss_d;
+	uint32_t ev_prot_v;
+	uint32_t ev_privilege_v;
+	uint32_t ev_swi;
+	uint32_t ev_trap;
+	uint32_t ev_extension;
+	uint32_t ev_div_zero;
+	uint32_t ev_dc_error;
+	uint32_t ev_maligned;
+	uint32_t unused_1;
+	uint32_t unused_2;
 };
 
-struct vector_table _VectorTable Z_GENERIC_SECTION(.exc_vector_table) = {
-	(u32_t)__reset,
-	(u32_t)__memory_error,
-	(u32_t)__instruction_error,
-	(u32_t)__ev_machine_check,
-	(u32_t)__ev_tlb_miss_i,
-	(u32_t)__ev_tlb_miss_d,
-	(u32_t)__ev_prot_v,
-	(u32_t)__ev_privilege_v,
-	(u32_t)__ev_swi,
-	(u32_t)__ev_trap,
-	(u32_t)__ev_extension,
-	(u32_t)__ev_div_zero,
-	(u32_t)__ev_dc_error,
-	(u32_t)__ev_maligned,
+struct vector_table _VectorTable _GENERIC_SECTION(.exc_vector_table) = {
+	(uint32_t)__reset,
+	(uint32_t)__memory_error,
+	(uint32_t)__instruction_error,
+	(uint32_t)__ev_machine_check,
+	(uint32_t)__ev_tlb_miss_i,
+	(uint32_t)__ev_tlb_miss_d,
+	(uint32_t)__ev_prot_v,
+	(uint32_t)__ev_privilege_v,
+	(uint32_t)__ev_swi,
+	(uint32_t)__ev_trap,
+	(uint32_t)__ev_extension,
+	(uint32_t)__ev_div_zero,
+	(uint32_t)__ev_dc_error,
+	(uint32_t)__ev_maligned,
 	0,
 	0
 };
+

arch/arc/core/vector_table.ld

@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2019 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/* when !XIP, .text is in RAM, and vector table must be at its very start */
-
-KEEP(*(.exc_vector_table))
-KEEP(*(".exc_vector_table.*"))
-KEEP(*(_IRQ_VECTOR_TABLE_SECTION_NAME))

arch/arc/defconfig

@@ -0,0 +1,6 @@
+CONFIG_ARC=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
+CONFIG_CPU_ARCEM4=y
+CONFIG_CPU_ARCV2=y
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y

arch/arc/include/kernel_arch_data.h

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014-2016 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -17,143 +27,97 @@
  * symbols" in the offsets.o module.
  */
 
-#ifndef ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_DATA_H_
-#define ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_DATA_H_
-
-#include <toolchain.h>
-#include <linker/sections.h>
-#include <arch/cpu.h>
-#include <vector_table.h>
-
-#ifndef _ASMLANGUAGE
-#include <kernel.h>
-#include <zephyr/types.h>
-#include <sys/util.h>
-#include <sys/dlist.h>
+#ifndef _kernel_arch_data__h_
+#define _kernel_arch_data__h_
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#ifdef CONFIG_ARC_HAS_SECURE
+#include <toolchain.h>
+#include <sections.h>
+#include <arch/cpu.h>
+#include <vector_table.h>
+
+#ifndef _ASMLANGUAGE
+#include <kernel.h>
+#include <nano_internal.h>
+#include <stdint.h>
+#include <misc/util.h>
+#include <misc/dlist.h>
+#endif
+
+#ifndef _ASMLANGUAGE
+
+struct _caller_saved {
+	/*
+	 * Saved on the stack as part of handling a regular IRQ or by the
+	 * kernel when calling the FIRQ return code.
+	 */
+};
+
+typedef struct _caller_saved _caller_saved_t;
+
 struct _irq_stack_frame {
-	u32_t lp_end;
-	u32_t lp_start;
-	u32_t lp_count;
+	uint32_t r0;
+	uint32_t r1;
+	uint32_t r2;
+	uint32_t r3;
+	uint32_t r4;
+	uint32_t r5;
+	uint32_t r6;
+	uint32_t r7;
+	uint32_t r8;
+	uint32_t r9;
+	uint32_t r10;
+	uint32_t r11;
+	uint32_t r12;
+	uint32_t r13;
+	uint32_t blink;
+	uint32_t lp_end;
+	uint32_t lp_start;
+	uint32_t lp_count;
 #ifdef CONFIG_CODE_DENSITY
 	/*
 	 * Currently unsupported. This is where those registers are
 	 * automatically pushed on the stack by the CPU when taking a regular
 	 * IRQ.
 	 */
-	u32_t ei_base;
-	u32_t ldi_base;
-	u32_t jli_base;
+	uint32_t ei_base;
+	uint32_t ldi_base;
+	uint32_t jli_base;
 #endif
-	u32_t r0;
-	u32_t r1;
-	u32_t r2;
-	u32_t r3;
-	u32_t r4;
-	u32_t r5;
-	u32_t r6;
-	u32_t r7;
-	u32_t r8;
-	u32_t r9;
-	u32_t r10;
-	u32_t r11;
-	u32_t r12;
-	u32_t r13;
-	u32_t blink;
-	u32_t pc;
-	u32_t sec_stat;
-	u32_t status32;
+	uint32_t pc;
+	uint32_t status32;
 };
-#else
-struct _irq_stack_frame {
-	u32_t r0;
-	u32_t r1;
-	u32_t r2;
-	u32_t r3;
-	u32_t r4;
-	u32_t r5;
-	u32_t r6;
-	u32_t r7;
-	u32_t r8;
-	u32_t r9;
-	u32_t r10;
-	u32_t r11;
-	u32_t r12;
-	u32_t r13;
-	u32_t blink;
-	u32_t lp_end;
-	u32_t lp_start;
-	u32_t lp_count;
-#ifdef CONFIG_CODE_DENSITY
-	/*
-	 * Currently unsupported. This is where those registers are
-	 * automatically pushed on the stack by the CPU when taking a regular
-	 * IRQ.
-	 */
-	u32_t ei_base;
-	u32_t ldi_base;
-	u32_t jli_base;
-#endif
-	u32_t pc;
-	u32_t status32;
-};
-#endif
 
 typedef struct _irq_stack_frame _isf_t;
 
-
+struct _callee_saved {
+	uint32_t sp; /* r28 */
+};
+typedef struct _callee_saved _callee_saved_t;
 
 /* callee-saved registers pushed on the stack, not in k_thread */
 struct _callee_saved_stack {
-	u32_t r13;
-	u32_t r14;
-	u32_t r15;
-	u32_t r16;
-	u32_t r17;
-	u32_t r18;
-	u32_t r19;
-	u32_t r20;
-	u32_t r21;
-	u32_t r22;
-	u32_t r23;
-	u32_t r24;
-	u32_t r25;
-	u32_t r26;
-	u32_t fp; /* r27 */
-
-#ifdef CONFIG_USERSPACE
-#ifdef CONFIG_ARC_HAS_SECURE
-	u32_t user_sp;
-	u32_t kernel_sp;
-#else
-	u32_t user_sp;
-#endif
-#endif
+	uint32_t r13;
+	uint32_t r14;
+	uint32_t r15;
+	uint32_t r16;
+	uint32_t r17;
+	uint32_t r18;
+	uint32_t r19;
+	uint32_t r20;
+	uint32_t r21;
+	uint32_t r22;
+	uint32_t r23;
+	uint32_t r24;
+	uint32_t r25;
+	uint32_t r26;
+	uint32_t fp; /* r27 */
 	/* r28 is the stack pointer and saved separately */
 	/* r29 is ILINK and does not need to be saved */
-	u32_t r30;
-
-#ifdef CONFIG_ARC_HAS_ACCL_REGS
-	u32_t r58;
-	u32_t r59;
-#endif
-
-#ifdef CONFIG_FPU_SHARING
-	u32_t fpu_status;
-	u32_t fpu_ctrl;
-#ifdef CONFIG_FP_FPU_DA
-	u32_t dpfp2h;
-	u32_t dpfp2l;
-	u32_t dpfp1h;
-	u32_t dpfp1l;
-#endif
-
-#endif
+	uint32_t r30;
 	/*
 	 * No need to save r31 (blink), it's either alread pushed as the pc or
 	 * blink on an irq stack frame.
@@ -162,10 +126,62 @@ struct _callee_saved_stack {
 
 typedef struct _callee_saved_stack _callee_saved_stack_t;
 
+#endif /* _ASMLANGUAGE */
+
+/* stacks */
+
+#define STACK_ALIGN_SIZE 4
+
+#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
+#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
+
+/*
+ * Reason a thread has relinquished control: fibers can only be in the NONE
+ * or COOP state, tasks can be one in the four.
+ */
+#define _CAUSE_NONE 0
+#define _CAUSE_COOP 1
+#define _CAUSE_RIRQ 2
+#define _CAUSE_FIRQ 3
+
+#ifndef _ASMLANGUAGE
+
+struct _thread_arch {
+
+	/* interrupt key when relinquishing control */
+	uint32_t intlock_key;
+
+	/* one of the _CAUSE_xxxx definitions above */
+	int relinquish_cause;
+
+	/* return value from _Swap */
+	unsigned int return_value;
+
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* top of stack for hardware stack checking */
+	uint32_t stack_top;
+#endif
+};
+
+typedef struct _thread_arch _thread_arch_t;
+
+struct _kernel_arch {
+
+	char *rirq_sp; /* regular IRQ stack pointer base */
+
+	/*
+	 * FIRQ stack pointer is installed once in the second bank's SP, so
+	 * there is no need to track it in _kernel.
+	 */
+
+};
+
+typedef struct _kernel_arch _kernel_arch_t;
+
+#endif /* _ASMLANGUAGE */
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* _ASMLANGUAGE */
-
-#endif /* ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_DATA_H_ */
+#endif /* _kernel_arch_data__h_ */

arch/arc/include/kernel_arch_func.h

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014-2016 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -17,64 +27,72 @@
  * symbols" in the offsets.o module.
  */
 
-#ifndef ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_FUNC_H_
-#define ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_FUNC_H_
+#ifndef _kernel_arch_func__h_
+#define _kernel_arch_func__h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #if !defined(_ASMLANGUAGE)
 
-#include <kernel_arch_data.h>
-
 #ifdef CONFIG_CPU_ARCV2
 #include <v2/cache.h>
 #include <v2/irq.h>
 #endif
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-static ALWAYS_INLINE void arch_kernel_init(void)
+static ALWAYS_INLINE void nanoArchInit(void)
 {
-	z_irq_setup();
+	_icache_setup();
+	_irq_setup();
 }
 
+static ALWAYS_INLINE void
+_set_thread_return_value(struct k_thread *thread, unsigned int value)
+{
+	thread->arch.return_value = value;
+}
+
+static ALWAYS_INLINE int _is_in_isr(void)
+{
+	uint32_t act = _arc_v2_aux_reg_read(_ARC_V2_AUX_IRQ_ACT);
+#if CONFIG_IRQ_OFFLOAD
+	/* Check if we're in a TRAP_S exception as well */
+	if (_arc_v2_aux_reg_read(_ARC_V2_STATUS32) & _ARC_V2_STATUS32_AE &&
+	    _ARC_V2_ECR_VECTOR(_arc_v2_aux_reg_read(_ARC_V2_ECR)) == EXC_EV_TRAP
+	   ) {
+		return 1;
+	}
+#endif
+	return ((act & 0xffff) != 0);
+}
 
 /**
  *
- * @brief Indicates the interrupt number of the highest priority
+ * @bried Indicates the interrupt number of the highest priority
  * active interrupt
  *
  * @return IRQ number
  */
-static ALWAYS_INLINE int Z_INTERRUPT_CAUSE(void)
+static ALWAYS_INLINE int _INTERRUPT_CAUSE(void)
 {
-	u32_t irq_num = z_arc_v2_aux_reg_read(_ARC_V2_ICAUSE);
+	uint32_t irq_num = _arc_v2_aux_reg_read(_ARC_V2_ICAUSE);
 
 	return irq_num;
 }
 
-static inline bool arch_is_in_isr(void)
+
+extern void _thread_entry_wrapper(void);
+
+static inline void _IntLibInit(void)
 {
-	return z_arc_v2_irq_unit_is_in_isr();
+	/* nothing needed, here because the kernel requires it */
 }
 
-extern void z_thread_entry_wrapper(void);
-extern void z_user_thread_entry_wrapper(void);
-
-extern void z_arc_userspace_enter(k_thread_entry_t user_entry, void *p1,
-		 void *p2, void *p3, u32_t stack, u32_t size,
-		 struct k_thread *thread);
-
-
-extern void arch_switch(void *switch_to, void **switched_from);
-extern void z_arc_fatal_error(unsigned int reason, const z_arch_esf_t *esf);
-
-extern void arch_sched_ipi(void);
+#endif /* _ASMLANGUAGE */
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* _ASMLANGUAGE */
-
-#endif /* ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_FUNC_H_ */
+#endif /* _kernel_arch_func__h_ */

arch/arc/include/kernel_event_logger_arch.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Kernel event logger support for ARM
+ */
+
+#ifndef __KERNEL_EVENT_LOGGER_ARCH_H__
+#define __KERNEL_EVENT_LOGGER_ARCH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get the identification of the current interrupt.
+ *
+ * This routine obtain the key of the interrupt that is currently processed
+ * if it is called from a ISR context.
+ *
+ * @return The key of the interrupt that is currently being processed.
+ */
+int _sys_current_irq_key_get(void)
+{
+	return _INTERRUPT_CAUSE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __KERNEL_EVENT_LOGGER_ARCH_H__ */

arch/arc/include/offsets_short_arch.h

@@ -1,11 +1,21 @@
 /*
  * Copyright (c) 2016 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
-#ifndef ZEPHYR_ARCH_ARC_INCLUDE_OFFSETS_SHORT_ARCH_H_
-#define ZEPHYR_ARCH_ARC_INCLUDE_OFFSETS_SHORT_ARCH_H_
+#ifndef _offsets_short_arch__h_
+#define _offsets_short_arch__h_
 
 #include <offsets.h>
 
@@ -17,27 +27,22 @@
 
 /* threads */
 
+#define _thread_offset_to_intlock_key \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_intlock_key_OFFSET)
+
 #define _thread_offset_to_relinquish_cause \
 	(___thread_t_arch_OFFSET + ___thread_arch_t_relinquish_cause_OFFSET)
 
-#define _thread_offset_to_k_stack_base \
-	(___thread_t_arch_OFFSET + ___thread_arch_t_k_stack_base_OFFSET)
+#define _thread_offset_to_return_value \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_return_value_OFFSET)
 
-#define _thread_offset_to_k_stack_top \
-	(___thread_t_arch_OFFSET + ___thread_arch_t_k_stack_top_OFFSET)
-
-#define _thread_offset_to_u_stack_base \
-	(___thread_t_arch_OFFSET + ___thread_arch_t_u_stack_base_OFFSET)
-
-#define _thread_offset_to_u_stack_top \
-	(___thread_t_arch_OFFSET + ___thread_arch_t_u_stack_top_OFFSET)
-
-#define _thread_offset_to_priv_stack_start \
-	(___thread_t_arch_OFFSET + ___thread_arch_t_priv_stack_start_OFFSET)
+#define _thread_offset_to_stack_top \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_stack_top_OFFSET)
 
 #define _thread_offset_to_sp \
 	(___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET)
 
+
 /* end - threads */
 
-#endif /* ZEPHYR_ARCH_ARC_INCLUDE_OFFSETS_SHORT_ARCH_H_ */
+#endif /* _offsets_short_arch__h_ */

arch/arc/include/start_task_arch.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief ARC nanokernel declarations to start a task
+ *
+ * ARC-specific parts of start_task().
+ *
+ * Currently empty, only here for abstraction.
+ */
+
+#ifndef _START_TASK_ARCH__H_
+#define _START_TASK_ARCH__H_
+
+#include <toolchain.h>
+#include <sections.h>
+
+#include <micro_private.h>
+#include <kernel_structs.h>
+#include <microkernel/task.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _START_TASK_ARCH(task, opt_ptr) \
+	do {/* nothing */              \
+	} while ((0))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _START_TASK_ARCH__H_ */

arch/arc/include/swap_macros.h

@@ -1,524 +0,0 @@
-/* swap_macros.h - helper macros for context switch */
-
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_
-#define ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_
-
-#include <kernel_structs.h>
-#include <offsets_short.h>
-#include <toolchain.h>
-#include <arch/cpu.h>
-
-#ifdef _ASMLANGUAGE
-
-/* save callee regs of current thread in r2 */
-.macro _save_callee_saved_regs
-
-	sub_s sp, sp, ___callee_saved_stack_t_SIZEOF
-
-	/* save regs on stack */
-	st_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
-	st_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
-	st_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
-	st r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
-	st r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
-	st r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
-	st r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
-	st r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
-	st r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
-	st r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
-	st r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
-	st r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
-	st r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
-	st r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
-	st fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
-
-#ifdef CONFIG_USERSPACE
-#ifdef CONFIG_ARC_HAS_SECURE
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	lr r13, [_ARC_V2_SEC_U_SP]
-	st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
-	lr r13, [_ARC_V2_SEC_K_SP]
-	st_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
-#else
-	lr r13, [_ARC_V2_USER_SP]
-	st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
-	lr r13, [_ARC_V2_KERNEL_SP]
-	st_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
-#endif /* CONFIG_ARC_SECURE_FIRMWARE */
-#else
-	lr r13, [_ARC_V2_USER_SP]
-	st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
-#endif
-#endif
-	st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
-
-#ifdef CONFIG_ARC_HAS_ACCL_REGS
-	st r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
-	st r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
-#endif
-
-#ifdef CONFIG_FPU_SHARING
-	ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
-	/* K_FP_REGS is bit 1 */
-	bbit0 r13, 1, 1f
-	lr r13, [_ARC_V2_FPU_STATUS]
-	st_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
-	lr r13, [_ARC_V2_FPU_CTRL]
-	st_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
-
-#ifdef CONFIG_FP_FPU_DA
-	lr r13, [_ARC_V2_FPU_DPFP1L]
-	st_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
-	lr r13, [_ARC_V2_FPU_DPFP1H]
-	st_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
-	lr r13, [_ARC_V2_FPU_DPFP2L]
-	st_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
-	lr r13, [_ARC_V2_FPU_DPFP2H]
-	st_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
-#endif
-1 :
-#endif
-
-	/* save stack pointer in struct k_thread */
-	st sp, [r2, _thread_offset_to_sp]
-.endm
-
-/* load the callee regs of thread (in r2)*/
-.macro _load_callee_saved_regs
-	/* restore stack pointer from struct k_thread */
-	ld sp, [r2, _thread_offset_to_sp]
-
-#ifdef CONFIG_ARC_HAS_ACCL_REGS
-	ld r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
-	ld r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
-#endif
-
-#ifdef CONFIG_FPU_SHARING
-	ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
-	/* K_FP_REGS is bit 1 */
-	bbit0 r13, 1, 2f
-
-	ld_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
-	sr r13, [_ARC_V2_FPU_STATUS]
-	ld_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
-	sr r13, [_ARC_V2_FPU_CTRL]
-
-#ifdef CONFIG_FP_FPU_DA
-	ld_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
-	sr r13, [_ARC_V2_FPU_DPFP1L]
-	ld_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
-	sr r13, [_ARC_V2_FPU_DPFP1H]
-	ld_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
-	sr r13, [_ARC_V2_FPU_DPFP2L]
-	ld_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
-	sr r13, [_ARC_V2_FPU_DPFP2H]
-#endif
-2 :
-#endif
-
-#ifdef CONFIG_USERSPACE
-#ifdef CONFIG_ARC_HAS_SECURE
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
-	sr r13, [_ARC_V2_SEC_U_SP]
-	ld_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
-	sr r13, [_ARC_V2_SEC_K_SP]
-#else
-	ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
-	sr r13, [_ARC_V2_USER_SP]
-	ld_s r13, [sp, ___callee_saved_stack_t_kernel_sp_OFFSET]
-	sr r13, [_ARC_V2_KERNEL_SP]
-#endif /* CONFIG_ARC_SECURE_FIRMWARE */
-#else
-	ld_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
-	sr r13, [_ARC_V2_USER_SP]
-#endif
-#endif
-
-	ld_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
-	ld_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
-	ld_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
-	ld r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
-	ld r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
-	ld r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
-	ld r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
-	ld r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
-	ld r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
-	ld r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
-	ld r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
-	ld r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
-	ld r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
-	ld r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
-	ld fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
-	ld r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
-
-	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
-
-.endm
-
-/* discard callee regs */
-.macro _discard_callee_saved_regs
-	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
-.endm
-
-/*
- * Must be called with interrupts locked or in P0.
- * Upon exit, sp will be pointing to the stack frame.
- */
-.macro _create_irq_stack_frame
-
-	sub_s sp, sp, ___isf_t_SIZEOF
-
-	st blink, [sp, ___isf_t_blink_OFFSET]
-
-	/* store these right away so we can use them if needed */
-
-	st_s r13, [sp, ___isf_t_r13_OFFSET]
-	st_s r12, [sp, ___isf_t_r12_OFFSET]
-	st   r11, [sp, ___isf_t_r11_OFFSET]
-	st   r10, [sp, ___isf_t_r10_OFFSET]
-	st   r9,  [sp, ___isf_t_r9_OFFSET]
-	st   r8,  [sp, ___isf_t_r8_OFFSET]
-	st   r7,  [sp, ___isf_t_r7_OFFSET]
-	st   r6,  [sp, ___isf_t_r6_OFFSET]
-	st   r5,  [sp, ___isf_t_r5_OFFSET]
-	st   r4,  [sp, ___isf_t_r4_OFFSET]
-	st_s r3,  [sp, ___isf_t_r3_OFFSET]
-	st_s r2,  [sp, ___isf_t_r2_OFFSET]
-	st_s r1,  [sp, ___isf_t_r1_OFFSET]
-	st_s r0,  [sp, ___isf_t_r0_OFFSET]
-
-	mov r0, lp_count
-	st_s r0, [sp, ___isf_t_lp_count_OFFSET]
-	lr r1, [_ARC_V2_LP_START]
-	lr r0, [_ARC_V2_LP_END]
-	st_s r1, [sp, ___isf_t_lp_start_OFFSET]
-	st_s r0, [sp, ___isf_t_lp_end_OFFSET]
-
-#ifdef CONFIG_CODE_DENSITY
-	lr r1, [_ARC_V2_JLI_BASE]
-	lr r0, [_ARC_V2_LDI_BASE]
-	lr r2, [_ARC_V2_EI_BASE]
-	st_s r1, [sp, ___isf_t_jli_base_OFFSET]
-	st_s r0, [sp, ___isf_t_ldi_base_OFFSET]
-	st_s r2, [sp, ___isf_t_ei_base_OFFSET]
-#endif
-
-.endm
-
-/*
- * Must be called with interrupts locked or in P0.
- * sp must be pointing the to stack frame.
- */
-.macro _pop_irq_stack_frame
-
-	ld blink, [sp, ___isf_t_blink_OFFSET]
-
-#ifdef CONFIG_CODE_DENSITY
-	ld_s r1, [sp, ___isf_t_jli_base_OFFSET]
-	ld_s r0, [sp, ___isf_t_ldi_base_OFFSET]
-	ld_s r2, [sp, ___isf_t_ei_base_OFFSET]
-	sr r1, [_ARC_V2_JLI_BASE]
-	sr r0, [_ARC_V2_LDI_BASE]
-	sr r2, [_ARC_V2_EI_BASE]
-#endif
-
-	ld_s r0, [sp, ___isf_t_lp_count_OFFSET]
-	mov lp_count, r0
-	ld_s r1, [sp, ___isf_t_lp_start_OFFSET]
-	ld_s r0, [sp, ___isf_t_lp_end_OFFSET]
-	sr r1, [_ARC_V2_LP_START]
-	sr r0, [_ARC_V2_LP_END]
-
-	ld_s r13, [sp, ___isf_t_r13_OFFSET]
-	ld_s r12, [sp, ___isf_t_r12_OFFSET]
-	ld   r11, [sp, ___isf_t_r11_OFFSET]
-	ld   r10, [sp, ___isf_t_r10_OFFSET]
-	ld   r9,  [sp, ___isf_t_r9_OFFSET]
-	ld   r8,  [sp, ___isf_t_r8_OFFSET]
-	ld   r7,  [sp, ___isf_t_r7_OFFSET]
-	ld   r6,  [sp, ___isf_t_r6_OFFSET]
-	ld   r5,  [sp, ___isf_t_r5_OFFSET]
-	ld   r4,  [sp, ___isf_t_r4_OFFSET]
-	ld_s r3,  [sp, ___isf_t_r3_OFFSET]
-	ld_s r2,  [sp, ___isf_t_r2_OFFSET]
-	ld_s r1,  [sp, ___isf_t_r1_OFFSET]
-	ld_s r0,  [sp, ___isf_t_r0_OFFSET]
-
-
-	/*
-	 * All gprs have been reloaded, the only one that is still usable is
-	 * ilink.
-	 *
-	 * The pc and status32 values will still be on the stack. We cannot
-	 * pop them yet because the callers of _pop_irq_stack_frame must reload
-	 * status32 differently depending on the execution context they are
-	 * running in (arch_switch(), firq or exception).
-	 */
-	add_s sp, sp, ___isf_t_SIZEOF
-
-.endm
-
-/*
- * To use this macro, r2 should have the value of thread struct pointer to
- * _kernel.current. r3 is a scratch reg.
- */
-.macro _load_stack_check_regs
-#if defined(CONFIG_ARC_SECURE_FIRMWARE)
-	ld r3, [r2, _thread_offset_to_k_stack_base]
-	sr r3, [_ARC_V2_S_KSTACK_BASE]
-	ld r3, [r2, _thread_offset_to_k_stack_top]
-	sr r3, [_ARC_V2_S_KSTACK_TOP]
-#ifdef CONFIG_USERSPACE
-	ld r3, [r2, _thread_offset_to_u_stack_base]
-	sr r3, [_ARC_V2_S_USTACK_BASE]
-	ld r3, [r2, _thread_offset_to_u_stack_top]
-	sr r3, [_ARC_V2_S_USTACK_TOP]
-#endif
-#else /* CONFIG_ARC_HAS_SECURE */
-	ld r3, [r2, _thread_offset_to_k_stack_base]
-	sr r3, [_ARC_V2_KSTACK_BASE]
-	ld r3, [r2, _thread_offset_to_k_stack_top]
-	sr r3, [_ARC_V2_KSTACK_TOP]
-#ifdef CONFIG_USERSPACE
-	ld r3, [r2, _thread_offset_to_u_stack_base]
-	sr r3, [_ARC_V2_USTACK_BASE]
-	ld r3, [r2, _thread_offset_to_u_stack_top]
-	sr r3, [_ARC_V2_USTACK_TOP]
-#endif
-#endif /* CONFIG_ARC_SECURE_FIRMWARE */
-.endm
-
-/* check and increase the interrupt nest counter
- * after increase, check whether nest counter == 1
- * the result will be EQ bit of status32
- * two temp regs are needed
- */
-.macro _check_and_inc_int_nest_counter reg1 reg2
-#ifdef CONFIG_SMP
-	_get_cpu_id \reg1
-	ld.as \reg1, [@_curr_cpu, \reg1]
-	ld \reg2, [\reg1, ___cpu_t_nested_OFFSET]
-#else
-	mov \reg1, _kernel
-	ld \reg2, [\reg1, _kernel_offset_to_nested]
-#endif
-	add \reg2, \reg2, 1
-#ifdef CONFIG_SMP
-	st \reg2, [\reg1, ___cpu_t_nested_OFFSET]
-#else
-	st \reg2, [\reg1, _kernel_offset_to_nested]
-#endif
-	cmp \reg2, 1
-.endm
-
-/* decrease interrupt stack nest counter
- * the counter > 0, interrupt stack is used, or
- * not used
- */
-.macro _dec_int_nest_counter reg1 reg2
-#ifdef CONFIG_SMP
-	_get_cpu_id \reg1
-	ld.as \reg1, [@_curr_cpu, \reg1]
-	ld \reg2, [\reg1, ___cpu_t_nested_OFFSET]
-#else
-	mov \reg1, _kernel
-	ld \reg2, [\reg1, _kernel_offset_to_nested]
-#endif
-	sub \reg2, \reg2, 1
-#ifdef CONFIG_SMP
-	st \reg2, [\reg1, ___cpu_t_nested_OFFSET]
-#else
-	st \reg2, [\reg1, _kernel_offset_to_nested]
-#endif
-.endm
-
-/* If multi bits in IRQ_ACT are set, i.e. last bit != fist bit, it's
- * in nest interrupt. The result will be EQ bit of status32
- * need two temp reg to do this
- */
-.macro _check_nest_int_by_irq_act  reg1, reg2
-	lr \reg1, [_ARC_V2_AUX_IRQ_ACT]
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	and \reg1, \reg1, ((1 << ARC_N_IRQ_START_LEVEL) - 1)
-#else
-	and \reg1, \reg1, 0xffff
-#endif
-	ffs \reg2, \reg1
-	fls \reg1, \reg1
-	cmp \reg1, \reg2
-.endm
-
-
-/* macro to get id of current cpu
- * the result will be in reg (a reg)
- */
-.macro _get_cpu_id reg
-	lr \reg, [_ARC_V2_IDENTITY]
-	xbfu \reg, \reg, 0xe8
-.endm
-
-/* macro to get the interrupt stack of current cpu
- * the result will be in irq_sp (a reg)
- */
-.macro _get_curr_cpu_irq_stack irq_sp
-#ifdef CONFIG_SMP
-	_get_cpu_id \irq_sp
-	ld.as \irq_sp, [@_curr_cpu, \irq_sp]
-	ld \irq_sp, [\irq_sp, ___cpu_t_irq_stack_OFFSET]
-#else
-	mov \irq_sp, _kernel
-	ld \irq_sp, [\irq_sp, _kernel_offset_to_irq_stack]
-#endif
-.endm
-
-/* macro to push aux reg through reg */
-.macro PUSHAX reg aux
-	lr \reg, [\aux]
-	st.a \reg, [sp, -4]
-.endm
-
-/* macro to pop aux reg through reg */
-.macro POPAX reg aux
-	ld.ab \reg, [sp, 4]
-	sr \reg, [\aux]
-.endm
-
-
-/* macro to store old thread call regs */
-.macro _store_old_thread_callee_regs
-
-	_save_callee_saved_regs
-#ifdef CONFIG_SMP
-	/* save old thread into switch handle which is required by
-	 * wait_for_switch
-	 */
-	st r2, [r2, ___thread_t_switch_handle_OFFSET]
-#endif
-.endm
-
-/* macro to store old thread call regs  in interrupt*/
-.macro _irq_store_old_thread_callee_regs
-#if defined(CONFIG_USERSPACE)
-/*
- * when USERSPACE is enabled, according to ARCv2 ISA, SP will be switched
- * if interrupt comes out in user mode, and will be recorded in bit 31
- * (U bit) of IRQ_ACT. when interrupt exits, SP will be switched back
- * according to U bit.
- *
- * need to remember the user/kernel status of interrupted thread, will be
- * restored when thread switched back
- *
- */
-	lr r1, [_ARC_V2_AUX_IRQ_ACT]
-	and r3, r1, 0x80000000
-	push_s r3
-
-	bclr r1, r1, 31
-	sr r1, [_ARC_V2_AUX_IRQ_ACT]
-#endif
-	_store_old_thread_callee_regs
-.endm
-
-/* macro to load new thread callee regs */
-.macro _load_new_thread_callee_regs
-#ifdef CONFIG_ARC_STACK_CHECKING
-	_load_stack_check_regs
-#endif
-	/*
-	 * _load_callee_saved_regs expects incoming thread in r2.
-	 * _load_callee_saved_regs restores the stack pointer.
-	 */
-	_load_callee_saved_regs
-
-#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
-	push_s r2
-	bl configure_mpu_thread
-	pop_s r2
-#endif
-
-	ld r3, [r2, _thread_offset_to_relinquish_cause]
-.endm
-
-
-/* when switch to thread caused by coop, some status regs need to set */
-.macro _set_misc_regs_irq_switch_from_coop
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	/* must return to secure mode, so set IRM bit to 1 */
-	lr r0, [_ARC_V2_SEC_STAT]
-	bset r0, r0, _ARC_V2_SEC_STAT_IRM_BIT
-	sflag r0
-#endif
-.endm
-
-/* when switch to thread caused by irq, some status regs need to set */
-.macro _set_misc_regs_irq_switch_from_irq
-#if defined(CONFIG_USERSPACE)
-/*
- * need to recover the user/kernel status of interrupted thread
- */
-	pop_s r3
-	lr r2, [_ARC_V2_AUX_IRQ_ACT]
-	or r2, r2, r3
-	sr r2, [_ARC_V2_AUX_IRQ_ACT]
-#endif
-
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	/* here need to recover SEC_STAT.IRM bit */
-	pop_s r3
-	sflag r3
-#endif
-.endm
-
-/* macro to get next switch handle in assembly */
-.macro _get_next_switch_handle
-	push_s r2
-	mov r0, sp
-	bl z_arch_get_next_switch_handle
-	pop_s  r2
-.endm
-
-/* macro to disable stack checking in assembly, need a GPR
- * to do this
- */
-.macro _disable_stack_checking reg
-#ifdef CONFIG_ARC_STACK_CHECKING
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	lr \reg, [_ARC_V2_SEC_STAT]
-	bclr \reg, \reg, _ARC_V2_SEC_STAT_SSC_BIT
-	sflag \reg
-
-#else
-	lr \reg, [_ARC_V2_STATUS32]
-	bclr \reg, \reg, _ARC_V2_STATUS32_SC_BIT
-	kflag \reg
-#endif
-#endif
-.endm
-
-/* macro to enable stack checking in assembly, need a GPR
- * to do this
- */
-.macro _enable_stack_checking reg
-#ifdef CONFIG_ARC_STACK_CHECKING
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-	lr \reg, [_ARC_V2_SEC_STAT]
-	bset \reg, \reg, _ARC_V2_SEC_STAT_SSC_BIT
-	sflag \reg
-#else
-	lr \reg, [_ARC_V2_STATUS32]
-	bset \reg, \reg, _ARC_V2_STATUS32_SC_BIT
-	kflag \reg
-#endif
-#endif
-.endm
-
-#endif /* _ASMLANGUAGE */
-
-#endif /*  ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_ */

arch/arc/include/v2/cache.h

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -12,17 +22,17 @@
  * ARCv2 processor architecture.
  */
 
-#ifndef ZEPHYR_ARCH_ARC_INCLUDE_V2_CACHE_H_
-#define ZEPHYR_ARCH_ARC_INCLUDE_V2_CACHE_H_
+#ifndef _ARCV2_CACHE__H_
+#define _ARCV2_CACHE__H_
 
 #include <arch/cpu.h>
 
-#ifndef _ASMLANGUAGE
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#ifndef _ASMLANGUAGE
+
 /* i-cache defines for IC_CTRL register */
 #define IC_CACHE_ENABLE   0x00
 #define IC_CACHE_DISABLE  0x01
@@ -34,26 +44,26 @@ extern "C" {
  *
  * Enables the i-cache and sets it to direct access mode.
  */
-static ALWAYS_INLINE void z_icache_setup(void)
+static ALWAYS_INLINE void _icache_setup(void)
 {
-	u32_t icache_config = (
+	uint32_t icache_config = (
 		IC_CACHE_DIRECT | /* direct mapping (one-way assoc.) */
 		IC_CACHE_ENABLE   /* i-cache enabled */
 	);
-	u32_t val;
+	uint32_t val;
 
-	val = z_arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
+	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
 	val &= 0xff;
-	if (val != 0U) { /* is i-cache present? */
+	if (val != 0) { /* is i-cache present? */
 		/* configure i-cache */
-		z_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
+		_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
 	}
 }
 
+#endif /* _ASMLANGUAGE */
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* _ASMLANGUAGE */
-
-#endif /* ZEPHYR_ARCH_ARC_INCLUDE_V2_CACHE_H_ */
+#endif /* _ARCV2_CACHE__H_ */

arch/arc/include/v2/irq.h

@@ -1,21 +1,29 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
  * @file
  * @brief Interrupt helper functions (ARC)
  *
- * This file contains private kernel structures definitions and various
+ * This file contains private nanokernel structures definitions and various
  * other definitions for the ARCv2 processor architecture.
  */
 
-#ifndef ZEPHYR_ARCH_ARC_INCLUDE_V2_IRQ_H_
-#define ZEPHYR_ARCH_ARC_INCLUDE_V2_IRQ_H_
-
-#include <arch/cpu.h>
+#ifndef _ARCV2_IRQ__H_
+#define _ARCV2_IRQ__H_
 
 #ifdef __cplusplus
 extern "C" {
@@ -23,53 +31,37 @@ extern "C" {
 
 #define _ARC_V2_AUX_IRQ_CTRL_BLINK (1 << 9)
 #define _ARC_V2_AUX_IRQ_CTRL_LOOP_REGS (1 << 10)
-#define _ARC_V2_AUX_IRQ_CTRL_U (1 << 11)
 #define _ARC_V2_AUX_IRQ_CTRL_LP (1 << 13)
 #define _ARC_V2_AUX_IRQ_CTRL_14_REGS 7
 #define _ARC_V2_AUX_IRQ_CTRL_16_REGS 8
 #define _ARC_V2_AUX_IRQ_CTRL_32_REGS 16
 
-
-#ifdef CONFIG_ARC_SECURE_FIRMWARE
-#define _ARC_V2_DEF_IRQ_LEVEL (ARC_N_IRQ_START_LEVEL - 1)
-#else
-#define _ARC_V2_DEF_IRQ_LEVEL (CONFIG_NUM_IRQ_PRIO_LEVELS - 1)
-#endif
-
+#define _ARC_V2_DEF_IRQ_LEVEL (CONFIG_NUM_IRQ_PRIO_LEVELS-1)
 #define _ARC_V2_WAKE_IRQ_LEVEL _ARC_V2_DEF_IRQ_LEVEL
 
-/*
- * INIT_IRQ_LOCK_KEY is init interrupt level setting of a thread.
- * It's configured by seti instruction when a thread starts to run
- *, i.e., z_thread_entry_wrapper and z_user_thread_entry_wrapper
- */
-#define _ARC_V2_INIT_IRQ_LOCK_KEY (0x10 | _ARC_V2_DEF_IRQ_LEVEL)
-
 #ifndef _ASMLANGUAGE
+
+extern void _firq_stack_setup(void);
+extern char _interrupt_stack[];
+
 /*
- * z_irq_setup
+ * _irq_setup
  *
  * Configures interrupt handling parameters
  */
-static ALWAYS_INLINE void z_irq_setup(void)
+static ALWAYS_INLINE void _irq_setup(void)
 {
-	u32_t aux_irq_ctrl_value = (
+	uint32_t aux_irq_ctrl_value = (
 		_ARC_V2_AUX_IRQ_CTRL_LOOP_REGS | /* save lp_xxx registers */
-#ifdef CONFIG_CODE_DENSITY
-		_ARC_V2_AUX_IRQ_CTRL_LP | /* save code density registers */
-#endif
 		_ARC_V2_AUX_IRQ_CTRL_BLINK     | /* save blink */
 		_ARC_V2_AUX_IRQ_CTRL_14_REGS     /* save r0 -> r13 (caller-saved) */
 	);
 
-	z_arc_cpu_sleep_mode = _ARC_V2_WAKE_IRQ_LEVEL;
+	nano_cpu_sleep_mode = _ARC_V2_WAKE_IRQ_LEVEL;
+	_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_CTRL, aux_irq_ctrl_value);
 
-#ifdef CONFIG_ARC_NORMAL_FIRMWARE
-	/* normal mode cannot write irq_ctrl, ignore it */
-	aux_irq_ctrl_value = aux_irq_ctrl_value;
-#else
-	z_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_CTRL, aux_irq_ctrl_value);
-#endif
+	_kernel.irq_stack = _interrupt_stack + CONFIG_ISR_STACK_SIZE;
+	_firq_stack_setup();
 }
 
 #endif /* _ASMLANGUAGE */
@@ -78,4 +70,4 @@ static ALWAYS_INLINE void z_irq_setup(void)
 }
 #endif
 
-#endif /* ZEPHYR_ARCH_ARC_INCLUDE_V2_IRQ_H_ */
+#endif /* _ARCV2_IRQ__H_ */

arch/arc/include/vector_table.h

@@ -1,7 +1,17 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
 /**
@@ -18,15 +28,20 @@
  * Refer to the ARCv2 manual for an explanation of the exceptions.
  */
 
-#ifndef ZEPHYR_ARCH_ARC_INCLUDE_VECTOR_TABLE_H_
-#define ZEPHYR_ARCH_ARC_INCLUDE_VECTOR_TABLE_H_
+#ifndef _VECTOR_TABLE__H_
+#define _VECTOR_TABLE__H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #define EXC_EV_TRAP	0x9
 
 #ifdef _ASMLANGUAGE
 
+#include <board.h>
 #include <toolchain.h>
-#include <linker/sections.h>
+#include <sections.h>
 
 GTEXT(__start)
 GTEXT(_VectorTable)
@@ -51,10 +66,6 @@ GTEXT(_isr_wrapper)
 
 #else
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 extern void __reset(void);
 extern void __memory_error(void);
 extern void __instruction_error(void);
@@ -70,10 +81,10 @@ extern void __ev_div_zero(void);
 extern void __ev_dc_error(void);
 extern void __ev_maligned(void);
 
+#endif /* _ASMLANGUAGE */
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* _ASMLANGUAGE */
-
-#endif /* ZEPHYR_ARCH_ARC_INCLUDE_VECTOR_TABLE_H_ */
+#endif /* _VECTOR_TABLE__H_ */

arch/arc/soc/em11d/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/arc/soc/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o