ci: integrate requirements into docs workflow.

Integrate into doc workflow.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.checkpatch.conf

@@ -5,6 +5,7 @@
 --min-conf-desc-length=1
 --typedefsfile=scripts/checkpatch/typedefsfile
 
+--ignore BRACES
 --ignore PRINTK_WITHOUT_KERN_LEVEL
 --ignore SPLIT_STRING
 --ignore VOLATILE

.clang-format

@@ -46,7 +46,6 @@ ForEachMacros:
   - 'SYS_DLIST_FOR_EACH_CONTAINER_SAFE'
   - 'SYS_DLIST_FOR_EACH_NODE'
   - 'SYS_DLIST_FOR_EACH_NODE_SAFE'
-  - 'SYS_SEM_LOCK'
   - 'SYS_SFLIST_FOR_EACH_CONTAINER'
   - 'SYS_SFLIST_FOR_EACH_CONTAINER_SAFE'
   - 'SYS_SFLIST_FOR_EACH_NODE'
@@ -111,4 +110,3 @@ WhitespaceSensitiveMacros:
   - LISTIFY
   - STRINGIFY
   - Z_STRINGIFY
-  - DT_FOREACH_PROP_ELEM_SEP

.github/SECURITY.md

@@ -8,11 +8,11 @@ updates:
   - The most recent release, and the release prior to that.
   - Active LTS releases.
 
-At this time, with the latest release of v4.0, the supported
+At this time, with the latest release of v3.6, the supported
 versions are:
 
-  - v4.0: Current release
-  - v3.7: Prior release and Current LTS
+  - v3.7: Current LTS
+  - v3.6: Prior release
   - v2.7: Prior LTS
 
 ## Reporting process

.github/dependabot.yml

@@ -1,13 +0,0 @@
-version: 2
-updates:
-  - package-ecosystem: "github-actions"
-    directory: "/"
-    schedule:
-      interval: "weekly"
-    commit-message:
-      prefix: "ci: github: "
-    labels: []
-    groups:
-      actions-deps:
-        patterns:
-          - "*"

.github/workflows/assigner.yml

@@ -24,7 +24,8 @@ jobs:
     steps:
     - name: Install Python dependencies
       run: |
-        pip install -U PyGithub>=1.55 west
+        sudo pip3 install -U setuptools wheel pip
+        pip3 install -U PyGithub>=1.55 west
 
     - name: Check out source code
       uses: actions/checkout@v4

.github/workflows/backport_issue_check.yml

@@ -25,7 +25,8 @@ jobs:
 
       - name: Install Python dependencies
         run: |
-          pip install -U pygithub
+          sudo pip3 install -U setuptools wheel pip
+          pip3 install -U pygithub
 
       - name: Run backport issue checker
         env:

.github/workflows/bsim-tests-publish.yaml

@@ -13,7 +13,7 @@ jobs:
 
     steps:
       - name: Download artifacts
-        uses: dawidd6/action-download-artifact@v8
+        uses: dawidd6/action-download-artifact@v6
         with:
           run_id: ${{ github.event.workflow_run.id }}
 

.github/workflows/bsim-tests.yaml

@@ -12,14 +12,12 @@ on:
       - "dts/*/nordic/**"
       - "tests/bluetooth/common/testlib/**"
       - "samples/bluetooth/**"
-      - "boards/native/**"
-      - "soc/native/**"
+      - "boards/posix/**"
+      - "soc/posix/**"
       - "arch/posix/**"
       - "include/zephyr/arch/posix/**"
       - "scripts/native_simulator/**"
       - "samples/net/sockets/echo_*/**"
-      - "modules/hal_nordic/**"
-      - "modules/mbedtls/**"
       - "modules/openthread/**"
       - "subsys/net/l2/openthread/**"
       - "include/zephyr/net/openthread.h"
@@ -38,7 +36,7 @@ jobs:
     runs-on:
       group: zephyr-runner-v2-linux-x64-4xlarge
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
       options: '--entrypoint /bin/bash'
     env:
       ZEPHYR_TOOLCHAIN_VARIANT: zephyr
@@ -78,7 +76,6 @@ jobs:
           git config --global user.email "bot@zephyrproject.org"
           git config --global user.name "Zephyr Bot"
           rm -fr ".git/rebase-apply"
-          rm -fr ".git/rebase-merge"
           git rebase origin/${BASE_REF}
           git clean -f -d
           git log  --pretty=oneline | head -n 10
@@ -98,16 +95,14 @@ jobs:
             .github/workflows/bsim-tests.yaml
             .github/workflows/bsim-tests-publish.yaml
             west.yml
-            boards/native/
-            soc/native/
+            boards/posix/
+            soc/posix/
             arch/posix/
             include/zephyr/arch/posix/
             scripts/native_simulator/
             tests/bsim/*
             boards/nordic/nrf5*/*dt*
             dts/*/nordic/
-            modules/mbedtls/**
-            modules/hal_nordic/**
 
       - name: Check if Bluethooth files changed
         uses: tj-actions/changed-files@v45
@@ -172,7 +167,7 @@ jobs:
 
       - name: Merge Test Results
         run: |
-          pip install junitparser junit2html
+          pip3 install junitparser junit2html
           junitparser merge --glob "./bsim_*/*bsim_results.*.xml" "./twister-out/twister.xml" junit.xml
           junit2html junit.xml junit.html
 

.github/workflows/bug_snapshot.yaml

@@ -25,7 +25,8 @@ jobs:
 
     - name: Install Python dependencies
       run: |
-        pip install -U pygithub
+        sudo pip3 install -U setuptools wheel pip
+        pip3 install -U pygithub
 
     - name: Snapshot bugs
       env:

.github/workflows/clang.yaml

@@ -0,0 +1,165 @@
+name: Build with Clang/LLVM
+
+on: pull_request_target
+
+concurrency:
+  group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
+  cancel-in-progress: true
+
+jobs:
+  clang-build:
+    if: github.repository_owner == 'zephyrproject-rtos'
+    runs-on:
+      group: zephyr-runner-v2-linux-x64-4xlarge
+    container:
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
+      options: '--entrypoint /bin/bash'
+    strategy:
+      fail-fast: false
+      matrix:
+        platform: ["native_sim"]
+    env:
+      CCACHE_DIR: /node-cache/ccache-zephyr
+      CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3"
+      CCACHE_REMOTE_ONLY: "true"
+      LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16
+      COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}
+      BASE_REF: ${{ github.base_ref }}
+    outputs:
+      report_needed: ${{ steps.twister.outputs.report_needed }}
+    steps:
+      - name: Apply container owner mismatch workaround
+        run: |
+          # FIXME: The owner UID of the GITHUB_WORKSPACE directory may not
+          #        match the container user UID because of the way GitHub
+          #        Actions runner is implemented. Remove this workaround when
+          #        GitHub comes up with a fundamental fix for this problem.
+          git config --global --add safe.directory ${GITHUB_WORKSPACE}
+
+      - name: Print cloud service information
+        run: |
+          echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}"
+          echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}"
+          echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}"
+
+      - name: Clone cached Zephyr repository
+        continue-on-error: true
+        run: |
+          git clone --shared /repo-cache/zephyrproject/zephyr .
+          git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY}
+
+      - name: Checkout
+        uses: actions/checkout@v4
+        with:
+          ref: ${{ github.event.pull_request.head.sha }}
+          fetch-depth: 0
+          persist-credentials: false
+
+      - name: Environment Setup
+        run: |
+          echo "$HOME/.local/bin" >> $GITHUB_PATH
+          git config --global user.email "bot@zephyrproject.org"
+          git config --global user.name "Zephyr Bot"
+          rm -fr ".git/rebase-apply"
+          git rebase origin/${BASE_REF}
+          git clean -f -d
+          git log  --pretty=oneline | head -n 10
+          west init -l . || true
+          west config --global update.narrow true
+          west config manifest.group-filter -- +ci,+optional
+          # In some cases modules are left in a state where they can't be
+          # updated (i.e. when we cancel a job and the builder is killed),
+          # So first retry to update, if that does not work, remove all modules
+          # and start over. (Workaround until we implement more robust module
+          # west caching).
+          west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west2.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject)
+
+          echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV
+
+      - name: Check Environment
+        run: |
+          cmake --version
+          ${LLVM_TOOLCHAIN_PATH}/bin/clang --version
+          gcc --version
+          ls -la
+
+      - name: Set up ccache
+        run: |
+          mkdir -p ${CCACHE_DIR}
+          ccache -M 10G
+          ccache -p
+          ccache -z -s -vv
+
+      - name: Update BabbleSim to manifest revision
+        run: |
+          export BSIM_VERSION=$( west list bsim -f {revision} )
+          echo "Manifest points to bsim sha $BSIM_VERSION"
+          cd /opt/bsim_west/bsim
+          git fetch -n origin ${BSIM_VERSION}
+          git -c advice.detachedHead=false checkout ${BSIM_VERSION}
+          west update
+          make everything -s -j 8
+
+      - name: Run Tests with Twister
+        id: twister
+        run: |
+          export ZEPHYR_BASE=${PWD}
+          export ZEPHYR_TOOLCHAIN_VARIANT=llvm
+
+          # check if we need to run a full twister or not based on files changed
+          python3 ./scripts/ci/test_plan.py --platform ${{ matrix.platform }} -c origin/${BASE_REF}..
+
+          # We can limit scope to just what has changed
+          if [ -s testplan.json ]; then
+            echo "report_needed=1" >> $GITHUB_OUTPUT
+            # Full twister but with options based on changes
+            ./scripts/twister --force-color --inline-logs -M -N -v --load-tests testplan.json --retry-failed 2
+          else
+            # if nothing is run, skip reporting step
+            echo "report_needed=0" >> $GITHUB_OUTPUT
+          fi
+
+      - name: Print ccache stats
+        if: always()
+        run: |
+          ccache -s -vv
+
+      - name: Upload Unit Test Results
+        if: always() && steps.twister.outputs.report_needed != 0
+        uses: actions/upload-artifact@v4
+        with:
+          name: Unit Test Results (Subset ${{ matrix.platform }})
+          path: twister-out/twister.xml
+
+  clang-build-results:
+    name: "Publish Unit Tests Results"
+    needs: clang-build
+    runs-on: ubuntu-22.04
+    if: (success() || failure() ) && needs.clang-build.outputs.report_needed != 0
+    steps:
+      - name: Download Artifacts
+        uses: actions/download-artifact@v4
+        with:
+          path: artifacts
+      - name: Merge Test Results
+        run: |
+          pip3 install junitparser junit2html
+          junitparser merge artifacts/*/twister.xml junit.xml
+          junit2html junit.xml junit-clang.html
+
+      - name: Upload Unit Test Results in HTML
+        if: always()
+        uses: actions/upload-artifact@v4
+        with:
+          name: HTML Unit Test Results
+          if-no-files-found: ignore
+          path: |
+            junit-clang.html
+
+      - name: Publish Unit Test Results
+        uses: EnricoMi/publish-unit-test-result-action@v2
+        if: always()
+        with:
+          check_name: Unit Test Results
+          files: "**/twister.xml"
+          comment_mode: off

.github/workflows/codecov.yaml

@@ -14,7 +14,7 @@ jobs:
     runs-on:
       group: zephyr-runner-v2-linux-x64-4xlarge
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
       options: '--entrypoint /bin/bash'
     strategy:
       fail-fast: false
@@ -34,7 +34,7 @@ jobs:
       CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3"
       CCACHE_REMOTE_ONLY: "true"
       # `--specs` is ignored because ccache is unable to resovle the toolchain specs file path.
-      CCACHE_IGNOREOPTIONS: '-specs=* --specs=*'
+      CCACHE_IGNOREOPTIONS: '--specs=*'
     steps:
       - name: Apply container owner mismatch workaround
         run: |
@@ -101,7 +101,7 @@ jobs:
           export ZEPHYR_BASE=${PWD}
           export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
           mkdir -p coverage/reports
-          pip install gcovr==6.0
+          pip3 install gcovr==6.0
           ./scripts/twister -E ${{matrix.normalized}}-testplan.json
           ls -la
           ./scripts/twister \
@@ -182,7 +182,7 @@ jobs:
       - name: Merge coverage files
         run: |
           pushd ./coverage/reports
-          pip install gcovr==6.0
+          pip3 install gcovr==6.0
           gcovr ${{ steps.get-coverage-files.outputs.mergefiles }}  --merge-mode-functions=separate --json merged.json
           gcovr ${{ steps.get-coverage-files.outputs.mergefiles }} --merge-mode-functions=separate --cobertura merged.xml
           popd
@@ -220,7 +220,7 @@ jobs:
 
       - name: Upload coverage to Codecov
         if: always()
-        uses: codecov/codecov-action@v5
+        uses: codecov/codecov-action@v4
         with:
           env_vars: OS,PYTHON
           fail_ci_if_error: false

.github/workflows/coding_guidelines.yml

@@ -21,15 +21,16 @@ jobs:
 
     - name: Install python dependencies
       run: |
-        pip install unidiff
-        pip install sh
+        pip3 install unidiff
+        pip3 install wheel
+        pip3 install sh
 
     - name: Install Packages
       run: |
         sudo apt-get update
         sudo apt-get install coccinelle
 
-    - name: Run Coding Guidelines Checks
+    - name: Run Coding Guildeines Checks
       continue-on-error: true
       id: coding_guidelines
       env:
@@ -39,8 +40,6 @@ jobs:
         git config --global user.email "actions@zephyrproject.org"
         git config --global user.name "Github Actions"
         git remote -v
-        rm -fr ".git/rebase-apply"
-        rm -fr ".git/rebase-merge"
         git rebase origin/${BASE_REF}
         git clean -f -d
         source zephyr-env.sh

.github/workflows/compliance.yml

@@ -23,23 +23,6 @@ jobs:
         ref: ${{ github.event.pull_request.head.sha }}
         fetch-depth: 0
 
-    - name: Rebase onto the target branch
-      env:
-        BASE_REF: ${{ github.base_ref }}
-      run: |
-        git config --global user.email "you@example.com"
-        git config --global user.name "Your Name"
-        git remote -v
-        # Ensure there's no merge commits in the PR
-        [[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \
-        (echo "::error ::Merge commits not allowed, rebase instead";false)
-        rm -fr ".git/rebase-apply"
-        rm -fr ".git/rebase-merge"
-        git rebase origin/${BASE_REF}
-        git clean -f -d
-        # debug
-        git log  --pretty=oneline | head -n 10
-
     - name: Set up Python
       uses: actions/setup-python@v5
       with:
@@ -53,11 +36,25 @@ jobs:
 
     - name: Install python dependencies
       run: |
-        pip install -r scripts/requirements-compliance.txt
-        pip install west
+        pip3 install setuptools
+        pip3 install wheel
+        pip3 install python-magic lxml junitparser gitlint pylint pykwalify yamllint clang-format unidiff sphinx-lint
+        pip3 install west
 
     - name: west setup
+      env:
+        BASE_REF: ${{ github.base_ref }}
       run: |
+        git config --global user.email "you@example.com"
+        git config --global user.name "Your Name"
+        git remote -v
+        # Ensure there's no merge commits in the PR
+        [[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \
+        (echo "::error ::Merge commits not allowed, rebase instead";false)
+        git rebase origin/${BASE_REF}
+        git clean -f -d
+        # debug
+        git log  --pretty=oneline | head -n 10
         west init -l . || true
         west config manifest.group-filter -- +ci,-optional
         west update -o=--depth=1 -n 2>&1 1> west.update.log || west update -o=--depth=1 -n 2>&1 1> west.update2.log
@@ -82,7 +79,7 @@ jobs:
         git log  --pretty=oneline | head -n 10
         # Increase rename limit to allow for large PRs
         git config diff.renameLimit 10000
-        ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -e SysbuildKconfigBasic -e ClangFormat \
+        ./scripts/ci/check_compliance.py --annotate -e KconfigBasic \
         -c origin/${BASE_REF}..
 
     - name: upload-results

.github/workflows/daily_test_version.yml

@@ -25,7 +25,7 @@ jobs:
 
     - name: install-pip
       run: |
-        pip install gitpython
+        pip3 install gitpython
 
     - name: checkout
       uses: actions/checkout@v4

.github/workflows/devicetree_checks.yml

@@ -26,7 +26,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-22.04, macos-14, windows-2022]
     steps:
     - name: checkout
@@ -62,7 +62,8 @@ jobs:
           ${{ runner.os }}-pip-${{ matrix.python-version }}
     - name: install python dependencies
       run: |
-        pip install pytest pyyaml tox
+        pip3 install wheel
+        pip3 install pytest pyyaml tox
     - name: run tox
       working-directory: scripts/dts/python-devicetree
       run: |

.github/workflows/do_not_merge.yml

@@ -6,15 +6,14 @@ on:
 
 jobs:
   do-not-merge:
+    if: ${{ contains(github.event.*.labels.*.name, 'DNM') ||
+            contains(github.event.*.labels.*.name, 'TSC') ||
+            contains(github.event.*.labels.*.name, 'Architecture Review') ||
+            contains(github.event.*.labels.*.name, 'dev-review') }}
     name: Prevent Merging
     runs-on: ubuntu-22.04
     steps:
       - name: Check for label
-        if: ${{ contains(github.event.*.labels.*.name, 'DNM') ||
-                contains(github.event.*.labels.*.name, 'DNM (manifest)') ||
-                contains(github.event.*.labels.*.name, 'TSC') ||
-                contains(github.event.*.labels.*.name, 'Architecture Review') ||
-                contains(github.event.*.labels.*.name, 'dev-review') }}
         run: |
           echo "Pull request is labeled as 'DNM', 'TSC', 'Architecture Review' or 'dev-review'."
           echo "This workflow fails so that the pull request cannot be merged."

.github/workflows/doc-build.yml

@@ -18,12 +18,14 @@ env:
   # so we fetch that through pip.
   CMAKE_VERSION: 3.20.5
   DOXYGEN_VERSION: 1.12.0
-  JOB_COUNT: 4
+  # Job count is set to 2 less than the vCPU count of 16 because the total available RAM is 32GiB
+  # and each sphinx-build process may use more than 2GiB of RAM.
+  JOB_COUNT: 14
 
 jobs:
   doc-file-check:
     name: Check for doc changes
-    runs-on: ubuntu-24.04
+    runs-on: ubuntu-22.04
     if: >
       github.repository_owner == 'zephyrproject-rtos'
     outputs:
@@ -40,7 +42,6 @@ jobs:
       with:
         files: |
           doc/
-          boards/**/doc/
           **.rst
           include/
           kernel/include/kernel_arch_interface.h
@@ -61,7 +62,7 @@ jobs:
     if: >
       github.repository_owner == 'zephyrproject-rtos' &&
         ( needs.doc-file-check.outputs.file_check == 'true' || github.event_name != 'pull_request' )
-    runs-on: ubuntu-24.04
+    runs-on: ubuntu-22.04
     timeout-minutes: 90
     concurrency:
       group: doc-build-html-${{ github.ref }}
@@ -82,7 +83,6 @@ jobs:
       with:
         ref: ${{ github.event.pull_request.head.sha }}
         fetch-depth: 0
-        path: zephyr
 
     - name: Rebase
       if: github.event_name == 'pull_request'
@@ -90,31 +90,44 @@ jobs:
       env:
         BASE_REF: ${{ github.base_ref }}
         PR_HEAD: ${{ github.event.pull_request.head.sha }}
-      working-directory: zephyr
       run: |
         git config --global user.email "actions@zephyrproject.org"
         git config --global user.name "Github Actions"
-        rm -fr ".git/rebase-apply"
-        rm -fr ".git/rebase-merge"
         git rebase origin/${BASE_REF}
         git clean -f -d
         git log --graph --oneline HEAD...${PR_HEAD}
 
-    - name: Setup Zephyr project
-      uses: zephyrproject-rtos/action-zephyr-setup@v1
+    - name: cache-pip
+      uses: actions/cache@v4
       with:
-        app-path: zephyr
-        toolchains: 'all'
+        path: ~/.cache/pip
+        key: pip-${{ hashFiles('doc/requirements.txt') }}
 
     - name: install-pip
-      working-directory: zephyr
       run: |
-        pip install -r doc/requirements.txt
-        pip install coverxygen
+        sudo pip3 install -U setuptools wheel pip
+        pip3 install -r doc/requirements.txt
+        pip3 install west==${WEST_VERSION}
+        pip3 install cmake==${CMAKE_VERSION}
+        pip3 install coverxygen
+        pip3 install mlx.traceability strictdoc
+
+    - name: west setup
+      run: |
+        west init -l .
+
+    - name: prcoess requirements
+      run: |
+        west update reqmgmt
+        pushd ../tools/reqmgmt
+        strictdoc export . --formats json
+        popd
+        cp ../tools/reqmgmt/output/json/index.json doc/requirements/requirements.json
+        python3 doc/requirements/create_req.py --json doc/requirements/requirements.json  --output doc/requirements/requirements.dox
+
 
     - name: build-docs
       shell: bash
-      working-directory: zephyr
       run: |
         if [[ "$GITHUB_REF" =~ "refs/tags/v" ]]; then
           DOC_TAG="release"
@@ -133,30 +146,16 @@ jobs:
         SPHINXOPTS_EXTRA="-q -t publish" \
         make -C doc ${DOC_TARGET}
 
-        # API documentation coverage
-        python3 -m coverxygen --xml-dir  doc/_build/html/doxygen/xml/ --src-dir include/ --output doc-coverage.info
-        # deprecated page causing issues
-        lcov --remove doc-coverage.info \*/deprecated > new.info
-        genhtml --no-function-coverage --no-branch-coverage new.info -o coverage-report
-
     - name: compress-docs
-      working-directory: zephyr
       run: |
-        tar --use-compress-program="xz -T0" -cf html-output.tar.xz --exclude html/_sources --exclude html/doxygen/xml --directory=doc/_build html
+        tar --use-compress-program="xz -T0" -cf html-output.tar.xz --directory=doc/_build html
         tar --use-compress-program="xz -T0" -cf api-output.tar.xz --directory=doc/_build html/doxygen/html
-        tar --use-compress-program="xz -T0" -cf api-coverage.tar.xz coverage-report
 
     - name: upload-build
       uses: actions/upload-artifact@v4
       with:
         name: html-output
-        path: zephyr/html-output.tar.xz
-
-    - name: upload-api-coverage
-      uses: actions/upload-artifact@v4
-      with:
-        name: api-coverage
-        path: zephyr/api-coverage.tar.xz
+        path: html-output.tar.xz
 
     - name: process-pr
       if: github.event_name == 'pull_request'
@@ -219,9 +218,10 @@ jobs:
 
     - name: install-pip
       run: |
-        pip install -r doc/requirements.txt
-        pip install west==${WEST_VERSION}
-        pip install cmake==${CMAKE_VERSION}
+        pip3 install -U setuptools wheel pip
+        pip3 install -r doc/requirements.txt
+        pip3 install west==${WEST_VERSION}
+        pip3 install cmake==${CMAKE_VERSION}
 
     - name: west setup
       run: |

.github/workflows/doc-publish-pr.yml

@@ -21,24 +21,16 @@ jobs:
 
     steps:
     - name: Download artifacts
-      id: download-artifacts
-      uses: dawidd6/action-download-artifact@v8
+      uses: dawidd6/action-download-artifact@v6
       with:
         workflow: doc-build.yml
         run_id: ${{ github.event.workflow_run.id }}
-        if_no_artifact_found: ignore
 
     - name: Load PR number
-      if: steps.download-artifacts.outputs.found_artifact == 'true'
-      uses: actions/github-script@v7
-      with:
-        script: |
-          let fs = require("fs");
-          let pr_number = Number(fs.readFileSync("./pr_num/pr_num"));
-          core.exportVariable("PR_NUM", pr_number);
+      run: |
+        echo "PR_NUM=$(<pr_num/pr_num)" >> $GITHUB_ENV
 
     - name: Check PR number
-      if: steps.download-artifacts.outputs.found_artifact == 'true'
       id: check-pr
       uses: carpentries/actions/check-valid-pr@v0.14.0
       with:
@@ -46,15 +38,12 @@ jobs:
         sha: ${{ github.event.workflow_run.head_sha }}
 
     - name: Validate PR number
-      if: |
-        steps.download-artifacts.outputs.found_artifact == 'true' &&
-        steps.check-pr.outputs.VALID != 'true'
+      if: steps.check-pr.outputs.VALID != 'true'
       run: |
         echo "ABORT: PR number validation failed!"
         exit 1
 
     - name: Uncompress HTML docs
-      if: steps.download-artifacts.outputs.found_artifact == 'true'
       run: |
         tar xf html-output/html-output.tar.xz -C html-output
         if [ -f api-coverage/api-coverage.tar.xz ]; then
@@ -62,7 +51,6 @@ jobs:
         fi
 
     - name: Configure AWS Credentials
-      if: steps.download-artifacts.outputs.found_artifact == 'true'
       uses: aws-actions/configure-aws-credentials@v4
       with:
         aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_PR_ACCESS_KEY_ID }}
@@ -70,7 +58,6 @@ jobs:
         aws-region: us-east-1
 
     - name: Upload to AWS S3
-      if: steps.download-artifacts.outputs.found_artifact == 'true'
       env:
         HEAD_BRANCH: ${{ github.event.workflow_run.head_branch }}
       run: |

.github/workflows/doc-publish.yml

@@ -24,7 +24,7 @@ jobs:
 
     steps:
     - name: Download artifacts
-      uses: dawidd6/action-download-artifact@v8
+      uses: dawidd6/action-download-artifact@v6
       with:
         workflow: doc-build.yml
         run_id: ${{ github.event.workflow_run.id }}

.github/workflows/errno.yml

@@ -10,7 +10,7 @@ jobs:
   check-errno:
     runs-on: ubuntu-22.04
     container:
-      image: ghcr.io/zephyrproject-rtos/ci:v0.27.4
+      image: ghcr.io/zephyrproject-rtos/ci:v0.26.13
 
     steps:
       - name: Apply container owner mismatch workaround

.github/workflows/footprint-tracking.yml

@@ -26,11 +26,8 @@ jobs:
       group: zephyr-runner-v2-linux-x64-4xlarge
     if: github.repository_owner == 'zephyrproject-rtos'
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
       options: '--entrypoint /bin/bash'
-    defaults:
-      run:
-        shell: bash
     strategy:
       fail-fast: false
     env:
@@ -58,7 +55,7 @@ jobs:
         run: |
           sudo apt-get update
           sudo apt-get install -y python3-venv
-          pip install -U gitpython
+          sudo pip3 install -U setuptools wheel pip gitpython
 
       - name: checkout
         uses: actions/checkout@v4
@@ -94,35 +91,5 @@ jobs:
         run: |
           python3 -m venv .venv
           . .venv/bin/activate
-          pip install awscli
+          pip3 install awscli
           aws s3 sync  --quiet footprint_data/ s3://testing.zephyrproject.org/footprint_data/
-
-      - name: Transform Footprint data to Twister JSON reports
-        run: |
-          shopt -s globstar
-          export ZEPHYR_BASE=${PWD}
-          python3 ./scripts/footprint/pack_as_twister.py -vvv \
-            --plan ./scripts/footprint/plan.txt \
-            --test-name='name.feature' \
-            ./footprint_data/**/
-
-      - name: Upload to ElasticSearch
-        env:
-          ELASTICSEARCH_KEY: ${{ secrets.ELASTICSEARCH_KEY }}
-          ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443"
-          ELASTICSEARCH_INDEX: ${{ vars.FOOTPRINT_TRACKING_INDEX }}
-        run: |
-          shopt -s globstar
-          pip install -U elasticsearch
-          run_date=`date --iso-8601=minutes`
-          python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \
-            --flatten footprint \
-            --flatten-list-names "{'children':'name'}" \
-            --transform "{ 'footprint_name': '^(?P<footprint_area>([^\/]+\/){0,2})(?P<footprint_path>([^\/]*\/)*)(?P<footprint_symbol>[^\/]*)$' }" \
-            --run-id "${{ github.run_id }}" \
-            --run-attempt "${{ github.run_attempt }}" \
-            --run-workflow "footprint-tracking:${{ github.event_name }}" \
-            --run-branch "${{ github.ref_name }}" \
-            -i ${ELASTICSEARCH_INDEX} \
-            ./footprint_data/**/twister_footprint.json
-        #

.github/workflows/hello_world_multiplatform.yaml

@@ -12,7 +12,8 @@ on:
       - v*-branch
       - collab-*
     paths:
-      - 'scripts/**'
+      - 'scripts/build/**'
+      - 'scripts/requirements*.txt'
       - '.github/workflows/hello_world_multiplatform.yaml'
       - 'SDK_VERSION'
 
@@ -44,8 +45,6 @@ jobs:
         run: |
           git config --global user.email "actions@zephyrproject.org"
           git config --global user.name "Github Actions"
-          rm -fr ".git/rebase-apply"
-          rm -fr ".git/rebase-merge"
           git rebase origin/${BASE_REF}
           git clean -f -d
           git log --graph --oneline HEAD...${PR_HEAD}
@@ -70,7 +69,7 @@ jobs:
           elif [ "${{ runner.os }}" = "Windows" ]; then
             EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O/tmp/twister-out"
           fi
-          ./scripts/twister --runtime-artifact-cleanup --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS
+          ./scripts/twister --force-color --inline-logs -T samples/hello_world -v $EXTRA_TWISTER_FLAGS
 
       - name: Upload artifacts
         if: failure()
@@ -79,4 +78,3 @@ jobs:
           if-no-files-found: ignore
           path:
             zephyr/twister-out/*/samples/hello_world/sample.basic.helloworld/build.log
-            zephyr/twister-out/*/samples/cpp/hello_world/sample.cpp.helloworld/build.log

.github/workflows/manifest.yml

@@ -20,13 +20,13 @@ jobs:
           BASE_REF: ${{ github.base_ref }}
         working-directory: zephyrproject/zephyr
         run: |
-          pip install west
+          pip3 install west
           git config --global user.email "you@example.com"
           git config --global user.name "Your Name"
           west init -l . || true
 
       - name: Manifest
-        uses: zephyrproject-rtos/action-manifest@v1.7.0
+        uses: zephyrproject-rtos/action-manifest@v1.3.1
         with:
           github-token: ${{ secrets.ZB_GITHUB_TOKEN }}
           manifest-path: 'west.yml'
@@ -36,4 +36,4 @@ jobs:
           label-prefix: 'manifest-'
           verbosity-level: '1'
           labels: 'manifest'
-          dnm-labels: 'DNM (manifest)'
+          dnm-labels: 'DNM'

.github/workflows/pylib_tests.yml

@@ -25,7 +25,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-22.04]
     steps:
     - name: checkout
@@ -44,7 +44,7 @@ jobs:
           ${{ runner.os }}-pip-${{ matrix.python-version }}
     - name: install-packages
       run: |
-        pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt
+        pip3 install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt
     - name: Run pytest for build_helpers
       env:
         ZEPHYR_BASE: ./

.github/workflows/release.yml

@@ -21,7 +21,7 @@ jobs:
           echo "TRIMMED_VERSION=${GITHUB_REF#refs/tags/v}" >> $GITHUB_OUTPUT
 
       - name: REUSE Compliance Check
-        uses: fsfe/reuse-action@v5
+        uses: fsfe/reuse-action@v4
         with:
           args: spdx -o zephyr-${{ steps.get_version.outputs.VERSION }}.spdx
 

.github/workflows/scripts_tests.yml

@@ -25,7 +25,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-20.04]
     steps:
       - name: checkout
@@ -42,8 +42,6 @@ jobs:
         run: |
           git config --global user.email "actions@zephyrproject.org"
           git config --global user.name "Github Actions"
-          rm -fr ".git/rebase-apply"
-          rm -fr ".git/rebase-merge"
           git rebase origin/${BASE_REF}
           git clean -f -d
           git log --graph --oneline HEAD...${PR_HEAD}
@@ -64,7 +62,7 @@ jobs:
 
       - name: install-packages
         run: |
-          pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt
+          pip3 install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt
 
       - name: Run pytest
         env:

.github/workflows/stats_merged_prs.yml

@@ -20,5 +20,5 @@ jobs:
           ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443"
           PR_STAT_ES_INDEX: ${{ vars.PR_STAT_ES_INDEX }}
         run: |
-          pip install pygithub elasticsearch
+          pip3 install pygithub elasticsearch
           python3 ./scripts/ci/stats/merged_prs.py --pull-request ${{ github.event.pull_request.number }} --repo ${{ github.repository }}

.github/workflows/twister-prep.yaml

@@ -1,147 +0,0 @@
-name: Prepare For a Twister Run
-
-on:
-  workflow_call:
-    outputs:
-      subset:
-        description: subset
-        value: ${{ jobs.prep_push.outputs.subset != '' && jobs.prep_push.outputs.subset ||  jobs.prep_pr.outputs.subset }}
-      size:
-        description: size
-        value: ${{ jobs.prep_push.outputs.size != '' && jobs.prep_push.outputs.size || jobs.prep_pr.outputs.size }}
-      fullrun:
-        description: fullrun
-        value: ${{ jobs.prep_push.outputs.fullrun != '' && jobs.prep_push.outputs.fullrun || jobs.prep_pr.outputs.size }}
-
-jobs:
-  prep_pr:
-    if: github.repository_owner == 'zephyrproject-rtos' && github.event_name == 'pull_request_target'
-    runs-on:
-      group: zephyr-runner-v2-linux-x64-4xlarge
-    container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
-      options: '--entrypoint /bin/bash'
-    outputs:
-      subset: ${{ steps.output-services.outputs.subset }}
-      size: ${{ steps.output-services.outputs.size }}
-      fullrun: ${{ steps.output-services.outputs.fullrun }}
-    env:
-      MATRIX_SIZE: 10
-      PUSH_MATRIX_SIZE: 20
-      WEEKLY_MATRIX_SIZE: 200
-      BSIM_OUT_PATH: /opt/bsim/
-      BSIM_COMPONENTS_PATH: /opt/bsim/components
-      TESTS_PER_BUILDER: 900
-      COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}
-      BASE_REF: ${{ github.base_ref }}
-    steps:
-      - name: Apply container owner mismatch workaround
-        run: |
-          # FIXME: The owner UID of the GITHUB_WORKSPACE directory may not
-          #        match the container user UID because of the way GitHub
-          #        Actions runner is implemented. Remove this workaround when
-          #        GitHub comes up with a fundamental fix for this problem.
-          git config --global --add safe.directory ${GITHUB_WORKSPACE}
-
-      - name: Print cloud service information
-        run: |
-          echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}"
-          echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}"
-          echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}"
-
-      - name: Clone cached Zephyr repository
-        continue-on-error: true
-        run: |
-          git clone --shared /repo-cache/zephyrproject/zephyr .
-          git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY}
-
-      - name: Checkout
-        uses: actions/checkout@v4
-        with:
-          ref: ${{ github.event.pull_request.head.sha }}
-          fetch-depth: 0
-          persist-credentials: false
-
-      - name: Environment Setup
-        run: |
-          git config --global user.email "bot@zephyrproject.org"
-          git config --global user.name "Zephyr Bot"
-          rm -fr ".git/rebase-apply"
-          rm -fr ".git/rebase-merge"
-          git rebase origin/${BASE_REF}
-          git clean -f -d
-          git log  --pretty=oneline | head -n 10
-          west init -l . || true
-          west config manifest.group-filter -- +ci,+optional
-          west config --global update.narrow true
-          west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject)
-          west forall -c 'git reset --hard HEAD'
-
-          echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV
-
-      - name: Generate Test Plan with Twister
-        id: test-plan
-        run: |
-          export ZEPHYR_BASE=${PWD}
-          export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
-          python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --no-detailed-test-id --pull-request -t $TESTS_PER_BUILDER
-          if [ -s .testplan ]; then
-            cat .testplan >> $GITHUB_ENV
-          else
-            echo "TWISTER_NODES=${MATRIX_SIZE}" >> $GITHUB_ENV
-          fi
-          rm -f testplan.json .testplan
-
-      - name: Determine matrix size
-        id: output-services
-        run: |
-          if [ -n "${TWISTER_NODES}" ]; then
-            subset="[$(seq -s',' 1 ${TWISTER_NODES})]"
-          else
-            subset="[$(seq -s',' 1 ${MATRIX_SIZE})]"
-          fi
-          size=${TWISTER_NODES}
-
-          echo "subset=${subset}" >> $GITHUB_OUTPUT
-          echo "size=${size}" >> $GITHUB_OUTPUT
-          echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT
-
-  prep_push:
-    if: github.repository_owner == 'zephyrproject-rtos' && (github.event_name == 'push' || github.event_name == 'schedule')
-    runs-on: ubuntu-22.04
-    outputs:
-      subset: ${{ steps.output-services.outputs.subset }}
-      size: ${{ steps.output-services.outputs.size }}
-      fullrun: ${{ steps.output-services.outputs.fullrun }}
-    env:
-      MATRIX_SIZE: 10
-      PUSH_MATRIX_SIZE: 20
-      WEEKLY_MATRIX_SIZE: 200
-      BSIM_OUT_PATH: /opt/bsim/
-      BSIM_COMPONENTS_PATH: /opt/bsim/components
-      TESTS_PER_BUILDER: 900
-      COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}
-      BASE_REF: ${{ github.base_ref }}
-    steps:
-      - name: Print cloud service information
-        run: |
-          echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}"
-          echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}"
-          echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}"
-
-      - name: Determine matrix size
-        id: output-services
-        run: |
-          if [ "${{github.event_name}}" = "push" ]; then
-            subset="[$(seq -s',' 1 ${PUSH_MATRIX_SIZE})]"
-            size=${MATRIX_SIZE}
-          elif [ "${{github.event_name}}" = "schedule" -a "${{github.repository}}" = "zephyrproject-rtos/zephyr" ]; then
-            subset="[$(seq -s',' 1 ${WEEKLY_MATRIX_SIZE})]"
-            size=${WEEKLY_MATRIX_SIZE}
-          else
-            size=0
-          fi
-
-          echo "subset=${subset}" >> $GITHUB_OUTPUT
-          echo "size=${size}" >> $GITHUB_OUTPUT
-          echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT

.github/workflows/twister-publish.yaml

@@ -1,53 +0,0 @@
-name: Publish Twister Test Results
-
-on:
-  workflow_run:
-    workflows: ["Run tests with twister"]
-    branches:
-      - main
-    types:
-      - completed
-
-jobs:
-  upload-to-elasticsearch:
-    if: |
-      github.repository == 'zephyrproject-rtos/zephyr' &&
-      github.event.workflow_run.event != 'pull_request_target'
-    env:
-      ELASTICSEARCH_KEY: ${{ secrets.ELASTICSEARCH_KEY }}
-      ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443"
-    runs-on: ubuntu-22.04
-    steps:
-      # Needed for elasticearch and upload script
-      - name: Checkout
-        uses: actions/checkout@v4
-        with:
-          fetch-depth: 0
-          persist-credentials: false
-
-      - name: Download Artifacts
-        id: download-artifacts
-        uses: dawidd6/action-download-artifact@v8
-        with:
-          path: artifacts
-          workflow: twister.yml
-          run_id: ${{ github.event.workflow_run.id }}
-          if_no_artifact_found: ignore
-
-      - name: Upload to elasticsearch
-        if: steps.download-artifacts.outputs.found_artifact == 'true'
-        run: |
-          pip install elasticsearch
-          # set run date on upload to get consistent and unified data across the matrix.
-          run_date=`date --iso-8601=minutes`
-          if [ "${{github.event.workflow_run.event}}" = "push" ]; then
-            python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \
-            --run-attempt ${{github.run_attempt}} \
-            --run-branch ${{github.ref_name}} \
-            --index zephyr-main-ci-push-1 artifacts/*/*/twister.json
-          elif [ "${{github.event.workflow_run.event}}" = "schedule" ]; then
-            python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \
-            --run-attempt ${{github.run_attempt}} \
-            --run-branch ${{github.ref_name}} \
-            --index zephyr-main-ci-weekly-1 artifacts/*/*/twister.json
-          fi

.github/workflows/twister.yaml

@@ -12,8 +12,8 @@ on:
       - v*-branch
       - collab-*
   schedule:
-    # Run at 17:00 UTC on every Saturday
-    - cron: '0 17 * * 6'
+    # Run at 03:00 UTC on every Sunday
+    - cron: '0 3 * * 0'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
@@ -21,7 +21,108 @@ concurrency:
 
 jobs:
   twister-build-prep:
-    uses: ./.github/workflows/twister-prep.yaml
+    if: github.repository_owner == 'zephyrproject-rtos'
+    runs-on:
+      group: zephyr-runner-v2-linux-x64-4xlarge
+    container:
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
+      options: '--entrypoint /bin/bash'
+    outputs:
+      subset: ${{ steps.output-services.outputs.subset }}
+      size: ${{ steps.output-services.outputs.size }}
+      fullrun: ${{ steps.output-services.outputs.fullrun }}
+    env:
+      MATRIX_SIZE: 10
+      PUSH_MATRIX_SIZE: 20
+      DAILY_MATRIX_SIZE: 80
+      BSIM_OUT_PATH: /opt/bsim/
+      BSIM_COMPONENTS_PATH: /opt/bsim/components
+      TESTS_PER_BUILDER: 700
+      COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}
+      BASE_REF: ${{ github.base_ref }}
+    steps:
+      - name: Apply container owner mismatch workaround
+        run: |
+          # FIXME: The owner UID of the GITHUB_WORKSPACE directory may not
+          #        match the container user UID because of the way GitHub
+          #        Actions runner is implemented. Remove this workaround when
+          #        GitHub comes up with a fundamental fix for this problem.
+          git config --global --add safe.directory ${GITHUB_WORKSPACE}
+
+      - name: Print cloud service information
+        run: |
+          echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}"
+          echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}"
+          echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}"
+
+      - name: Clone cached Zephyr repository
+        if: github.event_name == 'pull_request_target'
+        continue-on-error: true
+        run: |
+          git clone --shared /repo-cache/zephyrproject/zephyr .
+          git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY}
+
+      - name: Checkout
+        if: github.event_name == 'pull_request_target'
+        uses: actions/checkout@v4
+        with:
+          ref: ${{ github.event.pull_request.head.sha }}
+          fetch-depth: 0
+          persist-credentials: false
+
+      - name: Environment Setup
+        if: github.event_name == 'pull_request_target'
+        run: |
+          git config --global user.email "bot@zephyrproject.org"
+          git config --global user.name "Zephyr Bot"
+          rm -fr ".git/rebase-apply"
+          git rebase origin/${BASE_REF}
+          git clean -f -d
+          git log  --pretty=oneline | head -n 10
+          west init -l . || true
+          west config manifest.group-filter -- +ci,+optional
+          west config --global update.narrow true
+          west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject)
+          west forall -c 'git reset --hard HEAD'
+
+          echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV
+
+      - name: Generate Test Plan with Twister
+        if: github.event_name == 'pull_request_target'
+        id: test-plan
+        run: |
+          export ZEPHYR_BASE=${PWD}
+          export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
+          python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --pull-request -t $TESTS_PER_BUILDER
+          if [ -s .testplan ]; then
+            cat .testplan >> $GITHUB_ENV
+          else
+            echo "TWISTER_NODES=${MATRIX_SIZE}" >> $GITHUB_ENV
+          fi
+          rm -f testplan.json .testplan
+
+      - name: Determine matrix size
+        id: output-services
+        run: |
+          if [ "${{github.event_name}}" = "pull_request_target" ]; then
+            if [ -n "${TWISTER_NODES}" ]; then
+              subset="[$(seq -s',' 1 ${TWISTER_NODES})]"
+            else
+              subset="[$(seq -s',' 1 ${MATRIX_SIZE})]"
+            fi
+            size=${TWISTER_NODES}
+          elif [ "${{github.event_name}}" = "push" ]; then
+            subset="[$(seq -s',' 1 ${PUSH_MATRIX_SIZE})]"
+            size=${MATRIX_SIZE}
+          elif [ "${{github.event_name}}" = "schedule" -a "${{github.repository}}" = "zephyrproject-rtos/zephyr" ]; then
+            subset="[$(seq -s',' 1 ${DAILY_MATRIX_SIZE})]"
+            size=${DAILY_MATRIX_SIZE}
+          else
+            size=0
+          fi
+          echo "subset=${subset}" >> $GITHUB_OUTPUT
+          echo "size=${size}" >> $GITHUB_OUTPUT
+          echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT
 
   twister-build:
     runs-on:
@@ -29,7 +130,7 @@ jobs:
     needs: twister-build-prep
     if: needs.twister-build-prep.outputs.size != 0
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
       options: '--entrypoint /bin/bash'
     strategy:
       fail-fast: false
@@ -41,16 +142,15 @@ jobs:
       CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3"
       CCACHE_REMOTE_ONLY: "true"
       # `--specs` is ignored because ccache is unable to resolve the toolchain specs file path.
-      CCACHE_IGNOREOPTIONS: '-specs=* --specs=*'
+      CCACHE_IGNOREOPTIONS: '--specs=*'
       BSIM_OUT_PATH: /opt/bsim/
       BSIM_COMPONENTS_PATH: /opt/bsim/components
-      TWISTER_COMMON: '--no-detailed-test-id --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 '
-      WEEKLY_OPTIONS: ' -M --build-only --all --show-footprint --report-filtered'
+      TWISTER_COMMON: ' --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 '
+      DAILY_OPTIONS: ' -M --build-only --all --show-footprint'
       PR_OPTIONS: ' --clobber-output --integration'
-      PUSH_OPTIONS: ' --clobber-output -M --show-footprint --report-filtered'
+      PUSH_OPTIONS: ' --clobber-output -M --show-footprint'
       COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}
       BASE_REF: ${{ github.base_ref }}
-      LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16
     steps:
       - name: Print cloud service information
         run: |
@@ -85,7 +185,6 @@ jobs:
             git config --global user.email "bot@zephyrproject.org"
             git config --global user.name "Zephyr Builder"
             rm -fr ".git/rebase-apply"
-            rm -fr ".git/rebase-merge"
             git rebase origin/${BASE_REF}
             git clean -f -d
             git log  --pretty=oneline | head -n 10
@@ -131,7 +230,6 @@ jobs:
 
       - if: github.event_name == 'push'
         name: Run Tests with Twister (Push)
-        id: run_twister
         run: |
           export ZEPHYR_BASE=${PWD}
           export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
@@ -145,12 +243,11 @@ jobs:
 
       - if: github.event_name == 'pull_request_target'
         name: Run Tests with Twister (Pull Request)
-        id: run_twister_pr
         run: |
           rm -f testplan.json
           export ZEPHYR_BASE=${PWD}
           export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
-          python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --pull-request --no-detailed-test-id
+          python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --pull-request
           ./scripts/twister --subset ${{matrix.subset}}/${{ strategy.job-total }} --load-tests testplan.json ${TWISTER_COMMON} ${PR_OPTIONS}
           if [ "${{matrix.subset}}" = "1" -a ${{needs.twister-build-prep.outputs.fullrun}} = 'True' ]; then
             ./scripts/zephyr_module.py --twister-out module_tests.args
@@ -160,16 +257,15 @@ jobs:
           fi
 
       - if: github.event_name == 'schedule'
-        name: Run Tests with Twister (Weekly)
-        id: run_twister_sched
+        name: Run Tests with Twister (Daily)
         run: |
           export ZEPHYR_BASE=${PWD}
           export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
-          ./scripts/twister --subset ${{matrix.subset}}/${{ strategy.job-total }} ${TWISTER_COMMON} ${WEEKLY_OPTIONS}
+          ./scripts/twister --subset ${{matrix.subset}}/${{ strategy.job-total }} ${TWISTER_COMMON} ${DAILY_OPTIONS}
           if [ "${{matrix.subset}}" = "1" ]; then
             ./scripts/zephyr_module.py --twister-out module_tests.args
             if [ -s module_tests.args ]; then
-              ./scripts/twister +module_tests.args --outdir module_tests ${TWISTER_COMMON} ${WEEKLY_OPTIONS}
+              ./scripts/twister +module_tests.args --outdir module_tests ${TWISTER_COMMON} ${DAILY_OPTIONS}
             fi
           fi
 
@@ -198,7 +294,7 @@ jobs:
           timestamp="$(date)"
           version="$(git describe --abbrev=12 --always)"
           echo -e "# Generated at $timestamp ($version)\n" > $FREEZE_FILE
-          pip freeze | tee -a $FREEZE_FILE
+          pip3 freeze | tee -a $FREEZE_FILE
 
       - if: matrix.subset == 1 && github.event_name == 'push'
         name: Upload the list of Python packages
@@ -210,18 +306,20 @@ jobs:
 
   twister-test-results:
     name: "Publish Unit Tests Results"
-    needs:
-      - twister-build
+    env:
+      ELASTICSEARCH_KEY: ${{ secrets.ELASTICSEARCH_KEY }}
+      ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443"
+    needs: twister-build
     runs-on: ubuntu-22.04
     # the build-and-test job might be skipped, we don't need to run this job then
     if: success() || failure()
 
     steps:
-      - name: Check out source code
-        if: needs.twister-build.result == 'failure'
+      # Needed for elasticearch and upload script
+      - if: github.event_name == 'push' || github.event_name == 'schedule'
+        name: Checkout
         uses: actions/checkout@v4
         with:
-          ref: ${{ github.event.pull_request.head.sha }}
           fetch-depth: 0
           persist-credentials: false
 
@@ -230,21 +328,34 @@ jobs:
         with:
           path: artifacts
 
+      - if: github.event_name == 'push' || github.event_name == 'schedule'
+        name: Upload to elasticsearch
+        run: |
+          pip3 install elasticsearch
+          # set run date on upload to get consistent and unified data across the matrix.
+          run_date=`date --iso-8601=minutes`
+          if [ "${{github.event_name}}" = "push" ]; then
+            python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \
+              --index zephyr-main-ci-push-1 artifacts/*/*/twister.json
+          elif [ "${{github.event_name}}" = "schedule" ]; then
+            python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \
+              --index zephyr-main-ci-weekly-1 artifacts/*/*/twister.json
+          fi
+
       - name: Merge Test Results
         run: |
-          pip install junitparser junit2html
+          pip3 install junitparser junit2html
           junitparser merge artifacts/*/*/twister.xml junit.xml
           junit2html junit.xml junit.html
 
-      - name: Upload Unit Test Results
+      - name: Upload Unit Test Results in HTML
         if: always()
         uses: actions/upload-artifact@v4
         with:
-          name: Unit Test Results
+          name: HTML Unit Test Results
           if-no-files-found: ignore
           path: |
             junit.html
-            junit.xml
 
       - name: Publish Unit Test Results
         uses: EnricoMi/publish-unit-test-result-action@v2
@@ -252,25 +363,6 @@ jobs:
           check_name: Unit Test Results
           files: "**/twister.xml"
           comment_mode: off
-
-      - name: Analyze Twister Reports
-        if: needs.twister-build.result == 'failure'
-        run: |
-          ./scripts/ci/twister_report_analyzer.py artifacts/*/*/twister.json --long-summary --platforms --output-md errors.md
-          if [[ -s "errors.md" ]]; then
-            echo '### Error Summary! 🚀' >> $GITHUB_STEP_SUMMARY
-            cat errors.md  >> $GITHUB_STEP_SUMMARY
-          fi
-
-      - name: Upload Twister Analysis Results
-        if: needs.twister-build.result == 'failure'
-        uses: actions/upload-artifact@v4
-        with:
-          name: Twister Analysis Results
-          if-no-files-found: ignore
-          path: |
-            twister_report_summary.json
-
   twister-status-check:
     if: always()
     name: "Check Twister Status"

.github/workflows/twister_tests.yml

@@ -32,7 +32,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-22.04]
     steps:
     - name: checkout
@@ -51,7 +51,7 @@ jobs:
           ${{ runner.os }}-pip-${{ matrix.python-version }}
     - name: install-packages
       run: |
-        pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt -r scripts/requirements-run-test.txt
+        pip3 install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt -r scripts/requirements-run-test.txt
     - name: Run pytest for twisterlib
       env:
         ZEPHYR_BASE: ./

.github/workflows/twister_tests_blackbox.yml

@@ -21,10 +21,10 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-22.04]
     container:
-      image: ghcr.io/zephyrproject-rtos/ci:v0.27.4
+      image: ghcr.io/zephyrproject-rtos/ci:v0.26.13
 
     steps:
     - name: Apply Container Owner Mismatch Workaround
@@ -44,8 +44,7 @@ jobs:
 
         west init -l . || true
         # we do not depend on any hals, tools or bootloader, save some time and space...
-        west config manifest.group-filter -- -hal,-tools,-bootloader,-babblesim
-        west config manifest.project-filter -- -nrf_hw_models
+        west config manifest.group-filter -- -hal,-tools,-bootloader
         west config --global update.narrow true
         west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /github/cache/zephyrproject)
         west forall -c 'git reset --hard HEAD'

.github/workflows/west_cmds.yml

@@ -29,7 +29,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-22.04, macos-14, windows-2022]
     steps:
     - name: checkout
@@ -65,7 +65,8 @@ jobs:
           ${{ runner.os }}-pip-${{ matrix.python-version }}
     - name: install pytest
       run: |
-        pip install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial anytree junitparser
+        pip3 install wheel
+        pip3 install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial
     - name: run pytest-win
       if: runner.os == 'Windows'
       run: |

.gitignore

@@ -59,17 +59,6 @@ venv
 .clangd
 new.info
 
-# Cargo drops lock files in projects to capture resolved dependencies.
-# We don't want to record these.
-Cargo.lock
-
-# Cargo encourages a .cargo/config.toml file to symlink to a generated file.  Don't save these.
-.cargo/
-
-# Normal west builds will place the Rust target directory under the build directory.  However,
-# sometimes IDEs and such will litter these target directories as well.
-target/
-
 # CI output
 compliance.xml
 _error.types
@@ -102,10 +91,5 @@ MaintainersFormat.txt
 ModulesMaintainers.txt
 Nits.txt
 Pylint.txt
-Ruff.txt
 SphinxLint.txt
-SysbuildKconfig.txt
-SysbuildKconfigBasic.txt
-SysbuildKconfigBasicNoModules.txt
-TextEncoding.txt
 YAMLLint.txt

.mailmap

@@ -1,14 +1,14 @@
 Alexandr Kolosov <rikorsev@gmail.com>
 Alexandre d'Alton <alexandre.dalton@intel.com>
-Amir Kaplan <amir.kaplan@intel.com>
-Anas Nashif <anas.nashif@intel.com>
+Amir Kaplan <amir.kaplan@intel.com> <amir.kaplan@intel.com>
+Anas Nashif <anas.nashif@intel.com> <anas.nashif@intel.com>
 Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
 Anthony Smigielski <thebasti0ncode@gmail.com>
 Armand Ciejak <armand@riedonetworks.com>  <armandciejak@users.noreply.github.com>
 Aska Wu <aska.wu@linaro.org>
-Bit Pathe <bitpathe@gmail.com>
+Bit Pathe <bitpathe@gmail.com> <bitpathe@gmail.com>
 Bjarki Arge Andreasen <baa@trackunit.com>
-Carles Cufi <carles.cufi@nordicsemi.no>
+Carles Cufi <carles.cufi@nordicsemi.no> <carles.cufi@nordicsemi.no>
 chao an <anchao@xiaomi.com>
 Charles E. Youse <charles.youse@intel.com>
 Chen Xingyu <hi@xingrz.me>
@@ -16,32 +16,32 @@ Christoph Schnetzler <christoph.schnetzler@husqvarnagroup.com>
 Christoph Schramm <schramm@makaio.com>
 Christopher Friedt <cfriedt@meta.com>
 Christopher Friedt <cfriedt@meta.com> <cfriedt@fb.com>
-Chuck Jordan <cjordan@synopsys.com>
+Chuck Jordan <cjordan@synopsys.com> <cjordan@synopsys.com>
 Chunlin Han <chunlin.han@linaro.org> <chunlin.han@acer.com>
 David B. Kinder <david.b.kinder@intel.com>
 David Komel <a8961713@gmail.com>
 David Leach <david.leach@nxp.com>
-Dirk Brandewie <dirk.j.brandewie@intel.com>
-Douglas Su <d0u9.su@outlook.com>
+Dirk Brandewie <dirk.j.brandewie@intel.com> <dirk.j.brandewie@intel.com>
+Douglas Su <d0u9.su@outlook.com> <d0u9.su@outlook.com>
 Enjia Mai <enjia.mai@intel.com>
-Enjia Mai <enjia.mai@intel.com>
-Evan Couzens <evanx.couzens@intel.com>
+Enjia Mai <enjia.mai@intel.com> <enjiax.mai@intel.com>
+Evan Couzens <evanx.couzens@intel.com> <evanx.couzens@intel.com>
 Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
 Evgeniy Paltsev <PaltsevEvgeniy@gmail.com> <Eugeniy.Paltsev@synopsys.com>
-Felipe Neves <ryukokki.felipe@gmail.com>
+Felipe Neves <ryukokki.felipe@gmail.com> <ryukokki.felipe@gmail.com>
 Findlay Feng <i@fengch.me>
 Flavio Arieta Netto <flavio@exati.com.br>
 Francois Ramu <francois.ramu@st.com>
-Gerardo Aceves <gerardo.aceves@intel.com>
+Gerardo Aceves <gerardo.aceves@intel.com> <gerardo.aceves@intel.com>
 Gregory Shue <gregory.shue@legrand.com>
 Gregory Shue <gregory.shue@legrand.com> <gregory.shue@legrand.us>
 HaiLong Yang <cameledyang@pm.me>
 James Johnson <james.johnson672@t-mobile.com>
 Jarno Lämsä <jarno.lamsa@nordicsemi.no>
 Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
-Jeremie Garcia <jeremie.garcia@intel.com>
+Jeremie Garcia <jeremie.garcia@intel.com> <jeremie.garcia@intel.com>
 Jim Benjamin Luther <jilu@oticon.com>
-Johan Kruger <johan.kruger@windriver.com>
+Johan Kruger <johan.kruger@windriver.com> <johan.kruger@windriver.com>
 Johann Fischer <j.fischer@phytec.de>
 Jørgen Kvalvaag <jorgen.kvalvaag@nordicsemi.no>
 Juan Manuel Cruz Alcaraz <juan.m.cruz.alcaraz@intel.com>
@@ -51,11 +51,11 @@ Jun Li <jun.r.li@intel.com>
 Justin Watson <jwatson5@gmail.com>
 Kamil Sroka <kamil.sroka@nordicsemi.no>
 Katarzyna Giądła <katarzyna.giadla@nordicsemi.no>
-Keren Siman-Tov <keren.siman-tov@intel.com>
+Keren Siman-Tov <keren.siman-tov@intel.com> <keren.siman-tov@intel.com>
 Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
-Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
-Lei Liu <lei.a.liu@intel.com>
-Leona Cook <leonax.cook@intel.com>
+Kuo-Lang Tseng <kuo-lang.tseng@intel.com> <kuo-lang.tseng@intel.com>
+Lei Liu <lei.a.liu@intel.com> <lei.a.liu@intel.com>
+Leona Cook <leonax.cook@intel.com> <leonax.cook@intel.com>
 Leona Cook <leonax.cook@intel.com> <lsc@hackeress.com>
 Lixin Guo <lixinx.guo@intel.com>
 Łukasz Mazur <lukasz.mazur@hidglobal.com>
@@ -72,14 +72,14 @@ Martí Bolívar <marti.bolivar@nordicsemi.no> <marti.bolivar@linaro.org>
 Martí Bolívar <marti.bolivar@nordicsemi.no> <marti.f.bolivar@gmail.com>
 Martí Bolívar <marti.bolivar@nordicsemi.no> <marti@foundries.io>
 Martí Bolívar <marti.bolivar@nordicsemi.no> <marti@opensourcefoundries.com>
-Martin Jäger <martin@libre.solar> <17674105+martinjaeger@users.noreply.github.com>
+Martin Jäger <martin@libre.solar>  <17674105+martinjaeger@users.noreply.github.com>
 Mateusz Hołenko <mholenko@antmicro.com>
 Michael Rosen <michael.r.rosen@intel.com>
 Michal Narajowski <michal.narajowski@codecoup.pl>
-Mike Hirst <michael.hirst@windriver.com>
+Mike Hirst <michael.hirst@windriver.com> <michael.hirst@windriver.com>
 Ming Shao <ming.shao@intel.com>
 Mohan Kumar Kumar <mohankm@fb.com>
-Naga Raja Rao Tulasi <tulasi.r@tcs.com>
+Naga Raja Rao Tulasi <tulasi.r@tcs.com> <tulasi.r@tcs.com>
 Navin Sankar Velliangiri <navin@linumiz.com>
 NingX Zhao <ningx.zhao@intel.com>
 Nishikant Nayak <nishikantax.nayak@intel.com>
@@ -100,23 +100,21 @@ Radosław Koppel <radoslaw.koppel@nordicsemi.no> <r.koppel@k-el.com>
 Raja D. Singh <rdsingh@iotwizards.com>
 Ricardo Salveti <ricardo@opensourcefoundries.com>
 Ricardo Salveti <ricardo@opensourcefoundries.com> <ricardo.salveti@linaro.org>
-Ruud Derwig <Ruud.Derwig@synopsys.com>
+Ruud Derwig <Ruud.Derwig@synopsys.com> <Ruud.Derwig@synopsys.com>
 Saku Rautio <saku.rautio@nordicsemi.no>
 Scott Worley <scott.worley@microchip.com>
 Sean Nyekjaer <sean@geanix.com> <sean.nyekjaer@prevas.dk>
 Sean Nyekjaer <sean@geanix.com> <sean@nyekjaer.dk>
 Sharron Liu <sharron.liu@intel.com>
 Shilpashree L C <shilpashree.lc@intel.com>
-Shuang He <shuang.he@intel.com>
+Shuang He <shuang.he@intel.com> <shuang.he@intel.com>
 Sigvart Hovland <sigvart.hovland@nordicsemi.no>
 Stéphane D'Alu <sdalu@sdalu.com>
 Stine Åkredalen <stine.akredalen@nordicsemi.no>
-Thomas Heeley <thomas.heeley@intel.com>
+Thomas Heeley <thomas.heeley@intel.com> <thomas.heeley@intel.com>
 Tim Sørensen <tims@demant.com>
 Tim Sørensen <tims@demant.com> <tims@oticon.com>
-Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
-Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no> <vich@nordicsemi.no>
-Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no> <vinayak.kariappa@gmail.com>
+Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no> <vinayak.kariappa.chettimada@nordicsemi.no> <vich@nordicsemi.no> <vinayak.kariappa@gmail.com>
 Xiaorui Hu <xiaorui.hu@linaro.org>
 Yannis Damigos <giannis.damigos@gmail.com> <ydamigos@iccs.gr>
 Yonattan Louise <yonattan.a.louise.mendoza@intel.com>

.ruff.toml

@@ -1,30 +0,0 @@
-# Copyright (c) 2024 Basalte bv
-# SPDX-License-Identifier: Apache-2.0
-
-extend = ".ruff-excludes.toml"
-
-line-length = 100
-target-version = "py310"
-
-[lint]
-select = [
-    # zephyr-keep-sorted-start
-    "B",      # flake8-bugbear
-    "E",      # pycodestyle
-    "F",      # pyflakes
-    "I",      # isort
-    "SIM",    # flake8-simplify
-    "UP",     # pyupgrade
-    "W",      # pycodestyle warnings
-    # zephyr-keep-sorted-stop
-]
-
-ignore = [
-    # zephyr-keep-sorted-start
-    "SIM108", # Allow if-else blocks instead of forcing ternary operator
-    # zephyr-keep-sorted-stop
-]
-
-[format]
-quote-style = "preserve"
-line-ending = "lf"

CMakeLists.txt

@@ -88,7 +88,6 @@ set(SYSCALL_LIST_H_TARGET      syscall_list_h_target)
 set(DRIVER_VALIDATION_H_TARGET driver_validation_h_target)
 set(KOBJ_TYPES_H_TARGET        kobj_types_h_target)
 set(PARSE_SYSCALLS_TARGET      parse_syscalls_target)
-set(DEVICE_API_LD_TARGET       device_api_ld_target)
 
 define_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT BRIEF_DOCS " " FULL_DOCS " ")
 set_property(   GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-little${ARCH}) # BFD format
@@ -174,17 +173,7 @@ endif()
 
 # @Intent: Set compiler flags to detect general stack overflows across all functions
 if(CONFIG_STACK_CANARIES)
-  zephyr_compile_options("$<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,security_canaries>>")
-  zephyr_compile_options("$<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,security_canaries>>")
-elseif(CONFIG_STACK_CANARIES_STRONG)
-  zephyr_compile_options("$<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,security_canaries_strong>>")
-  zephyr_compile_options("$<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,security_canaries_strong>>")
-elseif(CONFIG_STACK_CANARIES_ALL)
-  zephyr_compile_options("$<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,security_canaries_all>>")
-  zephyr_compile_options("$<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,security_canaries_all>>")
-elseif(CONFIG_STACK_CANARIES_EXPLICIT)
-  zephyr_compile_options("$<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,security_canaries_explicit>>")
-  zephyr_compile_options("$<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,security_canaries_explitic>>")
+  zephyr_compile_options($<TARGET_PROPERTY:compiler,security_canaries>)
 endif()
 
 # @Intent: Obtain compiler optimizations flags and store in variables
@@ -231,8 +220,7 @@ SOC_* symbol.")
 endif()
 
 # Apply the final optimization flag(s)
-zephyr_compile_options($<$<COMPILE_LANGUAGE:C>:${OPTIMIZATION_FLAG}>)
-zephyr_compile_options($<$<COMPILE_LANGUAGE:CXX>:${OPTIMIZATION_FLAG}>)
+zephyr_compile_options(${OPTIMIZATION_FLAG})
 
 if(CONFIG_LTO)
   zephyr_compile_options($<TARGET_PROPERTY:compiler,optimization_lto>)
@@ -320,9 +308,7 @@ if(CONFIG_CODING_GUIDELINE_CHECK)
 endif()
 
 # @Intent: Set compiler specific macro inclusion of AUTOCONF_H
-zephyr_compile_options("SHELL: $<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,imacros> ${AUTOCONF_H}>")
-zephyr_compile_options("SHELL: $<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,imacros> ${AUTOCONF_H}>")
-zephyr_compile_options("SHELL: $<$<COMPILE_LANGUAGE:ASM>:$<TARGET_PROPERTY:asm,imacros> ${AUTOCONF_H}>")
+zephyr_compile_options("SHELL: $<TARGET_PROPERTY:compiler,imacros> ${AUTOCONF_H}")
 
 if(CONFIG_COMPILER_FREESTANDING)
   # @Intent: Set compiler specific flag for bare metal freestanding option
@@ -367,9 +353,7 @@ zephyr_compile_options($<$<COMPILE_LANGUAGE:ASM>:$<TARGET_PROPERTY:asm,required>
 # @Intent: Enforce standard integer type correspondence to match Zephyr usage.
 # (must be after compiler specific flags)
 if(CONFIG_ENFORCE_ZEPHYR_STDINT)
-  zephyr_compile_options("SHELL:$<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,imacros> ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h>")
-  zephyr_compile_options("SHELL:$<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,imacros> ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h>")
-  zephyr_compile_options("SHELL:$<$<COMPILE_LANGUAGE:ASM>:$<TARGET_PROPERTY:asm,imacros> ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h>")
+  zephyr_compile_options("SHELL: $<TARGET_PROPERTY:compiler,imacros> ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h")
 endif()
 
 # Common toolchain-agnostic assembly flags
@@ -614,8 +598,6 @@ add_custom_command(
   COMMAND_EXPAND_LISTS
 )
 add_custom_target(version_h DEPENDS ${PROJECT_BINARY_DIR}/include/generated/zephyr/version.h)
-zephyr_get(KERNEL_VERSION_CUSTOMIZATION SYSBUILD LOCAL)
-set_property(TARGET version_h PROPERTY KERNEL_VERSION_CUSTOMIZATION ${KERNEL_VERSION_CUSTOMIZATION})
 
 if(EXISTS ${APPLICATION_SOURCE_DIR}/VERSION)
   add_custom_command(
@@ -634,8 +616,6 @@ if(EXISTS ${APPLICATION_SOURCE_DIR}/VERSION)
     app_version_h
     DEPENDS ${PROJECT_BINARY_DIR}/include/generated/zephyr/app_version.h)
   add_dependencies(zephyr_interface app_version_h)
-  zephyr_get(APP_VERSION_CUSTOMIZATION SYSBUILD LOCAL)
-  set_property(TARGET app_version_h PROPERTY APP_VERSION_CUSTOMIZATION ${APP_VERSION_CUSTOMIZATION})
 endif()
 
 # Unfortunately, the order in which CMakeLists.txt code is processed
@@ -857,12 +837,7 @@ if(CONFIG_LEGACY_GENERATED_INCLUDE_PATH)
     ${CMAKE_CURRENT_BINARY_DIR}/include/generated/syscall_list.h)
 endif()
 
-add_custom_command(
-  OUTPUT
-  include/generated/zephyr/syscall_dispatch.c
-  include/generated/zephyr/syscall_exports_llext.c
-  syscall_weakdefs_llext.c
-  ${syscall_list_h}
+add_custom_command(OUTPUT include/generated/zephyr/syscall_dispatch.c ${syscall_list_h}
   # Also, some files are written to include/generated/zephyr/syscalls/
   COMMAND
   ${PYTHON_EXECUTABLE}
@@ -870,8 +845,7 @@ add_custom_command(
   --json-file        ${syscalls_json}                     # Read this file
   --base-output      include/generated/zephyr/syscalls    # Write to this dir
   --syscall-dispatch include/generated/zephyr/syscall_dispatch.c # Write this file
-  --syscall-exports-llext  include/generated/zephyr/syscall_exports_llext.c
-  --syscall-weakdefs-llext syscall_weakdefs_llext.c # compiled in CMake library 'syscall_weakdefs'
+  --syscall-export-llext  include/generated/zephyr/syscall_export_llext.c
   --syscall-list     ${syscall_list_h}
   $<$<BOOL:${CONFIG_USERSPACE}>:--gen-mrsh-files>
   ${SYSCALL_LONG_REGISTERS_ARG}
@@ -904,37 +878,6 @@ add_custom_target(${DRIVER_VALIDATION_H_TARGET} DEPENDS ${DRV_VALIDATION})
 include(${ZEPHYR_BASE}/cmake/kobj.cmake)
 gen_kobj(KOBJ_INCLUDE_PATH)
 
-# Generate sections for kernel device subsystems
-set(
-  DEVICE_API_LD_SECTIONS
-  ${CMAKE_CURRENT_BINARY_DIR}/include/generated/device-api-sections.ld
-  )
-
-set(DEVICE_API_LINKER_SECTIONS_CMAKE
-    ${CMAKE_CURRENT_BINARY_DIR}/include/generated/device-api-sections.cmake
-)
-
-add_custom_command(
-  OUTPUT ${DEVICE_API_LD_SECTIONS} ${DEVICE_API_LINKER_SECTIONS_CMAKE}
-  COMMAND
-    ${PYTHON_EXECUTABLE}
-    ${ZEPHYR_BASE}/scripts/build/gen_iter_sections.py
-    --alignment ${CONFIG_LINKER_ITERABLE_SUBALIGN}
-    --input ${struct_tags_json}
-    --tag __subsystem
-    --ld-output ${DEVICE_API_LD_SECTIONS}
-    --cmake-output ${DEVICE_API_LINKER_SECTIONS_CMAKE}
-  DEPENDS
-    ${ZEPHYR_BASE}/scripts/build/gen_iter_sections.py
-    ${struct_tags_json}
-  WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
-  )
-
-add_custom_target(${DEVICE_API_LD_TARGET}
-                  DEPENDS ${DEVICE_API_LD_SECTIONS}
-                          ${DEVICE_API_LINKER_SECTIONS_CMAKE}
-)
-
 # Add a pseudo-target that is up-to-date when all generated headers
 # are up-to-date.
 
@@ -965,7 +908,6 @@ add_dependencies(zephyr_interface
   ${SYSCALL_LIST_H_TARGET}
   ${DRIVER_VALIDATION_H_TARGET}
   ${KOBJ_TYPES_H_TARGET}
-  ${DEVICE_API_LD_TARGET}
   )
 
 add_custom_command(
@@ -1030,16 +972,6 @@ else()
   set(NO_WHOLE_ARCHIVE_LIBS kernel)
 endif()
 
-if(CONFIG_LLEXT)
-  # LLEXT exports symbols for all syscalls, including unimplemented ones.
-  # Weak definitions for these must be added at the end of the link order
-  # to avoid shadowing actual implementations.
-  add_library(syscall_weakdefs syscall_weakdefs_llext.c)
-  add_dependencies(syscall_weakdefs zephyr_generated_headers)
-  target_link_libraries(syscall_weakdefs zephyr_interface)
-  list(APPEND NO_WHOLE_ARCHIVE_LIBS syscall_weakdefs)
-endif()
-
 get_property(OUTPUT_FORMAT        GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT)
 
 if (CONFIG_CODE_DATA_RELOCATION)
@@ -1103,6 +1035,14 @@ if(CONFIG_USERSPACE)
   set(PROCESS_GPERF ${ZEPHYR_BASE}/scripts/build/process_gperf.py)
 endif()
 
+get_property(GLOBAL_CSTD GLOBAL PROPERTY CSTD)
+if(DEFINED GLOBAL_CSTD)
+  message(DEPRECATION
+    "Global CSTD property is deprecated, see Kconfig.zephyr for C Standard options.")
+  set(CSTD ${GLOBAL_CSTD})
+  list(APPEND CMAKE_C_COMPILE_FEATURES ${compile_features_${CSTD}})
+endif()
+
 # @Intent: Obtain compiler specific flag for specifying the c standard
 zephyr_compile_options(
   $<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,cstd>${CSTD}>
@@ -1118,10 +1058,10 @@ set_ifndef(  TOPT "${COMPILER_TOPT}")
 set_ifndef(  TOPT -Wl,-T) # Use this if the compiler driver doesn't set a value
 
 if(CONFIG_HAVE_CUSTOM_LINKER_SCRIPT)
-  string(CONFIGURE ${APPLICATION_SOURCE_DIR}/${CONFIG_CUSTOM_LINKER_SCRIPT} LINKER_SCRIPT)
+  set(LINKER_SCRIPT ${APPLICATION_SOURCE_DIR}/${CONFIG_CUSTOM_LINKER_SCRIPT})
   if(NOT EXISTS ${LINKER_SCRIPT})
-    string(CONFIGURE ${CONFIG_CUSTOM_LINKER_SCRIPT} LINKER_SCRIPT)
-    assert_exists(LINKER_SCRIPT)
+    set(LINKER_SCRIPT ${CONFIG_CUSTOM_LINKER_SCRIPT})
+    assert_exists(CONFIG_CUSTOM_LINKER_SCRIPT)
   endif()
 elseif(DEFINED BOARD_LINKER_SCRIPT)
   set(LINKER_SCRIPT ${BOARD_LINKER_SCRIPT})
@@ -1678,9 +1618,10 @@ list(APPEND
 )
 list(APPEND post_build_byproducts ${KERNEL_MAP_NAME})
 
-# Use ';' as separator to get proper space in resulting command.
-set(gap_fill_prop "$<TARGET_PROPERTY:bintools,elfconvert_flag_gapfill>")
-set(gap_fill "$<$<BOOL:${gap_fill_prop}>:${gap_fill_prop}${CONFIG_BUILD_GAP_FILL_PATTERN}>")
+if(NOT CONFIG_BUILD_NO_GAP_FILL)
+  # Use ';' as separator to get proper space in resulting command.
+  set(GAP_FILL "$<TARGET_PROPERTY:bintools,elfconvert_flag_gapfill>0xff")
+endif()
 
 if(CONFIG_OUTPUT_PRINT_MEMORY_USAGE)
   target_link_libraries(${logical_target_for_zephyr_elf} $<TARGET_PROPERTY:linker,memusage>)
@@ -1741,7 +1682,7 @@ if(CONFIG_BUILD_OUTPUT_HEX OR BOARD_FLASH_RUNNER STREQUAL openocd)
       post_build_commands
       COMMAND $<TARGET_PROPERTY:bintools,elfconvert_command>
               $<TARGET_PROPERTY:bintools,elfconvert_flag>
-              $<$<BOOL:${CONFIG_BUILD_OUTPUT_HEX_GAP_FILL}>:${gap_fill}>
+              ${GAP_FILL}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_outtarget>ihex
               ${remove_sections_argument_list}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_infile>${KERNEL_ELF_NAME}
@@ -1763,7 +1704,7 @@ if(CONFIG_BUILD_OUTPUT_BIN)
       post_build_commands
       COMMAND $<TARGET_PROPERTY:bintools,elfconvert_command>
               $<TARGET_PROPERTY:bintools,elfconvert_flag>
-              ${gap_fill}
+              ${GAP_FILL}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_outtarget>binary
               ${remove_sections_argument_list}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_infile>${KERNEL_ELF_NAME}
@@ -1850,7 +1791,7 @@ if(CONFIG_BUILD_OUTPUT_S19)
       post_build_commands
       COMMAND $<TARGET_PROPERTY:bintools,elfconvert_command>
               $<TARGET_PROPERTY:bintools,elfconvert_flag>
-              $<$<BOOL:${CONFIG_BUILD_OUTPUT_S19_GAP_FILL}>:${gap_fill}>
+              ${GAP_FILL}
               $<TARGET_PROPERTY:bintools,elfconvert_flag_outtarget>srec
               $<TARGET_PROPERTY:bintools,elfconvert_flag_srec_len>1
               $<TARGET_PROPERTY:bintools,elfconvert_flag_infile>${KERNEL_ELF_NAME}
@@ -1999,6 +1940,7 @@ if (CONFIG_LLEXT AND CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID)
     --elf-file ${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}
     --slid-listing ${PROJECT_BINARY_DIR}/slid_listing.txt
   )
+
 endif()
 
 if(NOT CMAKE_C_COMPILER_ID STREQUAL "ARMClang")
@@ -2229,57 +2171,51 @@ if((CMAKE_BUILD_TYPE IN_LIST build_types) AND (NOT NO_BUILD_TYPE_WARNING))
 endif()
 
 # Extension Development Kit (EDK) generation.
-if(CONFIG_LLEXT_EDK)
-  if(CONFIG_LLEXT_EDK_FORMAT_TAR_XZ)
-    set(llext_edk_extension "tar.xz")
-  elseif(CONFIG_LLEXT_EDK_FORMAT_TAR_ZSTD)
-    set(llext_edk_extension "tar.Z")
-  elseif(CONFIG_LLEXT_EDK_FORMAT_ZIP)
-    set(llext_edk_extension "zip")
-  else()
-    message(FATAL_ERROR "Unsupported LLEXT_EDK_FORMAT choice")
-  endif()
-  set(llext_edk_file ${PROJECT_BINARY_DIR}/${CONFIG_LLEXT_EDK_NAME}.${llext_edk_extension})
+set(llext_edk_file ${PROJECT_BINARY_DIR}/${CONFIG_LLEXT_EDK_NAME}.tar.xz)
 
-  # TODO maybe generate flags for C CXX ASM
-  zephyr_get_compile_definitions_for_lang(C zephyr_defs)
-  zephyr_get_compile_options_for_lang(C zephyr_flags)
+# TODO maybe generate flags for C CXX ASM
+zephyr_get_compile_definitions_for_lang(C zephyr_defs)
+zephyr_get_compile_options_for_lang(C zephyr_flags)
 
-  # Filter out non LLEXT and LLEXT_EDK flags - and add required ones
-  llext_filter_zephyr_flags(LLEXT_REMOVE_FLAGS ${zephyr_flags} llext_filt_flags)
-  llext_filter_zephyr_flags(LLEXT_EDK_REMOVE_FLAGS ${llext_filt_flags} llext_filt_flags)
+# Filter out non LLEXT and LLEXT_EDK flags - and add required ones
+llext_filter_zephyr_flags(LLEXT_REMOVE_FLAGS ${zephyr_flags} llext_filt_flags)
+llext_filter_zephyr_flags(LLEXT_EDK_REMOVE_FLAGS ${llext_filt_flags} llext_filt_flags)
 
-  set(llext_edk_cflags ${zephyr_defs} -DLL_EXTENSION_BUILD)
-  list(APPEND llext_edk_cflags ${llext_filt_flags})
-  list(APPEND llext_edk_cflags ${LLEXT_APPEND_FLAGS})
-  list(APPEND llext_edk_cflags ${LLEXT_EDK_APPEND_FLAGS})
+set(llext_edk_cflags ${zephyr_defs} -DLL_EXTENSION_BUILD)
+list(APPEND llext_edk_cflags ${llext_filt_flags})
+list(APPEND llext_edk_cflags ${LLEXT_APPEND_FLAGS})
+list(APPEND llext_edk_cflags ${LLEXT_EDK_APPEND_FLAGS})
 
-  build_info(llext-edk file PATH ${llext_edk_file})
-  build_info(llext-edk cflags VALUE ${llext_edk_cflags})
-  build_info(llext-edk include-dirs VALUE "$<TARGET_PROPERTY:zephyr_interface,INTERFACE_INCLUDE_DIRECTORIES>")
-
-  add_custom_command(
+add_custom_command(
     OUTPUT ${llext_edk_file}
     # Regenerate syscalls in case CONFIG_LLEXT_EDK_USERSPACE_ONLY
     COMMAND ${CMAKE_COMMAND}
-      -E make_directory edk/include/generated/zephyr
+        -E make_directory edk/include/generated/zephyr
     COMMAND
-      ${PYTHON_EXECUTABLE}
-      ${ZEPHYR_BASE}/scripts/build/gen_syscalls.py
-      --json-file        ${syscalls_json}                     # Read this file
-      --base-output      edk/include/generated/zephyr/syscalls           # Write to this dir
-      --syscall-dispatch edk/include/generated/zephyr/syscall_dispatch.c # Write this file
-      --syscall-list     ${edk_syscall_list_h}
-      $<$<BOOL:${CONFIG_LLEXT_EDK_USERSPACE_ONLY}>:--userspace-only>
-      ${SYSCALL_LONG_REGISTERS_ARG}
-      ${SYSCALL_SPLIT_TIMEOUT_ARG}
+        ${PYTHON_EXECUTABLE}
+        ${ZEPHYR_BASE}/scripts/build/gen_syscalls.py
+        --json-file        ${syscalls_json}                     # Read this file
+        --base-output      edk/include/generated/zephyr/syscalls           # Write to this dir
+        --syscall-dispatch edk/include/generated/zephyr/syscall_dispatch.c # Write this file
+        --syscall-list     ${edk_syscall_list_h}
+        $<$<BOOL:${CONFIG_LLEXT_EDK_USERSPACE_ONLY}>:--userspace-only>
+        ${SYSCALL_LONG_REGISTERS_ARG}
+        ${SYSCALL_SPLIT_TIMEOUT_ARG}
     COMMAND ${CMAKE_COMMAND}
+        -DPROJECT_BINARY_DIR=${PROJECT_BINARY_DIR}
+        -DAPPLICATION_SOURCE_DIR=${APPLICATION_SOURCE_DIR}
+        -DINTERFACE_INCLUDE_DIRECTORIES="$<TARGET_PROPERTY:zephyr_interface,INTERFACE_INCLUDE_DIRECTORIES>"
+        -Dllext_edk_file=${llext_edk_file}
+        -Dllext_edk_cflags="${llext_edk_cflags}"
+        -Dllext_edk_name=${CONFIG_LLEXT_EDK_NAME}
+        -DWEST_TOPDIR=${WEST_TOPDIR}
+        -DZEPHYR_BASE=${ZEPHYR_BASE}
+        -DCONFIG_LLEXT_EDK_USERSPACE_ONLY=${CONFIG_LLEXT_EDK_USERSPACE_ONLY}
         -P ${ZEPHYR_BASE}/cmake/llext-edk.cmake
-    DEPENDS ${logical_target_for_zephyr_elf} build_info_yaml_saved
+    DEPENDS ${logical_target_for_zephyr_elf}
     COMMAND_EXPAND_LISTS
-  )
-  add_custom_target(llext-edk DEPENDS ${llext_edk_file})
-endif()
+)
+add_custom_target(llext-edk DEPENDS ${llext_edk_file})
 
 # @Intent: Set compiler specific flags for standard C/C++ includes
 # Done at the very end, so any other system includes which may
@@ -2297,11 +2233,3 @@ add_subdirectory_ifdef(
   CONFIG_MAKEFILE_EXPORTS
   cmake/makefile_exports
   )
-
-toolchain_linker_finalize()
-
-# export build information
-build_info(zephyr version VALUE ${PROJECT_VERSION_STR})
-build_info(zephyr zephyr-base VALUE ${ZEPHYR_BASE})
-
-yaml_save(NAME build_info)

CODEOWNERS

@@ -0,0 +1,491 @@
+# CODEOWNERS for autoreview assigning in github
+
+# https://help.github.com/en/articles/about-code-owners#codeowners-syntax
+
+# Order is important; for each modified file, the last matching
+# pattern takes the most precedence.
+# That is, with the last pattern being
+# *.rst                                     @nashif
+# if only .rst files are being modified, only nashif is
+# automatically requested for review, but you can manually
+# add others as needed.
+
+# Do not use wildcard on all source yet
+#
+# +++++++++++ NOTE ++++++++++++++++
+#
+# Please use the MAINTAINERS file to add yourself in an area or to add a new
+# component or code. This file is going to be deprecated and currently only had
+# entries that are not covered by the MAINTAINERS file.
+
+/soc/arm/aspeed/                          @aspeeddylan
+/soc/atmel/                               @nandojve
+/soc/arm/bcm*/                            @sbranden
+/soc/arm/ene/                             @ene-steven
+/soc/arm/infineon_cat1/                   @ifyall @npal-cy
+/soc/arm/infineon_xmc/                    @parthitce
+/soc/arm/silabs_exx32/efm32pg1b/          @rdmeneze
+/soc/arm/silabs_exx32/efr32mg21/          @l-alfred
+/soc/arm/st_stm32/stm32mp1/               @arnopo
+/soc/arm/st_stm32/stm32h7/*stm32h735*     @benediktibk
+/soc/arm/st_stm32/stm32l4/*stm32l451*     @benediktibk
+/soc/arm/ti_simplelink/cc13x2_cc26x2/     @bwitherspoon
+/soc/arm/ti_simplelink/cc32xx/            @vanti
+/soc/arm/ti_simplelink/msp432p4xx/        @Mani-Sadhasivam
+/soc/arm/xilinx_zynq7000/                 @ibirnbaum
+/soc/arm/xilinx_zynqmp/                   @stephanosio
+/soc/arm/renesas_rcar/                    @aaillet
+/soc/riscv/openisa*/                      @dleach02
+/soc/riscv/riscv-privileged/andes_v5/      @cwshu @kevinwang821020 @jimmyzhe
+/soc/riscv/riscv-privileged/neorv32/       @henrikbrixandersen
+/soc/riscv/riscv-privileged/gd32vf103/     @soburi
+/soc/starfive/jh71xx/ 			  @pfarwsi
+/soc/riscv/riscv-privileged/niosv/         @sweeaun
+/boards/adafruit/feather_nrf52840/        @jacobw
+/boards/ene/                              @ene-steven
+/boards/arm/96b_argonkey/                 @avisconti
+/boards/arm/96b_avenger96/                @Mani-Sadhasivam
+/boards/arm/96b_carbon/                   @idlethread
+/boards/arm/96b_meerkat96/                @Mani-Sadhasivam
+/boards/arm/96b_nitrogen/                 @idlethread
+/boards/arm/96b_neonkey/                  @Mani-Sadhasivam
+/boards/arm/96b_stm32_sensor_mez/         @Mani-Sadhasivam
+/boards/arm/96b_wistrio/                  @Mani-Sadhasivam
+/boards/arm/acn52832/                     @sven-hm
+/boards/arm/arduino_mkrzero/              @soburi
+/boards/arm/bbc_microbit_v2/              @LingaoM
+/boards/arm/blackpill_f401ce/             @coderkalyan
+/boards/arm/blackpill_f411ce/             @coderkalyan
+/boards/arm/bt*10/                        @greg-leach
+/boards/arm/cc1352r1_launchxl/            @bwitherspoon
+/boards/arm/cc26x2r1_launchxl/            @bwitherspoon
+/boards/arm/cc3220sf_launchxl/            @vanti
+/boards/arm/cy8ckit_062_ble/              @ifyall @npal-cy
+/boards/arm/cy8ckit_062s4/                @DaWei8823
+/boards/arm/cy8ckit_062_wifi_bt/          @ifyall @npal-cy
+/boards/arm/cy8cproto_062_4343w/          @ifyall @npal-cy
+/boards/arm/efm32pg_stk3401a/             @rdmeneze
+/boards/arm/faze/                         @mbittan @simonguinot
+/boards/arm/frdm*/                        @mmahadevan108 @dleach02
+/boards/arm/gd32*/                        @nandojve
+/boards/arm/google_*/                     @jackrosenthal
+/boards/arm/hexiwear*/                    @mmahadevan108 @dleach02
+/boards/arm/ip_k66f/                      @parthitce @lmajewski
+/boards/arm/legend/                       @mbittan @simonguinot
+/boards/arm/lpcxpresso*/                  @mmahadevan108 @dleach02
+/boards/arm/mimx8mm_evk/                  @Mani-Sadhasivam
+/boards/arm/mimx8mm_phyboard_polis        @pefech
+/boards/arm/mimxrt*/                      @mmahadevan108 @dleach02
+/boards/arm/mps2_an385/                   @fvincenzo
+/boards/arm/msp_exp432p401r_launchxl/     @Mani-Sadhasivam
+/boards/arm/npcx7m6fb_evb/                @MulinChao @ChiHuaL
+/boards/arm/nrf*/                         @carlescufi @lemrey
+/boards/arm/nucleo_f401re/                @idlethread
+/boards/arm/nuvoton_pfm_m487/             @ssekar15
+/boards/arm/qemu_cortex_a9/               @ibirnbaum
+/boards/arm/qemu_cortex_r*/               @stephanosio
+/boards/arm/qemu_cortex_m*/               @ioannisg @stephanosio
+/boards/arm/quick_feather/                @fkokosinski @kgugala
+/boards/arm/rak4631_nrf52840/             @gpaquet85
+/boards/arm/rak5010_nrf52840/             @gpaquet85
+/boards/arm/rpi_pico/                     @yonsch
+/boards/arm/ronoth_lodev/                 @NorthernDean
+/boards/arm/xmc45_relax_kit/              @parthitce
+/boards/atmel/                            @nandojve
+/boards/arm/scobc_module1/                @yashi
+/boards/arm/v2m_beetle/                   @fvincenzo
+/boards/arm/olimexino_stm32/              @ydamigos
+/boards/arm/s32*/                         @manuargue
+/boards/arm/sensortile_box/               @avisconti
+/boards/arm/steval_fcu001v1/              @Navin-Sankar
+/boards/arm/stm32l1_disco/                @karlp
+/boards/arm/stm32h735g_disco/             @benediktibk
+/boards/arm/stm32f3_disco/                @ydamigos
+/boards/arm/rcar_*/                       @aaillet
+/boards/arm/ubx_bmd345eval_nrf52840/      @Navin-Sankar @brec-u-blox
+/boards/arm/nrf5340_audio_dk_nrf5340      @koffes @alexsven @erikrobstad @rick1082 @gWacey
+/boards/arm/stm32_min_dev/                @sidcha
+/boards/ezurio/*                          @rerickson1
+/boards/riscv/rv32m1_vega/                @dleach02
+/boards/riscv/adp_xc7k_ae350/             @cwshu @kevinwang821020 @jimmyzhe
+/boards/riscv/longan_nano/                @soburi
+/boards/riscv/neorv32/                    @henrikbrixandersen
+/boards/riscv/niosv*/                     @sweeaun
+/boards/riscv/sparkfun_red_v_things_plus/ @soburi
+/boards/riscv/stamp_c3/                   @soburi
+/boards/starfive/visionfive2/	 	  @kanakshilledar @pfarwsi
+/boards/shields/atmel_rf2xx/              @nandojve
+/boards/shields/esp_8266/                 @nandojve
+/boards/shields/inventek_eswifi/          @nandojve
+/boards/xtensa/odroid_go/                 @ydamigos
+/boards/xtensa/nxp_adsp_imx8/             @iuliana-prodan @dbaluta
+/boards/xtensa/kincony_kc868_a32/         @bbilas
+/boards/arm64/qemu_cortex_a53/            @carlocaione
+/boards/arm64/bcm958402m2_a72/            @abhishek-brcm
+/boards/arm64/mimx8mm_evk/                @MrVan @JiafeiPan
+/boards/arm64/mimx8mp_evk/                @MrVan @JiafeiPan
+/boards/arm64/mimx8mn_evk/                @JiafeiPan
+/boards/arm64/mimx93_evk/                 @JiafeiPan
+/boards/arm64/nxp_ls1046ardb/             @JiafeiPan
+/boards/arm64/xenvm/                      @lorc @firscity
+/boards/arm64/fvp_baser_aemv8r/           @povergoing
+/boards/arm64/fvp_base_revc_2xaemv8a/     @carlocaione
+/boards/arm64/intel_socfpga_agilex_socdk/ @siclim @ngboonkhai
+/boards/arm64/intel_socfpga_agilex5_socdk/ @teikheng @gdengi
+/boards/arm64/rcar_*/                     @lorc @xakep-amatop
+# All cmake related files
+/doc/develop/tools/coccinelle.rst                @himanshujha199640 @JuliaLawall
+/doc/services/device_mgmt/smp_protocol.rst  @de-nordic @nordicjm
+/doc/services/device_mgmt/smp_groups/       @de-nordic @nordicjm
+/doc/services/sensing/                      @lixuzha @ghu0510 @qianruh
+/doc/CMakeLists.txt                       @carlescufi
+/doc/_scripts/                            @carlescufi
+/drivers/*/*sam4l*                        @nandojve
+/drivers/*/*cc13xx_cc26xx*                @bwitherspoon
+/drivers/*/*gd32*                         @nandojve
+/drivers/*/*mcux*                         @mmahadevan108 @dleach02
+/drivers/*/*native_posix*                 @aescolar @daor-oti
+/drivers/*/*lpc11u6x*                     @mbittan @simonguinot
+/drivers/*/*npcx*                         @MulinChao @ChiHuaL
+/drivers/*/*andes*                        @cwshu @kevinwang821020 @jimmyzhe
+/drivers/*/*ifx_cat1*                     @ifyall @npal-cy
+/drivers/*/*neorv32*                      @henrikbrixandersen
+/drivers/*/*_s32*                         @manuargue
+/drivers/adc/adc_ads1x1x.c                @XenuIsWatching
+/drivers/adc/adc_stm32.c                  @cybertale
+/drivers/adc/adc_rpi_pico.c               @soburi
+/drivers/adc/*ads114s0x*                  @benediktibk
+/drivers/adc/*max11102_17*                @benediktibk
+/drivers/adc/*kb1200*                     @ene-steven
+/drivers/adc/adc_ad559x.c                 @bbilas
+/drivers/audio/*nrfx*                     @anangl
+/drivers/auxdisplay/*pt6314*              @xingrz
+/drivers/auxdisplay/*                      @thedjnK
+/drivers/bbram/*                          @yperess @sjg20 @jackrosenthal
+/drivers/bluetooth/                       @alwa-nordic @jhedberg @Vudentz
+/drivers/bluetooth/hci/hci_esp32.c        @sylvioalves
+/drivers/can/*mcp2515*                    @karstenkoenig
+/drivers/can/*rcar*                       @aaillet
+/drivers/clock_control/*agilex*           @siclim @gdengi
+/drivers/clock_control/*nrf*              @nordic-krch
+/drivers/clock_control/*esp32*            @extremegtx @sylvioalves
+/drivers/clock_control/*cpg_mssr*         @aaillet
+/drivers/console/ipm_console.c            @finikorg
+/drivers/console/semihost_console.c       @luozhongyao
+/drivers/console/jailhouse_debug_console.c @MrVan
+/drivers/counter/counter_cmos.c           @dcpleung
+/drivers/counter/counter_ll_stm32_timer.c @kentjhall
+/drivers/counter/*esp32*                  @sylvioalves
+/drivers/counter/dw_timer.c               @pbalsundar
+/drivers/counter/counter_timer_shell.c    @pbalsundar
+/drivers/crypto/*nrf_ecb*                 @maciekfabia @anangl
+/drivers/display/*rm68200*                @mmahadevan108
+/drivers/display/display_ili9342c.*       @extremegtx
+/drivers/dac/*ad56xx*                     @benediktibk
+/drivers/dac/dac_ad559x.c                 @bbilas
+/drivers/dai/                             @kv2019i @marcinszkudlinski @abonislawski
+/drivers/dai/intel/                       @kv2019i @marcinszkudlinski @abonislawski
+/drivers/dai/intel/ssp/                   @kv2019i @marcinszkudlinski @abonislawski
+/drivers/dai/intel/dmic/                  @marcinszkudlinski @abonislawski
+/drivers/dai/intel/alh/                   @abonislawski
+/drivers/dma/dma_dw_axi.c                 @pbalsundar
+/drivers/dma/*dw*                         @tbursztyka
+/drivers/dma/*dw_common*                  @abonislawski
+/drivers/dma/*sam0*                       @Sizurka
+/drivers/dma/dma_stm32*                   @cybertale @lowlander
+/drivers/dma/*pl330*                      @raveenp
+/drivers/dma/*iproc_pax*                  @raveenp
+/drivers/dma/*intel_adsp*                 @teburd @abonislawski
+/drivers/dma/*rpi_pico*                   @soburi
+/drivers/dma/*xmc4xxx*                    @talih0
+/drivers/eeprom/eeprom_stm32.c            @KwonTae-young
+/drivers/entropy/*b91*                    @andy-liu-telink
+/drivers/entropy/*bt_hci*                 @JordanYates
+/drivers/entropy/*rv32m1*                 @dleach02
+/drivers/ethernet/*dwmac*                 @npitre
+/drivers/ethernet/*stm32*                 @Nukersson @lochej
+/drivers/ethernet/*w5500*                 @parthitce
+/drivers/ethernet/*xlnx_gem*              @ibirnbaum
+/drivers/ethernet/*smsc91x*               @sgrrzhf
+/drivers/ethernet/*adin2111*              @GeorgeCGV
+/drivers/ethernet/*oa_tc6*                @lmajewski
+/drivers/ethernet/*lan865x*               @lmajewski
+/drivers/ethernet/dwc_xgmac               @Smale-12048867
+/drivers/ethernet/dwc_xgmac/dwc_xgmac     @Smale-12048867
+/drivers/ethernet/phy/                    @rlubos @tbursztyka @arvinf @jukkar
+/drivers/ethernet/phy/*adin2111*          @GeorgeCGV
+/drivers/mdio/*adin2111*                  @GeorgeCGV
+/drivers/flash/*stm32_qspi*               @lmajewski
+/drivers/flash/*b91*                      @andy-liu-telink
+/drivers/flash/*cadence*                  @ngboonkhai
+/drivers/flash/*cc13xx_cc26xx*            @pepe2k
+/drivers/flash/*nrf*                      @de-nordic
+/drivers/flash/*esp32*                    @sylvioalves
+/drivers/flash/flash_cadence_nand*        @nbalabak
+/drivers/gpio/*b91*                       @andy-liu-telink
+/drivers/gpio/*lmp90xxx*                  @henrikbrixandersen
+/drivers/gpio/*nct38xx*                   @MulinChao @ChiHuaL
+/drivers/gpio/*eos_s3*                    @fkokosinski @kgugala
+/drivers/gpio/*rcar*                      @aaillet
+/drivers/gpio/*esp32*                     @sylvioalves
+/drivers/gpio/*rpi_pico*                  @yonsch
+/drivers/gpio/*xlnx_ps*                   @ibirnbaum
+/drivers/gpio/*ads114s0x*                 @benediktibk
+/drivers/gpio/*bd8lb600fs*                @benediktibk
+/drivers/gpio/*pcal64xxa*                 @benediktibk
+/drivers/gpio/*kb1200*                    @ene-steven
+/drivers/gpio/gpio_altera_pio.c           @shilinte
+/drivers/gpio/gpio_ad559x.c               @bbilas
+/drivers/i2c/i2c_common.c                 @sjg20
+/drivers/i2c/i2c_emul.c                   @sjg20
+/drivers/i2c/i2c_ite_enhance.c            @GTLin08
+/drivers/i2c/i2c_ite_it8xxx2.c            @GTLin08
+/drivers/i2c/i2c_shell.c                  @nashif
+/drivers/i2c/Kconfig.i2c_emul             @sjg20
+/drivers/i2c/Kconfig.it8xxx2              @GTLin08
+/drivers/i2c/target/*eeprom*              @henrikbrixandersen
+/drivers/i2c/Kconfig.test                 @mbolivar-ampere
+/drivers/i2c/i2c_test.c                   @mbolivar-ampere
+/drivers/i2c/*rcar*                       @aaillet
+/drivers/i2c/*kb1200*                     @ene-steven
+/drivers/i2s/i2s_ll_stm32*                @avisconti
+/drivers/i2s/*nrfx*                       @anangl
+/drivers/i3c/i3c_cdns.c                   @XenuIsWatching
+/drivers/ieee802154/                      @rlubos @tbursztyka @jukkar @fgrandel
+/drivers/ieee802154/*b91*                 @andy-liu-telink
+/drivers/ieee802154/ieee802154_nrf5*      @ankuns
+/drivers/ieee802154/ieee802154_rf2xx*     @tbursztyka @nandojve
+/drivers/ieee802154/ieee802154_cc13xx*    @bwitherspoon @cfriedt @vaishnavachath
+/drivers/interrupt_controller/            @dcpleung @nashif
+/drivers/interrupt_controller/intc_gic.c  @stephanosio
+/drivers/interrupt_controller/*esp32*     @sylvioalves
+/drivers/interrupt_controller/intc_nuclei_eclic.c  @soburi
+/drivers/ipm/ipm_mhu*                     @karl-zh
+/drivers/ipm/Kconfig.nrfx                 @masz-nordic
+/drivers/ipm/Kconfig.nrfx_ipc_channel     @masz-nordic
+/drivers/ipm/ipm_cavs*                    @dcpleung @andyross
+/drivers/ipm/ipm_nrfx_ipc.c               @masz-nordic
+/drivers/ipm/ipm_nrfx_ipc.h               @masz-nordic
+/drivers/ipm/ipm_stm32_ipcc.c             @arnopo
+/drivers/ipm/ipm_stm32_hsem.c             @cameled
+/drivers/ipm/ipm_esp32.c                  @uLipe
+/drivers/ipm/ipm_ivshmem.c                @uLipe
+/drivers/kscan/*xec*                      @franciscomunoz @sjvasanth1
+/drivers/kscan/*ft5336*                   @MaureenHelm
+/drivers/kscan/*ht16k33*                  @henrikbrixandersen
+/drivers/led_strip/                       @mbolivar-ampere
+/drivers/mfd/mfd_ad559x.c                 @bbilas
+/drivers/mfd/mfd_max20335.c               @bbilas
+/drivers/misc/ft8xx/                      @hubertmis
+/drivers/modem/hl7800.c                   @rerickson1
+/drivers/modem/simcom-sim7080.c           @lgehreke
+/drivers/modem/simcom-sim7080.h           @lgehreke
+/drivers/modem/Kconfig.hl7800             @rerickson1
+/drivers/modem/Kconfig.simcom-sim7080     @lgehreke
+/drivers/pinctrl/*esp32*                  @sylvioalves
+/drivers/pinctrl/*it8xxx2*                @ite
+/drivers/pinctrl/*kb1200*                 @ene-steven
+/drivers/pm_cpu_ops/psci_shell.c          @nbalabak @gdengi
+/drivers/power_domain/                    @ceolin
+/drivers/ps2/*xec*                        @franciscomunoz @sjvasanth1
+/drivers/ps2/*npcx*                       @MulinChao @ChiHuaL
+/drivers/pwm/*b91*                        @andy-liu-telink
+/drivers/pwm/*pca9685*                    @nixward
+/drivers/pwm/*rpi_pico*                   @burumaj
+/drivers/pwm/*rv32m1*                     @henrikbrixandersen
+/drivers/pwm/*sam0*                       @nzmichaelh
+/drivers/pwm/*test*                       @JordanYates
+/drivers/pwm/*xlnx*                       @henrikbrixandersen
+/drivers/pwm/pwm_capture.c                @henrikbrixandersen
+/drivers/pwm/pwm_shell.c                  @henrikbrixandersen
+/drivers/pwm/*gecko*                      @sun681
+/drivers/pwm/*it8xxx2*                    @RuibinChang
+/drivers/pwm/*esp32*                      @LucasTambor
+/drivers/pwm/*rcar*                       @aaillet
+/drivers/pwm/*max31790*                   @benediktibk
+/drivers/pwm/*kb1200*                     @ene-steven
+/drivers/regulator/*                      @gmarull
+/drivers/regulator/regulator_max20335.c   @bbilas
+/drivers/regulator/regulator_pca9420.c    @danieldegrasse
+/drivers/regulator/regulator_rpi_pico.c   @soburi
+/drivers/regulator/regulator_shell.c      @danieldegrasse
+/drivers/reset/reset_intel_socfpga.c      @nbalabak
+/drivers/reset/Kconfig.intel_socfpga      @nbalabak
+/drivers/sensor/ams_iAQcore/              @alexanderwachter
+/drivers/sensor/ens210/                   @alexanderwachter
+/drivers/sensor/grow_r502a/               @DineshDK03
+/drivers/sensor/hts*/                     @avisconti
+/drivers/sensor/ina23*/                   @bbilas
+/drivers/sensor/lis*/                     @avisconti
+/drivers/sensor/lps*/                     @avisconti
+/drivers/sensor/lsm*/                     @avisconti
+/drivers/sensor/mpr/                      @sven-hm
+/drivers/sensor/qdec_stm32/               @valeriosetti
+/drivers/sensor/rpi_pico_temp/            @soburi
+/drivers/sensor/st*/                      @avisconti
+/drivers/sensor/veaa_x_3/                 @jeppenodgaard @MaureenHelm
+/drivers/sensor/ene_tack_kb1200/          @ene-steven
+/drivers/serial/*b91*                     @andy-liu-telink
+/drivers/serial/uart_altera_jtag.c        @nashif @gohshunjing
+/drivers/serial/uart_altera.c             @gohshunjing
+/drivers/serial/*ns16550*                 @dcpleung @nashif @gdengi
+/drivers/serial/*nrfx*                    @anangl
+/drivers/serial/Kconfig.mcux_iuart        @Mani-Sadhasivam
+/drivers/serial/uart_mcux_iuart.c         @Mani-Sadhasivam
+/drivers/serial/Kconfig.rtt               @carlescufi @pkral78
+/drivers/serial/uart_rtt.c                @carlescufi @pkral78
+/drivers/serial/*rpi_pico*                @yonsch
+/drivers/serial/Kconfig.xlnx              @wjliang
+/drivers/serial/uart_xlnx_ps.c            @wjliang
+/drivers/serial/uart_xlnx_uartlite.c      @henrikbrixandersen
+/drivers/serial/*xmc4xxx*                 @parthitce
+/drivers/serial/*numicro*                 @ssekar15
+/drivers/serial/*apbuart*                 @julius-barendt
+/drivers/serial/*rcar*                    @aaillet
+/drivers/serial/Kconfig.xen               @lorc @firscity
+/drivers/serial/uart_hvc_xen.c            @lorc @firscity
+/drivers/serial/uart_hvc_xen_consoleio.c  @lorc @firscity
+/drivers/serial/Kconfig.it8xxx2           @GTLin08
+/drivers/serial/uart_ite_it8xxx2.c        @GTLin08
+/drivers/serial/*intel_lw*                @shilinte
+/drivers/serial/*kb1200*                  @ene-steven
+/drivers/disk/sdmmc_stm32.c               @anthonybrandon
+/drivers/ptp_clock/                       @tbursztyka @jukkar
+/drivers/spi/*b91*                        @andy-liu-telink
+/drivers/spi/spi_rv32m1_lpspi*            @karstenkoenig
+/drivers/spi/*esp32*                      @sylvioalves
+/drivers/spi/*pl022*                      @soburi
+/drivers/sdhc/                            @danieldegrasse
+/drivers/sdhc/sdhc_cdns*                  @roymurlidhar @tanmaykathpalia
+/drivers/timer/*arm_arch*                 @carlocaione
+/drivers/timer/*cortex_m_systick*         @anangl
+/drivers/timer/*altera_avalon*            @nashif
+/drivers/timer/*riscv_machine*            @kgugala @pgielda
+/drivers/timer/*ite_it8xxx2*              @ite
+/drivers/timer/*xlnx_psttc*               @wjliang @stephanosio
+/drivers/timer/*cc13xx_cc26xx_rtc*        @vanti
+/drivers/timer/*cavs*                     @dcpleung
+/drivers/timer/*leon_gptimer*             @julius-barendt
+/drivers/timer/*mips_cp0*                 @frantony
+/drivers/timer/*rcar_cmt*                 @aaillet
+/drivers/timer/*esp32_sys*                @uLipe
+/drivers/timer/*sam0_rtc*                 @bendiscz
+/drivers/timer/*xtensa*                   @dcpleung
+/drivers/timer/*rv32m1_lptmr*             @mbolivar
+/drivers/timer/*nrf_rtc*                  @anangl
+/drivers/timer/*hpet*                     @dcpleung
+/drivers/usb/device/usb_dc_stm32.c        @ydamigos @loicpoulain
+/drivers/i2c/*b91*                        @andy-liu-telink
+/drivers/i2c/i2c_ll_stm32*                @ydamigos
+/drivers/i2c/i2c_rv32m1_lpi2c*            @henrikbrixandersen
+/drivers/i2c/*sam0*                       @Sizurka
+/drivers/i2c/i2c_dw*                      @dcpleung
+/drivers/i2c/*tca954x*                    @kurddt
+/drivers/*/*xec*                          @franciscomunoz @albertofloyd @sjvasanth1
+/drivers/watchdog/*gecko*                 @oanerer
+/drivers/watchdog/*sifive*                @katsuster
+/drivers/watchdog/wdt_handlers.c          @dcpleung @nashif
+/drivers/watchdog/*cc32xx*                @pavlohamov
+/drivers/watchdog/wdt_ite_it8xxx2.c       @RuibinChang
+/drivers/watchdog/Kconfig.it8xxx2         @RuibinChang
+/drivers/watchdog/wdt_counter.c           @nordic-krch
+/drivers/watchdog/*rpi_pico*              @thedjnK
+/drivers/watchdog/*dw*                    @softwarecki @pbalsundar
+/drivers/watchdog/*ifx*                   @sreeramIfx
+/drivers/watchdog/*kb1200*                @ene-steven
+/drivers/wifi/esp_at/                     @mniestroj
+/drivers/wifi/eswifi/                     @loicpoulain @nandojve
+/drivers/wifi/winc1500/                   @kludentwo
+/drivers/virtualization/		  @tbursztyka
+/dts/arm/acsip/                           @NorthernDean
+/dts/arm/aspeed/                          @aspeeddylan
+/dts/arm/atmel/                           @galak @nandojve
+/dts/arm/broadcom/                        @sbranden
+/dts/arm/cypress/                         @ifyall @npal-cy
+/dts/arm/ene/kb1200                       @ene-steven
+/dts/arm/gd/                              @nandojve
+/dts/arm/infineon/xmc4*                   @parthitce @ifyall @npal-cy
+/dts/arm/infineon/psoc6/                  @ifyall @npal-cy
+/dts/arm64/armv8-r.dtsi                   @povergoing
+/dts/arm64/intel/*intel_socfpga*          @siclim
+/dts/arm64/nxp/                           @JiafeiPan
+/dts/arm64/renesas/                       @lorc @xakep-amatop
+/dts/arm/quicklogic/                      @fkokosinski @kgugala
+/dts/arm/seeed_studio/                    @str4t0m
+/dts/arm/st/h7/*stm32h735*                @benediktibk
+/dts/arm/st/l4/*stm32l451*                @benediktibk
+/dts/arm/ti/cc13?2*                       @bwitherspoon
+/dts/arm/ti/cc26?2*                       @bwitherspoon
+/dts/arm/ti/cc3235*                       @vanti
+/dts/arm/nordic/                          @anangl @carlescufi
+/dts/arm/nuvoton/                         @ssekar15 @MulinChao @ChiHuaL
+/dts/arm/nxp/                             @mmahadevan108 @dleach02
+/dts/arm/nxp/nxp_s32*                     @manuargue
+/dts/arm/microchip/                       @franciscomunoz @albertofloyd @sjvasanth1
+/dts/arm/rpi_pico/                        @yonsch
+/dts/arm/silabs/efm32_pg_1b.dtsi          @rdmeneze
+/dts/arm/silabs/efm32gg11b*               @oanerer
+/dts/arm/silabs/efr32bg13p*               @mnkp
+/dts/arm/silabs/efr32bg22*                @kgugala @fkokosinski @pczarnecki
+/dts/arm/silabs/efr32xg13p*               @mnkp
+/dts/arm/silabs/efm32pg1b*                @rdmeneze
+/dts/arm/silabs/efr32mg21*                @l-alfred
+/dts/arm/silabs/efr32fg13*                @yonsch
+/dts/riscv/ite/                           @ite
+/dts/riscv/microchip/microchip-miv.dtsi   @galak
+/dts/riscv/openisa/rv32m1*                @dleach02
+/dts/riscv/starfive/                      @rajnesh-kanwal @pfarwsi
+/dts/riscv/andes/andes_v5*                @cwshu @kevinwang821020 @jimmyzhe
+/dts/riscv/niosv/                         @sweeaun
+/dts/arm/armv*m.dtsi                      @galak @ioannisg
+/dts/arm/armv7-a.dtsi                     @ibirnbaum
+/dts/arm/armv7-r.dtsi                     @bbolen @stephanosio
+/dts/arm/xilinx/                          @bbolen @stephanosio
+/dts/arm/renesas/rcar/                    @aaillet
+/dts/xtensa/xtensa.dtsi                   @ydamigos
+/dts/xtensa/intel/                        @dcpleung
+/dts/xtensa/espressif/                    @sylvioalves
+/dts/xtensa/nxp/                          @iuliana-prodan @dbaluta
+/dts/bindings/can/                        @alexanderwachter @henrikbrixandersen
+/dts/bindings/i2c/zephyr*i2c-emul*.yaml   @sjg20
+/dts/bindings/adc/st*stm32-adc.yaml       @cybertale
+/dts/bindings/adc/*ads114s08.yaml         @benediktibk
+/dts/bindings/adc/*max111*                @benediktibk
+/dts/bindings/modem/*hl7800.yaml          @rerickson1
+/dts/bindings/serial/ns16550.yaml         @dcpleung @nashif
+/dts/bindings/counter/snps,dw-timers.yaml @pbalsundar
+/dts/bindings/wifi/*esp-at.yaml           @mniestroj
+/dts/bindings/*/*gd32*                    @nandojve
+/dts/bindings/*/*sam*                     @nandojve
+/dts/bindings/*/*npcx*                    @MulinChao @ChiHuaL
+/dts/bindings/*/*psoc6*                   @ifyall @npal-cy
+/dts/bindings/*/*infineon*cat1*           @ifyall @npal-cy
+/dts/bindings/*/nordic*                   @anangl
+/dts/bindings/*/nxp*                      @mmahadevan108 @dleach02
+/dts/bindings/*/nxp*s32*                  @manuargue
+/dts/bindings/*/openisa*                  @dleach02
+/dts/bindings/*/raspberrypi*pico*         @yonsch
+/dts/bindings/sensor/ams*                 @alexanderwachter
+/dts/bindings/*/sifive*                   @mateusz-holenko @kgugala @pgielda
+/dts/bindings/*/andes*                    @cwshu @kevinwang821020 @jimmyzhe
+/dts/bindings/*/neorv32*                  @henrikbrixandersen
+/dts/bindings/*/*lan91c111*               @sgrrzhf
+/dts/bindings/i3c/                        @dcpleung
+/dts/bindings/pm_cpu_ops/*                @carlocaione
+/dts/bindings/ethernet/*gem.yaml          @ibirnbaum
+/dts/bindings/auxdisplay/*pt6314.yaml     @xingrz
+/dts/bindings/auxdisplay/*                 @thedjnK
+/dts/bindings/sensor/*bme680*             @BoschSensortec
+/dts/bindings/sensor/*ina23*              @bbilas
+/dts/bindings/sensor/st*                  @avisconti
+/dts/bindings/sensor/zephyr,sensing.yaml    @lixuzha @ghu0510 @qianruh
+/dts/bindings/sensor/zephyr,sensing*.yaml   @lixuzha @ghu0510 @qianruh
+/dts/bindings/smbus/                      @finikorg
+/dts/bindings/sip_svc/                    @maheshraotm
+/dts/bindings/cpu/intel,niosv.yaml        @sweeaun
+/dts/bindings/reset/intel,socfpga-reset.yaml    @nbalabak
+/dts/bindings/gpio/*pcal64*               @benediktibk
+/dts/bindings/gpio/*bd8lb600fs*           @benediktibk
+/dts/bindings/gpio/*ads114s0x*            @benediktibk
+/dts/bindings/pwm/*max31790*              @benediktibk
+/dts/bindings/dac/*ad56*                  @benediktibk

Kconfig.zephyr

@@ -17,13 +17,13 @@ osource "${APPLICATION_SOURCE_DIR}/VERSION"
 # Shield defaults should have precedence over board defaults, which should have
 # precedence over SoC defaults, so include them in that order.
 #
-# $ARCH and $KCONFIG_BOARD_DIR will be glob patterns when building documentation.
+# $ARCH and $BOARD_DIR will be glob patterns when building documentation.
 # This loads custom shields defconfigs (from BOARD_ROOT)
 osource "$(KCONFIG_BINARY_DIR)/Kconfig.shield.defconfig"
 # This loads Zephyr base shield defconfigs
 source "boards/shields/*/Kconfig.defconfig"
 
-osource "$(KCONFIG_BOARD_DIR)/Kconfig.defconfig"
+osource "$(BOARD_DIR)/Kconfig.defconfig"
 
 # This loads Zephyr specific SoC root defconfigs
 source "$(KCONFIG_BINARY_DIR)/soc/Kconfig.defconfig"
@@ -448,7 +448,6 @@ config CODING_GUIDELINE_CHECK
 config NATIVE_LIBC
 	bool
 	select FULL_LIBC_SUPPORTED
-	select TC_PROVIDES_POSIX_C_LANG_SUPPORT_R
 	help
 	  Zephyr will use the host system C library.
 
@@ -471,11 +470,9 @@ config NATIVE_APPLICATION
 	default y if ARCH_POSIX
 	depends on !NATIVE_LIBRARY
 	select NATIVE_BUILD
-	select DEPRECATED
 	help
 	  Build as a native application that can run on the host and using
-	  resources and libraries provided by the host. This option is deprecated
-	  and will be removed in Zephyr v4.3
+	  resources and libraries provided by the host.
 
 config NATIVE_LIBRARY
 	bool
@@ -539,10 +536,11 @@ config NO_OPTIMIZATIONS
 endchoice
 
 config LTO
-	bool "Link Time Optimization"
+	bool "Link Time Optimization [EXPERIMENTAL]"
 	depends on !(GEN_ISR_TABLES || GEN_IRQ_VECTOR_TABLE) || ISR_TABLES_LOCAL_DECLARATION
 	depends on !NATIVE_LIBRARY
 	depends on !CODE_DATA_RELOCATION
+	select EXPERIMENTAL
 	help
 	  This option enables Link Time Optimization.
 
@@ -709,21 +707,8 @@ config CLEANUP_INTERMEDIATE_FILES
 	  from the build process. Note this breaks incremental builds, west spdx
 	  (Software Bill of Material generation), and maybe others.
 
-config BUILD_GAP_FILL_PATTERN
-	hex "Gap fill pattern"
-	default 0xFF
-	help
-	  Pattern used for gap filling of output files.
-	  This value should be set to the value of a clean flash as this can
-	  significantly reduce flash write times.
-	  This setting only defines the gap fill pattern and doesn't enable gap
-	  filling.
-	  Note: binary files are always gap filled as they contain no address
-	  information.
-
 config BUILD_NO_GAP_FILL
-	bool "Don't fill gaps in generated hex/s19 files [DEPRECATED]."
-	select DEPRECATED
+	bool "Don't fill gaps in generated hex/bin/s19 files."
 
 config BUILD_OUTPUT_HEX
 	bool "Build a binary in HEX format"
@@ -731,12 +716,6 @@ config BUILD_OUTPUT_HEX
 	  Build an Intel HEX binary zephyr/zephyr.hex in the build directory.
 	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
 
-config BUILD_OUTPUT_HEX_GAP_FILL
-	bool "Fill gaps in hex files"
-	depends on !BUILD_NO_GAP_FILL
-	help
-	  Fill gaps in hex based files.
-
 config BUILD_OUTPUT_BIN
 	bool "Build a binary in BIN format"
 	default y
@@ -771,12 +750,6 @@ config BUILD_OUTPUT_S19
 	  Build an S19 binary zephyr/zephyr.s19 in the build directory.
 	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
 
-config BUILD_OUTPUT_S19_GAP_FILL
-	bool "Fill gaps in s19 files"
-	depends on !BUILD_NO_GAP_FILL
-	help
-	  Fill gaps in s19 based files.
-
 config BUILD_OUTPUT_UF2
 	bool "Build a binary in UF2 format"
 	depends on BUILD_OUTPUT_BIN
@@ -793,8 +766,7 @@ config BUILD_OUTPUT_UF2_FAMILY_ID
 	default "0xada52840" if SOC_NRF52840_QIAA
 	default "0x4fb2d5bd" if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
 	default "0x2abc77ec" if SOC_SERIES_LPC55XXX
-	default "0xe48bff56" if SOC_SERIES_RP2040
-	default "0xe48bff57" if SOC_SERIES_RP2350
+	default "0xe48bff56" if SOC_SERIES_RP2XXX
 	default "0x68ed2b88" if SOC_SERIES_SAMD21
 	default "0x55114460" if SOC_SERIES_SAMD51
 	default "0x647824b6" if SOC_SERIES_STM32F0X
@@ -1050,6 +1022,32 @@ config IS_BOOTLOADER
 	  This option indicates that Zephyr will act as a bootloader to execute
 	  a separate Zephyr image payload.
 
+config BOOTLOADER_SRAM_SIZE
+	int "SRAM reserved for bootloader [DEPRECATED]"
+	default 0
+	depends on !XIP || IS_BOOTLOADER
+	depends on ARM || XTENSA
+	help
+	  This option specifies the amount of SRAM (measure in kB) reserved for
+	  a bootloader image, when either:
+	  - the Zephyr image itself is to act as the bootloader, or
+	  - Zephyr is a !XIP image, which implicitly assumes existence of a
+	  bootloader that loads the Zephyr !XIP image onto SRAM.
+
+	  This option is deprecated, users should transition to using DTS to set this, if needed.
+	  To be removed after Zephyr 3.7 release.
+
+config BOOTLOADER_SRAM_SIZE_DEPRECATED
+	bool
+	default y
+	select DEPRECATED
+	depends on BOOTLOADER_SRAM_SIZE != 0
+	depends on !XIP || IS_BOOTLOADER
+	depends on ARM || XTENSA
+	help
+	  Non-prompt symbol to indicate that the deprecated BOOTLOADER_SRAM_SIZE Kconfig has a
+	  non-0 value. Please transition to using devicetree.
+
 config BOOTLOADER_BOSSA
 	bool "BOSSA bootloader support"
 	select USE_DT_CODE_PARTITION

SDK_VERSION

@@ -1 +1 @@
-0.17.0
+0.16.8

VERSION

@@ -1,5 +1,5 @@
-VERSION_MAJOR = 4
-VERSION_MINOR = 1
-PATCHLEVEL = 0
+VERSION_MAJOR = 3
+VERSION_MINOR = 7
+PATCHLEVEL = 99
 VERSION_TWEAK = 0
 EXTRAVERSION =

arch/Kconfig

@@ -50,12 +50,11 @@ config ARM64
 	select ARCH_HAS_THREAD_LOCAL_STORAGE
 	select USE_SWITCH
 	select USE_SWITCH_SUPPORTED
+	select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
 	select BARRIER_OPERATIONS_ARCH
 	select ARCH_HAS_DIRECTED_IPIS
 	select ARCH_HAS_DEMAND_PAGING
 	select ARCH_HAS_DEMAND_MAPPING
-	select ARCH_SUPPORTS_EVICTION_TRACKING
-	select EVICTION_TRACKING if DEMAND_PAGING
 	help
 	  ARM64 (AArch64) architecture
 
@@ -94,6 +93,7 @@ config X86
 	select ARCH_HAS_THREAD_LOCAL_STORAGE
 	select ARCH_HAS_DEMAND_PAGING if !X86_64
 	select ARCH_HAS_DEMAND_MAPPING if ARCH_HAS_DEMAND_PAGING
+	select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
 	select NEED_LIBC_MEM_PARTITION if USERSPACE && TIMING_FUNCTIONS \
 					  && !BOARD_HAS_TIMING_FUNCTIONS \
 					  && !SOC_HAS_TIMING_FUNCTIONS
@@ -121,6 +121,7 @@ config RISCV
 	select ARCH_SUPPORTS_EMPTY_IRQ_SPURIOUS
 	select ARCH_HAS_CODE_DATA_RELOCATION
 	select ARCH_HAS_THREAD_LOCAL_STORAGE
+	select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
 	select USE_SWITCH_SUPPORTED
 	select USE_SWITCH
 	select SCHED_IPI_SUPPORTED if SMP
@@ -135,6 +136,7 @@ config XTENSA
 	select ARCH_IS_SET
 	select USE_SWITCH
 	select USE_SWITCH_SUPPORTED
+	select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
 	select ARCH_HAS_CODE_DATA_RELOCATION
 	select ARCH_HAS_TIMING_FUNCTIONS
 	select ARCH_MEM_DOMAIN_DATA if USERSPACE
@@ -449,8 +451,9 @@ config ISR_TABLES_LOCAL_DECLARATION_SUPPORTED
 	depends on "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" || "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "gnuarmemb"
 
 config ISR_TABLES_LOCAL_DECLARATION
-	bool "ISR tables created locally and placed by linker"
+	bool "ISR tables created locally and placed by linker [EXPERIMENTAL]"
 	depends on ISR_TABLES_LOCAL_DECLARATION_SUPPORTED
+	select EXPERIMENTAL
 	help
 	  Enable new scheme of interrupt tables generation.
 	  This is totally different generator that would create tables entries locally
@@ -576,12 +579,11 @@ config IRQ_OFFLOAD
 config IRQ_OFFLOAD_NESTED
 	bool "irq_offload() supports nested IRQs"
 	depends on IRQ_OFFLOAD
-	default y if ARM64 || X86 || RISCV || XTENSA
 	help
-	  When set by the platform layers, indicates that
-	  irq_offload() may legally be called in interrupt context to
-	  cause a synchronous nested interrupt on the current CPU.
-	  Not all hardware is capable.
+	  When set by the arch layer, indicates that irq_offload() may
+	  legally be called in interrupt context to cause a
+	  synchronous nested interrupt on the current CPU.  Not all
+	  hardware is capable.
 
 config EXCEPTION_DEBUG
 	bool "Unhandled exception debugging"
@@ -692,12 +694,6 @@ config ARCH_SUPPORTS_ROM_START
 config ARCH_SUPPORTS_EMPTY_IRQ_SPURIOUS
 	bool
 
-config ARCH_SUPPORTS_EVICTION_TRACKING
-	bool
-	help
-	  Architecture code supports page tracking for eviction algorithms
-	  when demand paging is enabled.
-
 config ARCH_HAS_EXTRA_EXCEPTION_INFO
 	bool
 
@@ -1144,9 +1140,3 @@ config ARCH_HAS_CUSTOM_BUSY_WAIT
 	  It's possible that an architecture port cannot or does not want to use
 	  the provided k_busy_wait(), but instead must do something custom. It must
 	  enable this option in that case.
-
-config ARCH_HAS_CUSTOM_CURRENT_IMPL
-	bool
-	help
-	  Select when architecture implements arch_current_thread() &
-	  arch_current_thread_set().

arch/arc/Kconfig

@@ -262,7 +262,7 @@ config ARC_CURRENT_THREAD_USE_NO_TLS
 	  RGF_NUM_BANKS the parameter is disabled by-default because banks syncronization
 	  requires significant time, and it slows down performance.
 	  ARCMWDT works with tls pointer in different way then GCC. Optimized access to
-	  TLS pointer via the _current symbol does not provide significant advantages
+	  TLS pointer via _current variable does not provide significant advantages
 	  in case of MetaWare.
 
 config GEN_ISR_TABLES
@@ -343,15 +343,6 @@ config ARC_NORMAL_FIRMWARE
 	  resources of the ARC processors, and, therefore, it shall avoid
 	  accessing them.
 
-config ARC_VPX_COOPERATIVE_SHARING
-	bool "Cooperative sharing of ARC VPX vector registers"
-	select SCHED_CPU_MASK if MP_MAX_NUM_CPUS > 1
-	help
-	  This option enables the cooperative sharing of the ARC VPX vector
-	  registers. Threads that want to use those registers must successfully
-	  call arc_vpx_lock() before using them, and call arc_vpx_unlock()
-	  when done using them.
-
 source "arch/arc/core/dsp/Kconfig"
 
 menu "ARC MPU Options"
@@ -383,7 +374,9 @@ config ARC_EXCEPTION_STACK_SIZE
 endmenu
 
 config ARC_EARLY_SOC_INIT
-	bool "Make early stage SoC-specific initialization"
+	bool "Make early stage SoC-specific initialization [DEPRECATED]"
+	select SOC_RESET_HOOK
+	select DEPRECATED
 	help
 	  Call SoC per-core setup code on early stage initialization
 	  (before C runtime initialization). Setup code is called in form of

arch/arc/core/CMakeLists.txt

@@ -34,5 +34,3 @@ add_subdirectory_ifdef(CONFIG_ARC_CORE_MPU mpu)
 add_subdirectory_ifdef(CONFIG_ARC_SECURE_FIRMWARE secureshield)
 
 zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)
-
-zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c)

arch/arc/core/elf.c

@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2024 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/llext/elf.h>
-#include <zephyr/llext/llext.h>
-#include <zephyr/llext/loader.h>
-#include <zephyr/logging/log.h>
-#include <zephyr/sys/util.h>
-
-LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL);
-
-#define R_ARC_32            4
-#define R_ARC_B26           5 /* AKA R_ARC_64 */
-#define R_ARC_S25W_PCREL    17
-#define R_ARC_32_ME         27
-
-/* ARCompact insns packed in memory have Middle Endian encoding */
-#define ME(x) (((x & 0xffff0000) >> 16) | ((x & 0xffff) << 16))
-
-/**
- * @brief Architecture specific function for relocating shared elf
- *
- * Elf files contain a series of relocations described in multiple sections.
- * These relocation instructions are architecture specific and each architecture
- * supporting modules must implement this.
- *
- * The relocation codes are well documented:
- * https://github.com/foss-for-synopsys-dwc-arc-processors/arc-ABI-manual/blob/master/ARCv2_ABI.pdf
- * https://github.com/zephyrproject-rtos/binutils-gdb
- */
-int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr, const char *sym_name,
-		      uintptr_t load_bias)
-{
-	int ret = 0;
-	uint32_t insn = UNALIGNED_GET((uint32_t *)loc);
-	uint32_t value;
-
-	sym_base_addr += rel->r_addend;
-
-	int reloc_type = ELF32_R_TYPE(rel->r_info);
-
-	switch (reloc_type) {
-	case R_ARC_32:
-	case R_ARC_B26:
-		UNALIGNED_PUT(sym_base_addr, (uint32_t *)loc);
-		break;
-	case R_ARC_S25W_PCREL:
-		/* ((S + A) - P) >> 2
-		 * S = symbol address
-		 * A = addend
-		 * P = relative offset to PCL
-		 */
-		value = (sym_base_addr + rel->r_addend - (loc & ~0x3)) >> 2;
-
-		insn = ME(insn);
-
-		/* disp25w */
-		insn = insn & ~0x7fcffcf;
-		insn |= ((value >> 0) & 0x01ff) << 18;
-		insn |= ((value >> 9) & 0x03ff) << 6;
-		insn |= ((value >> 19) & 0x000f) << 0;
-
-		insn = ME(insn);
-
-		UNALIGNED_PUT(insn, (uint32_t *)loc);
-		break;
-	case R_ARC_32_ME:
-		UNALIGNED_PUT(ME(sym_base_addr), (uint32_t *)loc);
-		break;
-	default:
-		LOG_ERR("unknown relocation: %u\n", reloc_type);
-		ret = -ENOEXEC;
-		break;
-	}
-
-	return ret;
-}

arch/arc/core/fault.c

@@ -346,7 +346,7 @@ static void dump_exception_info(uint32_t vector, uint32_t cause, uint32_t parame
  * invokes the user provided routine k_sys_fatal_error_handler() which is
  * responsible for implementing the error handling policy.
  */
-void z_arc_fault(struct arch_esf *esf, uint32_t old_sp)
+void _Fault(struct arch_esf *esf, uint32_t old_sp)
 {
 	uint32_t vector, cause, parameter;
 	uint32_t exc_addr = z_arc_v2_aux_reg_read(_ARC_V2_EFA);

arch/arc/core/fault_s.S

@@ -19,7 +19,7 @@
 #include <zephyr/syscall.h>
 #include <zephyr/arch/arc/asm-compat/assembler.h>
 
-GTEXT(z_arc_fault)
+GTEXT(_Fault)
 GTEXT(__reset)
 GTEXT(__memory_error)
 GTEXT(__instruction_error)
@@ -99,11 +99,11 @@ _exc_entry:
 
 	_save_exc_regs_into_stack
 
-	/* sp is parameter of z_arc_fault */
+	/* sp is parameter of _Fault */
 	MOVR r0, sp
 	/* ilink is the thread's original sp */
 	MOVR r1, ilink
-	jl z_arc_fault
+	jl _Fault
 
 _exc_return:
 /* the exception cause must be fixed in exception handler when exception returns

arch/arc/core/reset.S

@@ -16,8 +16,9 @@
 #include <zephyr/arch/cpu.h>
 #include <swap_macros.h>
 #include <zephyr/arch/arc/asm-compat/assembler.h>
-#ifdef CONFIG_ARC_EARLY_SOC_INIT
-  #include <soc_ctrl.h>
+
+#if defined(CONFIG_SOC_RESET_HOOK)
+GTEXT(soc_reset_hook)
 #endif
 
 GDATA(z_interrupt_stacks)
@@ -112,8 +113,8 @@ done_icache_invalidate:
 
 done_dcache_invalidate:
 
-#ifdef CONFIG_ARC_EARLY_SOC_INIT
-	soc_early_asm_init_percpu
+#ifdef CONFIG_SOC_RESET_HOOK
+	bl soc_reset_hook
 #endif
 
 	_dsp_extension_probe

arch/arc/core/smp.c

@@ -16,7 +16,6 @@
 #include <ipi.h>
 #include <zephyr/init.h>
 #include <zephyr/irq.h>
-#include <zephyr/platform/hooks.h>
 #include <arc_irq_offload.h>
 
 volatile struct {
@@ -116,11 +115,6 @@ void arch_secondary_cpu_init(int cpu_num)
 			   DT_IRQ(DT_NODELABEL(ici), priority), 0);
 	irq_enable(DT_IRQN(DT_NODELABEL(ici)));
 #endif
-
-#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
-	soc_per_core_init_hook();
-#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
-
 	/* call the function set by arch_cpu_start */
 	fn = arc_cpu_init[cpu_num].fn;
 

arch/arc/core/thread.c

@@ -19,15 +19,10 @@
 #include <zephyr/arch/arc/v2/mpu/arc_core_mpu.h>
 #endif
 
-#if defined(CONFIG_ARC_VPX_COOPERATIVE_SHARING) || defined(CONFIG_DSP_SHARING)
+#if defined(CONFIG_ARC_DSP) && defined(CONFIG_DSP_SHARING)
 #include <zephyr/arch/arc/v2/dsp/arc_dsp.h>
 static struct k_spinlock lock;
 #endif
-
-#if defined(CONFIG_ARC_VPX_COOPERATIVE_SHARING)
-static struct k_sem vpx_sem[CONFIG_MP_MAX_NUM_CPUS];
-#endif
-
 /*  initial stack frame */
 struct init_stack_frame {
 	uintptr_t pc;
@@ -325,65 +320,3 @@ void arc_dsp_enable(struct k_thread *thread, unsigned int options)
 	k_spin_unlock(&lock, key);
 }
 #endif /* CONFIG_ARC_DSP && CONFIG_DSP_SHARING */
-
-#if defined(CONFIG_ARC_VPX_COOPERATIVE_SHARING)
-int arc_vpx_lock(k_timeout_t timeout)
-{
-	k_spinlock_key_t key;
-	unsigned int id;
-
-	key = k_spin_lock(&lock);
-
-	id = _current_cpu->id;
-#if (CONFIG_MP_MAX_NUM_CPUS > 1) && defined(CONFIG_SCHED_CPU_MASK)
-	__ASSERT(!arch_is_in_isr() && (_current->base.cpu_mask == BIT(id)), "");
-#endif
-	k_spin_unlock(&lock, key);
-
-	/*
-	 * It is assumed that the thread is (still) pinned to
-	 * the same CPU identified by <id>.
-	 */
-
-	return k_sem_take(&vpx_sem[id], timeout);
-}
-
-void arc_vpx_unlock(void)
-{
-	k_spinlock_key_t key;
-	unsigned int id;
-
-	key = k_spin_lock(&lock);
-#if (CONFIG_MP_MAX_NUM_CPUS > 1) && defined(CONFIG_SCHED_CPU_MASK)
-	__ASSERT(!arch_is_in_isr() && (_current->base.cpu_mask == BIT(id)), "");
-#endif
-	id = _current_cpu->id;
-	k_spin_unlock(&lock, key);
-
-	/*
-	 * It is assumed that this thread is (still) pinned to
-	 * the CPU identified by <id>, and that it is the same CPU
-	 * used by arc_vpx_lock().
-	 */
-
-	k_sem_give(&vpx_sem[id]);
-}
-
-void arc_vpx_unlock_force(unsigned int id)
-{
-	__ASSERT(id < CONFIG_MP_MAX_NUM_CPUS, "");
-
-	k_sem_give(&vpx_sem[id]);
-}
-
-static int arc_vpx_sem_init(void)
-{
-	for (unsigned int i = 0; i < CONFIG_MP_MAX_NUM_CPUS; i++) {
-		k_sem_init(vpx_sem, 1, 1);
-	}
-
-	return 0;
-}
-
-SYS_INIT(arc_vpx_sem_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS);
-#endif

arch/arc/include/kernel_arch_func.h

@@ -26,8 +26,6 @@
 
 #include <v2/irq.h>
 
-#include <zephyr/platform/hooks.h>
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -35,10 +33,6 @@ extern "C" {
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
 	z_irq_setup();
-
-#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
-	soc_per_core_init_hook();
-#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 

arch/arm/Kconfig

@@ -155,12 +155,12 @@ config CPU_HAS_ARM_MPU
 	  This option is enabled when the CPU has a Memory Protection Unit (MPU)
 	  in ARM flavor.
 
-config CPU_HAS_NXP_SYSMPU
+config CPU_HAS_NXP_MPU
 	bool
 	select CPU_HAS_MPU
 	help
-	  This option is enabled when the CPU has an NXP System Memory Protection
-	  Unit (SYSMPU).
+	  This option is enabled when the CPU has a Memory Protection Unit (MPU)
+	  in NXP flavor.
 
 config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
 	bool "Custom fixed SoC MPU region definition"

arch/arm/core/cortex_a_r/CMakeLists.txt

@@ -24,4 +24,4 @@ zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c)
 zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE __aeabi_read_tp.S)
 zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c)
 zephyr_library_sources_ifdef(CONFIG_USE_SWITCH switch.S)
-zephyr_library_sources_ifndef(CONFIG_USE_SWITCH swap_helper.S exc_exit.S)
+zephyr_library_sources_ifndef(CONFIG_USE_SWITCH swap.c swap_helper.S exc_exit.S)

arch/arm/core/cortex_a_r/Kconfig

@@ -93,14 +93,6 @@ config CPU_CORTEX_R7
 	help
 	  This option signifies the use of a Cortex-R7 CPU
 
-config CPU_CORTEX_R8
-	bool
-	select CPU_AARCH32_CORTEX_R
-	select ARMV7_R
-	select ARMV7_R_FP if CPU_HAS_FPU
-	help
-	  This option signifies the use of a Cortex-R8 CPU
-
 config CPU_CORTEX_R52
 	bool
 	select CPU_AARCH32_CORTEX_R
@@ -111,32 +103,6 @@ config CPU_CORTEX_R52
 	help
 	  This option signifies the use of a Cortex-R52 CPU
 
-config CPU_CORTEX_R52_CACHE_SEGREGATION
-	bool "Control segregation of L1 I/D-Cache ways between Flash and AXIM"
-	depends on CPU_CORTEX_R52
-	help
-	  Control segregation of L1 I/D-Cache ways between Flash and AXIM.
-	  Updates to the cache segregation controls are only permitted before the caches
-	  have ever been enabled, following a system reset, otherwise the update is ignored.
-
-config CPU_CORTEX_R52_ICACHE_FLASH_WAY
-	int "L1 I-Cache Flash way"
-	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
-	range 0 4
-	default 0
-	help
-	  Configure L1 I-Cache ways for Flash interface. Default is reset value, all
-	  I-Cache ways are allocated for AXIM interface.
-
-config CPU_CORTEX_R52_DCACHE_FLASH_WAY
-	int "L1 D-Cache Flash way"
-	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
-	range 0 4
-	default 0
-	help
-	  Configure L1 D-Cache ways for Flash interface. Default is reset value,
-	  all D-Cache ways are allocated for AXIM interface.
-
 if CPU_AARCH32_CORTEX_R
 
 config ARMV7_R

arch/arm/core/cortex_a_r/__aeabi_read_tp.S

@@ -14,5 +14,5 @@ SECTION_FUNC(text, __aeabi_read_tp)
 	/*
 	 * TPIDRURW will be used as a base pointer point to TLS aera.
 	 */
-	mrc p15, 0, r0, c13, c0, 2
+	mrc 15, 0, r0, c13, c0, 2
 	bx lr

arch/arm/core/cortex_a_r/exc.S

@@ -237,28 +237,6 @@ SECTION_SUBSEC_FUNC(TEXT, __exc, z_arm_data_abort)
 	b z_arm_exc_exit
 
 #else
-
-GTEXT(z_arm_cortex_ar_exit_exc)
-SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_cortex_ar_exit_exc)
-
-	/* Note:
-	 * This function is expected to be *always* called with
-	 * processor mode set to MODE_SYS.
-	 */
-
-	/* decrement exception depth */
-	get_cpu r2
-	ldrb r1, [r2, #_cpu_offset_to_exc_depth]
-	sub r1, r1, #1
-	strb r1, [r2, #_cpu_offset_to_exc_depth]
-
-	/*
-	 * Restore r0-r3, r12, lr, lr_und and spsr_und from the exception stack
-	 * and return to the current thread.
-	 */
-	pop {r0-r3, r12, lr}
-	rfeia sp!
-
 /**
  * @brief Undefined instruction exception handler
  *

arch/arm/core/cortex_a_r/prep_c.c

@@ -1,6 +1,5 @@
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,6 +28,24 @@
 #include <cortex_a_r/stack.h>
 #endif
 
+#if defined(__GNUC__)
+/*
+ * GCC can detect if memcpy is passed a NULL argument, however one of
+ * the cases of relocate_vector_table() it is valid to pass NULL, so we
+ * suppress the warning for this case.  We need to do this before
+ * string.h is included to get the declaration of memcpy.
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wnonnull"
+#endif
+
+#include <string.h>
+
+#if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
+Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used))
+void *_vector_table_pointer;
+#endif
+
 #ifdef CONFIG_ARM_MPU
 extern void z_arm_mpu_init(void);
 extern void z_arm_configure_static_mpu_regions(void);
@@ -36,6 +53,38 @@ extern void z_arm_configure_static_mpu_regions(void);
 extern int z_arm_mmu_init(void);
 #endif
 
+#if defined(CONFIG_AARCH32_ARMV8_R)
+
+#define VECTOR_ADDRESS ((uintptr_t)_vector_start)
+
+static inline void relocate_vector_table(void)
+{
+	write_sctlr(read_sctlr() & ~HIVECS);
+	write_vbar(VECTOR_ADDRESS & VBAR_MASK);
+	barrier_isync_fence_full();
+}
+
+#else
+#define VECTOR_ADDRESS 0
+
+void __weak relocate_vector_table(void)
+{
+#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \
+	!defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
+	write_sctlr(read_sctlr() & ~HIVECS);
+	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
+	(void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size);
+#elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
+	_vector_table_pointer = _vector_start;
+#endif
+}
+
+#if defined(__GNUC__)
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* CONFIG_AARCH32_ARMV8_R */
+
 #if defined(CONFIG_CPU_HAS_FPU)
 
 static inline void z_arm_floating_point_init(void)
@@ -62,6 +111,7 @@ static inline void z_arm_floating_point_init(void)
 	__set_CPACR(reg_val);
 	barrier_isync_fence_full();
 
+#if !defined(CONFIG_FPU_SHARING)
 	/*
 	 * FPEXC: Floating-Point Exception Control register
 	 * comp. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition,
@@ -83,6 +133,7 @@ static inline void z_arm_floating_point_init(void)
 	 */
 	__set_FPEXC(FPEXC_EN);
 #endif
+#endif
 }
 
 #endif /* CONFIG_CPU_HAS_FPU */
@@ -104,6 +155,7 @@ void z_prep_c(void)
 	/* Initialize tpidruro with our struct _cpu instance address */
 	write_tpidruro((uintptr_t)&_kernel.cpus[0]);
 
+	relocate_vector_table();
 #if defined(CONFIG_CPU_HAS_FPU)
 	z_arm_floating_point_init();
 #endif

arch/arm/core/cortex_a_r/reboot.c

@@ -1,6 +1,5 @@
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,56 +12,6 @@
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/sys/util.h>
-#include <zephyr/linker/linker-defs.h>
-
-#if defined(CONFIG_AARCH32_ARMV8_R)
-
-#define VECTOR_ADDRESS ((uintptr_t)_vector_start)
-
-static inline void relocate_vector_table(void)
-{
-	write_sctlr(read_sctlr() & ~HIVECS);
-	write_vbar(VECTOR_ADDRESS & VBAR_MASK);
-	barrier_isync_fence_full();
-}
-
-#else
-
-#if defined(__GNUC__)
-/*
- * GCC can detect if memcpy is passed a NULL argument, however one of
- * the cases of relocate_vector_table() it is valid to pass NULL, so we
- * suppress the warning for this case.  We need to do this before
- * string.h is included to get the declaration of memcpy.
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wnonnull"
-#endif /* __GNUC__ */
-
-#include <string.h>
-
-#define VECTOR_ADDRESS 0
-
-void __weak relocate_vector_table(void)
-{
-#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) ||                                     \
-	!defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
-	write_sctlr(read_sctlr() & ~HIVECS);
-	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
-	(void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size);
-#endif
-}
-
-#if defined(__GNUC__)
-#pragma GCC diagnostic pop
-#endif
-
-#endif /* !CONFIG_AARCH32_ARMV8_R */
-
-void z_arm_relocate_vector_table(void)
-{
-	relocate_vector_table();
-}
 
 /**
  *

arch/arm/core/cortex_a_r/reset.S

@@ -1,7 +1,6 @@
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -56,12 +55,9 @@ SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)
     cmp r0, #MODE_HYP
     bne EL1_Reset_Handler
 
-    /*
-     * The HSCTLR register provides top-level control of system operation in Hyp mode.
-     * Since the OS is not running in Hyp mode, and considering the Armv8-R AArch32
-     * architecture profile, there's no need to modify HSCTLR configuration unless
-     * Fast Interrupts need to be enabled.
-     */
+    /* Init HSCTLR see Armv8-R AArch32 architecture profile */
+    ldr r0, =(HSCTLR_RES1 | SCTLR_I_BIT | SCTLR_C_BIT)
+    mcr p15, 4, r0, c1, c0, 0
 
     /* Init HACTLR: Enable EL1 access to all IMP DEF registers */
     ldr r0, =HACTLR_INIT
@@ -203,12 +199,6 @@ EL1_Reset_Handler:
 
 #endif /* CONFIG_DCLS */
 
-#if defined(CONFIG_CPU_CORTEX_R52_CACHE_SEGREGATION)
-    ldr r0, =IMP_CSCTLR(CONFIG_CPU_CORTEX_R52_ICACHE_FLASH_WAY,
-                        CONFIG_CPU_CORTEX_R52_DCACHE_FLASH_WAY)
-    mcr p15, 1, r0, c9, c1, 0
-#endif
-
     ldr r0, =arm_cpu_boot_params
 
 #if CONFIG_MP_MAX_NUM_CPUS > 1
@@ -329,6 +319,4 @@ _primary_core:
     bl z_arm_tcm_disable_ecc
 #endif
 
-    bl z_arm_relocate_vector_table
-
     bx r4

arch/arm/core/cortex_a_r/smp.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, 2024 Arm Limited (or its affiliates).
+ * Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -12,7 +12,6 @@
 #include "zephyr/cache.h"
 #include "zephyr/kernel/thread_stack.h"
 #include "zephyr/toolchain/gcc.h"
-#include <zephyr/platform/hooks.h>
 
 #define INV_MPID	UINT32_MAX
 
@@ -140,14 +139,10 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_
 	arm_cpu_boot_params.arg = arg;
 	arm_cpu_boot_params.cpu_num = cpu_num;
 
-	/* we need the barrier here to make sure the above changes to
-	 * arm_cpu_boot_params are completed before we set the mpid
-	 */
-	barrier_dsync_fence_full();
-
 	/* store mpid last as this is our synchronization point */
 	arm_cpu_boot_params.mpid = cpu_mpid;
 
+	barrier_dsync_fence_full();
 	sys_cache_data_invd_range(
 			(void *)&arm_cpu_boot_params,
 			sizeof(arm_cpu_boot_params));
@@ -199,10 +194,6 @@ void arch_secondary_cpu_init(void)
 	 */
 #endif
 
-#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
-	soc_per_core_init_hook();
-#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
-
 	fn = arm_cpu_boot_params.fn;
 	arg = arm_cpu_boot_params.arg;
 	barrier_dsync_fence_full();

arch/arm/core/cortex_a_r/swap.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018 Linaro, Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <kernel_internal.h>
+
+#include <errno.h>
+
+/* The 'key' actually represents the BASEPRI register
+ * prior to disabling interrupts via the BASEPRI mechanism.
+ *
+ * arch_swap() itself does not do much.
+ */
+int arch_swap(unsigned int key)
+{
+	/* store off key and return value */
+	_current->arch.basepri = key;
+	_current->arch.swap_return_value = -EAGAIN;
+
+	z_arm_cortex_r_svc();
+	irq_unlock(key);
+
+	/* Context switch is performed here. Returning implies the
+	 * thread has been context-switched-in again.
+	 */
+	return _current->arch.swap_return_value;
+}

arch/arm/core/cortex_a_r/swap_helper.S

@@ -126,7 +126,7 @@ out_fp_inactive:
      * TPIDRURW is used as a base pointer to all
      * thread variables with offsets added by toolchain.
      */
-    mcr p15, 0, r0, c13, c0, 2
+    mcr 15, 0, r0, c13, c0, 2
 #endif
 
 #if defined(CONFIG_ARM_STORE_EXC_RETURN)
@@ -336,14 +336,12 @@ _context_switch:
 
 _oops:
     /*
-     * Pass the exception frame to z_do_kernel_oops.
+     * Pass the exception frame to z_do_kernel_oops.  r0 contains the
+     * exception reason.
      */
     cps #MODE_SYS
     mov r0, sp
     cps #MODE_SVC
-    /* Zero callee_regs and exc_return (only used on Cortex-M) */
-    mov r1, #0
-    mov r2, #0
     bl z_do_kernel_oops
     b z_arm_int_exit
 
@@ -423,9 +421,5 @@ valid_syscall_id:
 
 GTEXT(z_arm_cortex_r_svc)
 SECTION_FUNC(TEXT, z_arm_cortex_r_svc)
-    .cfi_sections .debug_frame
-    .cfi_startproc simple
-    .cfi_def_cfa 13, 0x0
     svc #_SVC_CALL_CONTEXT_SWITCH
     bx lr
-    .cfi_endproc

arch/arm/core/cortex_a_r/switch.S

@@ -150,12 +150,10 @@ offload:
 
 _oops:
     /*
-     * Pass the exception frame to z_do_kernel_oops.
+     * Pass the exception frame to z_do_kernel_oops.  r0 contains the
+     * exception reason.
      */
     mov r0, sp
-    /* Zero callee_regs and exc_return (only used on Cortex-M) */
-    mov r1, #0
-    mov r2, #0
     bl z_do_kernel_oops
 
 inv:

arch/arm/core/cortex_a_r/vector_table.S

@@ -35,3 +35,27 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
 #else
 	ldr pc,=z_irq_spurious
 #endif
+
+
+#ifdef CONFIG_USE_SWITCH
+GTEXT(z_arm_cortex_ar_exit_exc)
+SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_cortex_ar_exit_exc)
+
+	/* Note:
+	 * This function is expected to be *always* called with
+	 * processor mode set to MODE_SYS.
+	 */
+
+	/* decrement exception depth */
+	get_cpu r2
+	ldrb r1, [r2, #_cpu_offset_to_exc_depth]
+	sub r1, r1, #1
+	strb r1, [r2, #_cpu_offset_to_exc_depth]
+
+	/*
+	 * Restore r0-r3, r12, lr, lr_und and spsr_und from the exception stack
+	 * and return to the current thread.
+	 */
+	pop {r0-r3, r12, lr}
+	rfeia sp!
+#endif

arch/arm/core/cortex_m/CMakeLists.txt

@@ -11,6 +11,7 @@ zephyr_library_sources(
   scb.c
   thread_abort.c
   vector_table.S
+  swap.c
   swap_helper.S
   irq_manage.c
   prep_c.c

arch/arm/core/cortex_m/cmse/arm_core_cmse.c

@@ -9,7 +9,7 @@
 
 int arm_cmse_mpu_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info = cmse_TT((void *)addr);
+	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
 
 	if (addr_info.flags.mpu_region_valid) {
 		return addr_info.flags.mpu_region;
@@ -40,7 +40,8 @@ int arm_cmse_addr_readwrite_ok(uint32_t addr, int force_npriv)
 	return arm_cmse_addr_read_write_ok(addr, force_npriv, 1);
 }
 
-static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size, int force_npriv, int rw)
+static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size,
+	int force_npriv, int rw)
 {
 	int flags = 0;
 
@@ -73,10 +74,10 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
 
 int arm_cmse_mpu_nonsecure_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info = cmse_TTA((void *)addr);
+	cmse_address_info_t addr_info =	cmse_TTA((void *)addr);
 
 	if (addr_info.flags.mpu_region_valid) {
-		return addr_info.flags.mpu_region;
+		return  addr_info.flags.mpu_region;
 	}
 
 	return -EINVAL;
@@ -84,7 +85,7 @@ int arm_cmse_mpu_nonsecure_region_get(uint32_t addr)
 
 int arm_cmse_sau_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info = cmse_TT((void *)addr);
+	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
 
 	if (addr_info.flags.sau_region_valid) {
 		return addr_info.flags.sau_region;
@@ -95,7 +96,7 @@ int arm_cmse_sau_region_get(uint32_t addr)
 
 int arm_cmse_idau_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info = cmse_TT((void *)addr);
+	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
 
 	if (addr_info.flags.idau_region_valid) {
 		return addr_info.flags.idau_region;
@@ -106,12 +107,13 @@ int arm_cmse_idau_region_get(uint32_t addr)
 
 int arm_cmse_addr_is_secure(uint32_t addr)
 {
-	cmse_address_info_t addr_info = cmse_TT((void *)addr);
+	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
 
 	return addr_info.flags.secure;
 }
 
-static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr, int force_npriv, int rw)
+static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr,
+	int force_npriv, int rw)
 {
 	cmse_address_info_t addr_info;
 	if (force_npriv) {
@@ -120,7 +122,8 @@ static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr, int force_npriv,
 		addr_info = cmse_TTA((void *)addr);
 	}
 
-	return rw ? addr_info.flags.nonsecure_readwrite_ok : addr_info.flags.nonsecure_read_ok;
+	return rw ? addr_info.flags.nonsecure_readwrite_ok :
+		addr_info.flags.nonsecure_read_ok;
 }
 
 int arm_cmse_addr_nonsecure_read_ok(uint32_t addr, int force_npriv)
@@ -134,7 +137,7 @@ int arm_cmse_addr_nonsecure_readwrite_ok(uint32_t addr, int force_npriv)
 }
 
 static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t size,
-						       int force_npriv, int rw)
+	int force_npriv, int rw)
 {
 	int flags = CMSE_NONSECURE;
 
@@ -153,14 +156,18 @@ static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t s
 	}
 }
 
-int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, int force_npriv)
+int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size,
+	int force_npriv)
 {
-	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 0);
+	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size,
+		force_npriv, 0);
 }
 
-int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int force_npriv)
+int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size,
+	int force_npriv)
 {
-	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 1);
+	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size,
+		force_npriv, 1);
 }
 
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */

arch/arm/core/cortex_m/coredump.c

@@ -7,31 +7,31 @@
 #include <string.h>
 #include <zephyr/debug/coredump.h>
 
-#define ARCH_HDR_VER 2
+#define ARCH_HDR_VER			2
 
 uint32_t z_arm_coredump_fault_sp;
 
 struct arm_arch_block {
 	struct {
-		uint32_t r0;
-		uint32_t r1;
-		uint32_t r2;
-		uint32_t r3;
-		uint32_t r12;
-		uint32_t lr;
-		uint32_t pc;
-		uint32_t xpsr;
-		uint32_t sp;
+		uint32_t	r0;
+		uint32_t	r1;
+		uint32_t	r2;
+		uint32_t	r3;
+		uint32_t	r12;
+		uint32_t	lr;
+		uint32_t	pc;
+		uint32_t	xpsr;
+		uint32_t	sp;
 
 		/* callee registers - optionally collected in V2 */
-		uint32_t r4;
-		uint32_t r5;
-		uint32_t r6;
-		uint32_t r7;
-		uint32_t r8;
-		uint32_t r9;
-		uint32_t r10;
-		uint32_t r11;
+		uint32_t	r4;
+		uint32_t	r5;
+		uint32_t	r6;
+		uint32_t	r7;
+		uint32_t	r8;
+		uint32_t	r9;
+		uint32_t	r10;
+		uint32_t	r11;
 	} r;
 } __packed;
 
@@ -76,12 +76,12 @@ void arch_coredump_info_dump(const struct arch_esf *esf)
 
 #if defined(CONFIG_EXTRA_EXCEPTION_INFO)
 	if (esf->extra_info.callee) {
-		arch_blk.r.r4 = esf->extra_info.callee->v1;
-		arch_blk.r.r5 = esf->extra_info.callee->v2;
-		arch_blk.r.r6 = esf->extra_info.callee->v3;
-		arch_blk.r.r7 = esf->extra_info.callee->v4;
-		arch_blk.r.r8 = esf->extra_info.callee->v5;
-		arch_blk.r.r9 = esf->extra_info.callee->v6;
+		arch_blk.r.r4  = esf->extra_info.callee->v1;
+		arch_blk.r.r5  = esf->extra_info.callee->v2;
+		arch_blk.r.r6  = esf->extra_info.callee->v3;
+		arch_blk.r.r7  = esf->extra_info.callee->v4;
+		arch_blk.r.r8  = esf->extra_info.callee->v5;
+		arch_blk.r.r9  = esf->extra_info.callee->v6;
 		arch_blk.r.r10 = esf->extra_info.callee->v7;
 		arch_blk.r.r11 = esf->extra_info.callee->v8;
 	}

arch/arm/core/cortex_m/cpu_idle.c

@@ -30,31 +30,27 @@ void z_arm_cpu_idle_init(void)
 #if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
 #define ON_EXIT_IDLE_HOOK SOC_ON_EXIT_CPU_IDLE
 #else
-#define ON_EXIT_IDLE_HOOK                                                                          \
-	do {                                                                                       \
-	} while (false)
+#define ON_EXIT_IDLE_HOOK do {} while (false)
 #endif
 
 #if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
-#define SLEEP_IF_ALLOWED(wait_instr)                                                               \
-	do {                                                                                       \
-		/* Skip the wait instr if on_enter_cpu_idle returns false */                       \
-		if (z_arm_on_enter_cpu_idle()) {                                                   \
-			/* Wait for all memory transaction to complete */                          \
-			/* before entering low power state. */                                     \
-			__DSB();                                                                   \
-			wait_instr();                                                              \
-			/* Inline the macro provided by SoC-specific code */                       \
-			ON_EXIT_IDLE_HOOK;                                                         \
-		}                                                                                  \
-	} while (false)
+#define SLEEP_IF_ALLOWED(wait_instr) do { \
+	/* Skip the wait instr if on_enter_cpu_idle returns false */ \
+	if (z_arm_on_enter_cpu_idle()) { \
+		/* Wait for all memory transaction to complete */ \
+		/* before entering low power state. */ \
+		__DSB(); \
+		wait_instr(); \
+		/* Inline the macro provided by SoC-specific code */ \
+		ON_EXIT_IDLE_HOOK; \
+	} \
+} while (false)
 #else
-#define SLEEP_IF_ALLOWED(wait_instr)                                                               \
-	do {                                                                                       \
-		__DSB();                                                                           \
-		wait_instr();                                                                      \
-		ON_EXIT_IDLE_HOOK;                                                                 \
-	} while (false)
+#define SLEEP_IF_ALLOWED(wait_instr) do { \
+	__DSB(); \
+	wait_instr(); \
+	ON_EXIT_IDLE_HOOK; \
+} while (false)
 #endif
 
 #ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE

arch/arm/core/cortex_m/debug.c

@@ -35,7 +35,7 @@ bool z_arm_debug_monitor_event_error_check(void)
 			printk("Null-pointer exception?\n");
 		}
 		__ASSERT((DWT->FUNCTION0 & DWT_FUNCTION_MATCHED_Msk) == 0,
-			 "MATCHED flag should have been cleared on read.");
+			"MATCHED flag should have been cleared on read.");
 
 		return true;
 	}
@@ -55,8 +55,8 @@ bool z_arm_debug_monitor_event_error_check(void)
  * so we add a build assert that catches it.
  */
 BUILD_ASSERT(!(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE &
-	       (CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)),
-	     "the size of the partition must be power of 2");
+	(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)),
+	"the size of the partition must be power of 2");
 
 int z_arm_debug_enable_null_pointer_detection(void)
 {
@@ -81,12 +81,20 @@ int z_arm_debug_enable_null_pointer_detection(void)
 	DWT->COMP0 = 0;
 	DWT->COMP1 = CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1;
 
-	DWT->FUNCTION0 = ((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) |
-			 ((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) |
-			 ((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk);
-	DWT->FUNCTION1 = ((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) |
-			 ((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) |
-			 ((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk);
+	DWT->FUNCTION0 =
+		((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk)
+		|
+		((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk)
+		|
+		((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk)
+		;
+	DWT->FUNCTION1 =
+		((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk)
+		|
+		((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk)
+		|
+		((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk)
+		;
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 
 	/* ASSERT that we have the comparator needed for the implementation */
@@ -98,10 +106,13 @@ int z_arm_debug_enable_null_pointer_detection(void)
 	/* Use comparator 0, R/W access check */
 	DWT->COMP0 = 0;
 
-	DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) & DWT_FUNCTION_FUNCTION_Msk;
+	DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) &
+		DWT_FUNCTION_FUNCTION_Msk;
+
 
 	/* Set mask according to the desired size */
-	DWT->MASK0 = 32 - __builtin_clzl(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1);
+	DWT->MASK0 = 32 - __builtin_clzl(
+		CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1);
 #endif
 
 	return 0;

arch/arm/core/cortex_m/exc_exit.c

@@ -55,8 +55,13 @@ FUNC_ALIAS(z_arm_exc_exit, z_arm_int_exit, void);
 Z_GENERIC_SECTION(.text._HandlerModeExit) void z_arm_exc_exit(void)
 {
 #ifdef CONFIG_PREEMPT_ENABLED
-	if (_kernel.ready_q.cache != _kernel.cpus->current) {
-		SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
+	/* If thread is preemptible */
+	if (_kernel.cpus->current->base.prio >= 0) {
+		/* and cached thread is not current thread */
+		if (_kernel.ready_q.cache != _kernel.cpus->current) {
+			/* trigger a context switch */
+			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
+		}
 	}
 #endif /* CONFIG_PREEMPT_ENABLED */
 

arch/arm/core/cortex_m/fault.c

@@ -22,7 +22,7 @@
 LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 
 #if defined(CONFIG_PRINTK) || defined(CONFIG_LOG)
-#define PR_EXC(...)              LOG_ERR(__VA_ARGS__)
+#define PR_EXC(...) LOG_ERR(__VA_ARGS__)
 #define STORE_xFAR(reg_var, reg) uint32_t reg_var = (uint32_t)reg
 #else
 #define PR_EXC(...)
@@ -35,11 +35,59 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 #define PR_FAULT_INFO(...)
 #endif
 
-#if defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_SYSMPU)
-#define EMN(edr)  (((edr) & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT)
-#define EACD(edr) (((edr) & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT)
+#if defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU)
+#define EMN(edr)   (((edr) & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT)
+#define EACD(edr)  (((edr) & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT)
 #endif
 
+/* Exception Return (EXC_RETURN) is provided in LR upon exception entry.
+ * It is used to perform an exception return and to detect possible state
+ * transition upon exception.
+ */
+
+/* Prefix. Indicates that this is an EXC_RETURN value.
+ * This field reads as 0b11111111.
+ */
+#define EXC_RETURN_INDICATOR_PREFIX     (0xFF << 24)
+/* bit[0]: Exception Secure. The security domain the exception was taken to. */
+#define EXC_RETURN_EXCEPTION_SECURE_Pos 0
+#define EXC_RETURN_EXCEPTION_SECURE_Msk \
+		BIT(EXC_RETURN_EXCEPTION_SECURE_Pos)
+#define EXC_RETURN_EXCEPTION_SECURE_Non_Secure 0
+#define EXC_RETURN_EXCEPTION_SECURE_Secure EXC_RETURN_EXCEPTION_SECURE_Msk
+/* bit[2]: Stack Pointer selection. */
+#define EXC_RETURN_SPSEL_Pos 2
+#define EXC_RETURN_SPSEL_Msk BIT(EXC_RETURN_SPSEL_Pos)
+#define EXC_RETURN_SPSEL_MAIN 0
+#define EXC_RETURN_SPSEL_PROCESS EXC_RETURN_SPSEL_Msk
+/* bit[3]: Mode. Indicates the Mode that was stacked from. */
+#define EXC_RETURN_MODE_Pos 3
+#define EXC_RETURN_MODE_Msk BIT(EXC_RETURN_MODE_Pos)
+#define EXC_RETURN_MODE_HANDLER 0
+#define EXC_RETURN_MODE_THREAD EXC_RETURN_MODE_Msk
+/* bit[4]: Stack frame type. Indicates whether the stack frame is a standard
+ * integer only stack frame or an extended floating-point stack frame.
+ */
+#define EXC_RETURN_STACK_FRAME_TYPE_Pos 4
+#define EXC_RETURN_STACK_FRAME_TYPE_Msk BIT(EXC_RETURN_STACK_FRAME_TYPE_Pos)
+#define EXC_RETURN_STACK_FRAME_TYPE_EXTENDED 0
+#define EXC_RETURN_STACK_FRAME_TYPE_STANDARD EXC_RETURN_STACK_FRAME_TYPE_Msk
+/* bit[5]: Default callee register stacking. Indicates whether the default
+ * stacking rules apply, or whether the callee registers are already on the
+ * stack.
+ */
+#define EXC_RETURN_CALLEE_STACK_Pos 5
+#define EXC_RETURN_CALLEE_STACK_Msk BIT(EXC_RETURN_CALLEE_STACK_Pos)
+#define EXC_RETURN_CALLEE_STACK_SKIPPED 0
+#define EXC_RETURN_CALLEE_STACK_DEFAULT EXC_RETURN_CALLEE_STACK_Msk
+/* bit[6]: Secure or Non-secure stack. Indicates whether a Secure or
+ * Non-secure stack is used to restore stack frame on exception return.
+ */
+#define EXC_RETURN_RETURN_STACK_Pos 6
+#define EXC_RETURN_RETURN_STACK_Msk BIT(EXC_RETURN_RETURN_STACK_Pos)
+#define EXC_RETURN_RETURN_STACK_Non_Secure 0
+#define EXC_RETURN_RETURN_STACK_Secure EXC_RETURN_RETURN_STACK_Msk
+
 /* Integrity signature for an ARMv8-M implementation */
 #if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
 #define INTEGRITY_SIGNATURE_STD 0xFEFA125BUL
@@ -54,12 +102,15 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 /* helpers to access memory/bus/usage faults */
-#define SCB_CFSR_MEMFAULTSR                                                                        \
-	(uint32_t)((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) >> SCB_CFSR_MEMFAULTSR_Pos)
-#define SCB_CFSR_BUSFAULTSR                                                                        \
-	(uint32_t)((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) >> SCB_CFSR_BUSFAULTSR_Pos)
-#define SCB_CFSR_USGFAULTSR                                                                        \
-	(uint32_t)((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) >> SCB_CFSR_USGFAULTSR_Pos)
+#define SCB_CFSR_MEMFAULTSR \
+	(uint32_t)((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) \
+		   >> SCB_CFSR_MEMFAULTSR_Pos)
+#define SCB_CFSR_BUSFAULTSR \
+	(uint32_t)((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) \
+		   >> SCB_CFSR_BUSFAULTSR_Pos)
+#define SCB_CFSR_USGFAULTSR \
+	(uint32_t)((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) \
+		   >> SCB_CFSR_USGFAULTSR_Pos)
 #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
 
 /**
@@ -100,8 +151,8 @@ static void fault_show(const struct arch_esf *esf, int fault)
 	PR_EXC("Fault! EXC #%d", fault);
 
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	PR_EXC("MMFSR: 0x%x, BFSR: 0x%x, UFSR: 0x%x", SCB_CFSR_MEMFAULTSR, SCB_CFSR_BUSFAULTSR,
-	       SCB_CFSR_USGFAULTSR);
+	PR_EXC("MMFSR: 0x%x, BFSR: 0x%x, UFSR: 0x%x", SCB_CFSR_MEMFAULTSR,
+	       SCB_CFSR_BUSFAULTSR, SCB_CFSR_USGFAULTSR);
 #if defined(CONFIG_ARM_SECURE_FIRMWARE)
 	PR_EXC("SFSR: 0x%x", SAU->SFSR);
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
@@ -124,7 +175,9 @@ static void fault_show(const struct arch_esf *esf, int fault)
 #ifdef CONFIG_USERSPACE
 Z_EXC_DECLARE(z_arm_user_string_nlen);
 
-static const struct z_exc_handle exceptions[] = {Z_EXC_HANDLE(z_arm_user_string_nlen)};
+static const struct z_exc_handle exceptions[] = {
+	Z_EXC_HANDLE(z_arm_user_string_nlen)
+};
 #endif
 
 /* Perform an assessment whether an MPU fault shall be
@@ -141,12 +194,12 @@ static bool memory_fault_recoverable(struct arch_esf *esf, bool synchronous)
 		uint32_t end = (uint32_t)exceptions[i].end & ~0x1U;
 
 #if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT)
-		/* Non-synchronous exceptions (e.g. DebugMonitor) may have
-		 * allowed PC to continue to the next instruction.
-		 */
-		end += (synchronous) ? 0x0 : 0x4;
+	/* Non-synchronous exceptions (e.g. DebugMonitor) may have
+	 * allowed PC to continue to the next instruction.
+	 */
+	end += (synchronous) ? 0x0 : 0x4;
 #else
-		ARG_UNUSED(synchronous);
+	ARG_UNUSED(synchronous);
 #endif
 		if (esf->basic.pc >= start && esf->basic.pc < end) {
 			esf->basic.pc = (uint32_t)(exceptions[i].fixup);
@@ -163,7 +216,8 @@ static bool memory_fault_recoverable(struct arch_esf *esf, bool synchronous)
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 
 #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
-uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp);
+uint32_t z_check_thread_stack_fail(const uint32_t fault_addr,
+	const uint32_t psp);
 #endif /* CONFIG_MPU_STACK_GUARD || defined(CONFIG_USERSPACE) */
 
 /**
@@ -174,7 +228,8 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp
  *
  * @return error code to identify the fatal error reason
  */
-static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverable)
+static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault,
+			      bool *recoverable)
 {
 	uint32_t reason = K_ERR_ARM_MEM_GENERIC;
 	uint32_t mmfar = -EINVAL;
@@ -184,7 +239,7 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, bool
 	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
 		reason = K_ERR_ARM_MEM_STACKING;
 		PR_FAULT_INFO("  Stacking error (context area might be"
-			      " not valid)");
+			" not valid)");
 	}
 	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
 		reason = K_ERR_ARM_MEM_UNSTACKING;
@@ -219,7 +274,8 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, bool
 #if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
 	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
 		reason = K_ERR_ARM_MEM_FP_LAZY_STATE_PRESERVATION;
-		PR_FAULT_INFO("  Floating-point lazy state preservation error");
+		PR_FAULT_INFO(
+			"  Floating-point lazy state preservation error");
 	}
 #endif /* CONFIG_ARMV7_M_ARMV8_M_FP */
 
@@ -236,7 +292,8 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, bool
 	 * Data Access Violation errors may or may not be caused by
 	 * thread stack overflows.
 	 */
-	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) || (SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
+	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
+		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
 #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
 		/* MemManage Faults are always banked between security
 		 * states. Therefore, we can safely assume the fault
@@ -256,8 +313,8 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, bool
 		 * handle the case of 'mmfar' holding the -EINVAL value.
 		 */
 		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
-			uint32_t min_stack_ptr =
-				z_check_thread_stack_fail(mmfar, ((uint32_t)&esf[0]));
+			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
+				((uint32_t) &esf[0]));
 
 			if (min_stack_ptr) {
 				/* When MemManage Stacking Error has occurred,
@@ -290,14 +347,14 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, bool
 				reason = K_ERR_STACK_CHK_FAIL;
 			} else {
 				__ASSERT(!(SCB->CFSR & SCB_CFSR_MSTKERR_Msk),
-					 "Stacking error not a stack fail\n");
+					"Stacking error not a stack fail\n");
 			}
 		}
 #else
-		(void)mmfar;
-		__ASSERT(!(SCB->CFSR & SCB_CFSR_MSTKERR_Msk),
-			 "Stacking or Data Access Violation error "
-			 "without stack guard, user-mode or null-pointer detection\n");
+	(void)mmfar;
+	__ASSERT(!(SCB->CFSR & SCB_CFSR_MSTKERR_Msk),
+		"Stacking or Data Access Violation error "
+		"without stack guard, user-mode or null-pointer detection\n");
 #endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */
 	}
 
@@ -383,7 +440,7 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl
 	}
 #endif /* !defined(CONFIG_ARMV7_M_ARMV8_M_FP) */
 
-#if defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_SYSMPU)
+#if defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU)
 	uint32_t sperr = SYSMPU->CESR & SYSMPU_CESR_SPERR_MASK;
 	uint32_t mask = BIT(31);
 	int i;
@@ -399,10 +456,13 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl
 
 			PR_FAULT_INFO("  NXP MPU error, port %d", i);
 			PR_FAULT_INFO("    Mode: %s, %s Address: 0x%x",
-				      edr & BIT(2) ? "Supervisor" : "User",
-				      edr & BIT(1) ? "Data" : "Instruction", ear);
-			PR_FAULT_INFO("    Type: %s, Master: %d, Regions: 0x%x",
-				      edr & BIT(0) ? "Write" : "Read", EMN(edr), EACD(edr));
+			       edr & BIT(2) ? "Supervisor" : "User",
+			       edr & BIT(1) ? "Data" : "Instruction",
+			       ear);
+			PR_FAULT_INFO(
+					"    Type: %s, Master: %d, Regions: 0x%x",
+			       edr & BIT(0) ? "Write" : "Read",
+			       EMN(edr), EACD(edr));
 
 			/* When stack protection is enabled, we need to assess
 			 * if the memory violation error is a stack corruption.
@@ -415,7 +475,7 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl
 				/* Note: we can assume the fault originated
 				 * from the same security state for ARM
 				 * platforms implementing the NXP MPU
-				 * (CONFIG_CPU_HAS_NXP_SYSMPU=y).
+				 * (CONFIG_CPU_HAS_NXP_MPU=y).
 				 *
 				 * As we only assess thread stack corruption,
 				 * we only process the error further, if the
@@ -425,7 +485,8 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl
 				 */
 				if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
 					uint32_t min_stack_ptr =
-						z_check_thread_stack_fail(ear, ((uint32_t)&esf[0]));
+						z_check_thread_stack_fail(ear,
+							((uint32_t) &esf[0]));
 
 					if (min_stack_ptr) {
 						/* When BusFault Stacking Error
@@ -455,20 +516,22 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl
 						 */
 						__set_PSP(min_stack_ptr);
 
-						reason = K_ERR_STACK_CHK_FAIL;
+						reason =
+							K_ERR_STACK_CHK_FAIL;
 						break;
 					}
 				}
 #else
 				(void)ear;
 				__ASSERT(0,
-					 "Stacking error without stack guard or User-mode support");
+					"Stacking error without stack guard"
+					"or User-mode support");
 #endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */
 			}
 		}
 		SYSMPU->CESR &= ~sperr;
 	}
-#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_SYSMPU) */
+#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */
 
 	/* clear BFSR sticky bits */
 	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
@@ -602,7 +665,8 @@ static void debug_monitor(struct arch_esf *esf, bool *recoverable)
 {
 	*recoverable = false;
 
-	PR_FAULT_INFO("***** Debug monitor exception *****");
+	PR_FAULT_INFO(
+		"***** Debug monitor exception *****");
 
 #if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT)
 	if (!z_arm_debug_monitor_event_error_check()) {
@@ -659,7 +723,7 @@ static inline bool z_arm_is_synchronous_svc(struct arch_esf *esf)
 #endif /* ARMV6_M_ARMV8_M_BASELINE && !ARMV8_M_BASELINE */
 
 	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
-	    ((fault_insn & 0x00ff) == _SVC_CALL_RUNTIME_EXCEPT)) {
+		((fault_insn & 0x00ff) == _SVC_CALL_RUNTIME_EXCEPT)) {
 		return true;
 	}
 #undef _SVC_OPCODE
@@ -679,7 +743,7 @@ static inline bool z_arm_is_pc_valid(uintptr_t pc)
 		return true;
 	}
 
-#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_itcm))
+#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
 	/* Is it in the ITCM */
 	if ((((uintptr_t)&__itcm_start) <= pc) && (pc < ((uintptr_t)&__itcm_end))) {
 		return true;
@@ -743,11 +807,13 @@ static uint32_t hard_fault(struct arch_esf *esf, bool *recoverable)
 			reason = secure_fault(esf);
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
 		} else {
-			__ASSERT(0, "Fault escalation without FSR info");
+			__ASSERT(0,
+			"Fault escalation without FSR info");
 		}
 	} else {
-		__ASSERT(0, "HardFault without HFSR info"
-			    " Shall never occur");
+		__ASSERT(0,
+		"HardFault without HFSR info"
+		" Shall never occur");
 	}
 #else
 #error Unknown ARM architecture
@@ -768,7 +834,8 @@ static void reserved_exception(const struct arch_esf *esf, int fault)
 	ARG_UNUSED(esf);
 
 	PR_FAULT_INFO("***** %s %d) *****",
-		      fault < 16 ? "Reserved Exception (" : "Spurious interrupt (IRQ ", fault - 16);
+	       fault < 16 ? "Reserved Exception (" : "Spurious interrupt (IRQ ",
+	       fault - 16);
 }
 
 /* Handler function for ARM fault conditions. */
@@ -783,7 +850,7 @@ static uint32_t fault_handle(struct arch_esf *esf, int fault, bool *recoverable)
 		reason = hard_fault(esf, recoverable);
 		break;
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-		/* HardFault is raised for all fault conditions on ARMv6-M. */
+	/* HardFault is raised for all fault conditions on ARMv6-M. */
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	case 4:
 		reason = mem_manage_fault(esf, 0, recoverable);
@@ -841,7 +908,7 @@ static void secure_stack_dump(const struct arch_esf *secure_esf)
 	uint32_t sec_ret_addr;
 #if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
 	if ((*top_of_sec_stack == INTEGRITY_SIGNATURE_STD) ||
-	    (*top_of_sec_stack == INTEGRITY_SIGNATURE_EXT)) {
+		(*top_of_sec_stack == INTEGRITY_SIGNATURE_EXT)) {
 #else
 	if (*top_of_sec_stack == INTEGRITY_SIGNATURE) {
 #endif /* CONFIG_ARMV7_M_ARMV8_M_FP */
@@ -860,6 +927,7 @@ static void secure_stack_dump(const struct arch_esf *secure_esf)
 		sec_ret_addr = *top_of_sec_stack;
 	}
 	PR_FAULT_INFO("  S instruction address:  0x%x", sec_ret_addr);
+
 }
 #define SECURE_STACK_DUMP(esf) secure_stack_dump(esf)
 #else
@@ -880,14 +948,15 @@ static void secure_stack_dump(const struct arch_esf *secure_esf)
  * @return ESF pointer on success, otherwise return NULL
  */
 static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_return,
-				       bool *nested_exc)
+	bool *nested_exc)
 {
 	bool alternative_state_exc = false;
 	struct arch_esf *ptr_esf = NULL;
 
 	*nested_exc = false;
 
-	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) != EXC_RETURN_INDICATOR_PREFIX) {
+	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
+			EXC_RETURN_INDICATOR_PREFIX) {
 		/* Invalid EXC_RETURN value. This is a fatal error. */
 		return NULL;
 	}
@@ -967,7 +1036,8 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_
 	/* The processor has a single execution state.
 	 * We verify that the Thread mode is using PSP.
 	 */
-	if ((exc_return & EXC_RETURN_MODE_THREAD) && (!(exc_return & EXC_RETURN_SPSEL_PROCESS))) {
+	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
+		(!(exc_return & EXC_RETURN_SPSEL_PROCESS))) {
 		PR_EXC("SPSEL in thread mode does not indicate PSP");
 		return NULL;
 	}
@@ -976,7 +1046,7 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_
 	if (!alternative_state_exc) {
 		if (exc_return & EXC_RETURN_MODE_THREAD) {
 			/* Returning to thread mode */
-			ptr_esf = (struct arch_esf *)psp;
+			ptr_esf =  (struct arch_esf *)psp;
 
 		} else {
 			/* Returning to handler mode */
@@ -1019,7 +1089,8 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_
  * @param callee_regs Callee-saved registers (R4-R11, PSP)
  *
  */
-void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, _callee_saved_t *callee_regs)
+void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
+	_callee_saved_t *callee_regs)
 {
 	uint32_t reason = K_ERR_CPU_EXCEPTION;
 	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
@@ -1037,10 +1108,13 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, _callee_saved_
 	/* Retrieve the Exception Stack Frame (ESF) to be supplied
 	 * as argument to the remainder of the fault handling process.
 	 */
-	esf = get_esf(msp, psp, exc_return, &nested_exc);
-	__ASSERT(esf != NULL, "ESF could not be retrieved successfully. Shall never occur.");
+	 esf = get_esf(msp, psp, exc_return, &nested_exc);
+	__ASSERT(esf != NULL,
+		"ESF could not be retrieved successfully. Shall never occur.");
 
-	z_arm_set_fault_sp(esf, exc_return);
+#ifdef CONFIG_DEBUG_COREDUMP
+	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
+#endif
 
 	reason = fault_handle(esf, fault, &recoverable);
 	if (recoverable) {
@@ -1056,8 +1130,11 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, _callee_saved_
 	 * so we only copy the fields before those.
 	 */
 	memcpy(&esf_copy, esf, offsetof(struct arch_esf, extra_info));
-	esf_copy.extra_info = (struct __extra_esf_info){
-		.callee = callee_regs, .exc_return = exc_return, .msp = msp};
+	esf_copy.extra_info = (struct __extra_esf_info) {
+		.callee = callee_regs,
+		.exc_return = exc_return,
+		.msp = msp
+	};
 #endif /* CONFIG_EXTRA_EXCEPTION_INFO */
 
 	/* Overwrite stacked IPSR to mark a nested exception,

arch/arm/core/cortex_m/fpu.c

@@ -23,10 +23,11 @@ void z_arm_save_fp_context(struct fpu_ctx_full *buffer)
 
 	if (CONTROL & CONTROL_FPCA_Msk) {
 		/* Store caller-saved and callee-saved FP registers. */
-		__asm__ volatile("vstmia %0, {s0-s15}\n"
-				 "vstmia %1, {s16-s31}\n" ::"r"(buffer->caller_saved),
-				 "r"(buffer->callee_saved)
-				 :);
+		__asm__ volatile(
+			"vstmia %0, {s0-s15}\n"
+			"vstmia %1, {s16-s31}\n"
+			:: "r" (buffer->caller_saved), "r" (buffer->callee_saved) :
+		);
 
 		buffer->fpscr = __get_FPSCR();
 		buffer->ctx_saved = true;
@@ -54,10 +55,11 @@ void z_arm_restore_fp_context(const struct fpu_ctx_full *buffer)
 		/* Restore FP state. */
 		__set_FPSCR(buffer->fpscr);
 
-		__asm__ volatile("vldmia %0, {s0-s15}\n"
-				 "vldmia %1, {s16-s31}\n" ::"r"(buffer->caller_saved),
-				 "r"(buffer->callee_saved)
-				 :);
+		__asm__ volatile(
+			"vldmia %0, {s0-s15}\n"
+			"vldmia %1, {s16-s31}\n"
+			:: "r" (buffer->caller_saved), "r" (buffer->callee_saved) :
+		);
 	}
 #endif
 }

arch/arm/core/cortex_m/irq_manage.c

@@ -28,7 +28,7 @@
 
 extern void z_arm_reserved(void);
 
-#define NUM_IRQS_PER_REG  32
+#define NUM_IRQS_PER_REG 32
 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
 
@@ -87,7 +87,8 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 	 */
 	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
 		 "invalid priority %d for %d irq! values must be less than %lu\n",
-		 prio - _IRQ_PRIO_OFFSET, irq, BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
+		 prio - _IRQ_PRIO_OFFSET, irq,
+		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
 	NVIC_SetPriority((IRQn_Type)irq, prio);
 }
 
@@ -140,6 +141,7 @@ void _arch_isr_direct_pm(void)
 #else
 #error Unknown ARM architecture
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+
 }
 #endif
 
@@ -163,7 +165,8 @@ void _arch_isr_direct_pm(void)
  *
  * @return The resulting target state of the given IRQ
  */
-irq_target_state_t irq_target_state_set(unsigned int irq, irq_target_state_t irq_target_state)
+irq_target_state_t irq_target_state_set(unsigned int irq,
+	irq_target_state_t irq_target_state)
 {
 	uint32_t result;
 
@@ -214,7 +217,7 @@ int irq_target_state_is_secure(unsigned int irq)
  * - Bits corresponding to un-implemented interrupts are RES0, so writes
  *   will be ignored.
  *
- */
+*/
 void irq_target_state_set_all_non_secure(void)
 {
 	int i;
@@ -238,8 +241,8 @@ void irq_target_state_set_all_non_secure(void)
 #ifdef CONFIG_DYNAMIC_INTERRUPTS
 #ifdef CONFIG_GEN_ISR_TABLES
 int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
-			     void (*routine)(const void *parameter), const void *parameter,
-			     uint32_t flags)
+			     void (*routine)(const void *parameter),
+			     const void *parameter, uint32_t flags)
 {
 	z_isr_install(irq, routine, parameter);
 	z_arm_irq_priority_set(irq, priority, flags);

arch/arm/core/cortex_m/isr_wrapper.c

@@ -68,7 +68,7 @@ void _isr_wrapper(void)
 #if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
 	int32_t irq_number = z_soc_irq_get_active();
 #else
-	/* _sw_isr_table does not map the exceptions, only the interrupts. */
+	/* _sw_isr_table does not map the expections, only the interrupts. */
 	int32_t irq_number = __get_IPSR();
 #endif
 	irq_number -= 16;

arch/arm/core/cortex_m/pm_s2ram.S

@@ -14,145 +14,6 @@
 #include <zephyr/arch/cpu.h>
 #include <zephyr/arch/common/pm_s2ram.h>
 
-/**
- * Macro expanding to an integer literal equal to the offset of
- * field `sr_name` in `struct __cpu_context`. This macro has to
- * be implemented in C, because GEN_OFFSET_SYM provides offsets
- * as C preprocessor definitions - there are not visible to the
- * assembler.
- *
- * See also: `arch/arm/core/offsets/offsets_aarch32.c`
- */
-#define CPU_CTX_SR_OFFSET(sr_name) \
-	___cpu_context_t_ ## sr_name ## _OFFSET
-
-/**
- * Macros used to save / load a special register in __cpu_context.
- * These also have to be implemented in C due to CPU_CTX_SR_OFFSET.
- */
-#define SAVE_SPECIAL_REG(sr_name, cpu_ctx_reg, tmp_reg)	\
-	mrs	tmp_reg, sr_name;			\
-	str	tmp_reg, [cpu_ctx_reg, # CPU_CTX_SR_OFFSET(sr_name)];
-
-#define RESTORE_SPECIAL_REG(sr_name, cpu_ctx_reg, tmp_reg)		\
-	ldr	tmp_reg, [cpu_ctx_reg, # CPU_CTX_SR_OFFSET(sr_name)];	\
-	msr	sr_name, tmp_reg;
-
-/*
- * The following macros could be written as assembler macros, but C is used
- * for portability (assembler macro syntax may differ between toolchains).
- */
-
-/*
- * Pushes registers r4~r12 and lr on the stack.
- * r0 is unmodified but other GPRs may be overwritten.
- */
-#if !defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-/* `push` on ARMv6-M / ARMv8-M Baseline:
- * only r0~r7 and lr may be pushed
- */
-#define PUSH_GPRS							\
-	push	{r4-r7};						\
-	mov	r1, r8;							\
-	mov	r2, r9;							\
-	mov	r3, r10;						\
-	mov	r4, r11;						\
-	mov	r5, r12;						\
-	push	{r1-r5, lr}
-#else
-/* `push` on ARMv7-M and ARMv8-M Mainline: no limitation */
-#define PUSH_GPRS							\
-	push	{r4-r12, lr}
-#endif /* !CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
-
-/*
- * Pops registers r4~r12 and lr from the stack
- * r0 is unmodified but other GPRs may be overwritten.
- */
-#if !defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-/* `pop` on ARMv6-M / ARMv8-M Baseline:
- * can only pop to r0~r7 and pc (not lr!)
- */
-#define POP_GPRS							\
-	pop	{r1-r6};						\
-	mov 	lr, r6;							\
-	mov 	r12, r5;						\
-	mov 	r11, r4;						\
-	mov 	r10, r3;						\
-	mov 	r9, r2;							\
-	mov 	r8, r1;							\
-	pop	{r4-r7}
-#else
-/* `pop` on ARMv7-M and ARMv8-M Mainline: no limitation */
-#define POP_GPRS							\
-	pop	{r4-r12, lr}
-#endif /* !CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
-
-
-#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-/* Registers present only on ARMv7-M and ARMv8-M Mainline */
-#define SAVE_FM_BP_REGS(cpu_ctx, tmp_reg)				\
-	SAVE_SPECIAL_REG(faultmask,	cpu_ctx, tmp_reg)		\
-	SAVE_SPECIAL_REG(basepri,	cpu_ctx, tmp_reg)
-
-#define RESTORE_FM_BP_REGS(cpu_ctx, tmp_reg)				\
-	RESTORE_SPECIAL_REG(faultmask,	cpu_ctx, tmp_reg)		\
-	RESTORE_SPECIAL_REG(basepri,	cpu_ctx, tmp_reg)
-#else
-/* Registers not present: do nothing */
-#define SAVE_FM_BP_REGS(cpu_ctx, tmp_reg)
-#define RESTORE_FM_BP_REGS(cpu_ctx, tmp_reg)
-#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
-
-#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
-/* Registers present only on certain ARMv8-M implementations */
-#define SAVE_SPLIM_REGS(cpu_ctx, tmp_reg)				\
-	SAVE_SPECIAL_REG(msplim,	cpu_ctx, tmp_reg)		\
-	SAVE_SPECIAL_REG(psplim,	cpu_ctx, tmp_reg)
-
-#define RESTORE_SPLIM_REGS(cpu_ctx, tmp_reg)				\
-	RESTORE_SPECIAL_REG(msplim,	cpu_ctx, tmp_reg)		\
-	RESTORE_SPECIAL_REG(psplim,	cpu_ctx, tmp_reg)
-#else
-/* Registers not present: do nothing */
-#define SAVE_SPLIM_REGS(cpu_ctx, tmp_reg)
-#define RESTORE_SPLIM_REGS(cpu_ctx, tmp_reg)
-#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */
-
-/*
- * Saves the CPU's special registers in the `struct __cpu_context`
- * pointed to by the `cpu_ctx` register.
- * The `tmp_reg` register is overwritten as part of this process.
- */
-#define SAVE_SPECIAL_REGISTERS(cpu_ctx, tmp_reg)			\
-	SAVE_SPECIAL_REG(msp,		cpu_ctx, tmp_reg)		\
-	SAVE_SPECIAL_REG(psp,		cpu_ctx, tmp_reg)		\
-	SAVE_SPECIAL_REG(primask,	cpu_ctx, tmp_reg)		\
-	SAVE_SPLIM_REGS(		cpu_ctx, tmp_reg)		\
-	SAVE_FM_BP_REGS(		cpu_ctx, tmp_reg)		\
-	SAVE_SPECIAL_REG(control,	cpu_ctx, tmp_reg)
-
-/*
- * Restores the CPU's special registers from the `struct __cpu_context`
- * pointed to by the `cpu_ctx` register.
- * The `tmp_reg` register is overwritten as part of this process.
- *
- * N.B.: ISB at the end is required because "Software must use an ISB
- * barrier instruction to ensure a write to the CONTROL register takes
- * effect before the next instruction is executed."
- *
- * If this macro is modified, make sure CONTROL is always the last
- * restored register, and that an ISB follows the MSR instruction.
- */
-#define RESTORE_SPECIAL_REGISTERS(cpu_ctx, tmp_reg)			\
-	RESTORE_SPECIAL_REG(msp,	cpu_ctx, tmp_reg)		\
-	RESTORE_SPECIAL_REG(psp,	cpu_ctx, tmp_reg)		\
-	RESTORE_SPECIAL_REG(primask,	cpu_ctx, tmp_reg)		\
-	RESTORE_SPLIM_REGS(		cpu_ctx, tmp_reg)		\
-	RESTORE_FM_BP_REGS(		cpu_ctx, tmp_reg)		\
-	RESTORE_SPECIAL_REG(control,	cpu_ctx, tmp_reg)		\
-	isb
-
 _ASM_FILE_PROLOGUE
 
 GTEXT(pm_s2ram_mark_set)
@@ -165,7 +26,7 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend)
 	 *
 	 * r0: address of the system_off function
 	 */
-	PUSH_GPRS
+	push	{r4-r12, lr}
 
 	/* Move system_off to protected register. */
 	mov 	r4, r0
@@ -173,14 +34,43 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend)
 	/* Store CPU context */
 	ldr	r1, =_cpu_context
 
-	SAVE_SPECIAL_REGISTERS(/* ctx: */ r1, /* tmp: */ r2)
+	mrs	r2, msp
+	str	r2, [r1, #___cpu_context_t_msp_OFFSET]
+
+	mrs	r2, msplim
+	str	r2, [r1, #___cpu_context_t_msplim_OFFSET]
+
+	mrs	r2, psp
+	str	r2, [r1, #___cpu_context_t_psp_OFFSET]
+
+	mrs	r2, psplim
+	str	r2, [r1, #___cpu_context_t_psplim_OFFSET]
+
+	mrs	r2, apsr
+	str	r2, [r1, #___cpu_context_t_apsr_OFFSET]
+
+	mrs	r2, ipsr
+	str	r2, [r1, #___cpu_context_t_ipsr_OFFSET]
+
+	mrs	r2, epsr
+	str	r2, [r1, #___cpu_context_t_epsr_OFFSET]
+
+	mrs	r2, primask
+	str	r2, [r1, #___cpu_context_t_primask_OFFSET]
+
+	mrs	r2, faultmask
+	str	r2, [r1, #___cpu_context_t_faultmask_OFFSET]
+
+	mrs	r2, basepri
+	str	r2, [r1, #___cpu_context_t_basepri_OFFSET]
+
+	mrs	r2, control
+	str	r2, [r1, #___cpu_context_t_control_OFFSET]
 
 	/*
 	 * Mark entering suspend to RAM.
 	 */
-	mov 	r1, lr
-	bl 	pm_s2ram_mark_set
-	mov	lr, r1
+	bl pm_s2ram_mark_set
 
 	/*
 	 * Call the system_off function passed as parameter. This should never
@@ -193,22 +83,15 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend)
 	 * not successful (in r0 the return value).
 	 */
 
-	/* Move return value of system_off to callee-saved register. */
-	mov 	r4, r0
-
 	/*
 	 * Reset the marking of suspend to RAM, return is ignored.
 	 */
-	mov 	r1, lr
-	bl	pm_s2ram_mark_check_and_clear
-	mov 	lr, r1
+	bl pm_s2ram_mark_check_and_clear
 
-	/* Move the stored return value of system_off back to r0,
-	 * setting it as return value for this function.
-	 */
+	/* Move system_off back to r0 as return value */
 	mov	r0, r4
 
-	POP_GPRS
+	pop	{r4-r12, lr}
 	bx	lr
 
 
@@ -216,26 +99,61 @@ GTEXT(arch_pm_s2ram_resume)
 SECTION_FUNC(TEXT, arch_pm_s2ram_resume)
 	/*
 	 * Check if reset occurred after suspending to RAM.
+	 * Store LR to ensure we can continue boot when we are not suspended
+	 * to RAM. In addition to LR, R0 is pushed too, to ensure "SP mod 8 = 0",
+	 * as stated by ARM rule 6.2.1.2 for AAPCS32.
 	 */
-	mov 	r1, lr
-	bl 	pm_s2ram_mark_check_and_clear
-	mov 	lr, r1
-	cmp     r0, #0x1
-	beq     .L_resume
-	bx      lr
+	push    {r0, lr}
+	bl      pm_s2ram_mark_check_and_clear
+	cmp	r0, #0x1
+	pop     {r0, lr}
+	beq	resume
+	bx	lr
 
-.L_resume:
+resume:
 	/*
 	 * Restore the CPU context
 	 */
 	ldr	r0, =_cpu_context
 
-	RESTORE_SPECIAL_REGISTERS(/* ctx: */ r0, /* tmp: */ r1)
+	ldr	r1, [r0, #___cpu_context_t_msp_OFFSET]
+	msr	msp, r1
 
-	POP_GPRS
+	ldr	r1, [r0, #___cpu_context_t_msplim_OFFSET]
+	msr	msplim, r1
+
+	ldr	r1, [r0, #___cpu_context_t_psp_OFFSET]
+	msr	psp, r1
+
+	ldr	r1, [r0, #___cpu_context_t_psplim_OFFSET]
+	msr	psplim, r1
+
+	ldr	r1, [r0, #___cpu_context_t_apsr_OFFSET]
+	msr	apsr_nzcvq, r1
+
+	ldr	r1, [r0, #___cpu_context_t_ipsr_OFFSET]
+	msr	ipsr, r1
+
+	ldr	r1, [r0, #___cpu_context_t_epsr_OFFSET]
+	msr	epsr, r1
+
+	ldr	r1, [r0, #___cpu_context_t_primask_OFFSET]
+	msr	primask, r1
+
+	ldr	r1, [r0, #___cpu_context_t_faultmask_OFFSET]
+	msr	faultmask, r1
+
+	ldr	r1, [r0, #___cpu_context_t_basepri_OFFSET]
+	msr	basepri, r1
+
+	ldr	r1, [r0, #___cpu_context_t_control_OFFSET]
+	msr	control, r1
+	isb
+
+	pop	{r4-r12, lr}
 
 	/*
 	 * Set the return value and return
 	 */
-	movs	r0, #0
+	mov	r0, #0
 	bx	lr

arch/arm/core/cortex_m/pm_s2ram.c

@@ -22,44 +22,20 @@ __noinit _cpu_context_t _cpu_context;
  */
 static __noinit uint32_t marker;
 
-void __attribute__((naked)) pm_s2ram_mark_set(void)
+void pm_s2ram_mark_set(void)
 {
-	__asm__ volatile(
-		/* Set the marker to MAGIC value */
-		"str	%[_magic_val], [%[_marker]]\n"
-
-		"bx	lr\n"
-		:
-		: [_magic_val] "r"(MAGIC), [_marker] "r"(&marker)
-		: "r1", "r4", "memory");
+	marker = MAGIC;
 }
 
-bool __attribute__((naked)) pm_s2ram_mark_check_and_clear(void)
+bool pm_s2ram_mark_check_and_clear(void)
 {
-	__asm__ volatile(
-		/* Set return value to 0 */
-		"mov	r0, #0\n"
+	if (marker == MAGIC) {
+		marker = 0;
 
-		/* Check the marker */
-		"ldr	r3, [%[_marker]]\n"
-		"cmp	r3, %[_magic_val]\n"
-		"bne	exit\n"
+		return true;
+	}
 
-		/*
-		 * Reset the marker
-		 */
-		"str	r0, [%[_marker]]\n"
-
-		/*
-		 * Set return value to 1
-		 */
-		"mov	r0, #1\n"
-
-		"exit:\n"
-		"bx lr\n"
-		:
-		: [_magic_val] "r"(MAGIC), [_marker] "r"(&marker)
-		: "r0", "r1", "r3", "r4", "memory");
+	return false;
 }
 
 #endif /* CONFIG_PM_S2RAM_CUSTOM_MARKING */

arch/arm/core/cortex_m/prep_c.c

@@ -37,23 +37,17 @@
 #include <string.h>
 
 #if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
-Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used)) void *_vector_table_pointer;
+Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used))
+void *_vector_table_pointer;
 #endif
 
 #ifdef CONFIG_CPU_CORTEX_M_HAS_VTOR
 
 #define VECTOR_ADDRESS ((uintptr_t)_vector_start)
 
-/* In some Cortex-M3 implementations SCB_VTOR bit[29] is called the TBLBASE bit */
-#ifdef SCB_VTOR_TBLBASE_Msk
-#define VTOR_MASK (SCB_VTOR_TBLBASE_Msk | SCB_VTOR_TBLOFF_Msk)
-#else
-#define VTOR_MASK SCB_VTOR_TBLOFF_Msk
-#endif
-
 static inline void relocate_vector_table(void)
 {
-	SCB->VTOR = VECTOR_ADDRESS & VTOR_MASK;
+	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
 	barrier_dsync_fence_full();
 	barrier_isync_fence_full();
 }
@@ -63,8 +57,8 @@ static inline void relocate_vector_table(void)
 
 void __weak relocate_vector_table(void)
 {
-#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) ||                                     \
-	!defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
+#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \
+    !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
 	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
 	(void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size);
 #elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
@@ -99,7 +93,7 @@ static inline void z_arm_floating_point_init(void)
 #else
 	/* Privileged access only */
 	SCB->CPACR |= CPACR_CP10_PRIV_ACCESS | CPACR_CP11_PRIV_ACCESS;
-#endif  /* CONFIG_USERSPACE */
+#endif /* CONFIG_USERSPACE */
 	/*
 	 * Upon reset, the FPU Context Control Register is 0xC0000000
 	 * (both Automatic and Lazy state preservation is enabled).
@@ -169,7 +163,7 @@ static inline void z_arm_floating_point_init(void)
 	 *
 	 * If CONFIG_INIT_ARCH_HW_AT_BOOT is set, CONTROL is cleared at reset.
 	 */
-#if (!defined(CONFIG_FPU) || !defined(CONFIG_FPU_SHARING)) &&                                      \
+#if (!defined(CONFIG_FPU) || !defined(CONFIG_FPU_SHARING)) && \
 	(!defined(CONFIG_INIT_ARCH_HW_AT_BOOT))
 
 	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));

arch/arm/core/cortex_m/reset.S

@@ -68,6 +68,13 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,z_arm_reset)
  */
 SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
 
+#if defined(CONFIG_DEBUG_THREAD_INFO)
+    /* Clear z_sys_post_kernel flag for RTOS aware debuggers */
+    movs.n r0, #0
+    ldr r1, =z_sys_post_kernel
+    strb r0, [r1]
+#endif /* CONFIG_DEBUG_THREAD_INFO */
+
 #if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
     /* Reset CONTROL register */
     movs.n r0, #0
@@ -86,18 +93,6 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
     bl arch_pm_s2ram_resume
 #endif /* CONFIG_PM_S2RAM */
 
-    /* Note: Make sure that variables like z_sys_post_kernel
-     *       are set after the call to arch_pm_s2ram_resume
-     *       to avoid any issues with suspend/resume path.
-     *       Refer issue #83660 for more details.
-     */
-#if defined(CONFIG_DEBUG_THREAD_INFO)
-    /* Clear z_sys_post_kernel flag for RTOS aware debuggers */
-    movs.n r0, #0
-    ldr r1, =z_sys_post_kernel
-    strb r0, [r1]
-#endif /* CONFIG_DEBUG_THREAD_INFO */
-
 #if defined(CONFIG_SOC_RESET_HOOK)
     bl soc_reset_hook
 #endif

arch/arm/core/cortex_m/scb.c

@@ -23,7 +23,7 @@
 #include <zephyr/cache.h>
 #include <zephyr/arch/cache.h>
 
-#if defined(CONFIG_CPU_HAS_NXP_SYSMPU)
+#if defined(CONFIG_CPU_HAS_NXP_MPU)
 #include <fsl_sysmpu.h>
 #endif
 
@@ -55,13 +55,14 @@ void z_arm_clear_arm_mpu_config(void)
 {
 	int i;
 
-	int num_regions = ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
+	int num_regions =
+		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
 
 	for (i = 0; i < num_regions; i++) {
 		ARM_MPU_ClrRegion(i);
 	}
 }
-#elif CONFIG_CPU_HAS_NXP_SYSMPU
+#elif CONFIG_CPU_HAS_NXP_MPU
 void z_arm_clear_arm_mpu_config(void)
 {
 	int i;
@@ -75,7 +76,7 @@ void z_arm_clear_arm_mpu_config(void)
 		SYSMPU_RegionEnable(SYSMPU, i, false);
 	}
 }
-#endif /* CONFIG_CPU_HAS_NXP_SYSMPU */
+#endif /* CONFIG_CPU_HAS_NXP_MPU */
 #endif /* CONFIG_ARM_MPU */
 
 #if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
@@ -89,7 +90,7 @@ void z_arm_clear_arm_mpu_config(void)
  */
 void z_arm_init_arch_hw_at_boot(void)
 {
-	/* Disable interrupts */
+    /* Disable interrupts */
 	__disable_irq();
 
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)

arch/arm/core/cortex_m/semihost.c

@@ -9,10 +9,11 @@
 
 long semihost_exec(enum semihost_instr instr, void *args)
 {
-	register unsigned int r0 __asm__("r0") = instr;
-	register void *r1 __asm__("r1") = args;
-	register int ret __asm__("r0");
+	register unsigned int r0 __asm__ ("r0") = instr;
+	register void *r1 __asm__ ("r1") = args;
+	register int ret __asm__ ("r0");
 
-	__asm__ __volatile__("bkpt 0xab" : "=r"(ret) : "r"(r0), "r"(r1) : "memory");
+	__asm__ __volatile__ ("bkpt 0xab"
+			      : "=r" (ret) : "r" (r0), "r" (r1) : "memory");
 	return ret;
 }

arch/arm/core/cortex_m/swap.c

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2018 Linaro, Limited
+ * Copyright (c) 2023 Arm Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <kernel_internal.h>
+
+#include <errno.h>
+
+/* The 'key' actually represents the BASEPRI register
+ * prior to disabling interrupts via the BASEPRI mechanism.
+ *
+ * arch_swap() itself does not do much.
+ *
+ * It simply stores the intlock key (the BASEPRI value) parameter into
+ * current->basepri, and then triggers a PendSV exception, which does
+ * the heavy lifting of context switching.
+
+ * This is the only place we have to save BASEPRI since the other paths to
+ * z_arm_pendsv all come from handling an interrupt, which means we know the
+ * interrupts were not locked: in that case the BASEPRI value is 0.
+ *
+ * Given that arch_swap() is called to effect a cooperative context switch,
+ * only the caller-saved integer registers need to be saved in the thread of the
+ * outgoing thread. This is all performed by the hardware, which stores it in
+ * its exception stack frame, created when handling the z_arm_pendsv exception.
+ *
+ * On ARMv6-M, the intlock key is represented by the PRIMASK register,
+ * as BASEPRI is not available.
+ */
+int arch_swap(unsigned int key)
+{
+	/* store off key and return value */
+	_current->arch.basepri = key;
+	_current->arch.swap_return_value = -EAGAIN;
+
+	/* set pending bit to make sure we will take a PendSV exception */
+	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
+
+	/* clear mask or enable all irqs to take a pendsv */
+	irq_unlock(0);
+
+	/* Context switch is performed here. Returning implies the
+	 * thread has been context-switched-in again.
+	 */
+	return _current->arch.swap_return_value;
+}
+
+uintptr_t z_arm_pendsv_c(uintptr_t exc_ret)
+{
+	/* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
+	IF_ENABLED(CONFIG_ARM_STORE_EXC_RETURN,
+		   (_kernel.cpus[0].current->arch.mode_exc_return = (uint8_t)exc_ret;));
+
+	/* Protect the kernel state while we play with the thread lists */
+	uint32_t basepri = arch_irq_lock();
+
+	/* fetch the thread to run from the ready queue cache */
+	struct k_thread *current = _kernel.cpus[0].current = _kernel.ready_q.cache;
+
+	/*
+	 * Clear PendSV so that if another interrupt comes in and
+	 * decides, with the new kernel state based on the new thread
+	 * being context-switched in, that it needs to reschedule, it
+	 * will take, but that previously pended PendSVs do not take,
+	 * since they were based on the previous kernel state and this
+	 * has been handled.
+	 */
+	SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk;
+
+	/* For Cortex-M, store TLS pointer in a global variable,
+	 * as it lacks the process ID or thread ID register
+	 * to be used by toolchain to access thread data.
+	 */
+	IF_ENABLED(CONFIG_THREAD_LOCAL_STORAGE,
+		   (extern uintptr_t z_arm_tls_ptr; z_arm_tls_ptr = current->tls));
+
+	IF_ENABLED(CONFIG_ARM_STORE_EXC_RETURN,
+		   (exc_ret = (exc_ret & 0xFFFFFF00) | current->arch.mode_exc_return));
+
+	/* Restore previous interrupt disable state (irq_lock key)
+	 * (We clear the arch.basepri field after restoring state)
+	 */
+	basepri = current->arch.basepri;
+	current->arch.basepri = 0;
+
+	arch_irq_unlock(basepri);
+
+#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
+	/* Re-program dynamic memory map */
+	z_arm_configure_dynamic_mpu_regions(current);
+#endif
+
+	/* restore mode */
+	IF_ENABLED(CONFIG_USERSPACE, ({
+			CONTROL_Type ctrl = {.w = __get_CONTROL()};
+			/* exit privileged state when returning to thread mode. */
+			ctrl.b.nPRIV = 0;
+			/* __set_CONTROL inserts an ISB which is may not be necessary here
+			 * (stack pointer may not be touched), but it's recommended to avoid
+			 * executing pre-fetched instructions with the previous privilege.
+			 */
+			__set_CONTROL(ctrl.w | current->arch.mode);
+		}));
+
+	return exc_ret;
+}

arch/arm/core/cortex_m/swap_helper.S

@@ -27,6 +27,7 @@ _ASM_FILE_PROLOGUE
 GTEXT(z_arm_svc)
 GTEXT(z_arm_pendsv)
 GTEXT(z_do_kernel_oops)
+GTEXT(z_arm_pendsv_c)
 #if defined(CONFIG_USERSPACE)
 GTEXT(z_arm_do_syscall)
 #endif
@@ -98,7 +99,7 @@ SECTION_FUNC(TEXT, z_arm_pendsv)
 #ifdef CONFIG_FPU_SHARING
     /* Assess whether switched-out thread had been using the FP registers. */
     tst lr, #_EXC_RETURN_FTYPE_Msk
-    bne .L_out_fp_endif
+    bne out_fp_endif
 
     /* FP context active: set FP state and store callee-saved registers.
      * Note: if Lazy FP stacking is enabled, storing the callee-saved
@@ -108,7 +109,7 @@ SECTION_FUNC(TEXT, z_arm_pendsv)
     add r0, r2, #_thread_offset_to_preempt_float
     vstmia r0, {s16-s31}
 
-.L_out_fp_endif:
+out_fp_endif:
     /* At this point FPCCR.LSPACT is guaranteed to be cleared,
      * regardless of whether the thread has an active FP context.
      */
@@ -117,129 +118,20 @@ SECTION_FUNC(TEXT, z_arm_pendsv)
 #error Unknown ARM architecture
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 
-    /* Protect the kernel state while we play with the thread lists */
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-    cpsid i
-#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
-    msr BASEPRI_MAX, r0
-    isb /* Make the effect of disabling interrupts be realized immediately */
-#else
-#error Unknown ARM architecture
-#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+    mov r4, lr
+    mov r0, lr
+    bl z_arm_pendsv_c
+    mov lr, r4
 
-    /*
-     * Prepare to clear PendSV with interrupts unlocked, but
-     * don't clear it yet. PendSV must not be cleared until
-     * the new thread is context-switched in since all decisions
-     * to pend PendSV have been taken with the current kernel
-     * state and this is what we're handling currently.
-     */
-    ldr r7, =_SCS_ICSR
-    ldr r6, =_SCS_ICSR_UNPENDSV
-
-    /* _kernel is still in r1 */
-
-    /* fetch the thread to run from the ready queue cache */
-    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
-
-    str r2, [r1, #_kernel_offset_to_current]
-
-    /*
-     * Clear PendSV so that if another interrupt comes in and
-     * decides, with the new kernel state based on the new thread
-     * being context-switched in, that it needs to reschedule, it
-     * will take, but that previously pended PendSVs do not take,
-     * since they were based on the previous kernel state and this
-     * has been handled.
-     */
-
-    /* _SCS_ICSR is still in r7 and _SCS_ICSR_UNPENDSV in r6 */
-    str r6, [r7, #0]
-
-#if defined(CONFIG_THREAD_LOCAL_STORAGE)
-    /* Grab the TLS pointer */
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-    ldr r4, =_thread_offset_to_tls
-    adds r4, r2, r4
-    ldr r0, [r4]
-#else
-    ldr r0, [r2, #_thread_offset_to_tls]
-#endif
-
-    /* For Cortex-M, store TLS pointer in a global variable,
-     * as it lacks the process ID or thread ID register
-     * to be used by toolchain to access thread data.
-     */
-    ldr r4, =z_arm_tls_ptr
-    str r0, [r4]
-#endif
+    ldr r1, =_kernel
+    ldr r2, [r1, #_kernel_offset_to_current]
 
 #if defined(CONFIG_ARM_STORE_EXC_RETURN)
     /* Restore EXC_RETURN value. */
-    ldrsb lr, [r2, #_thread_offset_to_mode_exc_return]
-#endif
-
-    /* Restore previous interrupt disable state (irq_lock key)
-     * (We clear the arch.basepri field after restoring state)
-     */
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && (_thread_offset_to_basepri > 124)
-    /* Doing it this way since the offset to thread->arch.basepri can in
-     * some configurations be larger than the maximum of 124 for ldr/str
-     * immediate offsets.
-     */
-    ldr r4, =_thread_offset_to_basepri
-    adds r4, r2, r4
-
-    ldr r0, [r4]
-    movs.n r3, #0
-    str r3, [r4]
-#else
-    ldr r0, [r2, #_thread_offset_to_basepri]
-    movs r3, #0
-    str r3, [r2, #_thread_offset_to_basepri]
+    mov lr, r0
 #endif
 
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-    /* BASEPRI not available, previous interrupt disable state
-     * maps to PRIMASK.
-     *
-     * Only enable interrupts if value is 0, meaning interrupts
-     * were enabled before irq_lock was called.
-     */
-    cmp r0, #0
-    bne .L_thread_irq_disabled
-    cpsie i
-.L_thread_irq_disabled:
-
-#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
-    /* Re-program dynamic memory map */
-    push {r2,lr}
-    mov r0, r2
-    bl z_arm_configure_dynamic_mpu_regions
-    pop {r2,r3}
-    mov lr, r3
-#endif
-
-#ifdef CONFIG_USERSPACE
-    /* restore mode */
-    ldr r3, =_thread_offset_to_mode
-    adds r3, r2, r3
-    ldr r0, [r3]
-    mrs r3, CONTROL
-    movs.n r1, #1
-    bics r3, r1
-    orrs r3, r0
-    msr CONTROL, r3
-
-    /* ISB is not strictly necessary here (stack pointer is not being
-     * touched), but it's recommended to avoid executing pre-fetched
-     * instructions with the previous privilege.
-     */
-    isb
-
-#endif
-
     ldr r4, =_thread_offset_to_callee_saved
     adds r0, r2, r4
 
@@ -257,13 +149,10 @@ SECTION_FUNC(TEXT, z_arm_pendsv)
     subs r0, #36
     ldmia r0!, {r4-r7}
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-    /* restore BASEPRI for the incoming thread */
-    msr BASEPRI, r0
-
 #ifdef CONFIG_FPU_SHARING
     /* Assess whether switched-in thread had been using the FP registers. */
     tst lr, #_EXC_RETURN_FTYPE_Msk
-    beq .L_in_fp_active
+    beq in_fp_active
     /* FP context inactive for swapped-in thread:
      * - reset FPSCR to 0
      * - set EXC_RETURN.F_Type (prevents FP frame un-stacking when returning
@@ -271,9 +160,9 @@ SECTION_FUNC(TEXT, z_arm_pendsv)
      */
     movs.n r3, #0
     vmsr fpscr, r3
-    b .L_in_fp_endif
+    b in_fp_endif
 
-.L_in_fp_active:
+in_fp_active:
     /* FP context active:
      * - clear EXC_RETURN.F_Type
      * - FPSCR and caller-saved registers will be restored automatically
@@ -281,7 +170,7 @@ SECTION_FUNC(TEXT, z_arm_pendsv)
      */
     add r0, r2, #_thread_offset_to_preempt_float
     vldmia r0, {s16-s31}
-.L_in_fp_endif:
+in_fp_endif:
     /* Clear CONTROL.FPCA that may have been set by FP instructions */
     mrs r3, CONTROL
     bic r3, #_CONTROL_FPCA_Msk
@@ -289,30 +178,6 @@ SECTION_FUNC(TEXT, z_arm_pendsv)
     isb
 #endif
 
-#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
-    /* Re-program dynamic memory map */
-    push {r2,lr}
-    mov r0, r2 /* _current thread */
-    bl z_arm_configure_dynamic_mpu_regions
-    pop {r2,lr}
-#endif
-
-#ifdef CONFIG_USERSPACE
-    /* restore mode */
-    ldr r0, [r2, #_thread_offset_to_mode]
-    mrs r3, CONTROL
-    bic r3, #1
-    orr r3, r0
-    msr CONTROL, r3
-
-    /* ISB is not strictly necessary here (stack pointer is not being
-     * touched), but it's recommended to avoid executing pre-fetched
-     * instructions with the previous privilege.
-     */
-    isb
-
-#endif
-
     /* load callee-saved + psp from thread */
     add r0, r2, #_thread_offset_to_callee_saved
     ldmia r0, {r4-r11, ip}
@@ -365,12 +230,12 @@ SECTION_FUNC(TEXT, z_arm_svc)
   movs r0, #_EXC_RETURN_SPSEL_Msk
   mov r1, lr
   tst r1, r0
-  beq .L_stack_frame_msp
+  beq _stack_frame_msp
   mrs r0, PSP
-  bne .L_stack_frame_endif
-.L_stack_frame_msp:
+  bne _stack_frame_endif
+_stack_frame_msp:
   mrs r0, MSP
-.L_stack_frame_endif:
+_stack_frame_endif:
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
     tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
     ite eq  /* if zero (equal), came from handler mode */
@@ -403,7 +268,7 @@ SECTION_FUNC(TEXT, z_arm_svc)
     mrs r2, CONTROL
 
     cmp r1, #3
-    beq .L_do_syscall
+    beq _do_syscall
 
     /*
      * check that we are privileged before invoking other SVCs
@@ -415,12 +280,12 @@ SECTION_FUNC(TEXT, z_arm_svc)
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
     tst r2, #0x1
 #endif
-    bne .L_oops
+    bne _oops
 
 #endif /* CONFIG_USERSPACE */
 
     cmp r1, #2
-    beq .L_oops
+    beq _oops
 
 #if defined(CONFIG_IRQ_OFFLOAD)
     push {r0, lr}
@@ -435,10 +300,9 @@ SECTION_FUNC(TEXT, z_arm_svc)
     /* exception return is done in z_arm_int_exit() */
     ldr r0, =z_arm_int_exit
     bx r0
-
 #endif
 
-.L_oops:
+_oops:
     push {r0, lr}
 #if defined(CONFIG_EXTRA_EXCEPTION_INFO)
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
@@ -451,7 +315,6 @@ SECTION_FUNC(TEXT, z_arm_svc)
     mov  r1, sp /* pointer to _callee_saved_t */
 #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
 #endif /* CONFIG_EXTRA_EXCEPTION_INFO */
-    mov r2, lr /* EXC_RETURN */
     bl z_do_kernel_oops
     /* return from SVC exception is done here */
 #if defined(CONFIG_EXTRA_EXCEPTION_INFO)
@@ -488,7 +351,7 @@ SECTION_FUNC(TEXT, z_arm_svc)
      * r6 - call_id
      * r8 - saved link register
      */
-.L_do_syscall:
+_do_syscall:
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
     movs r3, #24
     ldr r1, [r0, r3]   /* grab address of PC from stack frame */
@@ -514,7 +377,7 @@ SECTION_FUNC(TEXT, z_arm_svc)
     /* The supplied syscall_id must be lower than the limit
      * (Requires unsigned integer comparison)
      */
-    blo .L_valid_syscall_id
+    blo valid_syscall_id
 
     /* bad syscall id.  Set arg1 to bad id and set call_id to SYSCALL_BAD */
     str r6, [r0]
@@ -522,7 +385,7 @@ SECTION_FUNC(TEXT, z_arm_svc)
 
     /* Bad syscalls treated as valid syscalls with ID K_SYSCALL_BAD. */
 
-.L_valid_syscall_id:
+valid_syscall_id:
     ldr r0, =_kernel
     ldr r0, [r0, #_kernel_offset_to_current]
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)

arch/arm/core/cortex_m/thread.c

@@ -22,14 +22,15 @@
 #include <cmsis_core.h>
 
 #if (MPU_GUARD_ALIGN_AND_SIZE_FLOAT > MPU_GUARD_ALIGN_AND_SIZE)
-#define FP_GUARD_EXTRA_SIZE (MPU_GUARD_ALIGN_AND_SIZE_FLOAT - MPU_GUARD_ALIGN_AND_SIZE)
+#define FP_GUARD_EXTRA_SIZE	(MPU_GUARD_ALIGN_AND_SIZE_FLOAT - \
+				 MPU_GUARD_ALIGN_AND_SIZE)
 #else
-#define FP_GUARD_EXTRA_SIZE 0
+#define FP_GUARD_EXTRA_SIZE	0
 #endif
 
 #ifndef EXC_RETURN_FTYPE
 /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
-#define EXC_RETURN_FTYPE (0x00000010UL)
+#define EXC_RETURN_FTYPE           (0x00000010UL)
 #endif
 
 /* Default last octet of EXC_RETURN, for threads that have not run yet.
@@ -57,8 +58,9 @@ K_THREAD_STACK_DECLARE(z_main_stack, CONFIG_MAIN_STACK_SIZE);
  * addresses, we have to unset it manually before storing it in the 'pc' field
  * of the ESF.
  */
-void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *stack_ptr,
-		     k_thread_entry_t entry, void *p1, void *p2, void *p3)
+void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
+		     char *stack_ptr, k_thread_entry_t entry,
+		     void *p1, void *p2, void *p3)
 {
 	struct __basic_sf *iframe;
 
@@ -103,7 +105,8 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *sta
 	iframe->a3 = (uint32_t)p2;
 	iframe->a4 = (uint32_t)p3;
 
-	iframe->xpsr = 0x01000000UL; /* clear all, thumb bit is 1, even if RO */
+	iframe->xpsr =
+		0x01000000UL; /* clear all, thumb bit is 1, even if RO */
 
 	thread->callee_saved.psp = (uint32_t)iframe;
 	thread->arch.basepri = 0;
@@ -128,42 +131,52 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *sta
 	 */
 }
 
-#if defined(CONFIG_MPU_STACK_GUARD) && defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
+#if defined(CONFIG_MPU_STACK_GUARD) && defined(CONFIG_FPU) \
+	&& defined(CONFIG_FPU_SHARING)
 
-static inline void z_arm_thread_stack_info_adjust(struct k_thread *thread, bool use_large_guard)
+static inline void z_arm_thread_stack_info_adjust(struct k_thread *thread,
+	bool use_large_guard)
 {
 	if (use_large_guard) {
 		/* Switch to use a large MPU guard if not already. */
-		if ((thread->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) == 0) {
+		if ((thread->arch.mode &
+			Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) == 0) {
 			/* Default guard size is used. Update required. */
 			thread->arch.mode |= Z_ARM_MODE_MPU_GUARD_FLOAT_Msk;
 #if defined(CONFIG_USERSPACE)
 			if (thread->arch.priv_stack_start) {
 				/* User thread */
-				thread->arch.priv_stack_start += FP_GUARD_EXTRA_SIZE;
+				thread->arch.priv_stack_start +=
+					FP_GUARD_EXTRA_SIZE;
 			} else
 #endif /* CONFIG_USERSPACE */
 			{
 				/* Privileged thread */
-				thread->stack_info.start += FP_GUARD_EXTRA_SIZE;
-				thread->stack_info.size -= FP_GUARD_EXTRA_SIZE;
+				thread->stack_info.start +=
+					FP_GUARD_EXTRA_SIZE;
+				thread->stack_info.size -=
+					FP_GUARD_EXTRA_SIZE;
 			}
 		}
 	} else {
 		/* Switch to use the default MPU guard size if not already. */
-		if ((thread->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) {
+		if ((thread->arch.mode &
+			Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) {
 			/* Large guard size is used. Update required. */
 			thread->arch.mode &= ~Z_ARM_MODE_MPU_GUARD_FLOAT_Msk;
 #if defined(CONFIG_USERSPACE)
 			if (thread->arch.priv_stack_start) {
 				/* User thread */
-				thread->arch.priv_stack_start -= FP_GUARD_EXTRA_SIZE;
+				thread->arch.priv_stack_start -=
+					FP_GUARD_EXTRA_SIZE;
 			} else
 #endif /* CONFIG_USERSPACE */
 			{
 				/* Privileged thread */
-				thread->stack_info.start -= FP_GUARD_EXTRA_SIZE;
-				thread->stack_info.size += FP_GUARD_EXTRA_SIZE;
+				thread->stack_info.start -=
+					FP_GUARD_EXTRA_SIZE;
+				thread->stack_info.size +=
+					FP_GUARD_EXTRA_SIZE;
 			}
 		}
 	}
@@ -177,7 +190,7 @@ static inline void z_arm_thread_stack_info_adjust(struct k_thread *thread, bool
 uint32_t z_arm_mpu_stack_guard_and_fpu_adjust(struct k_thread *thread)
 {
 	if (((thread->base.user_options & K_FP_REGS) != 0) ||
-	    ((thread->arch.mode_exc_return & EXC_RETURN_FTYPE) == 0)) {
+		((thread->arch.mode_exc_return & EXC_RETURN_FTYPE) == 0)) {
 		/* The thread has been pre-tagged (at creation or later) with
 		 * K_FP_REGS, i.e. it is expected to be using the FPU registers
 		 * (if not already). Activate lazy stacking and program a large
@@ -213,11 +226,13 @@ uint32_t z_arm_mpu_stack_guard_and_fpu_adjust(struct k_thread *thread)
 #endif
 
 #ifdef CONFIG_USERSPACE
-FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, void *p1, void *p2, void *p3)
+FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
+					void *p1, void *p2, void *p3)
 {
 
 	/* Set up privileged stack before entering user mode */
-	_current->arch.priv_stack_start = (uint32_t)z_priv_stack_find(_current->stack_obj);
+	_current->arch.priv_stack_start =
+		(uint32_t)z_priv_stack_find(_current->stack_obj);
 #if defined(CONFIG_MPU_STACK_GUARD)
 #if defined(CONFIG_THREAD_STACK_INFO)
 	/* We're dropping to user mode which means the guard area is no
@@ -241,19 +256,21 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, void *p1, v
 	 */
 #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
 	_current->arch.priv_stack_start +=
-		((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0)
-			? MPU_GUARD_ALIGN_AND_SIZE_FLOAT
-			: MPU_GUARD_ALIGN_AND_SIZE;
+		((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) ?
+		MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE;
 #else
 	_current->arch.priv_stack_start += MPU_GUARD_ALIGN_AND_SIZE;
 #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
 #endif /* CONFIG_MPU_STACK_GUARD */
 
-	z_arm_userspace_enter(user_entry, p1, p2, p3, (uint32_t)_current->stack_info.start,
-			      _current->stack_info.size - _current->stack_info.delta);
+	z_arm_userspace_enter(user_entry, p1, p2, p3,
+			     (uint32_t)_current->stack_info.start,
+			     _current->stack_info.size -
+			     _current->stack_info.delta);
 	CODE_UNREACHABLE;
 }
 
+
 bool z_arm_thread_is_in_user_mode(void)
 {
 	uint32_t value;
@@ -294,12 +311,14 @@ void configure_builtin_stack_guard(struct k_thread *thread)
 	 * than the default thread stack (ensured by design).
 	 */
 	uint32_t guard_start =
-		((thread->arch.priv_stack_start) && (__get_PSP() >= thread->arch.priv_stack_start))
-			? (uint32_t)thread->arch.priv_stack_start
-			: (uint32_t)thread->stack_obj;
+		((thread->arch.priv_stack_start) &&
+			(__get_PSP() >= thread->arch.priv_stack_start)) ?
+		(uint32_t)thread->arch.priv_stack_start :
+		(uint32_t)thread->stack_obj;
 
 	__ASSERT(thread->stack_info.start == ((uint32_t)thread->stack_obj),
-		 "stack_info.start does not point to the start of the thread allocated area.");
+		"stack_info.start does not point to the start of the"
+		"thread allocated area.");
 #else
 	uint32_t guard_start = thread->stack_info.start;
 #endif
@@ -313,11 +332,13 @@ void configure_builtin_stack_guard(struct k_thread *thread)
 
 #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
 
-#define IS_MPU_GUARD_VIOLATION(guard_start, guard_len, fault_addr, stack_ptr)                      \
-	((fault_addr != -EINVAL)                                                                   \
-		 ? ((fault_addr >= guard_start) && (fault_addr < (guard_start + guard_len)) &&     \
-		    (stack_ptr < (guard_start + guard_len)))                                       \
-		 : (stack_ptr < (guard_start + guard_len)))
+#define IS_MPU_GUARD_VIOLATION(guard_start, guard_len, fault_addr, stack_ptr) \
+	((fault_addr != -EINVAL) ? \
+	((fault_addr >= guard_start) && \
+	(fault_addr < (guard_start + guard_len)) && \
+	(stack_ptr < (guard_start + guard_len))) \
+	: \
+	(stack_ptr < (guard_start + guard_len)))
 
 /**
  * @brief Assess occurrence of current thread's stack corruption
@@ -365,10 +386,11 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp
 	}
 #endif
 
-#if (defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)) && defined(CONFIG_MPU_STACK_GUARD)
-	uint32_t guard_len = ((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0)
-				     ? MPU_GUARD_ALIGN_AND_SIZE_FLOAT
-				     : MPU_GUARD_ALIGN_AND_SIZE;
+#if (defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)) && \
+	defined(CONFIG_MPU_STACK_GUARD)
+	uint32_t guard_len =
+		((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) ?
+		MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE;
 #else
 	/* If MPU_STACK_GUARD is not enabled, the guard length is
 	 * effectively zero. Stack overflows may be detected only
@@ -382,8 +404,10 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp
 		/* User thread */
 		if (z_arm_thread_is_in_user_mode() == false) {
 			/* User thread in privilege mode */
-			if (IS_MPU_GUARD_VIOLATION(thread->arch.priv_stack_start - guard_len,
-						   guard_len, fault_addr, psp)) {
+			if (IS_MPU_GUARD_VIOLATION(
+				thread->arch.priv_stack_start - guard_len,
+					guard_len,
+				fault_addr, psp)) {
 				/* Thread's privilege stack corruption */
 				return thread->arch.priv_stack_start;
 			}
@@ -395,21 +419,26 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp
 		}
 	} else {
 		/* Supervisor thread */
-		if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len, guard_len,
-					   fault_addr, psp)) {
+		if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start -
+				guard_len,
+				guard_len,
+				fault_addr, psp)) {
 			/* Supervisor thread stack corruption */
 			return thread->stack_info.start;
 		}
 	}
 #else /* CONFIG_USERSPACE */
 #if defined(CONFIG_MULTITHREADING)
-	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len, guard_len, fault_addr,
-				   psp)) {
+	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
+			guard_len,
+			fault_addr, psp)) {
 		/* Thread stack corruption */
 		return thread->stack_info.start;
 	}
 #else
-	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack, guard_len, fault_addr, psp)) {
+	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack,
+			guard_len,
+			fault_addr, psp)) {
 		/* Thread stack corruption */
 		return (uint32_t)K_THREAD_STACK_BUFFER(z_main_stack);
 	}
@@ -493,7 +522,7 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
 {
 	z_arm_prepare_switch_to_main();
 
-	z_current_thread_set(main_thread);
+	_current = main_thread;
 
 #if defined(CONFIG_THREAD_LOCAL_STORAGE)
 	/* On Cortex-M, TLS uses a global variable as pointer to
@@ -543,23 +572,23 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
 	 * When calling arch_irq_unlock_outlined, LR is lost which is fine since
 	 * we do not intend to return after calling z_thread_entry.
 	 */
-	__asm__ volatile("mov   r4,  %0\n" /* force _main to be stored in a register */
-			 "msr   PSP, %1\n" /* __set_PSP(stack_ptr) */
+	__asm__ volatile (
+	"mov   r4,  %0\n"	/* force _main to be stored in a register */
+	"msr   PSP, %1\n"	/* __set_PSP(stack_ptr) */
 
-			 "movs  r0,  #0\n" /* arch_irq_unlock(0) */
-			 "ldr   r3, =arch_irq_unlock_outlined\n"
-			 "blx   r3\n"
+	"mov   r0,  #0\n"	/* arch_irq_unlock(0) */
+	"ldr   r3, =arch_irq_unlock_outlined\n"
+	"blx   r3\n"
 
-			 "mov   r0, r4\n" /* z_thread_entry(_main, NULL, NULL, NULL) */
-			 "movs  r1, #0\n"
-			 "movs  r2, #0\n"
-			 "movs  r3, #0\n"
-			 "ldr   r4, =z_thread_entry\n"
-			 /* We don’t intend to return, so there is no need to link. */
-			 "bx    r4\n"
-			 :
-			 : "r"(_main), "r"(stack_ptr)
-			 : "r0", "r1", "r2", "r3", "r4", "ip", "lr", "memory");
+	"mov   r0, r4\n"	/* z_thread_entry(_main, NULL, NULL, NULL) */
+	"mov   r1, #0\n"
+	"mov   r2, #0\n"
+	"mov   r3, #0\n"
+	"ldr   r4, =z_thread_entry\n"
+	"bx    r4\n"		/* We don’t intend to return, so there is no need to link. */
+	: "+r" (_main)
+	: "r" (stack_ptr)
+	: "r0", "r1", "r2", "r3", "r4", "ip", "lr");
 
 	CODE_UNREACHABLE;
 }
@@ -568,7 +597,7 @@ __used void arch_irq_unlock_outlined(unsigned int key)
 {
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	__enable_fault_irq(); /* alters FAULTMASK */
-	__enable_irq();       /* alters PRIMASK */
+	__enable_irq(); /* alters PRIMASK */
 #endif
 	arch_irq_unlock(key);
 }
@@ -580,13 +609,14 @@ __used unsigned int arch_irq_lock_outlined(void)
 
 #if !defined(CONFIG_MULTITHREADING)
 
-FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(k_thread_entry_t main_entry, void *p1,
-							  void *p2, void *p3)
+FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
+	k_thread_entry_t main_entry, void *p1, void *p2, void *p3)
 {
 	z_arm_prepare_switch_to_main();
 
 	/* Set PSP to the highest address of the main stack. */
-	char *psp = K_THREAD_STACK_BUFFER(z_main_stack) + K_THREAD_STACK_SIZEOF(z_main_stack);
+	char *psp =	K_THREAD_STACK_BUFFER(z_main_stack) +
+		K_THREAD_STACK_SIZEOF(z_main_stack);
 
 #if defined(CONFIG_BUILTIN_STACK_GUARD)
 	char *psplim = (K_THREAD_STACK_BUFFER(z_main_stack));
@@ -606,31 +636,31 @@ FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(k_thread_entry_t main_
 	 * with the thread entry process.
 	 */
 
-	__asm__ volatile(
+	__asm__ volatile (
 #ifdef CONFIG_BUILTIN_STACK_GUARD
-		"msr  PSPLIM, %[_psplim]\n" /* __set_PSPLIM(_psplim) */
+	"msr  PSPLIM, %[_psplim]\n" /* __set_PSPLIM(_psplim) */
 #endif
-		"msr  PSP, %[_psp]\n" /* __set_PSP(psp) */
-		"movs r0, #0\n"
-		"ldr r1, =arch_irq_unlock_outlined\n"
-		"blx r1\n"
+	"msr  PSP, %[_psp]\n"       /* __set_PSP(psp) */
+	"mov r0, #0\n"
+	"ldr r1, =arch_irq_unlock_outlined\n"
+	"blx r1\n"
 
-		"mov r0, %[_p1]\n"
-		"mov r1, %[_p2]\n"
-		"mov r2, %[_p3]\n"
-		"blx  %[_main_entry]\n" /* main_entry(p1, p2, p3) */
+	"mov r0, %[_p1]\n"
+	"mov r1, %[_p2]\n"
+	"mov r2, %[_p3]\n"
+	"blx  %[_main_entry]\n"     /* main_entry(p1, p2, p3) */
 
-		"ldr r0, =arch_irq_lock_outlined\n"
-		"blx r0\n"
-		"loop: b loop\n\t" /* while (true); */
-		:
-		: [_p1] "r"(p1), [_p2] "r"(p2), [_p3] "r"(p3), [_psp] "r"(psp),
-		  [_main_entry] "r"(main_entry)
+	"ldr r0, =arch_irq_lock_outlined\n"
+	"blx r0\n"
+	"loop: b loop\n\t"    /* while (true); */
+	:
+	: [_p1]"r" (p1), [_p2]"r" (p2), [_p3]"r" (p3),
+	  [_psp]"r" (psp), [_main_entry]"r" (main_entry)
 #ifdef CONFIG_BUILTIN_STACK_GUARD
-			  ,
-		  [_psplim] "r"(psplim)
+	, [_psplim]"r" (psplim)
 #endif
-		: "r0", "r1", "r2", "ip", "lr");
+	: "r0", "r1", "r2", "ip", "lr"
+	);
 
 	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
 }

arch/arm/core/cortex_m/timing.c

@@ -28,7 +28,8 @@
  */
 static inline uint64_t z_arm_dwt_freq_get(void)
 {
-#if defined(CONFIG_CMSIS_CORE_HAS_SYSTEM_CORE_CLOCK)
+#if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) || \
+	defined(CONFIG_SOC_SERIES_IMXRT6XX)
 	/*
 	 * DWT frequency is taken directly from the
 	 * System Core clock (CPU) frequency, if the
@@ -73,6 +74,7 @@ static inline uint64_t z_arm_dwt_freq_get(void)
 		} while ((dcyc == 0) || (ddwt == 0));
 
 		dwt_frequency = (cyc_freq * ddwt) / dcyc;
+
 	}
 	return dwt_frequency;
 #endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */
@@ -99,9 +101,10 @@ timing_t arch_timing_counter_get(void)
 	return (timing_t)z_arm_dwt_get_cycles();
 }
 
-uint64_t arch_timing_cycles_get(volatile timing_t *const start, volatile timing_t *const end)
+uint64_t arch_timing_cycles_get(volatile timing_t *const start,
+				volatile timing_t *const end)
 {
-	return ((uint32_t)*end - (uint32_t)*start);
+	return (*end - *start);
 }
 
 uint64_t arch_timing_freq_get(void)

arch/arm/core/cortex_m/tz/CMakeLists.txt

@@ -2,10 +2,7 @@
 
 # '-mcmse' enables the generation of code for the Secure state of the ARMv8-M
 # Security Extensions. This option is required when building a Secure firmware.
-
-zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE $<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,cmse>>)
-zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE $<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,cmse>>)
-zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE $<$<COMPILE_LANGUAGE:ASM>:$<TARGET_PROPERTY:asm,cmse>>)
+zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE -mcmse)
 
 if(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)
 

arch/arm/core/fatal.c

@@ -101,9 +101,8 @@ void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf)
  *
  * @param esf exception frame
  * @param callee_regs Callee-saved registers (R4-R11)
- * @param exc_return EXC_RETURN value present in LR after exception entry.
  */
-void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs, uint32_t exc_return)
+void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs)
 {
 #if !(defined(CONFIG_EXTRA_EXCEPTION_INFO) && defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE))
 	ARG_UNUSED(callee_regs);
@@ -111,8 +110,6 @@ void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs,
 	/* Stacked R0 holds the exception reason. */
 	unsigned int reason = esf->basic.r0;
 
-	z_arm_set_fault_sp(esf, exc_return);
-
 #if defined(CONFIG_USERSPACE)
 	if (z_arm_preempted_thread_in_user_mode(esf)) {
 		/*

arch/arm/core/mmu/arm_mmu.c

@@ -304,15 +304,13 @@ static struct arm_mmu_perms_attrs arm_mmu_convert_attr_flags(uint32_t attrs)
 		perms_attrs.cacheable = 0;
 		perms_attrs.domain    = ARM_MMU_DOMAIN_DEVICE;
 
-		/*
-		 * ARM deprecates the marking of Device memory with a
-		 * shareability attribute other than Outer Shareable
-		 * or Shareable. This means ARM strongly recommends
-		 * that Device memory is never assigned a shareability
-		 * attribute of Non-shareable or Inner Shareable.
-		 */
-		perms_attrs.tex        = 0;
-		perms_attrs.bufferable = 1;
+		if (attrs & MATTR_SHARED) {
+			perms_attrs.tex        = 0;
+			perms_attrs.bufferable = 1;
+		} else {
+			perms_attrs.tex        = 2;
+			perms_attrs.bufferable = 0;
+		}
 	} else if (attrs & MT_NORMAL) {
 		/*
 		 * TEX[2] is always 1. TEX[1:0] contain the outer cache attri-

arch/arm/core/mpu/CMakeLists.txt

@@ -4,11 +4,11 @@ zephyr_library()
 
 zephyr_library_sources(                             arm_core_mpu.c)
 zephyr_library_sources_ifdef(CONFIG_CPU_HAS_ARM_MPU arm_mpu.c)
-zephyr_library_sources_ifdef(CONFIG_CPU_HAS_NXP_SYSMPU nxp_mpu.c)
+zephyr_library_sources_ifdef(CONFIG_CPU_HAS_NXP_MPU nxp_mpu.c)
 
 if(CONFIG_CPU_CORTEX_M AND NOT CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS)
   zephyr_library_sources_ifdef(CONFIG_CPU_HAS_ARM_MPU arm_mpu_regions.c)
-  zephyr_library_sources_ifdef(CONFIG_CPU_HAS_NXP_SYSMPU nxp_mpu_regions.c)
+  zephyr_library_sources_ifdef(CONFIG_CPU_HAS_NXP_MPU nxp_mpu_regions.c)
 endif()
 
 if (CONFIG_CPU_AARCH32_CORTEX_R)

arch/arm/core/mpu/Kconfig

@@ -5,10 +5,50 @@
 
 if CPU_HAS_MPU
 
+config ARM_MPU
+	bool "ARM MPU Support"
+	select MPU
+	select SRAM_REGION_PERMISSIONS
+	select THREAD_STACK_INFO
+	select ARCH_HAS_EXECUTABLE_PAGE_BIT
+	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(CPU_HAS_NXP_MPU || ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
+	select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if CPU_HAS_ARM_MPU && (ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
+	select MPU_GAP_FILLING if AARCH32_ARMV8_R
+	select ARCH_MEM_DOMAIN_SUPPORTS_ISOLATED_STACKS
+	select MEM_DOMAIN_ISOLATED_STACKS
+	help
+	  MCU implements Memory Protection Unit.
+
+	  Notes:
+	  The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
+	  alignment of MPU region base address and size.
+
+	  The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
+	  to have power-of-two alignment for base address and region size.
+
+	  The ARMv8-M MPU requires the active MPU regions be non-overlapping.
+	  As a result of this, the ARMv8-M MPU needs to fully partition the
+	  memory map when programming dynamic memory regions (e.g. PRIV stack
+	  guard, user thread stack, and application memory domains), if the
+	  system requires PRIV access policy different from the access policy
+	  of the ARMv8-M background memory map. The application developer may
+	  enforce full PRIV (kernel) memory partition by enabling the
+	  CONFIG_MPU_GAP_FILLING option.
+	  By not enforcing full partition, MPU may leave part of kernel
+	  SRAM area covered only by the default ARMv8-M memory map. This
+	  is fine for User Mode, since the background ARM map does not
+	  allow nPRIV access at all. However, since the background map
+	  policy allows instruction fetches by privileged code, forcing
+	  this Kconfig option off prevents the system from directly
+	  triggering MemManage exceptions upon accidental attempts to
+	  execute code from SRAM in XIP builds.
+	  Since this does not compromise User Mode, we make the skipping
+	  of full partitioning the default behavior for the ARMv8-M MPU
+	  driver.
+
 config ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
 	int
 	default 256 if ARM_MPU && ARMV6_M_ARMV8_M_BASELINE && !ARMV8_M_BASELINE
-	default 128 if ARM_MPU && FPU_SHARING && MPU_STACK_GUARD
 	default 64 if ARM_MPU && AARCH32_ARMV8_R
 	default 32 if ARM_MPU
 	default 4

arch/arm/core/mpu/arm_core_mpu_dev.h

@@ -76,7 +76,7 @@ struct k_thread;
  */
 #if (defined(CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS) && \
 		defined(CONFIG_MPU_GAP_FILLING)) \
-	|| defined(CONFIG_CPU_HAS_NXP_SYSMPU)
+	|| defined(CONFIG_CPU_HAS_NXP_MPU)
 /*
  * When dynamic regions may not be defined on top of statically
  * allocated memory regions, defining a region for a supervisor
@@ -96,7 +96,7 @@ struct k_thread;
  * using a single MPU region.
  */
 #define ARM_CORE_MPU_NUM_MPU_REGIONS_FOR_MPU_STACK_GUARD 1
-#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS || CPU_HAS_NXP_SYSMPU */
+#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS || CPU_HAS_NXP_MPU */
 
 #endif /* CONFIG_USERSPACE */
 

arch/arm/core/mpu/arm_mpu.c

@@ -37,14 +37,6 @@ BUILD_ASSERT((DT_FOREACH_STATUS_OKAY_NODE_VARGS(
 	      NODE_HAS_PROP_AND_OR, zephyr_memory_region_mpu) false) == false,
 	      "`zephyr,memory-region-mpu` was deprecated in favor of `zephyr,memory-attr`");
 
-#define NULL_PAGE_DETECT_NODE_FINDER(node_id, prop)                                                \
-	(DT_NODE_HAS_PROP(node_id, prop) && (DT_REG_ADDR(node_id) == 0) &&                         \
-	 (DT_REG_SIZE(node_id) >= CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE)) ||
-
-#define DT_NULL_PAGE_DETECT_NODE_EXIST                                                             \
-	(DT_FOREACH_STATUS_OKAY_VARGS(zephyr_memory_region, NULL_PAGE_DETECT_NODE_FINDER,          \
-				      zephyr_memory_attr) false)
-
 /*
  * Global status variable holding the number of HW MPU region indices, which
  * have been reserved by the MPU driver to program the static (fixed) memory
@@ -93,7 +85,7 @@ static int region_allocate_and_init(const uint8_t index,
 						    (reg).dt_addr,	\
 						    (reg).dt_size,	\
 						    _ATTR)
-#ifdef CONFIG_MEM_ATTR
+
 /* This internal function programs the MPU regions defined in the DT when using
  * the `zephyr,memory-attr = <( DT_MEM_ARM(...) )>` property.
  */
@@ -158,7 +150,7 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index)
 
 	return 0;
 }
-#endif /* CONFIG_MEM_ATTR */
+
 /* This internal function programs an MPU region
  * of a given configuration at a given MPU index.
  */
@@ -459,13 +451,13 @@ int z_arm_mpu_init(void)
 
 	/* Update the number of programmed MPU regions. */
 	static_regions_num = mpu_config.num_regions;
-#ifdef CONFIG_MEM_ATTR
+
 	/* DT-defined MPU regions. */
 	if (mpu_configure_regions_from_dt(&static_regions_num) == -EINVAL) {
 		__ASSERT(0, "Failed to allocate MPU regions from DT\n");
 		return -EINVAL;
 	}
-#endif /* CONFIG_MEM_ATTR */
+
 	/* Clear all regions before enabling MPU */
 	for (int i = static_regions_num; i < get_num_regions(); i++) {
 		mpu_clear_region(i);
@@ -478,9 +470,7 @@ int z_arm_mpu_init(void)
 	 */
 #if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_MPU)
 #if (defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)) && \
-	(CONFIG_FLASH_BASE_ADDRESS > CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE) && \
-	(!DT_NULL_PAGE_DETECT_NODE_EXIST)
-
+	(CONFIG_FLASH_BASE_ADDRESS > CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE)
 #pragma message "Null-Pointer exception detection cannot be configured on un-mapped flash areas"
 #else
 	const struct z_arm_mpu_partition unmap_region =	{

arch/arm/core/mpu/arm_mpu_regions.c

@@ -10,7 +10,6 @@
 #include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
 
 static const struct arm_mpu_region mpu_regions[] = {
-#ifdef CONFIG_XIP
 	/* Region 0 */
 	MPU_REGION_ENTRY("FLASH_0",
 			 CONFIG_FLASH_BASE_ADDRESS,
@@ -20,8 +19,6 @@ static const struct arm_mpu_region mpu_regions[] = {
 #else
 			 REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
 #endif
-#endif
-
 	/* Region 1 */
 	MPU_REGION_ENTRY("SRAM_0",
 			 CONFIG_SRAM_BASE_ADDRESS,

arch/arm/core/mpu/nxp_mpu.c

@@ -151,7 +151,7 @@ static int region_allocate_and_init(const uint8_t index,
 				  .end  = (reg).dt_addr + (reg).dt_size,	\
 				  .attr = _ATTR,				\
 				}
-#ifdef CONFIG_MEM_ATTR
+
 /* This internal function programs the MPU regions defined in the DT when using
  * the `zephyr,memory-attr = <( DT_MEM_ARM(...) )>` property.
  */
@@ -198,7 +198,7 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index)
 
 	return 0;
 }
-#endif /* CONFIG_MEM_ATTR */
+
 /**
  * This internal function is utilized by the MPU driver to combine a given
  * region attribute configuration and size and fill-in a driver-specific
@@ -700,13 +700,13 @@ int z_arm_mpu_init(void)
 
 	/* Update the number of programmed MPU regions. */
 	static_regions_num = mpu_config.num_regions;
-#ifdef CONFIG_MEM_ATTR
+
 	/* DT-defined MPU regions. */
 	if (mpu_configure_regions_from_dt(&static_regions_num) == -EINVAL) {
 		__ASSERT(0, "Failed to allocate MPU regions from DT\n");
 		return -EINVAL;
 	}
-#endif /* CONFIG_MEM_ATTR */
+
 	arm_core_mpu_enable();
 
 	return 0;

arch/arm/core/offsets/offsets_aarch32.c

@@ -83,21 +83,17 @@ GEN_OFFSET_SYM(_thread_stack_info_t, start);
  */
 #if defined(CONFIG_PM_S2RAM)
 GEN_OFFSET_SYM(_cpu_context_t, msp);
+GEN_OFFSET_SYM(_cpu_context_t, msplim);
 GEN_OFFSET_SYM(_cpu_context_t, psp);
-GEN_OFFSET_SYM(_cpu_context_t, primask);
-GEN_OFFSET_SYM(_cpu_context_t, control);
+GEN_OFFSET_SYM(_cpu_context_t, psplim);
+GEN_OFFSET_SYM(_cpu_context_t, apsr);
+GEN_OFFSET_SYM(_cpu_context_t, ipsr);
+GEN_OFFSET_SYM(_cpu_context_t, epsr);
 
-#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-/* Registers present only on ARMv7-M and ARMv8-M Mainline */
+GEN_OFFSET_SYM(_cpu_context_t, primask);
 GEN_OFFSET_SYM(_cpu_context_t, faultmask);
 GEN_OFFSET_SYM(_cpu_context_t, basepri);
-#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
-
-#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
-/* Registers present only on certain ARMv8-M implementations */
-GEN_OFFSET_SYM(_cpu_context_t, msplim);
-GEN_OFFSET_SYM(_cpu_context_t, psplim);
-#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */
+GEN_OFFSET_SYM(_cpu_context_t, control);
 #endif /* CONFIG_PM_S2RAM */
 
 #endif /* _ARM_OFFSETS_INC_ */

arch/arm/core/tls.c

@@ -40,10 +40,8 @@ size_t arch_tls_stack_setup(struct k_thread *new_thread, char *stack_ptr)
 	stack_ptr -= z_tls_data_size();
 	z_tls_copy(stack_ptr);
 
-#ifndef __IAR_SYSTEMS_ICC__
 	/* Skip two pointers due to toolchain */
 	stack_ptr -= sizeof(uintptr_t) * 2;
-#endif
 
 	/*
 	 * Set thread TLS pointer which is used in

arch/arm/include/cortex_a_r/exception.h

@@ -43,15 +43,6 @@ static ALWAYS_INLINE bool arch_is_in_nested_exception(const struct arch_esf *esf
 	return (arch_curr_cpu()->arch.exc_depth > 1U) ? (true) : (false);
 }
 
-/**
- * @brief No current implementation where core dump is not supported
- *
- * @param esf exception frame
- * @param exc_return EXC_RETURN value present in LR after exception entry.
- */
-static ALWAYS_INLINE void z_arm_set_fault_sp(const struct arch_esf *esf, uint32_t exc_return)
-{}
-
 #if defined(CONFIG_USERSPACE)
 /*
  * This function is used by privileged code to determine if the thread

arch/arm/include/cortex_a_r/kernel_arch_func.h

@@ -20,8 +20,6 @@
 #ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_KERNEL_ARCH_FUNC_H_
 #define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_KERNEL_ARCH_FUNC_H_
 
-#include <zephyr/platform/hooks.h>
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -30,28 +28,10 @@ extern "C" {
 
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
-#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
-	soc_per_core_init_hook();
-#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 #ifndef CONFIG_USE_SWITCH
 
-static ALWAYS_INLINE int arch_swap(unsigned int key)
-{
-	/* store off key and return value */
-	_current->arch.basepri = key;
-	_current->arch.swap_return_value = -EAGAIN;
-
-	z_arm_cortex_r_svc();
-	irq_unlock(key);
-
-	/* Context switch is performed here. Returning implies the
-	 * thread has been context-switched-in again.
-	 */
-	return _current->arch.swap_return_value;
-}
-
 static ALWAYS_INLINE void
 arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
 {

arch/arm/include/cortex_m/cmse.h

@@ -139,7 +139,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  * where typeof is used instead of __typeof__)
  */
 #ifndef typeof
-#define typeof __typeof__
+#define typeof  __typeof__
 #endif
 
 /**
@@ -157,7 +157,8 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  *
  * @return p_obj if object is readable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_READ_OK(p_obj) cmse_check_pointed_object(p_obj, CMSE_MPU_READ)
+#define ARM_CMSE_OBJECT_READ_OK(p_obj) \
+	cmse_check_pointed_object(p_obj, CMSE_MPU_READ)
 
 /**
  * @brief Read accessibility of an object (nPRIV mode)
@@ -174,7 +175,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  *
  * @return p_obj if object is readable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_UNPRIV_READ_OK(p_obj)                                                      \
+#define ARM_CMSE_OBJECT_UNPRIV_READ_OK(p_obj) \
 	cmse_check_pointed_object(p_obj, CMSE_MPU_UNPRIV | CMSE_MPU_READ)
 
 /**
@@ -192,7 +193,8 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  *
  * @return p_obj if object is Read and Writable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_READWRITE_OK(p_obj) cmse_check_pointed_object(p_obj, CMSE_MPU_READWRITE)
+#define ARM_CMSE_OBJECT_READWRITE_OK(p_obj) \
+	cmse_check_pointed_object(p_obj, CMSE_MPU_READWRITE)
 
 /**
  * @brief Read and Write accessibility of an object (nPRIV mode)
@@ -209,7 +211,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  *
  * @return p_obj if object is Read and Writable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_UNPRIV_READWRITE_OK(p_obj)                                                 \
+#define ARM_CMSE_OBJECT_UNPRIV_READWRITE_OK(p_obj) \
 	cmse_check_pointed_object(p_obj, CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE)
 
 #if defined(CONFIG_ARM_SECURE_FIRMWARE)
@@ -229,7 +231,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  * @param addr The address for which the MPU region is requested
  *
  * @return a valid MPU region number or -EINVAL
- */
+  */
 int arm_cmse_mpu_nonsecure_region_get(uint32_t addr);
 
 /**
@@ -247,7 +249,7 @@ int arm_cmse_mpu_nonsecure_region_get(uint32_t addr);
  * @param addr The address for which the SAU region is requested
  *
  * @return a valid SAU region number or -EINVAL
- */
+  */
 int arm_cmse_sau_region_get(uint32_t addr);
 
 /**
@@ -265,7 +267,7 @@ int arm_cmse_sau_region_get(uint32_t addr);
  * @param addr The address for which the IDAU region is requested
  *
  * @return a valid IDAU region number or -EINVAL
- */
+  */
 int arm_cmse_idau_region_get(uint32_t addr);
 
 /**
@@ -340,7 +342,8 @@ int arm_cmse_addr_nonsecure_readwrite_ok(uint32_t addr, int force_npriv);
  *
  * @return 1 if address range is readable, 0 otherwise.
  */
-int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, int force_npriv);
+int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size,
+	int force_npriv);
 
 /**
  * @brief Non-Secure Read and Write accessibility of an address range
@@ -362,7 +365,8 @@ int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, int forc
  *
  * @return 1 if address range is readable, 0 otherwise.
  */
-int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int force_npriv);
+int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size,
+	int force_npriv);
 
 /**
  * @brief Non-Secure Read accessibility of an object
@@ -379,7 +383,7 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int
  *
  * @return p_obj if object is readable from Non-Secure state, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_NONSECURE_READ_OK(p_obj)                                                   \
+#define ARM_CMSE_OBJECT_NONSECURE_READ_OK(p_obj) \
 	cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_READ)
 
 /**
@@ -397,8 +401,9 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int
  *
  * @return p_obj if object is readable from Non-Secure state, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_NONSECURE_UNPRIV_READ_OK(p_obj)                                            \
-	cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READ)
+#define ARM_CMSE_OBJECT_NONSECURE_UNPRIV_READ_OK(p_obj) \
+	cmse_check_pointed_object(p_obj, \
+		CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READ)
 
 /**
  * @brief Non-Secure Read and Write accessibility of an object
@@ -415,7 +420,7 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int
  *
  * @return p_obj if object is Non-Secure Read and Writable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_NONSECURE_READWRITE_OK(p_obj)                                              \
+#define ARM_CMSE_OBJECT_NONSECURE_READWRITE_OK(p_obj) \
 	cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_READWRITE)
 
 /**
@@ -433,8 +438,9 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int
  *
  * @return p_obj if object is Non-Secure Read and Writable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_NON_SECURE_UNPRIV_READWRITE_OK(p_obj)                                      \
-	cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE)
+#define ARM_CMSE_OBJECT_NON_SECURE_UNPRIV_READWRITE_OK(p_obj) \
+	cmse_check_pointed_object(p_obj, \
+			CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE)
 
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */