ci: integrate requirements into docs workflow.

Integrate into doc workflow.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.clang-format

@@ -46,7 +46,6 @@ ForEachMacros:
   - 'SYS_DLIST_FOR_EACH_CONTAINER_SAFE'
   - 'SYS_DLIST_FOR_EACH_NODE'
   - 'SYS_DLIST_FOR_EACH_NODE_SAFE'
-  - 'SYS_SEM_LOCK'
   - 'SYS_SFLIST_FOR_EACH_CONTAINER'
   - 'SYS_SFLIST_FOR_EACH_CONTAINER_SAFE'
   - 'SYS_SFLIST_FOR_EACH_NODE'

.github/workflows/bsim-tests.yaml

@@ -18,7 +18,6 @@ on:
       - "include/zephyr/arch/posix/**"
       - "scripts/native_simulator/**"
       - "samples/net/sockets/echo_*/**"
-      - "modules/mbedtls/**"
       - "modules/openthread/**"
       - "subsys/net/l2/openthread/**"
       - "include/zephyr/net/openthread.h"
@@ -37,7 +36,7 @@ jobs:
     runs-on:
       group: zephyr-runner-v2-linux-x64-4xlarge
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
       options: '--entrypoint /bin/bash'
     env:
       ZEPHYR_TOOLCHAIN_VARIANT: zephyr
@@ -104,7 +103,6 @@ jobs:
             tests/bsim/*
             boards/nordic/nrf5*/*dt*
             dts/*/nordic/
-            modules/mbedtls/**
 
       - name: Check if Bluethooth files changed
         uses: tj-actions/changed-files@v45

.github/workflows/clang.yaml

@@ -12,7 +12,7 @@ jobs:
     runs-on:
       group: zephyr-runner-v2-linux-x64-4xlarge
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
       options: '--entrypoint /bin/bash'
     strategy:
       fail-fast: false

.github/workflows/codecov.yaml

@@ -14,7 +14,7 @@ jobs:
     runs-on:
       group: zephyr-runner-v2-linux-x64-4xlarge
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
       options: '--entrypoint /bin/bash'
     strategy:
       fail-fast: false
@@ -34,7 +34,7 @@ jobs:
       CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3"
       CCACHE_REMOTE_ONLY: "true"
       # `--specs` is ignored because ccache is unable to resovle the toolchain specs file path.
-      CCACHE_IGNOREOPTIONS: '-specs=* --specs=*'
+      CCACHE_IGNOREOPTIONS: '--specs=*'
     steps:
       - name: Apply container owner mismatch workaround
         run: |

.github/workflows/devicetree_checks.yml

@@ -26,7 +26,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-22.04, macos-14, windows-2022]
     steps:
     - name: checkout

.github/workflows/doc-build.yml

@@ -42,7 +42,6 @@ jobs:
       with:
         files: |
           doc/
-          boards/**/doc/
           **.rst
           include/
           kernel/include/kernel_arch_interface.h
@@ -111,11 +110,22 @@ jobs:
         pip3 install west==${WEST_VERSION}
         pip3 install cmake==${CMAKE_VERSION}
         pip3 install coverxygen
+        pip3 install mlx.traceability strictdoc
 
     - name: west setup
       run: |
         west init -l .
 
+    - name: prcoess requirements
+      run: |
+        west update reqmgmt
+        pushd ../tools/reqmgmt
+        strictdoc export . --formats json
+        popd
+        cp ../tools/reqmgmt/output/json/index.json doc/requirements/requirements.json
+        python3 doc/requirements/create_req.py --json doc/requirements/requirements.json  --output doc/requirements/requirements.dox
+
+
     - name: build-docs
       shell: bash
       run: |
@@ -136,17 +146,10 @@ jobs:
         SPHINXOPTS_EXTRA="-q -t publish" \
         make -C doc ${DOC_TARGET}
 
-        # API documentation coverage
-        python3 -m coverxygen --xml-dir  doc/_build/html/doxygen/xml/ --src-dir include/ --output doc-coverage.info
-        # deprecated page causing issues
-        lcov --remove doc-coverage.info \*/deprecated > new.info
-        genhtml --no-function-coverage --no-branch-coverage new.info -o coverage-report
-
     - name: compress-docs
       run: |
         tar --use-compress-program="xz -T0" -cf html-output.tar.xz --directory=doc/_build html
         tar --use-compress-program="xz -T0" -cf api-output.tar.xz --directory=doc/_build html/doxygen/html
-        tar --use-compress-program="xz -T0" -cf api-coverage.tar.xz coverage-report
 
     - name: upload-build
       uses: actions/upload-artifact@v4
@@ -154,12 +157,6 @@ jobs:
         name: html-output
         path: html-output.tar.xz
 
-    - name: upload-api-coverage
-      uses: actions/upload-artifact@v4
-      with:
-        name: api-coverage
-        path: api-coverage.tar.xz
-
     - name: process-pr
       if: github.event_name == 'pull_request'
       run: |

.github/workflows/doc-publish-pr.yml

@@ -21,24 +21,16 @@ jobs:
 
     steps:
     - name: Download artifacts
-      id: download-artifacts
       uses: dawidd6/action-download-artifact@v6
       with:
         workflow: doc-build.yml
         run_id: ${{ github.event.workflow_run.id }}
-        if_no_artifact_found: ignore
 
     - name: Load PR number
-      if: steps.download-artifacts.outputs.found_artifact == 'true'
-      uses: actions/github-script@v7
-      with:
-        script: |
-          let fs = require("fs");
-          let pr_number = Number(fs.readFileSync("./pr_num/pr_num"));
-          core.exportVariable("PR_NUM", pr_number);
+      run: |
+        echo "PR_NUM=$(<pr_num/pr_num)" >> $GITHUB_ENV
 
     - name: Check PR number
-      if: steps.download-artifacts.outputs.found_artifact == 'true'
       id: check-pr
       uses: carpentries/actions/check-valid-pr@v0.14.0
       with:
@@ -46,15 +38,12 @@ jobs:
         sha: ${{ github.event.workflow_run.head_sha }}
 
     - name: Validate PR number
-      if: |
-        steps.download-artifacts.outputs.found_artifact == 'true' &&
-        steps.check-pr.outputs.VALID != 'true'
+      if: steps.check-pr.outputs.VALID != 'true'
       run: |
         echo "ABORT: PR number validation failed!"
         exit 1
 
     - name: Uncompress HTML docs
-      if: steps.download-artifacts.outputs.found_artifact == 'true'
       run: |
         tar xf html-output/html-output.tar.xz -C html-output
         if [ -f api-coverage/api-coverage.tar.xz ]; then
@@ -62,7 +51,6 @@ jobs:
         fi
 
     - name: Configure AWS Credentials
-      if: steps.download-artifacts.outputs.found_artifact == 'true'
       uses: aws-actions/configure-aws-credentials@v4
       with:
         aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_PR_ACCESS_KEY_ID }}
@@ -70,7 +58,6 @@ jobs:
         aws-region: us-east-1
 
     - name: Upload to AWS S3
-      if: steps.download-artifacts.outputs.found_artifact == 'true'
       env:
         HEAD_BRANCH: ${{ github.event.workflow_run.head_branch }}
       run: |

.github/workflows/errno.yml

@@ -10,7 +10,7 @@ jobs:
   check-errno:
     runs-on: ubuntu-22.04
     container:
-      image: ghcr.io/zephyrproject-rtos/ci:v0.27.4
+      image: ghcr.io/zephyrproject-rtos/ci:v0.26.13
 
     steps:
       - name: Apply container owner mismatch workaround

.github/workflows/footprint-tracking.yml

@@ -26,11 +26,8 @@ jobs:
       group: zephyr-runner-v2-linux-x64-4xlarge
     if: github.repository_owner == 'zephyrproject-rtos'
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
       options: '--entrypoint /bin/bash'
-    defaults:
-      run:
-        shell: bash
     strategy:
       fail-fast: false
     env:
@@ -96,33 +93,3 @@ jobs:
           . .venv/bin/activate
           pip3 install awscli
           aws s3 sync  --quiet footprint_data/ s3://testing.zephyrproject.org/footprint_data/
-
-      - name: Transform Footprint data to Twister JSON reports
-        run: |
-          shopt -s globstar
-          export ZEPHYR_BASE=${PWD}
-          python3 ./scripts/footprint/pack_as_twister.py -vvv \
-            --plan ./scripts/footprint/plan.txt \
-            --test-name='name.feature' \
-            ./footprint_data/**/
-
-      - name: Upload to ElasticSearch
-        env:
-          ELASTICSEARCH_KEY: ${{ secrets.ELASTICSEARCH_KEY }}
-          ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443"
-          ELASTICSEARCH_INDEX: ${{ vars.FOOTPRINT_TRACKING_INDEX }}
-        run: |
-          shopt -s globstar
-          pip3 install -U elasticsearch
-          run_date=`date --iso-8601=minutes`
-          python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \
-            --flatten footprint \
-            --flatten-list-names "{'children':'name'}" \
-            --transform "{ 'footprint_name': '^(?P<footprint_area>([^\/]+\/){0,2})(?P<footprint_path>([^\/]*\/)*)(?P<footprint_symbol>[^\/]*)$' }" \
-            --run-id "${{ github.run_id }}" \
-            --run-attempt "${{ github.run_attempt }}" \
-            --run-workflow "footprint-tracking:${{ github.event_name }}" \
-            --run-branch "${{ github.ref_name }}" \
-            -i ${ELASTICSEARCH_INDEX} \
-            ./footprint_data/**/twister_footprint.json
-        #

.github/workflows/hello_world_multiplatform.yaml

@@ -69,7 +69,7 @@ jobs:
           elif [ "${{ runner.os }}" = "Windows" ]; then
             EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O/tmp/twister-out"
           fi
-          ./scripts/twister --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS
+          ./scripts/twister --force-color --inline-logs -T samples/hello_world -v $EXTRA_TWISTER_FLAGS
 
       - name: Upload artifacts
         if: failure()
@@ -78,4 +78,3 @@ jobs:
           if-no-files-found: ignore
           path:
             zephyr/twister-out/*/samples/hello_world/sample.basic.helloworld/build.log
-            zephyr/twister-out/*/samples/cpp/hello_world/sample.cpp.helloworld/build.log

.github/workflows/pylib_tests.yml

@@ -25,7 +25,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-22.04]
     steps:
     - name: checkout

.github/workflows/scripts_tests.yml

@@ -25,7 +25,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-20.04]
     steps:
       - name: checkout

.github/workflows/twister.yaml

@@ -25,7 +25,7 @@ jobs:
     runs-on:
       group: zephyr-runner-v2-linux-x64-4xlarge
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
       options: '--entrypoint /bin/bash'
     outputs:
       subset: ${{ steps.output-services.outputs.subset }}
@@ -130,7 +130,7 @@ jobs:
     needs: twister-build-prep
     if: needs.twister-build-prep.outputs.size != 0
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823
       options: '--entrypoint /bin/bash'
     strategy:
       fail-fast: false
@@ -142,13 +142,13 @@ jobs:
       CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3"
       CCACHE_REMOTE_ONLY: "true"
       # `--specs` is ignored because ccache is unable to resolve the toolchain specs file path.
-      CCACHE_IGNOREOPTIONS: '-specs=* --specs=*'
+      CCACHE_IGNOREOPTIONS: '--specs=*'
       BSIM_OUT_PATH: /opt/bsim/
       BSIM_COMPONENTS_PATH: /opt/bsim/components
       TWISTER_COMMON: ' --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 '
       DAILY_OPTIONS: ' -M --build-only --all --show-footprint'
       PR_OPTIONS: ' --clobber-output --integration'
-      PUSH_OPTIONS: ' --clobber-output -M --show-footprint --report-filtered'
+      PUSH_OPTIONS: ' --clobber-output -M --show-footprint'
       COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}
       BASE_REF: ${{ github.base_ref }}
     steps:

.github/workflows/twister_tests.yml

@@ -32,7 +32,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-22.04]
     steps:
     - name: checkout

.github/workflows/twister_tests_blackbox.yml

@@ -21,10 +21,10 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-22.04]
     container:
-      image: ghcr.io/zephyrproject-rtos/ci:v0.27.4
+      image: ghcr.io/zephyrproject-rtos/ci:v0.26.13
 
     steps:
     - name: Apply Container Owner Mismatch Workaround

.github/workflows/west_cmds.yml

@@ -29,7 +29,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        python-version: ['3.10', '3.11', '3.12', '3.13']
+        python-version: ['3.10', '3.11', '3.12']
         os: [ubuntu-22.04, macos-14, windows-2022]
     steps:
     - name: checkout
@@ -66,7 +66,7 @@ jobs:
     - name: install pytest
       run: |
         pip3 install wheel
-        pip3 install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial anytree
+        pip3 install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial
     - name: run pytest-win
       if: runner.os == 'Windows'
       run: |

.gitignore

@@ -59,17 +59,6 @@ venv
 .clangd
 new.info
 
-# Cargo drops lock files in projects to capture resolved dependencies.
-# We don't want to record these.
-Cargo.lock
-
-# Cargo encourages a .cargo/config.toml file to symlink to a generated file.  Don't save these.
-.cargo/
-
-# Normal west builds will place the Rust target directory under the build directory.  However,
-# sometimes IDEs and such will litter these target directories as well.
-target/
-
 # CI output
 compliance.xml
 _error.types
@@ -103,5 +92,4 @@ ModulesMaintainers.txt
 Nits.txt
 Pylint.txt
 SphinxLint.txt
-TextEncoding.txt
 YAMLLint.txt

CMakeLists.txt

@@ -598,8 +598,6 @@ add_custom_command(
   COMMAND_EXPAND_LISTS
 )
 add_custom_target(version_h DEPENDS ${PROJECT_BINARY_DIR}/include/generated/zephyr/version.h)
-zephyr_get(KERNEL_VERSION_CUSTOMIZATION SYSBUILD LOCAL)
-set_property(TARGET version_h PROPERTY KERNEL_VERSION_CUSTOMIZATION ${KERNEL_VERSION_CUSTOMIZATION})
 
 if(EXISTS ${APPLICATION_SOURCE_DIR}/VERSION)
   add_custom_command(
@@ -618,8 +616,6 @@ if(EXISTS ${APPLICATION_SOURCE_DIR}/VERSION)
     app_version_h
     DEPENDS ${PROJECT_BINARY_DIR}/include/generated/zephyr/app_version.h)
   add_dependencies(zephyr_interface app_version_h)
-  zephyr_get(APP_VERSION_CUSTOMIZATION SYSBUILD LOCAL)
-  set_property(TARGET app_version_h PROPERTY APP_VERSION_CUSTOMIZATION ${APP_VERSION_CUSTOMIZATION})
 endif()
 
 # Unfortunately, the order in which CMakeLists.txt code is processed
@@ -2237,12 +2233,3 @@ add_subdirectory_ifdef(
   CONFIG_MAKEFILE_EXPORTS
   cmake/makefile_exports
   )
-
-toolchain_linker_finalize()
-
-yaml_context(EXISTS NAME build_info result)
-if(result)
-  build_info(zephyr version VALUE ${PROJECT_VERSION_STR})
-  build_info(zephyr zephyr-base VALUE ${ZEPHYR_BASE})
-  yaml_save(NAME build_info)
-endif()

Kconfig.zephyr

@@ -17,13 +17,13 @@ osource "${APPLICATION_SOURCE_DIR}/VERSION"
 # Shield defaults should have precedence over board defaults, which should have
 # precedence over SoC defaults, so include them in that order.
 #
-# $ARCH and $KCONFIG_BOARD_DIR will be glob patterns when building documentation.
+# $ARCH and $BOARD_DIR will be glob patterns when building documentation.
 # This loads custom shields defconfigs (from BOARD_ROOT)
 osource "$(KCONFIG_BINARY_DIR)/Kconfig.shield.defconfig"
 # This loads Zephyr base shield defconfigs
 source "boards/shields/*/Kconfig.defconfig"
 
-osource "$(KCONFIG_BOARD_DIR)/Kconfig.defconfig"
+osource "$(BOARD_DIR)/Kconfig.defconfig"
 
 # This loads Zephyr specific SoC root defconfigs
 source "$(KCONFIG_BINARY_DIR)/soc/Kconfig.defconfig"
@@ -536,10 +536,11 @@ config NO_OPTIMIZATIONS
 endchoice
 
 config LTO
-	bool "Link Time Optimization"
+	bool "Link Time Optimization [EXPERIMENTAL]"
 	depends on !(GEN_ISR_TABLES || GEN_IRQ_VECTOR_TABLE) || ISR_TABLES_LOCAL_DECLARATION
 	depends on !NATIVE_LIBRARY
 	depends on !CODE_DATA_RELOCATION
+	select EXPERIMENTAL
 	help
 	  This option enables Link Time Optimization.
 

MAINTAINERS.yml

@@ -314,13 +314,12 @@ Bluetooth HCI:
     - HoZHel
   files:
     - include/zephyr/drivers/bluetooth/
-    - include/zephyr/drivers/bluetooth.h
     - drivers/bluetooth/
     - samples/bluetooth/hci_*/
     - tests/bsim/bluetooth/hci_uart/
     - dts/bindings/bluetooth/
   labels:
-    - "area: Bluetooth HCI"
+    - "area: Bluetooth Host"
     - "area: Bluetooth"
   tests:
     - bluetooth
@@ -360,9 +359,8 @@ Bluetooth Host:
     - alwa-nordic
   collaborators:
     - hermabe
-    - rugeGerritsen
-    - sjanc
     - Thalley
+    - sjanc
     - theob-pro
   files:
     - doc/connectivity/bluetooth/
@@ -464,7 +462,6 @@ Bluetooth Audio:
     - pin-zephyr
     - niym-ot
     - jthm-ot
-    - babrsn
   files:
     - subsys/bluetooth/audio/
     - include/zephyr/bluetooth/audio/
@@ -492,6 +489,7 @@ Bluetooth Classic:
     - lylezhu2012
   collaborators:
     - jhedberg
+    - sjanc
   files:
     - subsys/bluetooth/common/
     - subsys/bluetooth/host/classic/
@@ -509,7 +507,6 @@ Bluetooth ISO:
   collaborators:
     - jhedberg
     - kruithofa
-    - rugeGerritsen
   files:
     - include/zephyr/bluetooth/iso.h
     - doc/connectivity/bluetooth/api/shell/iso.rst
@@ -572,9 +569,6 @@ Build system:
     - misc/generated/
     - snippets/
     - modules/Kconfig.sysbuild
-    - scripts/list_boards.py
-    - scripts/list_hardware.py
-    - scripts/schemas/*-schema.yml
   labels:
     - "area: Build System"
   tests:
@@ -885,7 +879,6 @@ Devicetree:
     - galak
   files-regex:
     - dts/bindings/.*zephyr.*
-    - dts/bindings/[^,]+$
   files:
     - scripts/dts/
     - dts/common/
@@ -920,7 +913,6 @@ Disk:
     - subsys/sd/
     - tests/subsys/sd/
     - tests/drivers/disk/
-    - tests/drivers/build_all/disk/
     - include/zephyr/sd/
     - dts/bindings/sd/
     - dts/bindings/mmc/
@@ -1021,6 +1013,8 @@ Release Notes:
   status: maintained
   maintainers:
     - anangl
+  collaborators:
+    - decsny
   files:
     - drivers/adc/
     - include/zephyr/drivers/adc.h
@@ -1055,7 +1049,6 @@ Release Notes:
     - yperess
   files:
     - tests/drivers/bbram/
-    - tests/drivers/build_all/bbram/
     - drivers/bbram/
     - include/zephyr/drivers/bbram.h
     - doc/hardware/peripherals/bbram.rst
@@ -1157,23 +1150,6 @@ Release Notes:
   tests:
     - drivers.clock
 
-"Drivers: Comparator":
-  status: maintained
-  maintainers:
-    - bjarki-andreasen
-  files:
-    - drivers/comparator/
-    - dts/bindings/comparator/
-    - include/zephyr/drivers/comparator.h
-    - include/zephyr/drivers/comparator/
-    - tests/drivers/build_all/comparator/
-    - tests/drivers/comparator/
-    - doc/hardware/peripherals/comparator.rst
-  labels:
-    - "area: Comparator"
-  tests:
-    - drivers.comparator
-
 "Drivers: Console":
   status: odd fixes
   files:
@@ -1228,7 +1204,6 @@ Release Notes:
     - samples/drivers/crypto/
     - tests/crypto/
     - doc/services/crypto/
-    - tests/drivers/build_all/crypto/
   labels:
     - "area: Crypto / RNG"
   tests:
@@ -1387,8 +1362,6 @@ Release Notes:
     - dts/bindings/ethernet/
     - tests/drivers/ethernet/
     - include/zephyr/drivers/ethernet/
-    - include/zephyr/net/phy.h
-    - include/zephyr/net/ethernet.h
   labels:
     - "area: Ethernet"
   tests:
@@ -1398,8 +1371,6 @@ Release Notes:
   status: maintained
   maintainers:
     - de-nordic
-  collaborators:
-    - rghaddab
   files:
     - drivers/flash/
     - dts/bindings/flash_controller/
@@ -1411,7 +1382,6 @@ Release Notes:
     - doc/hardware/peripherals/flash.rst
     - include/zephyr/drivers/flash/
     - tests/drivers/flash_simulator/
-    - tests/drivers/build_all/flash/
   labels:
     - "area: Flash"
   tests:
@@ -1587,7 +1557,9 @@ Release Notes:
     - drivers.i3c
 
 "Drivers: IEEE 802.15.4":
-  status: odd fixes
+  status: maintained
+  maintainers:
+    - fgrandel
   collaborators:
     - rlubos
     - ankuns
@@ -1640,7 +1612,6 @@ Release Notes:
     - doc/hardware/peripherals/mdio.rst
     - drivers/mdio/
     - include/zephyr/drivers/mdio.h
-    - include/zephyr/net/mdio.h
     - tests/drivers/build_all/mdio/
     - dts/bindings/mdio/
   labels:
@@ -2134,7 +2105,6 @@ Release Notes:
     - include/zephyr/drivers/w1.h
     - include/zephyr/drivers/sensor/w1_sensor.h
     - tests/drivers/w1/
-    - tests/drivers/build_all/w1/
     - samples/drivers/w1/
   labels:
     - "area: W1"
@@ -2301,6 +2271,18 @@ Filesystems:
   tests:
     - filesystem
 
+"Filesystems: FatFs reentrant support":
+  status: maintained
+  maintainers:
+    - ox11
+  files:
+    - modules/fatfs/zfs_ffsystem.c
+    - tests/subsys/fs/fat_fs_api/src/test_fat_file_reentrant.c
+  labels:
+    - "area: File System"
+  tests:
+    - filesystem.fat
+
 Formatted Output:
   status: maintained
   maintainers:
@@ -2376,8 +2358,6 @@ Input:
 IPC:
   status: maintained
   maintainers:
-    - doki-nordic
-  collaborators:
     - carlocaione
     - arnopo
   files:
@@ -2732,7 +2712,6 @@ hawkBit:
     - maass-hamburg
   files:
     - subsys/mgmt/hawkbit/
-    - include/zephyr/mgmt/hawkbit/
     - include/zephyr/mgmt/hawkbit.h
     - samples/subsys/mgmt/hawkbit/
   labels:
@@ -2922,6 +2901,8 @@ Networking:
   status: maintained
   maintainers:
     - jukkar
+  collaborators:
+    - fgrandel
   files:
     - doc/connectivity/networking/api/gptp.rst
     - include/zephyr/net/gptp.h
@@ -2993,7 +2974,9 @@ Networking:
     - sample.net.ptp
 
 "Networking: Native IEEE 802.15.4":
-  status: odd fixes
+  status: maintained
+  maintainers:
+    - fgrandel
   collaborators:
     - rlubos
     - jukkar
@@ -3098,18 +3081,6 @@ Open AMP:
   tests:
     - sample.ipc.openamp
 
-PHYTEC Platforms:
-  status: maintained
-  maintainers:
-    - dnltz
-  collaborators:
-    - jonas-rem
-    - pefech
-  files:
-    - boards/phytec/
-  labels:
-    - "platform: PHYTEC"
-
 POSIX API layer:
   status: maintained
   maintainers:
@@ -3133,7 +3104,6 @@ Power management:
   status: maintained
   maintainers:
     - ceolin
-    - bjarki-andreasen
   collaborators:
     - nashif
     - teburd
@@ -3495,9 +3465,9 @@ Nuvoton NPCM Platforms:
 Raspberry Pi Pico Platforms:
   status: maintained
   maintainers:
-    - soburi
-  collaborators:
     - yonsch
+  collaborators:
+    - soburi
   files:
     - boards/raspberrypi/
     - boards/adafruit/kb2040/
@@ -3523,9 +3493,7 @@ Silabs Platforms:
     - boards/silabs/
     - dts/arm/silabs/
     - dts/bindings/*/silabs*
-    - drivers/*/*gecko*
-    - drivers/bluetooth/hci/hci_silabs_*
-    - drivers/*/*silabs*
+    - drivers/*/*_gecko*
   labels:
     - "platform: Silabs"
 
@@ -3550,19 +3518,6 @@ Silabs SiM3U Platforms:
   description: >-
     SiM3U SoCs, dts files, and related drivers. Boards based on SiM3U SoCs.
 
-Gardena Platforms:
-  status: maintained
-  maintainers:
-    - rettichschnidi
-  collaborators:
-    - M1cha
-  files:
-    - boards/gardena/
-  labels:
-    - "platform: Gardena"
-  description: >-
-    Gardena board(s).
-
 Intel Platforms (X86):
   status: maintained
   maintainers:
@@ -4047,6 +4002,8 @@ TI K3 Platforms:
     - gramsay0
     - dnltz
   files:
+    - boards/phytec/phyboard_lyra/
+    - boards/phytec/phyboard_electra/
     - boards/ti/*am62*/
     - drivers/*/*ti_k3*
     - dts/bindings/*/ti,k3*
@@ -4067,12 +4024,8 @@ Xilinx Platforms:
   collaborators:
     - henrikbrixandersen
     - ibirnbaum
-    - michalsimek
   files:
-    - boards/amd/
-    - drivers/*/*xilinx*
     - drivers/*/*xlnx*
-    - drivers/*/*zynq*
     - dts/*/xilinx/
     - dts/bindings/*/*xlnx*
     - include/zephyr/*/*/*xlnx*
@@ -4151,20 +4104,6 @@ RTIO:
   tests:
     - rtio
 
-Secure storage:
-  status: maintained
-  maintainers:
-    - tomi-font
-  files:
-    - subsys/secure_storage/
-    - samples/psa/
-    - doc/services/secure_storage.rst
-    - tests/subsys/secure_storage/
-  labels:
-    - "area: Secure storage"
-  tests:
-    - psa.secure_storage
-
 Storage:
   status: odd fixes
   files:
@@ -4177,17 +4116,6 @@ Storage:
   tests:
     - storage
 
-Storage ZMS:
-  status: maintained
-  maintainers:
-    - rghaddab
-  files:
-    - subsys/fs/zms/
-    - include/zephyr/fs/zms.h
-    - samples/subsys/fs/zms/
-    - tests/subsys/fs/zms/
-    - doc/services/storage/zms/zms.rst
-
 Sysbuild:
   status: maintained
   maintainers:
@@ -4431,6 +4359,15 @@ West:
   labels:
     - "area: West"
 
+"West project: reqmgmt":
+  status: maintained
+  maintainers:
+    - nashif
+    - simhein
+  files: []
+  labels:
+    - "area: Requirements"
+
 "West project: acpica":
   status: maintained
   maintainers:
@@ -4804,8 +4741,6 @@ West:
 "West project: hal_rpi_pico":
   status: maintained
   maintainers:
-    - soburi
-  collaborators:
     - yonsch
   files:
     - modules/hal_rpi_pico/
@@ -4824,7 +4759,7 @@ West:
     - mnkp
     - rettichschnidi
   files:
-    - modules/hal_silabs/
+    - modules/Kconfig.silabs
   labels:
     - "platform: Silabs"
 
@@ -4898,14 +4833,6 @@ West:
   labels:
     - "platform: Intel"
 
-"West project: zephyr-lang-rust":
-  status: maintained
-  maintainers:
-    - d3zd3z
-  files: []
-  labels:
-    - "area: Rust"
-
 "West project: libmetal":
   status: odd fixes
   collaborators:
@@ -4987,7 +4914,6 @@ West:
   tests:
     - benchmark.crypto.mbedtls
     - crypto.mbedtls
-    - psa.secure_storage
 
 "West project: mcuboot":
   status: maintained
@@ -5160,7 +5086,6 @@ West:
     - "area: TF-M"
   tests:
     - trusted-firmware-m
-    - psa.secure_storage
 
 "West project: tf-m-tests":
   status: maintained
@@ -5233,8 +5158,6 @@ West:
     - modules/hostap/
   labels:
     - "area: Wi-Fi"
-  tests:
-    - net.wifi
 
 Xtensa arch:
   status: maintained
@@ -5251,6 +5174,7 @@ Xtensa arch:
     - boards/qemu/xtensa/
     - boards/cdns/xt-sim/
     - soc/cdns/dc233c/
+    - soc/cdns/dc233c/
     - soc/cdns/xtensa_sample_controller/
     - tests/arch/xtensa/
   labels:
@@ -5361,8 +5285,6 @@ Testing with Renode:
     - fkokosinski
   files:
     - cmake/emu/renode.cmake
-    - soc/renode/
-    - boards/renode/
     - boards/**/*/support/*.repl
     - boards/**/*/support/*.resc
   labels:

SDK_VERSION

@@ -1 +1 @@
-0.17.0
+0.16.8

VERSION

@@ -1,5 +1,5 @@
-VERSION_MAJOR = 4
-VERSION_MINOR = 0
-PATCHLEVEL = 0
+VERSION_MAJOR = 3
+VERSION_MINOR = 7
+PATCHLEVEL = 99
 VERSION_TWEAK = 0
 EXTRAVERSION =

arch/arc/Kconfig

@@ -343,15 +343,6 @@ config ARC_NORMAL_FIRMWARE
 	  resources of the ARC processors, and, therefore, it shall avoid
 	  accessing them.
 
-config ARC_VPX_COOPERATIVE_SHARING
-	bool "Cooperative sharing of ARC VPX vector registers"
-	select SCHED_CPU_MASK if MP_MAX_NUM_CPUS > 1
-	help
-	  This option enables the cooperative sharing of the ARC VPX vector
-	  registers. Threads that want to use those registers must successfully
-	  call arc_vpx_lock() before using them, and call arc_vpx_unlock()
-	  when done using them.
-
 source "arch/arc/core/dsp/Kconfig"
 
 menu "ARC MPU Options"
@@ -383,7 +374,9 @@ config ARC_EXCEPTION_STACK_SIZE
 endmenu
 
 config ARC_EARLY_SOC_INIT
-	bool "Make early stage SoC-specific initialization"
+	bool "Make early stage SoC-specific initialization [DEPRECATED]"
+	select SOC_RESET_HOOK
+	select DEPRECATED
 	help
 	  Call SoC per-core setup code on early stage initialization
 	  (before C runtime initialization). Setup code is called in form of

arch/arc/core/reset.S

@@ -16,8 +16,9 @@
 #include <zephyr/arch/cpu.h>
 #include <swap_macros.h>
 #include <zephyr/arch/arc/asm-compat/assembler.h>
-#ifdef CONFIG_ARC_EARLY_SOC_INIT
-  #include <soc_ctrl.h>
+
+#if defined(CONFIG_SOC_RESET_HOOK)
+GTEXT(soc_reset_hook)
 #endif
 
 GDATA(z_interrupt_stacks)
@@ -112,8 +113,8 @@ done_icache_invalidate:
 
 done_dcache_invalidate:
 
-#ifdef CONFIG_ARC_EARLY_SOC_INIT
-	soc_early_asm_init_percpu
+#ifdef CONFIG_SOC_RESET_HOOK
+	bl soc_reset_hook
 #endif
 
 	_dsp_extension_probe

arch/arc/core/thread.c

@@ -19,15 +19,10 @@
 #include <zephyr/arch/arc/v2/mpu/arc_core_mpu.h>
 #endif
 
-#if defined(CONFIG_ARC_VPX_COOPERATIVE_SHARING) || defined(CONFIG_DSP_SHARING)
+#if defined(CONFIG_ARC_DSP) && defined(CONFIG_DSP_SHARING)
 #include <zephyr/arch/arc/v2/dsp/arc_dsp.h>
 static struct k_spinlock lock;
 #endif
-
-#if defined(CONFIG_ARC_VPX_COOPERATIVE_SHARING)
-static struct k_sem vpx_sem[CONFIG_MP_MAX_NUM_CPUS];
-#endif
-
 /*  initial stack frame */
 struct init_stack_frame {
 	uintptr_t pc;
@@ -325,65 +320,3 @@ void arc_dsp_enable(struct k_thread *thread, unsigned int options)
 	k_spin_unlock(&lock, key);
 }
 #endif /* CONFIG_ARC_DSP && CONFIG_DSP_SHARING */
-
-#if defined(CONFIG_ARC_VPX_COOPERATIVE_SHARING)
-int arc_vpx_lock(k_timeout_t timeout)
-{
-	k_spinlock_key_t key;
-	unsigned int id;
-
-	key = k_spin_lock(&lock);
-
-	id = _current_cpu->id;
-#if (CONFIG_MP_MAX_NUM_CPUS > 1) && defined(CONFIG_SCHED_CPU_MASK)
-	__ASSERT(!arch_is_in_isr() && (_current->base.cpu_mask == BIT(id)), "");
-#endif
-	k_spin_unlock(&lock, key);
-
-	/*
-	 * It is assumed that the thread is (still) pinned to
-	 * the same CPU identified by <id>.
-	 */
-
-	return k_sem_take(&vpx_sem[id], timeout);
-}
-
-void arc_vpx_unlock(void)
-{
-	k_spinlock_key_t key;
-	unsigned int id;
-
-	key = k_spin_lock(&lock);
-#if (CONFIG_MP_MAX_NUM_CPUS > 1) && defined(CONFIG_SCHED_CPU_MASK)
-	__ASSERT(!arch_is_in_isr() && (_current->base.cpu_mask == BIT(id)), "");
-#endif
-	id = _current_cpu->id;
-	k_spin_unlock(&lock, key);
-
-	/*
-	 * It is assumed that this thread is (still) pinned to
-	 * the CPU identified by <id>, and that it is the same CPU
-	 * used by arc_vpx_lock().
-	 */
-
-	k_sem_give(&vpx_sem[id]);
-}
-
-void arc_vpx_unlock_force(unsigned int id)
-{
-	__ASSERT(id < CONFIG_MP_MAX_NUM_CPUS, "");
-
-	k_sem_give(&vpx_sem[id]);
-}
-
-static int arc_vpx_sem_init(void)
-{
-	for (unsigned int i = 0; i < CONFIG_MP_MAX_NUM_CPUS; i++) {
-		k_sem_init(vpx_sem, 1, 1);
-	}
-
-	return 0;
-}
-
-SYS_INIT(arc_vpx_sem_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS);
-#endif

arch/arm/core/cortex_a_r/Kconfig

@@ -93,14 +93,6 @@ config CPU_CORTEX_R7
 	help
 	  This option signifies the use of a Cortex-R7 CPU
 
-config CPU_CORTEX_R8
-	bool
-	select CPU_AARCH32_CORTEX_R
-	select ARMV7_R
-	select ARMV7_R_FP if CPU_HAS_FPU
-	help
-	  This option signifies the use of a Cortex-R8 CPU
-
 config CPU_CORTEX_R52
 	bool
 	select CPU_AARCH32_CORTEX_R

arch/arm/core/cortex_a_r/__aeabi_read_tp.S

@@ -14,5 +14,5 @@ SECTION_FUNC(text, __aeabi_read_tp)
 	/*
 	 * TPIDRURW will be used as a base pointer point to TLS aera.
 	 */
-	mrc p15, 0, r0, c13, c0, 2
+	mrc 15, 0, r0, c13, c0, 2
 	bx lr

arch/arm/core/cortex_a_r/prep_c.c

@@ -1,6 +1,5 @@
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,6 +28,24 @@
 #include <cortex_a_r/stack.h>
 #endif
 
+#if defined(__GNUC__)
+/*
+ * GCC can detect if memcpy is passed a NULL argument, however one of
+ * the cases of relocate_vector_table() it is valid to pass NULL, so we
+ * suppress the warning for this case.  We need to do this before
+ * string.h is included to get the declaration of memcpy.
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wnonnull"
+#endif
+
+#include <string.h>
+
+#if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
+Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used))
+void *_vector_table_pointer;
+#endif
+
 #ifdef CONFIG_ARM_MPU
 extern void z_arm_mpu_init(void);
 extern void z_arm_configure_static_mpu_regions(void);
@@ -36,6 +53,38 @@ extern void z_arm_configure_static_mpu_regions(void);
 extern int z_arm_mmu_init(void);
 #endif
 
+#if defined(CONFIG_AARCH32_ARMV8_R)
+
+#define VECTOR_ADDRESS ((uintptr_t)_vector_start)
+
+static inline void relocate_vector_table(void)
+{
+	write_sctlr(read_sctlr() & ~HIVECS);
+	write_vbar(VECTOR_ADDRESS & VBAR_MASK);
+	barrier_isync_fence_full();
+}
+
+#else
+#define VECTOR_ADDRESS 0
+
+void __weak relocate_vector_table(void)
+{
+#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \
+	!defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
+	write_sctlr(read_sctlr() & ~HIVECS);
+	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
+	(void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size);
+#elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
+	_vector_table_pointer = _vector_start;
+#endif
+}
+
+#if defined(__GNUC__)
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* CONFIG_AARCH32_ARMV8_R */
+
 #if defined(CONFIG_CPU_HAS_FPU)
 
 static inline void z_arm_floating_point_init(void)
@@ -62,6 +111,7 @@ static inline void z_arm_floating_point_init(void)
 	__set_CPACR(reg_val);
 	barrier_isync_fence_full();
 
+#if !defined(CONFIG_FPU_SHARING)
 	/*
 	 * FPEXC: Floating-Point Exception Control register
 	 * comp. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition,
@@ -83,6 +133,7 @@ static inline void z_arm_floating_point_init(void)
 	 */
 	__set_FPEXC(FPEXC_EN);
 #endif
+#endif
 }
 
 #endif /* CONFIG_CPU_HAS_FPU */
@@ -104,6 +155,7 @@ void z_prep_c(void)
 	/* Initialize tpidruro with our struct _cpu instance address */
 	write_tpidruro((uintptr_t)&_kernel.cpus[0]);
 
+	relocate_vector_table();
 #if defined(CONFIG_CPU_HAS_FPU)
 	z_arm_floating_point_init();
 #endif

arch/arm/core/cortex_a_r/reboot.c

@@ -1,6 +1,5 @@
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,56 +12,6 @@
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/sys/util.h>
-#include <zephyr/linker/linker-defs.h>
-
-#if defined(CONFIG_AARCH32_ARMV8_R)
-
-#define VECTOR_ADDRESS ((uintptr_t)_vector_start)
-
-static inline void relocate_vector_table(void)
-{
-	write_sctlr(read_sctlr() & ~HIVECS);
-	write_vbar(VECTOR_ADDRESS & VBAR_MASK);
-	barrier_isync_fence_full();
-}
-
-#else
-
-#if defined(__GNUC__)
-/*
- * GCC can detect if memcpy is passed a NULL argument, however one of
- * the cases of relocate_vector_table() it is valid to pass NULL, so we
- * suppress the warning for this case.  We need to do this before
- * string.h is included to get the declaration of memcpy.
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wnonnull"
-#endif /* __GNUC__ */
-
-#include <string.h>
-
-#define VECTOR_ADDRESS 0
-
-void __weak relocate_vector_table(void)
-{
-#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) ||                                     \
-	!defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
-	write_sctlr(read_sctlr() & ~HIVECS);
-	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
-	(void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size);
-#endif
-}
-
-#if defined(__GNUC__)
-#pragma GCC diagnostic pop
-#endif
-
-#endif /* !CONFIG_AARCH32_ARMV8_R */
-
-void z_arm_relocate_vector_table(void)
-{
-	relocate_vector_table();
-}
 
 /**
  *

arch/arm/core/cortex_a_r/reset.S

@@ -1,7 +1,6 @@
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.
  * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -320,6 +319,4 @@ _primary_core:
     bl z_arm_tcm_disable_ecc
 #endif
 
-    bl z_arm_relocate_vector_table
-
     bx r4

arch/arm/core/cortex_a_r/smp.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, 2024 Arm Limited (or its affiliates).
+ * Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -139,14 +139,10 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_
 	arm_cpu_boot_params.arg = arg;
 	arm_cpu_boot_params.cpu_num = cpu_num;
 
-	/* we need the barrier here to make sure the above changes to
-	 * arm_cpu_boot_params are completed before we set the mpid
-	 */
-	barrier_dsync_fence_full();
-
 	/* store mpid last as this is our synchronization point */
 	arm_cpu_boot_params.mpid = cpu_mpid;
 
+	barrier_dsync_fence_full();
 	sys_cache_data_invd_range(
 			(void *)&arm_cpu_boot_params,
 			sizeof(arm_cpu_boot_params));

arch/arm/core/cortex_a_r/swap_helper.S

@@ -126,7 +126,7 @@ out_fp_inactive:
      * TPIDRURW is used as a base pointer to all
      * thread variables with offsets added by toolchain.
      */
-    mcr p15, 0, r0, c13, c0, 2
+    mcr 15, 0, r0, c13, c0, 2
 #endif
 
 #if defined(CONFIG_ARM_STORE_EXC_RETURN)
@@ -336,14 +336,12 @@ _context_switch:
 
 _oops:
     /*
-     * Pass the exception frame to z_do_kernel_oops.
+     * Pass the exception frame to z_do_kernel_oops.  r0 contains the
+     * exception reason.
      */
     cps #MODE_SYS
     mov r0, sp
     cps #MODE_SVC
-    /* Zero callee_regs and exc_return (only used on Cortex-M) */
-    mov r1, #0
-    mov r2, #0
     bl z_do_kernel_oops
     b z_arm_int_exit
 

arch/arm/core/cortex_a_r/switch.S

@@ -150,12 +150,10 @@ offload:
 
 _oops:
     /*
-     * Pass the exception frame to z_do_kernel_oops.
+     * Pass the exception frame to z_do_kernel_oops.  r0 contains the
+     * exception reason.
      */
     mov r0, sp
-    /* Zero callee_regs and exc_return (only used on Cortex-M) */
-    mov r1, #0
-    mov r2, #0
     bl z_do_kernel_oops
 
 inv:

arch/arm/core/cortex_m/fault.c

@@ -40,6 +40,54 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 #define EACD(edr)  (((edr) & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT)
 #endif
 
+/* Exception Return (EXC_RETURN) is provided in LR upon exception entry.
+ * It is used to perform an exception return and to detect possible state
+ * transition upon exception.
+ */
+
+/* Prefix. Indicates that this is an EXC_RETURN value.
+ * This field reads as 0b11111111.
+ */
+#define EXC_RETURN_INDICATOR_PREFIX     (0xFF << 24)
+/* bit[0]: Exception Secure. The security domain the exception was taken to. */
+#define EXC_RETURN_EXCEPTION_SECURE_Pos 0
+#define EXC_RETURN_EXCEPTION_SECURE_Msk \
+		BIT(EXC_RETURN_EXCEPTION_SECURE_Pos)
+#define EXC_RETURN_EXCEPTION_SECURE_Non_Secure 0
+#define EXC_RETURN_EXCEPTION_SECURE_Secure EXC_RETURN_EXCEPTION_SECURE_Msk
+/* bit[2]: Stack Pointer selection. */
+#define EXC_RETURN_SPSEL_Pos 2
+#define EXC_RETURN_SPSEL_Msk BIT(EXC_RETURN_SPSEL_Pos)
+#define EXC_RETURN_SPSEL_MAIN 0
+#define EXC_RETURN_SPSEL_PROCESS EXC_RETURN_SPSEL_Msk
+/* bit[3]: Mode. Indicates the Mode that was stacked from. */
+#define EXC_RETURN_MODE_Pos 3
+#define EXC_RETURN_MODE_Msk BIT(EXC_RETURN_MODE_Pos)
+#define EXC_RETURN_MODE_HANDLER 0
+#define EXC_RETURN_MODE_THREAD EXC_RETURN_MODE_Msk
+/* bit[4]: Stack frame type. Indicates whether the stack frame is a standard
+ * integer only stack frame or an extended floating-point stack frame.
+ */
+#define EXC_RETURN_STACK_FRAME_TYPE_Pos 4
+#define EXC_RETURN_STACK_FRAME_TYPE_Msk BIT(EXC_RETURN_STACK_FRAME_TYPE_Pos)
+#define EXC_RETURN_STACK_FRAME_TYPE_EXTENDED 0
+#define EXC_RETURN_STACK_FRAME_TYPE_STANDARD EXC_RETURN_STACK_FRAME_TYPE_Msk
+/* bit[5]: Default callee register stacking. Indicates whether the default
+ * stacking rules apply, or whether the callee registers are already on the
+ * stack.
+ */
+#define EXC_RETURN_CALLEE_STACK_Pos 5
+#define EXC_RETURN_CALLEE_STACK_Msk BIT(EXC_RETURN_CALLEE_STACK_Pos)
+#define EXC_RETURN_CALLEE_STACK_SKIPPED 0
+#define EXC_RETURN_CALLEE_STACK_DEFAULT EXC_RETURN_CALLEE_STACK_Msk
+/* bit[6]: Secure or Non-secure stack. Indicates whether a Secure or
+ * Non-secure stack is used to restore stack frame on exception return.
+ */
+#define EXC_RETURN_RETURN_STACK_Pos 6
+#define EXC_RETURN_RETURN_STACK_Msk BIT(EXC_RETURN_RETURN_STACK_Pos)
+#define EXC_RETURN_RETURN_STACK_Non_Secure 0
+#define EXC_RETURN_RETURN_STACK_Secure EXC_RETURN_RETURN_STACK_Msk
+
 /* Integrity signature for an ARMv8-M implementation */
 #if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
 #define INTEGRITY_SIGNATURE_STD 0xFEFA125BUL
@@ -695,7 +743,7 @@ static inline bool z_arm_is_pc_valid(uintptr_t pc)
 		return true;
 	}
 
-#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_itcm))
+#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
 	/* Is it in the ITCM */
 	if ((((uintptr_t)&__itcm_start) <= pc) && (pc < ((uintptr_t)&__itcm_end))) {
 		return true;
@@ -1064,7 +1112,9 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
 	__ASSERT(esf != NULL,
 		"ESF could not be retrieved successfully. Shall never occur.");
 
-	z_arm_set_fault_sp(esf, exc_return);
+#ifdef CONFIG_DEBUG_COREDUMP
+	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
+#endif
 
 	reason = fault_handle(esf, fault, &recoverable);
 	if (recoverable) {

arch/arm/core/cortex_m/pm_s2ram.S

@@ -70,9 +70,7 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend)
 	/*
 	 * Mark entering suspend to RAM.
 	 */
-	mov 	r1, lr
-	bl 	pm_s2ram_mark_set
-	mov	lr, r1
+	bl pm_s2ram_mark_set
 
 	/*
 	 * Call the system_off function passed as parameter. This should never
@@ -88,9 +86,7 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend)
 	/*
 	 * Reset the marking of suspend to RAM, return is ignored.
 	 */
-	mov 	r1, lr
-	bl	pm_s2ram_mark_check_and_clear
-	mov 	lr, r1
+	bl pm_s2ram_mark_check_and_clear
 
 	/* Move system_off back to r0 as return value */
 	mov	r0, r4
@@ -103,13 +99,16 @@ GTEXT(arch_pm_s2ram_resume)
 SECTION_FUNC(TEXT, arch_pm_s2ram_resume)
 	/*
 	 * Check if reset occurred after suspending to RAM.
+	 * Store LR to ensure we can continue boot when we are not suspended
+	 * to RAM. In addition to LR, R0 is pushed too, to ensure "SP mod 8 = 0",
+	 * as stated by ARM rule 6.2.1.2 for AAPCS32.
 	 */
-	mov 	r1, lr
-	bl 	pm_s2ram_mark_check_and_clear
-	mov 	lr, r1
-	cmp     r0, #0x1
-	beq     resume
-	bx      lr
+	push    {r0, lr}
+	bl      pm_s2ram_mark_check_and_clear
+	cmp	r0, #0x1
+	pop     {r0, lr}
+	beq	resume
+	bx	lr
 
 resume:
 	/*

arch/arm/core/cortex_m/pm_s2ram.c

@@ -22,44 +22,20 @@ __noinit _cpu_context_t _cpu_context;
  */
 static __noinit uint32_t marker;
 
-void __attribute__((naked)) pm_s2ram_mark_set(void)
+void pm_s2ram_mark_set(void)
 {
-	__asm__ volatile(
-		/* Set the marker to MAGIC value */
-		"str	%[_magic_val], [%[_marker]]\n"
-
-		"bx	lr\n"
-		:
-		: [_magic_val] "r"(MAGIC), [_marker] "r"(&marker)
-		: "r1", "r4", "memory");
+	marker = MAGIC;
 }
 
-bool __attribute__((naked)) pm_s2ram_mark_check_and_clear(void)
+bool pm_s2ram_mark_check_and_clear(void)
 {
-	__asm__ volatile(
-		/* Set return value to 0 */
-		"mov	r0, #0\n"
+	if (marker == MAGIC) {
+		marker = 0;
 
-		/* Check the marker */
-		"ldr	r3, [%[_marker]]\n"
-		"cmp	r3, %[_magic_val]\n"
-		"bne	exit\n"
+		return true;
+	}
 
-		/*
-		 * Reset the marker
-		 */
-		"str	r0, [%[_marker]]\n"
-
-		/*
-		 * Set return value to 1
-		 */
-		"mov	r0, #1\n"
-
-		"exit:\n"
-		"bx lr\n"
-		:
-		: [_magic_val] "r"(MAGIC), [_marker] "r"(&marker)
-		: "r0", "r1", "r3", "r4", "memory");
+	return false;
 }
 
 #endif /* CONFIG_PM_S2RAM_CUSTOM_MARKING */

arch/arm/core/cortex_m/swap.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 Linaro, Limited
+ * Copyright (c) 2023 Arm Limited
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -47,3 +48,63 @@ int arch_swap(unsigned int key)
 	 */
 	return _current->arch.swap_return_value;
 }
+
+uintptr_t z_arm_pendsv_c(uintptr_t exc_ret)
+{
+	/* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
+	IF_ENABLED(CONFIG_ARM_STORE_EXC_RETURN,
+		   (_kernel.cpus[0].current->arch.mode_exc_return = (uint8_t)exc_ret;));
+
+	/* Protect the kernel state while we play with the thread lists */
+	uint32_t basepri = arch_irq_lock();
+
+	/* fetch the thread to run from the ready queue cache */
+	struct k_thread *current = _kernel.cpus[0].current = _kernel.ready_q.cache;
+
+	/*
+	 * Clear PendSV so that if another interrupt comes in and
+	 * decides, with the new kernel state based on the new thread
+	 * being context-switched in, that it needs to reschedule, it
+	 * will take, but that previously pended PendSVs do not take,
+	 * since they were based on the previous kernel state and this
+	 * has been handled.
+	 */
+	SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk;
+
+	/* For Cortex-M, store TLS pointer in a global variable,
+	 * as it lacks the process ID or thread ID register
+	 * to be used by toolchain to access thread data.
+	 */
+	IF_ENABLED(CONFIG_THREAD_LOCAL_STORAGE,
+		   (extern uintptr_t z_arm_tls_ptr; z_arm_tls_ptr = current->tls));
+
+	IF_ENABLED(CONFIG_ARM_STORE_EXC_RETURN,
+		   (exc_ret = (exc_ret & 0xFFFFFF00) | current->arch.mode_exc_return));
+
+	/* Restore previous interrupt disable state (irq_lock key)
+	 * (We clear the arch.basepri field after restoring state)
+	 */
+	basepri = current->arch.basepri;
+	current->arch.basepri = 0;
+
+	arch_irq_unlock(basepri);
+
+#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
+	/* Re-program dynamic memory map */
+	z_arm_configure_dynamic_mpu_regions(current);
+#endif
+
+	/* restore mode */
+	IF_ENABLED(CONFIG_USERSPACE, ({
+			CONTROL_Type ctrl = {.w = __get_CONTROL()};
+			/* exit privileged state when returning to thread mode. */
+			ctrl.b.nPRIV = 0;
+			/* __set_CONTROL inserts an ISB which is may not be necessary here
+			 * (stack pointer may not be touched), but it's recommended to avoid
+			 * executing pre-fetched instructions with the previous privilege.
+			 */
+			__set_CONTROL(ctrl.w | current->arch.mode);
+		}));
+
+	return exc_ret;
+}

arch/arm/core/cortex_m/swap_helper.S

@@ -27,6 +27,7 @@ _ASM_FILE_PROLOGUE
 GTEXT(z_arm_svc)
 GTEXT(z_arm_pendsv)
 GTEXT(z_do_kernel_oops)
+GTEXT(z_arm_pendsv_c)
 #if defined(CONFIG_USERSPACE)
 GTEXT(z_arm_do_syscall)
 #endif
@@ -117,125 +118,20 @@ out_fp_endif:
 #error Unknown ARM architecture
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 
-    /* Protect the kernel state while we play with the thread lists */
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-    cpsid i
-#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
-    msr BASEPRI_MAX, r0
-    isb /* Make the effect of disabling interrupts be realized immediately */
-#else
-#error Unknown ARM architecture
-#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
+    mov r4, lr
+    mov r0, lr
+    bl z_arm_pendsv_c
+    mov lr, r4
 
-    /*
-     * Prepare to clear PendSV with interrupts unlocked, but
-     * don't clear it yet. PendSV must not be cleared until
-     * the new thread is context-switched in since all decisions
-     * to pend PendSV have been taken with the current kernel
-     * state and this is what we're handling currently.
-     */
-    ldr r7, =_SCS_ICSR
-    ldr r6, =_SCS_ICSR_UNPENDSV
-
-    /* _kernel is still in r1 */
-
-    /* fetch the thread to run from the ready queue cache */
-    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
-
-    str r2, [r1, #_kernel_offset_to_current]
-
-    /*
-     * Clear PendSV so that if another interrupt comes in and
-     * decides, with the new kernel state based on the new thread
-     * being context-switched in, that it needs to reschedule, it
-     * will take, but that previously pended PendSVs do not take,
-     * since they were based on the previous kernel state and this
-     * has been handled.
-     */
-
-    /* _SCS_ICSR is still in r7 and _SCS_ICSR_UNPENDSV in r6 */
-    str r6, [r7, #0]
-
-#if defined(CONFIG_THREAD_LOCAL_STORAGE)
-    /* Grab the TLS pointer */
-    ldr r4, =_thread_offset_to_tls
-    adds r4, r2, r4
-    ldr r0, [r4]
-
-    /* For Cortex-M, store TLS pointer in a global variable,
-     * as it lacks the process ID or thread ID register
-     * to be used by toolchain to access thread data.
-     */
-    ldr r4, =z_arm_tls_ptr
-    str r0, [r4]
-#endif
+    ldr r1, =_kernel
+    ldr r2, [r1, #_kernel_offset_to_current]
 
 #if defined(CONFIG_ARM_STORE_EXC_RETURN)
     /* Restore EXC_RETURN value. */
-    ldrsb lr, [r2, #_thread_offset_to_mode_exc_return]
-#endif
-
-    /* Restore previous interrupt disable state (irq_lock key)
-     * (We clear the arch.basepri field after restoring state)
-     */
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && (_thread_offset_to_basepri > 124)
-    /* Doing it this way since the offset to thread->arch.basepri can in
-     * some configurations be larger than the maximum of 124 for ldr/str
-     * immediate offsets.
-     */
-    ldr r4, =_thread_offset_to_basepri
-    adds r4, r2, r4
-
-    ldr r0, [r4]
-    movs.n r3, #0
-    str r3, [r4]
-#else
-    ldr r0, [r2, #_thread_offset_to_basepri]
-    movs r3, #0
-    str r3, [r2, #_thread_offset_to_basepri]
+    mov lr, r0
 #endif
 
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-    /* BASEPRI not available, previous interrupt disable state
-     * maps to PRIMASK.
-     *
-     * Only enable interrupts if value is 0, meaning interrupts
-     * were enabled before irq_lock was called.
-     */
-    cmp r0, #0
-    bne _thread_irq_disabled
-    cpsie i
-_thread_irq_disabled:
-
-#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
-    /* Re-program dynamic memory map */
-    push {r2,lr}
-    mov r0, r2
-    bl z_arm_configure_dynamic_mpu_regions
-    pop {r2,r3}
-    mov lr, r3
-#endif
-
-#ifdef CONFIG_USERSPACE
-    /* restore mode */
-    ldr r3, =_thread_offset_to_mode
-    adds r3, r2, r3
-    ldr r0, [r3]
-    mrs r3, CONTROL
-    movs.n r1, #1
-    bics r3, r1
-    orrs r3, r0
-    msr CONTROL, r3
-
-    /* ISB is not strictly necessary here (stack pointer is not being
-     * touched), but it's recommended to avoid executing pre-fetched
-     * instructions with the previous privilege.
-     */
-    isb
-
-#endif
-
     ldr r4, =_thread_offset_to_callee_saved
     adds r0, r2, r4
 
@@ -253,9 +149,6 @@ _thread_irq_disabled:
     subs r0, #36
     ldmia r0!, {r4-r7}
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-    /* restore BASEPRI for the incoming thread */
-    msr BASEPRI, r0
-
 #ifdef CONFIG_FPU_SHARING
     /* Assess whether switched-in thread had been using the FP registers. */
     tst lr, #_EXC_RETURN_FTYPE_Msk
@@ -285,30 +178,6 @@ in_fp_endif:
     isb
 #endif
 
-#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
-    /* Re-program dynamic memory map */
-    push {r2,lr}
-    mov r0, r2 /* _current thread */
-    bl z_arm_configure_dynamic_mpu_regions
-    pop {r2,lr}
-#endif
-
-#ifdef CONFIG_USERSPACE
-    /* restore mode */
-    ldr r0, [r2, #_thread_offset_to_mode]
-    mrs r3, CONTROL
-    bic r3, #1
-    orr r3, r0
-    msr CONTROL, r3
-
-    /* ISB is not strictly necessary here (stack pointer is not being
-     * touched), but it's recommended to avoid executing pre-fetched
-     * instructions with the previous privilege.
-     */
-    isb
-
-#endif
-
     /* load callee-saved + psp from thread */
     add r0, r2, #_thread_offset_to_callee_saved
     ldmia r0, {r4-r11, ip}
@@ -431,7 +300,6 @@ _stack_frame_endif:
     /* exception return is done in z_arm_int_exit() */
     ldr r0, =z_arm_int_exit
     bx r0
-
 #endif
 
 _oops:
@@ -447,7 +315,6 @@ _oops:
     mov  r1, sp /* pointer to _callee_saved_t */
 #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
 #endif /* CONFIG_EXTRA_EXCEPTION_INFO */
-    mov r2, lr /* EXC_RETURN */
     bl z_do_kernel_oops
     /* return from SVC exception is done here */
 #if defined(CONFIG_EXTRA_EXCEPTION_INFO)

arch/arm/core/cortex_m/thread.c

@@ -586,9 +586,9 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
 	"mov   r3, #0\n"
 	"ldr   r4, =z_thread_entry\n"
 	"bx    r4\n"		/* We don’t intend to return, so there is no need to link. */
-	:
-	: "r" (_main), "r" (stack_ptr)
-	: "r0", "r1", "r2", "r3", "r4", "ip", "lr", "memory");
+	: "+r" (_main)
+	: "r" (stack_ptr)
+	: "r0", "r1", "r2", "r3", "r4", "ip", "lr");
 
 	CODE_UNREACHABLE;
 }

arch/arm/core/cortex_m/timing.c

@@ -104,7 +104,7 @@ timing_t arch_timing_counter_get(void)
 uint64_t arch_timing_cycles_get(volatile timing_t *const start,
 				volatile timing_t *const end)
 {
-	return ((uint32_t)*end - (uint32_t)*start);
+	return (*end - *start);
 }
 
 uint64_t arch_timing_freq_get(void)

arch/arm/core/fatal.c

@@ -101,9 +101,8 @@ void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf)
  *
  * @param esf exception frame
  * @param callee_regs Callee-saved registers (R4-R11)
- * @param exc_return EXC_RETURN value present in LR after exception entry.
  */
-void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs, uint32_t exc_return)
+void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs)
 {
 #if !(defined(CONFIG_EXTRA_EXCEPTION_INFO) && defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE))
 	ARG_UNUSED(callee_regs);
@@ -111,8 +110,6 @@ void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs,
 	/* Stacked R0 holds the exception reason. */
 	unsigned int reason = esf->basic.r0;
 
-	z_arm_set_fault_sp(esf, exc_return);
-
 #if defined(CONFIG_USERSPACE)
 	if (z_arm_preempted_thread_in_user_mode(esf)) {
 		/*

arch/arm/core/mpu/arm_mpu.c

@@ -37,13 +37,6 @@ BUILD_ASSERT((DT_FOREACH_STATUS_OKAY_NODE_VARGS(
 	      NODE_HAS_PROP_AND_OR, zephyr_memory_region_mpu) false) == false,
 	      "`zephyr,memory-region-mpu` was deprecated in favor of `zephyr,memory-attr`");
 
-#define NULL_PAGE_DETECT_NODE_FINDER(node_id, prop)                                                \
-	(DT_NODE_HAS_PROP(node_id, prop) && (DT_REG_ADDR(node_id) == 0) &&                         \
-	 (DT_REG_SIZE(node_id) >= CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE)) ||
-
-#define DT_NULL_PAGE_DETECT_NODE_EXIST                                                             \
-	(DT_FOREACH_STATUS_OKAY_NODE_VARGS(NULL_PAGE_DETECT_NODE_FINDER, zephyr_memory_attr) false)
-
 /*
  * Global status variable holding the number of HW MPU region indices, which
  * have been reserved by the MPU driver to program the static (fixed) memory
@@ -477,9 +470,7 @@ int z_arm_mpu_init(void)
 	 */
 #if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_MPU)
 #if (defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)) && \
-	(CONFIG_FLASH_BASE_ADDRESS > CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE) && \
-	(!DT_NULL_PAGE_DETECT_NODE_EXIST)
-
+	(CONFIG_FLASH_BASE_ADDRESS > CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE)
 #pragma message "Null-Pointer exception detection cannot be configured on un-mapped flash areas"
 #else
 	const struct z_arm_mpu_partition unmap_region =	{

arch/arm/include/cortex_a_r/exception.h

@@ -43,15 +43,6 @@ static ALWAYS_INLINE bool arch_is_in_nested_exception(const struct arch_esf *esf
 	return (arch_curr_cpu()->arch.exc_depth > 1U) ? (true) : (false);
 }
 
-/**
- * @brief No current implementation where core dump is not supported
- *
- * @param esf exception frame
- * @param exc_return EXC_RETURN value present in LR after exception entry.
- */
-static ALWAYS_INLINE void z_arm_set_fault_sp(const struct arch_esf *esf, uint32_t exc_return)
-{}
-
 #if defined(CONFIG_USERSPACE)
 /*
  * This function is used by privileged code to determine if the thread

arch/arm/include/cortex_m/exception.h

@@ -39,54 +39,6 @@ extern volatile irq_offload_routine_t offload_routine;
  */
 #define AIRCR_VECT_KEY_PERMIT_WRITE 0x05FAUL
 
-/* Exception Return (EXC_RETURN) is provided in LR upon exception entry.
- * It is used to perform an exception return and to detect possible state
- * transition upon exception.
- */
-
-/* Prefix. Indicates that this is an EXC_RETURN value.
- * This field reads as 0b11111111.
- */
-#define EXC_RETURN_INDICATOR_PREFIX     (0xFF << 24)
-/* bit[0]: Exception Secure. The security domain the exception was taken to. */
-#define EXC_RETURN_EXCEPTION_SECURE_Pos 0
-#define EXC_RETURN_EXCEPTION_SECURE_Msk \
-		BIT(EXC_RETURN_EXCEPTION_SECURE_Pos)
-#define EXC_RETURN_EXCEPTION_SECURE_Non_Secure 0
-#define EXC_RETURN_EXCEPTION_SECURE_Secure EXC_RETURN_EXCEPTION_SECURE_Msk
-/* bit[2]: Stack Pointer selection. */
-#define EXC_RETURN_SPSEL_Pos 2
-#define EXC_RETURN_SPSEL_Msk BIT(EXC_RETURN_SPSEL_Pos)
-#define EXC_RETURN_SPSEL_MAIN 0
-#define EXC_RETURN_SPSEL_PROCESS EXC_RETURN_SPSEL_Msk
-/* bit[3]: Mode. Indicates the Mode that was stacked from. */
-#define EXC_RETURN_MODE_Pos 3
-#define EXC_RETURN_MODE_Msk BIT(EXC_RETURN_MODE_Pos)
-#define EXC_RETURN_MODE_HANDLER 0
-#define EXC_RETURN_MODE_THREAD EXC_RETURN_MODE_Msk
-/* bit[4]: Stack frame type. Indicates whether the stack frame is a standard
- * integer only stack frame or an extended floating-point stack frame.
- */
-#define EXC_RETURN_STACK_FRAME_TYPE_Pos 4
-#define EXC_RETURN_STACK_FRAME_TYPE_Msk BIT(EXC_RETURN_STACK_FRAME_TYPE_Pos)
-#define EXC_RETURN_STACK_FRAME_TYPE_EXTENDED 0
-#define EXC_RETURN_STACK_FRAME_TYPE_STANDARD EXC_RETURN_STACK_FRAME_TYPE_Msk
-/* bit[5]: Default callee register stacking. Indicates whether the default
- * stacking rules apply, or whether the callee registers are already on the
- * stack.
- */
-#define EXC_RETURN_CALLEE_STACK_Pos 5
-#define EXC_RETURN_CALLEE_STACK_Msk BIT(EXC_RETURN_CALLEE_STACK_Pos)
-#define EXC_RETURN_CALLEE_STACK_SKIPPED 0
-#define EXC_RETURN_CALLEE_STACK_DEFAULT EXC_RETURN_CALLEE_STACK_Msk
-/* bit[6]: Secure or Non-secure stack. Indicates whether a Secure or
- * Non-secure stack is used to restore stack frame on exception return.
- */
-#define EXC_RETURN_RETURN_STACK_Pos 6
-#define EXC_RETURN_RETURN_STACK_Msk BIT(EXC_RETURN_RETURN_STACK_Pos)
-#define EXC_RETURN_RETURN_STACK_Non_Secure 0
-#define EXC_RETURN_RETURN_STACK_Secure EXC_RETURN_RETURN_STACK_Msk
-
 /*
  * The current executing vector is found in the IPSR register. All
  * IRQs and system exceptions are considered as interrupt context.
@@ -232,43 +184,6 @@ static ALWAYS_INLINE void z_arm_clear_faults(void)
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 }
 
-/**
- * @brief Set z_arm_coredump_fault_sp to stack pointer value expected by GDB
- *
- * @param esf exception frame
- * @param exc_return EXC_RETURN value present in LR after exception entry.
- */
-static ALWAYS_INLINE void z_arm_set_fault_sp(const struct arch_esf *esf, uint32_t exc_return)
-{
-#ifdef CONFIG_DEBUG_COREDUMP
-	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
-#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-	/* Gdb expects a stack pointer that does not include the exception stack frame in order to
-	 * unwind. So adjust the stack pointer accordingly.
-	 */
-	z_arm_coredump_fault_sp += sizeof(esf->basic);
-
-#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
-	/* Assess whether thread had been using the FP registers and add size of additional
-	 * registers if necessary
-	 */
-	if ((exc_return & EXC_RETURN_STACK_FRAME_TYPE_STANDARD) ==
-			EXC_RETURN_STACK_FRAME_TYPE_EXTENDED) {
-		z_arm_coredump_fault_sp += sizeof(esf->fpu);
-	}
-#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
-
-#if !(defined(CONFIG_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV8_M_BASELINE))
-	if ((esf->basic.xpsr & SCB_CCR_STKALIGN_Msk) == SCB_CCR_STKALIGN_Msk) {
-		/* Adjust stack alignment after PSR bit[9] detected */
-		z_arm_coredump_fault_sp |= 0x4;
-	}
-#endif /* !CONFIG_ARMV8_M_MAINLINE */
-
-#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE || CONFIG_ARMV6_M_ARMV8_M_BASELINE */
-#endif /* CONFIG_DEBUG_COREDUMP */
-}
-
 /**
  * @brief Assess whether a debug monitor event should be treated as an error
  *

arch/common/nocache.ld

@@ -7,6 +7,12 @@
 
 /* Copied from linker.ld */
 
+#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_nocache_ram), okay)
+#define NOCACHE_REGION LINKER_DT_NODE_REGION_NAME_TOKEN(DT_CHOSEN(zephyr_nocache_ram))
+#else
+#define NOCACHE_REGION RAMABLE_REGION
+#endif
+
 /* Non-cached region of RAM */
 SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)
 {
@@ -27,5 +33,5 @@ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)
 	MPU_ALIGN(_nocache_ram_size);
 #endif
 	_nocache_ram_end = .;
-} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+} GROUP_DATA_LINK_IN(NOCACHE_REGION, NOCACHE_REGION)
 _nocache_ram_size = _nocache_ram_end - _nocache_ram_start;

arch/common/ramfunc.ld

@@ -9,7 +9,6 @@
 
 SECTION_DATA_PROLOGUE(.ramfunc,,)
 {
-	__ramfunc_region_start = .;
 	MPU_ALIGN(__ramfunc_size);
 	__ramfunc_start = .;
 	*(.ramfunc)

arch/mips/core/isr.S

@@ -70,7 +70,6 @@ GTEXT(_Fault)
 
 GTEXT(_k_neg_eagain)
 GTEXT(z_thread_mark_switched_in)
-GTEXT(z_thread_mark_switched_out)
 
 /* exports */
 GTEXT(__isr_vec)
@@ -210,9 +209,6 @@ on_thread_stack:
 #endif /* CONFIG_PREEMPT_ENABLED */
 
 reschedule:
-#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
-	jal z_thread_mark_switched_out
-#endif
 	/*
 	 * Check if the current thread is the same as the thread on the ready Q. If
 	 * so, do not reschedule.

arch/riscv/core/CMakeLists.txt

@@ -27,4 +27,3 @@ zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
 zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c)
 zephyr_library_sources_ifdef(CONFIG_ARCH_STACKWALK stacktrace.c)
 zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)
-zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c)

arch/riscv/core/elf.c

@@ -1,373 +0,0 @@
-/** @file
- * @brief Architecture-specific relocations for RISC-V instruction sets.
- */
-/*
- * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <zephyr/llext/elf.h>
-#include <zephyr/llext/llext.h>
-#include <zephyr/logging/log.h>
-#include <zephyr/sys/util.h>
-
-#include <zephyr/arch/riscv/elf.h>
-
-#include <stdlib.h>
-
-LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL);
-
-/*
- * RISC-V relocations commonly use pairs of U-type and I-type instructions.
- * U-type instructions have 20-bit immediates, I-type instructions have 12-bit immediates.
- * Immediates in RISC-V are always sign-extended.
- * Thereby, this type of relocation can reach any address within a 2^31-1 byte range.
- */
-#define RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE INT32_MAX
-
-/* S-type has 12-bit signed immediate */
-#define RISCV_MAX_JUMP_DISTANCE_S_TYPE ((1 << 11) - 1)
-
-/* I-type has 12-bit signed immediate also */
-#define RISCV_MAX_JUMP_DISTANCE_I_TYPE ((1 << 11) - 1)
-
-/* B-type has 13-bit signed immediate */
-#define RISCV_MAX_JUMP_DISTANCE_B_TYPE ((1 << 12) - 1)
-
-/* CB-type has 9-bit signed immediate */
-#define RISCV_MAX_JUMP_DISTANCE_CB_TYPE ((1 << 8) - 1)
-
-/* CJ-type has 12-bit signed immediate (last bit implicit 0) */
-#define RISCV_MAX_JUMP_DISTANCE_CJ_TYPE ((1 << 11) - 1)
-
-static inline int riscv_relocation_fits(long long jump_target, long long max_distance,
-					elf_word reloc_type)
-{
-	if (llabs(jump_target) > max_distance) {
-		LOG_ERR("%lld byte relocation is not possible for type %" PRIu64 " (max %lld)!",
-			jump_target, (uint64_t)reloc_type, max_distance);
-		return -ENOEXEC; /* jump too far */
-	}
-
-	return 0;
-}
-
-static long long last_u_type_jump_target;
-
-/**
- * @brief RISC-V specific function for relocating partially linked ELF binaries
- *
- * This implementation follows the official RISC-V specification:
- * https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
- *
- */
-int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc_unsigned, uintptr_t sym_base_addr_unsigned,
-		      const char *sym_name, uintptr_t load_bias)
-{
-	/* FIXME currently, RISC-V relocations all fit in ELF_32_R_TYPE */
-	elf_word reloc_type = ELF32_R_TYPE(rel->r_info);
-	/*
-	 * The RISC-V specification uses the following symbolic names for the relocations:
-	 *
-	 * A - addend (rel->r_addend)
-	 * B - base address (load_bias)
-	 * G - global offset table (not supported yet)
-	 * P - position of the relocation (loc)
-	 * S - symbol value (sym_base_addr)
-	 * V - value at the relocation position (*loc)
-	 * GP - value of __global_pointer$ (not supported yet)
-	 * TLSMODULE - TLS module for the object (not supported yet)
-	 * TLSOFFSET - TLS static block for the object (not supported yet)
-	 */
-	intptr_t loc = (intptr_t)loc_unsigned;
-	uint8_t *loc8 = (uint8_t *)loc, tmp8;
-	uint16_t *loc16 = (uint16_t *)loc, tmp16;
-	uint32_t *loc32 = (uint32_t *)loc, tmp32;
-	uint64_t *loc64 = (uint64_t *)loc, tmp64;
-	/* uint32_t or uint64_t */
-	r_riscv_wordclass_t *loc_word = (r_riscv_wordclass_t *)loc;
-	uint32_t modified_operand;
-	uint16_t modified_compressed_operand;
-	int32_t imm8;
-	long long original_imm8, jump_target;
-	int16_t compressed_imm8;
-	__typeof__(rel->r_addend) target_alignment = 1;
-	const intptr_t sym_base_addr = (intptr_t)sym_base_addr_unsigned;
-
-	LOG_DBG("Relocating symbol %s at %p with base address %p load address %p type %" PRIu64,
-		sym_name, (void *)loc, (void *)sym_base_addr, (void *)load_bias,
-		(uint64_t)reloc_type);
-
-	/* FIXME not all types of relocations currently supported, especially TLS */
-
-	switch (reloc_type) {
-	case R_RISCV_NONE:
-		break;
-	case R_RISCV_32:
-		jump_target = sym_base_addr + rel->r_addend; /* S + A */
-		UNALIGNED_PUT((uint32_t)jump_target, loc32);
-		return riscv_relocation_fits(jump_target, INT32_MAX, reloc_type);
-	case R_RISCV_64:
-		/* full 64-bit range, need no range check */
-		UNALIGNED_PUT(sym_base_addr + rel->r_addend, loc64); /* S + A */
-		break;
-	case R_RISCV_RELATIVE:
-		/* either full 32-bit or 64-bit range, need no range check */
-		UNALIGNED_PUT(load_bias + rel->r_addend, loc_word); /* B + A */
-		break;
-	case R_RISCV_JUMP_SLOT:
-		/* either full 32-bit or 64-bit range, need no range check */
-		UNALIGNED_PUT(sym_base_addr, loc_word); /* S */
-		break;
-	case R_RISCV_BRANCH:
-		jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */
-		modified_operand = UNALIGNED_GET(loc32);
-		imm8 = jump_target;
-		modified_operand = R_RISCV_CLEAR_BTYPE_IMM8(modified_operand);
-		modified_operand = R_RISCV_SET_BTYPE_IMM8(modified_operand, imm8);
-		UNALIGNED_PUT(modified_operand, loc32);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_B_TYPE,
-					     reloc_type);
-	case R_RISCV_JAL:
-		jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */
-		modified_operand = UNALIGNED_GET(loc32);
-		imm8 = jump_target;
-		modified_operand = R_RISCV_CLEAR_JTYPE_IMM8(modified_operand);
-		modified_operand = R_RISCV_SET_JTYPE_IMM8(modified_operand, imm8);
-		UNALIGNED_PUT(modified_operand, loc32);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE,
-					     reloc_type);
-	case R_RISCV_CALL:
-	case R_RISCV_CALL_PLT:
-	case R_RISCV_PCREL_HI20:
-		modified_operand = UNALIGNED_GET(loc32);
-		jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */
-		imm8 = jump_target;
-		/* bit 12 of the immediate goes to I-type instruction and might
-		 * change the sign of the number
-		 */
-		/* in order to avoid that, we add 1 to the upper immediate if bit 12 is one */
-		/* see RISC-V la pseudo instruction */
-		imm8 += imm8 & 0x800;
-
-		original_imm8 = imm8;
-
-		modified_operand = R_RISCV_CLEAR_UTYPE_IMM8(modified_operand);
-		modified_operand = R_RISCV_SET_UTYPE_IMM8(modified_operand, imm8);
-		UNALIGNED_PUT(modified_operand, loc32);
-
-		if (reloc_type != R_RISCV_PCREL_HI20) {
-			/* PCREL_HI20 is only U-type, not truly U+I-type */
-			/* for the others, need to also modify following I-type */
-			loc32++;
-
-			imm8 = jump_target;
-
-			modified_operand = UNALIGNED_GET(loc32);
-			modified_operand = R_RISCV_CLEAR_ITYPE_IMM8(modified_operand);
-			modified_operand = R_RISCV_SET_ITYPE_IMM8(modified_operand, imm8);
-			UNALIGNED_PUT(modified_operand, loc32);
-		}
-
-		last_u_type_jump_target = jump_target;
-
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE,
-					     reloc_type);
-	case R_RISCV_PCREL_LO12_I:
-		/* need the same jump target as preceding U-type relocation */
-		if (last_u_type_jump_target == 0) {
-			LOG_ERR("R_RISCV_PCREL_LO12_I relocation without preceding U-type "
-				"relocation!");
-			return -ENOEXEC;
-		}
-		modified_operand = UNALIGNED_GET(loc32);
-		jump_target = last_u_type_jump_target; /* S - P */
-		last_u_type_jump_target = 0;
-		imm8 = jump_target;
-		modified_operand = R_RISCV_CLEAR_ITYPE_IMM8(modified_operand);
-		modified_operand = R_RISCV_SET_ITYPE_IMM8(modified_operand, imm8);
-		UNALIGNED_PUT(modified_operand, loc32);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE,
-					     reloc_type);
-		break;
-	case R_RISCV_PCREL_LO12_S:
-		/* need the same jump target as preceding U-type relocation */
-		if (last_u_type_jump_target == 0) {
-			LOG_ERR("R_RISCV_PCREL_LO12_I relocation without preceding U-type "
-				"relocation!");
-			return -ENOEXEC;
-		}
-		modified_operand = UNALIGNED_GET(loc32);
-		jump_target = last_u_type_jump_target; /* S - P */
-		last_u_type_jump_target = 0;
-		imm8 = jump_target;
-		modified_operand = R_RISCV_CLEAR_STYPE_IMM8(modified_operand);
-		modified_operand = R_RISCV_SET_STYPE_IMM8(modified_operand, imm8);
-		UNALIGNED_PUT(modified_operand, loc32);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE,
-					     reloc_type);
-	case R_RISCV_HI20:
-		jump_target = sym_base_addr + rel->r_addend; /* S + A */
-		modified_operand = UNALIGNED_GET(loc32);
-		imm8 = jump_target;
-		/* bit 12 of the immediate goes to I-type instruction and might
-		 * change the sign of the number
-		 */
-		/* in order to avoid that, we add 1 to the upper immediate if bit 12 is one*/
-		/* see RISC-V la pseudo instruction */
-		original_imm8 = imm8;
-		imm8 += imm8 & 0x800;
-		modified_operand = R_RISCV_CLEAR_UTYPE_IMM8(modified_operand);
-		modified_operand = R_RISCV_SET_UTYPE_IMM8(modified_operand, imm8);
-		UNALIGNED_PUT(modified_operand, loc32);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE,
-					     reloc_type);
-	case R_RISCV_LO12_I:
-		modified_operand = UNALIGNED_GET(loc32);
-		jump_target = sym_base_addr + rel->r_addend; /* S + A */
-		imm8 = jump_target;
-		/* this is always used with R_RISCV_HI20 */
-		modified_operand = R_RISCV_CLEAR_ITYPE_IMM8(modified_operand);
-		modified_operand = R_RISCV_SET_ITYPE_IMM8(modified_operand, imm8);
-		UNALIGNED_PUT(modified_operand, loc32);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE,
-					     reloc_type);
-	case R_RISCV_LO12_S:
-		modified_operand = UNALIGNED_GET(loc32);
-		imm8 = sym_base_addr + rel->r_addend; /* S + A */
-		/*
-		 * S-type is used for stores/loads etc.
-		 * size check is done at compile time, as it depends on the size of
-		 * the structure we are trying to load/store
-		 */
-		modified_operand = R_RISCV_CLEAR_STYPE_IMM8(modified_operand);
-		modified_operand = R_RISCV_SET_STYPE_IMM8(modified_operand, imm8);
-		UNALIGNED_PUT(modified_operand, loc32);
-		break;
-	/* for add/sub/set, compiler needs to ensure that the ELF sections are close enough */
-	case R_RISCV_ADD8:
-		tmp8 = UNALIGNED_GET(loc8);
-		tmp8 += sym_base_addr + rel->r_addend; /* V + S + A */
-		UNALIGNED_PUT(tmp8, loc8);
-		break;
-	case R_RISCV_ADD16:
-		tmp16 = UNALIGNED_GET(loc16);
-		tmp16 += sym_base_addr + rel->r_addend; /* V + S + A */
-		UNALIGNED_PUT(tmp16, loc16);
-		break;
-	case R_RISCV_ADD32:
-		tmp32 = UNALIGNED_GET(loc32);
-		tmp32 += sym_base_addr + rel->r_addend; /* V + S + A */
-		UNALIGNED_PUT(tmp32, loc32);
-		break;
-	case R_RISCV_ADD64:
-		tmp64 = UNALIGNED_GET(loc64);
-		tmp64 += sym_base_addr + rel->r_addend; /* V + S + A */
-		UNALIGNED_PUT(tmp64, loc64);
-		break;
-	case R_RISCV_SUB8:
-		tmp8 = UNALIGNED_GET(loc8);
-		tmp8 -= sym_base_addr + rel->r_addend; /* V - S - A */
-		UNALIGNED_PUT(tmp8, loc8);
-		break;
-	case R_RISCV_SUB16:
-		tmp16 = UNALIGNED_GET(loc16);
-		tmp16 -= sym_base_addr + rel->r_addend; /* V - S - A */
-		UNALIGNED_PUT(tmp16, loc16);
-		break;
-	case R_RISCV_SUB32:
-		tmp32 = UNALIGNED_GET(loc32);
-		tmp32 -= sym_base_addr + rel->r_addend; /* V - S - A */
-		UNALIGNED_PUT(tmp32, loc32);
-		break;
-	case R_RISCV_SUB64:
-		tmp64 = UNALIGNED_GET(loc64);
-		tmp64 -= sym_base_addr + rel->r_addend; /* V - S - A */
-		UNALIGNED_PUT(tmp64, loc64);
-		break;
-	case R_RISCV_SUB6:
-		tmp8 = UNALIGNED_GET(loc8) & (0x1F);
-		UNALIGNED_PUT(tmp8, loc8);
-		tmp8 = tmp8 - sym_base_addr - rel->r_addend; /* V - S - A */
-		tmp8 = tmp8 & (0x1F);
-		tmp8 = tmp8 | UNALIGNED_GET(loc8);
-		UNALIGNED_PUT(tmp8, loc8);
-		break;
-	case R_RISCV_SET6:
-		tmp8 = UNALIGNED_GET(loc8) & (0x1F);
-		UNALIGNED_PUT(tmp8, loc8);
-		tmp8 = sym_base_addr + rel->r_addend; /* S + A */
-		tmp8 = tmp8 | UNALIGNED_GET(loc8);
-		UNALIGNED_PUT(tmp8, loc8);
-		break;
-	case R_RISCV_SET8:
-		tmp8 = sym_base_addr + rel->r_addend; /* S + A */
-		UNALIGNED_PUT(tmp8, loc8);
-		break;
-	case R_RISCV_SET16:
-		tmp16 = sym_base_addr + rel->r_addend; /* S + A */
-		UNALIGNED_PUT(tmp16, loc16);
-		break;
-	case R_RISCV_SET32:
-		tmp32 = sym_base_addr + rel->r_addend; /* S + A */
-		UNALIGNED_PUT(tmp32, loc32);
-		break;
-	case R_RISCV_32_PCREL:
-		jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */
-		tmp32 = jump_target;
-		UNALIGNED_PUT(tmp32, loc32);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE,
-					     reloc_type);
-	case R_RISCV_PLT32:
-		jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */
-		tmp32 = jump_target;
-		UNALIGNED_PUT(tmp32, loc32);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE,
-					     reloc_type);
-	case R_RISCV_RVC_BRANCH:
-		jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */
-		modified_compressed_operand = UNALIGNED_GET(loc16);
-		compressed_imm8 = jump_target;
-		modified_compressed_operand =
-			R_RISCV_CLEAR_CBTYPE_IMM8(modified_compressed_operand);
-		modified_compressed_operand =
-			R_RISCV_SET_CBTYPE_IMM8(modified_compressed_operand, compressed_imm8);
-		UNALIGNED_PUT(modified_compressed_operand, loc16);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_CB_TYPE,
-					     reloc_type);
-	case R_RISCV_RVC_JUMP:
-		jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */
-		modified_compressed_operand = UNALIGNED_GET(loc16);
-		compressed_imm8 = jump_target;
-		modified_compressed_operand =
-			R_RISCV_CLEAR_CJTYPE_IMM8(modified_compressed_operand);
-		modified_compressed_operand =
-			R_RISCV_SET_CJTYPE_IMM8(modified_compressed_operand, compressed_imm8);
-		UNALIGNED_PUT(modified_compressed_operand, loc16);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_CJ_TYPE,
-					     reloc_type);
-	case R_RISCV_ALIGN:
-		/* we are supposed to move the symbol such that it is aligned to the next power of
-		 * two >= addend
-		 */
-		/* this involves moving the symbol */
-		while (target_alignment < rel->r_addend) {
-			target_alignment *= 2;
-		}
-		LOG_ERR("Symbol %s with location %p requires alignment to %" PRIu64 " bytes!",
-			sym_name, (void *)loc, (uint64_t)target_alignment);
-		LOG_ERR("Alignment relocation is currently not supported!");
-		return -ENOEXEC;
-	/* ignored, this is primarily intended for removing instructions during link-time
-	 * optimization
-	 */
-	case R_RISCV_RELAX:
-		break;
-	default:
-		LOG_ERR("Unsupported relocation type: %" PRIu64 " for symbol: %s",
-			(uint64_t)reloc_type, sym_name);
-		return -ENOEXEC;
-	}
-
-	return 0;
-}

arch/riscv/core/isr.S

@@ -163,14 +163,6 @@ SECTION_FUNC(exception.entry, _isr_wrapper)
 	lr t0, ___cpu_t_current_OFFSET(s0)
 	lr tp, _thread_offset_to_tls(t0)
 
-	/* Make sure global pointer is sane */
-#ifdef CONFIG_RISCV_GP
-	.option push
-	.option norelax
-	la gp, __global_pointer$
-	.option pop
-#endif /* CONFIG_RISCV_GP */
-
 	/* Clear our per-thread usermode flag */
 	lui t0, %tprel_hi(is_user_mode)
 	add t0, t0, tp, %tprel_add(is_user_mode)
@@ -451,12 +443,6 @@ do_fault:
 1:	mv a1, sp
 
 #ifdef CONFIG_EXCEPTION_DEBUG
-	/*
-	 * Restore the s0 we saved early in ISR entry
-	 * so it shows up properly in the CSF.
-	 */
-	lr s0, __struct_arch_esf_s0_OFFSET(sp)
-
 	/* Allocate space for caller-saved registers on current thread stack */
 	addi sp, sp, -__callee_saved_t_SIZEOF
 

arch/riscv/core/smp.c

@@ -74,11 +74,7 @@ void arch_secondary_cpu_init(int hartid)
 #endif
 #ifdef CONFIG_SMP
 	irq_enable(RISCV_IRQ_MSOFT);
-#endif /* CONFIG_SMP */
-#ifdef CONFIG_PLIC_IRQ_AFFINITY
-	/* Enable on secondary cores so that they can respond to PLIC */
-	irq_enable(RISCV_IRQ_MEXT);
-#endif /* CONFIG_PLIC_IRQ_AFFINITY */
+#endif
 	riscv_cpu_init[cpu_num].fn(riscv_cpu_init[cpu_num].arg);
 }
 

arch/xtensa/CMakeLists.txt

@@ -7,5 +7,5 @@ add_subdirectory(core)
 if (CONFIG_XTENSA_INSECURE_USERSPACE)
   message(WARNING "
   This userspace implementation uses the window ABI this means that the kernel
-  will spill registers on behalf of the userspace. Use it carefully.")
+  will spill registers in behave of the userpsace. Use it carefully.")
 endif()

arch/xtensa/core/CMakeLists.txt

@@ -53,7 +53,7 @@ set(CORE_ISA_DM ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/core-isa-dM.
 set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c)
 file(WRITE ${CORE_ISA_IN} "#include <xtensa/config/core-isa.h>\n")
 add_custom_command(OUTPUT ${CORE_ISA_DM}
-  COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__ ${XTENSA_CORE_LOCAL_C_FLAG}
+  COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__
           -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC}
           -I${SOC_FULL_DIR}
           ${CORE_ISA_IN} -o ${CORE_ISA_DM})

arch/xtensa/core/elf.c

@@ -6,7 +6,6 @@
 
 #include <zephyr/llext/elf.h>
 #include <zephyr/llext/llext.h>
-#include <zephyr/llext/llext_internal.h>
 #include <zephyr/llext/loader.h>
 #include <zephyr/logging/log.h>
 
@@ -19,7 +18,6 @@ LOG_MODULE_DECLARE(llext);
 #define R_XTENSA_JMP_SLOT       4
 #define R_XTENSA_RELATIVE       5
 #define R_XTENSA_PLT            6
-#define R_XTENSA_SLOT0_OP	20
 
 /**
  * @brief Architecture specific function for relocating shared elf
@@ -51,33 +49,6 @@ void arch_elf_relocate_local(struct llext_loader *ldr, struct llext *ext,
 		break;
 	case R_XTENSA_32:
 		*got_entry += sh_addr;
-		break;
-	case R_XTENSA_SLOT0_OP:
-		;
-		uint8_t *opc = (uint8_t *)got_entry;
-
-		/* Check the opcode: is this an L32R? And does it have to be relocated? */
-		if ((opc[0] & 0xf) != 1 || opc[1] || opc[2])
-			break;
-
-		elf_sym_t rsym;
-
-		int ret = llext_seek(ldr, ldr->sects[LLEXT_MEM_SYMTAB].sh_offset +
-				     ELF_R_SYM(rel->r_info) * sizeof(elf_sym_t));
-		if (!ret) {
-			ret = llext_read(ldr, &rsym, sizeof(elf_sym_t));
-		}
-		if (ret)
-			return;
-
-		uintptr_t link_addr = (uintptr_t)llext_loaded_sect_ptr(ldr, ext, rsym.st_shndx) +
-			rsym.st_value + rel->r_addend;
-
-		ssize_t value = (link_addr - (((uintptr_t)got_entry + 3) & ~3)) >> 2;
-
-		opc[1] = value & 0xff;
-		opc[2] = (value >> 8) & 0xff;
-
 		break;
 	default:
 		LOG_DBG("unsupported relocation type %u", type);

arch/xtensa/core/startup/reset_vector.S

@@ -104,7 +104,7 @@ _ResetHandler:
 	/* Read PWRSTAT */
 	movi	a2, XDM_MISC_PWRSTAT
 	/* Save area address - retained for later */
-	movi	a3, xthal_pso_savearea
+	movi	a3, _xtos_pso_savearea
 	/* Signature for compare - retained for later */
 	movi	a5, CORE_STATE_SIGNATURE
 	 /* PWRSTAT value - retained for later */
@@ -229,7 +229,7 @@ _ResetHandler:
 	 * MEMCTL register was already restored earlier, and as a side
 	 * effect, registers a3, a5, a7 are now preloaded with values
 	 * that we will use here.
-	 * a3 - pointer to save area base address (xthal_pso_savearea)
+	 * a3 - pointer to save area base address (_xtos_pso_savearea)
 	 * a5 - saved state signature (CORE_STATE_SIGNATURE)
 	 * a7 - contents of PWRSTAT register
 	 */
@@ -343,11 +343,11 @@ _ResetHandler:
 
 	/* make shutoff routine return zero */
 	movi	a2, 0
-	movi	a3, xthal_pso_savearea
+	movi	a3, _xtos_pso_savearea
 	/* Here, as below for _start, call0 is used as an unlimited-range
 	 * jump.
 	 */
-	call0	xthal_core_restore_nw
+	call0	_xtos_core_restore_nw
 	/*  (does not return) */
 .Lcoldstart:
 #endif

boards/01space/esp32c3_042_oled/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright 2022 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 65535 if WIFI && BT
+	default 51200 if WIFI
+	default 40960 if BT
+	default 4096

boards/01space/esp32c3_042_oled/board.yml

@@ -1,6 +1,5 @@
 board:
   name: esp32c3_042_oled
-  full_name: ESP32C3 0.42 OLED
   vendor: 01space
   socs:
   - name: esp32c3

boards/01space/esp32c3_042_oled/doc/index.rst

@@ -1,4 +1,7 @@
-.. zephyr:board:: esp32c3_042_oled
+.. _01space_esp32c3_042_oled:
+
+ESP32C3 0.42 OLED
+#################
 
 Overview
 ********
@@ -8,6 +11,12 @@ RISC-V WiFi/Bluetooth dual-mode chip.
 
 For more details see the `01space ESP32C3 0.42 OLED`_ Github repo.
 
+.. figure:: img/esp32c3_042_oled.webp
+   :align: center
+   :alt: 01space ESP32C3 0.42 OLED
+
+   01space ESP32C3 0.42 OLED
+
 Hardware
 ********
 

boards/96boards/aerocore2/board.yml

@@ -1,6 +1,5 @@
 board:
   name: 96b_aerocore2
-  full_name: Aerocore2
   vendor: 96boards
   socs:
     - name: stm32f427xx

boards/96boards/argonkey/board.yml

@@ -1,6 +1,5 @@
 board:
   name: 96b_argonkey
-  full_name: Argonkey
   vendor: 96boards
   socs:
     - name: stm32f412cx

boards/96boards/avenger96/96b_avenger96.yaml

@@ -14,6 +14,7 @@ testing:
     - cmsis_rtos_v2
     - net
     - mpu
+    - tinycrypt
     - crypto
     - aes
     - cmm

boards/96boards/avenger96/board.yml

@@ -1,6 +1,5 @@
 board:
   name: 96b_avenger96
-  full_name: Avenger96
   vendor: 96boards
   socs:
     - name: stm32mp157cxx

boards/96boards/carbon/Kconfig.defconfig

@@ -9,6 +9,16 @@ config SPI_STM32_INTERRUPT
 	default y
 	depends on SPI
 
+if BT
+
+config SPI
+	default y
+
+config BT_SPI
+	default y
+
+endif # BT
+
 endif # BOARD_96B_CARBON_STM32F401XE
 
 if BOARD_96B_CARBON_NRF51822

boards/96boards/carbon/board.yml

@@ -1,6 +1,5 @@
 board:
   name: 96b_carbon
-  full_name: Carbon
   vendor: 96boards
   socs:
   - name: stm32f401xe

boards/96boards/meerkat96/board.yml

@@ -1,6 +1,5 @@
 board:
   name: 96b_meerkat96
-  full_name: Meerkat96
   vendor: 96boards
   socs:
     - name: mcimx7d

boards/96boards/neonkey/board.yml

@@ -1,6 +1,5 @@
 board:
   name: 96b_neonkey
-  full_name: Neonkey
   vendor: 96boards
   socs:
     - name: stm32f411xe

boards/96boards/neonkey/doc/index.rst

@@ -216,8 +216,6 @@ GDB instance. To reattach, just follow the same steps above, till
 References
 **********
 
-.. target-notes::
-
 .. _96Boards website:
    https://www.96boards.org/product/neonkey/
 

boards/96boards/nitrogen/board.yml

@@ -1,6 +1,5 @@
 board:
   name: 96b_nitrogen
-  full_name: Nitrogen
   vendor: 96boards
   socs:
   - name: nrf52832

boards/96boards/stm32_sensor_mez/board.yml

@@ -1,6 +1,5 @@
 board:
   name: 96b_stm32_sensor_mez
-  full_name: STM32 Sensor Mezzanine
   vendor: st
   socs:
     - name: stm32f446xx

boards/96boards/wistrio/board.yml

@@ -1,6 +1,5 @@
 board:
   name: 96b_wistrio
-  full_name: WisTrio
   vendor: 96boards
   socs:
     - name: stm32l151xba

boards/96boards/wistrio/doc/96b_wistrio.rst

@@ -189,8 +189,6 @@ GDB instance. To reattach, just follow the same steps above, till
 References
 **********
 
-.. target-notes::
-
 .. _AN2606:
    https://www.st.com/resource/en/application_note/cd00167594.pdf
 

boards/Kconfig

@@ -129,7 +129,7 @@ config QEMU_EXTRA_FLAGS
 	  GDBstub over serial with `-serial tcp:127.0.0.1:5678,server`
 
 # There might not be any board options, hence the optional source
-osource "$(KCONFIG_BOARD_DIR)/Kconfig"
+osource "$(BOARD_DIR)/Kconfig"
 endmenu
 
 config BOARD_HAS_TIMING_FUNCTIONS

boards/Kconfig.v1

@@ -2,13 +2,9 @@
 
 # SPDX-License-Identifier: Apache-2.0
 
-# In HWMv1 the KCONFIG_BOARD_DIR points directly to the BOARD_DIR.
-# Set the BOARD_DIR variable for backwards compatibility to legacy hardware model.
-BOARD_DIR := $(KCONFIG_BOARD_DIR)
-
 choice
 	prompt "Board Selection"
 
-source "$(KCONFIG_BOARD_DIR)/Kconfig.board"
+source "$(BOARD_DIR)/Kconfig.board"
 
 endchoice

boards/Kconfig.v2

@@ -25,4 +25,4 @@ config BOARD_QUALIFIERS
 	  For example, if building for ``nrf5340dk/nrf5340/cpuapp`` then this will contain the
 	  value ``nrf5340/cpuapp``.
 
-osource "$(KCONFIG_BOARD_DIR)/Kconfig.$(BOARD)"
+osource "$(BOARD_DIR)/Kconfig.$(BOARD)"

boards/aconno/acn52832/board.yml

@@ -1,6 +1,5 @@
 board:
   name: acn52832
-  full_name: acn52832
   vendor: aconno
   socs:
   - name: nrf52832

boards/aconno/acn52832/doc/index.rst

@@ -1,4 +1,7 @@
-.. zephyr:board:: acn52832
+.. _acn52832:
+
+acn52832
+########
 
 Overview
 ********

boards/acrn/acrn/board.yml

@@ -1,11 +1,9 @@
 boards:
 
   - name: acrn
-    full_name: ACRN hypervisor
     socs:
       - name: atom
 
   - name: acrn_ehl_crb
-    full_name: ACRN on EHL hypervisor
     socs:
       - name: elkhart_lake

boards/actinius/icarus/board.yml

@@ -1,6 +1,5 @@
 board:
   name: actinius_icarus
-  full_name: Icarus
   vendor: actinius
   socs:
   - name: nrf9160

boards/actinius/icarus/doc/index.rst

@@ -1,8 +1,17 @@
-.. zephyr:board:: actinius_icarus
+.. _actinius_icarus:
+
+Actinius Icarus
+###############
 
 Overview
 ********
 
+.. figure:: img/Icarus_front.jpg
+     :align: center
+     :alt: Icarus IoT Dev Board
+
+     Icarus IoT Dev Board (nRF9160 Feather)
+
 The Icarus is a cost-effective cellular IoT board in Adafruit's Feather/FeatherWing
 form factor. It is built around Nordic Semi's nRF9160 modem and combines
 LTE-M, NB-IoT, GPS, accelerometer, USB, LiPo charger as well as

boards/actinius/icarus_bee/board.yml

@@ -1,6 +1,5 @@
 board:
   name: actinius_icarus_bee
-  full_name: Icarus Bee
   vendor: actinius
   socs:
   - name: nrf9160

boards/actinius/icarus_bee/doc/index.rst

@@ -1,8 +1,17 @@
-.. zephyr:board:: actinius_icarus_bee
+.. _actinius_icarus_bee:
+
+Actinius Icarus Bee
+###################
 
 Overview
 ********
 
+.. figure:: img/icarus-bee.jpg
+     :align: center
+     :alt: Icarus Bee
+
+     Icarus Bee (nRF9160 Bee)
+
 The Icarus Bee is a cellular IoT board in Bee/xBee form factor.
 It is built around Nordic Semi's nRF9160 modem and combines
 LTE-M, NB-IoT, GPS, accelerometer, SPI Flash, RGB LED, Button,

boards/actinius/icarus_som/board.yml

@@ -1,6 +1,5 @@
 board:
   name: actinius_icarus_som
-  full_name: Icarus SoM
   vendor: actinius
   socs:
   - name: nrf9160

boards/actinius/icarus_som/doc/index.rst

@@ -1,8 +1,17 @@
-.. zephyr:board:: actinius_icarus_som
+.. _actinius_icarus_som:
+
+Actinius Icarus SoM
+###################
 
 Overview
 ********
 
+.. figure:: img/icarus-som.jpg
+     :align: center
+     :alt: Icarus SoM
+
+     Icarus SoM (nRF9160)
+
 The Icarus SoM is a coin-sized, easy-to-solder cellular IoT Module
 built around Nordic Semi's nRF9160 modem and combines
 LTE-M, NB-IoT, GPS, accelerometer as well as an eSIM and option for

boards/actinius/icarus_som_dk/board.yml

@@ -1,6 +1,5 @@
 board:
   name: actinius_icarus_som_dk
-  full_name: Icarus SoM DK
   vendor: actinius
   socs:
   - name: nrf9160

boards/actinius/icarus_som_dk/doc/index.rst

@@ -1,8 +1,18 @@
-.. zephyr:board:: actinius_icarus_som_dk
+.. _actinius_icarus_som_dk:
+
+Actinius Icarus SoM DK
+######################
 
 Overview
 ********
 
+.. figure:: img/icarus-som-dk.jpg
+     :width: 450px
+     :align: center
+     :alt: Icarus SoM DK
+
+     Icarus SoM Development Kit (nRF9160)
+
 The Icarus SoM DK is a single board development kit for
 evaluation and development on the Icarus SoM (`Icarus SoM Docs`_).
 The Icarus SoM features the nRF9160 SiP from Nordic Semiconductor,
@@ -32,7 +42,7 @@ following devices (provided directly by Nordic):
 * :abbr:`WDT (Watchdog Timer)`
 * :abbr:`IDAU (Implementation Defined Attribution Unit)`
 
-.. figure:: img/icarus_som_dk_block_diagram.jpg
+.. figure:: img/icarus-som-dk-block-diagram.jpg
      :width: 450px
      :align: center
      :alt: Icarus SoM DK Block Diagram

boards/adafruit/feather_m0_basic_proto/board.yml

@@ -1,6 +1,5 @@
 board:
   name: adafruit_feather_m0_basic_proto
-  full_name: Feather M0 Basic Proto
   vendor: adafruit
   socs:
     - name: samd21g18a

boards/adafruit/feather_m0_basic_proto/doc/index.rst

@@ -1,4 +1,7 @@
-.. zephyr:board:: adafruit_feather_m0_basic_proto
+.. _adafruit_feather_m0_basic_proto:
+
+Adafruit Feather M0 Basic Proto
+###############################
 
 Overview
 ********
@@ -8,6 +11,10 @@ board with an onboard battery connector and charger for 3.7 V lithium
 polymer batteries, charging status indicator and user LEDs, native USB
 connector, 20 I/O pins, and a small prototyping area.
 
+.. image:: img/adafruit_feather_m0_basic_proto.jpg
+     :align: center
+     :alt: Adafruit Feather M0 Basic Proto
+
 Hardware
 ********
 

boards/adafruit/feather_m0_lora/board.yml

@@ -1,6 +1,5 @@
 board:
   name: adafruit_feather_m0_lora
-  full_name: Feather M0 LoRa
   vendor: adafruit
   socs:
     - name: samd21g18a

boards/adafruit/feather_m0_lora/doc/index.rst

@@ -1,4 +1,7 @@
-.. zephyr:board:: adafruit_feather_m0_lora
+.. _adafruit_feather_m0_lora:
+
+Adafruit Feather M0 LoRa
+########################
 
 Overview
 ********
@@ -8,6 +11,10 @@ boards with an onboard battery connector and charger for 3.7 V lithium
 polymer batteries, charging status indicator and user LEDs, native USB
 connector, 20 I/O pins, and a LoRa radio module from Semtech.
 
+.. image:: img/adafruit_feather_m0_lora.jpg
+     :align: center
+     :alt: Adafruit Feather M0 LoRa
+
 Hardware
 ********
 

boards/adafruit/feather_nrf52840/board.yml

@@ -1,6 +1,5 @@
 board:
   name: adafruit_feather_nrf52840
-  full_name: Feather nRF52840 (Express, Sense)
   vendor: adafruit
   socs:
     - name: nrf52840

boards/adafruit/feather_nrf52840/doc/index.rst

@@ -1,4 +1,7 @@
-.. zephyr:board:: adafruit_feather_nrf52840
+.. _adafruit_feather_nrf52840:
+
+Adafruit Feather nRF52840 (Express, Sense)
+##########################################
 
 Overview
 ********

boards/adafruit/feather_stm32f405/board.yml

@@ -1,6 +1,5 @@
 board:
   name: adafruit_feather_stm32f405
-  full_name: Feather STM32F405 Express
   vendor: adafruit
   socs:
     - name: stm32f405xx

boards/adafruit/feather_stm32f405/doc/index.rst

@@ -1,4 +1,7 @@
-.. zephyr:board:: adafruit_feather_stm32f405
+.. _adafruit_feather_stm32f405:
+
+Adafruit Feather STM32F405 Express
+##################################
 
 Overview
 ********
@@ -9,6 +12,10 @@ devices labeled as Feathers or FeatherWings. The board is equipped
 with a lithium ion battery charger, native USB C connector, 2MB of
 external flash memory, and SD card socket.
 
+.. image:: img/adafruit_feather_stm32f405.jpg
+     :align: center
+     :alt: Adafruit Feather STM32F405 Express
+
 Hardware
 ********
 

boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.dts

@@ -72,7 +72,6 @@
 		mmc {
 			status = "okay";
 			compatible = "zephyr,sdmmc-disk";
-			disk-name = "SD";
 		};
 	};
 };

boards/adafruit/grand_central_m4_express/board.yml

@@ -1,6 +1,5 @@
 board:
   name: adafruit_grand_central_m4_express
-  full_name: Grand Central M4 Express
   vendor: adafruit
   socs:
     - name: samd51p20a

boards/adafruit/grand_central_m4_express/doc/index.rst

@@ -1,4 +1,7 @@
-.. zephyr:board:: adafruit_grand_central_m4_express
+.. _adafruit_grand_central_m4_express:
+
+Adafruit Grand Central M4 Express
+#################################
 
 Overview
 ********
@@ -7,6 +10,13 @@ The Adafruit Grand Central M4 Express is an ARM development board with the
 form factor of an Arduino Mega.
 It features 70 GPIO pins, a microSDHC slot and 8MiB of QSPI Flash.
 
+.. figure:: img/adafruit_grand_central_m4_express.webp
+   :width: 800px
+   :align: center
+   :alt: Adafruit Grand Central M4 Express
+
+   Adafruit Grand Central M4 Express (Credit: Kattni Rembor / Adafruit)
+
 Hardware
 ********
 

boards/adafruit/itsybitsy/board.yml

@@ -1,6 +1,5 @@
 board:
   name: adafruit_itsybitsy
-  full_name: ItsyBitsy nRF52840
   vendor: adafruit
   socs:
   - name: nrf52840

boards/adafruit/itsybitsy/doc/index.rst

@@ -1,4 +1,7 @@
-.. zephyr:board:: adafruit_itsybitsy
+.. _adafruit_itsybitsy_nrf52840:
+
+Adafruit ItsyBitsy nRF52840
+###########################
 
 Overview
 ********
@@ -26,6 +29,10 @@ This development kit has the following features:
 * :abbr:`USB (Universal Serial Bus)`
 * :abbr:`WDT (Watchdog Timer)`
 
+.. image:: img/adafruit_itsybitsy_nrf52840.jpeg
+     :align: center
+     :alt: Adafruit ItsyBitsy nRF52840 Express
+
 Hardware
 ********
 - nRF52840 ARM Cortex-M4F CPU at 64MHz