Added a check to ensure the requested timeout does not exceed the
hardware's maximum supported value. This prevents register overflow
and ensures watchdog reliability.
So, added a check in qcom_wdt_start() to ensure the requested timeout
does not exceed the hardware-supported maximum value. If the requested
value exceeds the maximum value, then the timeout is clamped
at maximum value.
The timeout is first converted to watchdog ticks and then compared
against QCOM_WDT_MAX_TIMEOUT. This helps prevent misconfiguration
and potential watchdog misbehavior due to overflow.
QCOM_WDT_MAX_TIMEOUT is set to 0xFFFFF, as Qualcomm SoCs typically
use 20 bits to store bark/bite timeout values.
This work builds upon the previous submission:
https://lore.kernel.org/u-boot/20250527124926.128413-1-balaji.selvanathan@oss.qualcomm.com/
Signed-off-by: Gopinath Sekar <gopinath.sekar@oss.qualcomm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Link: https://patch.msgid.link/20250625094607.1348494-1-gopinath.sekar@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
This patch is not as E Shattow authored it, but contains non-trivial
changes from Heinrich Schuchardt as well. The original author has
requested that this commit be reverted until the changes can be
committed showing which parts were authored by E Shattow and which by
Heinrich Schuchardt.
This reverts commit 4c105d2ae7.
Signed-off-by: Tom Rini <trini@konsulko.com>
Make crypt_compare() accessible from board-specific code
by removing its dependency on the autoboot feature.
Signed-off-by: Tomas Paukrt <tomaspaukrt@email.cz>
Reviewed-by: Tom Rini <trini@konsulko.com>
The "fixed-layout" nvmem controller subnode used to be optional wrapper
around nvmem controller cells subnodes. The "fixed-layout" node is now
mandatory in most cases, but in order to support both recent and legacy
DTs, both variants have to be supported.
Implement support for the "fixed-layout" node in the most trivial manner,
check whether the nvmem cell supernode is compatible with "fixed-layout"
and if it is, proceed one level above it to find the nvmem controller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Peripheral registers on MPC83xx-series chips are declared in
immap_83xx.h as a set of structs that ultimately fill the entire MMIO
space of 1 MiB. This patch introduces a compile-time check of the size
of each peripheral struct. The purpose of these checks is two-fold:
1. To quickly tell readers of the code the total size of each struct
2. To verify that the size does not change when a struct is edited
If the size of a peripheral struct were to change by a few bytes due
to an editing error, the result would be mayhem for all following
peripherals, because all offsets would shift by the amount of the error.
All new checks have been compile-tested.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
This platform is unfortunately frequently very close to the binary
size limit. Currently it is so close that generic bug fixes can trigger
build failure. Remove the license command from the image as that frees
up nearly 7KiB of space.
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
The AM571x SoC has 1 GB DDR space. As part of normal re-location process
U-Boot copies itself to the top of DDR bank. However, on HS devices, the
top 37 MB is used by PPA and is firewalled. This results in an exception
and the boot fails. Set CONFIG_SYS_MEM_TOP_HIDE to reserve the top 38 MB
memory (aligned to 2MB as per page size for ARM32) to fix the boot.
Note: This limitation does not exist for other AM57x devices, but this
config is applied in the common defconfig since adding a separate
defconfig only for AM571x is not justified. Losing 38MB of memory at the
bootloader stage on other devices is acceptable.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Add a requirements.txt file to the pylibfdt script directory to specify
setuptools as a dependency. This follows the pattern of each tool in
U-Boot having its own requirements.txt file. The version is set to
78.1.1 to avoid conflict with the same in tools/patman/requirements.txt.
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # sandbox
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add a paragraph explaining that in addition to the requirements.txt
for test/py/test.py itself, users may need to install additional python
packages depending on the U-Boot configuration being built.
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # sandbox
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Set ubconfig to None and add a check in the show_timings() function of
test/py/test.py to ensure that the global ubconfig variable was actually
initialized before access attributes.
If tests fail early, e.g. because --build failed, ubconfig may not have
been initialized yet and results in an exception in an atexit handler.
Adding this check avoids unnecessary noise in the output.
Exception ignored in atexit callback: <function cleanup at 0x7de475ea6b60>
Traceback (most recent call last):
File "u-boot/test/py/conftest.py", line 669, in cleanup
show_timings()
File "u-boot/test/py/conftest.py", line 616, in show_timings
if ubconfig.timing:
^^^^^^^^
NameError: name 'ubconfig' is not defined
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # sandbox
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner <dlechner@baylibre.com> says:
MT8365 has different pinctrl register layout compared to other SoCs in
the family, so needs its own driver.
This is also the first SoC in this family supported in U-Boot using an
upstream devicetree that has the mediatek,pctl-regmap property, so we
need to add support for that to the common mediatek pinctrl code first.
Link: https://lore.kernel.org/r/20260106-pinctl-mtk-mt8365-v1-0-0ca3eb382468@baylibre.com
Add support for the mediatek,pctl-regmap devicetree property to the
common MediaTek pinctrl driver.
In upstream devicetrees from Linux, the pinctrl nodes may be on the
interrupt controller register address space rather than the pinctrl
register address space. In this case, there is a syscon node linking to
the actual pinctrl registers. This uses a common property name of
mediatek,pctl-regmap for the phandle to the syscon node.
The logic here is that if this property is present, we look up the
syscon node and use it's address as the base address of the pinctrl
registers and ignore the pinctrl node's own reg property. (Support
for interrupts could be added later if needed.)
There is also at least one SoC in Linux that has two syscon phandles
in this property. This implementation support parsing this, but doesn't
do anything with the second syscon yet (the 2nd syscon is for interrupts
which we are saving for later).
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner <dlechner@baylibre.com> says:
There were a number of bugs in the clock definitions for the mt8365
clock drivers. This series aims to fix the obvious issues.
This builds on [1] that implements the clk dump command to inspect the
clock trees at runtime. Using that revealed quite a few mistakes in
the clock definitions.
Additionally, the topckgen-cg hack is removed for mt8365 since it would
require an extra devicetree node using the same address space as the
topckgen node. This would not be accepted upstream in Linux, so we
shouldn't do it in U-Boot either. mt85{12,16,18} also have this hack.
I didn't attempt to remove it from those platforms since I don't have
hardware to test on.
Patches have been runtime tested on mt8365_evk hardware and compile-
tested on other platforms using:
./tools/buildman/buildman --boards=mt7986a_bpir3_sd,mt7620_rfb,mt7986_rfb,mt7987_emmc_rfb,mt7987_rfb,mt7622_rfb,mt7987_sd_rfb,mt7623a_unielec_u7623_02,mt7988_rfb,mt7623n_bpir2,mt7988_sd_rfb,mt7628_rfb,mt8183_pumpkin,mt7629_rfb,mt8365_evk,mt7981_emmc_rfb,mt8512_bm1_emmc,mt7981_rfb,mt8516_pumpkin,mt7981_sd_rfb,mt8518_ap1_emmc -b HEAD -c 9
[1]: https://lore.kernel.org/u-boot/20251218-clk-mtk-improvements-v1-0-72db131ba148@baylibre.com/
Link: https://lore.kernel.org/r/20260107-clk-mtk-mt8365-fixes-v2-0-3294a5d2f239@baylibre.com
Use a ID map to add clocks for the missing CLK_TOP_CLK32K and
CLK_TOP_CLK26M that were not included in the devicetree definitions.
This fixes getting the rate of any clock that had one of these as a
parent.
CLK_TOP_UNIVPLL does not appear to be a real clock, so it is omitted
now since we can do that with the ID map as well.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Remove the separate topckgen-cg driver for handling clock gates in the
topckgen address space. The devicetree bindings for this were not
acceptable upstream because it was creating a separate clock controller
using the same address space as the main topckgen clock controller. The
gates are moved to the topckgen tree instead.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add handling for gates in the topckgen clk drivers. This avoids the need
to have separate topckgen-cg drivers and devicetree nodes for the same
address space and clock ID range.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Split the struct mtk_clk_tree for MT8365 into separate structures for
the apmixedsys, topckgen and infracfg clock controllers. This is needed
to support moving the topckgen gates into the struct mtk_clk_tree. Since
apmixedsys can also have gates, we need separate structures.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Fix a number of clock parent definitions for MT8365 clocks. Most of
these are just informational or don't make a function change.
The clocks with the new PLL_FACTOR2 macro and the change in apu_parents
are fixing actual bugs.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add a flags field to struct mtk_fixed_clk to allow properly resolving
the parent clock. All chip-specific clocks are updated to populate this
field correctly.
The parent is currently only used for printing debug information, so
there are no functional bugs being fixed.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add a gates_offs field to struct mtk_cg_priv and use that instead of
struct mtk_clk_tree.gates_offs.
Prior to this change, struct mtk_clk_tree.gates_offs could be the offset
of struct mtk_clk_tree.gates or struct mtk_cg_priv.gates depending on
the context. This was confusing and error-prone. For example, in mt8365
there is one set of gates that needs an offset and one that does not
that share the same struct mtk_clk_tree. This is fixed in this patch by
giving the correct offset for each gate separately.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Fix a few missing clocks and even more clocks in the incorrect order.
Since the clocks are looked up by index, having them out of order or
skipping an ID will lead to incorrect clocks being used.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Enable CONFIG_CMD_CLK in the mt8365_evk_defconfig to allow using the
clk dump command for debugging clock configurations.
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner <dlechner@baylibre.com> says:
I started looking into fixing some bugs in the mt8365 clock driver and
realized that there was no way to inspect or debug the clock trees.
I set out to implement the dump function to help with this. The driver
architecture didn't make this easy since there was no way to know the
number of elements in each of the clock arrays. The first few patches
in this series are adding fields to the data structures to hold this
information.
Once that was fixed, I was still getting crashes due to other bugs. To
work around this, I implemented the of_xlate function to validate clk
IDs as early as possible and return errors instead of crashing when
requested IDs are invalid. This also makes use of the new size fields
to prevent out of bounds array accesses. There are a couple of drivers
that remap IDs, so there are a few extra patches to handle that as well.
Then finally, I was able to implement the dump function to print out the
clock tree information without crashing. In the v1 cover letter, there
is an example of the output (it is quite long and doesn't need to be
repeated here).
Link: https://lore.kernel.org/r/20260107-clk-mtk-improvements-v2-0-7d4338e520a1@baylibre.com
Implement dump callbacks for Mediatek clocks. On these platforms, there
are 100s of clocks, so it can be easy to miss mistakes. The dump
callbacks will be useful for debugging and verifying clock configs.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add range initializers to the id_offs_map arrays in the mt7623 clk
driver to set unmapped IDs to -1. This prevents accidental usage of
unmapped IDs that would otherwise map to 0.
mtk_common_clk_of_xlate() checks these values for < 0 and returns
-ENOENT in that case.
A range initializer covering the entire array is used since it is less
error-prone than manually looking up the value of each macro in the
existing initializers and checking for gaps. It is placed first so that
the specific initializers override it.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Update documentation comments to clarify the difference between which
.id fields are mapped (only struct clk.id) vs. unmapped (all struct
mtk_*.id and .parent fields). The unmapped IDs are the ones defined
in the devicetree bindings, while the mapped IDs are the ones used as
the index into the various clk arrays.
Also fix spelling of "parent" while we are touching this.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add driver-specific of_xlate ops for MediaTek clocks. This provides
better checking of the args passed from the devicetree. Compared to
the default of_xlate implementation, this will return -EINVAL if there
are zero args (id is always required) and -ENOENT if the id is out of
range for the clock type. This will protect against out of bounds array
accesses later on when the clk->id is used to index into the clock
data arrays.
If there is a id_offs_map, then we have to do that translation first
before checking the id to see if it is in range. There is no sense in
doing the mapping multiple times, so we save the mapped ID in clk->id
and remove mtk_clk_get_id().
mtk_clk_find_parent_rate() also had to be updated since it creates a
temporary struct clk to represent the parent clock. It now has do the
translation in case the parent clock also uses an id_offs_map.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Move all infrasys ops and related functions next to each other in the
file for better organization.
Generally all ops functions are grouped together like this for the other
ops types (apmixedsys, topckgen, etc). However the infrasys functions
were mixed in with the other sections making them harder to find. This
will also give a logical place to add any future infrasys-specific
functions.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add id_offs_map_size field to struct mtk_clk_tree and populate it for
all existing drivers.
Currently, there is no bounds checking when accessing the id_offs_map
array. Adding this field will allow for bounds checking in the future.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add num_gates field to struct mtk_cg_priv and populate it for all
existing drivers.
Currently, there is no bounds checking when accessing the gates array.
Adding this field will allow for bounds checking in the future.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add num_plls, num_fclks, num_fdivs, num_muxes, and num_gates fields to
the mtk_clk_tree struct and populate them in the clk trees for all
existing drivers.
Currently, there is no bounds checking when accessing the arrays in
the clk tree structs. Adding these fields will allow for bounds checking
in the future.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Lanes can use other lanes' reference clocks, as determined by refclk.
Use refclk to determine the clock to enable/disable instead of always
using the lane's own reference clock. This ensures the clock selected in
xpsgtr_configure_pll is the one enabled.
For the other half of the equation, always program REF_CLK_SEL even when
we are selecting the lane's own clock. This ensures that Linux's idea of
the reference clock matches the hardware. We use the "local" clock mux
for this instead of going through the ref clock network.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Link: https://lore.kernel.org/r/20240628205540.3098010-2-sean.anderson@linux.dev
Signed-off-by: Vinod Koul <vkoul@kernel.org>
[ Linux commit 687d6bccb28238fcfa65f7c1badfdfeac498c428 ]
Fixes: 1d78d68349 ("phy: zynqmp: Add serdes/psgtr driver")
Link: https://lore.kernel.org/r/20260106215501.727524-3-sean.anderson@linux.dev
Signed-off-by: Michal Simek <michal.simek@amd.com>
