With commit 0535e46d55 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our
device tree is not 8-byte aligned. In commit 85f586035d ("ARM: OMAP2+:
Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains
that we must have ALIGN(x) statements inside of a section to ensure that
padding is included and not simply that the linker address counter is
incremented. To that end, this patch:
- Rewrite the '.rel.dyn' (u-boot.lds) to follow modern practices, and
include the 8-byte alignment at the end of the section.
- Expands the '.dynamic' section (u-boot-64.lds) to be more readable
when adding a second statement to the section.
- Aligns the final section before _end (for U-Boot) or _image_binary_end
or __bss_end (for xPL phases) by 8-bytes by adding '. = ALIGN(8);' to
the final section before the symbol or changing an existing ALIGN(4)
statement.
- Ensure that we do have alignment by adding an ASSERT so that when not
aligned we fail to link (and explain why).
Signed-off-by: Tom Rini <trini@konsulko.com>
With commit 0535e46d55 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our
device tree is not 8-byte aligned. In commit 85f586035d ("ARM: OMAP2+:
Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains
that we must have ALIGN(x) statements inside of a section to ensure that
padding is included and not simply that the linker address counter is
incremented. To that end, this patch:
- Aligns the final section before _image_binary_end (for xPL phases) by
8-bytes by adding '. = ALIGN(8);' to the final section before the
symbol.
- Ensure that we do have alignment by adding an ASSERT so that when not
aligned we fail to link (and explain why).
Signed-off-by: Tom Rini <trini@konsulko.com>
With commit 0535e46d55 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our
device tree is not 8-byte aligned. In commit 85f586035d ("ARM: OMAP2+:
Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains
that we must have ALIGN(x) statements inside of a section to ensure that
padding is included and not simply that the linker address counter is
incremented. To that end, this patch:
- Aligns the final section before _end (for U-Boot) or _image_binary_end
(for xPL phases) by 8-bytes by adding '. = ALIGN(8);' to the final
section before the symbol.
- Remove a now-spurious '. = ALIGN(x);' statement that was intended to
provide the above alignments.
- Ensure that we do have alignment by adding an ASSERT so that when not
aligned we fail to link (and explain why).
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
With commit 0535e46d55 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our
device tree is not 8-byte aligned. In commit 85f586035d ("ARM: OMAP2+:
Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains
that we must have ALIGN(x) statements inside of a section to ensure that
padding is included and not simply that the linker address counter is
incremented. To that end, this patch:
- Aligns the final section before _end by 8-bytes by adding '. =
ALIGN(8);' or changing an existing ALIGN(4) statement.
- Ensure that we do have alignment by adding an ASSERT so that when not
aligned we fail to link (and explain why).
Signed-off-by: Tom Rini <trini@konsulko.com>
With commit 0535e46d55 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our
device tree is not 8-byte aligned. In commit 85f586035d ("ARM: OMAP2+:
Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains
that we must have ALIGN(x) statements inside of a section to ensure that
padding is included and not simply that the linker address counter is
incremented. To that end, this patch:
- Aligns the final section before _end 8-bytes by adding '. = ALIGN(8);'
to the final section before the symbol.
- Remove a now-spurious '. = ALIGN(x);' statement that was intended to
provide the above alignments.
- Ensure that we do have alignment by adding an ASSERT so that when not
aligned we fail to link (and explain why).
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
With commit 0535e46d55 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our
device tree is not 8-byte aligned. In commit 85f586035d ("ARM: OMAP2+:
Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains
that we must have ALIGN(x) statements inside of a section to ensure that
padding is included and not simply that the linker address counter is
incremented. To that end, this patch:
- Aligns the final section before _end (for U-Boot) or _image_binary_end
(for xPL phases) by 8-bytes by adding '. = ALIGN(8);' to the final
section before the symbol. For SPL we need this in two places to cover
all build configurations.
- Remove now-spurious '. = ALIGN(x);' statements that were intended to
provide the above alignments.
- Ensure that we do have alignment by adding an ASSERT so that when not
aligned we fail to link (and explain why).
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
With commit 0535e46d55 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our
device tree is not 8-byte aligned. In commit 85f586035d ("ARM: OMAP2+:
Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains
that we must have ALIGN(x) statements inside of a section to ensure that
padding is included and not simply that the linker address counter is
incremented. To that end, this patch:
- Aligns the final section before _end (for U-Boot) or _image_binary_end
(for xPL phases) by 8-bytes by adjusting the ALIGN(4) statement to be
ALIGN(8) in the final section before the symbol.
- Ensure that we do have alignment by adding an ASSERT so that when not
aligned we fail to link (and explain why).
Tested-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
With commit 0535e46d55 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our
device tree is not 8-byte aligned. In commit 85f586035d ("ARM: OMAP2+:
Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains
that we must have ALIGN(x) statements inside of a section to ensure that
padding is included and not simply that the linker address counter is
incremented. To that end, this patch:
- Remove part of what Marek Vasut did in commit 9ed99e2eea ("m68k:
Assure end of U-Boot is at 8-byte aligned offset") as we now better
understand what can trigger failure and check for it.
- Rewrite the '.dynsym' section to follow modern practices, and include
the 8-byte alignment at the end of the section.
- Ensure that we do have alignment by adding an ASSERT so that when not
aligned we fail to link (and explain why).
Signed-off-by: Tom Rini <trini@konsulko.com>
With commit 0535e46d55 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our
device tree is not 8-byte aligned. In commit 85f586035d ("ARM: OMAP2+:
Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains
that we must have ALIGN(x) statements inside of a section to ensure that
padding is included and not simply that the linker address counter is
incremented. To that end, this patch:
- Expands some linker sections to be more readable when adding a second
statement to the section.
- Aligns the final section before _end (for U-Boot) or
_image_binary_end or __bss_end (for xPL phases) by 8-bytes by adding
'. = ALIGN(8);' to the final section before the symbol.
- Ensure that we do have alignment by adding an ASSERT so that when not
aligned we fail to link (and explain why).
- Remove now-spurious '. = ALIGN(x);' statements that were intended to
provide the above alignments.
Tested-by: Michal Simek <michal.simek@amd.com> # Zynq
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
[trini: Also update arch/arm/cpu/armv8/u-boot.lds as Ilas requested]
Signed-off-by: Tom Rini <trini@konsulko.com>
If we have ASSERT macros that validate the position of
_image_binary_end, our awk expression will report a string that causes
the rest of our check to fail with garbage values. Have it exit after
the first match to fix this.
Signed-off-by: Tom Rini <trini@konsulko.com>
The micrel KSZ9031 phy has a optional clock pin (CLK125_NDO) which can be
used as reference clock for the MAC unit. The clock signal must meet the
RGMII requirements to ensure the correct data transmission between the
MAC and the PHY. The KSZ9031 phy does not fulfill the duty cycle
requirement if the phy is configured as slave. For a complete
describtion look at the errata sheets: DS80000691D or DS80000692D.
The errata sheet recommends to force the phy into master mode whenever
there is a 1000Base-T link-up as work around. Only set the
"micrel,force-master" property if you use the phy reference clock provided
by CLK125_NDO pin as MAC reference clock in your application.
Attention: this workaround is only usable if the link partner can
be configured to slave mode for 1000Base-T.
This follows linux implementation in commit
e1b505a60366 ("net: phy: micrel: add 125MHz reference clock workaround")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
Disable the support due to chip errata and call genphy_config_aneg
instead of genphy_config. For a complete describtion look at the
KSZ9031 errata sheets: DS80000691D or DS80000692D.
Micrel KSZ9021 has no errata, but has the same issue with Asymmetric Pause.
This patch apply the same workaround as the one for KSZ9031.
This follows linux implementation in commits
3aed3e2a143c ("net: phy: micrel: add Asym Pause workaround")
407d8098cb1a ("net: phy: micrel: add Asym Pause workaround for KSZ9021")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
Replace PHY interface mode bitmap handling with comparison test to match
U-Boot PHY subsystem behavior. U-Boot currently implements only single PHY
interface mode for each PHY. Linux currently uses bitmap of PHY interface
modes for each PHY.
The reason why in Linux uses bitmap of supported interface modes is so
that Linux can select the best serdes mode switching behavior for the PHY.
For example if the host only supports 10gbase-r serdes mode, then the PHY
must always talk to the host in 10gbase-r mode, even if the RJ-45 copper
speed was autonegotiated to lower speed (i.e. 1Gbps).
If the host supports both 10gbase-r and sgmii serdes modes, we want the
PHY to switch to sgmii if the RJ-45 speed is 1000/100/10, and to switch
to 10gbase-r if the RJ-45 speed is 10000.
U-Boot does not implement this functionality yet, therefore remove modes
which cannot be currently supported and switch mv_test_bit() to plain
mode comparison.
Fixes: b6fcab0728 ("net: phy: marvell10g: Adapt Marvell 10G PHY driver from Linux")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The usage of the net sub-system was missing the complete command for “net
stats”.
Signed-off-by: Link Mauve <linkmauve@linkmauve.fr>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Add Microsemi/Microchip MDIO driver for interfaces found in their network
switches.
Driver is based on the Linux version.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Jerome Forissier <jerome@forissier.org>
Given how the support for CONFIG_CMD_TFTPPUT is woven through the
support for the tftp protocol we currently end up including "put"
support in xPL phases, if enabled. This in turn can lead to size
overflow on those platforms as xPL tends to be constrained. To resolve
this, use "CMD_TFTPPUT" in the code to check for both CONFIG_CMD_TFTPPUT
being true and not being in an xPL build phase.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
After the preparatory patches moved most of the NFS code into common
files we now add the code to enable NFS support with lwIP.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Make some variables available to be used by either the legacy network
code or lwIP by moving them into the net-common files. This also allowed
removing a small number of duplicated variables from the lwIP code.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Move the net_state variable into common code so that it can be used by
either the legacy network code or lwIP. This is needed for porting
across the NFS support code for use with lwIP.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
When debugging the LWIP NFS implementation this debug line helped to
show the cause of an error. This could be useful to someone in the
future.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
This patch is not as E Shattow authored it, but contains non-trivial
changes from Heinrich Schuchardt as well. The original author has
requested that this commit be reverted until the changes can be
committed showing which parts were authored by E Shattow and which by
Heinrich Schuchardt.
This reverts commit 4c105d2ae7.
Signed-off-by: Tom Rini <trini@konsulko.com>
Make crypt_compare() accessible from board-specific code
by removing its dependency on the autoboot feature.
Signed-off-by: Tomas Paukrt <tomaspaukrt@email.cz>
Reviewed-by: Tom Rini <trini@konsulko.com>
The "fixed-layout" nvmem controller subnode used to be optional wrapper
around nvmem controller cells subnodes. The "fixed-layout" node is now
mandatory in most cases, but in order to support both recent and legacy
DTs, both variants have to be supported.
Implement support for the "fixed-layout" node in the most trivial manner,
check whether the nvmem cell supernode is compatible with "fixed-layout"
and if it is, proceed one level above it to find the nvmem controller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Peripheral registers on MPC83xx-series chips are declared in
immap_83xx.h as a set of structs that ultimately fill the entire MMIO
space of 1 MiB. This patch introduces a compile-time check of the size
of each peripheral struct. The purpose of these checks is two-fold:
1. To quickly tell readers of the code the total size of each struct
2. To verify that the size does not change when a struct is edited
If the size of a peripheral struct were to change by a few bytes due
to an editing error, the result would be mayhem for all following
peripherals, because all offsets would shift by the amount of the error.
All new checks have been compile-tested.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
This platform is unfortunately frequently very close to the binary
size limit. Currently it is so close that generic bug fixes can trigger
build failure. Remove the license command from the image as that frees
up nearly 7KiB of space.
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
The AM571x SoC has 1 GB DDR space. As part of normal re-location process
U-Boot copies itself to the top of DDR bank. However, on HS devices, the
top 37 MB is used by PPA and is firewalled. This results in an exception
and the boot fails. Set CONFIG_SYS_MEM_TOP_HIDE to reserve the top 38 MB
memory (aligned to 2MB as per page size for ARM32) to fix the boot.
Note: This limitation does not exist for other AM57x devices, but this
config is applied in the common defconfig since adding a separate
defconfig only for AM571x is not justified. Losing 38MB of memory at the
bootloader stage on other devices is acceptable.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Add a requirements.txt file to the pylibfdt script directory to specify
setuptools as a dependency. This follows the pattern of each tool in
U-Boot having its own requirements.txt file. The version is set to
78.1.1 to avoid conflict with the same in tools/patman/requirements.txt.
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # sandbox
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add a paragraph explaining that in addition to the requirements.txt
for test/py/test.py itself, users may need to install additional python
packages depending on the U-Boot configuration being built.
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # sandbox
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Set ubconfig to None and add a check in the show_timings() function of
test/py/test.py to ensure that the global ubconfig variable was actually
initialized before access attributes.
If tests fail early, e.g. because --build failed, ubconfig may not have
been initialized yet and results in an exception in an atexit handler.
Adding this check avoids unnecessary noise in the output.
Exception ignored in atexit callback: <function cleanup at 0x7de475ea6b60>
Traceback (most recent call last):
File "u-boot/test/py/conftest.py", line 669, in cleanup
show_timings()
File "u-boot/test/py/conftest.py", line 616, in show_timings
if ubconfig.timing:
^^^^^^^^
NameError: name 'ubconfig' is not defined
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # sandbox
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner <dlechner@baylibre.com> says:
MT8365 has different pinctrl register layout compared to other SoCs in
the family, so needs its own driver.
This is also the first SoC in this family supported in U-Boot using an
upstream devicetree that has the mediatek,pctl-regmap property, so we
need to add support for that to the common mediatek pinctrl code first.
Link: https://lore.kernel.org/r/20260106-pinctl-mtk-mt8365-v1-0-0ca3eb382468@baylibre.com
Add support for the mediatek,pctl-regmap devicetree property to the
common MediaTek pinctrl driver.
In upstream devicetrees from Linux, the pinctrl nodes may be on the
interrupt controller register address space rather than the pinctrl
register address space. In this case, there is a syscon node linking to
the actual pinctrl registers. This uses a common property name of
mediatek,pctl-regmap for the phandle to the syscon node.
The logic here is that if this property is present, we look up the
syscon node and use it's address as the base address of the pinctrl
registers and ignore the pinctrl node's own reg property. (Support
for interrupts could be added later if needed.)
There is also at least one SoC in Linux that has two syscon phandles
in this property. This implementation support parsing this, but doesn't
do anything with the second syscon yet (the 2nd syscon is for interrupts
which we are saving for later).
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner <dlechner@baylibre.com> says:
There were a number of bugs in the clock definitions for the mt8365
clock drivers. This series aims to fix the obvious issues.
This builds on [1] that implements the clk dump command to inspect the
clock trees at runtime. Using that revealed quite a few mistakes in
the clock definitions.
Additionally, the topckgen-cg hack is removed for mt8365 since it would
require an extra devicetree node using the same address space as the
topckgen node. This would not be accepted upstream in Linux, so we
shouldn't do it in U-Boot either. mt85{12,16,18} also have this hack.
I didn't attempt to remove it from those platforms since I don't have
hardware to test on.
Patches have been runtime tested on mt8365_evk hardware and compile-
tested on other platforms using:
./tools/buildman/buildman --boards=mt7986a_bpir3_sd,mt7620_rfb,mt7986_rfb,mt7987_emmc_rfb,mt7987_rfb,mt7622_rfb,mt7987_sd_rfb,mt7623a_unielec_u7623_02,mt7988_rfb,mt7623n_bpir2,mt7988_sd_rfb,mt7628_rfb,mt8183_pumpkin,mt7629_rfb,mt8365_evk,mt7981_emmc_rfb,mt8512_bm1_emmc,mt7981_rfb,mt8516_pumpkin,mt7981_sd_rfb,mt8518_ap1_emmc -b HEAD -c 9
[1]: https://lore.kernel.org/u-boot/20251218-clk-mtk-improvements-v1-0-72db131ba148@baylibre.com/
Link: https://lore.kernel.org/r/20260107-clk-mtk-mt8365-fixes-v2-0-3294a5d2f239@baylibre.com
Use a ID map to add clocks for the missing CLK_TOP_CLK32K and
CLK_TOP_CLK26M that were not included in the devicetree definitions.
This fixes getting the rate of any clock that had one of these as a
parent.
CLK_TOP_UNIVPLL does not appear to be a real clock, so it is omitted
now since we can do that with the ID map as well.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Remove the separate topckgen-cg driver for handling clock gates in the
topckgen address space. The devicetree bindings for this were not
acceptable upstream because it was creating a separate clock controller
using the same address space as the main topckgen clock controller. The
gates are moved to the topckgen tree instead.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add handling for gates in the topckgen clk drivers. This avoids the need
to have separate topckgen-cg drivers and devicetree nodes for the same
address space and clock ID range.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Split the struct mtk_clk_tree for MT8365 into separate structures for
the apmixedsys, topckgen and infracfg clock controllers. This is needed
to support moving the topckgen gates into the struct mtk_clk_tree. Since
apmixedsys can also have gates, we need separate structures.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Fix a number of clock parent definitions for MT8365 clocks. Most of
these are just informational or don't make a function change.
The clocks with the new PLL_FACTOR2 macro and the change in apu_parents
are fixing actual bugs.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add a flags field to struct mtk_fixed_clk to allow properly resolving
the parent clock. All chip-specific clocks are updated to populate this
field correctly.
The parent is currently only used for printing debug information, so
there are no functional bugs being fixed.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add a gates_offs field to struct mtk_cg_priv and use that instead of
struct mtk_clk_tree.gates_offs.
Prior to this change, struct mtk_clk_tree.gates_offs could be the offset
of struct mtk_clk_tree.gates or struct mtk_cg_priv.gates depending on
the context. This was confusing and error-prone. For example, in mt8365
there is one set of gates that needs an offset and one that does not
that share the same struct mtk_clk_tree. This is fixed in this patch by
giving the correct offset for each gate separately.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Fix a few missing clocks and even more clocks in the incorrect order.
Since the clocks are looked up by index, having them out of order or
skipping an ID will lead to incorrect clocks being used.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Enable CONFIG_CMD_CLK in the mt8365_evk_defconfig to allow using the
clk dump command for debugging clock configurations.
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner <dlechner@baylibre.com> says:
I started looking into fixing some bugs in the mt8365 clock driver and
realized that there was no way to inspect or debug the clock trees.
I set out to implement the dump function to help with this. The driver
architecture didn't make this easy since there was no way to know the
number of elements in each of the clock arrays. The first few patches
in this series are adding fields to the data structures to hold this
information.
Once that was fixed, I was still getting crashes due to other bugs. To
work around this, I implemented the of_xlate function to validate clk
IDs as early as possible and return errors instead of crashing when
requested IDs are invalid. This also makes use of the new size fields
to prevent out of bounds array accesses. There are a couple of drivers
that remap IDs, so there are a few extra patches to handle that as well.
Then finally, I was able to implement the dump function to print out the
clock tree information without crashing. In the v1 cover letter, there
is an example of the output (it is quite long and doesn't need to be
repeated here).
Link: https://lore.kernel.org/r/20260107-clk-mtk-improvements-v2-0-7d4338e520a1@baylibre.com
